sys/dev/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *
  26  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_display.c 254885 2013-08-25 19:37:15Z dumbbell $
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <uapi_drm/radeon_drm.h>
  31 #include "radeon.h"
  32
  33 #include "atom.h"
  34
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include <linux/err.h>
  38
  39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  40 {
  41         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  42         struct drm_device *dev = crtc->dev;
  43         struct radeon_device *rdev = dev->dev_private;
  44         int i;
  45
  46         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  47         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  48
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  52
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  56
  57         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  58         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  59         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  60
  61         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  62         for (i = 0; i < 256; i++) {
  63                 WREG32(AVIVO_DC_LUT_30_COLOR,
  64                              (radeon_crtc->lut_r[i] << 20) |
  65                              (radeon_crtc->lut_g[i] << 10) |
  66                              (radeon_crtc->lut_b[i] << 0));
  67         }
  68
  69         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  70 }
  71
  72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  73 {
  74         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  75         struct drm_device *dev = crtc->dev;
  76         struct radeon_device *rdev = dev->dev_private;
  77         int i;
  78
  79         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  80         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  81
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  85
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  91         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  92
  93         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  94         for (i = 0; i < 256; i++) {
  95                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  96                        (radeon_crtc->lut_r[i] << 20) |
  97                        (radeon_crtc->lut_g[i] << 10) |
  98                        (radeon_crtc->lut_b[i] << 0));
  99         }
 100 }
 101
 102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 103 {
 104         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 105         struct drm_device *dev = crtc->dev;
 106         struct radeon_device *rdev = dev->dev_private;
 107         int i;
 108
 109         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 110
 111         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 112                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 113                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 114         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 115                NI_GRPH_PRESCALE_BYPASS);
 116         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 117                NI_OVL_PRESCALE_BYPASS);
 118         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 119                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 120                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 121
 122         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 123
 124         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 125         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 127
 128         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 129         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 133         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 134
 135         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 136         for (i = 0; i < 256; i++) {
 137                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 138                        (radeon_crtc->lut_r[i] << 20) |
 139                        (radeon_crtc->lut_g[i] << 10) |
 140                        (radeon_crtc->lut_b[i] << 0));
 141         }
 142
 143         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 144                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 145                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 146                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 148         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 150                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 151         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 153                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 154         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 155                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 156                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 157         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 158         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 159
 160 }
 161
 162 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 163 {
 164         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 165         struct drm_device *dev = crtc->dev;
 166         struct radeon_device *rdev = dev->dev_private;
 167         int i;
 168         uint32_t dac2_cntl;
 169
 170         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 171         if (radeon_crtc->crtc_id == 0)
 172                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 173         else
 174                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 175         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 176
 177         WREG8(RADEON_PALETTE_INDEX, 0);
 178         for (i = 0; i < 256; i++) {
 179                 WREG32(RADEON_PALETTE_30_DATA,
 180                              (radeon_crtc->lut_r[i] << 20) |
 181                              (radeon_crtc->lut_g[i] << 10) |
 182                              (radeon_crtc->lut_b[i] << 0));
 183         }
 184 }
 185
 186 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 187 {
 188         struct drm_device *dev = crtc->dev;
 189         struct radeon_device *rdev = dev->dev_private;
 190
 191         if (!crtc->enabled)
 192                 return;
 193
 194         if (ASIC_IS_DCE5(rdev))
 195                 dce5_crtc_load_lut(crtc);
 196         else if (ASIC_IS_DCE4(rdev))
 197                 dce4_crtc_load_lut(crtc);
 198         else if (ASIC_IS_AVIVO(rdev))
 199                 avivo_crtc_load_lut(crtc);
 200         else
 201                 legacy_crtc_load_lut(crtc);
 202 }
 203
 204 /** Sets the color ramps on behalf of fbcon */
 205 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 206                               u16 blue, int regno)
 207 {
 208         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 209
 210         radeon_crtc->lut_r[regno] = red >> 6;
 211         radeon_crtc->lut_g[regno] = green >> 6;
 212         radeon_crtc->lut_b[regno] = blue >> 6;
 213 }
 214
 215 /** Gets the color ramps on behalf of fbcon */
 216 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 217                               u16 *blue, int regno)
 218 {
 219         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 220
 221         *red = radeon_crtc->lut_r[regno] << 6;
 222         *green = radeon_crtc->lut_g[regno] << 6;
 223         *blue = radeon_crtc->lut_b[regno] << 6;
 224 }
 225
 226 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 227                                   u16 *blue, uint32_t start, uint32_t size)
 228 {
 229         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 230         int end = (start + size > 256) ? 256 : start + size, i;
 231
 232         /* userspace palettes are always correct as is */
 233         for (i = start; i < end; i++) {
 234                 radeon_crtc->lut_r[i] = red[i] >> 6;
 235                 radeon_crtc->lut_g[i] = green[i] >> 6;
 236                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 237         }
 238         radeon_crtc_load_lut(crtc);
 239 }
 240
 241 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 242 {
 243         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 244
 245         drm_crtc_cleanup(crtc);
 246         drm_free(radeon_crtc, M_DRM);
 247 }
 248
 249 /*
 250  * Handle unpin events outside the interrupt handler proper.
 251  */
 252 static void radeon_unpin_work_func(void *arg, int pending)
 253 {
 254         struct radeon_unpin_work *work = arg;
 255         int r;
 256
 257         /* unpin of the old buffer */
 258         r = radeon_bo_reserve(work->old_rbo, false);
 259         if (likely(r == 0)) {
 260                 r = radeon_bo_unpin(work->old_rbo);
 261                 if (unlikely(r != 0)) {
 262                         DRM_ERROR("failed to unpin buffer after flip\n");
 263                 }
 264                 radeon_bo_unreserve(work->old_rbo);
 265         } else
 266                 DRM_ERROR("failed to reserve buffer after flip\n");
 267
 268         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 269         drm_free(work, M_DRM);
 270 }
 271
 272 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 273 {
 274         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 275         struct radeon_unpin_work *work;
 276         struct drm_pending_vblank_event *e;
 277         struct timeval now;
 278         u32 update_pending;
 279         int vpos, hpos;
 280
 281         lockmgr(&rdev->ddev->event_lock, LK_EXCLUSIVE);
 282         work = radeon_crtc->unpin_work;
 283         if (work == NULL ||
 284             (work->fence && !radeon_fence_signaled(work->fence))) {
 285                 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 286                 return;
 287         }
 288         /* New pageflip, or just completion of a previous one? */
 289         if (!radeon_crtc->deferred_flip_completion) {
 290                 /* do the flip (mmio) */
 291                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 292         } else {
 293                 /* This is just a completion of a flip queued in crtc
 294                  * at last invocation. Make sure we go directly to
 295                  * completion routine.
 296                  */
 297                 update_pending = 0;
 298                 radeon_crtc->deferred_flip_completion = 0;
 299         }
 300
 301         /* Has the pageflip already completed in crtc, or is it certain
 302          * to complete in this vblank?
 303          */
 304         if (update_pending &&
 305             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 306                                                                &vpos, &hpos)) &&
 307             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 308              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 309                 /* crtc didn't flip in this target vblank interval,
 310                  * but flip is pending in crtc. Based on the current
 311                  * scanout position we know that the current frame is
 312                  * (nearly) complete and the flip will (likely)
 313                  * complete before the start of the next frame.
 314                  */
 315                 update_pending = 0;
 316         }
 317         if (update_pending) {
 318                 /* crtc didn't flip in this target vblank interval,
 319                  * but flip is pending in crtc. It will complete it
 320                  * in next vblank interval, so complete the flip at
 321                  * next vblank irq.
 322                  */
 323                 radeon_crtc->deferred_flip_completion = 1;
 324                 lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 325                 return;
 326         }
 327
 328         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 329         radeon_crtc->unpin_work = NULL;
 330
 331         /* wakeup userspace */
 332         if (work->event) {
 333                 e = work->event;
 334                 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
 335                 e->event.tv_sec = now.tv_sec;
 336                 e->event.tv_usec = now.tv_usec;
 337                 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
 338                 drm_event_wakeup(&e->base);
 339         }
 340         lockmgr(&rdev->ddev->event_lock, LK_RELEASE);
 341
 342         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 343         radeon_fence_unref(&work->fence);
 344         radeon_post_page_flip(work->rdev, work->crtc_id);
 345         taskqueue_enqueue(rdev->tq, &work->work);
 346 }
 347
 348 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 349                                  struct drm_framebuffer *fb,
 350                                  struct drm_pending_vblank_event *event)
 351 {
 352         struct drm_device *dev = crtc->dev;
 353         struct radeon_device *rdev = dev->dev_private;
 354         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 355         struct radeon_framebuffer *old_radeon_fb;
 356         struct radeon_framebuffer *new_radeon_fb;
 357         struct drm_gem_object *obj;
 358         struct radeon_bo *rbo;
 359         struct radeon_unpin_work *work;
 360         u32 tiling_flags, pitch_pixels;
 361         u64 base;
 362         int r;
 363
 364         work = kmalloc(sizeof *work, M_DRM, M_WAITOK | M_ZERO);
 365         if (work == NULL)
 366                 return -ENOMEM;
 367
 368         work->event = event;
 369         work->rdev = rdev;
 370         work->crtc_id = radeon_crtc->crtc_id;
 371         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 372         new_radeon_fb = to_radeon_framebuffer(fb);
 373         /* schedule unpin of the old buffer */
 374         obj = old_radeon_fb->obj;
 375         /* take a reference to the old object */
 376         drm_gem_object_reference(obj);
 377         rbo = gem_to_radeon_bo(obj);
 378         work->old_rbo = rbo;
 379         obj = new_radeon_fb->obj;
 380         rbo = gem_to_radeon_bo(obj);
 381
 382         lockmgr(&rbo->tbo.bdev->fence_lock, LK_EXCLUSIVE);
 383         if (rbo->tbo.sync_obj)
 384                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 385         lockmgr(&rbo->tbo.bdev->fence_lock, LK_RELEASE);
 386
 387         TASK_INIT(&work->work, 0, radeon_unpin_work_func, work);
 388
 389         /* We borrow the event spin lock for protecting unpin_work */
 390         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 391         if (radeon_crtc->unpin_work) {
 392                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 393                 r = -EBUSY;
 394                 goto unlock_free;
 395         }
 396         radeon_crtc->unpin_work = work;
 397         radeon_crtc->deferred_flip_completion = 0;
 398         lockmgr(&dev->event_lock, LK_RELEASE);
 399
 400         /* pin the new buffer */
 401         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 402                          work->old_rbo, rbo);
 403
 404         r = radeon_bo_reserve(rbo, false);
 405         if (unlikely(r != 0)) {
 406                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 407                 goto pflip_cleanup;
 408         }
 409         /* Only 27 bit offset for legacy CRTC */
 410         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 411                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 412         if (unlikely(r != 0)) {
 413                 radeon_bo_unreserve(rbo);
 414                 r = -EINVAL;
 415                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 416                 goto pflip_cleanup;
 417         }
 418         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 419         radeon_bo_unreserve(rbo);
 420
 421         if (!ASIC_IS_AVIVO(rdev)) {
 422                 /* crtc offset is from display base addr not FB location */
 423                 base -= radeon_crtc->legacy_display_base_addr;
 424                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 425
 426                 if (tiling_flags & RADEON_TILING_MACRO) {
 427                         if (ASIC_IS_R300(rdev)) {
 428                                 base &= ~0x7ff;
 429                         } else {
 430                                 int byteshift = fb->bits_per_pixel >> 4;
 431                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 432                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 433                         }
 434                 } else {
 435                         int offset = crtc->y * pitch_pixels + crtc->x;
 436                         switch (fb->bits_per_pixel) {
 437                         case 8:
 438                         default:
 439                                 offset *= 1;
 440                                 break;
 441                         case 15:
 442                         case 16:
 443                                 offset *= 2;
 444                                 break;
 445                         case 24:
 446                                 offset *= 3;
 447                                 break;
 448                         case 32:
 449                                 offset *= 4;
 450                                 break;
 451                         }
 452                         base += offset;
 453                 }
 454                 base &= ~7;
 455         }
 456
 457         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 458         work->new_crtc_base = base;
 459         lockmgr(&dev->event_lock, LK_RELEASE);
 460
 461         /* update crtc fb */
 462         crtc->fb = fb;
 463
 464         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 465         if (r) {
 466                 DRM_ERROR("failed to get vblank before flip\n");
 467                 goto pflip_cleanup1;
 468         }
 469
 470         /* set the proper interrupt */
 471         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 472
 473         return 0;
 474
 475 pflip_cleanup1:
 476         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 477                 DRM_ERROR("failed to reserve new rbo in error path\n");
 478                 goto pflip_cleanup;
 479         }
 480         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 481                 DRM_ERROR("failed to unpin new rbo in error path\n");
 482         }
 483         radeon_bo_unreserve(rbo);
 484
 485 pflip_cleanup:
 486         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 487         radeon_crtc->unpin_work = NULL;
 488 unlock_free:
 489         lockmgr(&dev->event_lock, LK_RELEASE);
 490         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 491         radeon_fence_unref(&work->fence);
 492         drm_free(work, M_DRM);
 493
 494         return r;
 495 }
 496
 497 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 498         .cursor_set = radeon_crtc_cursor_set,
 499         .cursor_move = radeon_crtc_cursor_move,
 500         .gamma_set = radeon_crtc_gamma_set,
 501         .set_config = drm_crtc_helper_set_config,
 502         .destroy = radeon_crtc_destroy,
 503         .page_flip = radeon_crtc_page_flip,
 504 };
 505
 506 static void radeon_crtc_init(struct drm_device *dev, int index)
 507 {
 508         struct radeon_device *rdev = dev->dev_private;
 509         struct radeon_crtc *radeon_crtc;
 510         int i;
 511
 512         radeon_crtc = kmalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)),
 513                               M_DRM, M_WAITOK | M_ZERO);
 514         if (radeon_crtc == NULL)
 515                 return;
 516
 517         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 518
 519         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 520         radeon_crtc->crtc_id = index;
 521         rdev->mode_info.crtcs[index] = radeon_crtc;
 522
 523 #if 0
 524         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 525         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 526         radeon_crtc->mode_set.num_connectors = 0;
 527 #endif
 528
 529         for (i = 0; i < 256; i++) {
 530                 radeon_crtc->lut_r[i] = i << 2;
 531                 radeon_crtc->lut_g[i] = i << 2;
 532                 radeon_crtc->lut_b[i] = i << 2;
 533         }
 534
 535         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 536                 radeon_atombios_init_crtc(dev, radeon_crtc);
 537         else
 538                 radeon_legacy_init_crtc(dev, radeon_crtc);
 539 }
 540
 541 static const char *encoder_names[37] = {
 542         "NONE",
 543         "INTERNAL_LVDS",
 544         "INTERNAL_TMDS1",
 545         "INTERNAL_TMDS2",
 546         "INTERNAL_DAC1",
 547         "INTERNAL_DAC2",
 548         "INTERNAL_SDVOA",
 549         "INTERNAL_SDVOB",
 550         "SI170B",
 551         "CH7303",
 552         "CH7301",
 553         "INTERNAL_DVO1",
 554         "EXTERNAL_SDVOA",
 555         "EXTERNAL_SDVOB",
 556         "TITFP513",
 557         "INTERNAL_LVTM1",
 558         "VT1623",
 559         "HDMI_SI1930",
 560         "HDMI_INTERNAL",
 561         "INTERNAL_KLDSCP_TMDS1",
 562         "INTERNAL_KLDSCP_DVO1",
 563         "INTERNAL_KLDSCP_DAC1",
 564         "INTERNAL_KLDSCP_DAC2",
 565         "SI178",
 566         "MVPU_FPGA",
 567         "INTERNAL_DDI",
 568         "VT1625",
 569         "HDMI_SI1932",
 570         "DP_AN9801",
 571         "DP_DP501",
 572         "INTERNAL_UNIPHY",
 573         "INTERNAL_KLDSCP_LVTMA",
 574         "INTERNAL_UNIPHY1",
 575         "INTERNAL_UNIPHY2",
 576         "NUTMEG",
 577         "TRAVIS",
 578         "INTERNAL_VCE"
 579 };
 580
 581 static const char *hpd_names[6] = {
 582         "HPD1",
 583         "HPD2",
 584         "HPD3",
 585         "HPD4",
 586         "HPD5",
 587         "HPD6",
 588 };
 589
 590 static void radeon_print_display_setup(struct drm_device *dev)
 591 {
 592         struct drm_connector *connector;
 593         struct radeon_connector *radeon_connector;
 594         struct drm_encoder *encoder;
 595         struct radeon_encoder *radeon_encoder;
 596         uint32_t devices;
 597         int i = 0;
 598
 599         DRM_INFO("Radeon Display Connectors\n");
 600         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 601                 radeon_connector = to_radeon_connector(connector);
 602                 DRM_INFO("Connector %d:\n", i);
 603                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 604                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 605                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 606                 if (radeon_connector->ddc_bus) {
 607                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 608                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 609                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 610                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 611                                  radeon_connector->ddc_bus->rec.a_data_reg,
 612                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 613                                  radeon_connector->ddc_bus->rec.en_data_reg,
 614                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 615                                  radeon_connector->ddc_bus->rec.y_data_reg);
 616                         if (radeon_connector->router.ddc_valid)
 617                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 618                                          radeon_connector->router.ddc_mux_control_pin,
 619                                          radeon_connector->router.ddc_mux_state);
 620                         if (radeon_connector->router.cd_valid)
 621                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 622                                          radeon_connector->router.cd_mux_control_pin,
 623                                          radeon_connector->router.cd_mux_state);
 624                 } else {
 625                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 626                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 627                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 628                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 629                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 630                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 631                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 632                 }
 633                 DRM_INFO("  Encoders:\n");
 634                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 635                         radeon_encoder = to_radeon_encoder(encoder);
 636                         devices = radeon_encoder->devices & radeon_connector->devices;
 637                         if (devices) {
 638                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 639                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 640                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 641                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 642                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 643                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 644                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 645                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 646                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 647                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 648                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 649                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 650                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 651                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 652                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 653                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 654                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 655                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 656                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 657                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 658                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 659                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 660                         }
 661                 }
 662                 i++;
 663         }
 664 }
 665
 666 static bool radeon_setup_enc_conn(struct drm_device *dev)
 667 {
 668         struct radeon_device *rdev = dev->dev_private;
 669         bool ret = false;
 670
 671         if (rdev->bios) {
 672                 if (rdev->is_atom_bios) {
 673                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 674                         if (ret == false)
 675                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 676                 } else {
 677                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 678                         if (ret == false)
 679                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 680                 }
 681         } else {
 682                 if (!ASIC_IS_AVIVO(rdev))
 683                         ret = radeon_get_legacy_connector_info_from_table(dev);
 684         }
 685         if (ret) {
 686                 radeon_setup_encoder_clones(dev);
 687                 radeon_print_display_setup(dev);
 688         }
 689
 690         return ret;
 691 }
 692
 693 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 694 {
 695         struct drm_device *dev = radeon_connector->base.dev;
 696         struct radeon_device *rdev = dev->dev_private;
 697         int ret = 0;
 698
 699         /* on hw with routers, select right port */
 700         if (radeon_connector->router.ddc_valid)
 701                 radeon_router_select_ddc_port(radeon_connector);
 702
 703         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 704             ENCODER_OBJECT_ID_NONE) {
 705                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 706
 707                 if (dig->dp_i2c_bus)
 708                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 709                                                               dig->dp_i2c_bus->adapter);
 710         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 711                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 712                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 713
 714                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 715                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 716                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 717                                                               dig->dp_i2c_bus->adapter);
 718                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 719                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 720                                                               radeon_connector->ddc_bus->adapter);
 721         } else {
 722                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 723                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 724                                                               radeon_connector->ddc_bus->adapter);
 725         }
 726
 727         if (!radeon_connector->edid) {
 728                 if (rdev->is_atom_bios) {
 729                         /* some laptops provide a hardcoded edid in rom for LCDs */
 730                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 731                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 732                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 733                 } else
 734                         /* some servers provide a hardcoded edid in rom for KVMs */
 735                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 736         }
 737         if (radeon_connector->edid) {
 738                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 739                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 740                 return ret;
 741         }
 742         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 743         return 0;
 744 }
 745
 746 /* avivo */
 747 static void avivo_get_fb_div(struct radeon_pll *pll,
 748                              u32 target_clock,
 749                              u32 post_div,
 750                              u32 ref_div,
 751                              u32 *fb_div,
 752                              u32 *frac_fb_div)
 753 {
 754         u32 tmp = post_div * ref_div;
 755
 756         tmp *= target_clock;
 757         *fb_div = tmp / pll->reference_freq;
 758         *frac_fb_div = tmp % pll->reference_freq;
 759
 760         if (*fb_div > pll->max_feedback_div)
 761                 *fb_div = pll->max_feedback_div;
 762         else if (*fb_div < pll->min_feedback_div)
 763                 *fb_div = pll->min_feedback_div;
 764 }
 765
 766 static u32 avivo_get_post_div(struct radeon_pll *pll,
 767                               u32 target_clock)
 768 {
 769         u32 vco, post_div, tmp;
 770
 771         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 772                 return pll->post_div;
 773
 774         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 775                 if (pll->flags & RADEON_PLL_IS_LCD)
 776                         vco = pll->lcd_pll_out_min;
 777                 else
 778                         vco = pll->pll_out_min;
 779         } else {
 780                 if (pll->flags & RADEON_PLL_IS_LCD)
 781                         vco = pll->lcd_pll_out_max;
 782                 else
 783                         vco = pll->pll_out_max;
 784         }
 785
 786         post_div = vco / target_clock;
 787         tmp = vco % target_clock;
 788
 789         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 790                 if (tmp)
 791                         post_div++;
 792         } else {
 793                 if (!tmp)
 794                         post_div--;
 795         }
 796
 797         if (post_div > pll->max_post_div)
 798                 post_div = pll->max_post_div;
 799         else if (post_div < pll->min_post_div)
 800                 post_div = pll->min_post_div;
 801
 802         return post_div;
 803 }
 804
 805 #define MAX_TOLERANCE 10
 806
 807 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 808                               u32 freq,
 809                               u32 *dot_clock_p,
 810                               u32 *fb_div_p,
 811                               u32 *frac_fb_div_p,
 812                               u32 *ref_div_p,
 813                               u32 *post_div_p)
 814 {
 815         u32 target_clock = freq / 10;
 816         u32 post_div = avivo_get_post_div(pll, target_clock);
 817         u32 ref_div = pll->min_ref_div;
 818         u32 fb_div = 0, frac_fb_div = 0, tmp;
 819
 820         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 821                 ref_div = pll->reference_div;
 822
 823         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 824                 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
 825                 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
 826                 if (frac_fb_div >= 5) {
 827                         frac_fb_div -= 5;
 828                         frac_fb_div = frac_fb_div / 10;
 829                         frac_fb_div++;
 830                 }
 831                 if (frac_fb_div >= 10) {
 832                         fb_div++;
 833                         frac_fb_div = 0;
 834                 }
 835         } else {
 836                 while (ref_div <= pll->max_ref_div) {
 837                         avivo_get_fb_div(pll, target_clock, post_div, ref_div,
 838                                          &fb_div, &frac_fb_div);
 839                         if (frac_fb_div >= (pll->reference_freq / 2))
 840                                 fb_div++;
 841                         frac_fb_div = 0;
 842                         tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
 843                         tmp = (tmp * 10000) / target_clock;
 844
 845                         if (tmp > (10000 + MAX_TOLERANCE))
 846                                 ref_div++;
 847                         else if (tmp >= (10000 - MAX_TOLERANCE))
 848                                 break;
 849                         else
 850                                 ref_div++;
 851                 }
 852         }
 853
 854         *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
 855                 (ref_div * post_div * 10);
 856         *fb_div_p = fb_div;
 857         *frac_fb_div_p = frac_fb_div;
 858         *ref_div_p = ref_div;
 859         *post_div_p = post_div;
 860         DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 861                       *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 862 }
 863
 864 /* pre-avivo */
 865 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 866 {
 867         uint64_t mod;
 868
 869         n += d / 2;
 870
 871         mod = do_div(n, d);
 872         return n;
 873 }
 874
 875 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 876                                uint64_t freq,
 877                                uint32_t *dot_clock_p,
 878                                uint32_t *fb_div_p,
 879                                uint32_t *frac_fb_div_p,
 880                                uint32_t *ref_div_p,
 881                                uint32_t *post_div_p)
 882 {
 883         uint32_t min_ref_div = pll->min_ref_div;
 884         uint32_t max_ref_div = pll->max_ref_div;
 885         uint32_t min_post_div = pll->min_post_div;
 886         uint32_t max_post_div = pll->max_post_div;
 887         uint32_t min_fractional_feed_div = 0;
 888         uint32_t max_fractional_feed_div = 0;
 889         uint32_t best_vco = pll->best_vco;
 890         uint32_t best_post_div = 1;
 891         uint32_t best_ref_div = 1;
 892         uint32_t best_feedback_div = 1;
 893         uint32_t best_frac_feedback_div = 0;
 894         uint32_t best_freq = -1;
 895         uint32_t best_error = 0xffffffff;
 896         uint32_t best_vco_diff = 1;
 897         uint32_t post_div;
 898         u32 pll_out_min, pll_out_max;
 899
 900         DRM_DEBUG_KMS("PLL freq %ju %u %u\n", (uintmax_t)freq, pll->min_ref_div, pll->max_ref_div);
 901         freq = freq * 1000;
 902
 903         if (pll->flags & RADEON_PLL_IS_LCD) {
 904                 pll_out_min = pll->lcd_pll_out_min;
 905                 pll_out_max = pll->lcd_pll_out_max;
 906         } else {
 907                 pll_out_min = pll->pll_out_min;
 908                 pll_out_max = pll->pll_out_max;
 909         }
 910
 911         if (pll_out_min > 64800)
 912                 pll_out_min = 64800;
 913
 914         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 915                 min_ref_div = max_ref_div = pll->reference_div;
 916         else {
 917                 while (min_ref_div < max_ref_div-1) {
 918                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 919                         uint32_t pll_in = pll->reference_freq / mid;
 920                         if (pll_in < pll->pll_in_min)
 921                                 max_ref_div = mid;
 922                         else if (pll_in > pll->pll_in_max)
 923                                 min_ref_div = mid;
 924                         else
 925                                 break;
 926                 }
 927         }
 928
 929         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 930                 min_post_div = max_post_div = pll->post_div;
 931
 932         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 933                 min_fractional_feed_div = pll->min_frac_feedback_div;
 934                 max_fractional_feed_div = pll->max_frac_feedback_div;
 935         }
 936
 937         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 938                 uint32_t ref_div;
 939
 940                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 941                         continue;
 942
 943                 /* legacy radeons only have a few post_divs */
 944                 if (pll->flags & RADEON_PLL_LEGACY) {
 945                         if ((post_div == 5) ||
 946                             (post_div == 7) ||
 947                             (post_div == 9) ||
 948                             (post_div == 10) ||
 949                             (post_div == 11) ||
 950                             (post_div == 13) ||
 951                             (post_div == 14) ||
 952                             (post_div == 15))
 953                                 continue;
 954                 }
 955
 956                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 957                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 958                         uint32_t pll_in = pll->reference_freq / ref_div;
 959                         uint32_t min_feed_div = pll->min_feedback_div;
 960                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 961
 962                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 963                                 continue;
 964
 965                         while (min_feed_div < max_feed_div) {
 966                                 uint32_t vco;
 967                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 968                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 969                                 uint32_t frac_feedback_div;
 970                                 uint64_t tmp;
 971
 972                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 973
 974                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 975                                 vco = radeon_div(tmp, ref_div);
 976
 977                                 if (vco < pll_out_min) {
 978                                         min_feed_div = feedback_div + 1;
 979                                         continue;
 980                                 } else if (vco > pll_out_max) {
 981                                         max_feed_div = feedback_div;
 982                                         continue;
 983                                 }
 984
 985                                 while (min_frac_feed_div < max_frac_feed_div) {
 986                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 987                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 988                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 989                                         current_freq = radeon_div(tmp, ref_div * post_div);
 990
 991                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 992                                                 if (freq < current_freq)
 993                                                         error = 0xffffffff;
 994                                                 else
 995                                                         error = freq - current_freq;
 996                                         } else
 997                                                 error = abs(current_freq - freq);
 998                                         vco_diff = abs(vco - best_vco);
 999
1000                                         if ((best_vco == 0 && error < best_error) ||
1001                                             (best_vco != 0 &&
1002                                              ((best_error > 100 && error < best_error - 100) ||
1003                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1004                                                 best_post_div = post_div;
1005                                                 best_ref_div = ref_div;
1006                                                 best_feedback_div = feedback_div;
1007                                                 best_frac_feedback_div = frac_feedback_div;
1008                                                 best_freq = current_freq;
1009                                                 best_error = error;
1010                                                 best_vco_diff = vco_diff;
1011                                         } else if (current_freq == freq) {
1012                                                 if (best_freq == -1) {
1013                                                         best_post_div = post_div;
1014                                                         best_ref_div = ref_div;
1015                                                         best_feedback_div = feedback_div;
1016                                                         best_frac_feedback_div = frac_feedback_div;
1017                                                         best_freq = current_freq;
1018                                                         best_error = error;
1019                                                         best_vco_diff = vco_diff;
1020                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1021                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1022                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1023                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1024                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1025                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1026                                                         best_post_div = post_div;
1027                                                         best_ref_div = ref_div;
1028                                                         best_feedback_div = feedback_div;
1029                                                         best_frac_feedback_div = frac_feedback_div;
1030                                                         best_freq = current_freq;
1031                                                         best_error = error;
1032                                                         best_vco_diff = vco_diff;
1033                                                 }
1034                                         }
1035                                         if (current_freq < freq)
1036                                                 min_frac_feed_div = frac_feedback_div + 1;
1037                                         else
1038                                                 max_frac_feed_div = frac_feedback_div;
1039                                 }
1040                                 if (current_freq < freq)
1041                                         min_feed_div = feedback_div + 1;
1042                                 else
1043                                         max_feed_div = feedback_div;
1044                         }
1045                 }
1046         }
1047
1048         *dot_clock_p = best_freq / 10000;
1049         *fb_div_p = best_feedback_div;
1050         *frac_fb_div_p = best_frac_feedback_div;
1051         *ref_div_p = best_ref_div;
1052         *post_div_p = best_post_div;
1053         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1054                       (long long)freq,
1055                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1056                       best_ref_div, best_post_div);
1057
1058 }
1059
1060 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1061 {
1062         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1063
1064         if (radeon_fb->obj) {
1065                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1066         }
1067         drm_framebuffer_cleanup(fb);
1068         drm_free(radeon_fb, M_DRM);
1069 }
1070
1071 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1072                                                   struct drm_file *file_priv,
1073                                                   unsigned int *handle)
1074 {
1075         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1076
1077         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1078 }
1079
1080 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1081         .destroy = radeon_user_framebuffer_destroy,
1082         .create_handle = radeon_user_framebuffer_create_handle,
1083 };
1084
1085 int
1086 radeon_framebuffer_init(struct drm_device *dev,
1087                         struct radeon_framebuffer *rfb,
1088                         struct drm_mode_fb_cmd2 *mode_cmd,
1089                         struct drm_gem_object *obj)
1090 {
1091         int ret;
1092         rfb->obj = obj;
1093         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1094         if (ret) {
1095                 rfb->obj = NULL;
1096                 return ret;
1097         }
1098         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1099         return 0;
1100 }
1101
1102 static struct drm_framebuffer *
1103 radeon_user_framebuffer_create(struct drm_device *dev,
1104                                struct drm_file *file_priv,
1105                                struct drm_mode_fb_cmd2 *mode_cmd)
1106 {
1107         struct drm_gem_object *obj;
1108         struct radeon_framebuffer *radeon_fb;
1109         int ret;
1110
1111         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1112         if (obj ==  NULL) {
1113                 dev_err(dev->dev, "No GEM object associated to handle 0x%08X, "
1114                         "can't create framebuffer\n", mode_cmd->handles[0]);
1115                 return ERR_PTR(-ENOENT);
1116         }
1117
1118         radeon_fb = kmalloc(sizeof(*radeon_fb), M_DRM,
1119                             M_WAITOK | M_ZERO);
1120         if (radeon_fb == NULL) {
1121                 drm_gem_object_unreference_unlocked(obj);
1122                 return ERR_PTR(-ENOMEM);
1123         }
1124
1125         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1126         if (ret) {
1127                 kfree(radeon_fb, M_DRM);
1128                 drm_gem_object_unreference_unlocked(obj);
1129                 return ERR_PTR(ret);
1130         }
1131
1132         return &radeon_fb->base;
1133 }
1134
1135 static void radeon_output_poll_changed(struct drm_device *dev)
1136 {
1137         struct radeon_device *rdev = dev->dev_private;
1138         radeon_fb_output_poll_changed(rdev);
1139 }
1140
1141 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1142         .fb_create = radeon_user_framebuffer_create,
1143         .output_poll_changed = radeon_output_poll_changed
1144 };
1145
1146 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1147 {       { 0, "driver" },
1148         { 1, "bios" },
1149 };
1150
1151 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1152 {       { TV_STD_NTSC, "ntsc" },
1153         { TV_STD_PAL, "pal" },
1154         { TV_STD_PAL_M, "pal-m" },
1155         { TV_STD_PAL_60, "pal-60" },
1156         { TV_STD_NTSC_J, "ntsc-j" },
1157         { TV_STD_SCART_PAL, "scart-pal" },
1158         { TV_STD_PAL_CN, "pal-cn" },
1159         { TV_STD_SECAM, "secam" },
1160 };
1161
1162 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1163 {       { UNDERSCAN_OFF, "off" },
1164         { UNDERSCAN_ON, "on" },
1165         { UNDERSCAN_AUTO, "auto" },
1166 };
1167
1168 static int radeon_modeset_create_props(struct radeon_device *rdev)
1169 {
1170         int sz;
1171
1172         if (rdev->is_atom_bios) {
1173                 rdev->mode_info.coherent_mode_property =
1174                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1175                 if (!rdev->mode_info.coherent_mode_property)
1176                         return -ENOMEM;
1177         }
1178
1179         if (!ASIC_IS_AVIVO(rdev)) {
1180                 sz = DRM_ARRAY_SIZE(radeon_tmds_pll_enum_list);
1181                 rdev->mode_info.tmds_pll_property =
1182                         drm_property_create_enum(rdev->ddev, 0,
1183                                             "tmds_pll",
1184                                             radeon_tmds_pll_enum_list, sz);
1185         }
1186
1187         rdev->mode_info.load_detect_property =
1188                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1189         if (!rdev->mode_info.load_detect_property)
1190                 return -ENOMEM;
1191
1192         drm_mode_create_scaling_mode_property(rdev->ddev);
1193
1194         sz = DRM_ARRAY_SIZE(radeon_tv_std_enum_list);
1195         rdev->mode_info.tv_std_property =
1196                 drm_property_create_enum(rdev->ddev, 0,
1197                                     "tv standard",
1198                                     radeon_tv_std_enum_list, sz);
1199
1200         sz = DRM_ARRAY_SIZE(radeon_underscan_enum_list);
1201         rdev->mode_info.underscan_property =
1202                 drm_property_create_enum(rdev->ddev, 0,
1203                                     "underscan",
1204                                     radeon_underscan_enum_list, sz);
1205
1206         rdev->mode_info.underscan_hborder_property =
1207                 drm_property_create_range(rdev->ddev, 0,
1208                                         "underscan hborder", 0, 128);
1209         if (!rdev->mode_info.underscan_hborder_property)
1210                 return -ENOMEM;
1211
1212         rdev->mode_info.underscan_vborder_property =
1213                 drm_property_create_range(rdev->ddev, 0,
1214                                         "underscan vborder", 0, 128);
1215         if (!rdev->mode_info.underscan_vborder_property)
1216                 return -ENOMEM;
1217
1218         return 0;
1219 }
1220
1221 void radeon_update_display_priority(struct radeon_device *rdev)
1222 {
1223         /* adjustment options for the display watermarks */
1224         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1225                 /* set display priority to high for r3xx, rv515 chips
1226                  * this avoids flickering due to underflow to the
1227                  * display controllers during heavy acceleration.
1228                  * Don't force high on rs4xx igp chips as it seems to
1229                  * affect the sound card.  See kernel bug 15982.
1230                  */
1231                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1232                     !(rdev->flags & RADEON_IS_IGP))
1233                         rdev->disp_priority = 2;
1234                 else
1235                         rdev->disp_priority = 0;
1236         } else
1237                 rdev->disp_priority = radeon_disp_priority;
1238
1239 }
1240
1241 /*
1242  * Allocate hdmi structs and determine register offsets
1243  */
1244 static void radeon_afmt_init(struct radeon_device *rdev)
1245 {
1246         int i;
1247
1248         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1249                 rdev->mode_info.afmt[i] = NULL;
1250
1251         if (ASIC_IS_DCE6(rdev)) {
1252                 /* todo */
1253         } else if (ASIC_IS_DCE4(rdev)) {
1254                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1255                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1256                 rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt),
1257                                                   M_DRM,
1258                                                   M_WAITOK | M_ZERO);
1259                 if (rdev->mode_info.afmt[0]) {
1260                         rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1261                         rdev->mode_info.afmt[0]->id = 0;
1262                 }
1263                 rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt),
1264                                                   M_DRM,
1265                                                   M_WAITOK | M_ZERO);
1266                 if (rdev->mode_info.afmt[1]) {
1267                         rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1268                         rdev->mode_info.afmt[1]->id = 1;
1269                 }
1270                 if (!ASIC_IS_DCE41(rdev)) {
1271                         rdev->mode_info.afmt[2] = kmalloc(sizeof(struct radeon_afmt),
1272                                                           M_DRM,
1273                                                           M_WAITOK | M_ZERO);
1274                         if (rdev->mode_info.afmt[2]) {
1275                                 rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1276                                 rdev->mode_info.afmt[2]->id = 2;
1277                         }
1278                         rdev->mode_info.afmt[3] = kmalloc(sizeof(struct radeon_afmt),
1279                                                           M_DRM,
1280                                                           M_WAITOK | M_ZERO);
1281                         if (rdev->mode_info.afmt[3]) {
1282                                 rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1283                                 rdev->mode_info.afmt[3]->id = 3;
1284                         }
1285                         rdev->mode_info.afmt[4] = kmalloc(sizeof(struct radeon_afmt),
1286                                                           M_DRM,
1287                                                           M_WAITOK | M_ZERO);
1288                         if (rdev->mode_info.afmt[4]) {
1289                                 rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1290                                 rdev->mode_info.afmt[4]->id = 4;
1291                         }
1292                         rdev->mode_info.afmt[5] = kmalloc(sizeof(struct radeon_afmt),
1293                                                           M_DRM,
1294                                                           M_WAITOK | M_ZERO);
1295                         if (rdev->mode_info.afmt[5]) {
1296                                 rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1297                                 rdev->mode_info.afmt[5]->id = 5;
1298                         }
1299                 }
1300         } else if (ASIC_IS_DCE3(rdev)) {
1301                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1302                 rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt),
1303                                                   M_DRM,
1304                                                   M_WAITOK | M_ZERO);
1305                 if (rdev->mode_info.afmt[0]) {
1306                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1307                         rdev->mode_info.afmt[0]->id = 0;
1308                 }
1309                 rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt),
1310                                                   M_DRM,
1311                                                   M_WAITOK | M_ZERO);
1312                 if (rdev->mode_info.afmt[1]) {
1313                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1314                         rdev->mode_info.afmt[1]->id = 1;
1315                 }
1316         } else if (ASIC_IS_DCE2(rdev)) {
1317                 /* DCE2 has at least 1 routable audio block */
1318                 rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt),
1319                                                   M_DRM,
1320                                                   M_WAITOK | M_ZERO);
1321                 if (rdev->mode_info.afmt[0]) {
1322                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1323                         rdev->mode_info.afmt[0]->id = 0;
1324                 }
1325                 /* r6xx has 2 routable audio blocks */
1326                 if (rdev->family >= CHIP_R600) {
1327                         rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt),
1328                                                           M_DRM,
1329                                                           M_WAITOK | M_ZERO);
1330                         if (rdev->mode_info.afmt[1]) {
1331                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1332                                 rdev->mode_info.afmt[1]->id = 1;
1333                         }
1334                 }
1335         }
1336 }
1337
1338 static void radeon_afmt_fini(struct radeon_device *rdev)
1339 {
1340         int i;
1341
1342         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1343                 drm_free(rdev->mode_info.afmt[i], M_DRM);
1344                 rdev->mode_info.afmt[i] = NULL;
1345         }
1346 }
1347
1348 int radeon_modeset_init(struct radeon_device *rdev)
1349 {
1350         int i;
1351         int ret;
1352
1353         drm_mode_config_init(rdev->ddev);
1354         rdev->mode_info.mode_config_initialized = true;
1355
1356         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1357
1358         if (ASIC_IS_DCE5(rdev)) {
1359                 rdev->ddev->mode_config.max_width = 16384;
1360                 rdev->ddev->mode_config.max_height = 16384;
1361         } else if (ASIC_IS_AVIVO(rdev)) {
1362                 rdev->ddev->mode_config.max_width = 8192;
1363                 rdev->ddev->mode_config.max_height = 8192;
1364         } else {
1365                 rdev->ddev->mode_config.max_width = 4096;
1366                 rdev->ddev->mode_config.max_height = 4096;
1367         }
1368
1369         rdev->ddev->mode_config.preferred_depth = 24;
1370         rdev->ddev->mode_config.prefer_shadow = 1;
1371
1372         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1373
1374         ret = radeon_modeset_create_props(rdev);
1375         if (ret) {
1376                 return ret;
1377         }
1378
1379         /* init i2c buses */
1380         radeon_i2c_init(rdev);
1381
1382         /* check combios for a valid hardcoded EDID - Sun servers */
1383         if (!rdev->is_atom_bios) {
1384                 /* check for hardcoded EDID in BIOS */
1385                 radeon_combios_check_hardcoded_edid(rdev);
1386         }
1387
1388         /* allocate crtcs */
1389         for (i = 0; i < rdev->num_crtc; i++) {
1390                 radeon_crtc_init(rdev->ddev, i);
1391         }
1392
1393         /* okay we should have all the bios connectors */
1394         ret = radeon_setup_enc_conn(rdev->ddev);
1395         if (!ret) {
1396                 return ret;
1397         }
1398
1399         /* init dig PHYs, disp eng pll */
1400         if (rdev->is_atom_bios) {
1401                 radeon_atom_encoder_init(rdev);
1402                 radeon_atom_disp_eng_pll_init(rdev);
1403         }
1404
1405         /* initialize hpd */
1406         radeon_hpd_init(rdev);
1407
1408         /* setup afmt */
1409         radeon_afmt_init(rdev);
1410
1411         /* Initialize power management */
1412         radeon_pm_init(rdev);
1413
1414         radeon_fbdev_init(rdev);
1415         drm_kms_helper_poll_init(rdev->ddev);
1416
1417         return 0;
1418 }
1419
1420 void radeon_modeset_fini(struct radeon_device *rdev)
1421 {
1422         radeon_fbdev_fini(rdev);
1423         drm_free(rdev->mode_info.bios_hardcoded_edid, M_DRM);
1424         radeon_pm_fini(rdev);
1425
1426         if (rdev->mode_info.mode_config_initialized) {
1427                 radeon_afmt_fini(rdev);
1428                 drm_kms_helper_poll_fini(rdev->ddev);
1429                 radeon_hpd_fini(rdev);
1430                 DRM_UNLOCK(rdev->ddev); /* Work around lock recursion. dumbbell@ */
1431                 drm_mode_config_cleanup(rdev->ddev);
1432                 DRM_LOCK(rdev->ddev);
1433                 rdev->mode_info.mode_config_initialized = false;
1434         }
1435         /* free i2c buses */
1436         radeon_i2c_fini(rdev);
1437 }
1438
1439 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1440 {
1441         /* try and guess if this is a tv or a monitor */
1442         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1443             (mode->vdisplay == 576) || /* 576p */
1444             (mode->vdisplay == 720) || /* 720p */
1445             (mode->vdisplay == 1080)) /* 1080p */
1446                 return true;
1447         else
1448                 return false;
1449 }
1450
1451 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1452                                 const struct drm_display_mode *mode,
1453                                 struct drm_display_mode *adjusted_mode)
1454 {
1455         struct drm_device *dev = crtc->dev;
1456         struct radeon_device *rdev = dev->dev_private;
1457         struct drm_encoder *encoder;
1458         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1459         struct radeon_encoder *radeon_encoder;
1460         struct drm_connector *connector;
1461         struct radeon_connector *radeon_connector;
1462         bool first = true;
1463         u32 src_v = 1, dst_v = 1;
1464         u32 src_h = 1, dst_h = 1;
1465
1466         radeon_crtc->h_border = 0;
1467         radeon_crtc->v_border = 0;
1468
1469         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1470                 if (encoder->crtc != crtc)
1471                         continue;
1472                 radeon_encoder = to_radeon_encoder(encoder);
1473                 connector = radeon_get_connector_for_encoder(encoder);
1474                 radeon_connector = to_radeon_connector(connector);
1475
1476                 if (first) {
1477                         /* set scaling */
1478                         if (radeon_encoder->rmx_type == RMX_OFF)
1479                                 radeon_crtc->rmx_type = RMX_OFF;
1480                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1481                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1482                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1483                         else
1484                                 radeon_crtc->rmx_type = RMX_OFF;
1485                         /* copy native mode */
1486                         memcpy(&radeon_crtc->native_mode,
1487                                &radeon_encoder->native_mode,
1488                                 sizeof(struct drm_display_mode));
1489                         src_v = crtc->mode.vdisplay;
1490                         dst_v = radeon_crtc->native_mode.vdisplay;
1491                         src_h = crtc->mode.hdisplay;
1492                         dst_h = radeon_crtc->native_mode.hdisplay;
1493
1494                         /* fix up for overscan on hdmi */
1495                         if (ASIC_IS_AVIVO(rdev) &&
1496                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1497                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1498                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1499                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1500                               is_hdtv_mode(mode)))) {
1501                                 if (radeon_encoder->underscan_hborder != 0)
1502                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1503                                 else
1504                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1505                                 if (radeon_encoder->underscan_vborder != 0)
1506                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1507                                 else
1508                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1509                                 radeon_crtc->rmx_type = RMX_FULL;
1510                                 src_v = crtc->mode.vdisplay;
1511                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1512                                 src_h = crtc->mode.hdisplay;
1513                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1514                         }
1515                         first = false;
1516                 } else {
1517                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1518                                 /* WARNING: Right now this can't happen but
1519                                  * in the future we need to check that scaling
1520                                  * are consistent across different encoder
1521                                  * (ie all encoder can work with the same
1522                                  *  scaling).
1523                                  */
1524                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1525                                 return false;
1526                         }
1527                 }
1528         }
1529         if (radeon_crtc->rmx_type != RMX_OFF) {
1530                 fixed20_12 a, b;
1531                 a.full = dfixed_const(src_v);
1532                 b.full = dfixed_const(dst_v);
1533                 radeon_crtc->vsc.full = dfixed_div(a, b);
1534                 a.full = dfixed_const(src_h);
1535                 b.full = dfixed_const(dst_h);
1536                 radeon_crtc->hsc.full = dfixed_div(a, b);
1537         } else {
1538                 radeon_crtc->vsc.full = dfixed_const(1);
1539                 radeon_crtc->hsc.full = dfixed_const(1);
1540         }
1541         return true;
1542 }
1543
1544 /*
1545  * Retrieve current video scanout position of crtc on a given gpu.
1546  *
1547  * \param dev Device to query.
1548  * \param crtc Crtc to query.
1549  * \param *vpos Location where vertical scanout position should be stored.
1550  * \param *hpos Location where horizontal scanout position should go.
1551  *
1552  * Returns vpos as a positive number while in active scanout area.
1553  * Returns vpos as a negative number inside vblank, counting the number
1554  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1555  * until start of active scanout / end of vblank."
1556  *
1557  * \return Flags, or'ed together as follows:
1558  *
1559  * DRM_SCANOUTPOS_VALID = Query successful.
1560  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1561  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1562  * this flag means that returned position may be offset by a constant but
1563  * unknown small number of scanlines wrt. real scanout position.
1564  *
1565  */
1566 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1567 {
1568         u32 stat_crtc = 0, vbl = 0, position = 0;
1569         int vbl_start, vbl_end, vtotal, ret = 0;
1570         bool in_vbl = true;
1571
1572         struct radeon_device *rdev = dev->dev_private;
1573
1574         if (ASIC_IS_DCE4(rdev)) {
1575                 if (crtc == 0) {
1576                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1577                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1578                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1579                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1580                         ret |= DRM_SCANOUTPOS_VALID;
1581                 }
1582                 if (crtc == 1) {
1583                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1584                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1585                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1586                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1587                         ret |= DRM_SCANOUTPOS_VALID;
1588                 }
1589                 if (crtc == 2) {
1590                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1591                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1592                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1593                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1594                         ret |= DRM_SCANOUTPOS_VALID;
1595                 }
1596                 if (crtc == 3) {
1597                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1598                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1599                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1600                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1601                         ret |= DRM_SCANOUTPOS_VALID;
1602                 }
1603                 if (crtc == 4) {
1604                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1605                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1606                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1607                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1608                         ret |= DRM_SCANOUTPOS_VALID;
1609                 }
1610                 if (crtc == 5) {
1611                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1612                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1613                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1614                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1615                         ret |= DRM_SCANOUTPOS_VALID;
1616                 }
1617         } else if (ASIC_IS_AVIVO(rdev)) {
1618                 if (crtc == 0) {
1619                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1620                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1621                         ret |= DRM_SCANOUTPOS_VALID;
1622                 }
1623                 if (crtc == 1) {
1624                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1625                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1626                         ret |= DRM_SCANOUTPOS_VALID;
1627                 }
1628         } else {
1629                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1630                 if (crtc == 0) {
1631                         /* Assume vbl_end == 0, get vbl_start from
1632                          * upper 16 bits.
1633                          */
1634                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1635                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1636                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1637                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1638                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1639                         if (!(stat_crtc & 1))
1640                                 in_vbl = false;
1641
1642                         ret |= DRM_SCANOUTPOS_VALID;
1643                 }
1644                 if (crtc == 1) {
1645                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1646                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1647                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1648                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1649                         if (!(stat_crtc & 1))
1650                                 in_vbl = false;
1651
1652                         ret |= DRM_SCANOUTPOS_VALID;
1653                 }
1654         }
1655
1656         /* Decode into vertical and horizontal scanout position. */
1657         *vpos = position & 0x1fff;
1658         *hpos = (position >> 16) & 0x1fff;
1659
1660         /* Valid vblank area boundaries from gpu retrieved? */
1661         if (vbl > 0) {
1662                 /* Yes: Decode. */
1663                 ret |= DRM_SCANOUTPOS_ACCURATE;
1664                 vbl_start = vbl & 0x1fff;
1665                 vbl_end = (vbl >> 16) & 0x1fff;
1666         }
1667         else {
1668                 /* No: Fake something reasonable which gives at least ok results. */
1669                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1670                 vbl_end = 0;
1671         }
1672
1673         /* Test scanout position against vblank region. */
1674         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1675                 in_vbl = false;
1676
1677         /* Check if inside vblank area and apply corrective offsets:
1678          * vpos will then be >=0 in video scanout area, but negative
1679          * within vblank area, counting down the number of lines until
1680          * start of scanout.
1681          */
1682
1683         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1684         if (in_vbl && (*vpos >= vbl_start)) {
1685                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1686                 *vpos = *vpos - vtotal;
1687         }
1688
1689         /* Correct for shifted end of vbl at vbl_end. */
1690         *vpos = *vpos - vbl_end;
1691
1692         /* In vblank? */
1693         if (in_vbl)
1694                 ret |= DRM_SCANOUTPOS_INVBL;
1695
1696         return ret;
1697 }