2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
26 * $FreeBSD: head/sys/dev/drm2/radeon/r600_hdmi.c 254885 2013-08-25 19:37:15Z dumbbell $
29 #include <linux/hdmi.h>
31 #include <uapi_drm/radeon_drm.h>
33 #include "radeon_asic.h"
40 enum r600_hdmi_color_format {
47 * IEC60958 status bits
49 enum r600_hdmi_iec_status_bits {
50 AUDIO_STATUS_DIG_ENABLE = 0x01,
51 AUDIO_STATUS_V = 0x02,
52 AUDIO_STATUS_VCFG = 0x04,
53 AUDIO_STATUS_EMPHASIS = 0x08,
54 AUDIO_STATUS_COPYRIGHT = 0x10,
55 AUDIO_STATUS_NONAUDIO = 0x20,
56 AUDIO_STATUS_PROFESSIONAL = 0x40,
57 AUDIO_STATUS_LEVEL = 0x80
60 static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
61 /* 32kHz 44.1kHz 48kHz */
62 /* Clock N CTS N CTS N CTS */
63 { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */
64 { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */
65 { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */
66 { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */
67 { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */
68 { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */
69 { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
70 { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */
71 { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */
72 { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */
73 { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */
77 * calculate CTS value if it's not found in the table
79 static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq)
82 *CTS = clock * N / (128 * freq) * 1000;
83 DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n",
87 struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
89 struct radeon_hdmi_acr res;
92 for (i = 0; r600_hdmi_predefined_acr[i].clock != clock &&
93 r600_hdmi_predefined_acr[i].clock != 0; i++)
95 res = r600_hdmi_predefined_acr[i];
97 /* In case some CTS are missing */
98 r600_hdmi_calc_cts(clock, &res.cts_32khz, res.n_32khz, 32000);
99 r600_hdmi_calc_cts(clock, &res.cts_44_1khz, res.n_44_1khz, 44100);
100 r600_hdmi_calc_cts(clock, &res.cts_48khz, res.n_48khz, 48000);
106 * update the N and CTS parameters for a given pixel clock rate
108 static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
110 struct drm_device *dev = encoder->dev;
111 struct radeon_device *rdev = dev->dev_private;
112 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
113 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
114 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
115 uint32_t offset = dig->afmt->offset;
117 WREG32(HDMI0_ACR_32_0 + offset, HDMI0_ACR_CTS_32(acr.cts_32khz));
118 WREG32(HDMI0_ACR_32_1 + offset, acr.n_32khz);
120 WREG32(HDMI0_ACR_44_0 + offset, HDMI0_ACR_CTS_44(acr.cts_44_1khz));
121 WREG32(HDMI0_ACR_44_1 + offset, acr.n_44_1khz);
123 WREG32(HDMI0_ACR_48_0 + offset, HDMI0_ACR_CTS_48(acr.cts_48khz));
124 WREG32(HDMI0_ACR_48_1 + offset, acr.n_48khz);
128 * build a HDMI Video Info Frame
130 static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
131 void *buffer, size_t size)
133 struct drm_device *dev = encoder->dev;
134 struct radeon_device *rdev = dev->dev_private;
135 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
136 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
137 uint32_t offset = dig->afmt->offset;
138 uint8_t *frame = (uint8_t*)buffer + 3;
140 /* Our header values (type, version, length) should be alright, Intel
141 * is using the same. Checksum function also seems to be OK, it works
142 * fine for audio infoframe. However calculated value is always lower
143 * by 2 in comparison to fglrx. It breaks displaying anything in case
144 * of TVs that strictly check the checksum. Hack it manually here to
145 * workaround this issue. */
148 WREG32(HDMI0_AVI_INFO0 + offset,
149 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
150 WREG32(HDMI0_AVI_INFO1 + offset,
151 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
152 WREG32(HDMI0_AVI_INFO2 + offset,
153 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
154 WREG32(HDMI0_AVI_INFO3 + offset,
155 frame[0xC] | (frame[0xD] << 8));
159 * build a Audio Info Frame
161 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
162 const void *buffer, size_t size)
164 struct drm_device *dev = encoder->dev;
165 struct radeon_device *rdev = dev->dev_private;
166 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
167 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
168 uint32_t offset = dig->afmt->offset;
169 const u8 *frame = (const u8*)buffer + 3;
171 WREG32(HDMI0_AUDIO_INFO0 + offset,
172 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
173 WREG32(HDMI0_AUDIO_INFO1 + offset,
174 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
178 * test if audio buffer is filled enough to start playing
180 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
182 struct drm_device *dev = encoder->dev;
183 struct radeon_device *rdev = dev->dev_private;
184 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
185 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
186 uint32_t offset = dig->afmt->offset;
188 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
192 * have buffer status changed since last call?
194 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
196 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
197 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
200 if (!dig->afmt || !dig->afmt->enabled)
203 status = r600_hdmi_is_audio_buffer_filled(encoder);
204 result = dig->afmt->last_buffer_filled_status != status;
205 dig->afmt->last_buffer_filled_status = status;
211 * write the audio workaround status to the hardware
213 static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
215 struct drm_device *dev = encoder->dev;
216 struct radeon_device *rdev = dev->dev_private;
217 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
218 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
219 uint32_t offset = dig->afmt->offset;
220 bool hdmi_audio_workaround = false; /* FIXME */
223 if (!hdmi_audio_workaround ||
224 r600_hdmi_is_audio_buffer_filled(encoder))
225 value = 0; /* disable workaround */
227 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
228 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
229 value, ~HDMI0_AUDIO_TEST_EN);
232 void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
234 struct drm_device *dev = encoder->dev;
235 struct radeon_device *rdev = dev->dev_private;
236 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
237 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
238 u32 base_rate = 24000;
240 if (!dig || !dig->afmt)
243 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
244 * doesn't matter which one you use. Just use the first one.
246 /* XXX two dtos; generally use dto0 for hdmi */
247 /* Express [24MHz / target pixel clock] as an exact rational
248 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
249 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
251 if (ASIC_IS_DCE3(rdev)) {
252 /* according to the reg specs, this should DCE3.2 only, but in
253 * practice it seems to cover DCE3.0 as well.
255 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
256 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
257 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
259 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
260 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate / 10) |
261 AUDIO_DTO_MODULE(clock / 10));
266 * update the info frames with the data from the current display mode
268 void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
270 struct drm_device *dev = encoder->dev;
271 struct radeon_device *rdev = dev->dev_private;
272 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
273 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
274 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
275 struct hdmi_avi_infoframe frame;
279 /* Silent, r600_hdmi_enable will raise WARN for us */
280 if (!dig->afmt->enabled)
282 offset = dig->afmt->offset;
284 r600_audio_set_dto(encoder, mode->clock);
286 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
287 HDMI0_NULL_SEND); /* send null packets when required */
289 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
291 if (ASIC_IS_DCE32(rdev)) {
292 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
293 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
294 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
295 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
296 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
297 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
299 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
300 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
301 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
302 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
303 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
306 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
307 HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
308 HDMI0_ACR_SOURCE); /* select SW CTS value */
310 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
311 HDMI0_NULL_SEND | /* send null packets when required */
312 HDMI0_GC_SEND | /* send general control packets */
313 HDMI0_GC_CONT); /* send general control packets every frame */
315 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
316 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
317 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
318 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
319 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
320 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
322 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
323 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
324 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
326 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
328 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
330 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
334 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
336 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
340 r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
341 r600_hdmi_update_ACR(encoder, mode->clock);
343 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
344 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
345 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
346 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
347 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
349 r600_hdmi_audio_workaround(encoder);
353 * update settings with current parameters from audio engine
355 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
357 struct drm_device *dev = encoder->dev;
358 struct radeon_device *rdev = dev->dev_private;
359 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
360 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
361 struct r600_audio audio = r600_audio_status(rdev);
362 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
363 struct hdmi_audio_infoframe frame;
368 if (!dig->afmt || !dig->afmt->enabled)
370 offset = dig->afmt->offset;
372 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
373 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
374 audio.channels, audio.rate, audio.bits_per_sample);
375 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
376 (int)audio.status_bits, (int)audio.category_code);
379 if (audio.status_bits & AUDIO_STATUS_PROFESSIONAL)
381 if (audio.status_bits & AUDIO_STATUS_NONAUDIO)
383 if (audio.status_bits & AUDIO_STATUS_COPYRIGHT)
385 if (audio.status_bits & AUDIO_STATUS_EMPHASIS)
388 iec |= HDMI0_60958_CS_CATEGORY_CODE(audio.category_code);
390 switch (audio.rate) {
392 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x3);
395 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x0);
398 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x2);
401 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0x8);
404 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xa);
407 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xc);
410 iec |= HDMI0_60958_CS_SAMPLING_FREQUENCY(0xe);
414 WREG32(HDMI0_60958_0 + offset, iec);
417 switch (audio.bits_per_sample) {
419 iec |= HDMI0_60958_CS_WORD_LENGTH(0x2);
422 iec |= HDMI0_60958_CS_WORD_LENGTH(0x3);
425 iec |= HDMI0_60958_CS_WORD_LENGTH(0xb);
428 if (audio.status_bits & AUDIO_STATUS_V)
430 WREG32_P(HDMI0_60958_1 + offset, iec, ~0x5000f);
432 err = hdmi_audio_infoframe_init(&frame);
434 DRM_ERROR("failed to setup audio infoframe\n");
438 frame.channels = audio.channels;
440 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
442 DRM_ERROR("failed to pack audio infoframe\n");
446 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
447 r600_hdmi_audio_workaround(encoder);
451 * enable the HDMI engine
453 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
455 struct drm_device *dev = encoder->dev;
456 struct radeon_device *rdev = dev->dev_private;
457 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
458 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
459 u32 hdmi = HDMI0_ERROR_ACK;
461 /* Silent, r600_hdmi_enable will raise WARN for us */
462 if (enable && dig->afmt->enabled)
464 if (!enable && !dig->afmt->enabled)
467 /* Older chipsets require setting HDMI and routing manually */
468 if (!ASIC_IS_DCE3(rdev)) {
470 hdmi |= HDMI0_ENABLE;
471 switch (radeon_encoder->encoder_id) {
472 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
474 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
475 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
477 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
480 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
482 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
483 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
485 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
488 case ENCODER_OBJECT_ID_INTERNAL_DDI:
490 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
491 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
493 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
496 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
498 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
501 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
502 radeon_encoder->encoder_id);
505 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
508 if (rdev->irq.installed) {
509 /* if irq is available use it */
510 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
512 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
514 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
517 dig->afmt->enabled = enable;
519 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
520 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);