2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
39 #include <sys/mplock2.h>
42 #include <vm/vm_param.h>
44 #include <vm/vm_kern.h>
45 #include <vm/vm_extern.h>
47 #include <vm/vm_map.h>
53 #include <machine/smp.h>
54 #include <machine_base/apic/apicreg.h>
55 #include <machine/atomic.h>
56 #include <machine/cpufunc.h>
57 #include <machine_base/apic/lapic.h>
58 #include <machine_base/apic/ioapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/apic/ioapic_abi.h>
69 #include <machine/intr_machdep.h> /* IPIs */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define CMOS_REG (0x70)
76 #define CMOS_DATA (0x71)
77 #define BIOS_RESET (0x0f)
78 #define BIOS_WARM (0x0a)
81 * this code MUST be enabled here and in mpboot.s.
82 * it follows the very early stages of AP boot by placing values in CMOS ram.
83 * it NORMALLY will never be needed and thus the primitive method for enabling.
86 #if defined(CHECK_POINTS)
87 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
88 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
90 #define CHECK_INIT(D); \
91 CHECK_WRITE(0x34, (D)); \
92 CHECK_WRITE(0x35, (D)); \
93 CHECK_WRITE(0x36, (D)); \
94 CHECK_WRITE(0x37, (D)); \
95 CHECK_WRITE(0x38, (D)); \
96 CHECK_WRITE(0x39, (D));
98 #define CHECK_PRINT(S); \
99 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
108 #else /* CHECK_POINTS */
110 #define CHECK_INIT(D)
111 #define CHECK_PRINT(S)
113 #endif /* CHECK_POINTS */
116 * Values to send to the POST hardware.
118 #define MP_BOOTADDRESS_POST 0x10
119 #define MP_PROBE_POST 0x11
120 #define MPTABLE_PASS1_POST 0x12
122 #define MP_START_POST 0x13
123 #define MP_ENABLE_POST 0x14
124 #define MPTABLE_PASS2_POST 0x15
126 #define START_ALL_APS_POST 0x16
127 #define INSTALL_AP_TRAMP_POST 0x17
128 #define START_AP_POST 0x18
130 #define MP_ANNOUNCE_POST 0x19
132 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
133 int current_postcode;
135 /** XXX FIXME: what system files declare these??? */
136 extern struct region_descriptor r_gdt, r_idt;
138 int mp_naps; /* # of Applications processors */
142 extern int64_t tsc_offsets[];
144 #ifdef SMP /* APIC-IO */
145 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
148 /* AP uses this during bootstrap. Do not staticize. */
152 struct pcb stoppcbs[MAXCPU];
154 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
157 * Local data and functions.
160 static u_int boot_address;
161 static int mp_finish;
162 static int mp_finish_lapic;
164 static void mp_enable(u_int boot_addr);
166 static int start_all_aps(u_int boot_addr);
168 static void install_ap_tramp(u_int boot_addr);
170 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
171 static int smitest(void);
173 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
174 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
175 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
176 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
177 static u_int bootMP_size;
183 * Calculate usable address in base memory for AP trampoline code.
186 mp_bootaddress(u_int basemem)
188 POSTCODE(MP_BOOTADDRESS_POST);
190 base_memory = basemem;
192 bootMP_size = mptramp_end - mptramp_start;
193 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
194 if (((basemem * 1024) - boot_address) < bootMP_size)
195 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
196 /* 3 levels of page table pages */
197 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
199 return mptramp_pagetables;
203 * Startup the SMP processors.
208 POSTCODE(MP_START_POST);
209 mp_enable(boot_address);
214 * Print various information about the SMP system hardware and setup.
221 POSTCODE(MP_ANNOUNCE_POST);
223 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
224 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
225 for (x = 1; x <= mp_naps; ++x)
226 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
229 kprintf(" Warning: APIC I/O disabled\n");
233 * AP cpu's call this to sync up protected mode.
235 * WARNING! %gs is not set up on entry. This routine sets up %gs.
241 int x, myid = bootAP;
243 struct mdglobaldata *md;
244 struct privatespace *ps;
246 ps = &CPU_prvspace[myid];
248 gdt_segs[GPROC0_SEL].ssd_base =
249 (long) &ps->mdglobaldata.gd_common_tss;
250 ps->mdglobaldata.mi.gd_prvspace = ps;
252 /* We fill the 32-bit segment descriptors */
253 for (x = 0; x < NGDT; x++) {
254 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
255 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
257 /* And now a 64-bit one */
258 ssdtosyssd(&gdt_segs[GPROC0_SEL],
259 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
261 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
262 r_gdt.rd_base = (long) &gdt[myid * NGDT];
263 lgdt(&r_gdt); /* does magic intra-segment return */
265 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
266 wrmsr(MSR_FSBASE, 0); /* User value */
267 wrmsr(MSR_GSBASE, (u_int64_t)ps);
268 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
274 mdcpu->gd_currentldt = _default_ldt;
277 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
278 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
280 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
282 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
284 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
286 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
287 md->gd_common_tssd = *md->gd_tss_gdt;
289 /* double fault stack */
290 md->gd_common_tss.tss_ist1 =
291 (long)&md->mi.gd_prvspace->idlestack[
292 sizeof(md->mi.gd_prvspace->idlestack)];
297 * Set to a known state:
298 * Set by mpboot.s: CR0_PG, CR0_PE
299 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
302 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
305 /* Set up the fast syscall stuff */
306 msr = rdmsr(MSR_EFER) | EFER_SCE;
307 wrmsr(MSR_EFER, msr);
308 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
309 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
310 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
311 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
312 wrmsr(MSR_STAR, msr);
313 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
315 pmap_set_opt(); /* PSE/4MB pages, etc */
317 /* Initialize the PAT MSR. */
321 /* set up CPU registers and state */
324 /* set up SSE/NX registers */
327 /* set up FPU state on the AP */
328 npxinit(__INITIAL_NPXCW__);
330 /* disable the APIC, just to be SURE */
331 lapic->svr &= ~APIC_SVR_ENABLE;
334 /*******************************************************************
335 * local functions and data
339 * start the SMP system
342 mp_enable(u_int boot_addr)
344 POSTCODE(MP_ENABLE_POST);
348 /* Initialize BSP's local APIC */
351 /* start each Application Processor */
352 start_all_aps(boot_addr);
358 MachIntrABI.finalize();
362 * start each AP in our list
365 start_all_aps(u_int boot_addr)
367 vm_offset_t va = boot_address + KERNBASE;
368 u_int64_t *pt4, *pt3, *pt2;
375 u_long mpbioswarmvec;
376 struct mdglobaldata *gd;
377 struct privatespace *ps;
379 POSTCODE(START_ALL_APS_POST);
381 /* install the AP 1st level boot code */
382 pmap_kenter(va, boot_address);
383 cpu_invlpg((void *)va); /* JG XXX */
384 bcopy(mptramp_start, (void *)va, bootMP_size);
386 /* Locate the page tables, they'll be below the trampoline */
387 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
388 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
389 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
391 /* Create the initial 1GB replicated page tables */
392 for (i = 0; i < 512; i++) {
393 /* Each slot of the level 4 pages points to the same level 3 page */
394 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
395 pt4[i] |= PG_V | PG_RW | PG_U;
397 /* Each slot of the level 3 pages points to the same level 2 page */
398 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
399 pt3[i] |= PG_V | PG_RW | PG_U;
401 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
402 pt2[i] = i * (2 * 1024 * 1024);
403 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
406 /* save the current value of the warm-start vector */
407 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
408 outb(CMOS_REG, BIOS_RESET);
409 mpbiosreason = inb(CMOS_DATA);
411 /* setup a vector to our boot code */
412 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
413 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
414 outb(CMOS_REG, BIOS_RESET);
415 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
418 * If we have a TSC we can figure out the SMI interrupt rate.
419 * The SMI does not necessarily use a constant rate. Spend
420 * up to 250ms trying to figure it out.
423 if (cpu_feature & CPUID_TSC) {
424 set_apic_timer(275000);
425 smilast = read_apic_timer();
426 for (x = 0; x < 20 && read_apic_timer(); ++x) {
427 smicount = smitest();
428 if (smibest == 0 || smilast - smicount < smibest)
429 smibest = smilast - smicount;
432 if (smibest > 250000)
435 smibest = smibest * (int64_t)1000000 /
436 get_apic_timer_frequency();
440 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
441 1000000 / smibest, smibest);
444 for (x = 1; x <= mp_naps; ++x) {
446 /* This is a bit verbose, it will go away soon. */
448 /* first page of AP's private space */
449 pg = x * x86_64_btop(sizeof(struct privatespace));
451 /* allocate new private data page(s) */
452 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
453 MDGLOBALDATA_BASEALLOC_SIZE);
455 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
456 bzero(gd, sizeof(*gd));
457 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
459 /* prime data page for it to use */
460 mi_gdinit(&gd->mi, x);
462 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
463 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
465 /* setup a vector to our boot code */
466 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
467 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
468 outb(CMOS_REG, BIOS_RESET);
469 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
472 * Setup the AP boot stack
474 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
477 /* attempt to start the Application Processor */
478 CHECK_INIT(99); /* setup checkpoints */
479 if (!start_ap(gd, boot_addr, smibest)) {
480 kprintf("\nAP #%d (PHY# %d) failed!\n",
481 x, CPUID_TO_APICID(x));
482 CHECK_PRINT("trace"); /* show checkpoints */
483 /* better panic as the AP may be running loose */
484 kprintf("panic y/n? [y] ");
488 CHECK_PRINT("trace"); /* show checkpoints */
491 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
494 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
495 for (shift = 0; (1 << shift) <= ncpus; ++shift)
498 ncpus2_shift = shift;
500 ncpus2_mask = ncpus2 - 1;
502 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
503 if ((1 << shift) < ncpus)
505 ncpus_fit = 1 << shift;
506 ncpus_fit_mask = ncpus_fit - 1;
508 /* build our map of 'other' CPUs */
509 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
510 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
511 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
513 /* restore the warmstart vector */
514 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
515 outb(CMOS_REG, BIOS_RESET);
516 outb(CMOS_DATA, mpbiosreason);
519 * NOTE! The idlestack for the BSP was setup by locore. Finish
520 * up, clean out the P==V mapping we did earlier.
525 * Wait all APs to finish initializing LAPIC
529 kprintf("SMP: Waiting APs LAPIC initialization\n");
530 if (cpu_feature & CPUID_TSC)
531 tsc0_offset = rdtsc();
534 while (smp_lapic_mask != smp_startup_mask) {
536 if (cpu_feature & CPUID_TSC)
537 tsc0_offset = rdtsc();
539 while (try_mplock() == 0)
542 /* number of APs actually started */
548 * load the 1st level AP boot code into base memory.
551 /* targets for relocation */
552 extern void bigJump(void);
553 extern void bootCodeSeg(void);
554 extern void bootDataSeg(void);
555 extern void MPentry(void);
557 extern u_int mp_gdtbase;
562 install_ap_tramp(u_int boot_addr)
565 int size = *(int *) ((u_long) & bootMP_size);
566 u_char *src = (u_char *) ((u_long) bootMP);
567 u_char *dst = (u_char *) boot_addr + KERNBASE;
568 u_int boot_base = (u_int) bootMP;
573 POSTCODE(INSTALL_AP_TRAMP_POST);
575 for (x = 0; x < size; ++x)
579 * modify addresses in code we just moved to basemem. unfortunately we
580 * need fairly detailed info about mpboot.s for this to work. changes
581 * to mpboot.s might require changes here.
584 /* boot code is located in KERNEL space */
585 dst = (u_char *) boot_addr + KERNBASE;
587 /* modify the lgdt arg */
588 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
589 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
591 /* modify the ljmp target for MPentry() */
592 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
593 *dst32 = ((u_int) MPentry - KERNBASE);
595 /* modify the target for boot code segment */
596 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
597 dst8 = (u_int8_t *) (dst16 + 1);
598 *dst16 = (u_int) boot_addr & 0xffff;
599 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
601 /* modify the target for boot data segment */
602 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
603 dst8 = (u_int8_t *) (dst16 + 1);
604 *dst16 = (u_int) boot_addr & 0xffff;
605 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
611 * This function starts the AP (application processor) identified
612 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
613 * to accomplish this. This is necessary because of the nuances
614 * of the different hardware we might encounter. It ain't pretty,
615 * but it seems to work.
617 * NOTE: eventually an AP gets to ap_init(), which is called just
618 * before the AP goes into the LWKT scheduler's idle loop.
621 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
625 u_long icr_lo, icr_hi;
627 POSTCODE(START_AP_POST);
629 /* get the PHYSICAL APIC ID# */
630 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
632 /* calculate the vector */
633 vector = (boot_addr >> 12) & 0xff;
635 /* We don't want anything interfering */
638 /* Make sure the target cpu sees everything */
642 * Try to detect when a SMI has occurred, wait up to 200ms.
644 * If a SMI occurs during an AP reset but before we issue
645 * the STARTUP command, the AP may brick. To work around
646 * this problem we hold off doing the AP startup until
647 * after we have detected the SMI. Hopefully another SMI
648 * will not occur before we finish the AP startup.
650 * Retries don't seem to help. SMIs have a window of opportunity
651 * and if USB->legacy keyboard emulation is enabled in the BIOS
652 * the interrupt rate can be quite high.
654 * NOTE: Don't worry about the L1 cache load, it might bloat
655 * ldelta a little but ndelta will be so huge when the SMI
656 * occurs the detection logic will still work fine.
659 set_apic_timer(200000);
664 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
665 * and running the target CPU. OR this INIT IPI might be latched (P5
666 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
669 * see apic/apicreg.h for icr bit definitions.
671 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
675 * Setup the address for the target AP. We can setup
676 * icr_hi once and then just trigger operations with
679 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
680 icr_hi |= (physical_cpu << 24);
681 icr_lo = lapic->icr_lo & 0xfff00000;
682 lapic->icr_hi = icr_hi;
685 * Do an INIT IPI: assert RESET
687 * Use edge triggered mode to assert INIT
689 lapic->icr_lo = icr_lo | 0x00004500;
690 while (lapic->icr_lo & APIC_DELSTAT_MASK)
694 * The spec calls for a 10ms delay but we may have to use a
695 * MUCH lower delay to avoid bricking an AP due to a fast SMI
696 * interrupt. We have other loops here too and dividing by 2
697 * doesn't seem to be enough even after subtracting 350us,
700 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
701 * interrupt was detected we use the full 10ms.
705 else if (smibest < 150 * 4 + 350)
707 else if ((smibest - 350) / 4 < 10000)
708 u_sleep((smibest - 350) / 4);
713 * Do an INIT IPI: deassert RESET
715 * Use level triggered mode to deassert. It is unclear
716 * why we need to do this.
718 lapic->icr_lo = icr_lo | 0x00008500;
719 while (lapic->icr_lo & APIC_DELSTAT_MASK)
721 u_sleep(150); /* wait 150us */
724 * Next we do a STARTUP IPI: the previous INIT IPI might still be
725 * latched, (P5 bug) this 1st STARTUP would then terminate
726 * immediately, and the previously started INIT IPI would continue. OR
727 * the previous INIT IPI has already run. and this STARTUP IPI will
728 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
731 lapic->icr_lo = icr_lo | 0x00000600 | vector;
732 while (lapic->icr_lo & APIC_DELSTAT_MASK)
734 u_sleep(200); /* wait ~200uS */
737 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
738 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
739 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
740 * recognized after hardware RESET or INIT IPI.
742 lapic->icr_lo = icr_lo | 0x00000600 | vector;
743 while (lapic->icr_lo & APIC_DELSTAT_MASK)
746 /* Resume normal operation */
749 /* wait for it to start, see ap_init() */
750 set_apic_timer(5000000);/* == 5 seconds */
751 while (read_apic_timer()) {
752 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
753 return 1; /* return SUCCESS */
756 return 0; /* return FAILURE */
771 while (read_apic_timer()) {
773 for (count = 0; count < 100; ++count)
774 ntsc = rdtsc(); /* force loop to occur */
776 ndelta = ntsc - ltsc;
779 if (ndelta > ldelta * 2)
782 ldelta = ntsc - ltsc;
785 return(read_apic_timer());
789 * Synchronously flush the TLB on all other CPU's. The current cpu's
790 * TLB is not flushed. If the caller wishes to flush the current cpu's
791 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
793 * NOTE: If for some reason we were unable to start all cpus we cannot
794 * safely use broadcast IPIs.
797 static cpumask_t smp_invltlb_req;
799 #define SMP_INVLTLB_DEBUG
805 struct mdglobaldata *md = mdcpu;
806 #ifdef SMP_INVLTLB_DEBUG
811 crit_enter_gd(&md->mi);
812 md->gd_invltlb_ret = 0;
813 ++md->mi.gd_cnt.v_smpinvltlb;
814 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
815 #ifdef SMP_INVLTLB_DEBUG
818 if (smp_startup_mask == smp_active_mask) {
819 all_but_self_ipi(XINVLTLB_OFFSET);
821 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
822 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
825 #ifdef SMP_INVLTLB_DEBUG
827 kprintf("smp_invltlb: ipi sent\n");
829 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
830 (smp_active_mask & ~md->mi.gd_cpumask)) {
833 #ifdef SMP_INVLTLB_DEBUG
835 if (++count == 400000000) {
837 kprintf("smp_invltlb: endless loop %08lx %08lx, "
838 "rflags %016jx retry",
839 (long)md->gd_invltlb_ret,
840 (long)smp_invltlb_req,
841 (intmax_t)read_rflags());
842 __asm __volatile ("sti");
847 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
852 kprintf("bcpu %d\n", bcpu);
853 xgd = globaldata_find(bcpu);
854 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
857 Debugger("giving up");
863 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
864 crit_exit_gd(&md->mi);
871 * Called from Xinvltlb assembly with interrupts disabled. We didn't
872 * bother to bump the critical section count or nested interrupt count
873 * so only do very low level operations here.
876 smp_invltlb_intr(void)
878 struct mdglobaldata *md = mdcpu;
879 struct mdglobaldata *omd;
884 mask = smp_invltlb_req;
887 cpu = BSFCPUMASK(mask);
888 mask &= ~CPUMASK(cpu);
889 omd = (struct mdglobaldata *)globaldata_find(cpu);
890 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
897 * When called the executing CPU will send an IPI to all other CPUs
898 * requesting that they halt execution.
900 * Usually (but not necessarily) called with 'other_cpus' as its arg.
902 * - Signals all CPUs in map to stop.
903 * - Waits for each to stop.
910 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
911 * from executing at same time.
914 stop_cpus(cpumask_t map)
916 map &= smp_active_mask;
918 /* send the Xcpustop IPI to all CPUs in map */
919 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
921 while ((stopped_cpus & map) != map)
929 * Called by a CPU to restart stopped CPUs.
931 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
933 * - Signals all CPUs in map to restart.
934 * - Waits for each to restart.
942 restart_cpus(cpumask_t map)
944 /* signal other cpus to restart */
945 started_cpus = map & smp_active_mask;
947 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
954 * This is called once the mpboot code has gotten us properly relocated
955 * and the MMU turned on, etc. ap_init() is actually the idle thread,
956 * and when it returns the scheduler will call the real cpu_idle() main
957 * loop for the idlethread. Interrupts are disabled on entry and should
958 * remain disabled at return.
966 * Adjust smp_startup_mask to signal the BSP that we have started
967 * up successfully. Note that we do not yet hold the BGL. The BSP
968 * is waiting for our signal.
970 * We can't set our bit in smp_active_mask yet because we are holding
971 * interrupts physically disabled and remote cpus could deadlock
972 * trying to send us an IPI.
974 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
978 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
979 * non-zero, then get the MP lock.
981 * Note: We are in a critical section.
983 * Note: we are the idle thread, we can only spin.
985 * Note: The load fence is memory volatile and prevents the compiler
986 * from improperly caching mp_finish_lapic, and the cpu from improperly
989 while (mp_finish_lapic == 0)
991 while (try_mplock() == 0)
994 if (cpu_feature & CPUID_TSC) {
996 * The BSP is constantly updating tsc0_offset, figure out
997 * the relative difference to synchronize ktrdump.
999 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1002 /* BSP may have changed PTD while we're waiting for the lock */
1005 /* Build our map of 'other' CPUs. */
1006 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1008 /* A quick check from sanity claus */
1009 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
1010 if (mycpu->gd_cpuid != cpu_id) {
1011 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
1012 kprintf("SMP: actual cpuid = %d lapicid %d\n",
1013 cpu_id, (lapic->id & 0xff000000) >> 24);
1015 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1017 panic("cpuid mismatch! boom!!");
1020 /* Initialize AP's local APIC for irq's */
1023 /* LAPIC initialization is done */
1024 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1027 /* Let BSP move onto the next initialization stage */
1031 * Interlock for finalization. Wait until mp_finish is non-zero,
1032 * then get the MP lock.
1034 * Note: We are in a critical section.
1036 * Note: we are the idle thread, we can only spin.
1038 * Note: The load fence is memory volatile and prevents the compiler
1039 * from improperly caching mp_finish, and the cpu from improperly
1042 while (mp_finish == 0)
1044 while (try_mplock() == 0)
1047 /* BSP may have changed PTD while we're waiting for the lock */
1050 /* Set memory range attributes for this CPU to match the BSP */
1051 mem_range_AP_init();
1054 * Once we go active we must process any IPIQ messages that may
1055 * have been queued, because no actual IPI will occur until we
1056 * set our bit in the smp_active_mask. If we don't the IPI
1057 * message interlock could be left set which would also prevent
1060 * The idle loop doesn't expect the BGL to be held and while
1061 * lwkt_switch() normally cleans things up this is a special case
1062 * because we returning almost directly into the idle loop.
1064 * The idle thread is never placed on the runq, make sure
1065 * nothing we've done put it there.
1067 KKASSERT(get_mplock_count(curthread) == 1);
1068 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1071 * Enable interrupts here. idle_restore will also do it, but
1072 * doing it here lets us clean up any strays that got posted to
1073 * the CPU during the AP boot while we are still in a critical
1076 __asm __volatile("sti; pause; pause"::);
1077 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1079 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1080 lwkt_process_ipiq();
1083 * Releasing the mp lock lets the BSP finish up the SMP init
1086 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1090 * Get SMP fully working before we start initializing devices.
1098 kprintf("Finish MP startup\n");
1100 while (smp_active_mask != smp_startup_mask)
1102 while (try_mplock() == 0)
1105 kprintf("Active CPU Mask: %016jx\n",
1106 (uintmax_t)smp_active_mask);
1110 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1113 cpu_send_ipiq(int dcpu)
1115 if (CPUMASK(dcpu) & smp_active_mask)
1116 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1119 #if 0 /* single_apic_ipi_passive() not working yet */
1121 * Returns 0 on failure, 1 on success
1124 cpu_send_ipiq_passive(int dcpu)
1127 if (CPUMASK(dcpu) & smp_active_mask) {
1128 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1129 APIC_DELMODE_FIXED);