2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/ioapic_abi.h>
60 #include <machine_base/apic/lapic.h>
61 #include <machine_base/apic/ioapic.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
69 #include <machine/md_var.h> /* setidt() */
70 #include <machine_base/icu/icu.h> /* IPIs */
71 #include <machine/intr_machdep.h> /* IPIs */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
83 * this code MUST be enabled here and in mpboot.s.
84 * it follows the very early stages of AP boot by placing values in CMOS ram.
85 * it NORMALLY will never be needed and thus the primitive method for enabling.
88 #if defined(CHECK_POINTS)
89 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
90 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
92 #define CHECK_INIT(D); \
93 CHECK_WRITE(0x34, (D)); \
94 CHECK_WRITE(0x35, (D)); \
95 CHECK_WRITE(0x36, (D)); \
96 CHECK_WRITE(0x37, (D)); \
97 CHECK_WRITE(0x38, (D)); \
98 CHECK_WRITE(0x39, (D));
100 #define CHECK_PRINT(S); \
101 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
110 #else /* CHECK_POINTS */
112 #define CHECK_INIT(D)
113 #define CHECK_PRINT(S)
115 #endif /* CHECK_POINTS */
118 * Values to send to the POST hardware.
120 #define MP_BOOTADDRESS_POST 0x10
121 #define MP_PROBE_POST 0x11
122 #define MPTABLE_PASS1_POST 0x12
124 #define MP_START_POST 0x13
125 #define MP_ENABLE_POST 0x14
126 #define MPTABLE_PASS2_POST 0x15
128 #define START_ALL_APS_POST 0x16
129 #define INSTALL_AP_TRAMP_POST 0x17
130 #define START_AP_POST 0x18
132 #define MP_ANNOUNCE_POST 0x19
134 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
135 int current_postcode;
137 /** XXX FIXME: what system files declare these??? */
138 extern struct region_descriptor r_gdt, r_idt;
140 int mp_naps; /* # of Applications processors */
144 extern int64_t tsc_offsets[];
146 #ifdef SMP /* APIC-IO */
147 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
151 * APIC ID logical/physical mapping structures.
152 * We oversize these to simplify boot-time config.
154 int cpu_num_to_apic_id[NAPICID];
155 int apic_id_to_logical[NAPICID];
157 /* AP uses this during bootstrap. Do not staticize. */
161 /* Hotwire a 0->4MB V==P mapping */
162 extern pt_entry_t *KPTphys;
165 * SMP page table page. Setup by locore to point to a page table
166 * page from which we allocate per-cpu privatespace areas io_apics,
169 extern pt_entry_t *SMPpt;
171 struct pcb stoppcbs[MAXCPU];
174 * Local data and functions.
177 static u_int boot_address;
178 static int mp_finish;
179 static int mp_finish_lapic;
181 static void mp_enable(u_int boot_addr);
183 static int start_all_aps(u_int boot_addr);
184 static void install_ap_tramp(u_int boot_addr);
185 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
186 static int smitest(void);
188 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
189 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
190 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
191 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
197 * Calculate usable address in base memory for AP trampoline code.
200 mp_bootaddress(u_int basemem)
202 POSTCODE(MP_BOOTADDRESS_POST);
204 base_memory = basemem;
206 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
207 if ((base_memory - boot_address) < bootMP_size)
208 boot_address -= 4096; /* not enough, lower by 4k */
214 * Startup the SMP processors.
219 POSTCODE(MP_START_POST);
220 mp_enable(boot_address);
225 * Print various information about the SMP system hardware and setup.
232 POSTCODE(MP_ANNOUNCE_POST);
234 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
235 kprintf(" cpu0 (BSP): apic id: %2d\n", CPU_TO_ID(0));
236 for (x = 1; x <= mp_naps; ++x)
237 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPU_TO_ID(x));
240 kprintf(" Warning: APIC I/O disabled\n");
244 * AP cpu's call this to sync up protected mode.
246 * WARNING! We must ensure that the cpu is sufficiently initialized to
247 * be able to use to the FP for our optimized bzero/bcopy code before
248 * we enter more mainstream C code.
250 * WARNING! %fs is not set up on entry. This routine sets up %fs.
256 int x, myid = bootAP;
258 struct mdglobaldata *md;
259 struct privatespace *ps;
261 ps = &CPU_prvspace[myid];
263 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
264 gdt_segs[GPROC0_SEL].ssd_base =
265 (int) &ps->mdglobaldata.gd_common_tss;
266 ps->mdglobaldata.mi.gd_prvspace = ps;
268 for (x = 0; x < NGDT; x++) {
269 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
272 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
273 r_gdt.rd_base = (int) &gdt[myid * NGDT];
274 lgdt(&r_gdt); /* does magic intra-segment return */
279 mdcpu->gd_currentldt = _default_ldt;
281 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
282 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
284 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
286 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
287 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
288 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
289 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
290 md->gd_common_tssd = *md->gd_tss_gdt;
294 * Set to a known state:
295 * Set by mpboot.s: CR0_PG, CR0_PE
296 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
299 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
301 pmap_set_opt(); /* PSE/4MB pages, etc */
303 /* set up CPU registers and state */
306 /* set up FPU state on the AP */
307 npxinit(__INITIAL_NPXCW__);
309 /* set up SSE registers */
313 /*******************************************************************
314 * local functions and data
318 * start the SMP system
321 mp_enable(u_int boot_addr)
323 POSTCODE(MP_ENABLE_POST);
327 /* Initialize BSP's local APIC */
330 /* start each Application Processor */
331 start_all_aps(boot_addr);
337 MachIntrABI.finalize();
341 mp_set_cpuids(int cpu_id, int apic_id)
343 CPU_TO_ID(cpu_id) = apic_id;
344 ID_TO_CPU(apic_id) = cpu_id;
348 ioapic_map(vm_paddr_t pa)
350 KKASSERT(pa < 0x100000000LL);
351 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
355 * start each AP in our list
358 start_all_aps(u_int boot_addr)
366 u_long mpbioswarmvec;
367 struct mdglobaldata *gd;
368 struct privatespace *ps;
372 POSTCODE(START_ALL_APS_POST);
374 /* install the AP 1st level boot code */
375 install_ap_tramp(boot_addr);
378 /* save the current value of the warm-start vector */
379 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
380 outb(CMOS_REG, BIOS_RESET);
381 mpbiosreason = inb(CMOS_DATA);
383 /* setup a vector to our boot code */
384 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
385 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
386 outb(CMOS_REG, BIOS_RESET);
387 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
390 * If we have a TSC we can figure out the SMI interrupt rate.
391 * The SMI does not necessarily use a constant rate. Spend
392 * up to 250ms trying to figure it out.
395 if (cpu_feature & CPUID_TSC) {
396 set_apic_timer(275000);
397 smilast = read_apic_timer();
398 for (x = 0; x < 20 && read_apic_timer(); ++x) {
399 smicount = smitest();
400 if (smibest == 0 || smilast - smicount < smibest)
401 smibest = smilast - smicount;
404 if (smibest > 250000)
407 smibest = smibest * (int64_t)1000000 /
408 get_apic_timer_frequency();
412 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
413 1000000 / smibest, smibest);
416 /* set up temporary P==V mapping for AP boot */
417 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
418 kptbase = (uintptr_t)(void *)KPTphys;
419 for (x = 0; x < NKPT; x++) {
420 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
421 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
426 for (x = 1; x <= mp_naps; ++x) {
428 /* This is a bit verbose, it will go away soon. */
430 /* first page of AP's private space */
431 pg = x * i386_btop(sizeof(struct privatespace));
433 /* allocate new private data page(s) */
434 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
435 MDGLOBALDATA_BASEALLOC_SIZE);
436 /* wire it into the private page table page */
437 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
438 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
439 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
441 pg += MDGLOBALDATA_BASEALLOC_PAGES;
443 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
444 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
445 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
446 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
448 /* allocate and set up an idle stack data page */
449 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
450 for (i = 0; i < UPAGES; i++) {
451 SMPpt[pg + 4 + i] = (pt_entry_t)
452 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
455 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
456 bzero(gd, sizeof(*gd));
457 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
459 /* prime data page for it to use */
460 mi_gdinit(&gd->mi, x);
462 gd->gd_CMAP1 = &SMPpt[pg + 0];
463 gd->gd_CMAP2 = &SMPpt[pg + 1];
464 gd->gd_CMAP3 = &SMPpt[pg + 2];
465 gd->gd_PMAP1 = &SMPpt[pg + 3];
466 gd->gd_CADDR1 = ps->CPAGE1;
467 gd->gd_CADDR2 = ps->CPAGE2;
468 gd->gd_CADDR3 = ps->CPAGE3;
469 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
472 * Per-cpu pmap for get_ptbase().
474 gd->gd_GDADDR1= (unsigned *)
475 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
476 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
478 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
479 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
482 * Setup the AP boot stack
484 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
487 /* attempt to start the Application Processor */
488 CHECK_INIT(99); /* setup checkpoints */
489 if (!start_ap(gd, boot_addr, smibest)) {
490 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
491 CHECK_PRINT("trace"); /* show checkpoints */
492 /* better panic as the AP may be running loose */
493 kprintf("panic y/n? [y] ");
497 CHECK_PRINT("trace"); /* show checkpoints */
500 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
503 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
504 for (shift = 0; (1 << shift) <= ncpus; ++shift)
507 ncpus2_shift = shift;
509 ncpus2_mask = ncpus2 - 1;
511 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
512 if ((1 << shift) < ncpus)
514 ncpus_fit = 1 << shift;
515 ncpus_fit_mask = ncpus_fit - 1;
517 /* build our map of 'other' CPUs */
518 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
519 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
520 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
522 /* restore the warmstart vector */
523 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
524 outb(CMOS_REG, BIOS_RESET);
525 outb(CMOS_DATA, mpbiosreason);
528 * NOTE! The idlestack for the BSP was setup by locore. Finish
529 * up, clean out the P==V mapping we did earlier.
531 for (x = 0; x < NKPT; x++)
536 * Wait all APs to finish initializing LAPIC
540 kprintf("SMP: Waiting APs LAPIC initialization\n");
541 if (cpu_feature & CPUID_TSC)
542 tsc0_offset = rdtsc();
545 while (smp_lapic_mask != smp_startup_mask) {
547 if (cpu_feature & CPUID_TSC)
548 tsc0_offset = rdtsc();
550 while (try_mplock() == 0)
553 /* number of APs actually started */
558 * load the 1st level AP boot code into base memory.
561 /* targets for relocation */
562 extern void bigJump(void);
563 extern void bootCodeSeg(void);
564 extern void bootDataSeg(void);
565 extern void MPentry(void);
567 extern u_int mp_gdtbase;
570 install_ap_tramp(u_int boot_addr)
573 int size = *(int *) ((u_long) & bootMP_size);
574 u_char *src = (u_char *) ((u_long) bootMP);
575 u_char *dst = (u_char *) boot_addr + KERNBASE;
576 u_int boot_base = (u_int) bootMP;
581 POSTCODE(INSTALL_AP_TRAMP_POST);
583 for (x = 0; x < size; ++x)
587 * modify addresses in code we just moved to basemem. unfortunately we
588 * need fairly detailed info about mpboot.s for this to work. changes
589 * to mpboot.s might require changes here.
592 /* boot code is located in KERNEL space */
593 dst = (u_char *) boot_addr + KERNBASE;
595 /* modify the lgdt arg */
596 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
597 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
599 /* modify the ljmp target for MPentry() */
600 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
601 *dst32 = ((u_int) MPentry - KERNBASE);
603 /* modify the target for boot code segment */
604 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
605 dst8 = (u_int8_t *) (dst16 + 1);
606 *dst16 = (u_int) boot_addr & 0xffff;
607 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
609 /* modify the target for boot data segment */
610 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
611 dst8 = (u_int8_t *) (dst16 + 1);
612 *dst16 = (u_int) boot_addr & 0xffff;
613 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
618 * This function starts the AP (application processor) identified
619 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
620 * to accomplish this. This is necessary because of the nuances
621 * of the different hardware we might encounter. It ain't pretty,
622 * but it seems to work.
624 * NOTE: eventually an AP gets to ap_init(), which is called just
625 * before the AP goes into the LWKT scheduler's idle loop.
628 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
632 u_long icr_lo, icr_hi;
634 POSTCODE(START_AP_POST);
636 /* get the PHYSICAL APIC ID# */
637 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
639 /* calculate the vector */
640 vector = (boot_addr >> 12) & 0xff;
642 /* We don't want anything interfering */
645 /* Make sure the target cpu sees everything */
649 * Try to detect when a SMI has occurred, wait up to 200ms.
651 * If a SMI occurs during an AP reset but before we issue
652 * the STARTUP command, the AP may brick. To work around
653 * this problem we hold off doing the AP startup until
654 * after we have detected the SMI. Hopefully another SMI
655 * will not occur before we finish the AP startup.
657 * Retries don't seem to help. SMIs have a window of opportunity
658 * and if USB->legacy keyboard emulation is enabled in the BIOS
659 * the interrupt rate can be quite high.
661 * NOTE: Don't worry about the L1 cache load, it might bloat
662 * ldelta a little but ndelta will be so huge when the SMI
663 * occurs the detection logic will still work fine.
666 set_apic_timer(200000);
671 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
672 * and running the target CPU. OR this INIT IPI might be latched (P5
673 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
676 * see apic/apicreg.h for icr bit definitions.
678 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
682 * Setup the address for the target AP. We can setup
683 * icr_hi once and then just trigger operations with
686 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
687 icr_hi |= (physical_cpu << 24);
688 icr_lo = lapic->icr_lo & 0xfff00000;
689 lapic->icr_hi = icr_hi;
692 * Do an INIT IPI: assert RESET
694 * Use edge triggered mode to assert INIT
696 lapic->icr_lo = icr_lo | 0x0000c500;
697 while (lapic->icr_lo & APIC_DELSTAT_MASK)
701 * The spec calls for a 10ms delay but we may have to use a
702 * MUCH lower delay to avoid bricking an AP due to a fast SMI
703 * interrupt. We have other loops here too and dividing by 2
704 * doesn't seem to be enough even after subtracting 350us,
707 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
708 * interrupt was detected we use the full 10ms.
712 else if (smibest < 150 * 4 + 350)
714 else if ((smibest - 350) / 4 < 10000)
715 u_sleep((smibest - 350) / 4);
720 * Do an INIT IPI: deassert RESET
722 * Use level triggered mode to deassert. It is unclear
723 * why we need to do this.
725 lapic->icr_lo = icr_lo | 0x00008500;
726 while (lapic->icr_lo & APIC_DELSTAT_MASK)
728 u_sleep(150); /* wait 150us */
731 * Next we do a STARTUP IPI: the previous INIT IPI might still be
732 * latched, (P5 bug) this 1st STARTUP would then terminate
733 * immediately, and the previously started INIT IPI would continue. OR
734 * the previous INIT IPI has already run. and this STARTUP IPI will
735 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
738 lapic->icr_lo = icr_lo | 0x00000600 | vector;
739 while (lapic->icr_lo & APIC_DELSTAT_MASK)
741 u_sleep(200); /* wait ~200uS */
744 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
745 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
746 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
747 * recognized after hardware RESET or INIT IPI.
749 lapic->icr_lo = icr_lo | 0x00000600 | vector;
750 while (lapic->icr_lo & APIC_DELSTAT_MASK)
753 /* Resume normal operation */
756 /* wait for it to start, see ap_init() */
757 set_apic_timer(5000000);/* == 5 seconds */
758 while (read_apic_timer()) {
759 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
760 return 1; /* return SUCCESS */
763 return 0; /* return FAILURE */
778 while (read_apic_timer()) {
780 for (count = 0; count < 100; ++count)
781 ntsc = rdtsc(); /* force loop to occur */
783 ndelta = ntsc - ltsc;
786 if (ndelta > ldelta * 2)
789 ldelta = ntsc - ltsc;
792 return(read_apic_timer());
796 * Lazy flush the TLB on all other CPU's. DEPRECATED.
798 * If for some reason we were unable to start all cpus we cannot safely
799 * use broadcast IPIs.
802 static cpumask_t smp_invltlb_req;
803 #define SMP_INVLTLB_DEBUG
809 struct mdglobaldata *md = mdcpu;
810 #ifdef SMP_INVLTLB_DEBUG
815 crit_enter_gd(&md->mi);
816 md->gd_invltlb_ret = 0;
817 ++md->mi.gd_cnt.v_smpinvltlb;
818 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
819 #ifdef SMP_INVLTLB_DEBUG
822 if (smp_startup_mask == smp_active_mask) {
823 all_but_self_ipi(XINVLTLB_OFFSET);
825 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
826 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
829 #ifdef SMP_INVLTLB_DEBUG
831 kprintf("smp_invltlb: ipi sent\n");
833 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
834 (smp_active_mask & ~md->mi.gd_cpumask)) {
837 #ifdef SMP_INVLTLB_DEBUG
839 if (++count == 400000000) {
841 kprintf("smp_invltlb: endless loop %08lx %08lx, "
842 "rflags %016lx retry",
843 (long)md->gd_invltlb_ret,
844 (long)smp_invltlb_req,
845 (long)read_eflags());
846 __asm __volatile ("sti");
851 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
855 kprintf("bcpu %d\n", bcpu);
856 xgd = globaldata_find(bcpu);
857 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
866 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
867 crit_exit_gd(&md->mi);
874 * Called from Xinvltlb assembly with interrupts disabled. We didn't
875 * bother to bump the critical section count or nested interrupt count
876 * so only do very low level operations here.
879 smp_invltlb_intr(void)
881 struct mdglobaldata *md = mdcpu;
882 struct mdglobaldata *omd;
886 mask = smp_invltlb_req;
890 cpu = BSFCPUMASK(mask);
891 mask &= ~CPUMASK(cpu);
892 omd = (struct mdglobaldata *)globaldata_find(cpu);
893 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
900 * When called the executing CPU will send an IPI to all other CPUs
901 * requesting that they halt execution.
903 * Usually (but not necessarily) called with 'other_cpus' as its arg.
905 * - Signals all CPUs in map to stop.
906 * - Waits for each to stop.
913 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
914 * from executing at same time.
917 stop_cpus(cpumask_t map)
919 map &= smp_active_mask;
921 /* send the Xcpustop IPI to all CPUs in map */
922 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
924 while ((stopped_cpus & map) != map)
932 * Called by a CPU to restart stopped CPUs.
934 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
936 * - Signals all CPUs in map to restart.
937 * - Waits for each to restart.
945 restart_cpus(cpumask_t map)
947 /* signal other cpus to restart */
948 started_cpus = map & smp_active_mask;
950 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
957 * This is called once the mpboot code has gotten us properly relocated
958 * and the MMU turned on, etc. ap_init() is actually the idle thread,
959 * and when it returns the scheduler will call the real cpu_idle() main
960 * loop for the idlethread. Interrupts are disabled on entry and should
961 * remain disabled at return.
969 * Adjust smp_startup_mask to signal the BSP that we have started
970 * up successfully. Note that we do not yet hold the BGL. The BSP
971 * is waiting for our signal.
973 * We can't set our bit in smp_active_mask yet because we are holding
974 * interrupts physically disabled and remote cpus could deadlock
975 * trying to send us an IPI.
977 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
981 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
982 * non-zero, then get the MP lock.
984 * Note: We are in a critical section.
986 * Note: we are the idle thread, we can only spin.
988 * Note: The load fence is memory volatile and prevents the compiler
989 * from improperly caching mp_finish_lapic, and the cpu from improperly
992 while (mp_finish_lapic == 0)
994 while (try_mplock() == 0)
997 if (cpu_feature & CPUID_TSC) {
999 * The BSP is constantly updating tsc0_offset, figure out
1000 * the relative difference to synchronize ktrdump.
1002 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1005 /* BSP may have changed PTD while we're waiting for the lock */
1008 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1012 /* Build our map of 'other' CPUs. */
1013 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1015 /* A quick check from sanity claus */
1016 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
1017 if (mycpu->gd_cpuid != apic_id) {
1018 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
1019 kprintf("SMP: apic_id = %d\n", apic_id);
1020 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1021 panic("cpuid mismatch! boom!!");
1024 /* Initialize AP's local APIC for irq's */
1027 /* LAPIC initialization is done */
1028 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1031 /* Let BSP move onto the next initialization stage */
1035 * Interlock for finalization. Wait until mp_finish is non-zero,
1036 * then get the MP lock.
1038 * Note: We are in a critical section.
1040 * Note: we are the idle thread, we can only spin.
1042 * Note: The load fence is memory volatile and prevents the compiler
1043 * from improperly caching mp_finish, and the cpu from improperly
1046 while (mp_finish == 0)
1048 while (try_mplock() == 0)
1051 /* BSP may have changed PTD while we're waiting for the lock */
1054 /* Set memory range attributes for this CPU to match the BSP */
1055 mem_range_AP_init();
1058 * Once we go active we must process any IPIQ messages that may
1059 * have been queued, because no actual IPI will occur until we
1060 * set our bit in the smp_active_mask. If we don't the IPI
1061 * message interlock could be left set which would also prevent
1064 * The idle loop doesn't expect the BGL to be held and while
1065 * lwkt_switch() normally cleans things up this is a special case
1066 * because we returning almost directly into the idle loop.
1068 * The idle thread is never placed on the runq, make sure
1069 * nothing we've done put it there.
1071 KKASSERT(get_mplock_count(curthread) == 1);
1072 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1075 * Enable interrupts here. idle_restore will also do it, but
1076 * doing it here lets us clean up any strays that got posted to
1077 * the CPU during the AP boot while we are still in a critical
1080 __asm __volatile("sti; pause; pause"::);
1081 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1083 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1084 lwkt_process_ipiq();
1087 * Releasing the mp lock lets the BSP finish up the SMP init
1090 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1094 * Get SMP fully working before we start initializing devices.
1102 kprintf("Finish MP startup\n");
1104 while (smp_active_mask != smp_startup_mask)
1106 while (try_mplock() == 0)
1109 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
1112 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1115 cpu_send_ipiq(int dcpu)
1117 if (CPUMASK(dcpu) & smp_active_mask)
1118 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1121 #if 0 /* single_apic_ipi_passive() not working yet */
1123 * Returns 0 on failure, 1 on success
1126 cpu_send_ipiq_passive(int dcpu)
1129 if (CPUMASK(dcpu) & smp_active_mask) {
1130 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1131 APIC_DELMODE_FIXED);