drm/radeon: Import the Radeon KMS driver from FreeBSD
authorFrançois Tigeot <ftigeot@wolfpond.org>
Tue, 8 Oct 2013 19:15:54 +0000 (21:15 +0200)
committerFrançois Tigeot <ftigeot@wolfpond.org>
Tue, 8 Oct 2013 21:05:13 +0000 (23:05 +0200)
* Credits for porting an updated version of this driver from Linux
  mainly go to Jean-Sébastien Pédron <jean-sebastien.pedron@dumbbell.fr>

* Compatibility layer for running 32-bit applications on 64-bit systems
  left out

Additional credits from the FreeBSD import message:

This driver is based on Linux 3.8 and a previous effort by kan@.

More informations about this project can be found on the FreeBSD wiki:
    https://wiki.freebsd.org/AMD_GPU

Help from: kib@, kan@
Tested by: avg@, kwm@, ray@,
Alexander Yerenkow <yerenkow@gmail.com>,
Anders Bolt-Evensen <andersbo87@me.com>,
Denis Djubajlo <stdedjub@googlemail.com>,
J.R. Oldroyd <fbsd@opal.com>,
Mikaël Urankar <mikael.urankar@gmail.com>,
Pierre-Emmanuel Pédron <pepcitron@gmail.com>,
Sam Fourman Jr. <sfourman@gmail.com>,
Wade <wade-is-great@live.com>,
(probably other I forgot...)
HW donations: kyzh, Yakaz

150 files changed:
Makefile_upgrade.inc
sys/dev/drm/ati_pcigart.c
sys/dev/drm/drm_buffer.c
sys/dev/drm/include/uapi_drm/radeon_drm.h [moved from sys/dev/drm/radeon/radeon_drm.h with 77% similarity]
sys/dev/drm/radeon/Makefile
sys/dev/drm/radeon/ObjectID.h [new file with mode: 0644]
sys/dev/drm/radeon/README [new file with mode: 0644]
sys/dev/drm/radeon/atom-bits.h [new file with mode: 0644]
sys/dev/drm/radeon/atom-names.h [new file with mode: 0644]
sys/dev/drm/radeon/atom-types.h [new file with mode: 0644]
sys/dev/drm/radeon/atom.c [new file with mode: 0644]
sys/dev/drm/radeon/atom.h [new file with mode: 0644]
sys/dev/drm/radeon/atombios.h [new file with mode: 0644]
sys/dev/drm/radeon/atombios_crtc.c [new file with mode: 0644]
sys/dev/drm/radeon/atombios_dp.c [new file with mode: 0644]
sys/dev/drm/radeon/atombios_encoders.c [new file with mode: 0644]
sys/dev/drm/radeon/atombios_i2c.c [new file with mode: 0644]
sys/dev/drm/radeon/avivod.h [new file with mode: 0644]
sys/dev/drm/radeon/cayman_blit_shaders.c [new file with mode: 0644]
sys/dev/drm/radeon/cayman_blit_shaders.h [new file with mode: 0644]
sys/dev/drm/radeon/cayman_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/evergreen.c [new file with mode: 0644]
sys/dev/drm/radeon/evergreen_blit_kms.c [new file with mode: 0644]
sys/dev/drm/radeon/evergreen_blit_shaders.c [new file with mode: 0644]
sys/dev/drm/radeon/evergreen_blit_shaders.h [new file with mode: 0644]
sys/dev/drm/radeon/evergreen_cs.c [new file with mode: 0644]
sys/dev/drm/radeon/evergreen_hdmi.c [new file with mode: 0644]
sys/dev/drm/radeon/evergreen_reg.h [new file with mode: 0644]
sys/dev/drm/radeon/evergreen_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/evergreend.h [new file with mode: 0644]
sys/dev/drm/radeon/ni.c [new file with mode: 0644]
sys/dev/drm/radeon/ni_reg.h [new file with mode: 0644]
sys/dev/drm/radeon/nid.h [new file with mode: 0644]
sys/dev/drm/radeon/r100.c [new file with mode: 0644]
sys/dev/drm/radeon/r100_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/r100_track.h [new file with mode: 0644]
sys/dev/drm/radeon/r100d.h [new file with mode: 0644]
sys/dev/drm/radeon/r200.c [new file with mode: 0644]
sys/dev/drm/radeon/r200_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/r300.c [new file with mode: 0644]
sys/dev/drm/radeon/r300_cmdbuf.c
sys/dev/drm/radeon/r300_reg.h
sys/dev/drm/radeon/r300_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/r300d.h [new file with mode: 0644]
sys/dev/drm/radeon/r420.c [new file with mode: 0644]
sys/dev/drm/radeon/r420_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/r420d.h [new file with mode: 0644]
sys/dev/drm/radeon/r500_reg.h [new file with mode: 0644]
sys/dev/drm/radeon/r520.c [new file with mode: 0644]
sys/dev/drm/radeon/r520d.h [new file with mode: 0644]
sys/dev/drm/radeon/r600.c [new file with mode: 0644]
sys/dev/drm/radeon/r600_audio.c [new file with mode: 0644]
sys/dev/drm/radeon/r600_blit.c
sys/dev/drm/radeon/r600_blit_kms.c [new file with mode: 0644]
sys/dev/drm/radeon/r600_blit_shaders.c [new file with mode: 0644]
sys/dev/drm/radeon/r600_blit_shaders.h [new file with mode: 0644]
sys/dev/drm/radeon/r600_cp.c
sys/dev/drm/radeon/r600_cp.h [new file with mode: 0644]
sys/dev/drm/radeon/r600_cs.c [new file with mode: 0644]
sys/dev/drm/radeon/r600_cs.h [new file with mode: 0644]
sys/dev/drm/radeon/r600_hdmi.c [new file with mode: 0644]
sys/dev/drm/radeon/r600_microcode.h [deleted file]
sys/dev/drm/radeon/r600_reg.h [new file with mode: 0644]
sys/dev/drm/radeon/r600_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/r600d.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_acpi.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_acpi.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_agp.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_asic.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_asic.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_atombios.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_atpx_handler.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_benchmark.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_bios.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_blit_common.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_clocks.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_combios.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_connectors.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_cp.c
sys/dev/drm/radeon/radeon_cs.c
sys/dev/drm/radeon/radeon_cursor.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_device.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_display.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_drv.c
sys/dev/drm/radeon/radeon_drv.h
sys/dev/drm/radeon/radeon_encoders.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_fb.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_fence.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_gart.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_gem.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_gem.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_i2c.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_irq.c
sys/dev/drm/radeon/radeon_irq_kms.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_irq_kms.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_kms.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_kms.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_legacy_crtc.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_legacy_encoders.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_legacy_tv.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_mem.c
sys/dev/drm/radeon/radeon_microcode.h [deleted file]
sys/dev/drm/radeon/radeon_mode.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_object.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_object.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_pm.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_prime.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_reg.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_ring.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_sa.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_semaphore.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_state.c
sys/dev/drm/radeon/radeon_test.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_trace.h [new file with mode: 0644]
sys/dev/drm/radeon/radeon_trace_points.c [new file with mode: 0644]
sys/dev/drm/radeon/radeon_ttm.c [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/cayman [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/evergreen [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/r100 [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/r200 [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/r300 [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/r420 [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/r600 [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/rn50 [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/rs600 [new file with mode: 0644]
sys/dev/drm/radeon/reg_srcs/rv515 [new file with mode: 0644]
sys/dev/drm/radeon/rn50_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/rs100d.h [new file with mode: 0644]
sys/dev/drm/radeon/rs400.c [new file with mode: 0644]
sys/dev/drm/radeon/rs400d.h [new file with mode: 0644]
sys/dev/drm/radeon/rs600.c [new file with mode: 0644]
sys/dev/drm/radeon/rs600_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/rs600d.h [new file with mode: 0644]
sys/dev/drm/radeon/rs690.c [new file with mode: 0644]
sys/dev/drm/radeon/rs690d.h [new file with mode: 0644]
sys/dev/drm/radeon/rv200d.h [new file with mode: 0644]
sys/dev/drm/radeon/rv250d.h [new file with mode: 0644]
sys/dev/drm/radeon/rv350d.h [new file with mode: 0644]
sys/dev/drm/radeon/rv515.c [new file with mode: 0644]
sys/dev/drm/radeon/rv515_reg_safe.h [new file with mode: 0644]
sys/dev/drm/radeon/rv515d.h [new file with mode: 0644]
sys/dev/drm/radeon/rv770.c [new file with mode: 0644]
sys/dev/drm/radeon/rv770d.h [new file with mode: 0644]
sys/dev/drm/radeon/si.c [new file with mode: 0644]
sys/dev/drm/radeon/si_blit_shaders.c [new file with mode: 0644]
sys/dev/drm/radeon/si_blit_shaders.h [new file with mode: 0644]
sys/dev/drm/radeon/si_reg.h [new file with mode: 0644]
sys/dev/drm/radeon/sid.h [new file with mode: 0644]
sys/dev/drm/ttm/ttm_agp_backend.c

index 3cf8a6b..e23e742 100644 (file)
@@ -2155,6 +2155,7 @@ TO_REMOVE+=/usr/share/nls/fo_FO.UTF-8
 TO_REMOVE+=/usr/share/nls/hi_IN.UTF-8
 TO_REMOVE+=/usr/share/nls/la_LN.UTF-8
 TO_REMOVE+=/usr/share/man/man9/idr_init1.9.gz
+TO_REMOVE+=/boot/kernel/radeon.ko
 
 .if ${MACHINE_ARCH} == "x86_64"
 TO_REMOVE+=/usr/sbin/stlstats
index 80d3a8b..bdd877d 100644 (file)
@@ -1,4 +1,13 @@
-/*-
+/**
+ * \file ati_pcigart.c
+ * ATI PCI GART support
+ *
+ * \author Gareth Hughes <gareth@valinux.com>
+ */
+
+/*
+ * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
+ *
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
  *
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  *
- * Authors:
- *   Gareth Hughes <gareth@valinux.com>
- *
- */
-
-/** @file ati_pcigart.c
- * Implementation of ATI's PCIGART, which provides an aperture in card virtual
- * address space with addresses remapped to system memory.
+ * $FreeBSD: head/sys/dev/drm2/ati_pcigart.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
 
 #include <drm/drmP.h>
 
-#define ATI_PCIGART_PAGE_SIZE          4096    /* PCI GART page size */
-#define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
-
-#define ATI_PCIE_WRITE 0x4
-#define ATI_PCIE_READ 0x8
-
-static void
-drm_ati_alloc_pcigart_table_cb(void *arg, bus_dma_segment_t *segs,
-                              int nsegs, int error)
-{
-       struct drm_dma_handle *dmah = arg;
-
-       if (error != 0)
-               return;
-
-       KASSERT(nsegs == 1,
-           ("drm_ati_alloc_pcigart_table_cb: bad dma segment count"));
+#define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
 
-       dmah->busaddr = segs[0].ds_addr;
-}
-
-static int
-drm_ati_alloc_pcigart_table(struct drm_device *dev,
-                           struct drm_ati_pcigart_info *gart_info)
+static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
+                                      struct drm_ati_pcigart_info *gart_info)
 {
-       struct drm_dma_handle *dmah;
-       int flags, ret;
-
-       dmah = kmalloc(sizeof(struct drm_dma_handle), DRM_MEM_DMA,
-           M_ZERO | M_NOWAIT);
-       if (dmah == NULL)
-               return ENOMEM;
-
-       DRM_UNLOCK(dev);
-       ret = bus_dma_tag_create(NULL, PAGE_SIZE, 0, /* tag, align, boundary */
-           gart_info->table_mask, BUS_SPACE_MAXADDR, /* lowaddr, highaddr */
-           NULL, NULL, /* filtfunc, filtfuncargs */
-           gart_info->table_size, 1, /* maxsize, nsegs */
-           gart_info->table_size, /* maxsegsize */
-           0, /* flags */
-           &dmah->tag);
-       if (ret != 0) {
-               kfree(dmah, DRM_MEM_DMA);
-               return ENOMEM;
-       }
-
-       flags = BUS_DMA_WAITOK | BUS_DMA_ZERO;
-
-       if (gart_info->gart_reg_if == DRM_ATI_GART_IGP)
-           flags |= BUS_DMA_NOCACHE;
-       
-       ret = bus_dmamem_alloc(dmah->tag, &dmah->vaddr, flags, &dmah->map);
-       if (ret != 0) {
-               bus_dma_tag_destroy(dmah->tag);
-               kfree(dmah, DRM_MEM_DMA);
-               return ENOMEM;
-       }
-       DRM_LOCK(dev);
-
-       ret = bus_dmamap_load(dmah->tag, dmah->map, dmah->vaddr,
-           gart_info->table_size, drm_ati_alloc_pcigart_table_cb, dmah,
-           BUS_DMA_NOWAIT);
-       if (ret != 0) {
-               bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
-               bus_dma_tag_destroy(dmah->tag);
-               kfree(dmah, DRM_MEM_DMA);
-               return ENOMEM;
-       }
-
-       gart_info->dmah = dmah;
+       gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
+                                               PAGE_SIZE, 0xFFFFFFFFUL);
+       if (gart_info->table_handle == NULL)
+               return -ENOMEM;
 
        return 0;
 }
 
-static void
-drm_ati_free_pcigart_table(struct drm_device *dev,
-                          struct drm_ati_pcigart_info *gart_info)
+static void drm_ati_free_pcigart_table(struct drm_device *dev,
+                                      struct drm_ati_pcigart_info *gart_info)
 {
-       struct drm_dma_handle *dmah = gart_info->dmah;
-
-       bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
-       bus_dma_tag_destroy(dmah->tag);
-       kfree(dmah, DRM_MEM_DMA);
-       gart_info->dmah = NULL;
+       drm_pci_free(dev, gart_info->table_handle);
+       gart_info->table_handle = NULL;
 }
 
-int
-drm_ati_pcigart_cleanup(struct drm_device *dev,
-                       struct drm_ati_pcigart_info *gart_info)
+int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 {
+       struct drm_sg_mem *entry = dev->sg;
+#ifdef __linux__
+       unsigned long pages;
+       int i;
+       int max_pages;
+#endif
+
        /* we need to support large memory configurations */
-       if (dev->sg == NULL) {
+       if (!entry) {
                DRM_ERROR("no scatter/gather memory!\n");
                return 0;
        }
 
        if (gart_info->bus_addr) {
-               if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
-                       gart_info->bus_addr = 0;
-                       if (gart_info->dmah)
-                               drm_ati_free_pcigart_table(dev, gart_info);
+#ifdef __linux__
+
+               max_pages = (gart_info->table_size / sizeof(u32));
+               pages = (entry->pages <= max_pages)
+                 ? entry->pages : max_pages;
+
+               for (i = 0; i < pages; i++) {
+                       if (!entry->busaddr[i])
+                               break;
+                       pci_unmap_page(dev->pdev, entry->busaddr[i],
+                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
                }
+#endif
+
+               if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
+                       gart_info->bus_addr = 0;
+       }
+
+       if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
+           gart_info->table_handle) {
+               drm_ati_free_pcigart_table(dev, gart_info);
        }
 
        return 1;
 }
 
-int
-drm_ati_pcigart_init(struct drm_device *dev,
-                    struct drm_ati_pcigart_info *gart_info)
+int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 {
+       struct drm_local_map *map = &gart_info->mapping;
+       struct drm_sg_mem *entry = dev->sg;
        void *address = NULL;
        unsigned long pages;
-       u32 *pci_gart, page_base;
+       u32 *pci_gart = NULL, page_base, gart_idx;
        dma_addr_t bus_address = 0;
-       dma_addr_t entry_addr;
        int i, j, ret = 0;
-       int max_pages;
+       int max_ati_pages, max_real_pages;
 
-       /* we need to support large memory configurations */
-       if (dev->sg == NULL) {
+       if (!entry) {
                DRM_ERROR("no scatter/gather memory!\n");
                goto done;
        }
@@ -161,60 +116,89 @@ drm_ati_pcigart_init(struct drm_device *dev,
        if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
                DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
 
+#ifdef __linux__
+               if (pci_set_dma_mask(dev->pdev, gart_info->table_mask)) {
+                       DRM_ERROR("fail to set dma mask to 0x%Lx\n",
+                                 (unsigned long long)gart_info->table_mask);
+                       ret = 1;
+                       goto done;
+               }
+#endif
+
                ret = drm_ati_alloc_pcigart_table(dev, gart_info);
                if (ret) {
                        DRM_ERROR("cannot allocate PCI GART page!\n");
                        goto done;
                }
 
-               address = (void *)gart_info->dmah->vaddr;
-               bus_address = gart_info->dmah->busaddr;
+               pci_gart = gart_info->table_handle->vaddr;
+               address = gart_info->table_handle->vaddr;
+               bus_address = gart_info->table_handle->busaddr;
        } else {
                address = gart_info->addr;
                bus_address = gart_info->bus_addr;
-               DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n",
-                         (unsigned int)bus_address, (unsigned long)address);
+               DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
+                         (unsigned long long)bus_address,
+                         (unsigned long)address);
        }
 
-       pci_gart = (u32 *) address;
-
-       max_pages = (gart_info->table_size / sizeof(u32));
-       pages = (dev->sg->pages <= max_pages)
-           ? dev->sg->pages : max_pages;
 
-       memset(pci_gart, 0, max_pages * sizeof(u32));
+       max_ati_pages = (gart_info->table_size / sizeof(u32));
+       max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
+       pages = (entry->pages <= max_real_pages)
+           ? entry->pages : max_real_pages;
 
-       KASSERT(PAGE_SIZE >= ATI_PCIGART_PAGE_SIZE, ("page size too small"));
+       if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
+               memset(pci_gart, 0, max_ati_pages * sizeof(u32));
+       } else {
+               memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u32));
+       }
 
+       gart_idx = 0;
        for (i = 0; i < pages; i++) {
-               entry_addr = dev->sg->busaddr[i];
+#ifdef __linux__
+               /* we need to support large memory configurations */
+               entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
+                                                0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+               if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
+                       DRM_ERROR("unable to map PCIGART pages!\n");
+                       drm_ati_pcigart_cleanup(dev, gart_info);
+                       address = NULL;
+                       bus_address = 0;
+                       goto done;
+               }
+#endif
+               page_base = (u32) entry->busaddr[i];
+
                for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
-                       page_base = (u32) entry_addr & ATI_PCIGART_PAGE_MASK;
+                       u32 val;
+
                        switch(gart_info->gart_reg_if) {
                        case DRM_ATI_GART_IGP:
-                               page_base |=
-                                   (upper_32_bits(entry_addr) & 0xff) << 4;
-                               page_base |= 0xc;
+                               val = page_base | 0xc;
                                break;
                        case DRM_ATI_GART_PCIE:
-                               page_base >>= 8;
-                               page_base |=
-                                   (upper_32_bits(entry_addr) & 0xff) << 24;
-                               page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE;
+                               val = (page_base >> 8) | 0xc;
                                break;
                        default:
                        case DRM_ATI_GART_PCI:
+                               val = page_base;
                                break;
                        }
-                       *pci_gart = cpu_to_le32(page_base);
-                       pci_gart++;
-                       entry_addr += ATI_PCIGART_PAGE_SIZE;
+                       if (gart_info->gart_table_location ==
+                           DRM_ATI_GART_MAIN)
+                               pci_gart[gart_idx] = cpu_to_le32(val);
+                       else
+                               DRM_WRITE32(map, gart_idx * sizeof(u32), val);
+                       gart_idx++;
+                       page_base += ATI_PCIGART_PAGE_SIZE;
                }
        }
-
        ret = 1;
 
-    done:
+       wbinvd();
+
+      done:
        gart_info->addr = address;
        gart_info->bus_addr = bus_address;
        return ret;
index 0cdb713..0d27e44 100644 (file)
@@ -137,9 +137,9 @@ void drm_buffer_free(struct drm_buffer *buf)
                int nr_pages = buf->size / PAGE_SIZE + 1;
                int idx;
                for (idx = 0; idx < nr_pages; ++idx)
-                       kfree(buf->data[idx], DRM_MEM_DRIVER);
+                       drm_free(buf->data[idx], DRM_MEM_DRIVER);
 
-               kfree(buf, DRM_MEM_DRIVER);
+               drm_free(buf, DRM_MEM_DRIVER);
        }
 }
 
similarity index 77%
rename from sys/dev/drm/radeon/radeon_drm.h
rename to sys/dev/drm/include/uapi_drm/radeon_drm.h
index ba6100a..7890a7e 100644 (file)
  *    Kevin E. Martin <martin@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *    Keith Whitwell <keith@tungstengraphics.com>
- * __FBSDID("$FreeBSD: src/sys/dev/drm/radeon_drm.h,v 1.18 2009/08/23 15:02:58 rnoland Exp $");
+ *
+ * $FreeBSD: head/sys/dev/drm2/radeon/radeon_drm.h 254885 2013-08-25 19:37:15Z dumbbell $
  */
 
 #ifndef __RADEON_DRM_H__
 #define __RADEON_DRM_H__
 
+#include <uapi_drm/drm.h>
+
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the X server file (radeon_sarea.h)
  */
@@ -304,7 +307,8 @@ typedef union {
 #define RADEON_INDEX_PRIM_OFFSET       20
 
 #define RADEON_SCRATCH_REG_OFFSET      32
-#define R600_SCRATCH_REG_OFFSET                256
+
+#define R600_SCRATCH_REG_OFFSET         256
 
 #define RADEON_NR_SAREA_CLIPRECTS      12
 
@@ -494,8 +498,20 @@ typedef struct {
 #define DRM_RADEON_SETPARAM   0x19
 #define DRM_RADEON_SURF_ALLOC 0x1a
 #define DRM_RADEON_SURF_FREE  0x1b
-
-#define DRM_RADEON_CS         0x26
+/* KMS ioctl */
+#define DRM_RADEON_GEM_INFO            0x1c
+#define DRM_RADEON_GEM_CREATE          0x1d
+#define DRM_RADEON_GEM_MMAP            0x1e
+#define DRM_RADEON_GEM_PREAD           0x21
+#define DRM_RADEON_GEM_PWRITE          0x22
+#define DRM_RADEON_GEM_SET_DOMAIN      0x23
+#define DRM_RADEON_GEM_WAIT_IDLE       0x24
+#define DRM_RADEON_CS                  0x26
+#define DRM_RADEON_INFO                        0x27
+#define DRM_RADEON_GEM_SET_TILING      0x28
+#define DRM_RADEON_GEM_GET_TILING      0x29
+#define DRM_RADEON_GEM_BUSY            0x2a
+#define DRM_RADEON_GEM_VA              0x2b
 
 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
@@ -524,7 +540,20 @@ typedef struct {
 #define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
 #define DRM_IOCTL_RADEON_SURF_FREE  DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
-#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
+/* KMS */
+#define DRM_IOCTL_RADEON_GEM_INFO      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
+#define DRM_IOCTL_RADEON_GEM_CREATE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
+#define DRM_IOCTL_RADEON_GEM_MMAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
+#define DRM_IOCTL_RADEON_GEM_PREAD     DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
+#define DRM_IOCTL_RADEON_GEM_PWRITE    DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
+#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN        DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
+#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
+#define DRM_IOCTL_RADEON_CS            DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
+#define DRM_IOCTL_RADEON_INFO          DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
+#define DRM_IOCTL_RADEON_GEM_SET_TILING        DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
+#define DRM_IOCTL_RADEON_GEM_GET_TILING        DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
+#define DRM_IOCTL_RADEON_GEM_BUSY      DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
+#define DRM_IOCTL_RADEON_GEM_VA                DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
 
 typedef struct drm_radeon_init {
        enum {
@@ -532,10 +561,10 @@ typedef struct drm_radeon_init {
                RADEON_CLEANUP_CP = 0x02,
                RADEON_INIT_R200_CP = 0x03,
                RADEON_INIT_R300_CP = 0x04,
-               RADEON_INIT_R600_CP = 0x05,
+               RADEON_INIT_R600_CP = 0x05
        } func;
        unsigned long sarea_priv_offset;
-       int is_pci; /* for overriding only */
+       int is_pci;
        int cp_mode;
        int gart_size;
        int ring_size;
@@ -547,8 +576,8 @@ typedef struct drm_radeon_init {
        unsigned int depth_bpp;
        unsigned int depth_offset, depth_pitch;
 
-       unsigned long fb_offset DEPRECATED;     /* deprecated, driver asks hardware */
-       unsigned long mmio_offset DEPRECATED;   /* deprecated, driver asks hardware */
+       unsigned long fb_offset;
+       unsigned long mmio_offset;
        unsigned long ring_offset;
        unsigned long ring_rptr_offset;
        unsigned long buffers_offset;
@@ -616,7 +645,7 @@ typedef struct drm_radeon_vertex2 {
 } drm_radeon_vertex2_t;
 
 /* v1.3 - obsoletes drm_radeon_vertex2
- *      - allows arbitarily large cliprect list
+ *      - allows arbitrarily large cliprect list
  *      - allows updating of tcl packet, vector and scalar state
  *      - allows memory-efficient description of state updates
  *      - allows state to be emitted without a primitive
@@ -658,9 +687,6 @@ typedef struct drm_radeon_indirect {
        int discard;
 } drm_radeon_indirect_t;
 
-#define RADEON_INDIRECT_DISCARD (1 << 0)
-#define RADEON_INDIRECT_NOFLUSH (1 << 1)
-
 /* enum for card type parameters */
 #define RADEON_CARD_PCI 0
 #define RADEON_CARD_AGP 1
@@ -739,7 +765,6 @@ typedef struct drm_radeon_setparam {
 #define RADEON_SETPARAM_FB_LOCATION    1       /* determined framebuffer location */
 #define RADEON_SETPARAM_SWITCH_TILING  2       /* enable/disable color tiling */
 #define RADEON_SETPARAM_PCIGART_LOCATION 3     /* PCI Gart Location */
-
 #define RADEON_SETPARAM_NEW_MEMMAP 4           /* Use new memory map */
 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5    /* PCI GART Table Size */
 #define RADEON_SETPARAM_VBLANK_CRTC 6           /* VBLANK CRTC */
@@ -758,23 +783,202 @@ typedef struct drm_radeon_surface_free {
 #define        DRM_RADEON_VBLANK_CRTC1         1
 #define        DRM_RADEON_VBLANK_CRTC2         2
 
-/* New interface which obsolete all previous interface.
+/*
+ * Kernel modesetting world below.
  */
-#define RADEON_CHUNK_ID_RELOCS 0x01
-#define RADEON_CHUNK_ID_IB     0x02
-#define RADEON_CHUNK_ID_OLD 0xff
+#define RADEON_GEM_DOMAIN_CPU          0x1
+#define RADEON_GEM_DOMAIN_GTT          0x2
+#define RADEON_GEM_DOMAIN_VRAM         0x4
+
+struct drm_radeon_gem_info {
+       uint64_t        gart_size;
+       uint64_t        vram_size;
+       uint64_t        vram_visible;
+};
+
+#define RADEON_GEM_NO_BACKING_STORE 1
+
+struct drm_radeon_gem_create {
+       uint64_t        size;
+       uint64_t        alignment;
+       uint32_t        handle;
+       uint32_t        initial_domain;
+       uint32_t        flags;
+};
+
+#define RADEON_TILING_MACRO                            0x1
+#define RADEON_TILING_MICRO                            0x2
+#define RADEON_TILING_SWAP_16BIT                       0x4
+#define RADEON_TILING_SWAP_32BIT                       0x8
+/* this object requires a surface when mapped - i.e. front buffer */
+#define RADEON_TILING_SURFACE                          0x10
+#define RADEON_TILING_MICRO_SQUARE                     0x20
+#define RADEON_TILING_EG_BANKW_SHIFT                   8
+#define RADEON_TILING_EG_BANKW_MASK                    0xf
+#define RADEON_TILING_EG_BANKH_SHIFT                   12
+#define RADEON_TILING_EG_BANKH_MASK                    0xf
+#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT       16
+#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK                0xf
+#define RADEON_TILING_EG_TILE_SPLIT_SHIFT              24
+#define RADEON_TILING_EG_TILE_SPLIT_MASK               0xf
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT      28
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK       0xf
+
+struct drm_radeon_gem_set_tiling {
+       uint32_t        handle;
+       uint32_t        tiling_flags;
+       uint32_t        pitch;
+};
+
+struct drm_radeon_gem_get_tiling {
+       uint32_t        handle;
+       uint32_t        tiling_flags;
+       uint32_t        pitch;
+};
+
+struct drm_radeon_gem_mmap {
+       uint32_t        handle;
+       uint32_t        pad;
+       uint64_t        offset;
+       uint64_t        size;
+       uint64_t        addr_ptr;
+};
+
+struct drm_radeon_gem_set_domain {
+       uint32_t        handle;
+       uint32_t        read_domains;
+       uint32_t        write_domain;
+};
+
+struct drm_radeon_gem_wait_idle {
+       uint32_t        handle;
+       uint32_t        pad;
+};
+
+struct drm_radeon_gem_busy {
+       uint32_t        handle;
+       uint32_t        domain;
+};
+
+struct drm_radeon_gem_pread {
+       /** Handle for the object being read. */
+       uint32_t handle;
+       uint32_t pad;
+       /** Offset into the object to read from */
+       uint64_t offset;
+       /** Length of data to read */
+       uint64_t size;
+       /** Pointer to write the data into. */
+       /* void *, but pointers are not 32/64 compatible */
+       uint64_t data_ptr;
+};
+
+struct drm_radeon_gem_pwrite {
+       /** Handle for the object being written to. */
+       uint32_t handle;
+       uint32_t pad;
+       /** Offset into the object to write to */
+       uint64_t offset;
+       /** Length of data to write */
+       uint64_t size;
+       /** Pointer to read the data from. */
+       /* void *, but pointers are not 32/64 compatible */
+       uint64_t data_ptr;
+};
+
+#define RADEON_VA_MAP                  1
+#define RADEON_VA_UNMAP                        2
+
+#define RADEON_VA_RESULT_OK            0
+#define RADEON_VA_RESULT_ERROR         1
+#define RADEON_VA_RESULT_VA_EXIST      2
+
+#define RADEON_VM_PAGE_VALID           (1 << 0)
+#define RADEON_VM_PAGE_READABLE                (1 << 1)
+#define RADEON_VM_PAGE_WRITEABLE       (1 << 2)
+#define RADEON_VM_PAGE_SYSTEM          (1 << 3)
+#define RADEON_VM_PAGE_SNOOPED         (1 << 4)
+
+struct drm_radeon_gem_va {
+       uint32_t                handle;
+       uint32_t                operation;
+       uint32_t                vm_id;
+       uint32_t                flags;
+       uint64_t                offset;
+};
+
+#define RADEON_CHUNK_ID_RELOCS 0x01
+#define RADEON_CHUNK_ID_IB     0x02
+#define RADEON_CHUNK_ID_FLAGS  0x03
+#define RADEON_CHUNK_ID_CONST_IB       0x04
+
+/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
+#define RADEON_CS_KEEP_TILING_FLAGS 0x01
+#define RADEON_CS_USE_VM            0x02
+#define RADEON_CS_END_OF_FRAME      0x04 /* a hint from userspace which CS is the last one */
+/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
+#define RADEON_CS_RING_GFX          0
+#define RADEON_CS_RING_COMPUTE      1
+#define RADEON_CS_RING_DMA          2
+/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
+/* 0 = normal, + = higher priority, - = lower priority */
 
 struct drm_radeon_cs_chunk {
-       uint32_t chunk_id;
-       uint32_t length_dw;
-       uint64_t chunk_data;
+       uint32_t                chunk_id;
+       uint32_t                length_dw;
+       uint64_t                chunk_data;
+};
+
+/* drm_radeon_cs_reloc.flags */
+
+struct drm_radeon_cs_reloc {
+       uint32_t                handle;
+       uint32_t                read_domains;
+       uint32_t                write_domain;
+       uint32_t                flags;
 };
 
 struct drm_radeon_cs {
-       uint32_t        num_chunks;
-       uint32_t        cs_id;
-       uint64_t        chunks; /* this points to uint64_t * which point to
-                                  cs chunks */
+       uint32_t                num_chunks;
+       uint32_t                cs_id;
+       /* this points to uint64_t * which point to cs chunks */
+       uint64_t                chunks;
+       /* updates to the limits after this CS ioctl */
+       uint64_t                gart_limit;
+       uint64_t                vram_limit;
+};
+
+#define RADEON_INFO_DEVICE_ID          0x00
+#define RADEON_INFO_NUM_GB_PIPES       0x01
+#define RADEON_INFO_NUM_Z_PIPES        0x02
+#define RADEON_INFO_ACCEL_WORKING      0x03
+#define RADEON_INFO_CRTC_FROM_ID       0x04
+#define RADEON_INFO_ACCEL_WORKING2     0x05
+#define RADEON_INFO_TILING_CONFIG      0x06
+#define RADEON_INFO_WANT_HYPERZ                0x07
+#define RADEON_INFO_WANT_CMASK         0x08 /* get access to CMASK on r300 */
+#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */
+#define RADEON_INFO_NUM_BACKENDS       0x0a /* DB/backends for r600+ - need for OQ */
+#define RADEON_INFO_NUM_TILE_PIPES     0x0b /* tile pipes for r600+ */
+#define RADEON_INFO_FUSION_GART_WORKING        0x0c /* fusion writes to GTT were broken before this */
+#define RADEON_INFO_BACKEND_MAP                0x0d /* pipe to backend map, needed by mesa */
+/* virtual address start, va < start are reserved by the kernel */
+#define RADEON_INFO_VA_START           0x0e
+/* maximum size of ib using the virtual memory cs */
+#define RADEON_INFO_IB_VM_MAX_SIZE     0x0f
+/* max pipes - needed for compute shaders */
+#define RADEON_INFO_MAX_PIPES          0x10
+/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */
+#define RADEON_INFO_TIMESTAMP          0x11
+/* max shader engines (SE) - needed for geometry shaders, etc. */
+#define RADEON_INFO_MAX_SE             0x12
+/* max SH per SE */
+#define RADEON_INFO_MAX_SH_PER_SE      0x13
+
+struct drm_radeon_info {
+       uint32_t                request;
+       uint32_t                pad;
+       uint64_t                value;
 };
 
 #endif
index 0f990e7..8725e87 100644 (file)
-KMOD   = radeon
-SRCS   = r300_cmdbuf.c r600_blit.c r600_cp.c radeon_cp.c radeon_cs.c \
-       radeon_drv.c radeon_irq.c radeon_mem.c radeon_state.c
-SRCS   += device_if.h bus_if.h pci_if.h opt_drm.h
-CFLAGS += ${DEBUG_FLAGS} -I. -I.. -I@/dev/drm -I@/dev/drm/radeon
+# $FreeBSD: head/sys/modules/drm2/radeonkms/Makefile 254885 2013-08-25 19:37:15Z dumbbell $
 
-.if ${CC} != "icc"
-CFLAGS += --param large-function-growth=1000
-.endif
+.PATH: ${.CURDIR}/../../../dev/drm/radeon
 
-.if defined(DRM_DEBUG)
-DRM_DEBUG_OPT= "\#define DRM_DEBUG 1"
-.endif
+KMOD   = radeonkms
+SRCS   =                                                               \
+       rn50_reg_safe.h                                                 \
+       r100_reg_safe.h                                                 \
+       r200_reg_safe.h                                                 \
+       rv515_reg_safe.h                                                \
+       r300_reg_safe.h                                                 \
+       r420_reg_safe.h                                                 \
+       rs600_reg_safe.h                                                \
+       r600_reg_safe.h                                                 \
+       evergreen_reg_safe.h                                            \
+       cayman_reg_safe.h
+SRCS   +=                                                              \
+       radeon_acpi.c                                                   \
+       radeon_agp.c                                                    \
+       radeon_asic.c                                                   \
+       radeon_atombios.c                                               \
+       radeon_atpx_handler.c                                           \
+       radeon_benchmark.c                                              \
+       radeon_bios.c                                                   \
+       radeon_clocks.c                                                 \
+       radeon_combios.c                                                \
+       radeon_connectors.c                                             \
+       radeon_cp.c                                                     \
+       radeon_cs.c                                                     \
+       radeon_cursor.c                                                 \
+       radeon_device.c                                                 \
+       radeon_display.c                                                \
+       radeon_drv.c                                                    \
+       radeon_encoders.c                                               \
+       radeon_fb.c                                                     \
+       radeon_fence.c                                                  \
+       radeon_gart.c                                                   \
+       radeon_gem.c                                                    \
+       radeon_i2c.c                                                    \
+       radeon_irq.c                                                    \
+       radeon_irq_kms.c                                                \
+       radeon_kms.c                                                    \
+       radeon_legacy_crtc.c                                            \
+       radeon_legacy_encoders.c                                        \
+       radeon_legacy_tv.c                                              \
+       radeon_mem.c                                                    \
+       radeon_object.c                                                 \
+       radeon_pm.c                                                     \
+       radeon_ring.c                                                   \
+       radeon_sa.c                                                     \
+       radeon_semaphore.c                                              \
+       radeon_state.c                                                  \
+       radeon_test.c                                                   \
+       radeon_ttm.c                                                    \
+       atom.c                                                          \
+       atombios_crtc.c                                                 \
+       atombios_dp.c                                                   \
+       atombios_encoders.c                                             \
+       atombios_i2c.c                                                  \
+       r100.c                                                          \
+       r200.c                                                          \
+       r300.c                                                          \
+       r300_cmdbuf.c                                                   \
+       r420.c                                                          \
+       rs400.c                                                         \
+       rs600.c                                                         \
+       rs690.c                                                         \
+       rv515.c                                                         \
+       r520.c                                                          \
+       r600.c                                                          \
+       r600_audio.c                                                    \
+       r600_blit.c                                                     \
+       r600_blit_kms.c                                                 \
+       r600_blit_shaders.c                                             \
+       r600_cp.c                                                       \
+       r600_cs.c                                                       \
+       r600_hdmi.c                                                     \
+       rv770.c                                                         \
+       evergreen.c                                                     \
+       evergreen_blit_kms.c                                            \
+       evergreen_blit_shaders.c                                        \
+       evergreen_cs.c                                                  \
+       evergreen_hdmi.c                                                \
+       cayman_blit_shaders.c                                           \
+       ni.c                                                            \
+       si.c                                                            \
+       si_blit_shaders.c
 
-.if !defined(DRM_NOLINUX)
-DRM_LINUX_OPT= "\#define DRM_LINUX 1"
-.endif
+#radeon_ioc32.c
+#radeon_prime.c
+#--radeon_trace_points.c
 
-opt_drm.h:
-       touch ${.TARGET}
-       echo $(DRM_DEBUG_OPT) >> ${.TARGET}
-       echo $(DRM_LINUX_OPT) >> ${.TARGET}
+SRCS   +=                                                              \
+       opt_acpi.h                                                      \
+       opt_compat.h                                                    \
+       opt_drm.h                                                       \
+       acpi_if.h                                                       \
+       bus_if.h                                                        \
+       device_if.h                                                     \
+       iicbb_if.h                                                      \
+       iicbus_if.h                                                     \
+       pci_if.h
+
+CFLAGS+= -I${.CURDIR}/../../../dev/drm/radeon -fms-extensions
+CFLAGS+= -I${SYSDIR}/contrib/dev/acpica-unix/include
 
 CFLAGS+= -I${SYSDIR}/dev/drm/include
 
diff --git a/sys/dev/drm/radeon/ObjectID.h b/sys/dev/drm/radeon/ObjectID.h
new file mode 100644 (file)
index 0000000..37abd7e
--- /dev/null
@@ -0,0 +1,698 @@
+/*
+* Copyright 2006-2007 Advanced Micro Devices, Inc.  
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* $FreeBSD: head/sys/dev/drm2/radeon/ObjectID.h 254885 2013-08-25 19:37:15Z dumbbell $
+*/
+/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */
+
+#ifndef _OBJECTID_H
+#define _OBJECTID_H
+
+#if defined(_X86_)
+#pragma pack(1)
+#endif
+
+/****************************************************/
+/* Graphics Object Type Definition                  */
+/****************************************************/
+#define GRAPH_OBJECT_TYPE_NONE                    0x0
+#define GRAPH_OBJECT_TYPE_GPU                     0x1
+#define GRAPH_OBJECT_TYPE_ENCODER                 0x2
+#define GRAPH_OBJECT_TYPE_CONNECTOR               0x3
+#define GRAPH_OBJECT_TYPE_ROUTER                  0x4
+/* deleted */
+#define GRAPH_OBJECT_TYPE_DISPLAY_PATH            0x6  
+#define GRAPH_OBJECT_TYPE_GENERIC                 0x7
+
+/****************************************************/
+/* Encoder Object ID Definition                     */
+/****************************************************/
+#define ENCODER_OBJECT_ID_NONE                    0x00 
+
+/* Radeon Class Display Hardware */
+#define ENCODER_OBJECT_ID_INTERNAL_LVDS           0x01
+#define ENCODER_OBJECT_ID_INTERNAL_TMDS1          0x02
+#define ENCODER_OBJECT_ID_INTERNAL_TMDS2          0x03
+#define ENCODER_OBJECT_ID_INTERNAL_DAC1           0x04
+#define ENCODER_OBJECT_ID_INTERNAL_DAC2           0x05     /* TV/CV DAC */
+#define ENCODER_OBJECT_ID_INTERNAL_SDVOA          0x06
+#define ENCODER_OBJECT_ID_INTERNAL_SDVOB          0x07
+
+/* External Third Party Encoders */
+#define ENCODER_OBJECT_ID_SI170B                  0x08
+#define ENCODER_OBJECT_ID_CH7303                  0x09
+#define ENCODER_OBJECT_ID_CH7301                  0x0A
+#define ENCODER_OBJECT_ID_INTERNAL_DVO1           0x0B    /* This belongs to Radeon Class Display Hardware */
+#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA          0x0C
+#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB          0x0D
+#define ENCODER_OBJECT_ID_TITFP513                0x0E
+#define ENCODER_OBJECT_ID_INTERNAL_LVTM1          0x0F    /* not used for Radeon */
+#define ENCODER_OBJECT_ID_VT1623                  0x10
+#define ENCODER_OBJECT_ID_HDMI_SI1930             0x11
+#define ENCODER_OBJECT_ID_HDMI_INTERNAL           0x12
+#define ENCODER_OBJECT_ID_ALMOND                  0x22
+#define ENCODER_OBJECT_ID_TRAVIS                  0x23
+#define ENCODER_OBJECT_ID_NUTMEG                  0x22
+/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1   0x13
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1    0x14
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1    0x15
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2    0x16  /* Shared with CV/TV and CRT */
+#define ENCODER_OBJECT_ID_SI178                   0X17  /* External TMDS (dual link, no HDCP.) */
+#define ENCODER_OBJECT_ID_MVPU_FPGA               0x18  /* MVPU FPGA chip */
+#define ENCODER_OBJECT_ID_INTERNAL_DDI            0x19
+#define ENCODER_OBJECT_ID_VT1625                  0x1A
+#define ENCODER_OBJECT_ID_HDMI_SI1932             0x1B
+#define ENCODER_OBJECT_ID_DP_AN9801               0x1C
+#define ENCODER_OBJECT_ID_DP_DP501                0x1D
+#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY         0x1E
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA   0x1F
+#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1        0x20
+#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2        0x21
+#define ENCODER_OBJECT_ID_INTERNAL_VCE            0x24
+
+#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO    0xFF
+
+/****************************************************/
+/* Connector Object ID Definition                   */
+/****************************************************/
+#define CONNECTOR_OBJECT_ID_NONE                  0x00 
+#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I     0x01
+#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I       0x02
+#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D     0x03
+#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D       0x04
+#define CONNECTOR_OBJECT_ID_VGA                   0x05
+#define CONNECTOR_OBJECT_ID_COMPOSITE             0x06
+#define CONNECTOR_OBJECT_ID_SVIDEO                0x07
+#define CONNECTOR_OBJECT_ID_YPbPr                 0x08
+#define CONNECTOR_OBJECT_ID_D_CONNECTOR           0x09
+#define CONNECTOR_OBJECT_ID_9PIN_DIN              0x0A  /* Supports both CV & TV */
+#define CONNECTOR_OBJECT_ID_SCART                 0x0B
+#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A           0x0C
+#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B           0x0D
+#define CONNECTOR_OBJECT_ID_LVDS                  0x0E
+#define CONNECTOR_OBJECT_ID_7PIN_DIN              0x0F
+#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR        0x10
+#define CONNECTOR_OBJECT_ID_CROSSFIRE             0x11
+#define CONNECTOR_OBJECT_ID_HARDCODE_DVI          0x12
+#define CONNECTOR_OBJECT_ID_DISPLAYPORT           0x13
+#define CONNECTOR_OBJECT_ID_eDP                   0x14
+#define CONNECTOR_OBJECT_ID_MXM                   0x15
+#define CONNECTOR_OBJECT_ID_LVDS_eDP              0x16
+
+/* deleted */
+
+/****************************************************/
+/* Router Object ID Definition                      */
+/****************************************************/
+#define ROUTER_OBJECT_ID_NONE                                                                                  0x00
+#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL                             0x01
+
+/****************************************************/
+/* Generic Object ID Definition                     */
+/****************************************************/
+#define GENERIC_OBJECT_ID_NONE                    0x00
+#define GENERIC_OBJECT_ID_GLSYNC                  0x01
+#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE        0x02
+#define GENERIC_OBJECT_ID_MXM_OPM                 0x03
+#define GENERIC_OBJECT_ID_STEREO_PIN              0x04        //This object could show up from Misc Object table, it follows ATOM_OBJECT format, and contains one ATOM_OBJECT_GPIO_CNTL_RECORD for the stereo pin
+
+/****************************************************/
+/* Graphics Object ENUM ID Definition               */
+/****************************************************/
+#define GRAPH_OBJECT_ENUM_ID1                     0x01
+#define GRAPH_OBJECT_ENUM_ID2                     0x02
+#define GRAPH_OBJECT_ENUM_ID3                     0x03
+#define GRAPH_OBJECT_ENUM_ID4                     0x04
+#define GRAPH_OBJECT_ENUM_ID5                     0x05
+#define GRAPH_OBJECT_ENUM_ID6                     0x06
+#define GRAPH_OBJECT_ENUM_ID7                     0x07
+
+/****************************************************/
+/* Graphics Object ID Bit definition                */
+/****************************************************/
+#define OBJECT_ID_MASK                            0x00FF
+#define ENUM_ID_MASK                              0x0700
+#define RESERVED1_ID_MASK                         0x0800
+#define OBJECT_TYPE_MASK                          0x7000
+#define RESERVED2_ID_MASK                         0x8000
+                                                  
+#define OBJECT_ID_SHIFT                           0x00
+#define ENUM_ID_SHIFT                             0x08
+#define OBJECT_TYPE_SHIFT                         0x0C
+
+
+/****************************************************/
+/* Graphics Object family definition                */
+/****************************************************/
+#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
+                                                                           GRAPHICS_OBJECT_ID   << OBJECT_ID_SHIFT)
+/****************************************************/
+/* GPU Object ID definition - Shared with BIOS      */
+/****************************************************/
+#define GPU_ENUM_ID1                            ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
+
+/****************************************************/
+/* Encoder Object ID definition - Shared with BIOS  */
+/****************************************************/
+/*
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1        0x2101      
+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1       0x2102
+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1       0x2103
+#define ENCODER_INTERNAL_DAC1_ENUM_ID1        0x2104
+#define ENCODER_INTERNAL_DAC2_ENUM_ID1        0x2105
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1       0x2106
+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1       0x2107
+#define ENCODER_SIL170B_ENUM_ID1              0x2108  
+#define ENCODER_CH7303_ENUM_ID1               0x2109
+#define ENCODER_CH7301_ENUM_ID1               0x210A
+#define ENCODER_INTERNAL_DVO1_ENUM_ID1        0x210B
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1       0x210C
+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1       0x210D
+#define ENCODER_TITFP513_ENUM_ID1             0x210E
+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1       0x210F
+#define ENCODER_VT1623_ENUM_ID1               0x2110
+#define ENCODER_HDMI_SI1930_ENUM_ID1          0x2111
+#define ENCODER_HDMI_INTERNAL_ENUM_ID1        0x2112
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1   0x2113
+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1    0x2114
+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1    0x2115
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    0x2116  
+#define ENCODER_SI178_ENUM_ID1                   0x2117 
+#define ENCODER_MVPU_FPGA_ENUM_ID1               0x2118
+#define ENCODER_INTERNAL_DDI_ENUM_ID1            0x2119
+#define ENCODER_VT1625_ENUM_ID1                  0x211A
+#define ENCODER_HDMI_SI1932_ENUM_ID1             0x211B
+#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1       0x211C
+#define ENCODER_DP_DP501_ENUM_ID1                0x211D
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1         0x211E
+*/
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC1_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC2_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID2    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+#define ENCODER_SIL170B_ENUM_ID1           ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7303_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7301_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DVO1_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_TITFP513_ENUM_ID1          ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_VT1623_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1930_ENUM_ID1       ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_INTERNAL_ENUM_ID1     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+
+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT)  // Shared with CV/TV and CRT
+
+#define ENCODER_SI178_ENUM_ID1                    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)  
+
+#define ENCODER_MVPU_FPGA_ENUM_ID1                ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                   GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                   ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DDI_ENUM_ID1     (  GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) 
+
+#define ENCODER_VT1625_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1932_ENUM_ID1       ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_DP501_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_AN9801_ENUM_ID1            ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                             GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                             ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1   ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)  
+
+#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
+
+#define ENCODER_ALMOND_ENUM_ID1                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
+
+#define ENCODER_ALMOND_ENUM_ID2                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                  GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_ALMOND << OBJECT_ID_SHIFT)
+
+#define ENCODER_TRAVIS_ENUM_ID1                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
+
+#define ENCODER_TRAVIS_ENUM_ID2                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                  GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_TRAVIS << OBJECT_ID_SHIFT)
+
+#define ENCODER_NUTMEG_ENUM_ID1                  ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_NUTMEG << OBJECT_ID_SHIFT)
+
+#define ENCODER_VCE_ENUM_ID1                     ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_INTERNAL_VCE << OBJECT_ID_SHIFT)
+
+/****************************************************/
+/* Connector Object ID definition - Shared with BIOS */
+/****************************************************/
+/*
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1        0x3101
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1          0x3102
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1        0x3103
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1          0x3104
+#define CONNECTOR_VGA_ENUM_ID1                      0x3105
+#define CONNECTOR_COMPOSITE_ENUM_ID1                0x3106
+#define CONNECTOR_SVIDEO_ENUM_ID1                   0x3107
+#define CONNECTOR_YPbPr_ENUM_ID1                    0x3108
+#define CONNECTOR_D_CONNECTORE_ENUM_ID1             0x3109
+#define CONNECTOR_9PIN_DIN_ENUM_ID1                 0x310A
+#define CONNECTOR_SCART_ENUM_ID1                    0x310B
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1              0x310C
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1              0x310D
+#define CONNECTOR_LVDS_ENUM_ID1                     0x310E
+#define CONNECTOR_7PIN_DIN_ENUM_ID1                 0x310F
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1           0x3110
+*/
+#define CONNECTOR_LVDS_ENUM_ID1                ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_LVDS_ENUM_ID2                ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_eDP_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_eDP_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID3   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID4   ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3     ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_VGA_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_VGA_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_COMPOSITE_ENUM_ID1           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_COMPOSITE_ENUM_ID2           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SVIDEO_ENUM_ID1              ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SVIDEO_ENUM_ID2              ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_YPbPr_ENUM_ID1               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_YPbPr_ENUM_ID2               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_D_CONNECTOR_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_D_CONNECTOR_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_9PIN_DIN_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_9PIN_DIN_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SCART_ENUM_ID1               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SCART_ENUM_ID2               ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_7PIN_DIN_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_7PIN_DIN_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1      ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2      ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID1           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID2           ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID1        ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID2        ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID1         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID2         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID4         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID5         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID6         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_MXM_ENUM_ID1                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_A
+
+#define CONNECTOR_MXM_ENUM_ID2                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_B
+
+#define CONNECTOR_MXM_ENUM_ID3                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_C
+
+#define CONNECTOR_MXM_ENUM_ID4                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DP_D
+
+#define CONNECTOR_MXM_ENUM_ID5                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_LVDS_TXxx
+
+#define CONNECTOR_MXM_ENUM_ID6                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_LVDS_UXxx
+
+#define CONNECTOR_MXM_ENUM_ID7                 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT)          //Mapping to MXM_DAC
+
+#define CONNECTOR_LVDS_eDP_ENUM_ID1            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_LVDS_eDP_ENUM_ID2            ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 CONNECTOR_OBJECT_ID_LVDS_eDP << OBJECT_ID_SHIFT)
+
+/****************************************************/
+/* Router Object ID definition - Shared with BIOS   */
+/****************************************************/
+#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1      ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
+                                                GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
+
+/* deleted */
+
+/****************************************************/
+/* Generic Object ID definition - Shared with BIOS  */
+/****************************************************/
+#define GENERICOBJECT_GLSYNC_ENUM_ID1           (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1       (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2       (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_MXM_OPM_ENUM_ID1           (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_STEREO_PIN_ENUM_ID1        (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                 GENERIC_OBJECT_ID_STEREO_PIN << OBJECT_ID_SHIFT)
+
+/****************************************************/
+/* Object Cap definition - Shared with BIOS         */
+/****************************************************/
+#define GRAPHICS_OBJECT_CAP_I2C                 0x00000001L
+#define GRAPHICS_OBJECT_CAP_TABLE_ID            0x00000002L
+
+
+#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID                   0x01
+#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID     0x02
+#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID    0x03
+
+#if defined(_X86_)
+#pragma pack()
+#endif
+
+#endif  /*GRAPHICTYPE */
+
+
+
+
diff --git a/sys/dev/drm/radeon/README b/sys/dev/drm/radeon/README
new file mode 100644 (file)
index 0000000..9adc355
--- /dev/null
@@ -0,0 +1,6 @@
+# $FreeBSD: head/sys/dev/drm2/radeon/README 254885 2013-08-25 19:37:15Z dumbbell $
+
+== Updates to reg_srcs/ files ==
+
+When a file in the "reg_srcs" subdirectory in updated, be sure to regen
+headers by running "make" in tools/tools/drm/radeon/mkregtable.
diff --git a/sys/dev/drm/radeon/atom-bits.h b/sys/dev/drm/radeon/atom-bits.h
new file mode 100644 (file)
index 0000000..b106ada
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Stanislaw Skowronek
+ *
+ * $FreeBSD: head/sys/dev/drm2/radeon/atom-bits.h 254885 2013-08-25 19:37:15Z dumbbell $
+ */
+
+#ifndef ATOM_BITS_H
+#define ATOM_BITS_H
+
+static inline uint8_t get_u8(void *bios, int ptr)
+{
+    return ((unsigned char *)bios)[ptr];
+}
+#define U8(ptr) get_u8(ctx->ctx->bios, (ptr))
+#define CU8(ptr) get_u8(ctx->bios, (ptr))
+static inline uint16_t get_u16(void *bios, int ptr)
+{
+    return get_u8(bios ,ptr)|(((uint16_t)get_u8(bios, ptr+1))<<8);
+}
+#define U16(ptr) get_u16(ctx->ctx->bios, (ptr))
+#define CU16(ptr) get_u16(ctx->bios, (ptr))
+static inline uint32_t get_u32(void *bios, int ptr)
+{
+    return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16);
+}
+#define U32(ptr) get_u32(ctx->ctx->bios, (ptr))
+#define CU32(ptr) get_u32(ctx->bios, (ptr))
+#define CSTR(ptr) (((char *)(ctx->bios))+(ptr))
+
+#endif
diff --git a/sys/dev/drm/radeon/atom-names.h b/sys/dev/drm/radeon/atom-names.h
new file mode 100644 (file)
index 0000000..22d17dc
--- /dev/null
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Stanislaw Skowronek
+ *
+ * $FreeBSD: head/sys/dev/drm2/radeon/atom-names.h 254885 2013-08-25 19:37:15Z dumbbell $
+ */
+
+#ifndef ATOM_NAMES_H
+#define ATOM_NAMES_H
+
+#include "atom.h"
+
+#ifdef ATOM_DEBUG
+
+#define ATOM_OP_NAMES_CNT 123
+static char *atom_op_names[ATOM_OP_NAMES_CNT] = {
+"RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
+"MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
+"OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
+"SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
+"SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
+"SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
+"MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
+"DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
+"ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
+"SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
+"SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
+"COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
+"JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
+"JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
+"TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
+"CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
+"CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
+"MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
+"RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
+"XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
+"SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
+"DEBUG", "CTB_DS",
+};
+
+#define ATOM_TABLE_NAMES_CNT 74
+static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
+"ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
+"VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
+"GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
+"GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
+"DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
+"MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
+"EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
+"DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
+"DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
+"CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
+"TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
+"EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
+"EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
+"SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
+"EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
+"LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
+"GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
+"DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
+"ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
+"ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
+"MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
+"VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
+"EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
+"CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
+"MemoryDeviceInit", "EnableYUV",
+};
+
+#define ATOM_IO_NAMES_CNT 5
+static char *atom_io_names[ATOM_IO_NAMES_CNT] = {
+"MM", "PLL", "MC", "PCIE", "PCIE PORT",
+};
+
+#else
+
+#define ATOM_OP_NAMES_CNT 0
+#define ATOM_TABLE_NAMES_CNT 0
+#define ATOM_IO_NAMES_CNT 0
+
+#endif
+
+#endif
diff --git a/sys/dev/drm/radeon/atom-types.h b/sys/dev/drm/radeon/atom-types.h
new file mode 100644 (file)
index 0000000..2a8ae9c
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Dave Airlie
+ *
+ * $FreeBSD: head/sys/dev/drm2/radeon/atom-types.h 254885 2013-08-25 19:37:15Z dumbbell $
+ */
+
+#ifndef ATOM_TYPES_H
+#define ATOM_TYPES_H
+
+/* sync atom types to kernel types */
+
+typedef uint16_t USHORT;
+typedef uint32_t ULONG;
+typedef uint8_t UCHAR;
+
+
+#ifndef ATOM_BIG_ENDIAN
+#if defined(__BIG_ENDIAN)
+#define ATOM_BIG_ENDIAN 1
+#else
+#define ATOM_BIG_ENDIAN 0
+#endif
+#endif
+#endif
diff --git a/sys/dev/drm/radeon/atom.c b/sys/dev/drm/radeon/atom.c
new file mode 100644 (file)
index 0000000..5d43b8f
--- /dev/null
@@ -0,0 +1,1403 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Stanislaw Skowronek
+ *
+ * $FreeBSD: head/sys/dev/drm2/radeon/atom.c 254894 2013-08-26 06:31:57Z dumbbell $
+ */
+
+#define ATOM_DEBUG
+
+#include "atom.h"
+#include "atom-names.h"
+#include "atom-bits.h"
+#include "radeon.h"
+
+#define ATOM_COND_ABOVE                0
+#define ATOM_COND_ABOVEOREQUAL 1
+#define ATOM_COND_ALWAYS       2
+#define ATOM_COND_BELOW                3
+#define ATOM_COND_BELOWOREQUAL 4
+#define ATOM_COND_EQUAL                5
+#define ATOM_COND_NOTEQUAL     6
+
+#define ATOM_PORT_ATI  0
+#define ATOM_PORT_PCI  1
+#define ATOM_PORT_SYSIO        2
+
+#define ATOM_UNIT_MICROSEC     0
+#define ATOM_UNIT_MILLISEC     1
+
+#define PLL_INDEX      2
+#define PLL_DATA       3
+
+typedef struct {
+       struct atom_context *ctx;
+       uint32_t *ps, *ws;
+       int ps_shift;
+       uint16_t start;
+       unsigned last_jump;
+       unsigned long last_jump_jiffies;
+       bool abort;
+} atom_exec_context;
+
+int atom_debug = 0;
+static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params);
+
+static uint32_t atom_arg_mask[8] =
+    { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
+0xFF000000 };
+static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
+
+static int atom_dst_to_src[8][4] = {
+       /* translate destination alignment field to the source alignment encoding */
+       {0, 0, 0, 0},
+       {1, 2, 3, 0},
+       {1, 2, 3, 0},
+       {1, 2, 3, 0},
+       {4, 5, 6, 7},
+       {4, 5, 6, 7},
+       {4, 5, 6, 7},
+       {4, 5, 6, 7},
+};
+static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
+
+static int debug_depth = 0;
+#ifdef ATOM_DEBUG
+static void debug_print_spaces(int n)
+{
+       while (n--)
+               kprintf("   ");
+}
+
+#define ATOM_DEBUG_PRINT(...) do if (atom_debug) { kprintf(__FILE__ __VA_ARGS__); } while (0)
+#define ATOM_SDEBUG_PRINT(...) do if (atom_debug) { kprintf(__FILE__); debug_print_spaces(debug_depth); kprintf(__VA_ARGS__); } while (0)
+#else
+#define ATOM_DEBUG_PRINT(...) do { } while (0)
+#define ATOM_SDEBUG_PRINT(...) do { } while (0)
+#endif
+
+static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
+                                uint32_t index, uint32_t data)
+{
+       struct radeon_device *rdev = ctx->card->dev->dev_private;
+       uint32_t temp = 0xCDCDCDCD;
+
+       while (1)
+               switch (CU8(base)) {
+               case ATOM_IIO_NOP:
+                       base++;
+                       break;
+               case ATOM_IIO_READ:
+                       temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1));
+                       base += 3;
+                       break;
+               case ATOM_IIO_WRITE:
+                       if (rdev->family == CHIP_RV515)
+                               (void)ctx->card->ioreg_read(ctx->card, CU16(base + 1));
+                       ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp);
+                       base += 3;
+                       break;
+               case ATOM_IIO_CLEAR:
+                       temp &=
+                           ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
+                             CU8(base + 2));
+                       base += 3;
+                       break;
+               case ATOM_IIO_SET:
+                       temp |=
+                           (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
+                                                                       2);
+                       base += 3;
+                       break;
+               case ATOM_IIO_MOVE_INDEX:
+                       temp &=
+                           ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
+                             CU8(base + 3));
+                       temp |=
+                           ((index >> CU8(base + 2)) &
+                            (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
+                                                                         3);
+                       base += 4;
+                       break;
+               case ATOM_IIO_MOVE_DATA:
+                       temp &=
+                           ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
+                             CU8(base + 3));
+                       temp |=
+                           ((data >> CU8(base + 2)) &
+                            (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
+                                                                         3);
+                       base += 4;
+                       break;
+               case ATOM_IIO_MOVE_ATTR:
+                       temp &=
+                           ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
+                             CU8(base + 3));
+                       temp |=
+                           ((ctx->
+                             io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
+                                                                         CU8
+                                                                         (base
+                                                                          +
+                                                                          1))))
+                           << CU8(base + 3);
+                       base += 4;
+                       break;
+               case ATOM_IIO_END:
+                       return temp;
+               default:
+                       DRM_INFO("Unknown IIO opcode.\n");
+                       return 0;
+               }
+}
+
+static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
+                                int *ptr, uint32_t *saved, int print)
+{
+       uint32_t idx, val = 0xCDCDCDCD, align, arg;
+       struct atom_context *gctx = ctx->ctx;
+       arg = attr & 7;
+       align = (attr >> 3) & 7;
+       switch (arg) {
+       case ATOM_ARG_REG:
+               idx = U16(*ptr);
+               (*ptr) += 2;
+               if (print)
+                       ATOM_DEBUG_PRINT("REG[0x%04X]", idx);
+               idx += gctx->reg_block;
+               switch (gctx->io_mode) {
+               case ATOM_IO_MM:
+                       val = gctx->card->reg_read(gctx->card, idx);
+                       break;
+               case ATOM_IO_PCI:
+                       DRM_INFO(
+                              "PCI registers are not implemented.\n");
+                       return 0;
+               case ATOM_IO_SYSIO:
+                       DRM_INFO(
+                              "SYSIO registers are not implemented.\n");
+                       return 0;
+               default:
+                       if (!(gctx->io_mode & 0x80)) {
+                               DRM_INFO("Bad IO mode.\n");
+                               return 0;
+                       }
+                       if (!gctx->iio[gctx->io_mode & 0x7F]) {
+                               DRM_INFO(
+                                      "Undefined indirect IO read method %d.\n",
+                                      gctx->io_mode & 0x7F);
+                               return 0;
+                       }
+                       val =
+                           atom_iio_execute(gctx,
+                                            gctx->iio[gctx->io_mode & 0x7F],
+                                            idx, 0);
+               }
+               break;
+       case ATOM_ARG_PS:
+               idx = U8(*ptr);
+               (*ptr)++;
+               /* get_unaligned_le32 avoids unaligned accesses from atombios
+                * tables, noticed on a DEC Alpha. */
+               val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
+               if (print)
+                       ATOM_DEBUG_PRINT("PS[0x%02X,0x%04X]", idx, val);
+               break;
+       case ATOM_ARG_WS:
+               idx = U8(*ptr);
+               (*ptr)++;
+               if (print)
+                       ATOM_DEBUG_PRINT("WS[0x%02X]", idx);
+               switch (idx) {
+               case ATOM_WS_QUOTIENT:
+                       val = gctx->divmul[0];
+                       break;
+               case ATOM_WS_REMAINDER:
+                       val = gctx->divmul[1];
+                       break;
+               case ATOM_WS_DATAPTR:
+                       val = gctx->data_block;
+                       break;
+               case ATOM_WS_SHIFT:
+                       val = gctx->shift;
+                       break;
+               case ATOM_WS_OR_MASK:
+                       val = 1 << gctx->shift;
+                       break;
+               case ATOM_WS_AND_MASK:
+                       val = ~(1 << gctx->shift);
+                       break;
+               case ATOM_WS_FB_WINDOW:
+                       val = gctx->fb_base;
+                       break;
+               case ATOM_WS_ATTRIBUTES:
+                       val = gctx->io_attr;
+                       break;
+               case ATOM_WS_REGPTR:
+                       val = gctx->reg_block;
+                       break;
+               default:
+                       val = ctx->ws[idx];
+               }
+               break;
+       case ATOM_ARG_ID:
+               idx = U16(*ptr);
+               (*ptr) += 2;
+               if (print) {
+                       if (gctx->data_block)
+                               ATOM_DEBUG_PRINT("ID[0x%04X+%04X]", idx, gctx->data_block);
+                       else
+                               ATOM_DEBUG_PRINT("ID[0x%04X]", idx);
+               }
+               val = U32(idx + gctx->data_block);
+               break;
+       case ATOM_ARG_FB:
+               idx = U8(*ptr);
+               (*ptr)++;
+               if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
+                       DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
+                                 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
+                       val = 0;
+               } else
+                       val = gctx->scratch[(gctx->fb_base / 4) + idx];
+               if (print)
+                       ATOM_DEBUG_PRINT("FB[0x%02X]", idx);
+               break;
+       case ATOM_ARG_IMM:
+               switch (align) {
+               case ATOM_SRC_DWORD:
+                       val = U32(*ptr);
+                       (*ptr) += 4;
+                       if (print)
+                               ATOM_DEBUG_PRINT("IMM 0x%08X\n", val);
+                       return val;
+               case ATOM_SRC_WORD0:
+               case ATOM_SRC_WORD8:
+               case ATOM_SRC_WORD16:
+                       val = U16(*ptr);
+                       (*ptr) += 2;
+                       if (print)
+                               ATOM_DEBUG_PRINT("IMM 0x%04X\n", val);
+                       return val;
+               case ATOM_SRC_BYTE0:
+               case ATOM_SRC_BYTE8:
+               case ATOM_SRC_BYTE16:
+               case ATOM_SRC_BYTE24:
+                       val = U8(*ptr);
+                       (*ptr)++;
+                       if (print)
+                               ATOM_DEBUG_PRINT("IMM 0x%02X\n", val);
+                       return val;
+               }
+               return 0;
+       case ATOM_ARG_PLL:
+               idx = U8(*ptr);
+               (*ptr)++;
+               if (print)
+                       ATOM_DEBUG_PRINT("PLL[0x%02X]", idx);
+               val = gctx->card->pll_read(gctx->card, idx);
+               break;
+       case ATOM_ARG_MC:
+               idx = U8(*ptr);
+               (*ptr)++;
+               if (print)
+                       ATOM_DEBUG_PRINT("MC[0x%02X]", idx);
+               val = gctx->card->mc_read(gctx->card, idx);
+               break;
+       }
+       if (saved)
+               *saved = val;
+       val &= atom_arg_mask[align];
+       val >>= atom_arg_shift[align];
+       if (print)
+               switch (align) {
+               case ATOM_SRC_DWORD:
+                       ATOM_DEBUG_PRINT(".[31:0] -> 0x%08X\n", val);
+                       break;
+               case ATOM_SRC_WORD0:
+                       ATOM_DEBUG_PRINT(".[15:0] -> 0x%04X\n", val);
+                       break;
+               case ATOM_SRC_WORD8:
+                       ATOM_DEBUG_PRINT(".[23:8] -> 0x%04X\n", val);
+                       break;
+               case ATOM_SRC_WORD16:
+                       ATOM_DEBUG_PRINT(".[31:16] -> 0x%04X\n", val);
+                       break;
+               case ATOM_SRC_BYTE0:
+                       ATOM_DEBUG_PRINT(".[7:0] -> 0x%02X\n", val);
+                       break;
+               case ATOM_SRC_BYTE8:
+                       ATOM_DEBUG_PRINT(".[15:8] -> 0x%02X\n", val);
+                       break;
+               case ATOM_SRC_BYTE16:
+                       ATOM_DEBUG_PRINT(".[23:16] -> 0x%02X\n", val);
+                       break;
+               case ATOM_SRC_BYTE24:
+                       ATOM_DEBUG_PRINT(".[31:24] -> 0x%02X\n", val);
+                       break;
+               }
+       return val;
+}
+
+static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
+{
+       uint32_t align = (attr >> 3) & 7, arg = attr & 7;
+       switch (arg) {
+       case ATOM_ARG_REG:
+       case ATOM_ARG_ID:
+               (*ptr) += 2;
+               break;
+       case ATOM_ARG_PLL:
+       case ATOM_ARG_MC:
+       case ATOM_ARG_PS:
+       case ATOM_ARG_WS:
+       case ATOM_ARG_FB:
+               (*ptr)++;
+               break;
+       case ATOM_ARG_IMM:
+               switch (align) {
+               case ATOM_SRC_DWORD:
+                       (*ptr) += 4;
+                       return;
+               case ATOM_SRC_WORD0:
+               case ATOM_SRC_WORD8:
+               case ATOM_SRC_WORD16:
+                       (*ptr) += 2;
+                       return;
+               case ATOM_SRC_BYTE0:
+               case ATOM_SRC_BYTE8:
+               case ATOM_SRC_BYTE16:
+               case ATOM_SRC_BYTE24:
+                       (*ptr)++;
+                       return;
+               }
+               return;
+       }
+}
+
+static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
+{
+       return atom_get_src_int(ctx, attr, ptr, NULL, 1);
+}
+
+static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
+{
+       uint32_t val = 0xCDCDCDCD;
+
+       switch (align) {
+       case ATOM_SRC_DWORD:
+               val = U32(*ptr);
+               (*ptr) += 4;
+               break;
+       case ATOM_SRC_WORD0:
+       case ATOM_SRC_WORD8:
+       case ATOM_SRC_WORD16:
+               val = U16(*ptr);
+               (*ptr) += 2;
+               break;
+       case ATOM_SRC_BYTE0:
+       case ATOM_SRC_BYTE8:
+       case ATOM_SRC_BYTE16:
+       case ATOM_SRC_BYTE24:
+               val = U8(*ptr);
+               (*ptr)++;
+               break;
+       }
+       return val;
+}
+
+static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
+                            int *ptr, uint32_t *saved, int print)
+{
+       return atom_get_src_int(ctx,
+                               arg | atom_dst_to_src[(attr >> 3) &
+                                                     7][(attr >> 6) & 3] << 3,
+                               ptr, saved, print);
+}
+
+static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
+{
+       atom_skip_src_int(ctx,
+                         arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
+                                                                3] << 3, ptr);
+}
+
+static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
+                        int *ptr, uint32_t val, uint32_t saved)
+{
+       uint32_t align =
+           atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
+           val, idx;
+       struct atom_context *gctx = ctx->ctx;
+       old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
+       val <<= atom_arg_shift[align];
+       val &= atom_arg_mask[align];
+       saved &= ~atom_arg_mask[align];
+       val |= saved;
+       switch (arg) {
+       case ATOM_ARG_REG:
+               idx = U16(*ptr);
+               (*ptr) += 2;
+               ATOM_DEBUG_PRINT("REG[0x%04X]", idx);
+               idx += gctx->reg_block;
+               switch (gctx->io_mode) {
+               case ATOM_IO_MM:
+                       if (idx == 0)
+                               gctx->card->reg_write(gctx->card, idx,
+                                                     val << 2);
+                       else
+                               gctx->card->reg_write(gctx->card, idx, val);
+                       break;
+               case ATOM_IO_PCI:
+                       DRM_INFO(
+                              "PCI registers are not implemented.\n");
+                       return;
+               case ATOM_IO_SYSIO:
+                       DRM_INFO(
+                              "SYSIO registers are not implemented.\n");
+                       return;
+               default:
+                       if (!(gctx->io_mode & 0x80)) {
+                               DRM_INFO("Bad IO mode.\n");
+                               return;
+                       }
+                       if (!gctx->iio[gctx->io_mode & 0xFF]) {
+                               DRM_INFO(
+                                      "Undefined indirect IO write method %d.\n",
+                                      gctx->io_mode & 0x7F);
+                               return;
+                       }
+                       atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
+                                        idx, val);
+               }
+               break;
+       case ATOM_ARG_PS:
+               idx = U8(*ptr);
+               (*ptr)++;
+               ATOM_DEBUG_PRINT("PS[0x%02X]", idx);
+               ctx->ps[idx] = cpu_to_le32(val);
+               break;
+       case ATOM_ARG_WS:
+               idx = U8(*ptr);
+               (*ptr)++;
+               ATOM_DEBUG_PRINT("WS[0x%02X]", idx);
+               switch (idx) {
+               case ATOM_WS_QUOTIENT:
+                       gctx->divmul[0] = val;
+                       break;
+               case ATOM_WS_REMAINDER:
+                       gctx->divmul[1] = val;
+                       break;
+               case ATOM_WS_DATAPTR:
+                       gctx->data_block = val;
+                       break;
+               case ATOM_WS_SHIFT:
+                       gctx->shift = val;
+                       break;
+               case ATOM_WS_OR_MASK:
+               case ATOM_WS_AND_MASK:
+                       break;
+               case ATOM_WS_FB_WINDOW:
+                       gctx->fb_base = val;
+                       break;
+               case ATOM_WS_ATTRIBUTES:
+                       gctx->io_attr = val;
+                       break;
+               case ATOM_WS_REGPTR:
+                       gctx->reg_block = val;
+                       break;
+               default:
+                       ctx->ws[idx] = val;
+               }
+               break;
+       case ATOM_ARG_FB:
+               idx = U8(*ptr);
+               (*ptr)++;
+               if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
+                       DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
+                                 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
+               } else
+                       gctx->scratch[(gctx->fb_base / 4) + idx] = val;
+               ATOM_DEBUG_PRINT("FB[0x%02X]", idx);
+               break;
+       case ATOM_ARG_PLL:
+               idx = U8(*ptr);
+               (*ptr)++;
+               ATOM_DEBUG_PRINT("PLL[0x%02X]", idx);
+               gctx->card->pll_write(gctx->card, idx, val);
+               break;
+       case ATOM_ARG_MC:
+               idx = U8(*ptr);
+               (*ptr)++;
+               ATOM_DEBUG_PRINT("MC[0x%02X]", idx);
+               gctx->card->mc_write(gctx->card, idx, val);
+               return;
+       }
+       switch (align) {
+       case ATOM_SRC_DWORD:
+               ATOM_DEBUG_PRINT(".[31:0] <- 0x%08X\n", old_val);
+               break;
+       case ATOM_SRC_WORD0:
+               ATOM_DEBUG_PRINT(".[15:0] <- 0x%04X\n", old_val);
+               break;
+       case ATOM_SRC_WORD8:
+               ATOM_DEBUG_PRINT(".[23:8] <- 0x%04X\n", old_val);
+               break;
+       case ATOM_SRC_WORD16:
+               ATOM_DEBUG_PRINT(".[31:16] <- 0x%04X\n", old_val);
+               break;
+       case ATOM_SRC_BYTE0:
+               ATOM_DEBUG_PRINT(".[7:0] <- 0x%02X\n", old_val);
+               break;
+       case ATOM_SRC_BYTE8:
+               ATOM_DEBUG_PRINT(".[15:8] <- 0x%02X\n", old_val);
+               break;
+       case ATOM_SRC_BYTE16:
+               ATOM_DEBUG_PRINT(".[23:16] <- 0x%02X\n", old_val);
+               break;
+       case ATOM_SRC_BYTE24:
+               ATOM_DEBUG_PRINT(".[31:24] <- 0x%02X\n", old_val);
+               break;
+       }
+}
+
+static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, src, saved;
+       int dptr = *ptr;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       ATOM_SDEBUG_PRINT("   src: ");
+       src = atom_get_src(ctx, attr, ptr);
+       dst += src;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, src, saved;
+       int dptr = *ptr;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       ATOM_SDEBUG_PRINT("   src: ");
+       src = atom_get_src(ctx, attr, ptr);
+       dst &= src;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
+{
+       DRM_INFO("ATOM BIOS beeped!\n");
+}
+
+static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
+{
+       int idx = U8((*ptr)++);
+       int r = 0;
+
+       if (idx < ATOM_TABLE_NAMES_CNT)
+               ATOM_SDEBUG_PRINT("   table: %d (%s)\n", idx, atom_table_names[idx]);
+       else
+               ATOM_SDEBUG_PRINT("   table: %d\n", idx);
+       if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
+               r = atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
+       if (r) {
+               ctx->abort = true;
+       }
+}
+
+static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t saved;
+       int dptr = *ptr;
+       attr &= 0x38;
+       attr |= atom_def_dst[attr >> 3] << 6;
+       atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
+}
+
+static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, src;
+       ATOM_SDEBUG_PRINT("   src1: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+       ATOM_SDEBUG_PRINT("   src2: ");
+       src = atom_get_src(ctx, attr, ptr);
+       ctx->ctx->cs_equal = (dst == src);
+       ctx->ctx->cs_above = (dst > src);
+       ATOM_SDEBUG_PRINT("   result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
+              ctx->ctx->cs_above ? "GT" : "LE");
+}
+
+static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
+{
+       unsigned count = U8((*ptr)++);
+       ATOM_SDEBUG_PRINT("   count: %d\n", count);
+       if (arg == ATOM_UNIT_MICROSEC)
+               DRM_UDELAY(count);
+       else if (!drm_can_sleep())
+               DRM_MDELAY(count);
+       else
+               DRM_MSLEEP(count);
+}
+
+static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, src;
+       ATOM_SDEBUG_PRINT("   src1: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+       ATOM_SDEBUG_PRINT("   src2: ");
+       src = atom_get_src(ctx, attr, ptr);
+       if (src != 0) {
+               ctx->ctx->divmul[0] = dst / src;
+               ctx->ctx->divmul[1] = dst % src;
+       } else {
+               ctx->ctx->divmul[0] = 0;
+               ctx->ctx->divmul[1] = 0;
+       }
+}
+
+static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
+{
+       /* functionally, a nop */
+}
+
+static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
+{
+       int execute = 0, target = U16(*ptr);
+       unsigned long cjiffies;
+
+       (*ptr) += 2;
+       switch (arg) {
+       case ATOM_COND_ABOVE:
+               execute = ctx->ctx->cs_above;
+               break;
+       case ATOM_COND_ABOVEOREQUAL:
+               execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
+               break;
+       case ATOM_COND_ALWAYS:
+               execute = 1;
+               break;
+       case ATOM_COND_BELOW:
+               execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
+               break;
+       case ATOM_COND_BELOWOREQUAL:
+               execute = !ctx->ctx->cs_above;
+               break;
+       case ATOM_COND_EQUAL:
+               execute = ctx->ctx->cs_equal;
+               break;
+       case ATOM_COND_NOTEQUAL:
+               execute = !ctx->ctx->cs_equal;
+               break;
+       }
+       if (arg != ATOM_COND_ALWAYS)
+               ATOM_SDEBUG_PRINT("   taken: %s\n", execute ? "yes" : "no");
+       ATOM_SDEBUG_PRINT("   target: 0x%04X\n", target);
+       if (execute) {
+               if (ctx->last_jump == (ctx->start + target)) {
+                       cjiffies = jiffies;
+                       if (time_after(cjiffies, ctx->last_jump_jiffies)) {
+                               cjiffies -= ctx->last_jump_jiffies;
+                               if ((jiffies_to_msecs(cjiffies) > 5000)) {
+                                       DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n");
+                                       ctx->abort = true;
+                               }
+                       } else {
+                               /* jiffies wrap around we will just wait a little longer */
+                               ctx->last_jump_jiffies = jiffies;
+                       }
+               } else {
+                       ctx->last_jump = ctx->start + target;
+                       ctx->last_jump_jiffies = jiffies;
+               }
+               *ptr = ctx->start + target;
+       }
+}
+
+static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, mask, src, saved;
+       int dptr = *ptr;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
+       ATOM_SDEBUG_PRINT("   mask: 0x%08x", mask);
+       ATOM_SDEBUG_PRINT("   src: ");
+       src = atom_get_src(ctx, attr, ptr);
+       dst &= mask;
+       dst |= src;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t src, saved;
+       int dptr = *ptr;
+       if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
+               atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
+       else {
+               atom_skip_dst(ctx, arg, attr, ptr);
+               saved = 0xCDCDCDCD;
+       }
+       ATOM_SDEBUG_PRINT("   src: ");
+       src = atom_get_src(ctx, attr, ptr);
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, src, saved);
+}
+
+static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, src;
+       ATOM_SDEBUG_PRINT("   src1: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+       ATOM_SDEBUG_PRINT("   src2: ");
+       src = atom_get_src(ctx, attr, ptr);
+       ctx->ctx->divmul[0] = dst * src;
+}
+
+static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
+{
+       /* nothing */
+}
+
+static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, src, saved;
+       int dptr = *ptr;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       ATOM_SDEBUG_PRINT("   src: ");
+       src = atom_get_src(ctx, attr, ptr);
+       dst |= src;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t val = U8((*ptr)++);
+       ATOM_SDEBUG_PRINT("POST card output: 0x%02X\n", val);
+}
+
+static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
+{
+       DRM_INFO("unimplemented!\n");
+}
+
+static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
+{
+       DRM_INFO("unimplemented!\n");
+}
+
+static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
+{
+       DRM_INFO("unimplemented!\n");
+}
+
+static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
+{
+       int idx = U8(*ptr);
+       (*ptr)++;
+       ATOM_SDEBUG_PRINT("   block: %d\n", idx);
+       if (!idx)
+               ctx->ctx->data_block = 0;
+       else if (idx == 255)
+               ctx->ctx->data_block = ctx->start;
+       else
+               ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
+       ATOM_SDEBUG_PRINT("   base: 0x%04X\n", ctx->ctx->data_block);
+}
+
+static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       ATOM_SDEBUG_PRINT("   fb_base: ");
+       ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
+}
+
+static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
+{
+       int port;
+       switch (arg) {
+       case ATOM_PORT_ATI:
+               port = U16(*ptr);
+               if (port < ATOM_IO_NAMES_CNT)
+                       ATOM_SDEBUG_PRINT("   port: %d (%s)\n", port, atom_io_names[port]);
+               else
+                       ATOM_SDEBUG_PRINT("   port: %d\n", port);
+               if (!port)
+                       ctx->ctx->io_mode = ATOM_IO_MM;
+               else
+                       ctx->ctx->io_mode = ATOM_IO_IIO | port;
+               (*ptr) += 2;
+               break;
+       case ATOM_PORT_PCI:
+               ctx->ctx->io_mode = ATOM_IO_PCI;
+               (*ptr)++;
+               break;
+       case ATOM_PORT_SYSIO:
+               ctx->ctx->io_mode = ATOM_IO_SYSIO;
+               (*ptr)++;
+               break;
+       }
+}
+
+static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
+{
+       ctx->ctx->reg_block = U16(*ptr);
+       (*ptr) += 2;
+       ATOM_SDEBUG_PRINT("   base: 0x%04X\n", ctx->ctx->reg_block);
+}
+
+static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++), shift;
+       uint32_t saved, dst;
+       int dptr = *ptr;
+       attr &= 0x38;
+       attr |= atom_def_dst[attr >> 3] << 6;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
+       ATOM_SDEBUG_PRINT("   shift: %d\n", shift);
+       dst <<= shift;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++), shift;
+       uint32_t saved, dst;
+       int dptr = *ptr;
+       attr &= 0x38;
+       attr |= atom_def_dst[attr >> 3] << 6;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
+       ATOM_SDEBUG_PRINT("   shift: %d\n", shift);
+       dst >>= shift;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++), shift;
+       uint32_t saved, dst;
+       int dptr = *ptr;
+       uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       /* op needs to full dst value */
+       dst = saved;
+       shift = atom_get_src(ctx, attr, ptr);
+       ATOM_SDEBUG_PRINT("   shift: %d\n", shift);
+       dst <<= shift;
+       dst &= atom_arg_mask[dst_align];
+       dst >>= atom_arg_shift[dst_align];
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++), shift;
+       uint32_t saved, dst;
+       int dptr = *ptr;
+       uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       /* op needs to full dst value */
+       dst = saved;
+       shift = atom_get_src(ctx, attr, ptr);
+       ATOM_SDEBUG_PRINT("   shift: %d\n", shift);
+       dst >>= shift;
+       dst &= atom_arg_mask[dst_align];
+       dst >>= atom_arg_shift[dst_align];
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, src, saved;
+       int dptr = *ptr;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       ATOM_SDEBUG_PRINT("   src: ");
+       src = atom_get_src(ctx, attr, ptr);
+       dst -= src;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t src, val, target;
+       ATOM_SDEBUG_PRINT("   switch: ");
+       src = atom_get_src(ctx, attr, ptr);
+       while (U16(*ptr) != ATOM_CASE_END)
+               if (U8(*ptr) == ATOM_CASE_MAGIC) {
+                       (*ptr)++;
+                       ATOM_SDEBUG_PRINT("   case: ");
+                       val =
+                           atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
+                                        ptr);
+                       target = U16(*ptr);
+                       if (val == src) {
+                               ATOM_SDEBUG_PRINT("   target: %04X\n", target);
+                               *ptr = ctx->start + target;
+                               return;
+                       }
+                       (*ptr) += 2;
+               } else {
+                       DRM_INFO("Bad case.\n");
+                       return;
+               }
+       (*ptr) += 2;
+}
+
+static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, src;
+       ATOM_SDEBUG_PRINT("   src1: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+       ATOM_SDEBUG_PRINT("   src2: ");
+       src = atom_get_src(ctx, attr, ptr);
+       ctx->ctx->cs_equal = ((dst & src) == 0);
+       ATOM_SDEBUG_PRINT("   result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
+}
+
+static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
+{
+       uint8_t attr = U8((*ptr)++);
+       uint32_t dst, src, saved;
+       int dptr = *ptr;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+       ATOM_SDEBUG_PRINT("   src: ");
+       src = atom_get_src(ctx, attr, ptr);
+       dst ^= src;
+       ATOM_SDEBUG_PRINT("   dst: ");
+       atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
+{
+       DRM_INFO("unimplemented!\n");
+}
+
+static struct {
+       void (*func) (atom_exec_context *, int *, int);
+       int arg;
+} opcode_table[ATOM_OP_CNT] = {
+       {
+       NULL, 0}, {
+       atom_op_move, ATOM_ARG_REG}, {
+       atom_op_move, ATOM_ARG_PS}, {
+       atom_op_move, ATOM_ARG_WS}, {
+       atom_op_move, ATOM_ARG_FB}, {
+       atom_op_move, ATOM_ARG_PLL}, {
+       atom_op_move, ATOM_ARG_MC}, {
+       atom_op_and, ATOM_ARG_REG}, {
+       atom_op_and, ATOM_ARG_PS}, {
+       atom_op_and, ATOM_ARG_WS}, {
+       atom_op_and, ATOM_ARG_FB}, {
+       atom_op_and, ATOM_ARG_PLL}, {
+       atom_op_and, ATOM_ARG_MC}, {
+       atom_op_or, ATOM_ARG_REG}, {
+       atom_op_or, ATOM_ARG_PS}, {
+       atom_op_or, ATOM_ARG_WS}, {
+       atom_op_or, ATOM_ARG_FB}, {
+       atom_op_or, ATOM_ARG_PLL}, {
+       atom_op_or, ATOM_ARG_MC}, {
+       atom_op_shift_left, ATOM_ARG_REG}, {
+       atom_op_shift_left, ATOM_ARG_PS}, {
+       atom_op_shift_left, ATOM_ARG_WS}, {
+       atom_op_shift_left, ATOM_ARG_FB}, {
+       atom_op_shift_left, ATOM_ARG_PLL}, {
+       atom_op_shift_left, ATOM_ARG_MC}, {
+       atom_op_shift_right, ATOM_ARG_REG}, {
+       atom_op_shift_right, ATOM_ARG_PS}, {
+       atom_op_shift_right, ATOM_ARG_WS}, {
+       atom_op_shift_right, ATOM_ARG_FB}, {
+       atom_op_shift_right, ATOM_ARG_PLL}, {
+       atom_op_shift_right, ATOM_ARG_MC}, {
+       atom_op_mul, ATOM_ARG_REG}, {
+       atom_op_mul, ATOM_ARG_PS}, {
+       atom_op_mul, ATOM_ARG_WS}, {
+       atom_op_mul, ATOM_ARG_FB}, {
+       atom_op_mul, ATOM_ARG_PLL}, {
+       atom_op_mul, ATOM_ARG_MC}, {
+       atom_op_div, ATOM_ARG_REG}, {
+       atom_op_div, ATOM_ARG_PS}, {
+       atom_op_div, ATOM_ARG_WS}, {
+       atom_op_div, ATOM_ARG_FB}, {
+       atom_op_div, ATOM_ARG_PLL}, {
+       atom_op_div, ATOM_ARG_MC}, {
+       atom_op_add, ATOM_ARG_REG}, {
+       atom_op_add, ATOM_ARG_PS}, {
+       atom_op_add, ATOM_ARG_WS}, {
+       atom_op_add, ATOM_ARG_FB}, {
+       atom_op_add, ATOM_ARG_PLL}, {
+       atom_op_add, ATOM_ARG_MC}, {
+       atom_op_sub, ATOM_ARG_REG}, {
+       atom_op_sub, ATOM_ARG_PS}, {
+       atom_op_sub, ATOM_ARG_WS}, {
+       atom_op_sub, ATOM_ARG_FB}, {
+       atom_op_sub, ATOM_ARG_PLL}, {
+       atom_op_sub, ATOM_ARG_MC}, {
+       atom_op_setport, ATOM_PORT_ATI}, {
+       atom_op_setport, ATOM_PORT_PCI}, {
+       atom_op_setport, ATOM_PORT_SYSIO}, {
+       atom_op_setregblock, 0}, {
+       atom_op_setfbbase, 0}, {
+       atom_op_compare, ATOM_ARG_REG}, {
+       atom_op_compare, ATOM_ARG_PS}, {
+       atom_op_compare, ATOM_ARG_WS}, {
+       atom_op_compare, ATOM_ARG_FB}, {
+       atom_op_compare, ATOM_ARG_PLL}, {
+       atom_op_compare, ATOM_ARG_MC}, {
+       atom_op_switch, 0}, {
+       atom_op_jump, ATOM_COND_ALWAYS}, {
+       atom_op_jump, ATOM_COND_EQUAL}, {
+       atom_op_jump, ATOM_COND_BELOW}, {
+       atom_op_jump, ATOM_COND_ABOVE}, {
+       atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
+       atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
+       atom_op_jump, ATOM_COND_NOTEQUAL}, {
+       atom_op_test, ATOM_ARG_REG}, {
+       atom_op_test, ATOM_ARG_PS}, {
+       atom_op_test, ATOM_ARG_WS}, {
+       atom_op_test, ATOM_ARG_FB}, {
+       atom_op_test, ATOM_ARG_PLL}, {
+       atom_op_test, ATOM_ARG_MC}, {
+       atom_op_delay, ATOM_UNIT_MILLISEC}, {
+       atom_op_delay, ATOM_UNIT_MICROSEC}, {
+       atom_op_calltable, 0}, {
+       atom_op_repeat, 0}, {
+       atom_op_clear, ATOM_ARG_REG}, {
+       atom_op_clear, ATOM_ARG_PS}, {
+       atom_op_clear, ATOM_ARG_WS}, {
+       atom_op_clear, ATOM_ARG_FB}, {
+       atom_op_clear, ATOM_ARG_PLL}, {
+       atom_op_clear, ATOM_ARG_MC}, {
+       atom_op_nop, 0}, {
+       atom_op_eot, 0}, {
+       atom_op_mask, ATOM_ARG_REG}, {
+       atom_op_mask, ATOM_ARG_PS}, {
+       atom_op_mask, ATOM_ARG_WS}, {
+       atom_op_mask, ATOM_ARG_FB}, {
+       atom_op_mask, ATOM_ARG_PLL}, {
+       atom_op_mask, ATOM_ARG_MC}, {
+       atom_op_postcard, 0}, {
+       atom_op_beep, 0}, {
+       atom_op_savereg, 0}, {
+       atom_op_restorereg, 0}, {
+       atom_op_setdatablock, 0}, {
+       atom_op_xor, ATOM_ARG_REG}, {
+       atom_op_xor, ATOM_ARG_PS}, {
+       atom_op_xor, ATOM_ARG_WS}, {
+       atom_op_xor, ATOM_ARG_FB}, {
+       atom_op_xor, ATOM_ARG_PLL}, {
+       atom_op_xor, ATOM_ARG_MC}, {
+       atom_op_shl, ATOM_ARG_REG}, {
+       atom_op_shl, ATOM_ARG_PS}, {
+       atom_op_shl, ATOM_ARG_WS}, {
+       atom_op_shl, ATOM_ARG_FB}, {
+       atom_op_shl, ATOM_ARG_PLL}, {
+       atom_op_shl, ATOM_ARG_MC}, {
+       atom_op_shr, ATOM_ARG_REG}, {
+       atom_op_shr, ATOM_ARG_PS}, {
+       atom_op_shr, ATOM_ARG_WS}, {
+       atom_op_shr, ATOM_ARG_FB}, {
+       atom_op_shr, ATOM_ARG_PLL}, {
+       atom_op_shr, ATOM_ARG_MC}, {
+atom_op_debug, 0},};
+
+static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
+{
+       int base = CU16(ctx->cmd_table + 4 + 2 * index);
+       int len, ws, ps, ptr;
+       unsigned char op;
+       atom_exec_context ectx;
+       int ret = 0;
+
+       if (!base)
+               return -EINVAL;
+
+       len = CU16(base + ATOM_CT_SIZE_PTR);
+       ws = CU8(base + ATOM_CT_WS_PTR);
+       ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
+       ptr = base + ATOM_CT_CODE_PTR;
+
+       ATOM_SDEBUG_PRINT(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
+
+       ectx.ctx = ctx;
+       ectx.ps_shift = ps / 4;
+       ectx.start = base;
+       ectx.ps = params;
+       ectx.abort = false;
+       ectx.last_jump = 0;
+       if (ws)
+               ectx.ws = kmalloc(4 * ws, DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
+       else
+               ectx.ws = NULL;
+
+       debug_depth++;
+       while (1) {
+               op = CU8(ptr++);
+               if (op < ATOM_OP_NAMES_CNT)
+                       ATOM_SDEBUG_PRINT("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
+               else
+                       ATOM_SDEBUG_PRINT("[%d] @ 0x%04X\n", op, ptr - 1);
+               if (ectx.abort) {
+                       DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
+                               base, len, ws, ps, ptr - 1);
+                       ret = -EINVAL;
+                       goto free;
+               }
+
+               if (op < ATOM_OP_CNT && op > 0)
+                       opcode_table[op].func(&ectx, &ptr,
+                                             opcode_table[op].arg);
+               else
+                       break;
+
+               if (op == ATOM_OP_EOT)
+                       break;
+       }
+       debug_depth--;
+       ATOM_SDEBUG_PRINT("<<\n");
+
+free:
+       if (ws)
+               drm_free(ectx.ws, DRM_MEM_DRIVER);
+       return ret;
+}
+
+int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
+{
+       int r;
+
+       spin_lock(&ctx->mutex);
+       /* reset reg block */
+       ctx->reg_block = 0;
+       /* reset fb window */
+       ctx->fb_base = 0;
+       /* reset io mode */
+       ctx->io_mode = ATOM_IO_MM;
+       r = atom_execute_table_locked(ctx, index, params);
+       spin_unlock(&ctx->mutex);
+       return r;
+}
+
+static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
+
+static void atom_index_iio(struct atom_context *ctx, int base)
+{
+       ctx->iio = kmalloc(2 * 256, DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
+       while (CU8(base) == ATOM_IIO_START) {
+               ctx->iio[CU8(base + 1)] = base + 2;
+               base += 2;
+               while (CU8(base) != ATOM_IIO_END)
+                       base += atom_iio_len[CU8(base)];
+               base += 3;
+       }
+}
+
+struct atom_context *atom_parse(struct card_info *card, void *bios)
+{
+       int base;
+       struct atom_context *ctx =
+           kmalloc(sizeof(struct atom_context), DRM_MEM_DRIVER,
+                   M_ZERO | M_WAITOK);
+       char *str;
+       char name[512];
+       int i;
+
+       if (!ctx)
+               return NULL;
+
+       ctx->card = card;
+       ctx->bios = bios;
+
+       if (CU16(0) != ATOM_BIOS_MAGIC) {
+               DRM_INFO("Invalid BIOS magic.\n");
+               drm_free(ctx, DRM_MEM_DRIVER);
+               return NULL;
+       }
+       if (strncmp
+           (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
+            strlen(ATOM_ATI_MAGIC))) {
+               DRM_INFO("Invalid ATI magic.\n");
+               drm_free(ctx, DRM_MEM_DRIVER);
+               return NULL;
+       }
+
+       base = CU16(ATOM_ROM_TABLE_PTR);
+       if (strncmp
+           (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
+            strlen(ATOM_ROM_MAGIC))) {
+               DRM_INFO("Invalid ATOM magic.\n");
+               drm_free(ctx, DRM_MEM_DRIVER);
+               return NULL;
+       }
+
+       ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
+       ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
+       atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
+
+       str = CSTR(CU16(base + ATOM_ROM_MSG_PTR));
+       while (*str && ((*str == '\n') || (*str == '\r')))
+               str++;
+       /* name string isn't always 0 terminated */
+       for (i = 0; i < 511; i++) {
+               name[i] = str[i];
+               if (name[i] < '.' || name[i] > 'z') {
+                       name[i] = 0;
+                       break;
+               }
+       }
+       DRM_INFO("ATOM BIOS: %s\n", name);
+
+       return ctx;
+}
+
+int atom_asic_init(struct atom_context *ctx)
+{
+       struct radeon_device *rdev = ctx->card->dev->dev_private;
+       int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
+       uint32_t ps[16];
+       int ret;
+
+       memset(ps, 0, 64);
+
+       ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
+       ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
+       if (!ps[0] || !ps[1])
+               return 1;
+
+       if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
+               return 1;
+       ret = atom_execute_table(ctx, ATOM_CMD_INIT, ps);
+       if (ret)
+               return ret;
+
+       memset(ps, 0, 64);
+
+       if (rdev->family < CHIP_R600) {
+               if (CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_SPDFANCNTL))
+                       atom_execute_table(ctx, ATOM_CMD_SPDFANCNTL, ps);
+       }
+       return ret;
+}
+
+void atom_destroy(struct atom_context *ctx)
+{
+       if (ctx->iio)
+               drm_free(ctx->iio, DRM_MEM_DRIVER);
+       drm_free(ctx, DRM_MEM_DRIVER);
+}
+
+bool atom_parse_data_header(struct atom_context *ctx, int index,
+                           uint16_t * size, uint8_t * frev, uint8_t * crev,
+                           uint16_t * data_start)
+{
+       int offset = index * 2 + 4;
+       int idx = CU16(ctx->data_table + offset);
+       u16 *mdt = (u16 *)((char *)ctx->bios + ctx->data_table + 4);
+
+       if (!mdt[index])
+               return false;
+
+       if (size)
+               *size = CU16(idx);
+       if (frev)
+               *frev = CU8(idx + 2);
+       if (crev)
+               *crev = CU8(idx + 3);
+       *data_start = idx;
+       return true;
+}
+
+bool atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
+                          uint8_t * crev)
+{
+       int offset = index * 2 + 4;
+       int idx = CU16(ctx->cmd_table + offset);
+       u16 *mct = (u16 *)((char *)ctx->bios + ctx->cmd_table + 4);
+
+       if (!mct[index])
+               return false;
+
+       if (frev)
+               *frev = CU8(idx + 2);
+       if (crev)
+               *crev = CU8(idx + 3);
+       return true;
+}
+
+int atom_allocate_fb_scratch(struct atom_context *ctx)
+{
+       int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);
+       uint16_t data_offset;
+       int usage_bytes = 0;
+       struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;
+
+       if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
+               firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)((char *)ctx->bios + data_offset);
+
+               DRM_DEBUG("atom firmware requested %08x %dkb\n",
+                         firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware,
+                         firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);
+
+               usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024;
+       }
+       ctx->scratch_size_bytes = 0;
+       if (usage_bytes == 0)
+               usage_bytes = 20 * 1024;
+       /* allocate some scratch memory */
+       ctx->scratch = kmalloc(usage_bytes, DRM_MEM_DRIVER, M_ZERO | M_WAITOK);
+       if (!ctx->scratch)
+               return -ENOMEM;
+       ctx->scratch_size_bytes = usage_bytes;
+       return 0;
+}
diff --git a/sys/dev/drm/radeon/atom.h b/sys/dev/drm/radeon/atom.h
new file mode 100644 (file)
index 0000000..2553c0c
--- /dev/null
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Stanislaw Skowronek
+ *
+ * $FreeBSD: head/sys/dev/drm2/radeon/atom.h 254885 2013-08-25 19:37:15Z dumbbell $
+ */
+
+#ifndef ATOM_H
+#define ATOM_H
+
+#include <drm/drmP.h>
+
+#define ATOM_BIOS_MAGIC                0xAA55
+#define ATOM_ATI_MAGIC_PTR     0x30
+#define ATOM_ATI_MAGIC         " 761295520"
+#define ATOM_ROM_TABLE_PTR     0x48
+
+#define ATOM_ROM_MAGIC         "ATOM"
+#define ATOM_ROM_MAGIC_PTR     4
+
+#define ATOM_ROM_MSG_PTR       0x10
+#define ATOM_ROM_CMD_PTR       0x1E
+#define ATOM_ROM_DATA_PTR      0x20
+
+#define ATOM_CMD_INIT          0
+#define ATOM_CMD_SETSCLK       0x0A
+#define ATOM_CMD_SETMCLK       0x0B
+#define ATOM_CMD_SETPCLK       0x0C
+#define ATOM_CMD_SPDFANCNTL    0x39
+
+#define ATOM_DATA_FWI_PTR      0xC
+#define ATOM_DATA_IIO_PTR      0x32
+
+#define ATOM_FWI_DEFSCLK_PTR   8
+#define ATOM_FWI_DEFMCLK_PTR   0xC
+#define ATOM_FWI_MAXSCLK_PTR   0x24
+#define ATOM_FWI_MAXMCLK_PTR   0x28
+
+#define ATOM_CT_SIZE_PTR       0
+#define ATOM_CT_WS_PTR         4
+#define ATOM_CT_PS_PTR         5
+#define ATOM_CT_PS_MASK                0x7F
+#define ATOM_CT_CODE_PTR       6
+
+#define ATOM_OP_CNT            123
+#define ATOM_OP_EOT            91
+
+#define ATOM_CASE_MAGIC                0x63
+#define ATOM_CASE_END          0x5A5A
+
+#define ATOM_ARG_REG           0
+#define ATOM_ARG_PS            1
+#define ATOM_ARG_WS            2
+#define ATOM_ARG_FB            3
+#define ATOM_ARG_ID            4
+#define ATOM_ARG_IMM           5
+#define ATOM_ARG_PLL           6
+#define ATOM_ARG_MC            7
+
+#define ATOM_SRC_DWORD         0
+#define ATOM_SRC_WORD0         1
+#define ATOM_SRC_WORD8         2
+#define ATOM_SRC_WORD16                3
+#define ATOM_SRC_BYTE0         4
+#define ATOM_SRC_BYTE8         5
+#define ATOM_SRC_BYTE16                6
+#define ATOM_SRC_BYTE24                7
+
+#define ATOM_WS_QUOTIENT       0x40
+#define ATOM_WS_REMAINDER      0x41
+#define ATOM_WS_DATAPTR                0x42
+#define ATOM_WS_SHIFT          0x43
+#define ATOM_WS_OR_MASK                0x44
+#define ATOM_WS_AND_MASK       0x45
+#define ATOM_WS_FB_WINDOW      0x46
+#define ATOM_WS_ATTRIBUTES     0x47
+#define ATOM_WS_REGPTR         0x48
+
+#define ATOM_IIO_NOP           0
+#define ATOM_IIO_START         1
+#define ATOM_IIO_READ          2
+#define ATOM_IIO_WRITE         3
+#define ATOM_IIO_CLEAR         4
+#define ATOM_IIO_SET           5
+#define ATOM_IIO_MOVE_INDEX    6
+#define ATOM_IIO_MOVE_ATTR     7
+#define ATOM_IIO_MOVE_DATA     8
+#define ATOM_IIO_END           9
+
+#define ATOM_IO_MM             0
+#define ATOM_IO_PCI            1
+#define ATOM_IO_SYSIO          2
+#define ATOM_IO_IIO            0x80
+
+struct card_info {
+       struct drm_device *dev;
+       void (* reg_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
+        uint32_t (* reg_read)(struct card_info *, uint32_t);          /*  filled by driver */
+       void (* ioreg_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
+        uint32_t (* ioreg_read)(struct card_info *, uint32_t);          /*  filled by driver */
+       void (* mc_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
+        uint32_t (* mc_read)(struct card_info *, uint32_t);          /*  filled by driver */
+       void (* pll_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
+        uint32_t (* pll_read)(struct card_info *, uint32_t);          /*  filled by driver */
+};
+
+struct atom_context {
+       struct card_info *card;
+       struct lock mutex;
+       void *bios;
+       uint32_t cmd_table, data_table;
+       uint16_t *iio;
+
+       uint16_t data_block;
+       uint32_t fb_base;
+       uint32_t divmul[2];
+       uint16_t io_attr;
+       uint16_t reg_block;
+       uint8_t shift;
+       int cs_equal, cs_above;
+       int io_mode;
+       uint32_t *scratch;
+       int scratch_size_bytes;
+};
+
+extern int atom_debug;
+
+struct atom_context *atom_parse(struct card_info *, void *);
+int atom_execute_table(struct atom_context *, int, uint32_t *);
+int atom_asic_init(struct atom_context *);
+void atom_destroy(struct atom_context *);
+bool atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size,
+                           uint8_t *frev, uint8_t *crev, uint16_t *data_start);
+bool atom_parse_cmd_header(struct atom_context *ctx, int index,
+                          uint8_t *frev, uint8_t *crev);
+int atom_allocate_fb_scratch(struct atom_context *ctx);
+#include "atom-types.h"
+#include "atombios.h"
+#include "ObjectID.h"
+
+#endif
diff --git a/sys/dev/drm/radeon/atombios.h b/sys/dev/drm/radeon/atombios.h
new file mode 100644 (file)
index 0000000..5b506b3
--- /dev/null
@@ -0,0 +1,8012 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.  
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * $FreeBSD: head/sys/dev/drm2/radeon/atombios.h 254885 2013-08-25 19:37:15Z dumbbell $
+ */
+
+
+/****************************************************************************/ 
+/*Portion I: Definitions  shared between VBIOS and Driver                   */
+/****************************************************************************/
+
+
+#ifndef _ATOMBIOS_H
+#define _ATOMBIOS_H
+
+#define ATOM_VERSION_MAJOR                   0x00020000
+#define ATOM_VERSION_MINOR                   0x00000002
+
+#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
+
+/* Endianness should be specified before inclusion,
+ * default to little endian
+ */
+#ifndef ATOM_BIG_ENDIAN
+#error Endian not specified
+#endif
+
+#ifdef _H2INC
+  #ifndef ULONG 
+    typedef unsigned long ULONG;
+  #endif
+
+  #ifndef UCHAR
+    typedef unsigned char UCHAR;
+  #endif
+
+  #ifndef USHORT 
+    typedef unsigned short USHORT;
+  #endif
+#endif
+      
+#define ATOM_DAC_A            0 
+#define ATOM_DAC_B            1
+#define ATOM_EXT_DAC          2
+
+#define ATOM_CRTC1            0
+#define ATOM_CRTC2            1
+#define ATOM_CRTC3            2
+#define ATOM_CRTC4            3
+#define ATOM_CRTC5            4
+#define ATOM_CRTC6            5
+#define ATOM_CRTC_INVALID     0xFF
+
+#define ATOM_DIGA             0
+#define ATOM_DIGB             1
+
+#define ATOM_PPLL1            0
+#define ATOM_PPLL2            1
+#define ATOM_DCPLL            2
+#define ATOM_PPLL0            2
+#define ATOM_EXT_PLL1         8
+#define ATOM_EXT_PLL2         9
+#define ATOM_EXT_CLOCK        10
+#define ATOM_PPLL_INVALID     0xFF
+
+#define ENCODER_REFCLK_SRC_P1PLL       0       
+#define ENCODER_REFCLK_SRC_P2PLL       1
+#define ENCODER_REFCLK_SRC_DCPLL       2
+#define ENCODER_REFCLK_SRC_EXTCLK      3
+#define ENCODER_REFCLK_SRC_INVALID     0xFF
+
+#define ATOM_SCALER1          0
+#define ATOM_SCALER2          1
+
+#define ATOM_SCALER_DISABLE   0   
+#define ATOM_SCALER_CENTER    1   
+#define ATOM_SCALER_EXPANSION 2   
+#define ATOM_SCALER_MULTI_EX  3   
+
+#define ATOM_DISABLE          0
+#define ATOM_ENABLE           1
+#define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
+#define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
+#define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
+#define ATOM_LCD_SELFTEST_START                                                                        (ATOM_DISABLE+5)
+#define ATOM_LCD_SELFTEST_STOP                                                                 (ATOM_ENABLE+5)
+#define ATOM_ENCODER_INIT                                        (ATOM_DISABLE+7)
+#define ATOM_INIT                                                (ATOM_DISABLE+7)
+#define ATOM_GET_STATUS                         (ATOM_DISABLE+8)
+
+#define ATOM_BLANKING         1
+#define ATOM_BLANKING_OFF     0
+
+#define ATOM_CURSOR1          0
+#define ATOM_CURSOR2          1
+
+#define ATOM_ICON1            0
+#define ATOM_ICON2            1
+
+#define ATOM_CRT1             0
+#define ATOM_CRT2             1
+
+#define ATOM_TV_NTSC          1
+#define ATOM_TV_NTSCJ         2
+#define ATOM_TV_PAL           3
+#define ATOM_TV_PALM          4
+#define ATOM_TV_PALCN         5
+#define ATOM_TV_PALN          6
+#define ATOM_TV_PAL60         7
+#define ATOM_TV_SECAM         8
+#define ATOM_TV_CV            16
+
+#define ATOM_DAC1_PS2         1
+#define ATOM_DAC1_CV          2
+#define ATOM_DAC1_NTSC        3
+#define ATOM_DAC1_PAL         4
+
+#define ATOM_DAC2_PS2         ATOM_DAC1_PS2
+#define ATOM_DAC2_CV          ATOM_DAC1_CV
+#define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
+#define ATOM_DAC2_PAL         ATOM_DAC1_PAL
+#define ATOM_PM_ON            0
+#define ATOM_PM_STANDBY       1
+#define ATOM_PM_SUSPEND       2
+#define ATOM_PM_OFF           3
+
+/* Bit0:{=0:single, =1:dual},
+   Bit1 {=0:666RGB, =1:888RGB},
+   Bit2:3:{Grey level}
+   Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
+
+#define ATOM_PANEL_MISC_DUAL               0x00000001
+#define ATOM_PANEL_MISC_888RGB             0x00000002
+#define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
+#define ATOM_PANEL_MISC_FPDI               0x00000010
+#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
+#define ATOM_PANEL_MISC_SPATIAL            0x00000020
+#define ATOM_PANEL_MISC_TEMPORAL           0x00000040
+#define ATOM_PANEL_MISC_API_ENABLED        0x00000080
+
+
+#define MEMTYPE_DDR1              "DDR1"
+#define MEMTYPE_DDR2              "DDR2"
+#define MEMTYPE_DDR3              "DDR3"
+#define MEMTYPE_DDR4              "DDR4"
+
+#define ASIC_BUS_TYPE_PCI         "PCI"
+#define ASIC_BUS_TYPE_AGP         "AGP"
+#define ASIC_BUS_TYPE_PCIE        "PCI_EXPRESS"
+
+/* Maximum size of that FireGL flag string */
+
+#define ATOM_FIREGL_FLAG_STRING     "FGL"             //Flag used to enable FireGL Support
+#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3        //sizeof( ATOM_FIREGL_FLAG_STRING )
+
+#define ATOM_FAKE_DESKTOP_STRING    "DSK"             //Flag used to enable mobile ASIC on Desktop
+#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 
+
+#define ATOM_M54T_FLAG_STRING       "M54T"            //Flag used to enable M54T Support
+#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4        //sizeof( ATOM_M54T_FLAG_STRING )
+
+#define HW_ASSISTED_I2C_STATUS_FAILURE          2
+#define HW_ASSISTED_I2C_STATUS_SUCCESS          1
+
+#pragma pack(1)                                       /* BIOS data must use byte aligment */
+
+/*  Define offset to location of ROM header. */
+
+#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER           0x00000048L
+#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE                              0x00000002L
+
+#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94
+#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20    /* including the terminator 0x0! */
+#define        OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER           0x002f
+#define        OFFSET_TO_GET_ATOMBIOS_STRINGS_START            0x006e
+
+/* Common header for all ROM Data tables.
+  Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header. 
+  And the pointer actually points to this header. */
+
+typedef struct _ATOM_COMMON_TABLE_HEADER
+{
+  USHORT usStructureSize;
+  UCHAR  ucTableFormatRevision;   /*Change it when the Parser is not backward compatible */
+  UCHAR  ucTableContentRevision;  /*Change it only when the table needs to change but the firmware */
+                                  /*Image can't be updated, while Driver needs to carry the new table! */
+}ATOM_COMMON_TABLE_HEADER;
+
+/****************************************************************************/ 
+// Structure stores the ROM header.
+/****************************************************************************/ 
+typedef struct _ATOM_ROM_HEADER
+{
+  ATOM_COMMON_TABLE_HEADER             sHeader;
+  UCHAR         uaFirmWareSignature[4];    /*Signature to distinguish between Atombios and non-atombios, 
+                                      atombios should init it as "ATOM", don't change the position */
+  USHORT usBiosRuntimeSegmentAddress;
+  USHORT usProtectedModeInfoOffset;
+  USHORT usConfigFilenameOffset;
+  USHORT usCRC_BlockOffset;
+  USHORT usBIOS_BootupMessageOffset;
+  USHORT usInt10Offset;
+  USHORT usPciBusDevInitCode;
+  USHORT usIoBaseAddress;
+  USHORT usSubsystemVendorID;
+  USHORT usSubsystemID;
+  USHORT usPCI_InfoOffset; 
+  USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
+  USHORT usMasterDataTableOffset;   /*Offset for SW to get all data table offsets, Don't change the position */
+  UCHAR  ucExtendedFunctionCode;
+  UCHAR  ucReserved;
+}ATOM_ROM_HEADER;
+
+/*==============================Command Table Portion==================================== */
+
+#ifdef UEFI_BUILD
+       #define UTEMP   USHORT
+       #define USHORT  void*
+#endif
+
+/****************************************************************************/ 
+// Structures used in Command.mtb 
+/****************************************************************************/ 
+typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
+  USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
+  USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
+  USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
+  USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
+  USHORT DIGxEncoderControl;                                                                            //Only used by Bios
+  USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
+  USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
+  USHORT MemoryParamAdjust;                                                                             //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
+  USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
+  USHORT GPIOPinControl;                                                                                                //Atomic Table,  only used by Bios
+  USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
+  USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
+  USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2  
+  USHORT EnableDispPowerGating;                  //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
+  USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
+  USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
+  USHORT MemoryPLLInit;                          //Atomic Table,  used only by Bios
+  USHORT AdjustDisplayPll;                                                                                      //Atomic Table,  used by various SW componentes. 
+  USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock                
+  USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
+  USHORT ASIC_StaticPwrMgtStatusChange;          //Obsolete ,     only used by Bios   
+  USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2  
+  USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
+  USHORT HW_Misc_Operation;                      //Atomic Table,  directly used by various SW components,latest version 1.1 
+  USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1  
+  USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1 
+  USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1 
+  USHORT CV1OutputControl;                       //Atomic Table,  Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead 
+  USHORT GetConditionalGoldenSetting;            //Only used by Bios
+  USHORT TVEncoderControl;                       //Function Table,directly used by various SW components,latest version 1.1
+  USHORT PatchMCSetting;                         //only used by BIOS
+  USHORT MC_SEQ_Control;                         //only used by BIOS
+  USHORT TV1OutputControl;                       //Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead
+  USHORT EnableScaler;                           //Atomic Table,  used only by Bios
+  USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1 
+  USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1 
+  USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1 
+  USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
+  USHORT GetSCLKOverMCLKRatio;                   //Atomic Table,  only used by Bios
+  USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
+  USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1 
+  USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
+  USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1 
+  USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
+  USHORT UpdateCRTC_DoubleBufferRegisters;                      //Atomic Table,  used only by Bios
+  USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
+  USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
+  USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1 
+  USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1 
+  USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
+  USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
+  USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
+  USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
+  USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios    
+  USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
+  USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components 
+  USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
+  USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
+  USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
+  USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
+  USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
+  USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
+  USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
+  USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
+  USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
+  USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
+  USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
+  USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
+  USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
+  USHORT DAC2OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
+  USHORT ComputeMemoryClockParam;                //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
+  USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
+  USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
+  USHORT GetDispObjectInfo;                      //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
+  USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
+  USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
+  USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
+  USHORT DIG2TransmitterControl;                      //Atomic Table,directly used by various SW components,latest version 1.1 
+  USHORT ProcessAuxChannelTransaction;                                  //Function Table,only used by Bios
+  USHORT DPEncoderService;                                                                                      //Function Table,only used by Bios
+  USHORT GetVoltageInfo;                         //Function Table,only used by Bios since SI
+}ATOM_MASTER_LIST_OF_COMMAND_TABLES;   
+
+// For backward compatible 
+#define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
+#define DPTranslatorControl                      DIG2EncoderControl
+#define UNIPHYTransmitterControl                            DIG1TransmitterControl
+#define LVTMATransmitterControl                                     DIG2TransmitterControl
+#define SetCRTC_DPM_State                        GetConditionalGoldenSetting
+#define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange
+#define HPDInterruptService                      ReadHWAssistedI2CStatus
+#define EnableVGA_Access                         GetSCLKOverMCLKRatio
+#define EnableYUV                                GetDispObjectInfo                         
+#define DynamicClockGating                       EnableDispPowerGating
+#define SetupHWAssistedI2CStatus                 ComputeMemoryClockParam
+
+#define TMDSAEncoderControl                      PatchMCSetting
+#define LVDSEncoderControl                       MC_SEQ_Control
+#define LCD1OutputControl                        HW_Misc_Operation
+
+
+typedef struct _ATOM_MASTER_COMMAND_TABLE
+{
+  ATOM_COMMON_TABLE_HEADER           sHeader;
+  ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
+}ATOM_MASTER_COMMAND_TABLE;
+
+/****************************************************************************/ 
+// Structures used in every command table
+/****************************************************************************/ 
+typedef struct _ATOM_TABLE_ATTRIBUTE
+{
+#if ATOM_BIG_ENDIAN
+  USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
+  USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
+  USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
+#else
+  USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
+  USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
+  USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
+#endif
+}ATOM_TABLE_ATTRIBUTE;
+
+typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
+{
+  ATOM_TABLE_ATTRIBUTE sbfAccess;
+  USHORT               susAccess;
+}ATOM_TABLE_ATTRIBUTE_ACCESS;
+
+/****************************************************************************/ 
+// Common header for all command tables.
+// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 
+// And the pointer actually points to this header.
+/****************************************************************************/ 
+typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
+{
+  ATOM_COMMON_TABLE_HEADER CommonHeader;
+  ATOM_TABLE_ATTRIBUTE     TableAttribute;     
+}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
+
+/****************************************************************************/ 
+// Structures used by ComputeMemoryEnginePLLTable
+/****************************************************************************/ 
+#define COMPUTE_MEMORY_PLL_PARAM        1
+#define COMPUTE_ENGINE_PLL_PARAM        2
+#define ADJUST_MC_SETTING_PARAM         3
+
+/****************************************************************************/ 
+// Structures used by AdjustMemoryControllerTable
+/****************************************************************************/ 
+typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
+{
+#if ATOM_BIG_ENDIAN
+  ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 
+  ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
+  ULONG ulClockFreq:24;
+#else
+  ULONG ulClockFreq:24;
+  ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
+  ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 
+#endif
+}ATOM_ADJUST_MEMORY_CLOCK_FREQ;
+#define POINTER_RETURN_FLAG             0x80
+
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
+{
+  ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
+  UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine  
+  UCHAR   ucReserved;     //may expand to return larger Fbdiv later
+  UCHAR   ucFbDiv;        //return value
+  UCHAR   ucPostDiv;      //return value
+}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
+
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
+{
+  ULONG   ulClock;        //When return, [23:0] return real clock 
+  UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
+  USHORT  usFbDiv;                 //return Feedback value to be written to register
+  UCHAR   ucPostDiv;      //return post div to be written to register
+}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
+#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
+
+
+#define SET_CLOCK_FREQ_MASK                     0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
+#define USE_NON_BUS_CLOCK_MASK                  0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
+#define USE_MEMORY_SELF_REFRESH_MASK            0x02000000     //Only applicable to memory clock change, when set, using memory self refresh during clock transition
+#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
+#define FIRST_TIME_CHANGE_CLOCK                                                                        0x08000000      //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
+#define SKIP_SW_PROGRAM_PLL                                                                                    0x10000000      //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
+#define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK
+
+#define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
+#define b3USE_MEMORY_SELF_REFRESH                 0x02      //Only applicable to memory clock change, when set, using memory self refresh during clock transition
+#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
+#define b3FIRST_TIME_CHANGE_CLOCK                                                                      0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
+#define b3SKIP_SW_PROGRAM_PLL                                                                                  0x10                     //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
+
+typedef struct _ATOM_COMPUTE_CLOCK_FREQ
+{
+#if ATOM_BIG_ENDIAN
+  ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
+  ULONG ulClockFreq:24;                       // in unit of 10kHz
+#else
+  ULONG ulClockFreq:24;                       // in unit of 10kHz
+  ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
+#endif
+}ATOM_COMPUTE_CLOCK_FREQ;
+
+typedef struct _ATOM_S_MPLL_FB_DIVIDER
+{
+  USHORT usFbDivFrac;  
+  USHORT usFbDiv;  
+}ATOM_S_MPLL_FB_DIVIDER;
+
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
+{
+  union
+  {
+    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
+    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
+  };
+  UCHAR   ucRefDiv;                           //Output Parameter      
+  UCHAR   ucPostDiv;                          //Output Parameter      
+  UCHAR   ucCntlFlag;                         //Output Parameter      
+  UCHAR   ucReserved;
+}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
+
+// ucCntlFlag
+#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
+#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
+#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
+#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9                                               8
+
+
+// V4 are only used for APU which PLL outside GPU
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
+{
+#if ATOM_BIG_ENDIAN
+  ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
+  ULONG  ulClock:24;         //Input= target clock, output = actual clock 
+#else
+  ULONG  ulClock:24;         //Input= target clock, output = actual clock 
+  ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
+#endif
+}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
+
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
+{
+  union
+  {
+    ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
+    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
+  };
+  UCHAR   ucRefDiv;                           //Output Parameter      
+  UCHAR   ucPostDiv;                          //Output Parameter      
+  union
+  {
+    UCHAR   ucCntlFlag;                       //Output Flags
+    UCHAR   ucInputFlag;                      //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
+  };
+  UCHAR   ucReserved;                       
+}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
+
+// ucInputFlag
+#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN  1   // 1-StrobeMode, 0-PerformanceMode
+
+// use for ComputeMemoryClockParamTable
+typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
+{
+  union
+  {
+    ULONG  ulClock;         
+    ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output:UPPER_WORD=FB_DIV_INTEGER,  LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
+  };
+  UCHAR   ucDllSpeed;                         //Output 
+  UCHAR   ucPostDiv;                          //Output
+  union{
+    UCHAR   ucInputFlag;                      //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
+    UCHAR   ucPllCntlFlag;                    //Output: 
+  };
+  UCHAR   ucBWCntl;                       
+}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
+
+// definition of ucInputFlag
+#define MPLL_INPUT_FLAG_STROBE_MODE_EN          0x01
+// definition of ucPllCntlFlag
+#define MPLL_CNTL_FLAG_VCO_MODE_MASK            0x03 
+#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL            0x04
+#define MPLL_CNTL_FLAG_QDR_ENABLE               0x08
+#define MPLL_CNTL_FLAG_AD_HALF_RATE             0x10
+
+//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
+#define MPLL_CNTL_FLAG_BYPASS_AD_PLL            0x04
+
+typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
+{
+  ATOM_COMPUTE_CLOCK_FREQ ulClock;
+  ULONG ulReserved[2];
+}DYNAMICE_MEMORY_SETTINGS_PARAMETER;
+
+typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
+{
+  ATOM_COMPUTE_CLOCK_FREQ ulClock;
+  ULONG ulMemoryClock;
+  ULONG ulReserved;
+}DYNAMICE_ENGINE_SETTINGS_PARAMETER;
+
+/****************************************************************************/ 
+// Structures used by SetEngineClockTable
+/****************************************************************************/ 
+typedef struct _SET_ENGINE_CLOCK_PARAMETERS
+{
+  ULONG ulTargetEngineClock;          //In 10Khz unit
+}SET_ENGINE_CLOCK_PARAMETERS;
+
+typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
+{
+  ULONG ulTargetEngineClock;          //In 10Khz unit
+  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
+}SET_ENGINE_CLOCK_PS_ALLOCATION;
+
+/****************************************************************************/ 
+// Structures used by SetMemoryClockTable
+/****************************************************************************/ 
+typedef struct _SET_MEMORY_CLOCK_PARAMETERS
+{
+  ULONG ulTargetMemoryClock;          //In 10Khz unit
+}SET_MEMORY_CLOCK_PARAMETERS;
+
+typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
+{
+  ULONG ulTargetMemoryClock;          //In 10Khz unit
+  COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
+}SET_MEMORY_CLOCK_PS_ALLOCATION;
+
+/****************************************************************************/ 
+// Structures used by ASIC_Init.ctb
+/****************************************************************************/ 
+typedef struct _ASIC_INIT_PARAMETERS
+{
+  ULONG ulDefaultEngineClock;         //In 10Khz unit
+  ULONG ulDefaultMemoryClock;         //In 10Khz unit
+}ASIC_INIT_PARAMETERS;
+
+typedef struct _ASIC_INIT_PS_ALLOCATION
+{
+  ASIC_INIT_PARAMETERS sASICInitClocks;
+  SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
+}ASIC_INIT_PS_ALLOCATION;
+
+/****************************************************************************/ 
+// Structure used by DynamicClockGatingTable.ctb
+/****************************************************************************/ 
+typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 
+{
+  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
+  UCHAR ucPadding[3];
+}DYNAMIC_CLOCK_GATING_PARAMETERS;
+#define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
+
+/****************************************************************************/ 
+// Structure used by EnableDispPowerGatingTable.ctb
+/****************************************************************************/ 
+typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 
+{
+  UCHAR ucDispPipeId;                 // ATOM_CRTC1, ATOM_CRTC2, ...
+  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
+  UCHAR ucPadding[2];
+}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
+
+/****************************************************************************/ 
+// Structure used by EnableASIC_StaticPwrMgtTable.ctb
+/****************************************************************************/ 
+typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
+{
+  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
+  UCHAR ucPadding[3];
+}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
+#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
+
+/****************************************************************************/ 
+// Structures used by DAC_LoadDetectionTable.ctb
+/****************************************************************************/ 
+typedef struct _DAC_LOAD_DETECTION_PARAMETERS
+{
+  USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
+  UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
+  UCHAR  ucMisc;                                                                                       //Valid only when table revision =1.3 and above
+}DAC_LOAD_DETECTION_PARAMETERS;
+
+// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
+#define DAC_LOAD_MISC_YPrPb                                            0x01
+
+typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
+{
+  DAC_LOAD_DETECTION_PARAMETERS            sDacload;
+  ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
+}DAC_LOAD_DETECTION_PS_ALLOCATION;
+
+/****************************************************************************/ 
+// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
+/****************************************************************************/ 
+typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 
+{
+  USHORT usPixelClock;                // in 10KHz; for bios convenient
+  UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
+  UCHAR  ucAction;                    // 0: turn off encoder
+                                      // 1: setup and turn on encoder
+                                      // 7: ATOM_ENCODER_INIT Initialize DAC
+}DAC_ENCODER_CONTROL_PARAMETERS;
+
+#define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
+
+/****************************************************************************/ 
+// Structures used by DIG1EncoderControlTable
+//                    DIG2EncoderControlTable
+//                    ExternalEncoderControlTable
+/****************************************************************************/ 
+typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
+{
+  USHORT usPixelClock;         // in 10KHz; for bios convenient
+  UCHAR  ucConfig;               
+                            // [2] Link Select:
+                            // =0: PHY linkA if bfLane<3
+                            // =1: PHY linkB if bfLanes<3
+                            // =0: PHY linkA+B if bfLanes=3
+                            // [3] Transmitter Sel
+                            // =0: UNIPHY or PCIEPHY
+                            // =1: LVTMA                                       
+  UCHAR ucAction;           // =0: turn off encoder                                    
+                            // =1: turn on encoder                     
+  UCHAR ucEncoderMode;
+                            // =0: DP   encoder      
+                            // =1: LVDS encoder          
+                            // =2: DVI  encoder  
+                            // =3: HDMI encoder
+                            // =4: SDVO encoder
+  UCHAR ucLaneNum;          // how many lanes to enable
+  UCHAR ucReserved[2];
+}DIG_ENCODER_CONTROL_PARAMETERS;
+#define DIG_ENCODER_CONTROL_PS_ALLOCATION                        DIG_ENCODER_CONTROL_PARAMETERS
+#define EXTERNAL_ENCODER_CONTROL_PARAMETER                     DIG_ENCODER_CONTROL_PARAMETERS
+
+//ucConfig
+#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK                            0x01
+#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ         0x00
+#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ         0x01
+#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ         0x02
+#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK                                0x04
+#define ATOM_ENCODER_CONFIG_LINKA                                                                0x00
+#define ATOM_ENCODER_CONFIG_LINKB                                                                0x04
+#define ATOM_ENCODER_CONFIG_LINKA_B                                                      ATOM_TRANSMITTER_CONFIG_LINKA
+#define ATOM_ENCODER_CONFIG_LINKB_A                                                      ATOM_ENCODER_CONFIG_LINKB
+#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK       0x08
+#define ATOM_ENCODER_CONFIG_UNIPHY                                                       0x00
+#define ATOM_ENCODER_CONFIG_LVTMA                                                                0x08
+#define ATOM_ENCODER_CONFIG_TRANSMITTER1                                 0x00
+#define ATOM_ENCODER_CONFIG_TRANSMITTER2                                 0x08
+#define ATOM_ENCODER_CONFIG_DIGB                                                                 0x80                  // VBIOS Internal use, outside SW should set this bit=0
+// ucAction
+// ATOM_ENABLE:  Enable Encoder
+// ATOM_DISABLE: Disable Encoder
+
+//ucEncoderMode
+#define ATOM_ENCODER_MODE_DP                                                                                   0
+#define ATOM_ENCODER_MODE_LVDS                                                                         1
+#define ATOM_ENCODER_MODE_DVI                                                                                  2
+#define ATOM_ENCODER_MODE_HDMI                                                                         3
+#define ATOM_ENCODER_MODE_SDVO                                                                         4
+#define ATOM_ENCODER_MODE_DP_AUDIO                5
+#define ATOM_ENCODER_MODE_TV                                                                                   13
+#define ATOM_ENCODER_MODE_CV                                                                                   14
+#define ATOM_ENCODER_MODE_CRT                                                                                  15
+#define ATOM_ENCODER_MODE_DVO                                                                                  16
+#define ATOM_ENCODER_MODE_DP_SST                  ATOM_ENCODER_MODE_DP    // For DP1.2
+#define ATOM_ENCODER_MODE_DP_MST                  5                       // For DP1.2
+
+typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
+{
+#if ATOM_BIG_ENDIAN
+    UCHAR ucReserved1:2;
+    UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
+    UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
+    UCHAR ucReserved:1;
+    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
+#else
+    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
+    UCHAR ucReserved:1;
+    UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
+    UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
+    UCHAR ucReserved1:2;
+#endif
+}ATOM_DIG_ENCODER_CONFIG_V2;
+
+
+typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
+{
+  USHORT usPixelClock;      // in 10KHz; for bios convenient
+  ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
+  UCHAR ucAction;                                       
+  UCHAR ucEncoderMode;
+                            // =0: DP   encoder      
+                            // =1: LVDS encoder          
+                            // =2: DVI  encoder  
+                            // =3: HDMI encoder
+                            // =4: SDVO encoder
+  UCHAR ucLaneNum;          // how many lanes to enable
+  UCHAR ucStatus;           // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
+  UCHAR ucReserved;
+}DIG_ENCODER_CONTROL_PARAMETERS_V2;
+
+//ucConfig
+#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK                         0x01
+#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ                0x00
+#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ                0x01
+#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK                             0x04
+#define ATOM_ENCODER_CONFIG_V2_LINKA                                                             0x00
+#define ATOM_ENCODER_CONFIG_V2_LINKB                                                             0x04
+#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK      0x18
+#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1                                0x00
+#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2                                0x08
+#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3                                0x10
+
+// ucAction:
+// ATOM_DISABLE
+// ATOM_ENABLE
+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       0x08
+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    0x09
+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    0x0a
+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    0x13
+#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    0x0b
+#define ATOM_ENCODER_CMD_DP_VIDEO_OFF                 0x0c
+#define ATOM_ENCODER_CMD_DP_VIDEO_ON                  0x0d
+#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS    0x0e
+#define ATOM_ENCODER_CMD_SETUP                        0x0f
+#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE             0x10
+
+// ucStatus
+#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
+#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE  0x00
+
+//ucTableFormatRevision=1
+//ucTableContentRevision=3
+// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
+typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
+{
+#if ATOM_BIG_ENDIAN
+    UCHAR ucReserved1:1;
+    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
+    UCHAR ucReserved:3;
+    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
+#else
+    UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
+    UCHAR ucReserved:3;
+    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
+    UCHAR ucReserved1:1;
+#endif
+}ATOM_DIG_ENCODER_CONFIG_V3;
+
+#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK                         0x03
+#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ                0x00
+#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ                0x01
+#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL                                       0x70
+#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER                                      0x00
+#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER                                      0x10
+#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER                                      0x20
+#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER                                      0x30
+#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER                                      0x40
+#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER                                      0x50
+
+typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
+{
+  USHORT usPixelClock;      // in 10KHz; for bios convenient
+  ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
+  UCHAR ucAction;                              
+  union {
+    UCHAR ucEncoderMode;
+                            // =0: DP   encoder      
+                            // =1: LVDS encoder          
+                            // =2: DVI  encoder  
+                            // =3: HDMI encoder
+                            // =4: SDVO encoder
+                            // =5: DP audio
+    UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
+                           // =0:     external DP
+                           // =1:     internal DP2
+                           // =0x11:  internal DP1 for NutMeg/Travis DP translator
+  };
+  UCHAR ucLaneNum;          // how many lanes to enable
+  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
+  UCHAR ucReserved;
+}DIG_ENCODER_CONTROL_PARAMETERS_V3;
+
+//ucTableFormatRevision=1
+//ucTableContentRevision=4
+// start from NI           
+// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
+typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
+{
+#if ATOM_BIG_ENDIAN
+    UCHAR ucReserved1:1;
+    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
+    UCHAR ucReserved:2;
+    UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
+#else
+    UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
+    UCHAR ucReserved:2;
+    UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
+    UCHAR ucReserved1:1;
+#endif
+}ATOM_DIG_ENCODER_CONFIG_V4;
+
+#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK                         0x03
+#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ                0x00
+#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ                0x01
+#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ                0x02
+#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ                0x03
+#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL                                       0x70
+#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER                                      0x00
+#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER                                      0x10
+#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER                                      0x20
+#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER                                      0x30
+#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER                                      0x40
+#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER                                      0x50
+#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER                                      0x60
+
+typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
+{
+  USHORT usPixelClock;      // in 10KHz; for bios convenient
+  union{
+  ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
+  UCHAR ucConfig;
+  };
+  UCHAR ucAction;                              
+  union {
+    UCHAR ucEncoderMode;
+                            // =0: DP   encoder      
+                            // =1: LVDS encoder          
+                            // =2: DVI  encoder  
+                            // =3: HDMI encoder
+                            // =4: SDVO encoder
+                            // =5: DP audio
+    UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
+                           // =0:     external DP
+                           // =1:     internal DP2
+                           // =0x11:  internal DP1 for NutMeg/Travis DP translator
+  };
+  UCHAR ucLaneNum;          // how many lanes to enable
+  UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
+  UCHAR ucHPD_ID;           // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
+}DIG_ENCODER_CONTROL_PARAMETERS_V4;
+
+// define ucBitPerColor: 
+#define PANEL_BPC_UNDEFINE                               0x00
+#define PANEL_6BIT_PER_COLOR                             0x01 
+#define PANEL_8BIT_PER_COLOR                             0x02
+#define PANEL_10BIT_PER_COLOR                            0x03
+#define PANEL_12BIT_PER_COLOR                            0x04
+#define PANEL_16BIT_PER_COLOR                            0x05
+
+//define ucPanelMode
+#define DP_PANEL_MODE_EXTERNAL_DP_MODE                   0x00
+#define DP_PANEL_MODE_INTERNAL_DP2_MODE                  0x01
+#define DP_PANEL_MODE_INTERNAL_DP1_MODE                  0x11
+
+/****************************************************************************/ 
+// Structures used by UNIPHYTransmitterControlTable
+//                    LVTMATransmitterControlTable
+//                    DVOOutputControlTable
+/****************************************************************************/ 
+typedef struct _ATOM_DP_VS_MODE
+{
+  UCHAR ucLaneSel;
+  UCHAR ucLaneSet;
+}ATOM_DP_VS_MODE;
+
+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
+{
+       union
+       {
+  USHORT usPixelClock;         // in 10KHz; for bios convenient
+       USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
+  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
+       };
+  UCHAR ucConfig;
+                                                                                                       // [0]=0: 4 lane Link,      
+                                                                                                       //    =1: 8 lane Link ( Dual Links TMDS ) 
+                          // [1]=0: InCoherent mode   
+                                                                                                       //    =1: Coherent Mode                                                                         
+                                                                                                       // [2] Link Select:
+                                                                                               // =0: PHY linkA   if bfLane<3
+                                                                                                       // =1: PHY linkB   if bfLanes<3
+                                                                                               // =0: PHY linkA+B if bfLanes=3         
+                          // [5:4]PCIE lane Sel
+                          // =0: lane 0~3 or 0~7
+                          // =1: lane 4~7
+                          // =2: lane 8~11 or 8~15
+                          // =3: lane 12~15 
+       UCHAR ucAction;                           // =0: turn off encoder                                       
+                               // =1: turn on encoder                  
+  UCHAR ucReserved[4];
+}DIG_TRANSMITTER_CONTROL_PARAMETERS;
+
+#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION          DIG_TRANSMITTER_CONTROL_PARAMETERS                                      
+
+//ucInitInfo
+#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff                  
+
+//ucConfig 
+#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK                     0x01
+#define ATOM_TRANSMITTER_CONFIG_COHERENT                               0x02
+#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK          0x04
+#define ATOM_TRANSMITTER_CONFIG_LINKA                                          0x00
+#define ATOM_TRANSMITTER_CONFIG_LINKB                                          0x04
+#define ATOM_TRANSMITTER_CONFIG_LINKA_B                                        0x00                    
+#define ATOM_TRANSMITTER_CONFIG_LINKB_A                                        0x04
+
+#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK       0x08                    // only used when ATOM_TRANSMITTER_ACTION_ENABLE
+#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER           0x00                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
+#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER           0x08                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
+
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK                    0x30
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL                    0x00
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE                    0x20
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN          0x30
+#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK          0xc0
+#define ATOM_TRANSMITTER_CONFIG_LANE_0_3                               0x00
+#define ATOM_TRANSMITTER_CONFIG_LANE_0_7                               0x00
+#define ATOM_TRANSMITTER_CONFIG_LANE_4_7                               0x40
+#define ATOM_TRANSMITTER_CONFIG_LANE_8_11                              0x80
+#define ATOM_TRANSMITTER_CONFIG_LANE_8_15                              0x80
+#define ATOM_TRANSMITTER_CONFIG_LANE_12_15                     0xc0
+
+//ucAction
+#define ATOM_TRANSMITTER_ACTION_DISABLE                                               0
+#define ATOM_TRANSMITTER_ACTION_ENABLE                                        1
+#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF                                     2
+#define ATOM_TRANSMITTER_ACTION_LCD_BLON                                      3
+#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
+#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START              5
+#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP                       6
+#define ATOM_TRANSMITTER_ACTION_INIT                                                  7
+#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT        8
+#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT                 9
+#define ATOM_TRANSMITTER_ACTION_SETUP                                                 10
+#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
+#define ATOM_TRANSMITTER_ACTION_POWER_ON               12
+#define ATOM_TRANSMITTER_ACTION_POWER_OFF              13
+
+// Following are used for DigTransmitterControlTable ver1.2
+typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
+{
+#if ATOM_BIG_ENDIAN
+  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
+                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
+                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
+  UCHAR ucReserved:1;               
+  UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
+  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
+  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
+                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
+
+  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
+  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
+#else
+  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
+  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
+  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
+                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
+  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
+  UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
+  UCHAR ucReserved:1;               
+  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
+                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
+                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
+#endif
+}ATOM_DIG_TRANSMITTER_CONFIG_V2;
+
+//ucConfig 
+//Bit0
+#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR                 0x01
+
+//Bit1
+#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT                                      0x02
+
+//Bit2
+#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK                       0x04
+#define ATOM_TRANSMITTER_CONFIG_V2_LINKA                                   0x00
+#define ATOM_TRANSMITTER_CONFIG_V2_LINKB                                           0x04
+
+// Bit3
+#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK            0x08
+#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER                          0x00                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
+#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER                          0x08                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
+
+// Bit4
+#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR                         0x10
+
+// Bit7:6
+#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
+#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1                0x00    //AB
+#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2                0x40    //CD
+#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3                0x80    //EF
+
+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
+{
+       union
+       {
+  USHORT usPixelClock;         // in 10KHz; for bios convenient
+       USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
+  ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
+       };
+  ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
+       UCHAR ucAction;                           // define as ATOM_TRANSMITER_ACTION_XXX
+  UCHAR ucReserved[4];
+}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
+
+typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
+{
+#if ATOM_BIG_ENDIAN
+  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
+                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
+                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
+  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
+  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
+  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
+                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
+  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
+  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
+#else
+  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
+  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
+  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
+                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
+  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
+  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
+  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
+                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
+                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
+#endif
+}ATOM_DIG_TRANSMITTER_CONFIG_V3;
+
+
+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
+{
+       union
+       {
+    USHORT usPixelClock;               // in 10KHz; for bios convenient
+         USHORT usInitInfo;                    // when init uniphy,lower 8bit is used for connector type defined in objectid.h
+    ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
+       };
+  ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
+       UCHAR ucAction;                             // define as ATOM_TRANSMITER_ACTION_XXX
+  UCHAR ucLaneNum;
+  UCHAR ucReserved[3];
+}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
+
+//ucConfig 
+//Bit0
+#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR                 0x01
+
+//Bit1
+#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT                                      0x02
+
+//Bit2
+#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK                       0x04
+#define ATOM_TRANSMITTER_CONFIG_V3_LINKA                                   0x00
+#define ATOM_TRANSMITTER_CONFIG_V3_LINKB                                           0x04
+
+// Bit3
+#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK            0x08
+#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER                          0x00
+#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER                          0x08
+
+// Bit5:4
+#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK              0x30
+#define ATOM_TRASMITTER_CONFIG_V3_P1PLL                                0x00
+#define ATOM_TRASMITTER_CONFIG_V3_P2PLL                                  0x10
+#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT            0x20
+
+// Bit7:6
+#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK     0xC0
+#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1                0x00    //AB
+#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2                0x40    //CD
+#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3                0x80    //EF
+
+
+/****************************************************************************/ 
+// Structures used by UNIPHYTransmitterControlTable V1.4
+// ASIC Families: NI
+// ucTableFormatRevision=1
+// ucTableContentRevision=4
+/****************************************************************************/ 
+typedef struct _ATOM_DP_VS_MODE_V4
+{
+  UCHAR ucLaneSel;
+       union
+       {  
+         UCHAR ucLaneSet;
+         struct {
+#if ATOM_BIG_ENDIAN
+                 UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
+                 UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
+                 UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
+#else
+                 UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
+                 UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
+                 UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
+#endif
+               };
+       }; 
+}ATOM_DP_VS_MODE_V4;
+typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
+{
+#if ATOM_BIG_ENDIAN
+  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
+                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
+                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
+  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
+  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
+  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
+                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
+  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
+  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
+#else
+  UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
+  UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
+  UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
+                                    //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
+  UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
+  UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
+  UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
+                                    //        =1 Dig Transmitter 2 ( Uniphy CD )
+                                    //        =2 Dig Transmitter 3 ( Uniphy EF )
+#endif
+}ATOM_DIG_TRANSMITTER_CONFIG_V4;
+
+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
+{
+  union
+  {
+    USHORT usPixelClock;               // in 10KHz; for bios convenient
+    USHORT usInitInfo;                 // when init uniphy,lower 8bit is used for connector type defined in objectid.h
+    ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode     Redefined comparing to previous version
+  };
+  union
+  {
+  ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
+  UCHAR ucConfig;
+  };
+  UCHAR ucAction;                                  // define as ATOM_TRANSMITER_ACTION_XXX                             
+  UCHAR ucLaneNum;
+  UCHAR ucReserved[3];
+}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
+
+//ucConfig 
+//Bit0
+#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR                 0x01
+//Bit1
+#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT                                      0x02
+//Bit2
+#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK                       0x04
+#define ATOM_TRANSMITTER_CONFIG_V4_LINKA                                   0x00                        
+#define ATOM_TRANSMITTER_CONFIG_V4_LINKB                                           0x04
+// Bit3
+#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK            0x08
+#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER                          0x00                           
+#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER                          0x08                          
+// Bit5:4
+#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK             0x30
+#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL                               0x00
+#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL                               0x10
+#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL                               0x20   // New in _V4
+#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT           0x30   // Changed comparing to V3
+// Bit7:6
+#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK     0xC0
+#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1                0x00    //AB
+#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2                0x40    //CD
+#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3                0x80    //EF
+
+
+typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
+{
+#if ATOM_BIG_ENDIAN
+  UCHAR ucReservd1:1;
+  UCHAR ucHPDSel:3;
+  UCHAR ucPhyClkSrcId:2;            
+  UCHAR ucCoherentMode:1;            
+  UCHAR ucReserved:1;
+#else
+  UCHAR ucReserved:1;
+  UCHAR ucCoherentMode:1;            
+  UCHAR ucPhyClkSrcId:2;            
+  UCHAR ucHPDSel:3;
+  UCHAR ucReservd1:1;
+#endif
+}ATOM_DIG_TRANSMITTER_CONFIG_V5;
+
+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
+{
+  USHORT usSymClock;                   // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock,  (HDMI deep color), =pixel clock * deep_color_ratio
+  UCHAR  ucPhyId;                   // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
+  UCHAR  ucAction;                                 // define as ATOM_TRANSMITER_ACTION_xxx
+  UCHAR  ucLaneNum;                 // indicate lane number 1-8
+  UCHAR  ucConnObjId;               // Connector Object Id defined in ObjectId.h
+  UCHAR  ucDigMode;                 // indicate DIG mode
+  union{
+  ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
+  UCHAR ucConfig;
+  };
+  UCHAR  ucDigEncoderSel;           // indicate DIG front end encoder 
+  UCHAR  ucDPLaneSet;
+  UCHAR  ucReserved;
+  UCHAR  ucReserved1;
+}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
+
+//ucPhyId
+#define ATOM_PHY_ID_UNIPHYA                                 0  
+#define ATOM_PHY_ID_UNIPHYB                                 1
+#define ATOM_PHY_ID_UNIPHYC                                 2
+#define ATOM_PHY_ID_UNIPHYD                                 3
+#define ATOM_PHY_ID_UNIPHYE                                 4
+#define ATOM_PHY_ID_UNIPHYF                                 5
+#define ATOM_PHY_ID_UNIPHYG                                 6
+
+// ucDigEncoderSel
+#define ATOM_TRANMSITTER_V5__DIGA_SEL                       0x01
+#define ATOM_TRANMSITTER_V5__DIGB_SEL                       0x02
+#define ATOM_TRANMSITTER_V5__DIGC_SEL                       0x04
+#define ATOM_TRANMSITTER_V5__DIGD_SEL                       0x08
+#define ATOM_TRANMSITTER_V5__DIGE_SEL                       0x10
+#define ATOM_TRANMSITTER_V5__DIGF_SEL                       0x20
+#define ATOM_TRANMSITTER_V5__DIGG_SEL                       0x40
+
+// ucDigMode
+#define ATOM_TRANSMITTER_DIGMODE_V5_DP                      0
+#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS                    1
+#define ATOM_TRANSMITTER_DIGMODE_V5_DVI                     2
+#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI                    3
+#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO                    4
+#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST                  5
+
+// ucDPLaneSet
+#define DP_LANE_SET__0DB_0_4V                               0x00
+#define DP_LANE_SET__0DB_0_6V                               0x01
+#define DP_LANE_SET__0DB_0_8V                               0x02
+#define DP_LANE_SET__0DB_1_2V                               0x03
+#define DP_LANE_SET__3_5DB_0_4V                             0x08  
+#define DP_LANE_SET__3_5DB_0_6V                             0x09
+#define DP_LANE_SET__3_5DB_0_8V                             0x0a
+#define DP_LANE_SET__6DB_0_4V                               0x10
+#define DP_LANE_SET__6DB_0_6V                               0x11
+#define DP_LANE_SET__9_5DB_0_4V                             0x18  
+
+// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
+// Bit1
+#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT                                      0x02
+
+// Bit3:2
+#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK             0x0c
+#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT                0x02
+
+#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL                               0x00
+#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL                               0x04
+#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL                               0x08   
+#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT           0x0c
+// Bit6:4
+#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK                          0x70
+#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT                     0x04
+
+#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL                                  0x00
+#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL                                      0x10
+#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL                                      0x20
+#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL                                      0x30
+#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL                                      0x40
+#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL                                      0x50
+#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL                                      0x60
+
+#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5            DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
+
+
+/****************************************************************************/ 
+// Structures used by ExternalEncoderControlTable V1.3
+// ASIC Families: Evergreen, Llano, NI
+// ucTableFormatRevision=1
+// ucTableContentRevision=3
+/****************************************************************************/ 
+
+typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
+{
+  union{
+  USHORT usPixelClock;      // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 
+  USHORT usConnectorId;     // connector id, valid when ucAction = INIT
+  };
+  UCHAR  ucConfig;          // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT  
+  UCHAR  ucAction;          // 
+  UCHAR  ucEncoderMode;     // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
+  UCHAR  ucLaneNum;         // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT  
+  UCHAR  ucBitPerColor;     // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
+  UCHAR  ucReserved;        
+}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
+
+// ucAction
+#define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT         0x00
+#define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT          0x01
+#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT           0x07
+#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP          0x0f
+#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF   0x10
+#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING       0x11
+#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION      0x12
+#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP              0x14
+
+// ucConfig
+#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK                             0x03
+#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ            0x00
+#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ            0x01
+#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ            0x02
+#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK                0x70
+#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1                        0x00
+#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2                        0x10
+#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3                        0x20
+
+typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
+{
+  EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
+  ULONG ulReserved[2];
+}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
+
+
+/****************************************************************************/ 
+// Structures used by DAC1OuputControlTable
+//                    DAC2OuputControlTable
+//                    LVTMAOutputControlTable  (Before DEC30)
+//                    TMDSAOutputControlTable  (Before DEC30)
+/****************************************************************************/ 
+typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+{
+  UCHAR  ucAction;                    // Possible input:ATOM_ENABLE||ATOMDISABLE
+                                      // When the display is LCD, in addition to above:
+                                      // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
+                                      // ATOM_LCD_SELFTEST_STOP
+                                      
+  UCHAR  aucPadding[3];               // padding to DWORD aligned
+}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
+
+#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+
+
+#define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 
+#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 
+#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
+#define DVO_OUTPUT_CONTROL_PARAMETERS_V3        DIG_TRANSMITTER_CONTROL_PARAMETERS
+
+/****************************************************************************/ 
+// Structures used by BlankCRTCTable
+/****************************************************************************/ 
+typedef struct _BLANK_CRTC_PARAMETERS
+{
+  UCHAR  ucCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
+  UCHAR  ucBlanking;                  // ATOM_BLANKING or ATOM_BLANKINGOFF
+  USHORT usBlackColorRCr;
+  USHORT usBlackColorGY;
+  USHORT usBlackColorBCb;
+}BLANK_CRTC_PARAMETERS;
+#define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
+
+/****************************************************************************/ 
+// Structures used by EnableCRTCTable
+//                    EnableCRTCMemReqTable
+//                    UpdateCRTC_DoubleBufferRegistersTable
+/****************************************************************************/ 
+typedef struct _ENABLE_CRTC_PARAMETERS
+{
+  UCHAR ucCRTC;                          // ATOM_CRTC1 or ATOM_CRTC2
+  UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE 
+  UCHAR ucPadding[2];
+}ENABLE_CRTC_PARAMETERS;
+#define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
+
+/****************************************************************************/ 
+// Structures used by SetCRTC_OverScanTable
+/****************************************************************************/ 
+typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
+{
+  USHORT usOverscanRight;             // right
+  USHORT usOverscanLeft;              // left
+  USHORT usOverscanBottom;            // bottom
+  USHORT usOverscanTop;               // top
+  UCHAR  ucCRTC;                      // ATOM_CRTC1 or ATOM_CRTC2
+  UCHAR  ucPadding[3];
+}SET_CRTC_OVERSCAN_PARAMETERS;
+#define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
+
+/****************************************************************************/ 
+// Structures used by SetCRTC_ReplicationTable
+/****************************************************************************/ 
+typedef struct _SET_CRTC_REPLICATION_PARAMETERS
+{
+  UCHAR ucH_Replication;              // horizontal replication
+  UCHAR ucV_Replication;              // vertical replication
+  UCHAR usCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
+  UCHAR ucPadding;
+}SET_CRTC_REPLICATION_PARAMETERS;
+#define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
+
+/****************************************************************************/ 
+// Structures used by SelectCRTC_SourceTable
+/****************************************************************************/ 
+typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
+{
+  UCHAR ucCRTC;                          // ATOM_CRTC1 or ATOM_CRTC2
+  UCHAR ucDevice;                     // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
+  UCHAR ucPadding[2];
+}SELECT_CRTC_SOURCE_PARAMETERS;
+#define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
+
+typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
+{
+  UCHAR ucCRTC;                          // ATOM_CRTC1 or ATOM_CRTC2
+  UCHAR ucEncoderID;                  // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
+  UCHAR ucEncodeMode;                                                                  // Encoding mode, only valid when using DIG1/DIG2/DVO
+  UCHAR ucPadding;
+}SELECT_CRTC_SOURCE_PARAMETERS_V2;
+
+//ucEncoderID
+//#define ASIC_INT_DAC1_ENCODER_ID                                             0x00 
+//#define ASIC_INT_TV_ENCODER_ID                                                                       0x02
+//#define ASIC_INT_DIG1_ENCODER_ID                                                             0x03
+//#define ASIC_INT_DAC2_ENCODER_ID                                                             0x04
+//#define ASIC_EXT_TV_ENCODER_ID                                                                       0x06
+//#define ASIC_INT_DVO_ENCODER_ID                                                                      0x07
+//#define ASIC_INT_DIG2_ENCODER_ID                                                             0x09
+//#define ASIC_EXT_DIG_ENCODER_ID                                                                      0x05
+
+//ucEncodeMode
+//#define ATOM_ENCODER_MODE_DP                                                                         0
+//#define ATOM_ENCODER_MODE_LVDS                                                                       1
+//#define ATOM_ENCODER_MODE_DVI                                                                                2
+//#define ATOM_ENCODER_MODE_HDMI                                                                       3
+//#define ATOM_ENCODER_MODE_SDVO                                                                       4
+//#define ATOM_ENCODER_MODE_TV                                                                         13
+//#define ATOM_ENCODER_MODE_CV                                                                         14
+//#define ATOM_ENCODER_MODE_CRT                                                                                15
+
+/****************************************************************************/ 
+// Structures used by SetPixelClockTable
+//                    GetPixelClockTable 
+/****************************************************************************/ 
+//Major revision=1., Minor revision=1
+typedef struct _PIXEL_CLOCK_PARAMETERS
+{
+  USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
+                                      // 0 means disable PPLL
+  USHORT usRefDiv;                    // Reference divider
+  USHORT usFbDiv;                     // feedback divider
+  UCHAR  ucPostDiv;                   // post divider  
+  UCHAR  ucFracFbDiv;                 // fractional feedback divider
+  UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
+  UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
+  UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
+  UCHAR  ucPadding;
+}PIXEL_CLOCK_PARAMETERS;
+
+//Major revision=1., Minor revision=2, add ucMiscIfno
+//ucMiscInfo:
+#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
+#define MISC_DEVICE_INDEX_MASK        0xF0
+#define MISC_DEVICE_INDEX_SHIFT       4
+
+typedef struct _PIXEL_CLOCK_PARAMETERS_V2
+{
+  USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
+                                      // 0 means disable PPLL
+  USHORT usRefDiv;                    // Reference divider
+  USHORT usFbDiv;                     // feedback divider
+  UCHAR  ucPostDiv;                   // post divider  
+  UCHAR  ucFracFbDiv;                 // fractional feedback divider
+  UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
+  UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
+  UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
+  UCHAR  ucMiscInfo;                  // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
+}PIXEL_CLOCK_PARAMETERS_V2;
+
+//Major revision=1., Minor revision=3, structure/definition change
+//ucEncoderMode:
+//ATOM_ENCODER_MODE_DP
+//ATOM_ENOCDER_MODE_LVDS
+//ATOM_ENOCDER_MODE_DVI
+//ATOM_ENOCDER_MODE_HDMI
+//ATOM_ENOCDER_MODE_SDVO
+//ATOM_ENCODER_MODE_TV                                                                         13
+//ATOM_ENCODER_MODE_CV                                                                         14
+//ATOM_ENCODER_MODE_CRT                                                                                15
+
+//ucDVOConfig
+//#define DVO_ENCODER_CONFIG_RATE_SEL                                                  0x01
+//#define DVO_ENCODER_CONFIG_DDR_SPEED                                         0x00
+//#define DVO_ENCODER_CONFIG_SDR_SPEED                                         0x01
+//#define DVO_ENCODER_CONFIG_OUTPUT_SEL                                                0x0c
+//#define DVO_ENCODER_CONFIG_LOW12BIT                                                  0x00
+//#define DVO_ENCODER_CONFIG_UPPER12BIT                                                0x04
+//#define DVO_ENCODER_CONFIG_24BIT                                                             0x08
+
+//ucMiscInfo: also changed, see below
+#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL                                               0x01
+#define PIXEL_CLOCK_MISC_VGA_MODE                                                                              0x02
+#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK                                                 0x04
+#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1                                                        0x00
+#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2                                                        0x04
+#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK                        0x08
+#define PIXEL_CLOCK_MISC_REF_DIV_SRC                    0x10
+// V1.4 for RoadRunner
+#define PIXEL_CLOCK_V4_MISC_SS_ENABLE               0x10
+#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE           0x20
+
+
+typedef struct _PIXEL_CLOCK_PARAMETERS_V3
+{
+  USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
+                                      // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
+  USHORT usRefDiv;                    // Reference divider
+  USHORT usFbDiv;                     // feedback divider
+  UCHAR  ucPostDiv;                   // post divider  
+  UCHAR  ucFracFbDiv;                 // fractional feedback divider
+  UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
+  UCHAR  ucTransmitterId;             // graphic encoder id defined in objectId.h
+       union
+       {
+  UCHAR  ucEncoderMode;               // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
+       UCHAR  ucDVOConfig;                                                                     // when use DVO, need to know SDR/DDR, 12bit or 24bit
+       };
+  UCHAR  ucMiscInfo;                  // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
+                                      // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
+                                      // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
+}PIXEL_CLOCK_PARAMETERS_V3;
+
+#define PIXEL_CLOCK_PARAMETERS_LAST                    PIXEL_CLOCK_PARAMETERS_V2
+#define GET_PIXEL_CLOCK_PS_ALLOCATION          PIXEL_CLOCK_PARAMETERS_LAST
+
+typedef struct _PIXEL_CLOCK_PARAMETERS_V5
+{
+  UCHAR  ucCRTC;             // ATOM_CRTC1~6, indicate the CRTC controller to 
+                             // drive the pixel clock. not used for DCPLL case.
+  union{
+  UCHAR  ucReserved;
+  UCHAR  ucFracFbDiv;        // [gphan] temporary to prevent build problem.  remove it after driver code is changed.
+  };
+  USHORT usPixelClock;       // target the pixel clock to drive the CRTC timing
+                             // 0 means disable PPLL/DCPLL. 
+  USHORT usFbDiv;            // feedback divider integer part. 
+  UCHAR  ucPostDiv;          // post divider. 
+  UCHAR  ucRefDiv;           // Reference divider
+  UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
+  UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h, 
+                             // indicate which graphic encoder will be used. 
+  UCHAR  ucEncoderMode;      // Encoder mode: 
+  UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL 
+                             // bit[1]= when VGA timing is used. 
+                             // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
+                             // bit[4]= RefClock source for PPLL. 
+                             // =0: XTLAIN( default mode )
+                                  // =1: other external clock source, which is pre-defined
+                             //     by VBIOS depend on the feature required.
+                             // bit[7:5]: reserved.
+  ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
+
+}PIXEL_CLOCK_PARAMETERS_V5;
+
+#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL                                    0x01
+#define PIXEL_CLOCK_V5_MISC_VGA_MODE                                                           0x02
+#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK           0x0c
+#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP              0x00
+#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP              0x04
+#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP              0x08
+#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC             0x10
+
+typedef struct _CRTC_PIXEL_CLOCK_FREQ
+{
+#if ATOM_BIG_ENDIAN
+  ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to 
+                              // drive the pixel clock. not used for DCPLL case.
+  ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing. 
+                              // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
+#else
+  ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing. 
+                              // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
+  ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to 
+                              // drive the pixel clock. not used for DCPLL case.
+#endif
+}CRTC_PIXEL_CLOCK_FREQ;
+
+typedef struct _PIXEL_CLOCK_PARAMETERS_V6
+{
+  union{
+    CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;    // pixel clock and CRTC id frequency 
+    ULONG ulDispEngClkFreq;                  // dispclk frequency
+  };
+  USHORT usFbDiv;            // feedback divider integer part. 
+  UCHAR  ucPostDiv;          // post divider. 
+  UCHAR  ucRefDiv;           // Reference divider
+  UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
+  UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h, 
+                             // indicate which graphic encoder will be used. 
+  UCHAR  ucEncoderMode;      // Encoder mode: 
+  UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL 
+                             // bit[1]= when VGA timing is used. 
+                             // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
+                             // bit[4]= RefClock source for PPLL. 
+                             // =0: XTLAIN( default mode )
+                                  // =1: other external clock source, which is pre-defined                                            
+                             //     by VBIOS depend on the feature required.
+                             // bit[7:5]: reserved.
+  ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
+
+}PIXEL_CLOCK_PARAMETERS_V6;
+
+#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL                                    0x01
+#define PIXEL_CLOCK_V6_MISC_VGA_MODE                                                           0x02
+#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK           0x0c
+#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP              0x00
+#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP              0x04
+#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP              0x08
+#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP              0x0c
+#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC             0x10
+
+typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
+{
+  PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
+}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
+
+typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
+{
+  UCHAR  ucStatus;
+  UCHAR  ucRefDivSrc;                 // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
+  UCHAR  ucReserved[2];
+}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
+
+typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
+{
+  PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
+}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
+
+/****************************************************************************/ 
+// Structures used by AdjustDisplayPllTable
+/****************************************************************************/ 
+typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
+{
+       USHORT usPixelClock;
+       UCHAR ucTransmitterID;
+       UCHAR ucEncodeMode;
+       union
+       {
+               UCHAR ucDVOConfig;                                                                      //if DVO, need passing link rate and output 12bitlow or 24bit
+               UCHAR ucConfig;                                                                                 //if none DVO, not defined yet
+       };
+       UCHAR ucReserved[3];
+}ADJUST_DISPLAY_PLL_PARAMETERS;
+
+#define ADJUST_DISPLAY_CONFIG_SS_ENABLE       0x10
+#define ADJUST_DISPLAY_PLL_PS_ALLOCATION                       ADJUST_DISPLAY_PLL_PARAMETERS
+
+typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
+{
+       USHORT usPixelClock;                    // target pixel clock
+       UCHAR ucTransmitterID;                  // GPU transmitter id defined in objectid.h
+       UCHAR ucEncodeMode;                     // encoder mode: CRT, LVDS, DP, TMDS or HDMI
+  UCHAR ucDispPllConfig;                 // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
+  UCHAR ucExtTransmitterID;               // external encoder id.
+       UCHAR ucReserved[2];
+}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
+
+// usDispPllConfig v1.2 for RoadRunner
+#define DISPPLL_CONFIG_DVO_RATE_SEL                0x0001     // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_DDR_SPEED               0x0000     // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_SDR_SPEED               0x0001     // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_OUTPUT_SEL              0x000c     // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_LOW12BIT                0x0000     // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_UPPER12BIT              0x0004     // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_DVO_24BIT                   0x0008     // need only when ucTransmitterID = DVO
+#define DISPPLL_CONFIG_SS_ENABLE                   0x0010     // Only used when ucEncoderMode = DP or LVDS
+#define DISPPLL_CONFIG_COHERENT_MODE               0x0020     // Only used when ucEncoderMode = TMDS or HDMI
+#define DISPPLL_CONFIG_DUAL_LINK                   0x0040     // Only used when ucEncoderMode = TMDS or LVDS
+
+
+typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
+{
+  ULONG ulDispPllFreq;                 // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
+  UCHAR ucRefDiv;                      // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
+  UCHAR ucPostDiv;                     // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
+  UCHAR ucReserved[2];  
+}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
+
+typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
+{
+  union 
+  {
+    ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3  sInput;
+    ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
+  };
+} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
+
+/****************************************************************************/ 
+// Structures used by EnableYUVTable
+/****************************************************************************/ 
+typedef struct _ENABLE_YUV_PARAMETERS
+{
+  UCHAR ucEnable;                     // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
+  UCHAR ucCRTC;                       // Which CRTC needs this YUV or RGB format
+  UCHAR ucPadding[2];
+}ENABLE_YUV_PARAMETERS;
+#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
+
+/****************************************************************************/ 
+// Structures used by GetMemoryClockTable
+/****************************************************************************/ 
+typedef struct _GET_MEMORY_CLOCK_PARAMETERS
+{
+  ULONG ulReturnMemoryClock;          // current memory speed in 10KHz unit
+} GET_MEMORY_CLOCK_PARAMETERS;
+#define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
+
+/****************************************************************************/ 
+// Structures used by GetEngineClockTable
+/****************************************************************************/ 
+typedef struct _GET_ENGINE_CLOCK_PARAMETERS
+{
+  ULONG ulReturnEngineClock;          // current engine speed in 10KHz unit
+} GET_ENGINE_CLOCK_PARAMETERS;
+#define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
+
+/****************************************************************************/ 
+// Following Structures and constant may be obsolete
+/****************************************************************************/ 
+//Maxium 8 bytes,the data read in will be placed in the parameter space.
+//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
+typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
+{
+  USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
+  USHORT    usVRAMAddress;      //Address in Frame Buffer where to pace raw EDID
+  USHORT    usStatus;           //When use output: lower byte EDID checksum, high byte hardware status
+                                //WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte
+  UCHAR     ucSlaveAddr;        //Read from which slave
+  UCHAR     ucLineNumber;       //Read from which HW assisted line
+}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
+#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
+
+
+#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
+#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
+#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
+#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
+#define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
+
+typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+{
+  USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
+  USHORT    usByteOffset;       //Write to which byte
+                                //Upper portion of usByteOffset is Format of data 
+                                //1bytePS+offsetPS
+                                //2bytesPS+offsetPS
+                                //blockID+offsetPS
+                                //blockID+offsetID
+                                //blockID+counterID+offsetID
+  UCHAR     ucData;             //PS data1
+  UCHAR     ucStatus;           //Status byte 1=success, 2=failure, Also is used as PS data2
+  UCHAR     ucSlaveAddr;        //Write to which slave
+  UCHAR     ucLineNumber;       //Write from which HW assisted line
+}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
+
+#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+
+typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
+{
+  USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
+  UCHAR     ucSlaveAddr;        //Write to which slave
+  UCHAR     ucLineNumber;       //Write from which HW assisted line
+}SET_UP_HW_I2C_DATA_PARAMETERS;
+
+
+/**************************************************************************/
+#define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+
+
+/****************************************************************************/ 
+// Structures used by PowerConnectorDetectionTable
+/****************************************************************************/ 
+typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
+{
+  UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
+       UCHAR   ucPwrBehaviorId;                                                        
+       USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
+}POWER_CONNECTOR_DETECTION_PARAMETERS;
+
+typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
+{                               
+  UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
+       UCHAR   ucReserved;
+       USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
+  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved;
+}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
+
+/****************************LVDS SS Command Table Definitions**********************/
+
+/****************************************************************************/ 
+// Structures used by EnableSpreadSpectrumOnPPLLTable
+/****************************************************************************/ 
+typedef struct _ENABLE_LVDS_SS_PARAMETERS
+{
+  USHORT  usSpreadSpectrumPercentage;       
+  UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
+  UCHAR   ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
+  UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
+  UCHAR   ucPadding[3];
+}ENABLE_LVDS_SS_PARAMETERS;
+
+//ucTableFormatRevision=1,ucTableContentRevision=2
+typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
+{
+  USHORT  usSpreadSpectrumPercentage;       
+  UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
+  UCHAR   ucSpreadSpectrumStep;           //
+  UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
+  UCHAR   ucSpreadSpectrumDelay;
+  UCHAR   ucSpreadSpectrumRange;
+  UCHAR   ucPadding;
+}ENABLE_LVDS_SS_PARAMETERS_V2;
+
+//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
+typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
+{
+  USHORT  usSpreadSpectrumPercentage;
+  UCHAR   ucSpreadSpectrumType;           // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
+  UCHAR   ucSpreadSpectrumStep;           //
+  UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
+  UCHAR   ucSpreadSpectrumDelay;
+  UCHAR   ucSpreadSpectrumRange;
+  UCHAR   ucPpll;                                                                                                // ATOM_PPLL1/ATOM_PPLL2
+}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
+
+typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
+{
+  USHORT  usSpreadSpectrumPercentage;
+  UCHAR   ucSpreadSpectrumType;                // Bit[0]: 0-Down Spread,1-Center Spread. 
+                                        // Bit[1]: 1-Ext. 0-Int. 
+                                        // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
+                                        // Bits[7:4] reserved
+  UCHAR   ucEnable;                        // ATOM_ENABLE or ATOM_DISABLE
+  USHORT  usSpreadSpectrumAmount;              // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]    
+  USHORT  usSpreadSpectrumStep;                // SS_STEP_SIZE_DSFRAC
+}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
+
+#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD      0x00
+#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD    0x01
+#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD       0x02
+#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK    0x0c
+#define ATOM_PPLL_SS_TYPE_V2_P1PLL            0x00
+#define ATOM_PPLL_SS_TYPE_V2_P2PLL            0x04
+#define ATOM_PPLL_SS_TYPE_V2_DCPLL            0x08
+#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK     0x00FF
+#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT    0
+#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK     0x0F00
+#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT    8
+
+// Used by DCE5.0
+ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
+{
+  USHORT  usSpreadSpectrumAmountFrac;   // SS_AMOUNT_DSFRAC New in DCE5.0
+  UCHAR   ucSpreadSpectrumType;                // Bit[0]: 0-Down Spread,1-Center Spread. 
+                                        // Bit[1]: 1-Ext. 0-Int. 
+                                        // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
+                                        // Bits[7:4] reserved
+  UCHAR   ucEnable;                        // ATOM_ENABLE or ATOM_DISABLE
+  USHORT  usSpreadSpectrumAmount;              // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]    
+  USHORT  usSpreadSpectrumStep;                // SS_STEP_SIZE_DSFRAC
+}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
+    
+#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD      0x00
+#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD    0x01
+#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD       0x02
+#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK    0x0c
+#define ATOM_PPLL_SS_TYPE_V3_P1PLL            0x00
+#define ATOM_PPLL_SS_TYPE_V3_P2PLL            0x04
+#define ATOM_PPLL_SS_TYPE_V3_DCPLL            0x08
+#define ATOM_PPLL_SS_TYPE_V3_P0PLL            ATOM_PPLL_SS_TYPE_V3_DCPLL
+#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK     0x00FF
+#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT    0
+#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK     0x0F00
+#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT    8
+
+#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
+
+/**************************************************************************/
+
+typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
+{
+  PIXEL_CLOCK_PARAMETERS sPCLKInput;
+  ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 
+}SET_PIXEL_CLOCK_PS_ALLOCATION;
+
+#define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
+
+/****************************************************************************/ 
+// Structures used by ###
+/****************************************************************************/ 
+typedef struct _MEMORY_TRAINING_PARAMETERS
+{
+  ULONG ulTargetMemoryClock;          //In 10Khz unit
+}MEMORY_TRAINING_PARAMETERS;
+#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
+
+
+/****************************LVDS and other encoder command table definitions **********************/
+
+
+/****************************************************************************/ 
+// Structures used by LVDSEncoderControlTable   (Before DCE30)
+//                    LVTMAEncoderControlTable  (Before DCE30)
+//                    TMDSAEncoderControlTable  (Before DCE30)
+/****************************************************************************/ 
+typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
+{
+  USHORT usPixelClock;  // in 10KHz; for bios convenient
+  UCHAR  ucMisc;        // bit0=0: Enable single link
+                        //     =1: Enable dual link
+                        // Bit1=0: 666RGB
+                        //     =1: 888RGB
+  UCHAR  ucAction;      // 0: turn off encoder
+                        // 1: setup and turn on encoder
+}LVDS_ENCODER_CONTROL_PARAMETERS;
+
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
+   
+#define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
+
+
+//ucTableFormatRevision=1,ucTableContentRevision=2
+typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
+{
+  USHORT usPixelClock;  // in 10KHz; for bios convenient
+  UCHAR  ucMisc;        // see PANEL_ENCODER_MISC_xx defintions below
+  UCHAR  ucAction;      // 0: turn off encoder
+                        // 1: setup and turn on encoder
+  UCHAR  ucTruncate;    // bit0=0: Disable truncate
+                        //     =1: Enable truncate
+                        // bit4=0: 666RGB
+                        //     =1: 888RGB
+  UCHAR  ucSpatial;     // bit0=0: Disable spatial dithering
+                        //     =1: Enable spatial dithering
+                        // bit4=0: 666RGB
+                        //     =1: 888RGB
+  UCHAR  ucTemporal;    // bit0=0: Disable temporal dithering
+                        //     =1: Enable temporal dithering
+                        // bit4=0: 666RGB
+                        //     =1: 888RGB
+                        // bit5=0: Gray level 2
+                        //     =1: Gray level 4
+  UCHAR  ucFRC;         // bit4=0: 25FRC_SEL pattern E
+                        //     =1: 25FRC_SEL pattern F
+                        // bit6:5=0: 50FRC_SEL pattern A
+                        //       =1: 50FRC_SEL pattern B
+                        //       =2: 50FRC_SEL pattern C
+                        //       =3: 50FRC_SEL pattern D
+                        // bit7=0: 75FRC_SEL pattern E
+                        //     =1: 75FRC_SEL pattern F
+}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
+
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
+   
+#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
+  
+#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
+
+#define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
+
+/****************************************************************************/ 
+// Structures used by ###
+/****************************************************************************/ 
+typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
+{                               
+  UCHAR    ucEnable;            // Enable or Disable External TMDS encoder
+  UCHAR    ucMisc;              // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
+  UCHAR    ucPadding[2];
+}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
+
+typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
+{                               
+  ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS    sXTmdsEncoder;
+  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved;     //Caller doesn't need to init this portion
+}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
+
+#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
+
+typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
+{                               
+  ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2    sXTmdsEncoder;
+  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
+}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
+
+typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
+{
+  DIG_ENCODER_CONTROL_PARAMETERS            sDigEncoder;
+  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
+}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
+
+/****************************************************************************/ 
+// Structures used by DVOEncoderControlTable
+/****************************************************************************/ 
+//ucTableFormatRevision=1,ucTableContentRevision=3
+
+//ucDVOConfig:
+#define DVO_ENCODER_CONFIG_RATE_SEL                                                    0x01
+#define DVO_ENCODER_CONFIG_DDR_SPEED                                           0x00
+#define DVO_ENCODER_CONFIG_SDR_SPEED                                           0x01
+#define DVO_ENCODER_CONFIG_OUTPUT_SEL                                          0x0c
+#define DVO_ENCODER_CONFIG_LOW12BIT                                                    0x00
+#define DVO_ENCODER_CONFIG_UPPER12BIT                                          0x04
+#define DVO_ENCODER_CONFIG_24BIT                                                               0x08
+
+typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
+{
+  USHORT usPixelClock; 
+  UCHAR  ucDVOConfig;
+  UCHAR  ucAction;                                                                                                             //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
+  UCHAR  ucReseved[4];
+}DVO_ENCODER_CONTROL_PARAMETERS_V3;
+#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3   DVO_ENCODER_CONTROL_PARAMETERS_V3
+
+//ucTableFormatRevision=1
+//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 
+// bit1=0: non-coherent mode
+//     =1: coherent mode
+
+//==========================================================================================
+//Only change is here next time when changing encoder parameter definitions again!
+#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
+
+#define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
+#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
+
+//==========================================================================================
+#define PANEL_ENCODER_MISC_DUAL                0x01
+#define PANEL_ENCODER_MISC_COHERENT            0x02
+#define        PANEL_ENCODER_MISC_TMDS_LINKB                                    0x04
+#define        PANEL_ENCODER_MISC_HDMI_TYPE                                     0x08
+
+#define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
+#define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
+#define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
+
+#define PANEL_ENCODER_TRUNCATE_EN              0x01
+#define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
+#define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
+#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
+#define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
+#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
+#define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
+#define PANEL_ENCODER_25FRC_MASK               0x10
+#define PANEL_ENCODER_25FRC_E                  0x00
+#define PANEL_ENCODER_25FRC_F                  0x10
+#define PANEL_ENCODER_50FRC_MASK               0x60
+#define PANEL_ENCODER_50FRC_A                  0x00
+#define PANEL_ENCODER_50FRC_B                  0x20
+#define PANEL_ENCODER_50FRC_C                  0x40
+#define PANEL_ENCODER_50FRC_D                  0x60
+#define PANEL_ENCODER_75FRC_MASK               0x80
+#define PANEL_ENCODER_75FRC_E                  0x00
+#define PANEL_ENCODER_75FRC_F                  0x80
+
+/****************************************************************************/ 
+// Structures used by SetVoltageTable
+/****************************************************************************/ 
+#define SET_VOLTAGE_TYPE_ASIC_VDDC             1
+#define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
+#define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
+#define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
+#define SET_VOLTAGE_INIT_MODE                  5
+#define SET_VOLTAGE_GET_MAX_VOLTAGE            6                                       //Gets the Max. voltage for the soldered Asic
+
+#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
+#define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
+#define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
+
+#define        SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0
+#define        SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1      
+#define        SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2
+
+typedef struct _SET_VOLTAGE_PARAMETERS
+{
+  UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
+  UCHAR    ucVoltageMode;               // To set all, to set source A or source B or ...
+  UCHAR    ucVoltageIndex;              // An index to tell which voltage level
+  UCHAR    ucReserved;          
+}SET_VOLTAGE_PARAMETERS;
+
+typedef struct _SET_VOLTAGE_PARAMETERS_V2
+{
+  UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
+  UCHAR    ucVoltageMode;               // Not used, maybe use for state machine for differen power mode
+  USHORT   usVoltageLevel;              // real voltage level
+}SET_VOLTAGE_PARAMETERS_V2;
+
+
+typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
+{
+  UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
+  UCHAR    ucVoltageMode;               // Indicate action: Set voltage level
+  USHORT   usVoltageLevel;              // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
+}SET_VOLTAGE_PARAMETERS_V1_3;
+
+//ucVoltageType
+#define VOLTAGE_TYPE_VDDC                    1
+#define VOLTAGE_TYPE_MVDDC                   2
+#define VOLTAGE_TYPE_MVDDQ                   3
+#define VOLTAGE_TYPE_VDDCI                   4
+
+//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
+#define ATOM_SET_VOLTAGE                     0        //Set voltage Level
+#define ATOM_INIT_VOLTAGE_REGULATOR          3        //Init Regulator
+#define ATOM_SET_VOLTAGE_PHASE               4        //Set Vregulator Phase
+#define ATOM_GET_MAX_VOLTAGE                 6        //Get Max Voltage, not used in SetVoltageTable v1.3
+#define ATOM_GET_VOLTAGE_LEVEL               6        //Get Voltage level from vitual voltage ID
+
+// define vitual voltage id in usVoltageLevel
+#define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
+#define ATOM_VIRTUAL_VOLTAGE_ID1             0xff02
+#define ATOM_VIRTUAL_VOLTAGE_ID2             0xff03
+#define ATOM_VIRTUAL_VOLTAGE_ID3             0xff04
+
+typedef struct _SET_VOLTAGE_PS_ALLOCATION
+{
+  SET_VOLTAGE_PARAMETERS sASICSetVoltage;
+  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
+}SET_VOLTAGE_PS_ALLOCATION;
+
+// New Added from SI for GetVoltageInfoTable, input parameter structure
+typedef struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
+{
+  UCHAR    ucVoltageType;               // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
+  UCHAR    ucVoltageMode;               // Input: Indicate action: Get voltage info
+  USHORT   usVoltageLevel;              // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 
+  ULONG    ulReserved;
+}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
+
+// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
+typedef struct  _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
+{
+  ULONG    ulVotlageGpioState;
+  ULONG    ulVoltageGPioMask;
+}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
+
+// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
+typedef struct  _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
+{
+  USHORT   usVoltageLevel;
+  USHORT   usVoltageId;                                  // Voltage Id programmed in Voltage Regulator
+  ULONG    ulReseved;
+}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
+
+
+// GetVoltageInfo v1.1 ucVoltageMode
+#define        ATOM_GET_VOLTAGE_VID                0x00
+#define ATOM_GET_VOTLAGE_INIT_SEQ           0x03
+#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID   0x04
+// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
+#define        ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
+
+// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
+#define        ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
+// undefined power state
+#define        ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
+#define        ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
+
+/****************************************************************************/ 
+// Structures used by TVEncoderControlTable
+/****************************************************************************/ 
+typedef struct _TV_ENCODER_CONTROL_PARAMETERS
+{
+  USHORT usPixelClock;                // in 10KHz; for bios convenient
+  UCHAR  ucTvStandard;                // See definition "ATOM_TV_NTSC ..."
+  UCHAR  ucAction;                    // 0: turn off encoder
+                                      // 1: setup and turn on encoder
+}TV_ENCODER_CONTROL_PARAMETERS;
+
+typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
+{
+  TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;          
+  WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved; // Don't set this one
+}TV_ENCODER_CONTROL_PS_ALLOCATION;
+
+//==============================Data Table Portion====================================
+
+/****************************************************************************/ 
+// Structure used in Data.mtb
+/****************************************************************************/ 
+typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
+{
+  USHORT        UtilityPipeLine;               // Offest for the utility to get parser info,Don't change this position!
+  USHORT        MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 
+  USHORT        MultimediaConfigInfo;     // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
+  USHORT        StandardVESA_Timing;      // Only used by Bios
+  USHORT        FirmwareInfo;             // Shared by various SW components,latest version 1.4
+  USHORT        PaletteData;              // Only used by BIOS
+  USHORT        LCD_Info;                 // Shared by various SW components,latest version 1.3, was called LVDS_Info 
+  USHORT        DIGTransmitterInfo;       // Internal used by VBIOS only version 3.1
+  USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1 
+  USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
+  USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600           
+  USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
+  USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
+  USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
+  USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
+  USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
+  USHORT        CompassionateData;        // Will be obsolete from R600
+  USHORT        SaveRestoreInfo;          // Only used by Bios
+  USHORT        PPLL_SS_Info;             // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
+  USHORT        OemInfo;                  // Defined and used by external SW, should be obsolete soon
+  USHORT        XTMDS_Info;               // Will be obsolete from R600
+  USHORT        MclkSS_Info;              // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
+  USHORT        Object_Header;            // Shared by various SW components,latest version 1.1
+  USHORT        IndirectIOAccess;         // Only used by Bios,this table position can't change at all!!
+  USHORT        MC_InitParameter;         // Only used by command table
+  USHORT        ASIC_VDDC_Info;                                                // Will be obsolete from R600
+  USHORT        ASIC_InternalSS_Info;                  // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
+  USHORT        TV_VideoMode;                                                  // Only used by command table
+  USHORT        VRAM_Info;                                                             // Only used by command table, latest version 1.3
+  USHORT        MemoryTrainingInfo;                            // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
+  USHORT        IntegratedSystemInfo;                  // Shared by various SW components
+  USHORT        ASIC_ProfilingInfo;                            // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
+  USHORT        VoltageObjectInfo;                             // Shared by various SW components, latest version 1.1
+       USHORT                          PowerSourceInfo;                                        // Shared by various SW components, latest versoin 1.1
+}ATOM_MASTER_LIST_OF_DATA_TABLES;
+
+typedef struct _ATOM_MASTER_DATA_TABLE
+{ 
+  ATOM_COMMON_TABLE_HEADER sHeader;  
+  ATOM_MASTER_LIST_OF_DATA_TABLES   ListOfDataTables;
+}ATOM_MASTER_DATA_TABLE;
+
+// For backward compatible 
+#define LVDS_Info                LCD_Info
+#define DAC_Info                 PaletteData
+#define TMDS_Info                DIGTransmitterInfo
+
+/****************************************************************************/ 
+// Structure used in MultimediaCapabilityInfoTable
+/****************************************************************************/ 
+typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
+{
+  ATOM_COMMON_TABLE_HEADER sHeader;  
+  ULONG                    ulSignature;      // HW info table signature string "$ATI"
+  UCHAR                    ucI2C_Type;       // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
+  UCHAR                    ucTV_OutInfo;     // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
+  UCHAR                    ucVideoPortInfo;  // Provides the video port capabilities
+  UCHAR                    ucHostPortInfo;   // Provides host port configuration information
+}ATOM_MULTIMEDIA_CAPABILITY_INFO;
+
+/****************************************************************************/ 
+// Structure used in MultimediaConfigInfoTable
+/****************************************************************************/ 
+typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
+{
+  ATOM_COMMON_TABLE_HEADER sHeader;
+  ULONG                    ulSignature;      // MM info table signature sting "$MMT"
+  UCHAR                    ucTunerInfo;      // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
+  UCHAR                    ucAudioChipInfo;  // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
+  UCHAR                    ucProductID;      // Defines as OEM ID or ATI board ID dependent on product type setting
+  UCHAR                    ucMiscInfo1;      // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
+  UCHAR                    ucMiscInfo2;      // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
+  UCHAR                    ucMiscInfo3;      // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
+  UCHAR                    ucMiscInfo4;      // Video Decoder Host Config (2:0) reserved (7:3)
+  UCHAR                    ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+  UCHAR                    ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+  UCHAR                    ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+  UCHAR                    ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+  UCHAR                    ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
+}ATOM_MULTIMEDIA_CONFIG_INFO;
+
+
+/****************************************************************************/ 
+// Structures used in FirmwareInfoTable
+/****************************************************************************/ 
+
+// usBIOSCapability Definition:
+// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 
+// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 
+// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 
+// Others: Reserved
+#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
+#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
+#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
+#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008             // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 
+#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010             // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 
+#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
+#define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
+#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
+#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
+#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
+#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
+#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
+#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT  0x0008             // (valid from v2.1 ): =1: memclk ss enable with external ss chip
+#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT  0x0010             // (valid from v2.1 ): =1: engclk ss enable with external ss chip
+
+#ifndef _H2INC
+
+//Please don't add or expand this bitfield structure below, this one will retire soon.!
+typedef struct _ATOM_FIRMWARE_CAPABILITY
+{
+#if ATOM_BIG_ENDIAN
+  USHORT Reserved:1;
+  USHORT SCL2Redefined:1;
+  USHORT PostWithoutModeSet:1;
+  USHORT HyperMemory_Size:4;
+  USHORT HyperMemory_Support:1;
+  USHORT PPMode_Assigned:1;
+  USHORT WMI_SUPPORT:1;
+  USHORT GPUControlsBL:1;
+  USHORT EngineClockSS_Support:1;
+  USHORT MemoryClockSS_Support:1;
+  USHORT ExtendedDesktopSupport:1;
+  USHORT DualCRTC_Support:1;
+  USHORT FirmwarePosted:1;
+#else
+  USHORT FirmwarePosted:1;
+  USHORT DualCRTC_Support:1;
+  USHORT ExtendedDesktopSupport:1;
+  USHORT MemoryClockSS_Support:1;
+  USHORT EngineClockSS_Support:1;
+  USHORT GPUControlsBL:1;
+  USHORT WMI_SUPPORT:1;
+  USHORT PPMode_Assigned:1;
+  USHORT HyperMemory_Support:1;
+  USHORT HyperMemory_Size:4;
+  USHORT PostWithoutModeSet:1;
+  USHORT SCL2Redefined:1;
+  USHORT Reserved:1;
+#endif
+}ATOM_FIRMWARE_CAPABILITY;
+
+typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
+{
+  ATOM_FIRMWARE_CAPABILITY sbfAccess;
+  USHORT                   susAccess;
+}ATOM_FIRMWARE_CAPABILITY_ACCESS;
+
+#else
+
+typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
+{
+  USHORT                   susAccess;
+}ATOM_FIRMWARE_CAPABILITY_ACCESS;
+
+#endif
+
+typedef struct _ATOM_FIRMWARE_INFO
+{
+  ATOM_COMMON_TABLE_HEADER        sHeader; 
+  ULONG                           ulFirmwareRevision;
+  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
+  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
+  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
+  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
+  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
+  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
+  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
+  UCHAR                           ucASICMaxTemperature;
+  UCHAR                           ucPadding[3];               //Don't use them
+  ULONG                           aulReservedForBIOS[3];      //Don't use them
+  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
+  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
+  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit, the definitions above can't change!!!
+  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+  USHORT                          usReferenceClock;           //In 10Khz unit  
+  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
+  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
+  UCHAR                           ucDesign_ID;                //Indicate what is the board design
+  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
+}ATOM_FIRMWARE_INFO;
+
+typedef struct _ATOM_FIRMWARE_INFO_V1_2
+{
+  ATOM_COMMON_TABLE_HEADER        sHeader; 
+  ULONG                           ulFirmwareRevision;
+  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
+  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
+  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
+  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
+  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
+  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
+  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
+  UCHAR                           ucASICMaxTemperature;
+  UCHAR                           ucMinAllowedBL_Level;
+  UCHAR                           ucPadding[2];               //Don't use them
+  ULONG                           aulReservedForBIOS[2];      //Don't use them
+  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
+  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
+  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
+  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
+  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+  USHORT                          usReferenceClock;           //In 10Khz unit  
+  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
+  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
+  UCHAR                           ucDesign_ID;                //Indicate what is the board design
+  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
+}ATOM_FIRMWARE_INFO_V1_2;
+
+typedef struct _ATOM_FIRMWARE_INFO_V1_3
+{
+  ATOM_COMMON_TABLE_HEADER        sHeader; 
+  ULONG                           ulFirmwareRevision;
+  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
+  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
+  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
+  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
+  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
+  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
+  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
+  UCHAR                           ucASICMaxTemperature;
+  UCHAR                           ucMinAllowedBL_Level;
+  UCHAR                           ucPadding[2];               //Don't use them
+  ULONG                           aulReservedForBIOS;         //Don't use them
+  ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
+  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
+  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
+  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
+  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
+  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+  USHORT                          usReferenceClock;           //In 10Khz unit  
+  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
+  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
+  UCHAR                           ucDesign_ID;                //Indicate what is the board design
+  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
+}ATOM_FIRMWARE_INFO_V1_3;
+
+typedef struct _ATOM_FIRMWARE_INFO_V1_4
+{
+  ATOM_COMMON_TABLE_HEADER        sHeader; 
+  ULONG                           ulFirmwareRevision;
+  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
+  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
+  ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
+  ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
+  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
+  ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
+  ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
+  UCHAR                           ucASICMaxTemperature;
+  UCHAR                           ucMinAllowedBL_Level;
+  USHORT                          usBootUpVDDCVoltage;        //In MV unit
+  USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
+  USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
+  ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
+  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
+  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
+  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
+  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
+  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+  USHORT                          usReferenceClock;           //In 10Khz unit  
+  USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit 
+  UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
+  UCHAR                           ucDesign_ID;                //Indicate what is the board design
+  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
+}ATOM_FIRMWARE_INFO_V1_4;
+
+//the structure below to be used from Cypress
+typedef struct _ATOM_FIRMWARE_INFO_V2_1
+{
+  ATOM_COMMON_TABLE_HEADER        sHeader; 
+  ULONG                           ulFirmwareRevision;
+  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
+  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
+  ULONG                           ulReserved1;
+  ULONG                           ulReserved2;
+  ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
+  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
+  ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock
+  ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit
+  UCHAR                           ucReserved1;                //Was ucASICMaxTemperature;
+  UCHAR                           ucMinAllowedBL_Level;
+  USHORT                          usBootUpVDDCVoltage;        //In MV unit
+  USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
+  USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
+  ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
+  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
+  USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
+  USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
+  USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
+  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
+  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+  USHORT                          usCoreReferenceClock;       //In 10Khz unit  
+  USHORT                          usMemoryReferenceClock;     //In 10Khz unit  
+  USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
+  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
+  UCHAR                           ucReserved4[3];
+}ATOM_FIRMWARE_INFO_V2_1;
+
+//the structure below to be used from NI
+//ucTableFormatRevision=2
+//ucTableContentRevision=2
+typedef struct _ATOM_FIRMWARE_INFO_V2_2
+{
+  ATOM_COMMON_TABLE_HEADER        sHeader; 
+  ULONG                           ulFirmwareRevision;
+  ULONG                           ulDefaultEngineClock;       //In 10Khz unit
+  ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
+  ULONG                           ulReserved[2];
+  ULONG                           ulReserved1;                //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
+  ULONG                           ulReserved2;                //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
+  ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
+  ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock  ?
+  ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.          
+  UCHAR                           ucReserved3;                //Was ucASICMaxTemperature;
+  UCHAR                           ucMinAllowedBL_Level;
+  USHORT                          usBootUpVDDCVoltage;        //In MV unit
+  USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
+  USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
+  ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
+  ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
+  UCHAR                           ucRemoteDisplayConfig;
+  UCHAR                           ucReserved5[3];             //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
+  ULONG                           ulReserved6;                //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
+  ULONG                           ulReserved7;                //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
+  USHORT                          usReserved11;               //Was usMaxPixelClock;  //In 10Khz unit, Max.  Pclk used only for DAC
+  USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
+  USHORT                          usBootUpVDDCIVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
+  ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+  USHORT                          usCoreReferenceClock;       //In 10Khz unit  
+  USHORT                          usMemoryReferenceClock;     //In 10Khz unit  
+  USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
+  UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
+  UCHAR                           ucReserved9[3];
+  USHORT                          usBootUpMVDDCVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
+  USHORT                          usReserved12;
+  ULONG                           ulReserved10[3];            // New added comparing to previous version
+}ATOM_FIRMWARE_INFO_V2_2;
+
+#define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V2_2
+
+
+// definition of ucRemoteDisplayConfig
+#define REMOTE_DISPLAY_DISABLE                   0x00
+#define REMOTE_DISPLAY_ENABLE                    0x01
+
+/****************************************************************************/ 
+// Structures used in IntegratedSystemInfoTable
+/****************************************************************************/ 
+#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
+#define IGP_CAP_FLAG_AC_CARD               0x4
+#define IGP_CAP_FLAG_SDVO_CARD             0x8
+#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
+
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
+{
+  ATOM_COMMON_TABLE_HEADER        sHeader; 
+  ULONG                                  ulBootUpEngineClock;              //in 10kHz unit
+  ULONG                                  ulBootUpMemoryClock;              //in 10kHz unit
+  ULONG                                  ulMaxSystemMemoryClock;           //in 10kHz unit
+  ULONG                                  ulMinSystemMemoryClock;           //in 10kHz unit
+  UCHAR                           ucNumberOfCyclesInPeriodHi;
+  UCHAR                           ucLCDTimingSel;             //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
+  USHORT                          usReserved1;
+  USHORT                          usInterNBVoltageLow;        //An intermidiate PMW value to set the voltage 
+  USHORT                          usInterNBVoltageHigh;       //Another intermidiate PMW value to set the voltage 
+  ULONG                                  ulReserved[2];
+
+  USHORT                               usFSBClock;                                 //In MHz unit
+  USHORT                          usCapabilityFlag;                    //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
+                                                                                                                                                             //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
+                                                              //Bit[4]==1: P/2 mode, ==0: P/1 mode
+  USHORT                               usPCIENBCfgReg7;                                    //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
+  USHORT                               usK8MemoryClock;            //in MHz unit
+  USHORT                               usK8SyncStartDelay;         //in 0.01 us unit
+  USHORT                               usK8DataReturnTime;         //in 0.01 us unit
+  UCHAR                           ucMaxNBVoltage;
+  UCHAR                           ucMinNBVoltage;
+  UCHAR                           ucMemoryType;                                              //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
+  UCHAR                           ucNumberOfCyclesInPeriod;            //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 
+  UCHAR                           ucSta