From 4f5c2ed3649584b315f4bb9bef88ca57b30f7fbc Mon Sep 17 00:00:00 2001 From: John Marino Date: Fri, 17 Apr 2015 10:06:03 +0200 Subject: [PATCH] gcc50: Upgrade to GCC 5.1 release candidate plus while here: * remove 4+ Mb of unused texi files from contrib * update the 3 man pages from Release candidate * Change makefiles to not take man pages from contrib directory After thinking about it, I've decided to continue to update GCC from Subversion sources rather than limit updates to designated releases. This is the reason the man pages are not taken from contrib; they are only present in actual releases and not the SVN repository. The plan is to only update the man pages when GCC minor version is released. This is the first (and likely only) release candidate for GCC5. It will be known as gcc 5.1.0, but CCVER will remain at "gcc50" regardless if the version of gcc is 5.1.1 or 5.4.2. This includes changes up to SVN 222168 (April 17). --- contrib/gcc-5.0/README.DELETED | 28 +- contrib/gcc-5.0/README.DRAGONFLY | 14 +- gnu/usr.bin/cc50/Makefile.version | 4 +- gnu/usr.bin/cc50/drivers/cc/Makefile | 2 +- gnu/usr.bin/cc50/drivers/cc/gcc.1 | 7534 ++++++++++++------------ gnu/usr.bin/cc50/drivers/cpp/Makefile | 2 +- gnu/usr.bin/cc50/drivers/cpp/cpp.1 | 75 +- gnu/usr.bin/cc50/drivers/gcov/Makefile | 2 +- gnu/usr.bin/cc50/drivers/gcov/gcov.1 | 31 +- 9 files changed, 4000 insertions(+), 3692 deletions(-) diff --git a/contrib/gcc-5.0/README.DELETED b/contrib/gcc-5.0/README.DELETED index 0fa25d5f10..5316c49725 100644 --- a/contrib/gcc-5.0/README.DELETED +++ b/contrib/gcc-5.0/README.DELETED @@ -377,31 +377,7 @@ gcc/cp/Make-lang.in gcc/cp/NEWS gcc/cp/config-lang.in gcc/cstamp-h.in -gcc/doc/aot-compile.1 -gcc/doc/cpp.info -gcc/doc/cppinternals.info -gcc/doc/fsf-funding.7 -gcc/doc/gc-analyze.1 -gcc/doc/gcc.info -gcc/doc/gccinstall.info -gcc/doc/gccint.info -gcc/doc/gcj-dbtool.1 -gcc/doc/gcj.1 -gcc/doc/gcj.info -gcc/doc/gfdl.7 -gcc/doc/gfortran.1 -gcc/doc/gij.1 -gcc/doc/gpl.7 -gcc/doc/grmic.1 -gcc/doc/include/gpl.texi -gcc/doc/include/texinfo.tex -gcc/doc/install-old.texi -gcc/doc/install.texi -gcc/doc/install.texi2html -gcc/doc/jcf-dump.1 -gcc/doc/jv-convert.1 -gcc/doc/rebuild-gcj-db.1 -gcc/doc/tm.texi.in +gcc/doc/ gcc/exec-tool.in gcc/fortran/ gcc/gdbasan.in @@ -634,6 +610,7 @@ libiberty/README libiberty/_doprnt.c libiberty/aclocal.m4 libiberty/asprintf.c +libiberty/at-file.texi libiberty/atexit.c libiberty/basename.c libiberty/bcmp.c @@ -716,6 +693,7 @@ libitm/aclocal.m4 libitm/config.h.in libitm/configure libitm/configure.ac +libitm/libitm.texi libjava/ libmpx/ libobjc/ChangeLog diff --git a/contrib/gcc-5.0/README.DRAGONFLY b/contrib/gcc-5.0/README.DRAGONFLY index 3ed99a528f..68a49ecdb8 100644 --- a/contrib/gcc-5.0/README.DRAGONFLY +++ b/contrib/gcc-5.0/README.DRAGONFLY @@ -1,13 +1,15 @@ -GCC-5.0.0 SNAPSHOT +GCC-5.0.1 SNAPSHOT ================== -Original source can be downloaded from: +Original source of man pages can be downloaded from: http://ftp.gnu.org/gnu/gcc -XXX file = gcc-5-20150201.tar.bz2 -XXX date = 1 Febuary 2015 -XXX size = 89749171 -XXX sha1 = 0558cb236c982b5e1931ed18fc06967b3da1cd99 +file = gcc-5.1.0-RC-20150412.tar.bz2 +date = 13 April 2015 +size = 95081824 +sha1 = 405c12ba75a30d52ed3e0b369e84e36a6ec7d6a4 + +The source files are pulled directly from GCC's Subversion repository. See LAST_UPDATED for SVN revision The file README.DELETED contains a list of deleted files and directories. diff --git a/gnu/usr.bin/cc50/Makefile.version b/gnu/usr.bin/cc50/Makefile.version index 639baff57f..9e287e0010 100644 --- a/gnu/usr.bin/cc50/Makefile.version +++ b/gnu/usr.bin/cc50/Makefile.version @@ -1,5 +1,5 @@ -GCCCOMPLETEVER= 5.0.0 +GCCCOMPLETEVER= 5.0.1 GCCRELEASE= Snapshot # choices are "Snapshot" or "Release" -GCCDATESTAMP= 2015-04-02 +GCCDATESTAMP= 2015-04-17 GCCPOINTVER= ${GCCCOMPLETEVER:R} GCCSHORTVER= ${GCCPOINTVER:S/.//} diff --git a/gnu/usr.bin/cc50/drivers/cc/Makefile b/gnu/usr.bin/cc50/drivers/cc/Makefile index 0f9552a4a6..693b0c01b7 100644 --- a/gnu/usr.bin/cc50/drivers/cc/Makefile +++ b/gnu/usr.bin/cc50/drivers/cc/Makefile @@ -13,7 +13,7 @@ CFLAGS+= -DCONFIGURE_SPECS="\"\"" \ -DACCEL_DIR_SUFFIX="\"\"" \ -DDEFAULT_REAL_TARGET_MACHINE="\"${target_machine}\"" -DOC_Release= ${GCCDIR}/gcc/doc/gcc.1 +DOC_Release= gcc.1 #${GCCDIR}/gcc/doc/gcc.1 DOC_Snapshot= gcc.1 ${MFILE}: ${DOC_${GCCRELEASE}} diff --git a/gnu/usr.bin/cc50/drivers/cc/gcc.1 b/gnu/usr.bin/cc50/drivers/cc/gcc.1 index 023ecd05e6..1282146c27 100644 --- a/gnu/usr.bin/cc50/drivers/cc/gcc.1 +++ b/gnu/usr.bin/cc50/drivers/cc/gcc.1 @@ -1,4 +1,4 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.20) +.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.29) .\" .\" Standard preamble: .\" ======================================================================== @@ -38,6 +38,8 @@ . ds PI \(*p . ds L" `` . ds R" '' +. ds C` +. ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. @@ -48,17 +50,24 @@ .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. -.ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX .. -. nr % 0 -. rr F -.\} -.el \{\ -. de IX +.nr rF 0 +.if \n(.g .if rF .nr rF 1 +.if (\n(rF:(\n(.g==0)) \{ +. if \nF \{ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. +. if !\nF==2 \{ +. nr % 0 +. nr F 2 +. \} +. \} .\} +.rr rF .\" .\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). .\" Fear. Run. Save yourself. No user-serviceable parts. @@ -124,7 +133,7 @@ .\" ======================================================================== .\" .IX Title "GCC 1" -.TH GCC 1 "2015-01-11" "gcc-5.0.0" "GNU" +.TH GCC 1 "2015-04-12" "gcc-5.0.1" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -145,7 +154,7 @@ Only the most useful options are listed here; see below for the remainder. \fBg++\fR accepts mostly the same options as \fBgcc\fR. .SH "DESCRIPTION" .IX Header "DESCRIPTION" -When you invoke \s-1GCC\s0, it normally does preprocessing, compilation, +When you invoke \s-1GCC,\s0 it normally does preprocessing, compilation, assembly and linking. The \*(L"overall options\*(R" allow you to stop this process at an intermediate stage. For example, the \fB\-c\fR option says not to run the linker. Then the output consists of object files @@ -196,8 +205,8 @@ in the following sections. \&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline \&\-aux\-info\fR \fIfilename\fR \fB\-fallow\-parameterless\-variadic\-functions \&\-fno\-asm \-fno\-builtin \-fno\-builtin\-\fR\fIfunction\fR -\&\fB\-fhosted \-ffreestanding \-fopenmp \-fopenmp\-simd \-fms\-extensions -\&\-fplan9\-extensions \-trigraphs \-traditional \-traditional\-cpp +\&\fB\-fhosted \-ffreestanding \-fopenacc \-fopenmp \-fopenmp\-simd +\&\-fms\-extensions \-fplan9\-extensions \-trigraphs \-traditional \-traditional\-cpp \&\-fallow\-single\-precision \-fcond\-mismatch \-flax\-vector\-conversions \&\-fsigned\-bitfields \-fsigned\-char \&\-funsigned\-bitfields \-funsigned\-char\fR @@ -224,7 +233,7 @@ in the following sections. \&\fB\-fvtv\-counts \-fvtv\-debug \&\-fvisibility\-ms\-compat \&\-fext\-numeric\-literals -\&\-Wabi=\fR\fIn\fR \fB\-Wconversion\-null \-Wctor\-dtor\-privacy +\&\-Wabi=\fR\fIn\fR \fB\-Wabi\-tag \-Wconversion\-null \-Wctor\-dtor\-privacy \&\-Wdelete\-non\-virtual\-dtor \-Wliteral\-suffix \-Wnarrowing \&\-Wnoexcept \-Wnon\-virtual\-dtor \-Wreorder \&\-Weffc++ \-Wstrict\-null\-sentinel @@ -263,8 +272,8 @@ in the following sections. \&\fB\-fsyntax\-only \-fmax\-errors=\fR\fIn\fR \fB\-Wpedantic \&\-pedantic\-errors \&\-w \-Wextra \-Wall \-Waddress \-Waggregate\-return -\&\-Waggressive\-loop\-optimizations \-Warray\-bounds -\&\-Wbool\-compare +\&\-Waggressive\-loop\-optimizations \-Warray\-bounds \-Warray\-bounds=\fR\fIn\fR +\&\fB\-Wbool\-compare \&\-Wno\-attributes \-Wno\-builtin\-macro\-redefined \&\-Wc90\-c99\-compat \-Wc99\-c11\-compat \&\-Wc++\-compat \-Wc++11\-compat \-Wc++14\-compat \-Wcast\-align \-Wcast\-qual @@ -324,6 +333,15 @@ in the following sections. \&\fB\-d\fR\fIletters\fR \fB\-dumpspecs \-dumpmachine \-dumpversion \&\-fsanitize=\fR\fIstyle\fR \fB\-fsanitize\-recover \-fsanitize\-recover=\fR\fIstyle\fR \&\fB\-fasan\-shadow\-offset=\fR\fInumber\fR \fB\-fsanitize\-undefined\-trap\-on\-error +\&\-fcheck\-pointer\-bounds \-fchkp\-check\-incomplete\-type +\&\-fchkp\-first\-field\-has\-own\-bounds \-fchkp\-narrow\-bounds +\&\-fchkp\-narrow\-to\-innermost\-array \-fchkp\-optimize +\&\-fchkp\-use\-fast\-string\-functions \-fchkp\-use\-nochk\-string\-functions +\&\-fchkp\-use\-static\-bounds \-fchkp\-use\-static\-const\-bounds +\&\-fchkp\-treat\-zero\-dynamic\-size\-as\-infinite \-fchkp\-check\-read +\&\-fchkp\-check\-read \-fchkp\-check\-write \-fchkp\-store\-bounds +\&\-fchkp\-instrument\-calls \-fchkp\-instrument\-marked\-only +\&\-fchkp\-use\-wrappers \&\-fdbg\-cnt\-list \-fdbg\-cnt=\fR\fIcounter-value-list\fR \&\fB\-fdisable\-ipa\-\fR\fIpass_name\fR \&\fB\-fdisable\-rtl\-\fR\fIpass_name\fR @@ -408,7 +426,7 @@ in the following sections. \&\-fgcse\-sm \-fhoist\-adjacent\-loads \-fif\-conversion \&\-fif\-conversion2 \-findirect\-inlining \&\-finline\-functions \-finline\-functions\-called\-once \-finline\-limit=\fR\fIn\fR -\&\fB\-finline\-small\-functions \-fipa\-cp \-fipa\-cp\-clone +\&\fB\-finline\-small\-functions \-fipa\-cp \-fipa\-cp\-clone \-fipa\-cp\-alignment \&\-fipa\-pta \-fipa\-profile \-fipa\-pure\-const \-fipa\-reference \-fipa\-icf \&\-fira\-algorithm=\fR\fIalgorithm\fR \&\fB\-fira\-region=\fR\fIregion\fR \fB\-fira\-hoist\-pressure @@ -449,8 +467,9 @@ in the following sections. \&\-fsel\-sched\-pipelining \-fsel\-sched\-pipelining\-outer\-loops \&\-fsemantic\-interposition \&\-fshrink\-wrap \-fsignaling\-nans \-fsingle\-precision\-constant -\&\-fsplit\-ivs\-in\-unroller \-fsplit\-wide\-types \-fssa\-phiopt \-fstack\-protector -\&\-fstack\-protector\-all \-fstack\-protector\-strong \-fstrict\-aliasing +\&\-fsplit\-ivs\-in\-unroller \-fsplit\-wide\-types \-fssa\-phiopt +\&\-fstack\-protector \-fstack\-protector\-all \-fstack\-protector\-strong +\&\-fstack\-protector\-explicit \-fstdarg\-opt \-fstrict\-aliasing \&\-fstrict\-overflow \-fthread\-jumps \-ftracer \-ftree\-bit\-ccp \&\-ftree\-builtin\-call\-dce \-ftree\-ccp \-ftree\-ch \&\-ftree\-coalesce\-inline\-vars \-ftree\-coalesce\-vars \-ftree\-copy\-prop @@ -467,7 +486,7 @@ in the following sections. \&\-funit\-at\-a\-time \-funroll\-all\-loops \-funroll\-loops \&\-funsafe\-loop\-optimizations \-funsafe\-math\-optimizations \-funswitch\-loops \&\-fipa\-ra \-fvariable\-expansion\-in\-unroller \-fvect\-cost\-model \-fvpt -\&\-fweb \-fwhole\-program \-fwpa \-fuse\-ld=\fR\fIlinker\fR \fB\-fuse\-linker\-plugin +\&\-fweb \-fwhole\-program \-fwpa \-fuse\-linker\-plugin \&\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR \&\fB\-O \-O0 \-O1 \-O2 \-O3 \-Os \-Ofast \-Og\fR .IP "\fIPreprocessor Options\fR" 4 @@ -490,10 +509,11 @@ in the following sections. \&\fB\-Wa,\fR\fIoption\fR \fB\-Xassembler\fR \fIoption\fR .IP "\fILinker Options\fR" 4 .IX Item "Linker Options" -\&\fIobject-file-name\fR \fB\-l\fR\fIlibrary\fR +\&\fIobject-file-name\fR \fB\-fuse\-ld=\fR\fIlinker\fR \fB\-l\fR\fIlibrary\fR \&\fB\-nostartfiles \-nodefaultlibs \-nostdlib \-pie \-rdynamic \&\-s \-static \-static\-libgcc \-static\-libstdc++ \&\-static\-libasan \-static\-libtsan \-static\-liblsan \-static\-libubsan +\&\-static\-libmpx \-static\-libmpxwrappers \&\-shared \-shared\-libgcc \-symbolic \&\-T\fR \fIscript\fR \fB\-Wl,\fR\fIoption\fR \fB\-Xlinker\fR \fIoption\fR \&\fB\-u\fR \fIsymbol\fR \fB\-z\fR \fIkeyword\fR @@ -551,7 +571,8 @@ in the following sections. \&\fB\-mfp16\-format=\fR\fIname\fR \&\fB\-mthumb\-interwork \-mno\-thumb\-interwork \&\-mcpu=\fR\fIname\fR \fB\-march=\fR\fIname\fR \fB\-mfpu=\fR\fIname\fR -\&\fB\-mstructure\-size\-boundary=\fR\fIn\fR +\&\fB\-mtune=\fR\fIname\fR \fB\-mprint\-tune\-info +\&\-mstructure\-size\-boundary=\fR\fIn\fR \&\fB\-mabort\-on\-noreturn \&\-mlong\-calls \-mno\-long\-calls \&\-msingle\-pic\-base \-mno\-single\-pic\-base @@ -572,8 +593,8 @@ in the following sections. .Sp \&\fI\s-1AVR\s0 Options\fR \&\fB\-mmcu=\fR\fImcu\fR \fB\-maccumulate\-args \-mbranch\-cost=\fR\fIcost\fR -\&\fB\-mcall\-prologues \-mint8 \-mno\-interrupts \-mrelax -\&\-mstrict\-X \-mtiny\-stack \-Waddr\-space\-convert\fR +\&\fB\-mcall\-prologues \-mint8 \-mn_flash=\fR\fIsize\fR \fB\-mno\-interrupts +\&\-mrelax \-mrmw \-mstrict\-X \-mtiny\-stack \-nodevicelib \-Waddr\-space\-convert\fR .Sp \&\fIBlackfin Options\fR \&\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR] @@ -687,44 +708,6 @@ in the following sections. \&\-mschedule=\fR\fIcpu-type\fR \fB\-mspace\-regs \-msio \-mwsio \&\-munix=\fR\fIunix-std\fR \fB\-nolibdld \-static \-threads\fR .Sp -\&\fIi386 and x86\-64 Options\fR -\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR -\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR \fB\-mdump\-tune\-features \-mno\-default -\&\-mfpmath=\fR\fIunit\fR -\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387 -\&\-mno\-fp\-ret\-in\-387 \-msoft\-float -\&\-mno\-wide\-multiply \-mrtd \-malign\-double -\&\-mpreferred\-stack\-boundary=\fR\fInum\fR -\&\fB\-mincoming\-stack\-boundary=\fR\fInum\fR -\&\fB\-mcld \-mcx16 \-msahf \-mmovbe \-mcrc32 -\&\-mrecip \-mrecip=\fR\fIopt\fR -\&\fB\-mvzeroupper \-mprefer\-avx128 -\&\-mmmx \-msse \-msse2 \-msse3 \-mssse3 \-msse4.1 \-msse4.2 \-msse4 \-mavx -\&\-mavx2 \-mavx512f \-mavx512pf \-mavx512er \-mavx512cd \-msha -\&\-maes \-mpclmul \-mfsgsbase \-mrdrnd \-mf16c \-mfma \-mprefetchwt1 -\&\-mclflushopt \-mxsavec \-mxsaves -\&\-msse4a \-m3dnow \-mpopcnt \-mabm \-mbmi \-mtbm \-mfma4 \-mxop \-mlzcnt -\&\-mbmi2 \-mfxsr \-mxsave \-mxsaveopt \-mrtm \-mlwp \-mmpx \-mthreads -\&\-mno\-align\-stringops \-minline\-all\-stringops -\&\-minline\-stringops\-dynamically \-mstringop\-strategy=\fR\fIalg\fR -\&\fB\-mmemcpy\-strategy=\fR\fIstrategy\fR \fB\-mmemset\-strategy=\fR\fIstrategy\fR -\&\fB\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double -\&\-m96bit\-long\-double \-mlong\-double\-64 \-mlong\-double\-80 \-mlong\-double\-128 -\&\-mregparm=\fR\fInum\fR \fB\-msseregparm -\&\-mveclibabi=\fR\fItype\fR \fB\-mvect8\-ret\-in\-mem -\&\-mpc32 \-mpc64 \-mpc80 \-mstackrealign -\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs -\&\-mcmodel=\fR\fIcode-model\fR \fB\-mabi=\fR\fIname\fR \fB\-maddress\-mode=\fR\fImode\fR -\&\fB\-m32 \-m64 \-mx32 \-m16 \-mlarge\-data\-threshold=\fR\fInum\fR -\&\fB\-msse2avx \-mfentry \-mrecord\-mcount \-mnop\-mcount \-m8bit\-idiv -\&\-mavx256\-split\-unaligned\-load \-mavx256\-split\-unaligned\-store -\&\-malign\-data=\fR\fItype\fR \fB\-mstack\-protector\-guard=\fR\fIguard\fR -.Sp -\&\fIi386 and x86\-64 Windows Options\fR -\&\fB\-mconsole \-mcygwin \-mno\-cygwin \-mdll -\&\-mnop\-fun\-dllimport \-mthread -\&\-municode \-mwin32 \-mwindows \-fno\-set\-stack\-executable\fR -.Sp \&\fI\s-1IA\-64\s0 Options\fR \&\fB\-mbig\-endian \-mlittle\-endian \-mgnu\-as \-mgnu\-ld \-mno\-pic \&\-mvolatile\-asm\-stop \-mregister\-names \-msdata \-mno\-sdata @@ -872,15 +855,15 @@ in the following sections. \&\-mperf\-ext \-mno\-perf\-ext \&\-mv3push \-mno\-v3push \&\-m16bit \-mno\-16bit -\&\-mgp\-direct \-mno\-gp\-direct \&\-misr\-vector\-size=\fR\fInum\fR \&\fB\-mcache\-block\-size=\fR\fInum\fR \&\fB\-march=\fR\fIarch\fR -\&\fB\-mforce\-fp\-as\-gp \-mforbid\-fp\-as\-gp -\&\-mex9 \-mctor\-dtor \-mrelax\fR +\&\fB\-mcmodel=\fR\fIcode-model\fR +\&\fB\-mctor\-dtor \-mrelax\fR .Sp \&\fINios \s-1II\s0 Options\fR -\&\fB\-G\fR \fInum\fR \fB\-mgpopt \-mno\-gpopt \-mel \-meb +\&\fB\-G\fR \fInum\fR \fB\-mgpopt=\fR\fIoption\fR \fB\-mgpopt \-mno\-gpopt +\&\-mel \-meb \&\-mno\-bypass\-cache \-mbypass\-cache \&\-mno\-cache\-volatile \-mcache\-volatile \&\-mno\-fast\-sw\-div \-mfast\-sw\-div @@ -889,6 +872,9 @@ in the following sections. \&\fB\-mcustom\-fpu\-cfg=\fR\fIname\fR \&\fB\-mhal \-msmallc \-msys\-crt0=\fR\fIname\fR \fB\-msys\-lib=\fR\fIname\fR .Sp +\&\fINvidia \s-1PTX\s0 Options\fR +\&\fB\-m32 \-m64 \-mmainkernel\fR +.Sp \&\fI\s-1PDP\-11\s0 Options\fR \&\fB\-mfpu \-msoft\-float \-mac0 \-mno\-ac0 \-m40 \-m45 \-m10 \&\-mbcopy \-mbcopy\-builtin \-mint32 \-mno\-int16 @@ -987,7 +973,7 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch \&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd \&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard -\&\-mhotpatch[=\fR\fIhalfwords\fR\fB] \-mno\-hotpatch\fR +\&\-mhotpatch=\fR\fIhalfwords\fR\fB,\fR\fIhalfwords\fR .Sp \&\fIScore Options\fR \&\fB\-meb \-mel @@ -1014,6 +1000,7 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-maccumulate\-outgoing\-args \-minvalid\-symbols \&\-matomic\-model=\fR\fIatomic-model\fR \&\fB\-mbranch\-cost=\fR\fInum\fR \fB\-mzdcbranch \-mno\-zdcbranch +\&\-mcbranch\-force\-delay\-slot \&\-mfused\-madd \-mno\-fused\-madd \-mfsca \-mno\-fsca \-mfsrra \-mno\-fsrra \&\-mpretend\-cmove \-mtas\fR .Sp @@ -1092,8 +1079,43 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\fB\-mrtp \-non\-static \-Bstatic \-Bdynamic \&\-Xbind\-lazy \-Xbind\-now\fR .Sp -\&\fIx86\-64 Options\fR -See i386 and x86\-64 Options. +\&\fIx86 Options\fR +\&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR \fB\-mdump\-tune\-features \-mno\-default +\&\-mfpmath=\fR\fIunit\fR +\&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387 +\&\-mno\-fp\-ret\-in\-387 \-msoft\-float +\&\-mno\-wide\-multiply \-mrtd \-malign\-double +\&\-mpreferred\-stack\-boundary=\fR\fInum\fR +\&\fB\-mincoming\-stack\-boundary=\fR\fInum\fR +\&\fB\-mcld \-mcx16 \-msahf \-mmovbe \-mcrc32 +\&\-mrecip \-mrecip=\fR\fIopt\fR +\&\fB\-mvzeroupper \-mprefer\-avx128 +\&\-mmmx \-msse \-msse2 \-msse3 \-mssse3 \-msse4.1 \-msse4.2 \-msse4 \-mavx +\&\-mavx2 \-mavx512f \-mavx512pf \-mavx512er \-mavx512cd \-msha +\&\-maes \-mpclmul \-mfsgsbase \-mrdrnd \-mf16c \-mfma \-mprefetchwt1 +\&\-mclflushopt \-mxsavec \-mxsaves +\&\-msse4a \-m3dnow \-mpopcnt \-mabm \-mbmi \-mtbm \-mfma4 \-mxop \-mlzcnt +\&\-mbmi2 \-mfxsr \-mxsave \-mxsaveopt \-mrtm \-mlwp \-mmpx \-mthreads +\&\-mno\-align\-stringops \-minline\-all\-stringops +\&\-minline\-stringops\-dynamically \-mstringop\-strategy=\fR\fIalg\fR +\&\fB\-mmemcpy\-strategy=\fR\fIstrategy\fR \fB\-mmemset\-strategy=\fR\fIstrategy\fR +\&\fB\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double +\&\-m96bit\-long\-double \-mlong\-double\-64 \-mlong\-double\-80 \-mlong\-double\-128 +\&\-mregparm=\fR\fInum\fR \fB\-msseregparm +\&\-mveclibabi=\fR\fItype\fR \fB\-mvect8\-ret\-in\-mem +\&\-mpc32 \-mpc64 \-mpc80 \-mstackrealign +\&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs +\&\-mcmodel=\fR\fIcode-model\fR \fB\-mabi=\fR\fIname\fR \fB\-maddress\-mode=\fR\fImode\fR +\&\fB\-m32 \-m64 \-mx32 \-m16 \-mlarge\-data\-threshold=\fR\fInum\fR +\&\fB\-msse2avx \-mfentry \-mrecord\-mcount \-mnop\-mcount \-m8bit\-idiv +\&\-mavx256\-split\-unaligned\-load \-mavx256\-split\-unaligned\-store +\&\-malign\-data=\fR\fItype\fR \fB\-mstack\-protector\-guard=\fR\fIguard\fR +.Sp +\&\fIx86 Windows Options\fR +\&\fB\-mconsole \-mcygwin \-mno\-cygwin \-mdll +\&\-mnop\-fun\-dllimport \-mthread +\&\-municode \-mwin32 \-mwindows \-fno\-set\-stack\-executable\fR .Sp \&\fIXstormy16 Options\fR \&\fB\-msim\fR @@ -1437,7 +1459,7 @@ option. .IX Item "language" Display the options supported for \fIlanguage\fR, where \&\fIlanguage\fR is the name of one of the languages supported in this -version of \s-1GCC\s0. +version of \s-1GCC.\s0 .IP "\fBcommon\fR" 4 .IX Item "common" Display the options that are common to all languages. @@ -1534,7 +1556,7 @@ or \fB/./\fR, or make the path absolute when generating a relative prefix. .IP "\fB\-\-version\fR" 4 .IX Item "--version" -Display the version number and copyrights of the invoked \s-1GCC\s0. +Display the version number and copyrights of the invoked \s-1GCC.\s0 .IP "\fB\-wrapper\fR" 4 .IX Item "-wrapper" Invoke all subcommands under a wrapper program. The name of the @@ -1556,7 +1578,7 @@ the shared object file is used to identify the plugin for the purposes of argument parsing (See \&\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR below). Each plugin should define the callback functions specified in the -Plugins \s-1API\s0. +Plugins \s-1API.\s0 .IP "\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR" 4 .IX Item "-fplugin-arg-name-key=value" Define an argument called \fIkey\fR with a value of \fIvalue\fR @@ -1589,7 +1611,7 @@ backslash) may be included by prefixing the character to be included with a backslash. The \fIfile\fR may itself contain additional @\fIfile\fR options; any such options will be processed recursively. .SS "Compiling \*(C+ Programs" -.IX Subsection "Compiling Programs" +.IX Subsection "Compiling Programs" \&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, \&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or \&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, @@ -1622,8 +1644,8 @@ accepts: In C mode, this is equivalent to \fB\-std=c90\fR. In \*(C+ mode, it is equivalent to \fB\-std=c++98\fR. .Sp -This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO\s0 -C90 (when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), +This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO +C90 \s0(when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the type of system you are using. It also enables the undesirable and @@ -1633,7 +1655,7 @@ the \f(CW\*(C`inline\*(C'\fR keyword. .Sp The alternate keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_extension_\|_\*(C'\fR, \&\f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR continue to work despite -\&\fB\-ansi\fR. You would not want to use them in an \s-1ISO\s0 C program, of +\&\fB\-ansi\fR. You would not want to use them in an \s-1ISO C\s0 program, of course, but it is useful to put them in header files that might be included in compilations done with \fB\-ansi\fR. Alternate predefined macros such as \f(CW\*(C`_\|_unix_\|_\*(C'\fR and \f(CW\*(C`_\|_vax_\|_\*(C'\fR are also available, with or @@ -1650,7 +1672,7 @@ from declaring certain functions or defining certain macros that the programs that might use these names for other things. .Sp Functions that are normally built in but do not have semantics -defined by \s-1ISO\s0 C (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in +defined by \s-1ISO C \s0(such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in functions when \fB\-ansi\fR is used. .IP "\fB\-std=\fR" 4 .IX Item "-std=" @@ -1663,9 +1685,9 @@ The compiler can accept several base standards, such as \fBc90\fR or compiler accepts all programs following that standard plus those using \s-1GNU\s0 extensions that do not contradict it. For example, \&\fB\-std=c90\fR turns off certain features of \s-1GCC\s0 that are -incompatible with \s-1ISO\s0 C90, such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR +incompatible with \s-1ISO C90,\s0 such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, but not other \s-1GNU\s0 extensions that do not have a meaning in -\&\s-1ISO\s0 C90, such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR +\&\s-1ISO C90,\s0 such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR expression. On the other hand, when a \s-1GNU\s0 dialect of a standard is specified, all features supported by the compiler are enabled, even when those features change the meaning of the base standard. As a result, some @@ -1685,11 +1707,11 @@ A value for this option must be provided; possible values are .IP "\fBiso9899:1990\fR" 4 .IX Item "iso9899:1990" .PD -Support all \s-1ISO\s0 C90 programs (certain \s-1GNU\s0 extensions that conflict -with \s-1ISO\s0 C90 are disabled). Same as \fB\-ansi\fR for C code. +Support all \s-1ISO C90\s0 programs (certain \s-1GNU\s0 extensions that conflict +with \s-1ISO C90\s0 are disabled). Same as \fB\-ansi\fR for C code. .IP "\fBiso9899:199409\fR" 4 .IX Item "iso9899:199409" -\&\s-1ISO\s0 C90 as modified in amendment 1. +\&\s-1ISO C90\s0 as modified in amendment 1. .IP "\fBc99\fR" 4 .IX Item "c99" .PD 0 @@ -1700,7 +1722,7 @@ with \s-1ISO\s0 C90 are disabled). Same as \fB\-ansi\fR for C code. .IP "\fBiso9899:199x\fR" 4 .IX Item "iso9899:199x" .PD -\&\s-1ISO\s0 C99. This standard is substantially completely supported, modulo +\&\s-1ISO C99. \s0 This standard is substantially completely supported, modulo bugs and floating-point issues (mainly but not entirely relating to optional C99 features from Annexes F and G). See @@ -1714,7 +1736,7 @@ names \fBc9x\fR and \fBiso9899:199x\fR are deprecated. .IP "\fBiso9899:2011\fR" 4 .IX Item "iso9899:2011" .PD -\&\s-1ISO\s0 C11, the 2011 revision of the \s-1ISO\s0 C standard. This standard is +\&\s-1ISO C11,\s0 the 2011 revision of the \s-1ISO C\s0 standard. This standard is substantially completely supported, modulo bugs, floating-point issues (mainly but not entirely relating to optional C11 features from Annexes F and G) and the optional Annexes K (Bounds-checking @@ -1725,21 +1747,21 @@ interfaces) and L (Analyzability). The name \fBc1x\fR is deprecated. .IP "\fBgnu89\fR" 4 .IX Item "gnu89" .PD -\&\s-1GNU\s0 dialect of \s-1ISO\s0 C90 (including some C99 features). +\&\s-1GNU\s0 dialect of \s-1ISO C90 \s0(including some C99 features). .IP "\fBgnu99\fR" 4 .IX Item "gnu99" .PD 0 .IP "\fBgnu9x\fR" 4 .IX Item "gnu9x" .PD -\&\s-1GNU\s0 dialect of \s-1ISO\s0 C99. The name \fBgnu9x\fR is deprecated. +\&\s-1GNU\s0 dialect of \s-1ISO C99. \s0 The name \fBgnu9x\fR is deprecated. .IP "\fBgnu11\fR" 4 .IX Item "gnu11" .PD 0 .IP "\fBgnu1x\fR" 4 .IX Item "gnu1x" .PD -\&\s-1GNU\s0 dialect of \s-1ISO\s0 C11. This is the default for C code. +\&\s-1GNU\s0 dialect of \s-1ISO C11. \s0 This is the default for C code. The name \fBgnu1x\fR is deprecated. .IP "\fBc++98\fR" 4 .IX Item "c++98" @@ -1747,7 +1769,7 @@ The name \fBgnu1x\fR is deprecated. .IP "\fBc++03\fR" 4 .IX Item "c++03" .PD -The 1998 \s-1ISO\s0 \*(C+ standard plus the 2003 technical corrigendum and some +The 1998 \s-1ISO \*(C+\s0 standard plus the 2003 technical corrigendum and some additional defect reports. Same as \fB\-ansi\fR for \*(C+ code. .IP "\fBgnu++98\fR" 4 .IX Item "gnu++98" @@ -1763,7 +1785,7 @@ additional defect reports. Same as \fB\-ansi\fR for \*(C+ code. .IP "\fBc++0x\fR" 4 .IX Item "c++0x" .PD -The 2011 \s-1ISO\s0 \*(C+ standard plus amendments. +The 2011 \s-1ISO \*(C+\s0 standard plus amendments. The name \fBc++0x\fR is deprecated. .IP "\fBgnu++11\fR" 4 .IX Item "gnu++11" @@ -1779,7 +1801,7 @@ The name \fBgnu++0x\fR is deprecated. .IP "\fBc++1y\fR" 4 .IX Item "c++1y" .PD -The 2014 \s-1ISO\s0 \*(C+ standard plus amendments. +The 2014 \s-1ISO \*(C+\s0 standard plus amendments. The name \fBc++1y\fR is deprecated. .IP "\fBgnu++14\fR" 4 .IX Item "gnu++14" @@ -1791,7 +1813,7 @@ The name \fBc++1y\fR is deprecated. The name \fBgnu++1y\fR is deprecated. .IP "\fBc++1z\fR" 4 .IX Item "c++1z" -The next revision of the \s-1ISO\s0 \*(C+ standard, tentatively planned for +The next revision of the \s-1ISO \*(C+\s0 standard, tentatively planned for 2017. Support is highly experimental, and will almost certainly change in incompatible ways in future releases. .IP "\fBgnu++1z\fR" 4 @@ -1806,16 +1828,14 @@ releases. .IX Item "-fgnu89-inline" The option \fB\-fgnu89\-inline\fR tells \s-1GCC\s0 to use the traditional \&\s-1GNU\s0 semantics for \f(CW\*(C`inline\*(C'\fR functions when in C99 mode. - This option -is accepted and ignored by \s-1GCC\s0 versions 4.1.3 up to but not including -4.3. In \s-1GCC\s0 versions 4.3 and later it changes the behavior of \s-1GCC\s0 in -C99 mode. Using this option is roughly equivalent to adding the +.Sp +Using this option is roughly equivalent to adding the \&\f(CW\*(C`gnu_inline\*(C'\fR function attribute to all inline functions. .Sp The option \fB\-fno\-gnu89\-inline\fR explicitly tells \s-1GCC\s0 to use the C99 semantics for \f(CW\*(C`inline\*(C'\fR when in C99 or gnu99 mode (i.e., it -specifies the default behavior). This option was first supported in -\&\s-1GCC\s0 4.3. This option is not supported in \fB\-std=c90\fR or +specifies the default behavior). +This option is not supported in \fB\-std=c90\fR or \&\fB\-std=gnu90\fR mode. .Sp The preprocessor macros \f(CW\*(C`_\|_GNUC_GNU_INLINE_\|_\*(C'\fR and @@ -1855,7 +1875,7 @@ In \*(C+, this switch only affects the \f(CW\*(C`typeof\*(C'\fR keyword, since use the \fB\-fno\-gnu\-keywords\fR flag instead, which has the same effect. In C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this switch only affects the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, since -\&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO\s0 C99. +\&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO C99.\s0 .IP "\fB\-fno\-builtin\fR" 4 .IX Item "-fno-builtin" .PD 0 @@ -1883,7 +1903,7 @@ known not to modify global memory. With the \fB\-fno\-builtin\-\fR\fIfunction\fR option only the built-in function \fIfunction\fR is disabled. \fIfunction\fR must not begin with \fB_\|_builtin_\fR. If a -function is named that is not built-in in this version of \s-1GCC\s0, this +function is named that is not built-in in this version of \s-1GCC,\s0 this option is ignored. There is no corresponding \&\fB\-fbuiltin\-\fR\fIfunction\fR option; if you wish to enable built-in functions selectively when using \fB\-fno\-builtin\fR or @@ -1907,6 +1927,18 @@ implies \fB\-fno\-builtin\fR. A freestanding environment is one in which the standard library may not exist, and program startup may not necessarily be at \f(CW\*(C`main\*(C'\fR. The most obvious example is an \s-1OS\s0 kernel. This is equivalent to \fB\-fno\-hosted\fR. +.IP "\fB\-fopenacc\fR" 4 +.IX Item "-fopenacc" +Enable handling of OpenACC directives \f(CW\*(C`#pragma acc\*(C'\fR in C/\*(C+ and +\&\f(CW\*(C`!$acc\*(C'\fR in Fortran. When \fB\-fopenacc\fR is specified, the +compiler generates accelerated code according to the OpenACC Application +Programming Interface v2.0 <\fBhttp://www.openacc.org/\fR>. This option +implies \fB\-pthread\fR, and thus is only supported on targets that +have support for \fB\-pthread\fR. +.Sp +Note that this is an experimental feature, incomplete, and subject to +change in future versions of \s-1GCC. \s0 See +<\fBhttps://gcc.gnu.org/wiki/OpenACC\fR> for more information. .IP "\fB\-fopenmp\fR" 4 .IX Item "-fopenmp" Enable handling of OpenMP directives \f(CW\*(C`#pragma omp\*(C'\fR in C/\*(C+ and @@ -1937,7 +1969,7 @@ When the option \fB\-fgnu\-tm\fR is specified, the compiler generates code for the Linux variant of Intel's current Transactional Memory \s-1ABI\s0 specification document (Revision 1.1, May 6 2009). This is an experimental feature whose interface may change in future versions -of \s-1GCC\s0, as the official specification changes. Please note that not +of \s-1GCC,\s0 as the official specification changes. Please note that not all architectures are supported for this feature. .Sp For more information on \s-1GCC\s0's support for transactional memory, @@ -1961,7 +1993,7 @@ to previous types declarations. Some cases of unnamed fields in structures and unions are only accepted with this option. .Sp -Note that this option is off for all targets but i?86 and x86_64 +Note that this option is off for all targets but x86 targets using ms-abi. .IP "\fB\-fplan9\-extensions\fR" 4 .IX Item "-fplan9-extensions" @@ -1974,8 +2006,8 @@ fields declared using a typedef. This is only supported for C, not \*(C+. .IP "\fB\-trigraphs\fR" 4 .IX Item "-trigraphs" -Support \s-1ISO\s0 C trigraphs. The \fB\-ansi\fR option (and \fB\-std\fR -options for strict \s-1ISO\s0 C conformance) implies \fB\-trigraphs\fR. +Support \s-1ISO C\s0 trigraphs. The \fB\-ansi\fR option (and \fB\-std\fR +options for strict \s-1ISO C\s0 conformance) implies \fB\-trigraphs\fR. .IP "\fB\-traditional\fR" 4 .IX Item "-traditional" .PD 0 @@ -1984,8 +2016,8 @@ options for strict \s-1ISO\s0 C conformance) implies \fB\-trigraphs\fR. .PD Formerly, these options caused \s-1GCC\s0 to attempt to emulate a pre-standard C compiler. They are now only supported with the \fB\-E\fR switch. -The preprocessor continues to support a pre-standard mode. See the \s-1GNU\s0 -\&\s-1CPP\s0 manual for details. +The preprocessor continues to support a pre-standard mode. See the \s-1GNU +CPP\s0 manual for details. .IP "\fB\-fcond\-mismatch\fR" 4 .IX Item "-fcond-mismatch" Allow conditional expressions with mismatched types in the second and @@ -2036,7 +2068,7 @@ declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\* default, such a bit-field is signed, because this is consistent: the basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. .SS "Options Controlling \*(C+ Dialect" -.IX Subsection "Options Controlling Dialect" +.IX Subsection "Options Controlling Dialect" This section describes the command-line options that are only meaningful for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options regardless of what language your program is in. For example, you @@ -2048,12 +2080,12 @@ might compile a file \fIfirstClass.C\fR like this: .PP In this example, only \fB\-frepo\fR is an option meant only for \*(C+ programs; you can use the other options with any -language supported by \s-1GCC\s0. +language supported by \s-1GCC.\s0 .PP Here is a list of options that are \fIonly\fR for compiling \*(C+ programs: .IP "\fB\-fabi\-version=\fR\fIn\fR" 4 .IX Item "-fabi-version=n" -Use version \fIn\fR of the \*(C+ \s-1ABI\s0. The default is version 0. +Use version \fIn\fR of the \*(C+ \s-1ABI. \s0 The default is version 0. .Sp Version 0 refers to the version conforming most closely to the \*(C+ \s-1ABI\s0 specification. Therefore, the \s-1ABI\s0 obtained using version 0 @@ -2090,7 +2122,7 @@ behavior of function types with function-cv-qualifiers. See also \fB\-Wabi\fR. .IP "\fB\-fabi\-compat\-version=\fR\fIn\fR" 4 .IX Item "-fabi-compat-version=n" -Starting with \s-1GCC\s0 4.5, on targets that support strong aliases, G++ +On targets that support strong aliases, G++ works around mangling changes by creating an alias with the correct mangled name when defining a symbol with an incorrect mangled name. This switch specifies which \s-1ABI\s0 version to use for the alias. @@ -2146,11 +2178,10 @@ deprecated, and may be removed in a future version of G++. Inject friend functions into the enclosing namespace, so that they are visible outside the scope of the class in which they are declared. Friend functions were documented to work this way in the old Annotated -\&\*(C+ Reference Manual, and versions of G++ before 4.1 always worked -that way. However, in \s-1ISO\s0 \*(C+ a friend function that is not declared +\&\*(C+ Reference Manual. +However, in \s-1ISO \*(C+\s0 a friend function that is not declared in an enclosing scope can only be found using argument dependent -lookup. This option causes friends to be injected as they were in -earlier releases. +lookup. \s-1GCC\s0 defaults to the standard behavior. .Sp This option is for compatibility, and may be removed in a future release of G++. @@ -2231,12 +2262,12 @@ controlled by \f(CW\*(C`#pragma implementation\*(C'\fR. This causes linker errors if these functions are not inlined everywhere they are called. .IP "\fB\-fms\-extensions\fR" 4 .IX Item "-fms-extensions" -Disable Wpedantic warnings about constructs used in \s-1MFC\s0, such as implicit +Disable Wpedantic warnings about constructs used in \s-1MFC,\s0 such as implicit int and getting a pointer to member function via non-standard syntax. .IP "\fB\-fno\-nonansi\-builtins\fR" 4 .IX Item "-fno-nonansi-builtins" Disable built-in declarations of functions that are not mandated by -\&\s-1ANSI/ISO\s0 C. These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, +\&\s-1ANSI/ISO C. \s0 These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, \&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions. .IP "\fB\-fnothrow\-opt\fR" 4 .IX Item "-fnothrow-opt" @@ -2324,7 +2355,7 @@ warning or error to \fIn\fR. The default value is 10. .IX Item "-ftemplate-depth=n" Set the maximum instantiation depth for template classes to \fIn\fR. A limit on the template instantiation depth is needed to detect -endless recursions during template class instantiation. \s-1ANSI/ISO\s0 \*(C+ +endless recursions during template class instantiation. \s-1ANSI/ISO \*(C+\s0 conforming programs must not rely on a maximum depth greater than 17 (changed to 1024 in \*(C+11). The default value is 900, as the compiler can run out of stack space before hitting 1024 in some situations. @@ -2355,7 +2386,7 @@ are taken in different shared objects. The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with \&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not appear in the export table of a \s-1DSO\s0 and do not require a \s-1PLT\s0 indirection -when used within the \s-1DSO\s0. Enabling this option can have a dramatic effect +when used within the \s-1DSO. \s0 Enabling this option can have a dramatic effect on load and link times of a \s-1DSO\s0 as it massively reduces the size of the dynamic export table when the library makes heavy use of templates. .Sp @@ -2475,10 +2506,10 @@ is used when building the \*(C+ library.) In addition, these optimization, warning, and code generation options have meanings only for \*(C+ programs: .IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wabi (C, Objective-C, and Objective- only)" +.IX Item "-Wabi (C, Objective-C, and Objective- only)" When an explicit \fB\-fabi\-version=\fR\fIn\fR option is used, causes G++ to warn when it generates code that is probably not compatible with the -vendor-neutral \*(C+ \s-1ABI\s0. Since G++ now defaults to +vendor-neutral \*(C+ \s-1ABI. \s0 Since G++ now defaults to \&\fB\-fabi\-version=0\fR, \fB\-Wabi\fR has no effect unless either an older \s-1ABI\s0 version is selected (with \fB\-fabi\-version=\fR\fIn\fR) or an older compatibility version is selected (with @@ -2501,7 +2532,7 @@ level, e.g. \fB\-Wabi=2\fR to warn about changes relative to \&\fB\-fabi\-compat\-version=\fR\fIn\fR. .Sp The known incompatibilities in \fB\-fabi\-version=2\fR (which was the -default from \s-1GCC\s0 3.4 to 4.9) include: +default from \s-1GCC 3.4\s0 to 4.9) include: .RS 4 .IP "*" 4 A template with a non-type template parameter of reference type was @@ -2529,7 +2560,7 @@ These mangling issues were fixed in \fB\-fabi\-version=5\fR. Scoped enumerators passed as arguments to a variadic function are promoted like unscoped enumerators, causing \f(CW\*(C`va_arg\*(C'\fR to complain. On most targets this does not actually affect the parameter passing -\&\s-1ABI\s0, as there is no way to pass an argument smaller than \f(CW\*(C`int\*(C'\fR. +\&\s-1ABI,\s0 as there is no way to pass an argument smaller than \f(CW\*(C`int\*(C'\fR. .Sp Also, the \s-1ABI\s0 changed the mangling of template argument packs, \&\f(CW\*(C`const_cast\*(C'\fR, \f(CW\*(C`static_cast\*(C'\fR, prefix increment/decrement, and @@ -2567,6 +2598,11 @@ passed in memory as specified in psABI. For example: .RE .RS 4 .RE +.IP "\fB\-Wabi\-tag\fR (\*(C+ and Objective\-\*(C+ only)" 4 +.IX Item "-Wabi-tag ( and Objective- only)" +Warn when a type with an \s-1ABI\s0 tag is used in a context that does not +have that \s-1ABI\s0 tag. See \fB\*(C+ Attributes\fR for more information +about \s-1ABI\s0 tags. .IP "\fB\-Wctor\-dtor\-privacy\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wctor-dtor-privacy ( and Objective- only)" Warn when a class seems unusable because all the constructors or @@ -2657,7 +2693,7 @@ This is on by default for all pre\-\*(C+11 dialects and all \s-1GNU\s0 dialects: \&\fB\-std=c++98\fR, \fB\-std=gnu++98\fR, \fB\-std=gnu++11\fR, \&\fB\-std=gnu++14\fR. This option is off by default -for \s-1ISO\s0 \*(C+11 onwards (\fB\-std=c++11\fR, ...). +for \s-1ISO \*(C+11\s0 onwards (\fB\-std=c++11\fR, ...). .PP The following \fB\-W...\fR options are not affected by \fB\-Wall\fR. .IP "\fB\-Weffc++\fR (\*(C+ and Objective\-\*(C+ only)" 4 @@ -2769,7 +2805,7 @@ For example, you might compile a file \fIsome_class.m\fR like this: .PP In this example, \fB\-fgnu\-runtime\fR is an option meant only for Objective-C and Objective\-\*(C+ programs; you can use the other options with -any language supported by \s-1GCC\s0. +any language supported by \s-1GCC.\s0 .PP Note that since Objective-C is an extension of the C language, Objective-C compilations may also use options specific to the C front-end (e.g., @@ -2794,7 +2830,7 @@ runtime. This is the default for most types of systems. .IP "\fB\-fnext\-runtime\fR" 4 .IX Item "-fnext-runtime" Generate output compatible with the NeXT runtime. This is the default -for NeXT-based systems, including Darwin and Mac \s-1OS\s0 X. The macro +for NeXT-based systems, including Darwin and Mac \s-1OS X. \s0 The macro \&\f(CW\*(C`_\|_NEXT_RUNTIME_\|_\*(C'\fR is predefined if (and only if) this option is used. .IP "\fB\-fno\-nil\-receivers\fR" 4 @@ -2811,7 +2847,7 @@ This option is currently supported only for the NeXT runtime. In that case, Version 0 is the traditional (32\-bit) \s-1ABI\s0 without support for properties and other Objective-C 2.0 additions. Version 1 is the traditional (32\-bit) \s-1ABI\s0 with support for properties and other -Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI\s0. If +Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI. \s0 If nothing is specified, the default is Version 0 on 32\-bit target machines, and Version 2 on 64\-bit target machines. .IP "\fB\-fobjc\-call\-cxx\-cdtors\fR" 4 @@ -2835,7 +2871,7 @@ by the runtime immediately after a new object instance is allocated; the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods are invoked immediately before the runtime deallocates an object instance. .Sp -As of this writing, only the NeXT runtime on Mac \s-1OS\s0 X 10.4 and later has +As of this writing, only the NeXT runtime on Mac \s-1OS X 10.4\s0 and later has support for invoking the \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and \&\f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods. .IP "\fB\-fobjc\-direct\-dispatch\fR" 4 @@ -2850,7 +2886,7 @@ is required to use the Objective-C keywords \f(CW@try\fR, \&\f(CW@throw\fR, \f(CW@catch\fR, \f(CW@finally\fR and \&\f(CW@synchronized\fR. This option is available with both the \s-1GNU\s0 runtime and the NeXT runtime (but not available in conjunction with -the NeXT runtime on Mac \s-1OS\s0 X 10.2 and earlier). +the NeXT runtime on Mac \s-1OS X 10.2\s0 and earlier). .IP "\fB\-fobjc\-gc\fR" 4 .IX Item "-fobjc-gc" Enable garbage collection (\s-1GC\s0) in Objective-C and Objective\-\*(C+ @@ -2859,23 +2895,23 @@ programs. This option is only available with the NeXT runtime; the does not require special compiler flags. .IP "\fB\-fobjc\-nilcheck\fR" 4 .IX Item "-fobjc-nilcheck" -For the NeXT runtime with version 2 of the \s-1ABI\s0, check for a nil +For the NeXT runtime with version 2 of the \s-1ABI,\s0 check for a nil receiver in method invocations before doing the actual method call. This is the default and can be disabled using \&\fB\-fno\-objc\-nilcheck\fR. Class methods and super calls are never checked for nil in this way no matter what this flag is set to. Currently this flag does nothing when the \s-1GNU\s0 runtime, or an older -version of the NeXT runtime \s-1ABI\s0, is used. +version of the NeXT runtime \s-1ABI,\s0 is used. .IP "\fB\-fobjc\-std=objc1\fR" 4 .IX Item "-fobjc-std=objc1" Conform to the language syntax of Objective-C 1.0, the language -recognized by \s-1GCC\s0 4.0. This only affects the Objective-C additions to +recognized by \s-1GCC 4.0. \s0 This only affects the Objective-C additions to the C/\*(C+ language; it does not affect conformance to C/\*(C+ standards, which is controlled by the separate C/\*(C+ dialect option flags. When this option is used with the Objective-C or Objective\-\*(C+ compiler, -any Objective-C syntax that is not recognized by \s-1GCC\s0 4.0 is rejected. +any Objective-C syntax that is not recognized by \s-1GCC 4.0\s0 is rejected. This is useful if you need to make sure that your Objective-C code can -be compiled with older versions of \s-1GCC\s0. +be compiled with older versions of \s-1GCC.\s0 .IP "\fB\-freplace\-objc\-classes\fR" 4 .IX Item "-freplace-objc-classes" Emit a special marker instructing \fB\f(BIld\fB\|(1)\fR not to statically link in @@ -2884,7 +2920,7 @@ run time instead. This is used in conjunction with the Fix-and-Continue debugging mode, where the object file in question may be recompiled and dynamically reloaded in the course of program execution, without the need to restart the program itself. Currently, Fix-and-Continue functionality -is only available in conjunction with the NeXT runtime on Mac \s-1OS\s0 X 10.3 +is only available in conjunction with the NeXT runtime on Mac \s-1OS X 10.3\s0 and later. .IP "\fB\-fzero\-link\fR" 4 .IX Item "-fzero-link" @@ -3082,7 +3118,7 @@ option is known to the diagnostic machinery). Specifying the By default, each diagnostic emitted includes the original source line and a caret '^' indicating the column. This option suppresses this information. The source line is truncated to \fIn\fR characters, if -the \fB\-fmessage\-length=n\fR is given. When the output is done +the \fB\-fmessage\-length=n\fR option is given. When the output is done to the terminal, the width is limited to the width given by the \&\fB\s-1COLUMNS\s0\fR environment variable or, if not set, to the terminal width. .SS "Options to Request or Suppress Warnings" @@ -3092,7 +3128,7 @@ are not inherently erroneous but that are risky or suggest there may have been an error. .PP The following language-independent options do not enable specific -warnings but control the kinds of diagnostics produced by \s-1GCC\s0. +warnings but control the kinds of diagnostics produced by \s-1GCC.\s0 .IP "\fB\-fsyntax\-only\fR" 4 .IX Item "-fsyntax-only" Check the code for syntax errors, but don't do anything beyond that. @@ -3167,14 +3203,14 @@ warns that an unrecognized option is present. .IP "\fB\-pedantic\fR" 4 .IX Item "-pedantic" .PD -Issue all the warnings demanded by strict \s-1ISO\s0 C and \s-1ISO\s0 \*(C+; +Issue all the warnings demanded by strict \s-1ISO C\s0 and \s-1ISO \*(C+\s0; reject all programs that use forbidden extensions, and some other -programs that do not follow \s-1ISO\s0 C and \s-1ISO\s0 \*(C+. For \s-1ISO\s0 C, follows the -version of the \s-1ISO\s0 C standard specified by any \fB\-std\fR option used. +programs that do not follow \s-1ISO C\s0 and \s-1ISO \*(C+. \s0 For \s-1ISO C,\s0 follows the +version of the \s-1ISO C\s0 standard specified by any \fB\-std\fR option used. .Sp -Valid \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ programs should compile properly with or without +Valid \s-1ISO C\s0 and \s-1ISO \*(C+\s0 programs should compile properly with or without this option (though a rare few require \fB\-ansi\fR or a -\&\fB\-std\fR option specifying the required version of \s-1ISO\s0 C). However, +\&\fB\-std\fR option specifying the required version of \s-1ISO C\s0). However, without this option, certain \s-1GNU\s0 extensions and traditional C and \*(C+ features are supported as well. With this option, they are rejected. .Sp @@ -3184,24 +3220,24 @@ warnings are also disabled in the expression that follows \&\f(CW\*(C`_\|_extension_\|_\*(C'\fR. However, only system header files should use these escape routes; application programs should avoid them. .Sp -Some users try to use \fB\-Wpedantic\fR to check programs for strict \s-1ISO\s0 -C conformance. They soon find that it does not do quite what they want: +Some users try to use \fB\-Wpedantic\fR to check programs for strict \s-1ISO +C\s0 conformance. They soon find that it does not do quite what they want: it finds some non-ISO practices, but not all\-\-\-only those for which -\&\s-1ISO\s0 C \fIrequires\fR a diagnostic, and some others for which +\&\s-1ISO C \s0\fIrequires\fR a diagnostic, and some others for which diagnostics have been added. .Sp -A feature to report any failure to conform to \s-1ISO\s0 C might be useful in +A feature to report any failure to conform to \s-1ISO C\s0 might be useful in some instances, but would require considerable additional work and would be quite different from \fB\-Wpedantic\fR. We don't have plans to support such a feature in the near future. .Sp Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0 extended dialect of C, such as \fBgnu90\fR or \fBgnu99\fR, there is a -corresponding \fIbase standard\fR, the version of \s-1ISO\s0 C on which the \s-1GNU\s0 +corresponding \fIbase standard\fR, the version of \s-1ISO C\s0 on which the \s-1GNU\s0 extended dialect is based. Warnings from \fB\-Wpedantic\fR are given where they are required by the base standard. (It does not make sense -for such warnings to be given only for features not in the specified \s-1GNU\s0 -C dialect, since by definition the \s-1GNU\s0 dialects of C include all +for such warnings to be given only for features not in the specified \s-1GNU +C\s0 dialect, since by definition the \s-1GNU\s0 dialects of C include all features the compiler supports with the given option, and there would be nothing to warn about.) .IP "\fB\-pedantic\-errors\fR" 4 @@ -3223,7 +3259,7 @@ Options\fR and \fBObjective-C and Objective\-\*(C+ Dialect Options\fR. \&\fB\-Wall\fR turns on the following warning flags: .Sp \&\fB\-Waddress -\&\-Warray\-bounds\fR (only with\fB \fR\fB\-O2\fR) +\&\-Warray\-bounds=1\fR (only with\fB \fR\fB\-O2\fR) \&\fB\-Wc++11\-compat \-Wc++14\-compat \&\-Wchar\-subscripts \&\-Wenum\-compare\fR (in C/ObjC; this is on by default in \*(C+) @@ -3373,7 +3409,7 @@ functions without the attribute specified are disabled by \&\fB\-ffreestanding\fR or \fB\-fno\-builtin\fR. .Sp The formats are checked against the format features supported by \s-1GNU\s0 -libc version 2.2. These include all \s-1ISO\s0 C90 and C99 features, as well +libc version 2.2. These include all \s-1ISO C90\s0 and C99 features, as well as features from the Single Unix Specification and some \s-1BSD\s0 and \s-1GNU\s0 extensions. Other library implementations may not support all these features; \s-1GCC\s0 does not support warning about features that go beyond a @@ -3421,7 +3457,7 @@ The C standard specifies that zero-length formats are allowed. .IX Item "-Wformat=2" Enable \fB\-Wformat\fR plus additional format checks. Currently equivalent to \fB\-Wformat \-Wformat\-nonliteral \-Wformat\-security -\&\-Wformat\-signedness \-Wformat\-y2k\fR. +\&\-Wformat\-y2k\fR. .IP "\fB\-Wformat\-nonliteral\fR" 4 .IX Item "-Wformat-nonliteral" If \fB\-Wformat\fR is specified, also warn if the format string is not a @@ -3489,12 +3525,12 @@ enabled by default and it is made into an error by Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 -.IX Item "-Wignored-qualifiers (C and only)" +.IX Item "-Wignored-qualifiers (C and only)" Warn if the return type of a function has a type qualifier -such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, +such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO C\s0 such a type qualifier has no effect, since the value returned by a function is not an lvalue. For \*(C+, the warning is only emitted for scalar types or \f(CW\*(C`void\*(C'\fR. -\&\s-1ISO\s0 C prohibits qualified \f(CW\*(C`void\*(C'\fR return types on function +\&\s-1ISO C\s0 prohibits qualified \f(CW\*(C`void\*(C'\fR return types on function definitions, so such return types always receive a warning even without this option. .Sp @@ -3681,9 +3717,9 @@ expression to a type other than \f(CW\*(C`bool\*(C'\fR. For example: .Sp This warning is enabled by default for C and \*(C+ programs. .IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 -.IX Item "-Wsync-nand (C and only)" +.IX Item "-Wsync-nand (C and only)" Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR -built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. +built-in functions are used. These functions changed semantics in \s-1GCC 4.4.\s0 .IP "\fB\-Wtrigraphs\fR" 4 .IX Item "-Wtrigraphs" Warn if any trigraphs are encountered that might change the meaning of @@ -3720,7 +3756,7 @@ This warning is enabled by \fB\-Wall\fR. .Sp To suppress this warning use the \f(CW\*(C`unused\*(C'\fR attribute. .IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" +.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" Warn when a typedef locally defined in a function is not used. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wunused\-parameter\fR" 4 @@ -3827,7 +3863,7 @@ This warning is enabled by \fB\-Wall\fR or \fB\-Wextra\fR. .IP "\fB\-Wunknown\-pragmas\fR" 4 .IX Item "-Wunknown-pragmas" Warn when a \f(CW\*(C`#pragma\*(C'\fR directive is encountered that is not understood by -\&\s-1GCC\s0. If this command-line option is used, warnings are even issued +\&\s-1GCC. \s0 If this command-line option is used, warnings are even issued for unknown pragmas in system header files. This is not the case if the warnings are only enabled by the \fB\-Wall\fR command-line option. .IP "\fB\-Wno\-pragmas\fR" 4 @@ -3950,7 +3986,7 @@ Warn about functions that might be candidates for attributes functions visible in other compilation units or (in the case of \f(CW\*(C`pure\*(C'\fR and \&\f(CW\*(C`const\*(C'\fR) if it cannot prove that the function returns normally. A function returns normally if it doesn't contain an infinite loop or return abnormally -by throwing, calling \f(CW\*(C`abort()\*(C'\fR or trapping. This analysis requires option +by throwing, calling \f(CW\*(C`abort\*(C'\fR or trapping. This analysis requires option \&\fB\-fipa\-pure\-const\fR, which is enabled by default at \fB\-O\fR and higher. Higher optimization levels improve the accuracy of the analysis. .IP "\fB\-Wsuggest\-attribute=format\fR" 4 @@ -4005,9 +4041,27 @@ Warn about overriding virtual functions that are not marked with the override keyword. .IP "\fB\-Warray\-bounds\fR" 4 .IX Item "-Warray-bounds" +.PD 0 +.IP "\fB\-Warray\-bounds=\fR\fIn\fR" 4 +.IX Item "-Warray-bounds=n" +.PD This option is only active when \fB\-ftree\-vrp\fR is active (default for \fB\-O2\fR and above). It warns about subscripts to arrays that are always out of bounds. This warning is enabled by \fB\-Wall\fR. +.RS 4 +.IP "\fB\-Warray\-bounds=1\fR" 4 +.IX Item "-Warray-bounds=1" +This is the warning level of \fB\-Warray\-bounds\fR and is enabled +by \fB\-Wall\fR; higher levels are not, and must be explicitly requested. +.IP "\fB\-Warray\-bounds=2\fR" 4 +.IX Item "-Warray-bounds=2" +This warning level also warns about out of bounds access for +arrays at the end of a struct and for arrays accessed through +pointers. This warning level may give a larger number of +false positives and is deactivated by default. +.RE +.RS 4 +.RE .IP "\fB\-Wbool\-compare\fR" 4 .IX Item "-Wbool-compare" Warn about boolean expression compared with an integer value different from @@ -4087,13 +4141,13 @@ probably mistaken. .IP "\fB\-Wtraditional\fR (C and Objective-C only)" 4 .IX Item "-Wtraditional (C and Objective-C only)" Warn about certain constructs that behave differently in traditional and -\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C +\&\s-1ISO C. \s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C equivalent, and/or problematic constructs that should be avoided. .RS 4 .IP "*" 4 Macro parameters that appear within string literals in the macro body. In traditional C macro replacement takes place within string literals, -but in \s-1ISO\s0 C it does not. +but in \s-1ISO C\s0 it does not. .IP "*" 4 In traditional C, some preprocessor directives did not exist. Traditional preprocessors only considered a line to be a directive @@ -4148,9 +4202,9 @@ versa. The absence of these prototypes when compiling with traditional C causes serious problems. This is a subset of the possible conversion warnings; for the full set use \fB\-Wtraditional\-conversion\fR. .IP "*" 4 -Use of \s-1ISO\s0 C style function definitions. This warning intentionally is +Use of \s-1ISO C\s0 style function definitions. This warning intentionally is \&\fInot\fR issued for prototype declarations or variadic functions -because these \s-1ISO\s0 C features appear in your code when using +because these \s-1ISO C\s0 features appear in your code when using libiberty's traditional C compatibility macros, \f(CW\*(C`PARAMS\*(C'\fR and \&\f(CW\*(C`VPARAMS\*(C'\fR. This warning is also bypassed for nested functions because that feature is already a \s-1GCC\s0 extension and thus not relevant to @@ -4168,9 +4222,8 @@ except when the same as the default promotion. .IP "\fB\-Wdeclaration\-after\-statement\fR (C and Objective-C only)" 4 .IX Item "-Wdeclaration-after-statement (C and Objective-C only)" Warn when a declaration is found after a statement in a block. This -construct, known from \*(C+, was introduced with \s-1ISO\s0 C99 and is by default -allowed in \s-1GCC\s0. It is not supported by \s-1ISO\s0 C90 and was not supported by -\&\s-1GCC\s0 versions before \s-1GCC\s0 3.0. +construct, known from \*(C+, was introduced with \s-1ISO C99\s0 and is by default +allowed in \s-1GCC. \s0 It is not supported by \s-1ISO C90. \s0 .IP "\fB\-Wundef\fR" 4 .IX Item "-Wundef" Warn if an undefined identifier is evaluated in an \f(CW\*(C`#if\*(C'\fR directive. @@ -4252,7 +4305,7 @@ which depend on the \s-1MS\s0 runtime. .IP "\fB\-Wpointer\-arith\fR" 4 .IX Item "-Wpointer-arith" Warn about anything that depends on the \*(L"size of\*(R" a function type or -of \f(CW\*(C`void\*(C'\fR. \s-1GNU\s0 C assigns these types a size of 1, for +of \f(CW\*(C`void\*(C'\fR. \s-1GNU C\s0 assigns these types a size of 1, for convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers to functions. In \*(C+, warn also when an arithmetic operation involves \&\f(CW\*(C`NULL\*(C'\fR. This warning is also enabled by \fB\-Wpedantic\fR. @@ -4265,18 +4318,19 @@ example, warn if an unsigned variable is compared against zero with \&\fB\-Wextra\fR. .IP "\fB\-Wbad\-function\-cast\fR (C and Objective-C only)" 4 .IX Item "-Wbad-function-cast (C and Objective-C only)" -Warn whenever a function call is cast to a non-matching type. -For example, warn if \f(CW\*(C`int malloc()\*(C'\fR is cast to \f(CW\*(C`anything *\*(C'\fR. +Warn when a function call is cast to a non-matching type. +For example, warn if a call to a function returning an integer type +is cast to a pointer type. .IP "\fB\-Wc90\-c99\-compat\fR (C and Objective-C only)" 4 .IX Item "-Wc90-c99-compat (C and Objective-C only)" -Warn about features not present in \s-1ISO\s0 C90, but present in \s-1ISO\s0 C99. +Warn about features not present in \s-1ISO C90,\s0 but present in \s-1ISO C99.\s0 For instance, warn about use of variable length arrays, \f(CW\*(C`long long\*(C'\fR type, \f(CW\*(C`bool\*(C'\fR type, compound literals, designated initializers, and so on. This option is independent of the standards mode. Warnings are disabled in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. .IP "\fB\-Wc99\-c11\-compat\fR (C and Objective-C only)" 4 .IX Item "-Wc99-c11-compat (C and Objective-C only)" -Warn about features not present in \s-1ISO\s0 C99, but present in \s-1ISO\s0 C11. +Warn about features not present in \s-1ISO C99,\s0 but present in \s-1ISO C11.\s0 For instance, warn about use of anonymous structures and unions, \&\f(CW\*(C`_Atomic\*(C'\fR type qualifier, \f(CW\*(C`_Thread_local\*(C'\fR storage-class specifier, \&\f(CW\*(C`_Alignas\*(C'\fR specifier, \f(CW\*(C`Alignof\*(C'\fR operator, \f(CW\*(C`_Generic\*(C'\fR keyword, @@ -4284,19 +4338,19 @@ and so on. This option is independent of the standards mode. Warnings are disabled in the expression that follows \f(CW\*(C`_\|_extension_\|_\*(C'\fR. .IP "\fB\-Wc++\-compat\fR (C and Objective-C only)" 4 .IX Item "-Wc++-compat (C and Objective-C only)" -Warn about \s-1ISO\s0 C constructs that are outside of the common subset of -\&\s-1ISO\s0 C and \s-1ISO\s0 \*(C+, e.g. request for implicit conversion from +Warn about \s-1ISO C\s0 constructs that are outside of the common subset of +\&\s-1ISO C\s0 and \s-1ISO \*(C+,\s0 e.g. request for implicit conversion from \&\f(CW\*(C`void *\*(C'\fR to a pointer to non\-\f(CW\*(C`void\*(C'\fR type. .IP "\fB\-Wc++11\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wc++11-compat ( and Objective- only)" -Warn about \*(C+ constructs whose meaning differs between \s-1ISO\s0 \*(C+ 1998 -and \s-1ISO\s0 \*(C+ 2011, e.g., identifiers in \s-1ISO\s0 \*(C+ 1998 that are keywords -in \s-1ISO\s0 \*(C+ 2011. This warning turns on \fB\-Wnarrowing\fR and is +Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 1998\s0 +and \s-1ISO \*(C+ 2011,\s0 e.g., identifiers in \s-1ISO \*(C+ 1998\s0 that are keywords +in \s-1ISO \*(C+ 2011. \s0 This warning turns on \fB\-Wnarrowing\fR and is enabled by \fB\-Wall\fR. .IP "\fB\-Wc++14\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wc++14-compat ( and Objective- only)" -Warn about \*(C+ constructs whose meaning differs between \s-1ISO\s0 \*(C+ 2011 -and \s-1ISO\s0 \*(C+ 2014. This warning is enabled by \fB\-Wall\fR. +Warn about \*(C+ constructs whose meaning differs between \s-1ISO \*(C+ 2011\s0 +and \s-1ISO \*(C+ 2014. \s0 This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wcast\-qual\fR" 4 .IX Item "-Wcast-qual" Warn whenever a pointer is cast so as to remove a type qualifier from @@ -4456,10 +4510,10 @@ Warn for suspicious calls to the \f(CW\*(C`memset\*(C'\fR built-in function, if second argument is not zero and the third argument is zero. This warns e.g.@ about \f(CW\*(C`memset (buf, sizeof buf, 0)\*(C'\fR where most probably \&\f(CW\*(C`memset (buf, 0, sizeof buf)\*(C'\fR was meant instead. The diagnostics -is only emitted if the third argument is literal zero, if it is some expression -that is folded to zero, or e.g. a cast of zero to some type etc., it -is far less likely that user has mistakenly exchanged the arguments and -no warning is emitted. This warning is enabled by \fB\-Wall\fR. +is only emitted if the third argument is literal zero. If it is some +expression that is folded to zero, a cast of zero to some type, etc., +it is far less likely that the user has mistakenly exchanged the arguments +and no warning is emitted. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Waddress\fR" 4 .IX Item "-Waddress" Warn about suspicious uses of memory addresses. These include using @@ -4599,26 +4653,26 @@ Usually they indicate a typo in the user's code, as they have implementation-defined values, and should not be used in portable code. .IP "\fB\-Wnormalized\fR[\fB=\fR<\fBnone\fR|\fBid\fR|\fBnfc\fR|\fBnfkc\fR>]" 4 .IX Item "-Wnormalized[=]" -In \s-1ISO\s0 C and \s-1ISO\s0 \*(C+, two identifiers are different if they are +In \s-1ISO C\s0 and \s-1ISO \*(C+,\s0 two identifiers are different if they are different sequences of characters. However, sometimes when characters outside the basic \s-1ASCII\s0 character set are used, you can have two different character sequences that look the same. To avoid confusion, -the \s-1ISO\s0 10646 standard sets out some \fInormalization rules\fR which +the \s-1ISO 10646\s0 standard sets out some \fInormalization rules\fR which when applied ensure that two sequences that look the same are turned into the same sequence. \s-1GCC\s0 can warn you if you are using identifiers that have not been normalized; this option controls that warning. .Sp -There are four levels of warning supported by \s-1GCC\s0. The default is +There are four levels of warning supported by \s-1GCC. \s0 The default is \&\fB\-Wnormalized=nfc\fR, which warns about any identifier that is -not in the \s-1ISO\s0 10646 \*(L"C\*(R" normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the +not in the \s-1ISO 10646 \*(L"C\*(R"\s0 normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the recommended form for most uses. It is equivalent to \&\fB\-Wnormalized\fR. .Sp Unfortunately, there are some characters allowed in identifiers by -\&\s-1ISO\s0 C and \s-1ISO\s0 \*(C+ that, when turned into \s-1NFC\s0, are not allowed in +\&\s-1ISO C\s0 and \s-1ISO \*(C+\s0 that, when turned into \s-1NFC,\s0 are not allowed in identifiers. That is, there's no way to use these symbols in portable -\&\s-1ISO\s0 C or \*(C+ and have all your identifiers in \s-1NFC\s0. -\&\fB\-Wnormalized=id\fR suppresses the warning for these characters. +\&\s-1ISO C\s0 or \*(C+ and have all your identifiers in \s-1NFC. +\&\s0\fB\-Wnormalized=id\fR suppresses the warning for these characters. It is hoped that future versions of the standards involved will correct this, which is why this option is not the default. .Sp @@ -4628,11 +4682,11 @@ only do this if you are using some other normalization scheme (like \&\*(L"D\*(R"), because otherwise you can easily create bugs that are literally impossible to see. .Sp -Some characters in \s-1ISO\s0 10646 have distinct meanings but look identical +Some characters in \s-1ISO 10646\s0 have distinct meanings but look identical in some fonts or display methodologies, especially once formatting has -been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT\s0 \s-1LATIN\s0 \s-1SMALL\s0 -\&\s-1LETTER\s0 N\*(R", displays just like a regular \f(CW\*(C`n\*(C'\fR that has been -placed in a superscript. \s-1ISO\s0 10646 defines the \fI\s-1NFKC\s0\fR +been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT LATIN SMALL +LETTER N\*(R",\s0 displays just like a regular \f(CW\*(C`n\*(C'\fR that has been +placed in a superscript. \s-1ISO 10646\s0 defines the \fI\s-1NFKC\s0\fR normalization scheme to convert all these into a standard form as well, and \s-1GCC\s0 warns if your code is not in \s-1NFKC\s0 if you use \&\fB\-Wnormalized=nfkc\fR. This warning is comparable to warning @@ -4658,8 +4712,8 @@ Requires \fB\-flto\-odr\-type\-merging\fR to be enabled. Enabled by default. .IP "\fB\-Wopenmp\-simd\fR" 4 .IX Item "-Wopenmp-simd" Warn if the vectorizer cost model overrides the OpenMP or the Cilk Plus -simd directive set by user. The \fB\-fsimd\-cost\-model=unlimited\fR can -be used to relax the cost model. +simd directive set by user. The \fB\-fsimd\-cost\-model=unlimited\fR +option can be used to relax the cost model. .IP "\fB\-Woverride\-init\fR (C and Objective-C only)" 4 .IX Item "-Woverride-init (C and Objective-C only)" Warn if an initialized field without side effects is overridden when @@ -4690,9 +4744,9 @@ have the packed attribute: .IP "\fB\-Wpacked\-bitfield\-compat\fR" 4 .IX Item "-Wpacked-bitfield-compat" The 4.1, 4.2 and 4.3 series of \s-1GCC\s0 ignore the \f(CW\*(C`packed\*(C'\fR attribute -on bit-fields of type \f(CW\*(C`char\*(C'\fR. This has been fixed in \s-1GCC\s0 4.4 but +on bit-fields of type \f(CW\*(C`char\*(C'\fR. This has been fixed in \s-1GCC 4.4\s0 but the change can lead to differences in the structure layout. \s-1GCC\s0 -informs you when the offset of such a field has changed in \s-1GCC\s0 4.4. +informs you when the offset of such a field has changed in \s-1GCC 4.4.\s0 For example there is no longer a 4\-bit padding between field \f(CW\*(C`a\*(C'\fR and \f(CW\*(C`b\*(C'\fR in this structure: .Sp @@ -4739,7 +4793,7 @@ warnings produced by \fB\-Winline\fR to appear or disappear. .IP "\fB\-Wno\-invalid\-offsetof\fR (\*(C+ and Objective\-\*(C+ only)" 4 .IX Item "-Wno-invalid-offsetof ( and Objective- only)" Suppress warnings from applying the \f(CW\*(C`offsetof\*(C'\fR macro to a non-POD -type. According to the 2014 \s-1ISO\s0 \*(C+ standard, applying \f(CW\*(C`offsetof\*(C'\fR +type. According to the 2014 \s-1ISO \*(C+\s0 standard, applying \f(CW\*(C`offsetof\*(C'\fR to a non-standard-layout type is undefined. In existing \*(C+ implementations, however, \f(CW\*(C`offsetof\*(C'\fR typically gives meaningful results. This flag is for users who are aware that they are @@ -4764,12 +4818,12 @@ the search path but can't be used. .IP "\fB\-Wlong\-long\fR" 4 .IX Item "-Wlong-long" Warn if \f(CW\*(C`long long\*(C'\fR type is used. This is enabled by either -\&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR in \s-1ISO\s0 C90 and \*(C+98 +\&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR in \s-1ISO C90\s0 and \*(C+98 modes. To inhibit the warning messages, use \fB\-Wno\-long\-long\fR. .IP "\fB\-Wvariadic\-macros\fR" 4 .IX Item "-Wvariadic-macros" -Warn if variadic macros are used in \s-1ISO\s0 C90 mode, or if the \s-1GNU\s0 -alternate syntax is used in \s-1ISO\s0 C99 mode. This is enabled by either +Warn if variadic macros are used in \s-1ISO C90\s0 mode, or if the \s-1GNU\s0 +alternate syntax is used in \s-1ISO C99\s0 mode. This is enabled by either \&\fB\-Wpedantic\fR or \fB\-Wtraditional\fR. To inhibit the warning messages, use \fB\-Wno\-variadic\-macros\fR. .IP "\fB\-Wvarargs\fR" 4 @@ -4833,7 +4887,7 @@ standard's minimum limit, but very portable programs should avoid using longer strings. .Sp The limit applies \fIafter\fR string constant concatenation, and does -not count the trailing \s-1NUL\s0. In C90, the limit was 509 characters; in +not count the trailing \s-1NUL. \s0 In C90, the limit was 509 characters; in C99, it was raised to 4095. \*(C+98 does not specify a normative minimum maximum, so we do not diagnose overlength strings in \*(C+. .Sp @@ -4858,7 +4912,7 @@ either your program or \s-1GCC:\s0 .IP "\fB\-g\fR" 4 .IX Item "-g" Produce debugging information in the operating system's native format -(stabs, \s-1COFF\s0, \s-1XCOFF\s0, or \s-1DWARF\s0 2). \s-1GDB\s0 can work with this debugging +(stabs, \s-1COFF, XCOFF,\s0 or \s-1DWARF 2\s0). \s-1GDB\s0 can work with this debugging information. .Sp On most systems that use stabs format, \fB\-g\fR enables use of extra @@ -4891,8 +4945,8 @@ be useful, this option requires a debugger capable of reading .dwo files. .IP "\fB\-ggdb\fR" 4 .IX Item "-ggdb" -Produce debugging information for use by \s-1GDB\s0. This means to use the -most expressive format available (\s-1DWARF\s0 2, stabs, or the native format +Produce debugging information for use by \s-1GDB. \s0 This means to use the +most expressive format available (\s-1DWARF 2,\s0 stabs, or the native format if neither of those are supported), including \s-1GDB\s0 extensions if at all possible. .IP "\fB\-gpubnames\fR" 4 @@ -4907,8 +4961,8 @@ with a linker that can produce \s-1GDB\s0 index version 7. .IX Item "-gstabs" Produce debugging information in stabs format (if that is supported), without \s-1GDB\s0 extensions. This is the format used by \s-1DBX\s0 on most \s-1BSD\s0 -systems. On \s-1MIPS\s0, Alpha and System V Release 4 systems this option -produces stabs debugging output that is not understood by \s-1DBX\s0 or \s-1SDB\s0. +systems. On \s-1MIPS,\s0 Alpha and System V Release 4 systems this option +produces stabs debugging output that is not understood by \s-1DBX\s0 or \s-1SDB.\s0 On System V Release 4 systems this option requires the \s-1GNU\s0 assembler. .IP "\fB\-feliminate\-unused\-debug\-symbols\fR" 4 .IX Item "-feliminate-unused-debug-symbols" @@ -4945,7 +4999,7 @@ System V Release 4. .IP "\fB\-gxcoff\fR" 4 .IX Item "-gxcoff" Produce debugging information in \s-1XCOFF\s0 format (if that is supported). -This is the format used by the \s-1DBX\s0 debugger on \s-1IBM\s0 \s-1RS/6000\s0 systems. +This is the format used by the \s-1DBX\s0 debugger on \s-1IBM RS/6000\s0 systems. .IP "\fB\-gxcoff+\fR" 4 .IX Item "-gxcoff+" Produce debugging information in \s-1XCOFF\s0 format (if that is supported), @@ -4960,9 +5014,9 @@ The value of \fIversion\fR may be either 2, 3, 4 or 5; the default version for most targets is 4. \s-1DWARF\s0 Version 5 is only experimental. .Sp Note that with \s-1DWARF\s0 Version 2, some ports require and always -use some non-conflicting \s-1DWARF\s0 3 extensions in the unwind tables. +use some non-conflicting \s-1DWARF 3\s0 extensions in the unwind tables. .Sp -Version 4 may require \s-1GDB\s0 7.0 and \fB\-fvar\-tracking\-assignments\fR +Version 4 may require \s-1GDB 7.0\s0 and \fB\-fvar\-tracking\-assignments\fR for maximum benefit. .IP "\fB\-grecord\-gcc\-switches\fR" 4 .IX Item "-grecord-gcc-switches" @@ -5035,7 +5089,7 @@ debug information in version 1 of the \s-1DWARF\s0 format (which is very different from version 2), and it would have been too confusing. That debug format is long obsolete, but the option cannot be changed now. Instead use an additional \fB\-g\fR\fIlevel\fR option to change the -debug level for \s-1DWARF\s0. +debug level for \s-1DWARF.\s0 .IP "\fB\-gtoggle\fR" 4 .IX Item "-gtoggle" Turn off generation of debug info, if leaving out this option @@ -5087,7 +5141,7 @@ at runtime. Current suboptions are: .IX Item "-fsanitize=shift" This option enables checking that the result of a shift operation is not undefined. Note that what exactly is considered undefined differs -slightly between C and \*(C+, as well as between \s-1ISO\s0 C90 and C99, etc. +slightly between C and \*(C+, as well as between \s-1ISO C90\s0 and C99, etc. .IP "\fB\-fsanitize=integer\-divide\-by\-zero\fR" 4 .IX Item "-fsanitize=integer-divide-by-zero" Detect integer division by zero as well as \f(CW\*(C`INT_MIN / \-1\*(C'\fR division. @@ -5128,8 +5182,8 @@ overflow: .IP "\fB\-fsanitize=bounds\fR" 4 .IX Item "-fsanitize=bounds" This option enables instrumentation of array bounds. Various out of bounds -accesses are detected. Flexible array members and initializers of variables -with static storage are not instrumented. +accesses are detected. Flexible array members, flexible array member-like +arrays, and initializers of variables with static storage are not instrumented. .IP "\fB\-fsanitize=alignment\fR" 4 .IX Item "-fsanitize=alignment" This option enables checking of alignment of pointers when they are @@ -5172,6 +5226,11 @@ than 0/1 is loaded, a run-time error is issued. This option enables instrumentation of loads from an enum type. If a value outside the range of values for the enum type is loaded, a run-time error is issued. +.IP "\fB\-fsanitize=vptr\fR" 4 +.IX Item "-fsanitize=vptr" +This option enables instrumentation of \*(C+ member function calls, member +accesses and some conversions between pointers to base and derived classes, +to verify the referenced object has the correct dynamic type. .RE .RS 4 .Sp @@ -5197,7 +5256,8 @@ for a sanitizer component causes it to attempt to continue running the program as if no error happened. This means multiple runtime errors can be reported in a single program run, and the exit code of the program may indicate success even when errors -have been reported. The \fB\-fno\-sanitize\-recover=\fR can be used to alter +have been reported. The \fB\-fno\-sanitize\-recover=\fR option +can be used to alter this behavior: only the first detected error is reported and program then exits with a non-zero exit code. .Sp @@ -5222,11 +5282,124 @@ Similarly \fB\-fno\-sanitize\-recover\fR is equivalent to .Ve .IP "\fB\-fsanitize\-undefined\-trap\-on\-error\fR" 4 .IX Item "-fsanitize-undefined-trap-on-error" -The \fB\-fsanitize\-undefined\-trap\-on\-error\fR instructs the compiler to -report undefined behavior using \f(CW\*(C`_\|_builtin_trap ()\*(C'\fR rather than +The \fB\-fsanitize\-undefined\-trap\-on\-error\fR option instructs the compiler to +report undefined behavior using \f(CW\*(C`_\|_builtin_trap\*(C'\fR rather than a \f(CW\*(C`libubsan\*(C'\fR library routine. The advantage of this is that the \&\f(CW\*(C`libubsan\*(C'\fR library is not needed and is not linked in, so this is usable even in freestanding environments. +.IP "\fB\-fcheck\-pointer\-bounds\fR" 4 +.IX Item "-fcheck-pointer-bounds" +Enable Pointer Bounds Checker instrumentation. Each memory reference +is instrumented with checks of the pointer used for memory access against +bounds associated with that pointer. +.Sp +Currently there +is only an implementation for Intel \s-1MPX\s0 available, thus x86 target +and \fB\-mmpx\fR are required to enable this feature. +MPX-based instrumentation requires +a runtime library to enable \s-1MPX\s0 in hardware and handle bounds +violation signals. By default when \fB\-fcheck\-pointer\-bounds\fR +and \fB\-mmpx\fR options are used to link a program, the \s-1GCC\s0 driver +links against the \fIlibmpx\fR runtime library and \fIlibmpxwrappers\fR +library. It also passes '\-z bndplt' to a linker in case it supports this +option (which is checked on libmpx configuration). Note that old versions +of linker may ignore option. Gold linker doesn't support '\-z bndplt' +option. With no '\-z bndplt' support in linker all calls to dynamic libraries +lose passed bounds reducing overall protection level. It's highly +recommended to use linker with '\-z bndplt' support. In case such linker +is not available it is adviced to always use \fB\-static\-libmpxwrappers\fR +for better protection level or use \fB\-static\fR to completely avoid +external calls to dynamic libraries. MPX-based instrumentation +may be used for debugging and also may be included in production code +to increase program security. Depending on usage, you may +have different requirements for the runtime library. The current version +of the \s-1MPX\s0 runtime library is more oriented for use as a debugging +tool. \s-1MPX\s0 runtime library usage implies \fB\-lpthread\fR. See +also \fB\-static\-libmpx\fR. The runtime library behavior can be +influenced using various \fBCHKP_RT_*\fR environment variables. See +<\fBhttps://gcc.gnu.org/wiki/Intel%20MPX%20support%20in%20the%20GCC%20compiler\fR> +for more details. +.Sp +Generated instrumentation may be controlled by various +\&\fB\-fchkp\-*\fR options and by the \f(CW\*(C`bnd_variable_size\*(C'\fR +structure field attribute and +\&\f(CW\*(C`bnd_legacy\*(C'\fR, and \f(CW\*(C`bnd_instrument\*(C'\fR function attributes. \s-1GCC\s0 also provides a number of built-in +functions for controlling the Pointer Bounds Checker. +.IP "\fB\-fchkp\-check\-incomplete\-type\fR" 4 +.IX Item "-fchkp-check-incomplete-type" +Generate pointer bounds checks for variables with incomplete type. +Enabled by default. +.IP "\fB\-fchkp\-narrow\-bounds\fR" 4 +.IX Item "-fchkp-narrow-bounds" +Controls bounds used by Pointer Bounds Checker for pointers to object +fields. If narrowing is enabled then field bounds are used. Otherwise +object bounds are used. See also \fB\-fchkp\-narrow\-to\-innermost\-array\fR +and \fB\-fchkp\-first\-field\-has\-own\-bounds\fR. Enabled by default. +.IP "\fB\-fchkp\-first\-field\-has\-own\-bounds\fR" 4 +.IX Item "-fchkp-first-field-has-own-bounds" +Forces Pointer Bounds Checker to use narrowed bounds for the address of the +first field in the structure. By default a pointer to the first field has +the same bounds as a pointer to the whole structure. +.IP "\fB\-fchkp\-narrow\-to\-innermost\-array\fR" 4 +.IX Item "-fchkp-narrow-to-innermost-array" +Forces Pointer Bounds Checker to use bounds of the innermost arrays in +case of nested static array access. By default this option is disabled and +bounds of the outermost array are used. +.IP "\fB\-fchkp\-optimize\fR" 4 +.IX Item "-fchkp-optimize" +Enables Pointer Bounds Checker optimizations. Enabled by default at +optimization levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR. +.IP "\fB\-fchkp\-use\-fast\-string\-functions\fR" 4 +.IX Item "-fchkp-use-fast-string-functions" +Enables use of \f(CW*_nobnd\fR versions of string functions (not copying bounds) +by Pointer Bounds Checker. Disabled by default. +.IP "\fB\-fchkp\-use\-nochk\-string\-functions\fR" 4 +.IX Item "-fchkp-use-nochk-string-functions" +Enables use of \f(CW*_nochk\fR versions of string functions (not checking bounds) +by Pointer Bounds Checker. Disabled by default. +.IP "\fB\-fchkp\-use\-static\-bounds\fR" 4 +.IX Item "-fchkp-use-static-bounds" +Allow Pointer Bounds Checker to generate static bounds holding +bounds of static variables. Enabled by default. +.IP "\fB\-fchkp\-use\-static\-const\-bounds\fR" 4 +.IX Item "-fchkp-use-static-const-bounds" +Use statically-initialized bounds for constant bounds instead of +generating them each time they are required. By default enabled when +\&\fB\-fchkp\-use\-static\-bounds\fR is enabled. +.IP "\fB\-fchkp\-treat\-zero\-dynamic\-size\-as\-infinite\fR" 4 +.IX Item "-fchkp-treat-zero-dynamic-size-as-infinite" +With this option, objects with incomplete type whose +dynamically-obtained size is zero are treated as having infinite size +instead by Pointer Bounds +Checker. This option may be helpful if a program is linked with a library +missing size information for some symbols. Disabled by default. +.IP "\fB\-fchkp\-check\-read\fR" 4 +.IX Item "-fchkp-check-read" +Instructs Pointer Bounds Checker to generate checks for all read +accesses to memory. Enabled by default. +.IP "\fB\-fchkp\-check\-write\fR" 4 +.IX Item "-fchkp-check-write" +Instructs Pointer Bounds Checker to generate checks for all write +accesses to memory. Enabled by default. +.IP "\fB\-fchkp\-store\-bounds\fR" 4 +.IX Item "-fchkp-store-bounds" +Instructs Pointer Bounds Checker to generate bounds stores for +pointer writes. Enabled by default. +.IP "\fB\-fchkp\-instrument\-calls\fR" 4 +.IX Item "-fchkp-instrument-calls" +Instructs Pointer Bounds Checker to pass pointer bounds to calls. +Enabled by default. +.IP "\fB\-fchkp\-instrument\-marked\-only\fR" 4 +.IX Item "-fchkp-instrument-marked-only" +Instructs Pointer Bounds Checker to instrument only functions +marked with the \f(CW\*(C`bnd_instrument\*(C'\fR attribute. Disabled by default. +.IP "\fB\-fchkp\-use\-wrappers\fR" 4 +.IX Item "-fchkp-use-wrappers" +Allows Pointer Bounds Checker to replace calls to built-in functions +with calls to wrapper functions. When \fB\-fchkp\-use\-wrappers\fR +is used to link a program, the \s-1GCC\s0 driver automatically links +against \fIlibmpxwrappers\fR. See also \fB\-static\-libmpxwrappers\fR. +Enabled by default. .IP "\fB\-fdump\-final\-insns\fR[\fB=\fR\fIfile\fR]" 4 .IX Item "-fdump-final-insns[=file]" Dump the final internal representation (\s-1RTL\s0) to \fIfile\fR. If the @@ -5274,9 +5447,9 @@ When this option is passed to the compiler driver, it causes the other than debugging the compiler proper. .IP "\fB\-feliminate\-dwarf2\-dups\fR" 4 .IX Item "-feliminate-dwarf2-dups" -Compress \s-1DWARF\s0 2 debugging information by eliminating duplicated +Compress \s-1DWARF 2\s0 debugging information by eliminating duplicated information about each symbol. This option only makes sense when -generating \s-1DWARF\s0 2 debugging information with \fB\-gdwarf\-2\fR. +generating \s-1DWARF 2\s0 debugging information with \fB\-gdwarf\-2\fR. .IP "\fB\-femit\-struct\-debug\-baseonly\fR" 4 .IX Item "-femit-struct-debug-baseonly" Emit debug information for struct-like types @@ -5288,7 +5461,7 @@ but at significant potential loss in type information to the debugger. See \fB\-femit\-struct\-debug\-reduced\fR for a less aggressive option. See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. .Sp -This option works only with \s-1DWARF\s0 2. +This option works only with \s-1DWARF 2.\s0 .IP "\fB\-femit\-struct\-debug\-reduced\fR" 4 .IX Item "-femit-struct-debug-reduced" Emit debug information for struct-like types @@ -5301,7 +5474,7 @@ with some potential loss in type information to the debugger. See \fB\-femit\-struct\-debug\-baseonly\fR for a more aggressive option. See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. .Sp -This option works only with \s-1DWARF\s0 2. +This option works only with \s-1DWARF 2.\s0 .IP "\fB\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR]" 4 .IX Item "-femit-struct-debug-detailed[=spec-list]" Specify the struct-like types @@ -5347,7 +5520,7 @@ You may need to experiment to determine the best settings for your application. .Sp The default is \fB\-femit\-struct\-debug\-detailed=all\fR. .Sp -This option works only with \s-1DWARF\s0 2. +This option works only with \s-1DWARF 2.\s0 .IP "\fB\-fno\-merge\-debug\-strings\fR" 4 .IX Item "-fno-merge-debug-strings" Direct the linker to not merge together strings in the debugging @@ -5361,8 +5534,8 @@ When compiling files in directory \fI\fIold\fI\fR, record debugging information describing them as in \fI\fInew\fI\fR instead. .IP "\fB\-fno\-dwarf2\-cfi\-asm\fR" 4 .IX Item "-fno-dwarf2-cfi-asm" -Emit \s-1DWARF\s0 2 unwind info as compiler generated \f(CW\*(C`.eh_frame\*(C'\fR section -instead of using \s-1GAS\s0 \f(CW\*(C`.cfi_*\*(C'\fR directives. +Emit \s-1DWARF 2\s0 unwind info as compiler generated \f(CW\*(C`.eh_frame\*(C'\fR section +instead of using \s-1GAS \s0\f(CW\*(C`.cfi_*\*(C'\fR directives. .IP "\fB\-p\fR" 4 .IX Item "-p" Generate extra code to write profile information suitable for the @@ -5508,7 +5681,7 @@ Set the internal debug counter upper bound. \fIcounter-value-list\fR is a comma-separated list of \fIname\fR:\fIvalue\fR pairs which sets the upper bound of each debug counter \fIname\fR to \fIvalue\fR. All debug counters have the initial upper bound of \f(CW\*(C`UINT_MAX\*(C'\fR; -thus \f(CW\*(C`dbg_cnt()\*(C'\fR returns true always unless the upper bound +thus \f(CW\*(C`dbg_cnt\*(C'\fR returns true always unless the upper bound is set by this option. For example, with \fB\-fdbg\-cnt=dce:10,tail_call:0\fR, \&\f(CW\*(C`dbg_cnt(dce)\*(C'\fR returns true only for first 10 invocations. @@ -5519,7 +5692,7 @@ For example, with \fB\-fdbg\-cnt=dce:10,tail_call:0\fR, .IX Item "-fdisable-kind-pass=range-list" .PD This is a set of options that are used to explicitly disable/enable -optimization passes. These options are intended for use for debugging \s-1GCC\s0. +optimization passes. These options are intended for use for debugging \s-1GCC.\s0 Compiler users should use regular options for enabling/disabling passes instead. .RS 4 @@ -5992,7 +6165,7 @@ by some other path. When dumping pretty-printed trees, this option inhibits dumping the bodies of control structures. .Sp -When dumping \s-1RTL\s0, print the \s-1RTL\s0 in slim (condensed) form instead of +When dumping \s-1RTL,\s0 print the \s-1RTL\s0 in slim (condensed) form instead of the default LISP-like representation. .IP "\fBraw\fR" 4 .IX Item "raw" @@ -6027,7 +6200,7 @@ Enable showing virtual operands for every statement. Enable showing line numbers for statements. .IP "\fBuid\fR" 4 .IX Item "uid" -Enable showing the unique \s-1ID\s0 (\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. +Enable showing the unique \s-1ID \s0(\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. .IP "\fBverbose\fR" 4 .IX Item "verbose" Enable showing the tree dump for each statement. @@ -6105,7 +6278,7 @@ Dump aliasing information for each function. The file name is made by appending \fI.alias\fR to the source file name. .IP "\fBccp\fR" 4 .IX Item "ccp" -Dump each function after \s-1CCP\s0. The file name is made by appending +Dump each function after \s-1CCP. \s0 The file name is made by appending \&\fI.ccp\fR to the source file name. .IP "\fBstoreccp\fR" 4 .IX Item "storeccp" @@ -6433,6 +6606,8 @@ optimizing. Use of \fB\-gdwarf\-4\fR is recommended along with it. .Sp It can be enabled even if var-tracking is disabled, in which case annotations are created and maintained, but discarded at the end. +By default, this flag is enabled together with \fB\-fvar\-tracking\fR, +except when selective scheduling is enabled. .IP "\fB\-fvar\-tracking\-assignments\-toggle\fR" 4 .IX Item "-fvar-tracking-assignments-toggle" Toggle \fB\-fvar\-tracking\-assignments\fR, in the same way that @@ -6518,7 +6693,7 @@ Print the compiler's built-in specs\-\-\-and don't do anything else. (This is used when \s-1GCC\s0 itself is being built.) .IP "\fB\-fno\-eliminate\-unused\-debug\-types\fR" 4 .IX Item "-fno-eliminate-unused-debug-types" -Normally, when producing \s-1DWARF\s0 2 output, \s-1GCC\s0 avoids producing debug symbol +Normally, when producing \s-1DWARF 2\s0 output, \s-1GCC\s0 avoids producing debug symbol output for types that are nowhere used in the source file being compiled. Sometimes it is useful to have \s-1GCC\s0 emit debugging information for all types declared in a compilation @@ -6639,6 +6814,7 @@ also turns on the following optimization flags: \&\-finline\-small\-functions \&\-findirect\-inlining \&\-fipa\-cp +\&\-fipa\-cp\-alignment \&\-fipa\-sra \&\-fipa\-icf \&\-fisolate\-erroneous\-paths\-dereference @@ -6722,7 +6898,7 @@ function calls and pops them all at once. Disabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. .IP "\fB\-fforward\-propagate\fR" 4 .IX Item "-fforward-propagate" -Perform a forward propagation pass on \s-1RTL\s0. The pass tries to combine two +Perform a forward propagation pass on \s-1RTL. \s0 The pass tries to combine two instructions and checks if the result can be simplified. If loop unrolling is active, two passes are performed and the second is scheduled after loop unrolling. @@ -6748,17 +6924,16 @@ restore frame pointers; it also makes an extra register available in many functions. \fBIt also makes debugging impossible on some machines.\fR .Sp -On some machines, such as the \s-1VAX\s0, this flag has no effect, because +On some machines, such as the \s-1VAX,\s0 this flag has no effect, because the standard calling sequence automatically handles the frame pointer and nothing is saved by pretending it doesn't exist. The machine-description macro \f(CW\*(C`FRAME_POINTER_REQUIRED\*(C'\fR controls whether a target machine supports this flag. .Sp -Starting with \s-1GCC\s0 version 4.6, the default setting (when not optimizing for -size) for 32\-bit GNU/Linux x86 and 32\-bit Darwin x86 targets has been changed to -\&\fB\-fomit\-frame\-pointer\fR. The default can be reverted to -\&\fB\-fno\-omit\-frame\-pointer\fR by configuring \s-1GCC\s0 with the -\&\fB\-\-enable\-frame\-pointer\fR configure option. +The default setting (when not optimizing for +size) for 32\-bit GNU/Linux x86 and 32\-bit Darwin x86 targets is +\&\fB\-fomit\-frame\-pointer\fR. You can configure \s-1GCC\s0 with the +\&\fB\-\-enable\-frame\-pointer\fR configure option to change the default. .Sp Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. .IP "\fB\-foptimize\-sibling\-calls\fR" 4 @@ -6874,7 +7049,7 @@ attribute or declspec In C, emit \f(CW\*(C`static\*(C'\fR functions that are declared \f(CW\*(C`inline\*(C'\fR into the object file, even if the function has been inlined into all of its callers. This switch does not affect functions using the -\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU\s0 C90. In \*(C+, emit any and all +\&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU C90. \s0 In \*(C+, emit any and all inline functions into the object file. .IP "\fB\-fkeep\-static\-consts\fR" 4 .IX Item "-fkeep-static-consts" @@ -6941,7 +7116,7 @@ The default is \fB\-ffunction\-cse\fR .IP "\fB\-fno\-zero\-initialized\-in\-bss\fR" 4 .IX Item "-fno-zero-initialized-in-bss" If the target supports a \s-1BSS\s0 section, \s-1GCC\s0 by default puts variables that -are initialized to zero into \s-1BSS\s0. This can save space in the resulting +are initialized to zero into \s-1BSS. \s0 This can save space in the resulting code. .Sp This option turns off this behavior because some programs explicitly @@ -7064,11 +7239,11 @@ instructions to support this. Enabled by default at \fB\-O\fR and higher on architectures that support this. .IP "\fB\-fdce\fR" 4 .IX Item "-fdce" -Perform dead code elimination (\s-1DCE\s0) on \s-1RTL\s0. +Perform dead code elimination (\s-1DCE\s0) on \s-1RTL.\s0 Enabled by default at \fB\-O\fR and higher. .IP "\fB\-fdse\fR" 4 .IX Item "-fdse" -Perform dead store elimination (\s-1DSE\s0) on \s-1RTL\s0. +Perform dead store elimination (\s-1DSE\s0) on \s-1RTL.\s0 Enabled by default at \fB\-O\fR and higher. .IP "\fB\-fif\-conversion\fR" 4 .IX Item "-fif-conversion" @@ -7148,6 +7323,15 @@ registers after writing to their lower 32\-bit half. .Sp Enabled for Alpha, AArch64 and x86 at levels \fB\-O2\fR, \&\fB\-O3\fR, \fB\-Os\fR. +.IP "\fB\-fno\-lifetime\-dse\fR" 4 +.IX Item "-fno-lifetime-dse" +In \*(C+ the value of an object is only affected by changes within its +lifetime: when the constructor begins, the object has an indeterminate +value, and any changes during the lifetime of the object are dead when +the object is destroyed. Normally dead store elimination will take +advantage of this; if your code relies on the value of the object +storage persisting beyond the lifetime of the object, you can use this +flag to disable this optimization. .IP "\fB\-flive\-range\-shrinkage\fR" 4 .IX Item "-flive-range-shrinkage" Attempt to decrease register pressure through register live range @@ -7219,7 +7403,7 @@ The default value is 5. If the value \fIn\fR is greater or equal to 10, the dump output is sent to stderr using the same format as \fIn\fR minus 10. .IP "\fB\-flra\-remat\fR" 4 .IX Item "-flra-remat" -Enable CFG-sensitive rematerialization in \s-1LRA\s0. Instead of loading +Enable CFG-sensitive rematerialization in \s-1LRA. \s0 Instead of loading values of spilled pseudos, \s-1LRA\s0 tries to rematerialize (recalculate) values if it is profitable. .Sp @@ -7378,9 +7562,9 @@ When pipelining loops during selective scheduling, also pipeline outer loops. This option has no effect unless \fB\-fsel\-sched\-pipelining\fR is turned on. .IP "\fB\-fsemantic\-interposition\fR" 4 .IX Item "-fsemantic-interposition" -Some object formats, like \s-1ELF\s0, allow interposing of symbols by the +Some object formats, like \s-1ELF,\s0 allow interposing of symbols by the dynamic linker. -This means that for symbols exported from the \s-1DSO\s0, the compiler cannot perform +This means that for symbols exported from the \s-1DSO,\s0 the compiler cannot perform interprocedural propagation, inlining and other optimizations in anticipation that the function or variable in question may change. While this feature is useful, for example, to rewrite memory allocation functions by a debugging @@ -7450,7 +7634,7 @@ at \fB\-O\fR and higher. Perform full redundancy elimination (\s-1FRE\s0) on trees. The difference between \s-1FRE\s0 and \s-1PRE\s0 is that \s-1FRE\s0 only considers expressions that are computed on all paths leading to the redundant computation. -This analysis is faster than \s-1PRE\s0, though it exposes fewer redundancies. +This analysis is faster than \s-1PRE,\s0 though it exposes fewer redundancies. This flag is enabled by default at \fB\-O\fR and higher. .IP "\fB\-ftree\-phiprop\fR" 4 .IX Item "-ftree-phiprop" @@ -7507,6 +7691,13 @@ Because this optimization can create multiple copies of functions, it may significantly increase code size (see \fB\-\-param ipcp\-unit\-growth=\fR\fIvalue\fR). This flag is enabled by default at \fB\-O3\fR. +.IP "\fB\-fipa\-cp\-alignment\fR" 4 +.IX Item "-fipa-cp-alignment" +When enabled, this optimization propagates alignment of function +parameters to support better vectorization and string operations. +.Sp +This flag is enabled by default at \fB\-O2\fR and \fB\-Os\fR. It +requires that \fB\-fipa\-cp\fR is enabled. .IP "\fB\-fipa\-icf\fR" 4 .IX Item "-fipa-icf" Perform Identical Code Folding for functions and read-only variables. @@ -7514,7 +7705,7 @@ The optimization reduces code size and may disturb unwind stacks by replacing a function by equivalent one with a different name. The optimization works more effectively with link time optimization enabled. .Sp -Nevertheless the behavior is similar to Gold Linker \s-1ICF\s0 optimization, \s-1GCC\s0 \s-1ICF\s0 +Nevertheless the behavior is similar to Gold Linker \s-1ICF\s0 optimization, \s-1GCC ICF\s0 works on different levels and thus the optimizations are not same \- there are equivalences that are found only by \s-1GCC\s0 and equivalences found only by Gold. .Sp @@ -7549,7 +7740,7 @@ pass only operates on local scalar variables and is enabled by default at \fB\-O\fR and higher. .IP "\fB\-fssa\-phiopt\fR" 4 .IX Item "-fssa-phiopt" -Perform pattern matching on \s-1SSA\s0 \s-1PHI\s0 nodes to optimize conditional +Perform pattern matching on \s-1SSA PHI\s0 nodes to optimize conditional code. This pass is enabled by default at \fB\-O\fR and higher. .IP "\fB\-ftree\-switch\-conversion\fR" 4 .IX Item "-ftree-switch-conversion" @@ -7705,8 +7896,8 @@ to enable the Graphite loop transformation infrastructure. Enable the identity transformation for graphite. For every SCoP we generate the polyhedral representation and transform it back to gimple. Using \&\fB\-fgraphite\-identity\fR we can check the costs or benefits of the -\&\s-1GIMPLE\s0 \-> \s-1GRAPHITE\s0 \-> \s-1GIMPLE\s0 transformation. Some minimal optimizations -are also performed by the code generator \s-1ISL\s0, like index splitting and +\&\s-1GIMPLE \-\s0> \s-1GRAPHITE \-\s0> \s-1GIMPLE\s0 transformation. Some minimal optimizations +are also performed by the code generator \s-1ISL,\s0 like index splitting and dead code elimination in loops. .IP "\fB\-floop\-nest\-optimize\fR" 4 .IX Item "-floop-nest-optimize" @@ -7858,8 +8049,7 @@ from other functions. It is a more limited form of \&\fB\-ftree\-coalesce\-vars\fR. This may harm debug information of such inlined variables, but it keeps variables of the inlined-into function apart from each other, such that they are more likely to -contain the expected values in a debugging session. This was the -default in \s-1GCC\s0 versions older than 4.7. +contain the expected values in a debugging session. .IP "\fB\-ftree\-coalesce\-vars\fR" 4 .IX Item "-ftree-coalesce-vars" Tell the copyrename pass (see \fB\-ftree\-copyrename\fR) to attempt to @@ -7923,23 +8113,6 @@ checks like array bound checks and null pointer checks. This is enabled by default at \fB\-O2\fR and higher. Null pointer check elimination is only done if \fB\-fdelete\-null\-pointer\-checks\fR is enabled. -.IP "\fB\-ftracer\fR" 4 -.IX Item "-ftracer" -Perform tail duplication to enlarge superblock size. This transformation -simplifies the control flow of the function allowing other optimizations to do -a better job. -.IP "\fB\-funroll\-loops\fR" 4 -.IX Item "-funroll-loops" -Unroll loops whose number of iterations can be determined at compile -time or upon entry to the loop. \fB\-funroll\-loops\fR implies -\&\fB\-frerun\-cse\-after\-loop\fR. This option makes code larger, -and may or may not make it run faster. -.IP "\fB\-funroll\-all\-loops\fR" 4 -.IX Item "-funroll-all-loops" -Unroll all loops, even if their number of iterations is uncertain when -the loop is entered. This usually makes programs run more slowly. -\&\fB\-funroll\-all\-loops\fR implies the same options as -\&\fB\-funroll\-loops\fR, .IP "\fB\-fsplit\-ivs\-in\-unroller\fR" 4 .IX Item "-fsplit-ivs-in-unroller" Enables expression of values of induction variables in later iterations @@ -8229,7 +8402,7 @@ targets. Constructs webs as commonly used for register allocation purposes and assign each web individual pseudo register. This allows the register allocation pass to operate on pseudos directly, but also strengthens several other optimization -passes, such as \s-1CSE\s0, loop optimizer and trivial dead code remover. It can, +passes, such as \s-1CSE,\s0 loop optimizer and trivial dead code remover. It can, however, make debugging impossible, since variables no longer stay in a \&\*(L"home register\*(R". .Sp @@ -8247,7 +8420,7 @@ information. .IP "\fB\-flto[=\fR\fIn\fR\fB]\fR" 4 .IX Item "-flto[=n]" This option runs the standard link-time optimizer. When invoked -with source code, it generates \s-1GIMPLE\s0 (one of \s-1GCC\s0's internal +with source code, it generates \s-1GIMPLE \s0(one of \s-1GCC\s0's internal representations) and writes it to special \s-1ELF\s0 sections in the object file. When the object files are linked together, all the function bodies are read from these \s-1ELF\s0 sections and instantiated as if they @@ -8287,7 +8460,8 @@ them as usual to produce \fImyprog\fR. The only important thing to keep in mind is that to enable link-time optimizations you need to use the \s-1GCC\s0 driver to perform the link-step. \&\s-1GCC\s0 then automatically performs link-time optimization if any of the -objects involved were compiled with the \fB\-flto\fR. You generally +objects involved were compiled with the \fB\-flto\fR command-line option. +You generally should specify the optimization options to be used for link-time optimization though \s-1GCC\s0 tries to be clever at guessing an optimization level to use from the options used at compile-time @@ -8371,7 +8545,7 @@ link time. .Sp If \s-1LTO\s0 encounters objects with C linkage declared with incompatible types in separate translation units to be linked together (undefined -behavior according to \s-1ISO\s0 C99 6.2.7), a non-fatal diagnostic may be +behavior according to \s-1ISO C99 6.2.7\s0), a non-fatal diagnostic may be issued. The behavior is still undefined at run time. Similar diagnostics may be raised for other languages. .Sp @@ -8394,7 +8568,7 @@ regular (non-LTO) compilation. If object files containing \s-1GIMPLE\s0 bytecode are stored in a library archive, say \&\fIlibfoo.a\fR, it is possible to extract and use them in an \s-1LTO\s0 link if you are using a linker with plugin support. To create static libraries suitable -for \s-1LTO\s0, use \fBgcc-ar\fR and \fBgcc-ranlib\fR instead of \fBar\fR +for \s-1LTO,\s0 use \fBgcc-ar\fR and \fBgcc-ranlib\fR instead of \fBar\fR and \fBranlib\fR; to show the symbols of object files with \s-1GIMPLE\s0 bytecode, use \&\fBgcc-nm\fR. Those commands require that \fBar\fR, \fBranlib\fR @@ -8429,7 +8603,7 @@ The current implementation of \s-1LTO\s0 makes no attempt to generate bytecode that is portable between different types of hosts. The bytecode files are versioned and there is a strict version check, so bytecode files generated in one version of -\&\s-1GCC\s0 do not work with an older or newer version of \s-1GCC\s0. +\&\s-1GCC\s0 do not work with an older or newer version of \s-1GCC.\s0 .Sp Link-time optimization does not work well with generation of debugging information. Combining \fB\-flto\fR with @@ -8512,8 +8686,8 @@ and the object code. This makes them usable for both \s-1LTO\s0 linking and norm linking. This option is effective only when compiling with \fB\-flto\fR and is ignored at link time. .Sp -\&\fB\-fno\-fat\-lto\-objects\fR improves compilation time over plain \s-1LTO\s0, but -requires the complete toolchain to be aware of \s-1LTO\s0. It requires a linker with +\&\fB\-fno\-fat\-lto\-objects\fR improves compilation time over plain \s-1LTO,\s0 but +requires the complete toolchain to be aware of \s-1LTO.\s0 It requires a linker with linker plugin support for basic functionality. Additionally, \&\fBnm\fR, \fBar\fR and \fBranlib\fR need to support linker plugins to allow a full-featured build environment @@ -8534,12 +8708,6 @@ This pass only applies to certain targets that cannot explicitly represent the comparison operation before register allocation is complete. .Sp Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. -.IP "\fB\-fuse\-ld=bfd\fR" 4 -.IX Item "-fuse-ld=bfd" -Use the \fBbfd\fR linker instead of the default linker. -.IP "\fB\-fuse\-ld=gold\fR" 4 -.IX Item "-fuse-ld=gold" -Use the \fBgold\fR linker instead of the default linker. .IP "\fB\-fcprop\-registers\fR" 4 .IX Item "-fcprop-registers" After register allocation and post-register allocation instruction splitting, @@ -8628,7 +8796,7 @@ E.g. .Ve .Sp Then use the \fBcreate_gcov\fR tool to convert the raw profile data -to a format that can be used by \s-1GCC\s0. You must also supply the +to a format that can be used by \s-1GCC. \s0 You must also supply the unstripped binary for your program to this tool. See <\fBhttps://github.com/google/autofdo\fR>. .Sp @@ -8658,15 +8826,15 @@ them to store all pertinent intermediate computations into variables. .IP "\fB\-fexcess\-precision=\fR\fIstyle\fR" 4 .IX Item "-fexcess-precision=style" This option allows further control over excess precision on machines -where floating-point registers have more precision than the \s-1IEEE\s0 -\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR types and the processor does not +where floating-point registers have more precision than the \s-1IEEE +\&\s0\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR types and the processor does not support operations rounding to those types. By default, \&\fB\-fexcess\-precision=fast\fR is in effect; this means that operations are carried out in the precision of the registers and that it is unpredictable when rounding to the types specified in the source code takes place. When compiling C, if \&\fB\-fexcess\-precision=standard\fR is specified then excess -precision follows the rules specified in \s-1ISO\s0 C99; in particular, +precision follows the rules specified in \s-1ISO C99\s0; in particular, both casts and assignments cause values to be rounded to their semantic types (whereas \fB\-ffloat\-store\fR only affects assignments). This option is enabled by default for C if a strict @@ -8730,7 +8898,7 @@ The default is \fB\-fno\-unsafe\-math\-optimizations\fR. .IP "\fB\-fassociative\-math\fR" 4 .IX Item "-fassociative-math" Allow re-association of operands in series of floating-point operations. -This violates the \s-1ISO\s0 C and \*(C+ language standard by possibly changing +This violates the \s-1ISO C\s0 and \*(C+ language standard by possibly changing computation result. \s-1NOTE:\s0 re-ordering may change the sign of zero as well as ignore NaNs and inhibit or create underflow or overflow (and thus cannot be used on code that relies on rounding behavior like @@ -8833,8 +9001,8 @@ whether the result of a complex multiplication or division is \f(CW\*(C`NaN default is \fB\-fno\-cx\-limited\-range\fR, but is enabled by \&\fB\-ffast\-math\fR. .Sp -This option controls the default setting of the \s-1ISO\s0 C99 -\&\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to +This option controls the default setting of the \s-1ISO C99 +\&\s0\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to all languages. .IP "\fB\-fcx\-fortran\-rules\fR" 4 .IX Item "-fcx-fortran-rules" @@ -8999,6 +9167,14 @@ Like \fB\-fstack\-protector\fR except that all functions are protected. Like \fB\-fstack\-protector\fR but includes additional functions to be protected \-\-\- those that have local array definitions, or have references to local frame addresses. +.IP "\fB\-fstack\-protector\-explicit\fR" 4 +.IX Item "-fstack-protector-explicit" +Like \fB\-fstack\-protector\fR but only protects those functions which +have the \f(CW\*(C`stack_protect\*(C'\fR attribute +.IP "\fB\-fstdarg\-opt\fR" 4 +.IX Item "-fstdarg-opt" +Optimize the prologue of variadic argument functions with respect to usage of +those arguments. .IP "\fB\-fsection\-anchors\fR" 4 .IX Item "-fsection-anchors" Try to reduce the number of symbolic address calculations by using @@ -9097,7 +9273,7 @@ optimization is not done. .IP "\fBmax-gcse-insertion-ratio\fR" 4 .IX Item "max-gcse-insertion-ratio" If the ratio of expression insertions to deletions is larger than this value -for any expression, then \s-1RTL\s0 \s-1PRE\s0 inserts or removes the expression and thus +for any expression, then \s-1RTL PRE\s0 inserts or removes the expression and thus leaves partially redundant computations in the instruction stream. The default value is 20. .IP "\fBmax-pending-list-length\fR" 4 .IX Item "max-pending-list-length" @@ -9112,7 +9288,7 @@ when modulo scheduling a loop. Larger values can exponentially increase compilation time. .IP "\fBmax-inline-insns-single\fR" 4 .IX Item "max-inline-insns-single" -Several parameters control the tree inliner used in \s-1GCC\s0. +Several parameters control the tree inliner used in \s-1GCC.\s0 This number sets the maximum number of instructions (counted in \s-1GCC\s0's internal representation) in a single function that the tree inliner considers for inlining. This only affects functions declared @@ -9160,7 +9336,7 @@ before applying \fB\-\-param inline-unit-growth\fR. The default is 10000. .IP "\fBinline-unit-growth\fR" 4 .IX Item "inline-unit-growth" Specifies maximal overall growth of the compilation unit caused by inlining. -The default value is 30 which limits unit growth to 1.3 times the original +The default value is 20 which limits unit growth to 1.2 times the original size. Cold functions (either marked cold via an attribute or by profile feedback) are not accounted into the unit size. .IP "\fBipcp-unit-growth\fR" 4 @@ -9222,7 +9398,7 @@ The default value is 10. .IX Item "early-inlining-insns" Specify growth that the early inliner can make. In effect it increases the amount of inlining for code having a large abstraction penalty. -The default value is 10. +The default value is 14. .IP "\fBmax-early-inliner-iterations\fR" 4 .IX Item "max-early-inliner-iterations" Limit of iterations of the early inliner. This basically bounds @@ -9424,7 +9600,8 @@ This value is used to limit superblock formation once the given percentage of executed instructions is covered. This limits unnecessary code size expansion. .Sp -The \fBtracer-dynamic-coverage-feedback\fR is used only when profile +The \fBtracer-dynamic-coverage-feedback\fR parameter +is used only when profile feedback is available. The real profiles (as opposed to statically estimated ones) are much less balanced allowing the threshold to be larger value. .IP "\fBtracer-max-code-growth\fR" 4 @@ -9467,7 +9644,7 @@ Tuning this may improve compilation speed; it has no effect on code generation. .Sp The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when -\&\s-1RAM\s0 >= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\s0\*(R" is +\&\s-1RAM \s0>= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\*(R"\s0 is the smallest of actual \s-1RAM\s0 and \f(CW\*(C`RLIMIT_DATA\*(C'\fR or \f(CW\*(C`RLIMIT_AS\*(C'\fR. If \&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower bound of 30% is used. Setting this parameter and @@ -9482,7 +9659,7 @@ by \fBggc-min-expand\fR% beyond \fBggc-min-heapsize\fR. Again, tuning this may improve compilation speed, and has no effect on code generation. .Sp -The default is the smaller of \s-1RAM/8\s0, \s-1RLIMIT_RSS\s0, or a limit that +The default is the smaller of \s-1RAM/8, RLIMIT_RSS,\s0 or a limit that tries to ensure that \s-1RLIMIT_DATA\s0 or \s-1RLIMIT_AS\s0 are not exceeded, but with a lower bound of 4096 (four megabytes) and an upper bound of 131072 (128 megabytes). If \s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a @@ -9512,7 +9689,8 @@ branch or duplicate the code on its destination. Code is duplicated when its estimated size is smaller than this value multiplied by the estimated size of unconditional jump in the hot spots of the program. .Sp -The \fBreorder-block-duplicate-feedback\fR is used only when profile +The \fBreorder-block-duplicate-feedback\fR parameter +is used only when profile feedback is available. It may be set to higher values than \&\fBreorder-block-duplicate\fR since information about the hot spots is more accurate. @@ -9700,6 +9878,14 @@ of available registers reserved for some other purposes is given by this parameter. The default value of the parameter is 2, which is the minimal number of registers needed by typical instructions. This value is the best found from numerous experiments. +.IP "\fBlra-inheritance-ebb-probability-cutoff\fR" 4 +.IX Item "lra-inheritance-ebb-probability-cutoff" +\&\s-1LRA\s0 tries to reuse values reloaded in registers in subsequent insns. +This optimization is called inheritance. \s-1EBB\s0 is used as a region to +do this optimization. The parameter defines a minimal fall-through +edge probability in percentage used to add \s-1BB\s0 to inheritance \s-1EBB\s0 in +\&\s-1LRA. \s0 The default value of the parameter is 40. The value was chosen +from numerous runs of \s-1SPEC2000\s0 on x86\-64. .IP "\fBloop-invariant-max-bbs-in-loop\fR" 4 .IX Item "loop-invariant-max-bbs-in-loop" Loop invariant motion can be very expensive, both in compilation time and @@ -9784,7 +9970,7 @@ length can be changed using the \fBloop-block-tile-size\fR parameter. The default value is 51 iterations. .IP "\fBloop-unroll-jam-size\fR" 4 .IX Item "loop-unroll-jam-size" -Specify the unroll factor for the \fB\-floop\-unroll\-and\-jam\fR. The +Specify the unroll factor for the \fB\-floop\-unroll\-and\-jam\fR option. The default value is 4. .IP "\fBloop-unroll-jam-depth\fR" 4 .IX Item "loop-unroll-jam-depth" @@ -9801,6 +9987,14 @@ stores per one formal parameter of a function. IPA-CP calculates its own score of cloning profitability heuristics and performs those cloning opportunities with scores that exceed \&\fBipa-cp-eval-threshold\fR. +.IP "\fBipa-cp-recursion-penalty\fR" 4 +.IX Item "ipa-cp-recursion-penalty" +Percentage penalty the recursive functions will receive when they +are evaluated for cloning. +.IP "\fBipa-cp-single-call-penalty\fR" 4 +.IX Item "ipa-cp-single-call-penalty" +Percentage penalty functions containg a single call to another +function will receive when they are evaluated for cloning. .IP "\fBipa-max-agg-items\fR" 4 .IX Item "ipa-max-agg-items" IPA-CP is also capable to propagate a number of scalar values passed @@ -9832,7 +10026,7 @@ The number of partitions should exceed the number of CPUs used for compilation. The default value is 32. .IP "\fBlto-minpartition\fR" 4 .IX Item "lto-minpartition" -Size of minimal partition for \s-1WHOPR\s0 (in estimated instructions). +Size of minimal partition for \s-1WHOPR \s0(in estimated instructions). This prevents expenses of splitting very small programs into too many partitions. .IP "\fBcxx-max-namespaces-for-diagnostic-help\fR" 4 @@ -10068,7 +10262,7 @@ get trigraph conversion without warnings, but get the other .IP "\fB\-Wtraditional\fR" 4 .IX Item "-Wtraditional" Warn about certain constructs that behave differently in traditional and -\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C +\&\s-1ISO C. \s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C equivalent, and problematic constructs which should be avoided. .IP "\fB\-Wundef\fR" 4 .IX Item "-Wundef" @@ -10121,7 +10315,7 @@ in finding bugs in your own code, therefore suppressed. If you are responsible for the system library, you may want to see them. .IP "\fB\-w\fR" 4 .IX Item "-w" -Suppress all warnings, including those which \s-1GNU\s0 \s-1CPP\s0 issues by default. +Suppress all warnings, including those which \s-1GNU CPP\s0 issues by default. .IP "\fB\-pedantic\fR" 4 .IX Item "-pedantic" Issue all the mandatory diagnostics listed in the C standard. Some of @@ -10139,7 +10333,7 @@ suitable for \fBmake\fR describing the dependencies of the main source file. The preprocessor outputs one \fBmake\fR rule containing the object file name for that source file, a colon, and the names of all the included files, including those coming from \fB\-include\fR or -\&\fB\-imacros\fR command line options. +\&\fB\-imacros\fR command-line options. .Sp Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the object file name consists of the name of the source file with any @@ -10261,10 +10455,10 @@ This option allows use of a precompiled header together with \fB\-E\fR. It inse \&\f(CW\*(C`#pragma GCC pch_preprocess "\f(CIfilename\f(CW"\*(C'\fR in the output to mark the place where the precompiled header was found, and its \fIfilename\fR. When \fB\-fpreprocessed\fR is in use, \s-1GCC\s0 recognizes this \f(CW\*(C`#pragma\*(C'\fR -and loads the \s-1PCH\s0. +and loads the \s-1PCH.\s0 .Sp This option is off by default, because the resulting preprocessed output -is only really suitable as input to \s-1GCC\s0. It is switched on by +is only really suitable as input to \s-1GCC. \s0 It is switched on by \&\fB\-save\-temps\fR. .Sp You should not write this \f(CW\*(C`#pragma\*(C'\fR in your own code, but it is @@ -10317,7 +10511,7 @@ may be one of: .el .IP "\f(CWiso9899:1990\fR" 4 .IX Item "iso9899:1990" .PD -The \s-1ISO\s0 C standard from 1990. \fBc90\fR is the customary shorthand for +The \s-1ISO C\s0 standard from 1990. \fBc90\fR is the customary shorthand for this version of the standard. .Sp The \fB\-ansi\fR option is equivalent to \fB\-std=c90\fR. @@ -10339,7 +10533,7 @@ The 1990 C standard, as amended in 1994. .el .IP "\f(CWc9x\fR" 4 .IX Item "c9x" .PD -The revised \s-1ISO\s0 C standard, published in December 1999. Before +The revised \s-1ISO C\s0 standard, published in December 1999. Before publication, this was known as C9X. .ie n .IP """iso9899:2011""" 4 .el .IP "\f(CWiso9899:2011\fR" 4 @@ -10352,7 +10546,7 @@ publication, this was known as C9X. .el .IP "\f(CWc1x\fR" 4 .IX Item "c1x" .PD -The revised \s-1ISO\s0 C standard, published in December 2011. Before +The revised \s-1ISO C\s0 standard, published in December 2011. Before publication, this was known as C1X. .ie n .IP """gnu90""" 4 .el .IP "\f(CWgnu90\fR" 4 @@ -10384,7 +10578,7 @@ The 2011 C standard plus \s-1GNU\s0 extensions. .ie n .IP """c++98""" 4 .el .IP "\f(CWc++98\fR" 4 .IX Item "c++98" -The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. +The 1998 \s-1ISO \*(C+\s0 standard plus amendments. .ie n .IP """gnu++98""" 4 .el .IP "\f(CWgnu++98\fR" 4 .IX Item "gnu++98" @@ -10536,7 +10730,7 @@ line. If the value is less than 1 or greater than 100, the option is ignored. The default is 8. .IP "\fB\-fdebug\-cpp\fR" 4 .IX Item "-fdebug-cpp" -This option is only useful for debugging \s-1GCC\s0. When used with +This option is only useful for debugging \s-1GCC. \s0 When used with \&\fB\-E\fR, dumps debugging information about location maps. Every token in the output is preceded by the dump of the map its location belongs to. The dump of the map holding the location of a token would @@ -10569,12 +10763,12 @@ Note that \f(CW\*(C`\-ftrack\-macro\-expansion=2\*(C'\fR is activated by default .IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 .IX Item "-fexec-charset=charset" Set the execution character set, used for string and character -constants. The default is \s-1UTF\-8\s0. \fIcharset\fR can be any encoding +constants. The default is \s-1UTF\-8. \s0\fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. .IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 .IX Item "-fwide-exec-charset=charset" Set the wide execution character set, used for wide string and -character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16\s0, whichever +character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16,\s0 whichever corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with \&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have @@ -10582,10 +10776,10 @@ problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. .IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 .IX Item "-finput-charset=charset" Set the input character set, used for translation from the character -set of the input file to the source character set used by \s-1GCC\s0. If the +set of the input file to the source character set used by \s-1GCC. \s0 If the locale does not specify, or \s-1GCC\s0 cannot get this information from the -locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale -or this command line option. Currently the command line option takes +locale, the default is \s-1UTF\-8. \s0 This can be overridden by either the locale +or this command-line option. Currently the command-line option takes precedence if there's a conflict. \fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. .IP "\fB\-fworking\-directory\fR" 4 @@ -10621,7 +10815,7 @@ Cancel an assertion with the predicate \fIpredicate\fR and answer .IX Item "-dCHARS" \&\fI\s-1CHARS\s0\fR is a sequence of one or more of the following characters, and must not be preceded by a space. Other characters are interpreted -by the compiler proper, or reserved for future versions of \s-1GCC\s0, and so +by the compiler proper, or reserved for future versions of \s-1GCC,\s0 and so are silently ignored. If you specify characters whose behavior conflicts, the result is undefined. .RS 4 @@ -10697,12 +10891,12 @@ The \fB\-CC\fR option is generally used to support lint comments. .IP "\fB\-traditional\-cpp\fR" 4 .IX Item "-traditional-cpp" Try to imitate the behavior of old-fashioned C preprocessors, as -opposed to \s-1ISO\s0 C preprocessors. +opposed to \s-1ISO C\s0 preprocessors. .IP "\fB\-trigraphs\fR" 4 .IX Item "-trigraphs" Process trigraph sequences. These are three-character sequences, all starting with \fB??\fR, that -are defined by \s-1ISO\s0 C to stand for single characters. For example, +are defined by \s-1ISO C\s0 to stand for single characters. For example, \&\fB??/\fR stands for \fB\e\fR, so \fB'??/n'\fR is a character constant for a newline. By default, \s-1GCC\s0 ignores trigraphs, but in standard-conforming modes it converts them. See the \fB\-std\fR and @@ -10724,11 +10918,11 @@ short file names, such as MS-DOS. .IP "\fB\-\-target\-help\fR" 4 .IX Item "--target-help" .PD -Print text describing all the command line options instead of +Print text describing all the command-line options instead of preprocessing anything. .IP "\fB\-v\fR" 4 .IX Item "-v" -Verbose mode. Print out \s-1GNU\s0 \s-1CPP\s0's version number at the beginning of +Verbose mode. Print out \s-1GNU CPP\s0's version number at the beginning of execution, and report the final form of the include path. .IP "\fB\-H\fR" 4 .IX Item "-H" @@ -10743,7 +10937,7 @@ header file is printed with \fB...x\fR and a valid one with \fB...!\fR . .IP "\fB\-\-version\fR" 4 .IX Item "--version" .PD -Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to +Print out \s-1GNU CPP\s0's version number. With one dash, proceed to preprocess as normal. With two dashes, exit immediately. .SS "Passing Options to the Assembler" .IX Subsection "Passing Options to the Assembler" @@ -10782,6 +10976,12 @@ to the linker. .PD If any of these options is used, then the linker is not run, and object file names should not be used as arguments. +.IP "\fB\-fuse\-ld=bfd\fR" 4 +.IX Item "-fuse-ld=bfd" +Use the \fBbfd\fR linker instead of the default linker. +.IP "\fB\-fuse\-ld=gold\fR" 4 +.IX Item "-fuse-ld=gold" +Use the \fBgold\fR linker instead of the default linker. .IP "\fB\-l\fR\fIlibrary\fR" 4 .IX Item "-llibrary" .PD 0 @@ -10962,6 +11162,25 @@ option is not used, then this links against the shared version of \&\fIlibubsan\fR. The \fB\-static\-libubsan\fR option directs the \s-1GCC\s0 driver to link \fIlibubsan\fR statically, without necessarily linking other libraries statically. +.IP "\fB\-static\-libmpx\fR" 4 +.IX Item "-static-libmpx" +When the \fB\-fcheck\-pointer bounds\fR and \fB\-mmpx\fR options are +used to link a program, the \s-1GCC\s0 driver automatically links against +\&\fIlibmpx\fR. If \fIlibmpx\fR is available as a shared library, +and the \fB\-static\fR option is not used, then this links against +the shared version of \fIlibmpx\fR. The \fB\-static\-libmpx\fR +option directs the \s-1GCC\s0 driver to link \fIlibmpx\fR statically, +without necessarily linking other libraries statically. +.IP "\fB\-static\-libmpxwrappers\fR" 4 +.IX Item "-static-libmpxwrappers" +When the \fB\-fcheck\-pointer bounds\fR and \fB\-mmpx\fR options are used +to link a program without also using \fB\-fno\-chkp\-use\-wrappers\fR, the +\&\s-1GCC\s0 driver automatically links against \fIlibmpxwrappers\fR. If +\&\fIlibmpxwrappers\fR is available as a shared library, and the +\&\fB\-static\fR option is not used, then this links against the shared +version of \fIlibmpxwrappers\fR. The \fB\-static\-libmpxwrappers\fR +option directs the \s-1GCC\s0 driver to link \fIlibmpxwrappers\fR statically, +without necessarily linking other libraries statically. .IP "\fB\-static\-libstdc++\fR" 4 .IX Item "-static-libstdc++" When the \fBg++\fR program is used to link a \*(C+ program, it @@ -11079,7 +11298,7 @@ those results in a file name that is found, the unmodified program name is searched for using the directories specified in your \&\fB\s-1PATH\s0\fR environment variable. .Sp -The compiler checks to see if the path provided by the \fB\-B\fR +The compiler checks to see if the path provided by \fB\-B\fR refers to a directory, and if necessary it adds a directory separator character at the end of the path. .Sp @@ -11136,13 +11355,14 @@ such a suffix. .IP "\fB\-I\-\fR" 4 .IX Item "-I-" This option has been deprecated. Please use \fB\-iquote\fR instead for -\&\fB\-I\fR directories before the \fB\-I\-\fR and remove the \fB\-I\-\fR. +\&\fB\-I\fR directories before the \fB\-I\-\fR and remove the \fB\-I\-\fR +option. Any directories you specify with \fB\-I\fR options before the \fB\-I\-\fR option are searched only for the case of \f(CW\*(C`#include "\f(CIfile\f(CW"\*(C'\fR; they are not searched for \f(CW\*(C`#include <\f(CIfile\f(CW>\*(C'\fR. .Sp If additional directories are specified with \fB\-I\fR options after -the \fB\-I\-\fR, these directories are searched for all \f(CW\*(C`#include\*(C'\fR +the \fB\-I\-\fR option, these directories are searched for all \f(CW\*(C`#include\*(C'\fR directives. (Ordinarily \fIall\fR \fB\-I\fR directories are used this way.) .Sp @@ -11189,7 +11409,7 @@ but long int and pointer are 64\-bit. .Sp The default depends on the specific target configuration. Note that the \s-1LP64\s0 and \s-1ILP32\s0 ABIs are not link-compatible; you must compile your -entire program with the same \s-1ABI\s0, and link with a compatible set of libraries. +entire program with the same \s-1ABI,\s0 and link with a compatible set of libraries. .IP "\fB\-mbig\-endian\fR" 4 .IX Item "-mbig-endian" Generate big-endian code. This is the default when \s-1GCC\s0 is configured for an @@ -11267,11 +11487,12 @@ architecture. .IX Item "-mtune=name" Specify the name of the target processor for which \s-1GCC\s0 should tune the performance of the code. Permissible values for this option are: -\&\fBgeneric\fR, \fBcortex\-a53\fR, \fBcortex\-a57\fR, \fBthunderx\fR. +\&\fBgeneric\fR, \fBcortex\-a53\fR, \fBcortex\-a57\fR, \fBcortex\-a72\fR, +\&\fBexynos\-m1\fR, \fBthunderx\fR, \fBxgene1\fR. .Sp Additionally, this option can specify that \s-1GCC\s0 should tune the performance -of the code for a big.LITTLE system. The only permissible value is -\&\fBcortex\-a57.cortex\-a53\fR. +of the code for a big.LITTLE system. Permissible values for this +option are: \fBcortex\-a57.cortex\-a53\fR, \fBcortex\-a72.cortex\-a53\fR. .Sp Where none of \fB\-mtune=\fR, \fB\-mcpu=\fR or \fB\-march=\fR are specified, the code is tuned to perform well across a range @@ -11299,8 +11520,8 @@ by \fB\-mtune\fR). Where this option is used in conjunction with \fB\-march\fR or \fB\-mtune\fR, those options take precedence over the appropriate part of this option. .PP -\fB\-march\fR and \fB\-mcpu\fR feature modifiers -.IX Subsection "-march and -mcpu feature modifiers" +\fB\-march\fR and \fB\-mcpu\fR Feature Modifiers +.IX Subsection "-march and -mcpu Feature Modifiers" .PP Feature modifiers used with \fB\-march\fR and \fB\-mcpu\fR can be one the following: @@ -11415,7 +11636,7 @@ This is the mode used for floating-point calculations with round-to-nearest-or-even rounding mode. .IP "\fBint\fR" 4 .IX Item "int" -This is the mode used to perform integer calculations in the \s-1FPU\s0, e.g. +This is the mode used to perform integer calculations in the \s-1FPU,\s0 e.g. integer multiply, or integer multiply-and-accumulate. .RE .RS 4 @@ -11477,13 +11698,13 @@ values for \fIcpu\fR are .RS 4 .IP "\fB\s-1ARC600\s0\fR" 4 .IX Item "ARC600" -Compile for \s-1ARC600\s0. Aliases: \fB\-mA6\fR, \fB\-mARC600\fR. +Compile for \s-1ARC600. \s0 Aliases: \fB\-mA6\fR, \fB\-mARC600\fR. .IP "\fB\s-1ARC601\s0\fR" 4 .IX Item "ARC601" -Compile for \s-1ARC601\s0. Alias: \fB\-mARC601\fR. +Compile for \s-1ARC601. \s0 Alias: \fB\-mARC601\fR. .IP "\fB\s-1ARC700\s0\fR" 4 .IX Item "ARC700" -Compile for \s-1ARC700\s0. Aliases: \fB\-mA7\fR, \fB\-mARC700\fR. +Compile for \s-1ARC700. \s0 Aliases: \fB\-mA7\fR, \fB\-mARC700\fR. This is the default when configured with \fB\-\-with\-cpu=arc700\fR. .RE .RS 4 @@ -11510,7 +11731,7 @@ Generate Extended arithmetic instructions. Currently only supported. This is always enabled for \fB\-mcpu=ARC700\fR. .IP "\fB\-mno\-mpy\fR" 4 .IX Item "-mno-mpy" -Do not generate mpy instructions for \s-1ARC700\s0. +Do not generate mpy instructions for \s-1ARC700.\s0 .IP "\fB\-mmul32x16\fR" 4 .IX Item "-mmul32x16" Generate 32x16 bit multiply and mac instructions. @@ -11535,7 +11756,7 @@ implementation. implementation. .IP "\fB\-msimd\fR" 4 .IX Item "-msimd" -Enable generation of \s-1ARC\s0 \s-1SIMD\s0 instructions via target-specific +Enable generation of \s-1ARC SIMD\s0 instructions via target-specific builtins. Only valid for \fB\-mcpu=ARC700\fR. .IP "\fB\-msoft\-float\fR" 4 .IX Item "-msoft-float" @@ -11702,7 +11923,7 @@ optimizers then assume that indexed stores exist, which is not the case. .IP "\fB\-mlra\fR" 4 .IX Item "-mlra" -Enable Local Register Allocation. This is still experimental for \s-1ARC\s0, +Enable Local Register Allocation. This is still experimental for \s-1ARC,\s0 so by default the compiler uses standard reload (i.e. \fB\-mno\-lra\fR). .IP "\fB\-mlra\-priority\-none\fR" 4 @@ -11808,7 +12029,7 @@ The following options are maintained for backward compatibility, but are now deprecated and will be removed in a future release: .IP "\fB\-margonaut\fR" 4 .IX Item "-margonaut" -Obsolete \s-1FPX\s0. +Obsolete \s-1FPX.\s0 .IP "\fB\-mbig\-endian\fR" 4 .IX Item "-mbig-endian" .PD 0 @@ -11871,7 +12092,7 @@ Replaced by \fB\-mmultcost\fR. These \fB\-m\fR options are defined for the \s-1ARM\s0 port: .IP "\fB\-mabi=\fR\fIname\fR" 4 .IX Item "-mabi=name" -Generate code for the specified \s-1ABI\s0. Permissible values are: \fBapcs-gnu\fR, +Generate code for the specified \s-1ABI. \s0 Permissible values are: \fBapcs-gnu\fR, \&\fBatpcs\fR, \fBaapcs\fR, \fBaapcs-linux\fR and \fBiwmmxt\fR. .IP "\fB\-mapcs\-frame\fR" 4 .IX Item "-mapcs-frame" @@ -11880,9 +12101,10 @@ Standard for all functions, even if this is not strictly necessary for correct execution of the code. Specifying \fB\-fomit\-frame\-pointer\fR with this option causes the stack frames not to be generated for leaf functions. The default is \fB\-mno\-apcs\-frame\fR. +This option is deprecated. .IP "\fB\-mapcs\fR" 4 .IX Item "-mapcs" -This is a synonym for \fB\-mapcs\-frame\fR. +This is a synonym for \fB\-mapcs\-frame\fR and is deprecated. .IP "\fB\-mthumb\-interwork\fR" 4 .IX Item "-mthumb-interwork" Generate code that supports calling between the \s-1ARM\s0 and Thumb @@ -11914,7 +12136,7 @@ and uses FPU-specific calling conventions. .Sp The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are not link-compatible; you must -compile your entire program with the same \s-1ABI\s0, and link with a +compile your entire program with the same \s-1ABI,\s0 and link with a compatible set of libraries. .IP "\fB\-mlittle\-endian\fR" 4 .IX Item "-mlittle-endian" @@ -11972,7 +12194,8 @@ Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBarm1136j\-s\fR, \fBarm1136jf\-s\fR, \fBmpcore\fR, \fBmpcorenovfp\fR, \&\fBarm1156t2\-s\fR, \fBarm1156t2f\-s\fR, \fBarm1176jz\-s\fR, \fBarm1176jzf\-s\fR, \&\fBcortex\-a5\fR, \fBcortex\-a7\fR, \fBcortex\-a8\fR, \fBcortex\-a9\fR, -\&\fBcortex\-a12\fR, \fBcortex\-a15\fR, \fBcortex\-a53\fR, \fBcortex\-a57\fR, +\&\fBcortex\-a12\fR, \fBcortex\-a15\fR, \fBcortex\-a53\fR, +\&\fBcortex\-a57\fR, \fBcortex\-a72\fR, \&\fBcortex\-r4\fR, \&\fBcortex\-r4f\fR, \fBcortex\-r5\fR, \fBcortex\-r7\fR, \fBcortex\-m7\fR, \&\fBcortex\-m4\fR, @@ -11983,14 +12206,17 @@ Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBcortex\-m1.small\-multiply\fR, \&\fBcortex\-m0.small\-multiply\fR, \&\fBcortex\-m0plus.small\-multiply\fR, +\&\fBexynos\-m1\fR, \&\fBmarvell\-pj4\fR, \&\fBxscale\fR, \fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR, \&\fBfa526\fR, \fBfa626\fR, -\&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR. +\&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR, +\&\fBxgene1\fR. .Sp Additionally, this option can specify that \s-1GCC\s0 should tune the performance of the code for a big.LITTLE system. Permissible names are: -\&\fBcortex\-a15.cortex\-a7\fR, \fBcortex\-a57.cortex\-a53\fR. +\&\fBcortex\-a15.cortex\-a7\fR, \fBcortex\-a57.cortex\-a53\fR, +\&\fBcortex\-a72.cortex\-a53\fR. .Sp \&\fB\-mtune=generic\-\fR\fIarch\fR specifies that \s-1GCC\s0 should tune the performance for a blend of processors within architecture \fIarch\fR. @@ -12040,7 +12266,7 @@ If the selected floating-point hardware includes the \s-1NEON\s0 extension (e.g. \fB\-mfpu\fR=\fBneon\fR), note that floating-point operations are not generated by \s-1GCC\s0's auto-vectorization pass unless \&\fB\-funsafe\-math\-optimizations\fR is also specified. This is -because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE\s0 754 standard for +because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE 754\s0 standard for floating-point arithmetic (in particular denormal values are treated as zero), so the use of \s-1NEON\s0 instructions may lead to a loss of precision. .IP "\fB\-mfp16\-format=\fR\fIname\fR" 4 @@ -12113,7 +12339,7 @@ otherwise the default is \fBR10\fR. .IX Item "-mpic-data-is-text-relative" Assume that each data segments are relative to text segment at load time. Therefore, it permits addressing data using PC-relative operations. -This option is on by default for targets other than VxWorks \s-1RTP\s0. +This option is on by default for targets other than VxWorks \s-1RTP.\s0 .IP "\fB\-mpoke\-function\-name\fR" 4 .IX Item "-mpoke-function-name" Write the name of each function into the text section, directly @@ -12237,13 +12463,19 @@ off by default. Assume inline assembler is using unified asm syntax. The default is currently off which implies divided syntax. Currently this option is available only for Thumb1 and has no effect on \s-1ARM\s0 state and Thumb2. -However, this may change in future releases of \s-1GCC\s0. Divided syntax +However, this may change in future releases of \s-1GCC. \s0 Divided syntax should be considered deprecated. .IP "\fB\-mrestrict\-it\fR" 4 .IX Item "-mrestrict-it" Restricts generation of \s-1IT\s0 blocks to conform to the rules of ARMv8. \&\s-1IT\s0 blocks can only contain a single 16\-bit instruction from a select set of instructions. This option is on by default for ARMv8 Thumb mode. +.IP "\fB\-mprint\-tune\-info\fR" 4 +.IX Item "-mprint-tune-info" +Print \s-1CPU\s0 tuning information as comment in assembler file. This is +an option used only for regression testing of the compiler and not +intended for ordinary use in compiling code. This option is disabled +by default. .PP \fI\s-1AVR\s0 Options\fR .IX Subsection "AVR Options" @@ -12300,37 +12532,37 @@ The default for this option is@tie{}\fBavr2\fR. .ie n .IP """avr6""" 4 .el .IP "\f(CWavr6\fR" 4 .IX Item "avr6" -\&\*(L"Enhanced\*(R" devices with 3\-byte \s-1PC\s0, i.e. with more than 128@tie{}KiB of program memory. +\&\*(L"Enhanced\*(R" devices with 3\-byte \s-1PC,\s0 i.e. with more than 128@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega256rfr2\*(C'\fR, \f(CW\*(C`atmega2560\*(C'\fR, \f(CW\*(C`atmega2561\*(C'\fR, \f(CW\*(C`atmega2564rfr2\*(C'\fR. .ie n .IP """avrxmega2""" 4 .el .IP "\f(CWavrxmega2\fR" 4 .IX Item "avrxmega2" -\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 8@tie{}KiB and up to 64@tie{}KiB of program memory. +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 8@tie{}KiB and up to 64@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega16a4\*(C'\fR, \f(CW\*(C`atxmega16a4u\*(C'\fR, \f(CW\*(C`atxmega16c4\*(C'\fR, \f(CW\*(C`atxmega16d4\*(C'\fR, \f(CW\*(C`atxmega16e5\*(C'\fR, \f(CW\*(C`atxmega32a4\*(C'\fR, \f(CW\*(C`atxmega32a4u\*(C'\fR, \f(CW\*(C`atxmega32c3\*(C'\fR, \f(CW\*(C`atxmega32c4\*(C'\fR, \f(CW\*(C`atxmega32d3\*(C'\fR, \f(CW\*(C`atxmega32d4\*(C'\fR, \f(CW\*(C`atxmega32e5\*(C'\fR, \f(CW\*(C`atxmega8e5\*(C'\fR. .ie n .IP """avrxmega4""" 4 .el .IP "\f(CWavrxmega4\fR" 4 .IX Item "avrxmega4" -\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory. +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a3\*(C'\fR, \f(CW\*(C`atxmega64a3u\*(C'\fR, \f(CW\*(C`atxmega64a4u\*(C'\fR, \f(CW\*(C`atxmega64b1\*(C'\fR, \f(CW\*(C`atxmega64b3\*(C'\fR, \f(CW\*(C`atxmega64c3\*(C'\fR, \f(CW\*(C`atxmega64d3\*(C'\fR, \f(CW\*(C`atxmega64d4\*(C'\fR. .ie n .IP """avrxmega5""" 4 .el .IP "\f(CWavrxmega5\fR" 4 .IX Item "avrxmega5" -\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM\s0. -\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR. +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM. +\&\s0\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR. .ie n .IP """avrxmega6""" 4 .el .IP "\f(CWavrxmega6\fR" 4 .IX Item "avrxmega6" -\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 128@tie{}KiB of program memory. +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a3\*(C'\fR, \f(CW\*(C`atxmega128a3u\*(C'\fR, \f(CW\*(C`atxmega128b1\*(C'\fR, \f(CW\*(C`atxmega128b3\*(C'\fR, \f(CW\*(C`atxmega128c3\*(C'\fR, \f(CW\*(C`atxmega128d3\*(C'\fR, \f(CW\*(C`atxmega128d4\*(C'\fR, \f(CW\*(C`atxmega192a3\*(C'\fR, \f(CW\*(C`atxmega192a3u\*(C'\fR, \f(CW\*(C`atxmega192c3\*(C'\fR, \f(CW\*(C`atxmega192d3\*(C'\fR, \f(CW\*(C`atxmega256a3\*(C'\fR, \f(CW\*(C`atxmega256a3b\*(C'\fR, \f(CW\*(C`atxmega256a3bu\*(C'\fR, \f(CW\*(C`atxmega256a3u\*(C'\fR, \f(CW\*(C`atxmega256c3\*(C'\fR, \f(CW\*(C`atxmega256d3\*(C'\fR, \f(CW\*(C`atxmega384c3\*(C'\fR, \f(CW\*(C`atxmega384d3\*(C'\fR. .ie n .IP """avrxmega7""" 4 .el .IP "\f(CWavrxmega7\fR" 4 .IX Item "avrxmega7" -\&\*(L"\s-1XMEGA\s0\*(R" devices with more than 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM\s0. -\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR, \f(CW\*(C`atxmega128a4u\*(C'\fR. +\&\*(L"\s-1XMEGA\*(R"\s0 devices with more than 128@tie{}KiB of program memory and more than 64@tie{}KiB of \s-1RAM. +\&\s0\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR, \f(CW\*(C`atxmega128a4u\*(C'\fR. .ie n .IP """avrtiny""" 4 .el .IP "\f(CWavrtiny\fR" 4 .IX Item "avrtiny" -\&\*(L"\s-1TINY\s0\*(R" Tiny core devices with 512@tie{}B up to 4@tie{}KiB of program memory. +\&\*(L"\s-1TINY\*(R"\s0 Tiny core devices with 512@tie{}B up to 4@tie{}KiB of program memory. \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`attiny10\*(C'\fR, \f(CW\*(C`attiny20\*(C'\fR, \f(CW\*(C`attiny4\*(C'\fR, \f(CW\*(C`attiny40\*(C'\fR, \f(CW\*(C`attiny5\*(C'\fR, \f(CW\*(C`attiny9\*(C'\fR. .ie n .IP """avr1""" 4 .el .IP "\f(CWavr1\fR" 4 @@ -12371,6 +12603,10 @@ Assume \f(CW\*(C`int\*(C'\fR to be 8\-bit integer. This affects the sizes of al and \f(CW\*(C`long long\*(C'\fR is 4 bytes. Please note that this option does not conform to the C standards, but it results in smaller code size. +.IP "\fB\-mn\-flash=\fR\fInum\fR" 4 +.IX Item "-mn-flash=num" +Assume that the flash memory has a size of +\&\fInum\fR times 64@tie{}KiB. .IP "\fB\-mno\-interrupts\fR" 4 .IX Item "-mno-interrupts" Generated code is not compatible with hardware interrupts. @@ -12379,8 +12615,9 @@ Code size is smaller. .IX Item "-mrelax" Try to replace \f(CW\*(C`CALL\*(C'\fR resp. \f(CW\*(C`JMP\*(C'\fR instruction by the shorter \&\f(CW\*(C`RCALL\*(C'\fR resp. \f(CW\*(C`RJMP\*(C'\fR instruction if applicable. -Setting \fB\-mrelax\fR just adds the \fB\-\-relax\fR option to the -linker command line when the linker is called. +Setting \fB\-mrelax\fR just adds the \fB\-\-mlink\-relax\fR option to +the assembler's command line and the \fB\-\-relax\fR option to the +linker's command line. .Sp Jump relaxing is performed by the linker because jump offsets are not known before code is located. Therefore, the assembler code generated by the @@ -12389,6 +12626,10 @@ differ from instructions in the assembler code. .Sp Relaxing must be turned on if linker stubs are needed, see the section on \f(CW\*(C`EIND\*(C'\fR and linker stubs below. +.IP "\fB\-mrmw\fR" 4 +.IX Item "-mrmw" +Assume that the device supports the Read-Modify-Write +instructions \f(CW\*(C`XCH\*(C'\fR, \f(CW\*(C`LAC\*(C'\fR, \f(CW\*(C`LAS\*(C'\fR and \f(CW\*(C`LAT\*(C'\fR. .IP "\fB\-msp8\fR" 4 .IX Item "-msp8" Treat the stack pointer register as an 8\-bit register, @@ -12424,13 +12665,16 @@ performed as .IP "\fB\-mtiny\-stack\fR" 4 .IX Item "-mtiny-stack" Only change the lower 8@tie{}bits of the stack pointer. +.IP "\fB\-nodevicelib\fR" 4 +.IX Item "-nodevicelib" +Don't link against AVR-LibC's device specific library \f(CW\*(C`libdev.a\*(C'\fR. .IP "\fB\-Waddr\-space\-convert\fR" 4 .IX Item "-Waddr-space-convert" Warn about conversions between address spaces in the case where the resulting address space is not contained in the incoming address space. .PP -\f(CW\*(C`EIND\*(C'\fR and Devices with more than 128 Ki Bytes of Flash -.IX Subsection "EIND and Devices with more than 128 Ki Bytes of Flash" +\f(CW\*(C`EIND\*(C'\fR and Devices with More Than 128 Ki Bytes of Flash +.IX Subsection "EIND and Devices with More Than 128 Ki Bytes of Flash" .PP Pointers in the implementation are 16@tie{}bits wide. The address of a function or label is represented as word address so @@ -12534,7 +12778,7 @@ command-line option. .IX Item "-" tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. .IP "\-" 4 -.IX Item "-" +.IX Item "-" .PD 0 .ie n .IP "\-" 4 .el .IP "\-" 4 @@ -12620,13 +12864,18 @@ architecture and depends on the \fB\-mmcu=\fR\fImcu\fR option. Possible values are: .Sp \&\f(CW2\fR, \f(CW25\fR, \f(CW3\fR, \f(CW31\fR, \f(CW35\fR, -\&\f(CW4\fR, \f(CW5\fR, \f(CW51\fR, \f(CW6\fR, \f(CW102\fR, \f(CW104\fR, +\&\f(CW4\fR, \f(CW5\fR, \f(CW51\fR, \f(CW6\fR +.Sp +for \fImcu\fR=\f(CW\*(C`avr2\*(C'\fR, \f(CW\*(C`avr25\*(C'\fR, \f(CW\*(C`avr3\*(C'\fR, \f(CW\*(C`avr31\*(C'\fR, +\&\f(CW\*(C`avr35\*(C'\fR, \f(CW\*(C`avr4\*(C'\fR, \f(CW\*(C`avr5\*(C'\fR, \f(CW\*(C`avr51\*(C'\fR, \f(CW\*(C`avr6\*(C'\fR, +.Sp +respectively and +.Sp +\&\f(CW100\fR, \f(CW102\fR, \f(CW104\fR, \&\f(CW105\fR, \f(CW106\fR, \f(CW107\fR .Sp -for \fImcu\fR=\f(CW\*(C`avr2\*(C'\fR, \f(CW\*(C`avr25\*(C'\fR, \f(CW\*(C`avr3\*(C'\fR, -\&\f(CW\*(C`avr31\*(C'\fR, \f(CW\*(C`avr35\*(C'\fR, \f(CW\*(C`avr4\*(C'\fR, \f(CW\*(C`avr5\*(C'\fR, \f(CW\*(C`avr51\*(C'\fR, -\&\f(CW\*(C`avr6\*(C'\fR, \f(CW\*(C`avrxmega2\*(C'\fR, \f(CW\*(C`avrxmega4\*(C'\fR, \f(CW\*(C`avrxmega5\*(C'\fR, -\&\f(CW\*(C`avrxmega6\*(C'\fR, \f(CW\*(C`avrxmega7\*(C'\fR, respectively. +for \fImcu\fR=\f(CW\*(C`avrtiny\*(C'\fR, \f(CW\*(C`avrxmega2\*(C'\fR, \f(CW\*(C`avrxmega4\*(C'\fR, +\&\f(CW\*(C`avrxmega5\*(C'\fR, \f(CW\*(C`avrxmega6\*(C'\fR, \f(CW\*(C`avrxmega7\*(C'\fR, respectively. If \fImcu\fR specifies a device, this built-in macro is set accordingly. For example, with \fB\-mmcu=atmega8\fR the macro is defined to \f(CW4\fR. @@ -12724,7 +12973,7 @@ The definition of these macros is affected by \fB\-mtiny\-stack\fR. .el .IP "\f(CW_\|_AVR_SP8_\|_\fR" 4 .IX Item "__AVR_SP8__" .PD -The device has the \s-1SPH\s0 (high part of stack pointer) special function +The device has the \s-1SPH \s0(high part of stack pointer) special function register or has an 8\-bit stack pointer, respectively. The definition of these macros is affected by \fB\-mmcu=\fR and in the cases of \fB\-mmcu=avr2\fR and \fB\-mmcu=avr25\fR also @@ -12748,7 +12997,7 @@ The device has the \f(CW\*(C`RAMPD\*(C'\fR, \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`R .ie n .IP """_\|_NO_INTERRUPTS_\|_""" 4 .el .IP "\f(CW_\|_NO_INTERRUPTS_\|_\fR" 4 .IX Item "__NO_INTERRUPTS__" -This macro reflects the \fB\-mno\-interrupts\fR command line option. +This macro reflects the \fB\-mno\-interrupts\fR command-line option. .ie n .IP """_\|_AVR_ERRATA_SKIP_\|_""" 4 .el .IP "\f(CW_\|_AVR_ERRATA_SKIP_\|_\fR" 4 .IX Item "__AVR_ERRATA_SKIP__" @@ -12757,7 +13006,7 @@ This macro reflects the \fB\-mno\-interrupts\fR command line option. .el .IP "\f(CW_\|_AVR_ERRATA_SKIP_JMP_CALL_\|_\fR" 4 .IX Item "__AVR_ERRATA_SKIP_JMP_CALL__" .PD -Some \s-1AVR\s0 devices (\s-1AT90S8515\s0, ATmega103) must not skip 32\-bit +Some \s-1AVR\s0 devices (\s-1AT90S8515,\s0 ATmega103) must not skip 32\-bit instructions because of a hardware erratum. Skip instructions are \&\f(CW\*(C`SBRS\*(C'\fR, \f(CW\*(C`SBRC\*(C'\fR, \f(CW\*(C`SBIS\*(C'\fR, \f(CW\*(C`SBIC\*(C'\fR and \f(CW\*(C`CPSE\*(C'\fR. The second macro is only defined if \f(CW\*(C`_\|_AVR_HAVE_JMP_CALL_\|_\*(C'\fR is also @@ -12765,7 +13014,7 @@ set. .ie n .IP """_\|_AVR_ISA_RMW_\|_""" 4 .el .IP "\f(CW_\|_AVR_ISA_RMW_\|_\fR" 4 .IX Item "__AVR_ISA_RMW__" -The device has Read-Modify-Write instructions (\s-1XCH\s0, \s-1LAC\s0, \s-1LAS\s0 and \s-1LAT\s0). +The device has Read-Modify-Write instructions (\s-1XCH, LAC, LAS\s0 and \s-1LAT\s0). .ie n .IP """_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW""" 4 .el .IP "\f(CW_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW\fR" 4 .IX Item "__AVR_SFR_OFFSET__=offset" @@ -12949,8 +13198,8 @@ should be used instead of \f(CW\*(C`main\*(C'\fR. This option can only be used in conjunction with \fB\-mmulticore\fR. .IP "\fB\-msdram\fR" 4 .IX Item "-msdram" -Build a standalone application for \s-1SDRAM\s0. Proper start files and -link scripts are used to put the application into \s-1SDRAM\s0, and the macro +Build a standalone application for \s-1SDRAM.\s0 Proper start files and +link scripts are used to put the application into \s-1SDRAM,\s0 and the macro \&\f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR is defined. The loader should initialize \s-1SDRAM\s0 before loading the application. .IP "\fB\-micplb\fR" 4 @@ -13009,7 +13258,7 @@ These options are defined specifically for the \s-1CRIS\s0 ports. .PD Generate code for the specified architecture. The choices for \&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for -respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0. +respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX.\s0 Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is \&\fBv10\fR. .IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4 @@ -13102,7 +13351,7 @@ or storage for local variables needs to be allocated. With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate) instruction sequences that load addresses for functions from the \s-1PLT\s0 part of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the -\&\s-1PLT\s0. The default is \fB\-mgotplt\fR. +\&\s-1PLT. \s0 The default is \fB\-mgotplt\fR. .IP "\fB\-melf\fR" 4 .IX Item "-melf" Legacy no-op option only recognized with the cris-axis-elf and @@ -13158,7 +13407,7 @@ However, \fBfar\fR is not valid with \fB\-mcr16c\fR, as the These options are defined for all architectures running the Darwin operating system. .PP -\&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it creates +\&\s-1FSF GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it creates an object file for the single architecture that \s-1GCC\s0 was built to target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple \&\fB\-arch\fR options are used; it does so by running the compiler or @@ -13218,7 +13467,7 @@ warn about constructs contained within header files found via .IX Item "-gused" Emit debugging information for symbols that are used. For stabs debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR. -This is by default \s-1ON\s0. +This is by default \s-1ON.\s0 .IP "\fB\-gfull\fR" 4 .IX Item "-gfull" Emit debugging information for all symbols and types. @@ -13294,7 +13543,7 @@ an executable when linking, using the Darwin \fIlibtool\fR command. This causes \s-1GCC\s0's output file to have the \fB\s-1ALL\s0\fR subtype, instead of one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. .IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 -.IX Item "-allowable_client client_name" +.IX Item "-allowable_client client_name" .PD 0 .IP "\fB\-client_name\fR" 4 .IX Item "-client_name" @@ -13468,7 +13717,7 @@ compilers call this option \fB\-ieee_with_no_inexact\fR. .IP "\fB\-mieee\-with\-inexact\fR" 4 .IX Item "-mieee-with-inexact" This is like \fB\-mieee\fR except the generated code also maintains -the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the +the \s-1IEEE \s0\fIinexact-flag\fR. Turning on this option causes the generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to \&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor macro. On some Alpha implementations the resulting code may execute @@ -13594,8 +13843,8 @@ before it can find the variables and constants in its own data segment. .IP "\fB\-mno\-max\fR" 4 .IX Item "-mno-max" .PD -Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0, -\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction +Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX, +CIX, FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none is specified. .IP "\fB\-mfloat\-vax\fR" 4 @@ -13604,7 +13853,7 @@ of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none is specified. .IP "\fB\-mfloat\-ieee\fR" 4 .IX Item "-mfloat-ieee" .PD -Generate code that uses (does not use) \s-1VAX\s0 F and G floating-point +Generate code that uses (does not use) \s-1VAX F\s0 and G floating-point arithmetic instead of \s-1IEEE\s0 single and double precision. .IP "\fB\-mexplicit\-relocs\fR" 4 .IX Item "-mexplicit-relocs" @@ -13659,7 +13908,7 @@ The default is \fB\-mlarge\-text\fR. Set the instruction set and instruction scheduling parameters for machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR style name or the corresponding chip number. \s-1GCC\s0 supports scheduling -parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and +parameters for the \s-1EV4, EV5\s0 and \s-1EV6\s0 family of processors and chooses the default values for the instruction set from the processor you specify. If you do not specify a processor type, \s-1GCC\s0 defaults to the processor on which the compiler was built. @@ -13704,14 +13953,14 @@ Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions .IP "\fB21264\fR" 4 .IX Item "21264" .PD -Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. +Schedules as an \s-1EV6\s0 and supports the \s-1BWX, FIX,\s0 and \s-1MAX\s0 extensions. .IP "\fBev67\fR" 4 .IX Item "ev67" .PD 0 .IP "\fB21264a\fR" 4 .IX Item "21264a" .PD -Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. +Schedules as an \s-1EV6\s0 and supports the \s-1BWX, CIX, FIX,\s0 and \s-1MAX\s0 extensions. .RE .RS 4 .Sp @@ -13752,9 +14001,9 @@ A decimal number representing clock cycles. .IX Item "main" .PD The compiler contains estimates of the number of clock cycles for -\&\*(L"typical\*(R" \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches +\&\*(L"typical\*(R" \s-1EV4 & EV5\s0 hardware for the Level 1, 2 & 3 caches (also called Dcache, Scache, and Bcache), as well as to main memory. -Note that L3 is only valid for \s-1EV5\s0. +Note that L3 is only valid for \s-1EV5.\s0 .RE .RS 4 .RE @@ -13827,7 +14076,7 @@ Use multiply and add/subtract instructions. Do not use multiply and add/subtract instructions. .IP "\fB\-mfdpic\fR" 4 .IX Item "-mfdpic" -Select the \s-1FDPIC\s0 \s-1ABI\s0, which uses function descriptors to represent +Select the \s-1FDPIC ABI,\s0 which uses function descriptors to represent pointers to functions. Without any PIC/PIE\-related options, it implies \fB\-fPIE\fR. With \fB\-fpic\fR or \fB\-fpie\fR, it assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the @@ -13850,7 +14099,7 @@ Assume a large \s-1TLS\s0 segment when generating thread-local code. Do not assume a large \s-1TLS\s0 segment when generating thread-local code. .IP "\fB\-mgprel\-ro\fR" 4 .IX Item "-mgprel-ro" -Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC\s0 \s-1ABI\s0 for data +Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC ABI\s0 for data that is known to be in read-only sections. It's enabled by default, except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help make the global offset table smaller, it trades 1 instruction for 4. @@ -13994,7 +14243,7 @@ Select the processor type for which to generate code. Possible values are These \fB\-m\fR options are defined for GNU/Linux targets: .IP "\fB\-mglibc\fR" 4 .IX Item "-mglibc" -Use the \s-1GNU\s0 C library. This is the default except +Use the \s-1GNU C\s0 library. This is the default except on \fB*\-*\-linux\-*uclibc*\fR and \fB*\-*\-linux\-*android*\fR targets. .IP "\fB\-muclibc\fR" 4 .IX Item "-muclibc" @@ -14073,8 +14322,8 @@ These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers: .IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 .IX Item "-march=architecture-type" Generate code for the specified architecture. The choices for -\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0 -1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors. Refer to +\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA 1.0, \s0\fB1.1\fR for \s-1PA +1.1,\s0 and \fB2.0\fR for \s-1PA 2.0\s0 processors. Refer to \&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper architecture option for your machine. Code compiled for lower numbered architectures runs on higher numbered architectures, but not the @@ -14100,7 +14349,7 @@ floating-point operations, the compiler aborts. .IP "\fB\-mdisable\-indexing\fR" 4 .IX Item "-mdisable-indexing" Prevent the compiler from using indexing address modes. This avoids some -rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0. +rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH.\s0 .IP "\fB\-mno\-space\-regs\fR" 4 .IX Item "-mno-space-regs" Generate code that assumes the target has no space registers. This allows @@ -14157,17 +14406,17 @@ cross-compilation. \&\fB\-msoft\-float\fR changes the calling convention in the output file; therefore, it is only useful if you compile \fIall\fR of a program with this option. In particular, you need to compile \fIlibgcc.a\fR, the -library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for +library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for this to work. .IP "\fB\-msio\fR" 4 .IX Item "-msio" -Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO\s0. The default is +Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO. \s0 The default is \&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR, -\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO\s0. These +\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO. \s0 These options are available under HP-UX and HI-UX. .IP "\fB\-mgnu\-ld\fR" 4 .IX Item "-mgnu-ld" -Use options specific to \s-1GNU\s0 \fBld\fR. +Use options specific to \s-1GNU \s0\fBld\fR. This passes \fB\-shared\fR to \fBld\fR when building a shared library. It is the default when \s-1GCC\s0 is configured, explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not @@ -14177,10 +14426,10 @@ The \fBld\fR that is called is determined by the \&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available -on the 64\-bit HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +on the 64\-bit HP-UX \s-1GCC,\s0 i.e. configured with \fBhppa*64*\-*\-hpux*\fR. .IP "\fB\-mhp\-ld\fR" 4 .IX Item "-mhp-ld" -Use options specific to \s-1HP\s0 \fBld\fR. +Use options specific to \s-1HP \s0\fBld\fR. This passes \fB\-b\fR to \fBld\fR when building a shared library and passes \fB+Accept TypeMismatch\fR to \fBld\fR on all links. It is the default when \s-1GCC\s0 is configured, explicitly or @@ -14191,7 +14440,7 @@ The \fBld\fR that is called is determined by the \fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and finally by the user's \&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64\-bit -HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. +HP-UX \s-1GCC,\s0 i.e. configured with \fBhppa*64*\-*\-hpux*\fR. .IP "\fB\-mlong\-calls\fR" 4 .IX Item "-mlong-calls" Generate code that uses long call sequences. This ensures that a call @@ -14200,7 +14449,7 @@ long calls only when the distance from the call site to the beginning of the function or translation unit, as the case may be, exceeds a predefined limit set by the branch type being used. The limits for normal calls are 7,600,000 and 240,000 bytes, respectively for the -\&\s-1PA\s0 2.0 and \s-1PA\s0 1.X architectures. Sibcalls are always limited at +\&\s-1PA 2.0\s0 and \s-1PA 1.X\s0 architectures. Sibcalls are always limited at 240,000 bytes. .Sp Distances are measured from the beginning of functions when using the @@ -14228,7 +14477,7 @@ is available on HP-UX 10.10 and later. \fB98\fR is available on HP-UX \&\fB95\fR for HP-UX 10.10 though to 11.00, and \fB98\fR for HP-UX 11.11 and later. .Sp -\&\fB\-munix=93\fR provides the same predefines as \s-1GCC\s0 3.3 and 3.4. +\&\fB\-munix=93\fR provides the same predefines as \s-1GCC 3.3\s0 and 3.4. \&\fB\-munix=95\fR provides additional predefines for \f(CW\*(C`XOPEN_UNIX\*(C'\fR and \f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, and the startfile \fIunix95.o\fR. \&\fB\-munix=98\fR provides additional predefines for \f(CW\*(C`_XOPEN_UNIX\*(C'\fR, @@ -14266,1393 +14515,197 @@ Add support for multithreading with the \fIdce thread\fR library under HP-UX. This option sets flags for both the preprocessor and linker. .PP -\fIIntel 386 and \s-1AMD\s0 x86\-64 Options\fR -.IX Subsection "Intel 386 and AMD x86-64 Options" +\fI\s-1IA\-64\s0 Options\fR +.IX Subsection "IA-64 Options" .PP -These \fB\-m\fR options are defined for the i386 and x86\-64 family of -computers: -.IP "\fB\-march=\fR\fIcpu-type\fR" 4 -.IX Item "-march=cpu-type" -Generate instructions for the machine type \fIcpu-type\fR. In contrast to -\&\fB\-mtune=\fR\fIcpu-type\fR, which merely tunes the generated code -for the specified \fIcpu-type\fR, \fB\-march=\fR\fIcpu-type\fR allows \s-1GCC\s0 -to generate code that may not run at all on processors other than the one -indicated. Specifying \fB\-march=\fR\fIcpu-type\fR implies -\&\fB\-mtune=\fR\fIcpu-type\fR. -.Sp -The choices for \fIcpu-type\fR are: -.RS 4 -.IP "\fBnative\fR" 4 -.IX Item "native" -This selects the \s-1CPU\s0 to generate code for at compilation time by determining -the processor type of the compiling machine. Using \fB\-march=native\fR -enables all instruction subsets supported by the local machine (hence -the result might not run on different machines). Using \fB\-mtune=native\fR -produces code optimized for the local machine under the constraints -of the selected instruction set. -.IP "\fBi386\fR" 4 -.IX Item "i386" -Original Intel i386 \s-1CPU\s0. -.IP "\fBi486\fR" 4 -.IX Item "i486" -Intel i486 \s-1CPU\s0. (No scheduling is implemented for this chip.) -.IP "\fBi586\fR" 4 -.IX Item "i586" -.PD 0 -.IP "\fBpentium\fR" 4 -.IX Item "pentium" -.PD -Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support. -.IP "\fBpentium-mmx\fR" 4 -.IX Item "pentium-mmx" -Intel Pentium \s-1MMX\s0 \s-1CPU\s0, based on Pentium core with \s-1MMX\s0 instruction set support. -.IP "\fBpentiumpro\fR" 4 -.IX Item "pentiumpro" -Intel Pentium Pro \s-1CPU\s0. -.IP "\fBi686\fR" 4 -.IX Item "i686" -When used with \fB\-march\fR, the Pentium Pro -instruction set is used, so the code runs on all i686 family chips. -When used with \fB\-mtune\fR, it has the same meaning as \fBgeneric\fR. -.IP "\fBpentium2\fR" 4 -.IX Item "pentium2" -Intel Pentium \s-1II\s0 \s-1CPU\s0, based on Pentium Pro core with \s-1MMX\s0 instruction set -support. -.IP "\fBpentium3\fR" 4 -.IX Item "pentium3" +These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" +Generate code for a big-endian target. This is the default for HP-UX. +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" +Generate code for a little-endian target. This is the default for \s-1AIX5\s0 +and GNU/Linux. +.IP "\fB\-mgnu\-as\fR" 4 +.IX Item "-mgnu-as" .PD 0 -.IP "\fBpentium3m\fR" 4 -.IX Item "pentium3m" +.IP "\fB\-mno\-gnu\-as\fR" 4 +.IX Item "-mno-gnu-as" .PD -Intel Pentium \s-1III\s0 \s-1CPU\s0, based on Pentium Pro core with \s-1MMX\s0 and \s-1SSE\s0 instruction -set support. -.IP "\fBpentium-m\fR" 4 -.IX Item "pentium-m" -Intel Pentium M; low-power version of Intel Pentium \s-1III\s0 \s-1CPU\s0 -with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support. Used by Centrino notebooks. -.IP "\fBpentium4\fR" 4 -.IX Item "pentium4" +Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default. +.IP "\fB\-mgnu\-ld\fR" 4 +.IX Item "-mgnu-ld" .PD 0 -.IP "\fBpentium4m\fR" 4 -.IX Item "pentium4m" +.IP "\fB\-mno\-gnu\-ld\fR" 4 +.IX Item "-mno-gnu-ld" .PD -Intel Pentium 4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support. -.IP "\fBprescott\fR" 4 -.IX Item "prescott" -Improved version of Intel Pentium 4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction -set support. -.IP "\fBnocona\fR" 4 -.IX Item "nocona" -Improved version of Intel Pentium 4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, -\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. -.IP "\fBcore2\fR" 4 -.IX Item "core2" -Intel Core 2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 -instruction set support. -.IP "\fBnehalem\fR" 4 -.IX Item "nehalem" -Intel Nehalem \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, -\&\s-1SSE4\s0.1, \s-1SSE4\s0.2 and \s-1POPCNT\s0 instruction set support. -.IP "\fBwestmere\fR" 4 -.IX Item "westmere" -Intel Westmere \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, -\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AES\s0 and \s-1PCLMUL\s0 instruction set support. -.IP "\fBsandybridge\fR" 4 -.IX Item "sandybridge" -Intel Sandy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, -\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AES\s0 and \s-1PCLMUL\s0 instruction set support. -.IP "\fBivybridge\fR" 4 -.IX Item "ivybridge" -Intel Ivy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, -\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C -instruction set support. -.IP "\fBhaswell\fR" 4 -.IX Item "haswell" -Intel Haswell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, -\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, -\&\s-1BMI\s0, \s-1BMI2\s0 and F16C instruction set support. -.IP "\fBbroadwell\fR" 4 -.IX Item "broadwell" -Intel Broadwell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, -\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, -\&\s-1BMI\s0, \s-1BMI2\s0, F16C, \s-1RDSEED\s0, \s-1ADCX\s0 and \s-1PREFETCHW\s0 instruction set support. -.IP "\fBbonnell\fR" 4 -.IX Item "bonnell" -Intel Bonnell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 -instruction set support. -.IP "\fBsilvermont\fR" 4 -.IX Item "silvermont" -Intel Silvermont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, -\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1POPCNT\s0, \s-1AES\s0, \s-1PCLMUL\s0 and \s-1RDRND\s0 instruction set support. -.IP "\fBk6\fR" 4 -.IX Item "k6" -\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support. -.IP "\fBk6\-2\fR" 4 -.IX Item "k6-2" +Generate (or don't) code for the \s-1GNU\s0 linker. This is the default. +.IP "\fB\-mno\-pic\fR" 4 +.IX Item "-mno-pic" +Generate code that does not use a global pointer register. The result +is not position independent code, and violates the \s-1IA\-64 ABI.\s0 +.IP "\fB\-mvolatile\-asm\-stop\fR" 4 +.IX Item "-mvolatile-asm-stop" .PD 0 -.IP "\fBk6\-3\fR" 4 -.IX Item "k6-3" +.IP "\fB\-mno\-volatile\-asm\-stop\fR" 4 +.IX Item "-mno-volatile-asm-stop" .PD -Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. -.IP "\fBathlon\fR" 4 -.IX Item "athlon" +Generate (or don't) a stop bit immediately before and after volatile asm +statements. +.IP "\fB\-mregister\-names\fR" 4 +.IX Item "-mregister-names" .PD 0 -.IP "\fBathlon-tbird\fR" 4 -.IX Item "athlon-tbird" +.IP "\fB\-mno\-register\-names\fR" 4 +.IX Item "-mno-register-names" .PD -\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions -support. -.IP "\fBathlon\-4\fR" 4 -.IX Item "athlon-4" +Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for +the stacked registers. This may make assembler output more readable. +.IP "\fB\-mno\-sdata\fR" 4 +.IX Item "-mno-sdata" .PD 0 -.IP "\fBathlon-xp\fR" 4 -.IX Item "athlon-xp" -.IP "\fBathlon-mp\fR" 4 -.IX Item "athlon-mp" +.IP "\fB\-msdata\fR" 4 +.IX Item "-msdata" .PD -Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3DNow!, enhanced 3DNow! and full \s-1SSE\s0 -instruction set support. -.IP "\fBk8\fR" 4 -.IX Item "k8" +Disable (or enable) optimizations that use the small data section. This may +be useful for working around optimizer bugs. +.IP "\fB\-mconstant\-gp\fR" 4 +.IX Item "-mconstant-gp" +Generate code that uses a single constant global pointer value. This is +useful when compiling kernel code. +.IP "\fB\-mauto\-pic\fR" 4 +.IX Item "-mauto-pic" +Generate code that is self-relocatable. This implies \fB\-mconstant\-gp\fR. +This is useful when compiling firmware code. +.IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4 +.IX Item "-minline-float-divide-min-latency" +Generate code for inline divides of floating-point values +using the minimum latency algorithm. +.IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-float-divide-max-throughput" +Generate code for inline divides of floating-point values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-float\-divide\fR" 4 +.IX Item "-mno-inline-float-divide" +Do not generate inline code for divides of floating-point values. +.IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4 +.IX Item "-minline-int-divide-min-latency" +Generate code for inline divides of integer values +using the minimum latency algorithm. +.IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4 +.IX Item "-minline-int-divide-max-throughput" +Generate code for inline divides of integer values +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-int\-divide\fR" 4 +.IX Item "-mno-inline-int-divide" +Do not generate inline code for divides of integer values. +.IP "\fB\-minline\-sqrt\-min\-latency\fR" 4 +.IX Item "-minline-sqrt-min-latency" +Generate code for inline square roots +using the minimum latency algorithm. +.IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4 +.IX Item "-minline-sqrt-max-throughput" +Generate code for inline square roots +using the maximum throughput algorithm. +.IP "\fB\-mno\-inline\-sqrt\fR" 4 +.IX Item "-mno-inline-sqrt" +Do not generate inline code for \f(CW\*(C`sqrt\*(C'\fR. +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" .PD 0 -.IP "\fBopteron\fR" 4 -.IX Item "opteron" -.IP "\fBathlon64\fR" 4 -.IX Item "athlon64" -.IP "\fBathlon-fx\fR" 4 -.IX Item "athlon-fx" +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" .PD -Processors based on the \s-1AMD\s0 K8 core with x86\-64 instruction set support, -including the \s-1AMD\s0 Opteron, Athlon 64, and Athlon 64 \s-1FX\s0 processors. -(This supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3DNow!, enhanced 3DNow! and 64\-bit -instruction set extensions.) -.IP "\fBk8\-sse3\fR" 4 -.IX Item "k8-sse3" +Do (don't) generate code that uses the fused multiply/add or multiply/subtract +instructions. The default is to use these instructions. +.IP "\fB\-mno\-dwarf2\-asm\fR" 4 +.IX Item "-mno-dwarf2-asm" .PD 0 -.IP "\fBopteron\-sse3\fR" 4 -.IX Item "opteron-sse3" -.IP "\fBathlon64\-sse3\fR" 4 -.IX Item "athlon64-sse3" +.IP "\fB\-mdwarf2\-asm\fR" 4 +.IX Item "-mdwarf2-asm" .PD -Improved versions of \s-1AMD\s0 K8 cores with \s-1SSE3\s0 instruction set support. -.IP "\fBamdfam10\fR" 4 -.IX Item "amdfam10" +Don't (or do) generate assembler code for the \s-1DWARF 2\s0 line number debugging +info. This may be useful when not using the \s-1GNU\s0 assembler. +.IP "\fB\-mearly\-stop\-bits\fR" 4 +.IX Item "-mearly-stop-bits" .PD 0 -.IP "\fBbarcelona\fR" 4 -.IX Item "barcelona" +.IP "\fB\-mno\-early\-stop\-bits\fR" 4 +.IX Item "-mno-early-stop-bits" .PD -CPUs based on \s-1AMD\s0 Family 10h cores with x86\-64 instruction set support. (This -supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit -instruction set extensions.) -.IP "\fBbdver1\fR" 4 -.IX Item "bdver1" -CPUs based on \s-1AMD\s0 Family 15h cores with x86\-64 instruction set support. (This -supersets \s-1FMA4\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, -\&\s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set extensions.) -.IP "\fBbdver2\fR" 4 -.IX Item "bdver2" -\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This -supersets \s-1BMI\s0, \s-1TBM\s0, F16C, \s-1FMA\s0, \s-1FMA4\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, -\&\s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set -extensions.) -.IP "\fBbdver3\fR" 4 -.IX Item "bdver3" -\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This -supersets \s-1BMI\s0, \s-1TBM\s0, F16C, \s-1FMA\s0, \s-1FMA4\s0, \s-1FSGSBASE\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, -\&\s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and -64\-bit instruction set extensions. -.IP "\fBbdver4\fR" 4 -.IX Item "bdver4" -\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This -supersets \s-1BMI\s0, \s-1BMI2\s0, \s-1TBM\s0, F16C, \s-1FMA\s0, \s-1FMA4\s0, \s-1FSGSBASE\s0, \s-1AVX\s0, \s-1AVX2\s0, \s-1XOP\s0, \s-1LWP\s0, -\&\s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, -\&\s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set extensions. -.IP "\fBbtver1\fR" 4 -.IX Item "btver1" -CPUs based on \s-1AMD\s0 Family 14h cores with x86\-64 instruction set support. (This -supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4A\s0, \s-1CX16\s0, \s-1ABM\s0 and 64\-bit -instruction set extensions.) -.IP "\fBbtver2\fR" 4 -.IX Item "btver2" -CPUs based on \s-1AMD\s0 Family 16h cores with x86\-64 instruction set support. This -includes \s-1MOVBE\s0, F16C, \s-1BMI\s0, \s-1AVX\s0, \s-1PCL_MUL\s0, \s-1AES\s0, \s-1SSE4\s0.2, \s-1SSE4\s0.1, \s-1CX16\s0, \s-1ABM\s0, -\&\s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE3\s0, \s-1SSE2\s0, \s-1SSE\s0, \s-1MMX\s0 and 64\-bit instruction set extensions. -.IP "\fBwinchip\-c6\fR" 4 -.IX Item "winchip-c6" -\&\s-1IDT\s0 WinChip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction -set support. -.IP "\fBwinchip2\fR" 4 -.IX Item "winchip2" -\&\s-1IDT\s0 WinChip 2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow! -instruction set support. -.IP "\fBc3\fR" 4 -.IX Item "c3" -\&\s-1VIA\s0 C3 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. (No scheduling is -implemented for this chip.) -.IP "\fBc3\-2\fR" 4 -.IX Item "c3-2" -\&\s-1VIA\s0 C3\-2 (Nehemiah/C5XL) \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. -(No scheduling is -implemented for this chip.) -.IP "\fBgeode\fR" 4 -.IX Item "geode" -\&\s-1AMD\s0 Geode embedded processor with \s-1MMX\s0 and 3DNow! instruction set support. -.RE -.RS 4 -.RE +Allow stop bits to be placed earlier than immediately preceding the +instruction that triggered the stop bit. This can improve instruction +scheduling, but does not always do so. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4 +.IX Item "-mtls-size=tls-size" +Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and +64. .IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 .IX Item "-mtune=cpu-type" -Tune to \fIcpu-type\fR everything applicable about the generated code, except -for the \s-1ABI\s0 and the set of available instructions. -While picking a specific \fIcpu-type\fR schedules things appropriately -for that particular chip, the compiler does not generate any code that -cannot run on the default machine type unless you use a -\&\fB\-march=\fR\fIcpu-type\fR option. -For example, if \s-1GCC\s0 is configured for i686\-pc\-linux\-gnu -then \fB\-mtune=pentium4\fR generates code that is tuned for Pentium 4 -but still runs on i686 machines. -.Sp -The choices for \fIcpu-type\fR are the same as for \fB\-march\fR. -In addition, \fB\-mtune\fR supports 2 extra choices for \fIcpu-type\fR: -.RS 4 -.IP "\fBgeneric\fR" 4 -.IX Item "generic" -Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors. -If you know the \s-1CPU\s0 on which your code will run, then you should use -the corresponding \fB\-mtune\fR or \fB\-march\fR option instead of -\&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users -of your application will have, then you should use this option. -.Sp -As new processors are deployed in the marketplace, the behavior of this -option will change. Therefore, if you upgrade to a newer version of -\&\s-1GCC\s0, code generation controlled by this option will change to reflect -the processors -that are most common at the time that version of \s-1GCC\s0 is released. -.Sp -There is no \fB\-march=generic\fR option because \fB\-march\fR -indicates the instruction set the compiler can use, and there is no -generic instruction set applicable to all processors. In contrast, -\&\fB\-mtune\fR indicates the processor (or, in this case, collection of -processors) for which the code is optimized. -.IP "\fBintel\fR" 4 -.IX Item "intel" -Produce code optimized for the most current Intel processors, which are -Haswell and Silvermont for this version of \s-1GCC\s0. If you know the \s-1CPU\s0 -on which your code will run, then you should use the corresponding -\&\fB\-mtune\fR or \fB\-march\fR option instead of \fB\-mtune=intel\fR. -But, if you want your application performs better on both Haswell and -Silvermont, then you should use this option. -.Sp -As new Intel processors are deployed in the marketplace, the behavior of -this option will change. Therefore, if you upgrade to a newer version of -\&\s-1GCC\s0, code generation controlled by this option will change to reflect -the most current Intel processors at the time that version of \s-1GCC\s0 is -released. -.Sp -There is no \fB\-march=intel\fR option because \fB\-march\fR indicates -the instruction set the compiler can use, and there is no common -instruction set applicable to all processors. In contrast, -\&\fB\-mtune\fR indicates the processor (or, in this case, collection of -processors) for which the code is optimized. -.RE -.RS 4 -.RE -.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 -.IX Item "-mcpu=cpu-type" -A deprecated synonym for \fB\-mtune\fR. -.IP "\fB\-mfpmath=\fR\fIunit\fR" 4 -.IX Item "-mfpmath=unit" -Generate floating-point arithmetic for selected unit \fIunit\fR. The choices -for \fIunit\fR are: -.RS 4 -.IP "\fB387\fR" 4 -.IX Item "387" -Use the standard 387 floating-point coprocessor present on the majority of chips and -emulated otherwise. Code compiled with this option runs almost everywhere. -The temporary results are computed in 80\-bit precision instead of the precision -specified by the type, resulting in slightly different results compared to most -of other chips. See \fB\-ffloat\-store\fR for more detailed description. -.Sp -This is the default choice for i386 compiler. -.IP "\fBsse\fR" 4 -.IX Item "sse" -Use scalar floating-point instructions present in the \s-1SSE\s0 instruction set. -This instruction set is supported by Pentium \s-1III\s0 and newer chips, -and in the \s-1AMD\s0 line -by Athlon\-4, Athlon \s-1XP\s0 and Athlon \s-1MP\s0 chips. The earlier version of the \s-1SSE\s0 -instruction set supports only single-precision arithmetic, thus the double and -extended-precision arithmetic are still done using 387. A later version, present -only in Pentium 4 and \s-1AMD\s0 x86\-64 chips, supports double-precision -arithmetic too. -.Sp -For the i386 compiler, you must use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR -or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option -effective. For the x86\-64 compiler, these extensions are enabled by default. -.Sp -The resulting code should be considerably faster in the majority of cases and avoid -the numerical instability problems of 387 code, but may break some existing -code that expects temporaries to be 80 bits. -.Sp -This is the default choice for the x86\-64 compiler. -.IP "\fBsse,387\fR" 4 -.IX Item "sse,387" +Tune the instruction scheduling for a particular \s-1CPU,\s0 Valid values are +\&\fBitanium\fR, \fBitanium1\fR, \fBmerced\fR, \fBitanium2\fR, +and \fBmckinley\fR. +.IP "\fB\-milp32\fR" 4 +.IX Item "-milp32" .PD 0 -.IP "\fBsse+387\fR" 4 -.IX Item "sse+387" -.IP "\fBboth\fR" 4 -.IX Item "both" +.IP "\fB\-mlp64\fR" 4 +.IX Item "-mlp64" .PD -Attempt to utilize both instruction sets at once. This effectively doubles the -amount of available registers, and on chips with separate execution units for -387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is -still experimental, because the \s-1GCC\s0 register allocator does not model separate -functional units well, resulting in unstable performance. -.RE -.RS 4 -.RE -.IP "\fB\-masm=\fR\fIdialect\fR" 4 -.IX Item "-masm=dialect" -Output assembly instructions using selected \fIdialect\fR. Supported -choices are \fBintel\fR or \fBatt\fR (the default). Darwin does -not support \fBintel\fR. -.IP "\fB\-mieee\-fp\fR" 4 -.IX Item "-mieee-fp" +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. These are HP-UX specific flags. +.IP "\fB\-mno\-sched\-br\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-data-spec" .PD 0 -.IP "\fB\-mno\-ieee\-fp\fR" 4 -.IX Item "-mno-ieee-fp" +.IP "\fB\-msched\-br\-data\-spec\fR" 4 +.IX Item "-msched-br-data-spec" .PD -Control whether or not the compiler uses \s-1IEEE\s0 floating-point -comparisons. These correctly handle the case where the result of a -comparison is unordered. -.IP "\fB\-msoft\-float\fR" 4 -.IX Item "-msoft-float" -Generate output containing library calls for floating point. -.Sp -\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0. -Normally the facilities of the machine's usual C compiler are used, but -this can't be done directly in cross-compilation. You must make your -own arrangements to provide suitable library functions for -cross-compilation. -.Sp -On machines where a function returns floating-point results in the 80387 -register stack, some floating-point opcodes may be emitted even if -\&\fB\-msoft\-float\fR is used. -.IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4 -.IX Item "-mno-fp-ret-in-387" -Do not use the \s-1FPU\s0 registers for return values of functions. -.Sp -The usual calling convention has functions return values of types -\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there -is no \s-1FPU\s0. The idea is that the operating system should emulate -an \s-1FPU\s0. -.Sp -The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned -in ordinary \s-1CPU\s0 registers instead. -.IP "\fB\-mno\-fancy\-math\-387\fR" 4 -.IX Item "-mno-fancy-math-387" -Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and -\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid -generating those instructions. This option is the default on FreeBSD, -OpenBSD and NetBSD. This option is overridden when \fB\-march\fR -indicates that the target \s-1CPU\s0 always has an \s-1FPU\s0 and so the -instruction does not need emulation. These -instructions are not generated unless you also use the -\&\fB\-funsafe\-math\-optimizations\fR switch. -.IP "\fB\-malign\-double\fR" 4 -.IX Item "-malign-double" +(Dis/En)able data speculative scheduling before reload. +This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and +the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR). +The default is 'disable'. +.IP "\fB\-msched\-ar\-data\-spec\fR" 4 +.IX Item "-msched-ar-data-spec" .PD 0 -.IP "\fB\-mno\-align\-double\fR" 4 -.IX Item "-mno-align-double" +.IP "\fB\-mno\-sched\-ar\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-data-spec" .PD -Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and -\&\f(CW\*(C`long long\*(C'\fR variables on a two-word boundary or a one-word -boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two-word boundary -produces code that runs somewhat faster on a Pentium at the -expense of more memory. -.Sp -On x86\-64, \fB\-malign\-double\fR is enabled by default. -.Sp -\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch, -structures containing the above types are aligned differently than -the published application binary interface specifications for the 386 -and are not binary compatible with structures in code compiled -without that switch. -.IP "\fB\-m96bit\-long\-double\fR" 4 -.IX Item "-m96bit-long-double" +(En/Dis)able data speculative scheduling after reload. +This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and +the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR). +The default is 'enable'. +.IP "\fB\-mno\-sched\-control\-spec\fR" 4 +.IX Item "-mno-sched-control-spec" .PD 0 -.IP "\fB\-m128bit\-long\-double\fR" 4 -.IX Item "-m128bit-long-double" +.IP "\fB\-msched\-control\-spec\fR" 4 +.IX Item "-msched-control-spec" .PD -These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The i386 -application binary interface specifies the size to be 96 bits, -so \fB\-m96bit\-long\-double\fR is the default in 32\-bit mode. -.Sp -Modern architectures (Pentium and newer) prefer \f(CW\*(C`long double\*(C'\fR -to be aligned to an 8\- or 16\-byte boundary. In arrays or structures -conforming to the \s-1ABI\s0, this is not possible. So specifying -\&\fB\-m128bit\-long\-double\fR aligns \f(CW\*(C`long double\*(C'\fR -to a 16\-byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional -32\-bit zero. -.Sp -In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as -its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is aligned on 16\-byte boundary. -.Sp -Notice that neither of these options enable any extra precision over the x87 -standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR. -.Sp -\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, this -changes the size of -structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, -as well as modifying the function calling convention for functions taking -\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible -with code compiled without that switch. -.IP "\fB\-mlong\-double\-64\fR" 4 -.IX Item "-mlong-double-64" +(Dis/En)able control speculative scheduling. This feature is +available only during region scheduling (i.e. before reload). +This results in generation of the \f(CW\*(C`ld.s\*(C'\fR instructions and +the corresponding check instructions \f(CW\*(C`chk.s\*(C'\fR. +The default is 'disable'. +.IP "\fB\-msched\-br\-in\-data\-spec\fR" 4 +.IX Item "-msched-br-in-data-spec" .PD 0 -.IP "\fB\-mlong\-double\-80\fR" 4 -.IX Item "-mlong-double-80" -.IP "\fB\-mlong\-double\-128\fR" 4 -.IX Item "-mlong-double-128" +.IP "\fB\-mno\-sched\-br\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-br-in-data-spec" .PD -These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size -of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR -type. This is the default for 32\-bit Bionic C library. A size -of 128 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the -\&\f(CW\*(C`_\|_float128\*(C'\fR type. This is the default for 64\-bit Bionic C library. -.Sp -\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, this -changes the size of -structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, -as well as modifying the function calling convention for functions taking -\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible -with code compiled without that switch. -.IP "\fB\-malign\-data=\fR\fItype\fR" 4 -.IX Item "-malign-data=type" -Control how \s-1GCC\s0 aligns variables. Supported values for \fItype\fR are -\&\fBcompat\fR uses increased alignment value compatible uses \s-1GCC\s0 4.8 -and earlier, \fBabi\fR uses alignment value as specified by the -psABI, and \fBcacheline\fR uses increased alignment value to match -the cache line size. \fBcompat\fR is the default. -.IP "\fB\-mlarge\-data\-threshold=\fR\fIthreshold\fR" 4 -.IX Item "-mlarge-data-threshold=threshold" -When \fB\-mcmodel=medium\fR is specified, data objects larger than -\&\fIthreshold\fR are placed in the large data section. This value must be the -same across all objects linked into the binary, and defaults to 65535. -.IP "\fB\-mrtd\fR" 4 -.IX Item "-mrtd" -Use a different function-calling convention, in which functions that -take a fixed number of arguments return with the \f(CW\*(C`ret \f(CInum\f(CW\*(C'\fR -instruction, which pops their arguments while returning. This saves one -instruction in the caller since there is no need to pop the arguments -there. -.Sp -You can specify that an individual function is called with this calling -sequence with the function attribute \f(CW\*(C`stdcall\*(C'\fR. You can also -override the \fB\-mrtd\fR option by using the function attribute -\&\f(CW\*(C`cdecl\*(C'\fR. -.Sp -\&\fBWarning:\fR this calling convention is incompatible with the one -normally used on Unix, so you cannot use it if you need to call -libraries compiled with the Unix compiler. -.Sp -Also, you must provide function prototypes for all functions that -take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); -otherwise incorrect code is generated for calls to those -functions. -.Sp -In addition, seriously incorrect code results if you call a -function with too many arguments. (Normally, extra arguments are -harmlessly ignored.) -.IP "\fB\-mregparm=\fR\fInum\fR" 4 -.IX Item "-mregparm=num" -Control how many registers are used to pass integer arguments. By -default, no registers are used to pass arguments, and at most 3 -registers can be used. You can control this behavior for a specific -function by using the function attribute \f(CW\*(C`regparm\*(C'\fR. -.Sp -\&\fBWarning:\fR if you use this switch, and -\&\fInum\fR is nonzero, then you must build all modules with the same -value, including any libraries. This includes the system libraries and -startup modules. -.IP "\fB\-msseregparm\fR" 4 -.IX Item "-msseregparm" -Use \s-1SSE\s0 register passing conventions for float and double arguments -and return values. You can control this behavior for a specific -function by using the function attribute \f(CW\*(C`sseregparm\*(C'\fR. -.Sp -\&\fBWarning:\fR if you use this switch then you must build all -modules with the same value, including any libraries. This includes -the system libraries and startup modules. -.IP "\fB\-mvect8\-ret\-in\-mem\fR" 4 -.IX Item "-mvect8-ret-in-mem" -Return 8\-byte vectors in memory instead of \s-1MMX\s0 registers. This is the -default on Solaris@tie{}8 and 9 and VxWorks to match the \s-1ABI\s0 of the Sun -Studio compilers until version 12. Later compiler versions (starting -with Studio 12 Update@tie{}1) follow the \s-1ABI\s0 used by other x86 targets, which -is the default on Solaris@tie{}10 and later. \fIOnly\fR use this option if -you need to remain compatible with existing code produced by those -previous compiler versions or older versions of \s-1GCC\s0. -.IP "\fB\-mpc32\fR" 4 -.IX Item "-mpc32" +(En/Dis)able speculative scheduling of the instructions that +are dependent on the data speculative loads before reload. +This is effective only with \fB\-msched\-br\-data\-spec\fR enabled. +The default is 'enable'. +.IP "\fB\-msched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-msched-ar-in-data-spec" .PD 0 -.IP "\fB\-mpc64\fR" 4 -.IX Item "-mpc64" -.IP "\fB\-mpc80\fR" 4 -.IX Item "-mpc80" -.PD -Set 80387 floating-point precision to 32, 64 or 80 bits. When \fB\-mpc32\fR -is specified, the significands of results of floating-point operations are -rounded to 24 bits (single precision); \fB\-mpc64\fR rounds the -significands of results of floating-point operations to 53 bits (double -precision) and \fB\-mpc80\fR rounds the significands of results of -floating-point operations to 64 bits (extended double precision), which is -the default. When this option is used, floating-point operations in higher -precisions are not available to the programmer without setting the \s-1FPU\s0 -control word explicitly. -.Sp -Setting the rounding of floating-point operations to less than the default -80 bits can speed some programs by 2% or more. Note that some mathematical -libraries assume that extended-precision (80\-bit) floating-point operations -are enabled by default; routines in such libraries could suffer significant -loss of accuracy, typically through so-called \*(L"catastrophic cancellation\*(R", -when this option is used to set the precision to less than extended precision. -.IP "\fB\-mstackrealign\fR" 4 -.IX Item "-mstackrealign" -Realign the stack at entry. On the Intel x86, the \fB\-mstackrealign\fR -option generates an alternate prologue and epilogue that realigns the -run-time stack if necessary. This supports mixing legacy codes that keep -4\-byte stack alignment with modern codes that keep 16\-byte stack alignment for -\&\s-1SSE\s0 compatibility. See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR, -applicable to individual functions. -.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4 -.IX Item "-mpreferred-stack-boundary=num" -Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR -byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified, -the default is 4 (16 bytes or 128 bits). -.Sp -\&\fBWarning:\fR When generating code for the x86\-64 architecture with -\&\s-1SSE\s0 extensions disabled, \fB\-mpreferred\-stack\-boundary=3\fR can be -used to keep the stack boundary aligned to 8 byte boundary. Since -x86\-64 \s-1ABI\s0 require 16 byte stack alignment, this is \s-1ABI\s0 incompatible and -intended to be used in controlled environment where stack space is -important limitation. This option leads to wrong code when functions -compiled with 16 byte stack alignment (such as functions from a standard -library) are called with misaligned stack. In this case, \s-1SSE\s0 -instructions may lead to misaligned memory access traps. In addition, -variable arguments are handled incorrectly for 16 byte aligned -objects (including x87 long double and _\|_int128), leading to wrong -results. You must build all modules with -\&\fB\-mpreferred\-stack\-boundary=3\fR, including any libraries. This -includes the system libraries and startup modules. -.IP "\fB\-mincoming\-stack\-boundary=\fR\fInum\fR" 4 -.IX Item "-mincoming-stack-boundary=num" -Assume the incoming stack is aligned to a 2 raised to \fInum\fR byte -boundary. If \fB\-mincoming\-stack\-boundary\fR is not specified, -the one specified by \fB\-mpreferred\-stack\-boundary\fR is used. -.Sp -On Pentium and Pentium Pro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values -should be aligned to an 8\-byte boundary (see \fB\-malign\-double\fR) or -suffer significant run time performance penalties. On Pentium \s-1III\s0, the -Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work -properly if it is not 16\-byte aligned. -.Sp -To ensure proper alignment of this values on the stack, the stack boundary -must be as aligned as that required by any value stored on the stack. -Further, every function must be generated such that it keeps the stack -aligned. Thus calling a function compiled with a higher preferred -stack boundary from a function compiled with a lower preferred stack -boundary most likely misaligns the stack. It is recommended that -libraries that use callbacks always use the default setting. -.Sp -This extra alignment does consume extra stack space, and generally -increases code size. Code that is sensitive to stack space usage, such -as embedded systems and operating system kernels, may want to reduce the -preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR. -.IP "\fB\-mmmx\fR" 4 -.IX Item "-mmmx" -.PD 0 -.IP "\fB\-msse\fR" 4 -.IX Item "-msse" -.IP "\fB\-msse2\fR" 4 -.IX Item "-msse2" -.IP "\fB\-msse3\fR" 4 -.IX Item "-msse3" -.IP "\fB\-mssse3\fR" 4 -.IX Item "-mssse3" -.IP "\fB\-msse4\fR" 4 -.IX Item "-msse4" -.IP "\fB\-msse4a\fR" 4 -.IX Item "-msse4a" -.IP "\fB\-msse4.1\fR" 4 -.IX Item "-msse4.1" -.IP "\fB\-msse4.2\fR" 4 -.IX Item "-msse4.2" -.IP "\fB\-mavx\fR" 4 -.IX Item "-mavx" -.IP "\fB\-mavx2\fR" 4 -.IX Item "-mavx2" -.IP "\fB\-mavx512f\fR" 4 -.IX Item "-mavx512f" -.IP "\fB\-mavx512pf\fR" 4 -.IX Item "-mavx512pf" -.IP "\fB\-mavx512er\fR" 4 -.IX Item "-mavx512er" -.IP "\fB\-mavx512cd\fR" 4 -.IX Item "-mavx512cd" -.IP "\fB\-msha\fR" 4 -.IX Item "-msha" -.IP "\fB\-maes\fR" 4 -.IX Item "-maes" -.IP "\fB\-mpclmul\fR" 4 -.IX Item "-mpclmul" -.IP "\fB\-mclfushopt\fR" 4 -.IX Item "-mclfushopt" -.IP "\fB\-mfsgsbase\fR" 4 -.IX Item "-mfsgsbase" -.IP "\fB\-mrdrnd\fR" 4 -.IX Item "-mrdrnd" -.IP "\fB\-mf16c\fR" 4 -.IX Item "-mf16c" -.IP "\fB\-mfma\fR" 4 -.IX Item "-mfma" -.IP "\fB\-mfma4\fR" 4 -.IX Item "-mfma4" -.IP "\fB\-mno\-fma4\fR" 4 -.IX Item "-mno-fma4" -.IP "\fB\-mprefetchwt1\fR" 4 -.IX Item "-mprefetchwt1" -.IP "\fB\-mxop\fR" 4 -.IX Item "-mxop" -.IP "\fB\-mlwp\fR" 4 -.IX Item "-mlwp" -.IP "\fB\-m3dnow\fR" 4 -.IX Item "-m3dnow" -.IP "\fB\-mpopcnt\fR" 4 -.IX Item "-mpopcnt" -.IP "\fB\-mabm\fR" 4 -.IX Item "-mabm" -.IP "\fB\-mbmi\fR" 4 -.IX Item "-mbmi" -.IP "\fB\-mbmi2\fR" 4 -.IX Item "-mbmi2" -.IP "\fB\-mlzcnt\fR" 4 -.IX Item "-mlzcnt" -.IP "\fB\-mfxsr\fR" 4 -.IX Item "-mfxsr" -.IP "\fB\-mxsave\fR" 4 -.IX Item "-mxsave" -.IP "\fB\-mxsaveopt\fR" 4 -.IX Item "-mxsaveopt" -.IP "\fB\-mxsavec\fR" 4 -.IX Item "-mxsavec" -.IP "\fB\-mxsaves\fR" 4 -.IX Item "-mxsaves" -.IP "\fB\-mrtm\fR" 4 -.IX Item "-mrtm" -.IP "\fB\-mtbm\fR" 4 -.IX Item "-mtbm" -.IP "\fB\-mmpx\fR" 4 -.IX Item "-mmpx" -.PD -These switches enable the use of instructions in the \s-1MMX\s0, \s-1SSE\s0, -\&\s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1AVX\s0, \s-1AVX2\s0, \s-1AVX512F\s0, \s-1AVX512PF\s0, \s-1AVX512ER\s0, \s-1AVX512CD\s0, -\&\s-1SHA\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, F16C, \s-1FMA\s0, \s-1SSE4A\s0, \s-1FMA4\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1ABM\s0, -\&\s-1BMI\s0, \s-1BMI2\s0, \s-1FXSR\s0, \s-1XSAVE\s0, \s-1XSAVEOPT\s0, \s-1LZCNT\s0, \s-1RTM\s0, \s-1MPX\s0 or 3DNow! -extended instruction sets. Each has a corresponding \fB\-mno\-\fR option -to disable use of these instructions. -.Sp -These extensions are also available as built-in functions: see -\&\fBX86 Built-in Functions\fR, for details of the functions enabled and -disabled by these switches. -.Sp -To generate \s-1SSE/SSE2\s0 instructions automatically from floating-point -code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR. -.Sp -\&\s-1GCC\s0 depresses SSEx instructions when \fB\-mavx\fR is used. Instead, it -generates new \s-1AVX\s0 instructions or \s-1AVX\s0 equivalence for all SSEx instructions -when needed. -.Sp -These options enable \s-1GCC\s0 to use these extended instructions in -generated code, even without \fB\-mfpmath=sse\fR. Applications that -perform run-time \s-1CPU\s0 detection must compile separate files for each -supported architecture, using the appropriate flags. In particular, -the file containing the \s-1CPU\s0 detection code should be compiled without -these options. -.IP "\fB\-mdump\-tune\-features\fR" 4 -.IX Item "-mdump-tune-features" -This option instructs \s-1GCC\s0 to dump the names of the x86 performance -tuning features and default settings. The names can be used in -\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR. -.IP "\fB\-mtune\-ctrl=\fR\fIfeature-list\fR" 4 -.IX Item "-mtune-ctrl=feature-list" -This option is used to do fine grain control of x86 code generation features. -\&\fIfeature-list\fR is a comma separated list of \fIfeature\fR names. See also -\&\fB\-mdump\-tune\-features\fR. When specified, the \fIfeature\fR is turned -on if it is not preceded with \fB^\fR, otherwise, it is turned off. -\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR is intended to be used by \s-1GCC\s0 -developers. Using it may lead to code paths not covered by testing and can -potentially result in compiler ICEs or runtime errors. -.IP "\fB\-mno\-default\fR" 4 -.IX Item "-mno-default" -This option instructs \s-1GCC\s0 to turn off all tunable features. See also -\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR and \fB\-mdump\-tune\-features\fR. -.IP "\fB\-mcld\fR" 4 -.IX Item "-mcld" -This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`cld\*(C'\fR instruction in the prologue -of functions that use string instructions. String instructions depend on -the \s-1DF\s0 flag to select between autoincrement or autodecrement mode. While the -\&\s-1ABI\s0 specifies the \s-1DF\s0 flag to be cleared on function entry, some operating -systems violate this specification by not clearing the \s-1DF\s0 flag in their -exception dispatchers. The exception handler can be invoked with the \s-1DF\s0 flag -set, which leads to wrong direction mode when string instructions are used. -This option can be enabled by default on 32\-bit x86 targets by configuring -\&\s-1GCC\s0 with the \fB\-\-enable\-cld\fR configure option. Generation of \f(CW\*(C`cld\*(C'\fR -instructions can be suppressed with the \fB\-mno\-cld\fR compiler option -in this case. -.IP "\fB\-mvzeroupper\fR" 4 -.IX Item "-mvzeroupper" -This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`vzeroupper\*(C'\fR instruction -before a transfer of control flow out of the function to minimize -the \s-1AVX\s0 to \s-1SSE\s0 transition penalty as well as remove unnecessary \f(CW\*(C`zeroupper\*(C'\fR -intrinsics. -.IP "\fB\-mprefer\-avx128\fR" 4 -.IX Item "-mprefer-avx128" -This option instructs \s-1GCC\s0 to use 128\-bit \s-1AVX\s0 instructions instead of -256\-bit \s-1AVX\s0 instructions in the auto-vectorizer. -.IP "\fB\-mcx16\fR" 4 -.IX Item "-mcx16" -This option enables \s-1GCC\s0 to generate \f(CW\*(C`CMPXCHG16B\*(C'\fR instructions. -\&\f(CW\*(C`CMPXCHG16B\*(C'\fR allows for atomic operations on 128\-bit double quadword -(or oword) data types. -This is useful for high-resolution counters that can be updated -by multiple processors (or cores). This instruction is generated as part of -atomic built-in functions: see \fB_\|_sync Builtins\fR or -\&\fB_\|_atomic Builtins\fR for details. -.IP "\fB\-msahf\fR" 4 -.IX Item "-msahf" -This option enables generation of \f(CW\*(C`SAHF\*(C'\fR instructions in 64\-bit code. -Early Intel Pentium 4 CPUs with Intel 64 support, -prior to the introduction of Pentium 4 G1 step in December 2005, -lacked the \f(CW\*(C`LAHF\*(C'\fR and \f(CW\*(C`SAHF\*(C'\fR instructions -which are supported by \s-1AMD64\s0. -These are load and store instructions, respectively, for certain status flags. -In 64\-bit mode, the \f(CW\*(C`SAHF\*(C'\fR instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, -\&\f(CW\*(C`drem\*(C'\fR, and \f(CW\*(C`remainder\*(C'\fR built-in functions; -see \fBOther Builtins\fR for details. -.IP "\fB\-mmovbe\fR" 4 -.IX Item "-mmovbe" -This option enables use of the \f(CW\*(C`movbe\*(C'\fR instruction to implement -\&\f(CW\*(C`_\|_builtin_bswap32\*(C'\fR and \f(CW\*(C`_\|_builtin_bswap64\*(C'\fR. -.IP "\fB\-mcrc32\fR" 4 -.IX Item "-mcrc32" -This option enables built-in functions \f(CW\*(C`_\|_builtin_ia32_crc32qi\*(C'\fR, -\&\f(CW\*(C`_\|_builtin_ia32_crc32hi\*(C'\fR, \f(CW\*(C`_\|_builtin_ia32_crc32si\*(C'\fR and -\&\f(CW\*(C`_\|_builtin_ia32_crc32di\*(C'\fR to generate the \f(CW\*(C`crc32\*(C'\fR machine instruction. -.IP "\fB\-mrecip\fR" 4 -.IX Item "-mrecip" -This option enables use of \f(CW\*(C`RCPSS\*(C'\fR and \f(CW\*(C`RSQRTSS\*(C'\fR instructions -(and their vectorized variants \f(CW\*(C`RCPPS\*(C'\fR and \f(CW\*(C`RSQRTPS\*(C'\fR) -with an additional Newton-Raphson step -to increase precision instead of \f(CW\*(C`DIVSS\*(C'\fR and \f(CW\*(C`SQRTSS\*(C'\fR -(and their vectorized -variants) for single-precision floating-point arguments. These instructions -are generated only when \fB\-funsafe\-math\-optimizations\fR is enabled -together with \fB\-finite\-math\-only\fR and \fB\-fno\-trapping\-math\fR. -Note that while the throughput of the sequence is higher than the throughput -of the non-reciprocal instruction, the precision of the sequence can be -decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). -.Sp -Note that \s-1GCC\s0 implements \f(CW\*(C`1.0f/sqrtf(\f(CIx\f(CW)\*(C'\fR in terms of \f(CW\*(C`RSQRTSS\*(C'\fR -(or \f(CW\*(C`RSQRTPS\*(C'\fR) already with \fB\-ffast\-math\fR (or the above option -combination), and doesn't need \fB\-mrecip\fR. -.Sp -Also note that \s-1GCC\s0 emits the above sequence with additional Newton-Raphson step -for vectorized single-float division and vectorized \f(CW\*(C`sqrtf(\f(CIx\f(CW)\*(C'\fR -already with \fB\-ffast\-math\fR (or the above option combination), and -doesn't need \fB\-mrecip\fR. -.IP "\fB\-mrecip=\fR\fIopt\fR" 4 -.IX Item "-mrecip=opt" -This option controls which reciprocal estimate instructions -may be used. \fIopt\fR is a comma-separated list of options, which may -be preceded by a \fB!\fR to invert the option: -.RS 4 -.IP "\fBall\fR" 4 -.IX Item "all" -Enable all estimate instructions. -.IP "\fBdefault\fR" 4 -.IX Item "default" -Enable the default instructions, equivalent to \fB\-mrecip\fR. -.IP "\fBnone\fR" 4 -.IX Item "none" -Disable all estimate instructions, equivalent to \fB\-mno\-recip\fR. -.IP "\fBdiv\fR" 4 -.IX Item "div" -Enable the approximation for scalar division. -.IP "\fBvec-div\fR" 4 -.IX Item "vec-div" -Enable the approximation for vectorized division. -.IP "\fBsqrt\fR" 4 -.IX Item "sqrt" -Enable the approximation for scalar square root. -.IP "\fBvec-sqrt\fR" 4 -.IX Item "vec-sqrt" -Enable the approximation for vectorized square root. -.RE -.RS 4 -.Sp -So, for example, \fB\-mrecip=all,!sqrt\fR enables -all of the reciprocal approximations, except for square root. -.RE -.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 -.IX Item "-mveclibabi=type" -Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an -external library. Supported values for \fItype\fR are \fBsvml\fR -for the Intel short -vector math library and \fBacml\fR for the \s-1AMD\s0 math core library. -To use this option, both \fB\-ftree\-vectorize\fR and -\&\fB\-funsafe\-math\-optimizations\fR have to be enabled, and an \s-1SVML\s0 or \s-1ACML\s0 -ABI-compatible library must be specified at link time. -.Sp -\&\s-1GCC\s0 currently emits calls to \f(CW\*(C`vmldExp2\*(C'\fR, -\&\f(CW\*(C`vmldLn2\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldPow2\*(C'\fR, -\&\f(CW\*(C`vmldTanh2\*(C'\fR, \f(CW\*(C`vmldTan2\*(C'\fR, \f(CW\*(C`vmldAtan2\*(C'\fR, \f(CW\*(C`vmldAtanh2\*(C'\fR, -\&\f(CW\*(C`vmldCbrt2\*(C'\fR, \f(CW\*(C`vmldSinh2\*(C'\fR, \f(CW\*(C`vmldSin2\*(C'\fR, \f(CW\*(C`vmldAsinh2\*(C'\fR, -\&\f(CW\*(C`vmldAsin2\*(C'\fR, \f(CW\*(C`vmldCosh2\*(C'\fR, \f(CW\*(C`vmldCos2\*(C'\fR, \f(CW\*(C`vmldAcosh2\*(C'\fR, -\&\f(CW\*(C`vmldAcos2\*(C'\fR, \f(CW\*(C`vmlsExp4\*(C'\fR, \f(CW\*(C`vmlsLn4\*(C'\fR, \f(CW\*(C`vmlsLog104\*(C'\fR, -\&\f(CW\*(C`vmlsLog104\*(C'\fR, \f(CW\*(C`vmlsPow4\*(C'\fR, \f(CW\*(C`vmlsTanh4\*(C'\fR, \f(CW\*(C`vmlsTan4\*(C'\fR, -\&\f(CW\*(C`vmlsAtan4\*(C'\fR, \f(CW\*(C`vmlsAtanh4\*(C'\fR, \f(CW\*(C`vmlsCbrt4\*(C'\fR, \f(CW\*(C`vmlsSinh4\*(C'\fR, -\&\f(CW\*(C`vmlsSin4\*(C'\fR, \f(CW\*(C`vmlsAsinh4\*(C'\fR, \f(CW\*(C`vmlsAsin4\*(C'\fR, \f(CW\*(C`vmlsCosh4\*(C'\fR, -\&\f(CW\*(C`vmlsCos4\*(C'\fR, \f(CW\*(C`vmlsAcosh4\*(C'\fR and \f(CW\*(C`vmlsAcos4\*(C'\fR for corresponding -function type when \fB\-mveclibabi=svml\fR is used, and \f(CW\*(C`_\|_vrd2_sin\*(C'\fR, -\&\f(CW\*(C`_\|_vrd2_cos\*(C'\fR, \f(CW\*(C`_\|_vrd2_exp\*(C'\fR, \f(CW\*(C`_\|_vrd2_log\*(C'\fR, \f(CW\*(C`_\|_vrd2_log2\*(C'\fR, -\&\f(CW\*(C`_\|_vrd2_log10\*(C'\fR, \f(CW\*(C`_\|_vrs4_sinf\*(C'\fR, \f(CW\*(C`_\|_vrs4_cosf\*(C'\fR, -\&\f(CW\*(C`_\|_vrs4_expf\*(C'\fR, \f(CW\*(C`_\|_vrs4_logf\*(C'\fR, \f(CW\*(C`_\|_vrs4_log2f\*(C'\fR, -\&\f(CW\*(C`_\|_vrs4_log10f\*(C'\fR and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR for the corresponding function type -when \fB\-mveclibabi=acml\fR is used. -.IP "\fB\-mabi=\fR\fIname\fR" 4 -.IX Item "-mabi=name" -Generate code for the specified calling convention. Permissible values -are \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems, and -\&\fBms\fR for the Microsoft \s-1ABI\s0. The default is to use the Microsoft -\&\s-1ABI\s0 when targeting Microsoft Windows and the SysV \s-1ABI\s0 on all other systems. -You can control this behavior for specific functions by -using the function attributes \f(CW\*(C`ms_abi\*(C'\fR and \f(CW\*(C`sysv_abi\*(C'\fR. -.IP "\fB\-mtls\-dialect=\fR\fItype\fR" 4 -.IX Item "-mtls-dialect=type" -Generate code to access thread-local storage using the \fBgnu\fR or -\&\fBgnu2\fR conventions. \fBgnu\fR is the conservative default; -\&\fBgnu2\fR is more efficient, but it may add compile\- and run-time -requirements that cannot be satisfied on all systems. -.IP "\fB\-mpush\-args\fR" 4 -.IX Item "-mpush-args" -.PD 0 -.IP "\fB\-mno\-push\-args\fR" 4 -.IX Item "-mno-push-args" -.PD -Use \s-1PUSH\s0 operations to store outgoing parameters. This method is shorter -and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled -by default. In some cases disabling it may improve performance because of -improved scheduling and reduced dependencies. -.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 -.IX Item "-maccumulate-outgoing-args" -If enabled, the maximum amount of space required for outgoing arguments is -computed in the function prologue. This is faster on most modern CPUs -because of reduced dependencies, improved scheduling and reduced stack usage -when the preferred stack boundary is not equal to 2. The drawback is a notable -increase in code size. This switch implies \fB\-mno\-push\-args\fR. -.IP "\fB\-mthreads\fR" 4 -.IX Item "-mthreads" -Support thread-safe exception handling on MinGW. Programs that rely -on thread-safe exception handling must compile and link all code with the -\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines -\&\fB\-D_MT\fR; when linking, it links in a special thread helper library -\&\fB\-lmingwthrd\fR which cleans up per-thread exception-handling data. -.IP "\fB\-mno\-align\-stringops\fR" 4 -.IX Item "-mno-align-stringops" -Do not align the destination of inlined string operations. This switch reduces -code size and improves performance in case the destination is already aligned, -but \s-1GCC\s0 doesn't know about it. -.IP "\fB\-minline\-all\-stringops\fR" 4 -.IX Item "-minline-all-stringops" -By default \s-1GCC\s0 inlines string operations only when the destination is -known to be aligned to least a 4\-byte boundary. -This enables more inlining and increases code -size, but may improve performance of code that depends on fast -\&\f(CW\*(C`memcpy\*(C'\fR, \f(CW\*(C`strlen\*(C'\fR, -and \f(CW\*(C`memset\*(C'\fR for short lengths. -.IP "\fB\-minline\-stringops\-dynamically\fR" 4 -.IX Item "-minline-stringops-dynamically" -For string operations of unknown size, use run-time checks with -inline code for small blocks and a library call for large blocks. -.IP "\fB\-mstringop\-strategy=\fR\fIalg\fR" 4 -.IX Item "-mstringop-strategy=alg" -Override the internal decision heuristic for the particular algorithm to use -for inlining string operations. The allowed values for \fIalg\fR are: -.RS 4 -.IP "\fBrep_byte\fR" 4 -.IX Item "rep_byte" -.PD 0 -.IP "\fBrep_4byte\fR" 4 -.IX Item "rep_4byte" -.IP "\fBrep_8byte\fR" 4 -.IX Item "rep_8byte" -.PD -Expand using i386 \f(CW\*(C`rep\*(C'\fR prefix of the specified size. -.IP "\fBbyte_loop\fR" 4 -.IX Item "byte_loop" -.PD 0 -.IP "\fBloop\fR" 4 -.IX Item "loop" -.IP "\fBunrolled_loop\fR" 4 -.IX Item "unrolled_loop" -.PD -Expand into an inline loop. -.IP "\fBlibcall\fR" 4 -.IX Item "libcall" -Always use a library call. -.RE -.RS 4 -.RE -.IP "\fB\-mmemcpy\-strategy=\fR\fIstrategy\fR" 4 -.IX Item "-mmemcpy-strategy=strategy" -Override the internal decision heuristic to decide if \f(CW\*(C`_\|_builtin_memcpy\*(C'\fR -should be inlined and what inline algorithm to use when the expected size -of the copy operation is known. \fIstrategy\fR -is a comma-separated list of \fIalg\fR:\fImax_size\fR:\fIdest_align\fR triplets. -\&\fIalg\fR is specified in \fB\-mstringop\-strategy\fR, \fImax_size\fR specifies -the max byte size with which inline algorithm \fIalg\fR is allowed. For the last -triplet, the \fImax_size\fR must be \f(CW\*(C`\-1\*(C'\fR. The \fImax_size\fR of the triplets -in the list must be specified in increasing order. The minimal byte size for -\&\fIalg\fR is \f(CW0\fR for the first triplet and \f(CW\*(C`\f(CImax_size\f(CW + 1\*(C'\fR of the -preceding range. -.IP "\fB\-mmemset\-strategy=\fR\fIstrategy\fR" 4 -.IX Item "-mmemset-strategy=strategy" -The option is similar to \fB\-mmemcpy\-strategy=\fR except that it is to control -\&\f(CW\*(C`_\|_builtin_memset\*(C'\fR expansion. -.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 -.IX Item "-momit-leaf-frame-pointer" -Don't keep the frame pointer in a register for leaf functions. This -avoids the instructions to save, set up, and restore frame pointers and -makes an extra register available in leaf functions. The option -\&\fB\-fomit\-leaf\-frame\-pointer\fR removes the frame pointer for leaf functions, -which might make debugging harder. -.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4 -.IX Item "-mtls-direct-seg-refs" -.PD 0 -.IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4 -.IX Item "-mno-tls-direct-seg-refs" -.PD -Controls whether \s-1TLS\s0 variables may be accessed with offsets from the -\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit), -or whether the thread base pointer must be added. Whether or not this -is valid depends on the operating system, and whether it maps the -segment to cover the entire \s-1TLS\s0 area. -.Sp -For systems that use the \s-1GNU\s0 C Library, the default is on. -.IP "\fB\-msse2avx\fR" 4 -.IX Item "-msse2avx" -.PD 0 -.IP "\fB\-mno\-sse2avx\fR" 4 -.IX Item "-mno-sse2avx" -.PD -Specify that the assembler should encode \s-1SSE\s0 instructions with \s-1VEX\s0 -prefix. The option \fB\-mavx\fR turns this on by default. -.IP "\fB\-mfentry\fR" 4 -.IX Item "-mfentry" -.PD 0 -.IP "\fB\-mno\-fentry\fR" 4 -.IX Item "-mno-fentry" -.PD -If profiling is active (\fB\-pg\fR), put the profiling -counter call before the prologue. -Note: On x86 architectures the attribute \f(CW\*(C`ms_hook_prologue\*(C'\fR -isn't possible at the moment for \fB\-mfentry\fR and \fB\-pg\fR. -.IP "\fB\-mrecord\-mcount\fR" 4 -.IX Item "-mrecord-mcount" -.PD 0 -.IP "\fB\-mno\-record\-mcount\fR" 4 -.IX Item "-mno-record-mcount" -.PD -If profiling is active (\fB\-pg\fR), generate a _\|_mcount_loc section -that contains pointers to each profiling call. This is useful for -automatically patching and out calls. -.IP "\fB\-mnop\-mcount\fR" 4 -.IX Item "-mnop-mcount" -.PD 0 -.IP "\fB\-mno\-nop\-mcount\fR" 4 -.IX Item "-mno-nop-mcount" -.PD -If profiling is active (\fB\-pg\fR), generate the calls to -the profiling functions as nops. This is useful when they -should be patched in later dynamically. This is likely only -useful together with \fB\-mrecord\-mcount\fR. -.IP "\fB\-mskip\-rax\-setup\fR" 4 -.IX Item "-mskip-rax-setup" -.PD 0 -.IP "\fB\-mno\-skip\-rax\-setup\fR" 4 -.IX Item "-mno-skip-rax-setup" -.PD -When generating code for the x86\-64 architecture with \s-1SSE\s0 extensions -disabled, \fB\-skip\-rax\-setup\fR can be used to skip setting up \s-1RAX\s0 -register when there are no variable arguments passed in vector registers. -.Sp -\&\fBWarning:\fR Since \s-1RAX\s0 register is used to avoid unnecessarily -saving vector registers on stack when passing variable arguments, the -impacts of this option are callees may waste some stack space, -misbehave or jump to a random location. \s-1GCC\s0 4.4 or newer don't have -those issues, regardless the \s-1RAX\s0 register value. -.IP "\fB\-m8bit\-idiv\fR" 4 -.IX Item "-m8bit-idiv" -.PD 0 -.IP "\fB\-mno\-8bit\-idiv\fR" 4 -.IX Item "-mno-8bit-idiv" -.PD -On some processors, like Intel Atom, 8\-bit unsigned integer divide is -much faster than 32\-bit/64\-bit integer divide. This option generates a -run-time check. If both dividend and divisor are within range of 0 -to 255, 8\-bit unsigned integer divide is used instead of -32\-bit/64\-bit integer divide. -.IP "\fB\-mavx256\-split\-unaligned\-load\fR" 4 -.IX Item "-mavx256-split-unaligned-load" -.PD 0 -.IP "\fB\-mavx256\-split\-unaligned\-store\fR" 4 -.IX Item "-mavx256-split-unaligned-store" -.PD -Split 32\-byte \s-1AVX\s0 unaligned load and store. -.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 -.IX Item "-mstack-protector-guard=guard" -Generate stack protection code using canary at \fIguard\fR. Supported -locations are \fBglobal\fR for global canary or \fBtls\fR for per-thread -canary in the \s-1TLS\s0 block (the default). This option has effect only when -\&\fB\-fstack\-protector\fR or \fB\-fstack\-protector\-all\fR is specified. -.PP -These \fB\-m\fR switches are supported in addition to the above -on x86\-64 processors in 64\-bit environments. -.IP "\fB\-m32\fR" 4 -.IX Item "-m32" -.PD 0 -.IP "\fB\-m64\fR" 4 -.IX Item "-m64" -.IP "\fB\-mx32\fR" 4 -.IX Item "-mx32" -.IP "\fB\-m16\fR" 4 -.IX Item "-m16" -.PD -Generate code for a 16\-bit, 32\-bit or 64\-bit environment. -The \fB\-m32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types -to 32 bits, and -generates code that runs on any i386 system. -.Sp -The \fB\-m64\fR option sets \f(CW\*(C`int\*(C'\fR to 32 bits and \f(CW\*(C`long\*(C'\fR and pointer -types to 64 bits, and generates code for the x86\-64 architecture. -For Darwin only the \fB\-m64\fR option also turns off the \fB\-fno\-pic\fR -and \fB\-mdynamic\-no\-pic\fR options. -.Sp -The \fB\-mx32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types -to 32 bits, and -generates code for the x86\-64 architecture. -.Sp -The \fB\-m16\fR option is the same as \fB\-m32\fR, except for that -it outputs the \f(CW\*(C`.code16gcc\*(C'\fR assembly directive at the beginning of -the assembly output so that the binary can run in 16\-bit mode. -.IP "\fB\-mno\-red\-zone\fR" 4 -.IX Item "-mno-red-zone" -Do not use a so-called \*(L"red zone\*(R" for x86\-64 code. The red zone is mandated -by the x86\-64 \s-1ABI\s0; it is a 128\-byte area beyond the location of the -stack pointer that is not modified by signal or interrupt handlers -and therefore can be used for temporary data without adjusting the stack -pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone. -.IP "\fB\-mcmodel=small\fR" 4 -.IX Item "-mcmodel=small" -Generate code for the small code model: the program and its symbols must -be linked in the lower 2 \s-1GB\s0 of the address space. Pointers are 64 bits. -Programs can be statically or dynamically linked. This is the default -code model. -.IP "\fB\-mcmodel=kernel\fR" 4 -.IX Item "-mcmodel=kernel" -Generate code for the kernel code model. The kernel runs in the -negative 2 \s-1GB\s0 of the address space. -This model has to be used for Linux kernel code. -.IP "\fB\-mcmodel=medium\fR" 4 -.IX Item "-mcmodel=medium" -Generate code for the medium model: the program is linked in the lower 2 -\&\s-1GB\s0 of the address space. Small symbols are also placed there. Symbols -with sizes larger than \fB\-mlarge\-data\-threshold\fR are put into -large data or \s-1BSS\s0 sections and can be located above 2GB. Programs can -be statically or dynamically linked. -.IP "\fB\-mcmodel=large\fR" 4 -.IX Item "-mcmodel=large" -Generate code for the large model. This model makes no assumptions -about addresses and sizes of sections. -.IP "\fB\-maddress\-mode=long\fR" 4 -.IX Item "-maddress-mode=long" -Generate code for long address mode. This is only supported for 64\-bit -and x32 environments. It is the default address mode for 64\-bit -environments. -.IP "\fB\-maddress\-mode=short\fR" 4 -.IX Item "-maddress-mode=short" -Generate code for short address mode. This is only supported for 32\-bit -and x32 environments. It is the default address mode for 32\-bit and -x32 environments. -.PP -\fIi386 and x86\-64 Windows Options\fR -.IX Subsection "i386 and x86-64 Windows Options" -.PP -These additional options are available for Microsoft Windows targets: -.IP "\fB\-mconsole\fR" 4 -.IX Item "-mconsole" -This option -specifies that a console application is to be generated, by -instructing the linker to set the \s-1PE\s0 header subsystem type -required for console applications. -This option is available for Cygwin and MinGW targets and is -enabled by default on those targets. -.IP "\fB\-mdll\fR" 4 -.IX Item "-mdll" -This option is available for Cygwin and MinGW targets. It -specifies that a DLL\-\-\-a dynamic link library\-\-\-is to be -generated, enabling the selection of the required runtime -startup object and entry point. -.IP "\fB\-mnop\-fun\-dllimport\fR" 4 -.IX Item "-mnop-fun-dllimport" -This option is available for Cygwin and MinGW targets. It -specifies that the \f(CW\*(C`dllimport\*(C'\fR attribute should be ignored. -.IP "\fB\-mthread\fR" 4 -.IX Item "-mthread" -This option is available for MinGW targets. It specifies -that MinGW-specific thread support is to be used. -.IP "\fB\-municode\fR" 4 -.IX Item "-municode" -This option is available for MinGW\-w64 targets. It causes -the \f(CW\*(C`UNICODE\*(C'\fR preprocessor macro to be predefined, and -chooses Unicode-capable runtime startup code. -.IP "\fB\-mwin32\fR" 4 -.IX Item "-mwin32" -This option is available for Cygwin and MinGW targets. It -specifies that the typical Microsoft Windows predefined macros are to -be set in the pre-processor, but does not influence the choice -of runtime library/startup code. -.IP "\fB\-mwindows\fR" 4 -.IX Item "-mwindows" -This option is available for Cygwin and MinGW targets. It -specifies that a \s-1GUI\s0 application is to be generated by -instructing the linker to set the \s-1PE\s0 header subsystem type -appropriately. -.IP "\fB\-fno\-set\-stack\-executable\fR" 4 -.IX Item "-fno-set-stack-executable" -This option is available for MinGW targets. It specifies that -the executable flag for the stack used by nested functions isn't -set. This is necessary for binaries running in kernel mode of -Microsoft Windows, as there the User32 \s-1API\s0, which is used to set executable -privileges, isn't available. -.IP "\fB\-fwritable\-relocated\-rdata\fR" 4 -.IX Item "-fwritable-relocated-rdata" -This option is available for MinGW and Cygwin targets. It specifies -that relocated-data in read-only section is put into .data -section. This is a necessary for older runtimes not supporting -modification of .rdata sections for pseudo-relocation. -.IP "\fB\-mpe\-aligned\-commons\fR" 4 -.IX Item "-mpe-aligned-commons" -This option is available for Cygwin and MinGW targets. It -specifies that the \s-1GNU\s0 extension to the \s-1PE\s0 file format that -permits the correct alignment of \s-1COMMON\s0 variables should be -used when generating code. It is enabled by default if -\&\s-1GCC\s0 detects that the target assembler found during configuration -supports the feature. -.PP -See also under \fBi386 and x86\-64 Options\fR for standard options. -.PP -\fI\s-1IA\-64\s0 Options\fR -.IX Subsection "IA-64 Options" -.PP -These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture. -.IP "\fB\-mbig\-endian\fR" 4 -.IX Item "-mbig-endian" -Generate code for a big-endian target. This is the default for HP-UX. -.IP "\fB\-mlittle\-endian\fR" 4 -.IX Item "-mlittle-endian" -Generate code for a little-endian target. This is the default for \s-1AIX5\s0 -and GNU/Linux. -.IP "\fB\-mgnu\-as\fR" 4 -.IX Item "-mgnu-as" -.PD 0 -.IP "\fB\-mno\-gnu\-as\fR" 4 -.IX Item "-mno-gnu-as" -.PD -Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default. -.IP "\fB\-mgnu\-ld\fR" 4 -.IX Item "-mgnu-ld" -.PD 0 -.IP "\fB\-mno\-gnu\-ld\fR" 4 -.IX Item "-mno-gnu-ld" -.PD -Generate (or don't) code for the \s-1GNU\s0 linker. This is the default. -.IP "\fB\-mno\-pic\fR" 4 -.IX Item "-mno-pic" -Generate code that does not use a global pointer register. The result -is not position independent code, and violates the \s-1IA\-64\s0 \s-1ABI\s0. -.IP "\fB\-mvolatile\-asm\-stop\fR" 4 -.IX Item "-mvolatile-asm-stop" -.PD 0 -.IP "\fB\-mno\-volatile\-asm\-stop\fR" 4 -.IX Item "-mno-volatile-asm-stop" -.PD -Generate (or don't) a stop bit immediately before and after volatile asm -statements. -.IP "\fB\-mregister\-names\fR" 4 -.IX Item "-mregister-names" -.PD 0 -.IP "\fB\-mno\-register\-names\fR" 4 -.IX Item "-mno-register-names" -.PD -Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for -the stacked registers. This may make assembler output more readable. -.IP "\fB\-mno\-sdata\fR" 4 -.IX Item "-mno-sdata" -.PD 0 -.IP "\fB\-msdata\fR" 4 -.IX Item "-msdata" -.PD -Disable (or enable) optimizations that use the small data section. This may -be useful for working around optimizer bugs. -.IP "\fB\-mconstant\-gp\fR" 4 -.IX Item "-mconstant-gp" -Generate code that uses a single constant global pointer value. This is -useful when compiling kernel code. -.IP "\fB\-mauto\-pic\fR" 4 -.IX Item "-mauto-pic" -Generate code that is self-relocatable. This implies \fB\-mconstant\-gp\fR. -This is useful when compiling firmware code. -.IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4 -.IX Item "-minline-float-divide-min-latency" -Generate code for inline divides of floating-point values -using the minimum latency algorithm. -.IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4 -.IX Item "-minline-float-divide-max-throughput" -Generate code for inline divides of floating-point values -using the maximum throughput algorithm. -.IP "\fB\-mno\-inline\-float\-divide\fR" 4 -.IX Item "-mno-inline-float-divide" -Do not generate inline code for divides of floating-point values. -.IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4 -.IX Item "-minline-int-divide-min-latency" -Generate code for inline divides of integer values -using the minimum latency algorithm. -.IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4 -.IX Item "-minline-int-divide-max-throughput" -Generate code for inline divides of integer values -using the maximum throughput algorithm. -.IP "\fB\-mno\-inline\-int\-divide\fR" 4 -.IX Item "-mno-inline-int-divide" -Do not generate inline code for divides of integer values. -.IP "\fB\-minline\-sqrt\-min\-latency\fR" 4 -.IX Item "-minline-sqrt-min-latency" -Generate code for inline square roots -using the minimum latency algorithm. -.IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4 -.IX Item "-minline-sqrt-max-throughput" -Generate code for inline square roots -using the maximum throughput algorithm. -.IP "\fB\-mno\-inline\-sqrt\fR" 4 -.IX Item "-mno-inline-sqrt" -Do not generate inline code for \f(CW\*(C`sqrt\*(C'\fR. -.IP "\fB\-mfused\-madd\fR" 4 -.IX Item "-mfused-madd" -.PD 0 -.IP "\fB\-mno\-fused\-madd\fR" 4 -.IX Item "-mno-fused-madd" -.PD -Do (don't) generate code that uses the fused multiply/add or multiply/subtract -instructions. The default is to use these instructions. -.IP "\fB\-mno\-dwarf2\-asm\fR" 4 -.IX Item "-mno-dwarf2-asm" -.PD 0 -.IP "\fB\-mdwarf2\-asm\fR" 4 -.IX Item "-mdwarf2-asm" -.PD -Don't (or do) generate assembler code for the \s-1DWARF\s0 2 line number debugging -info. This may be useful when not using the \s-1GNU\s0 assembler. -.IP "\fB\-mearly\-stop\-bits\fR" 4 -.IX Item "-mearly-stop-bits" -.PD 0 -.IP "\fB\-mno\-early\-stop\-bits\fR" 4 -.IX Item "-mno-early-stop-bits" -.PD -Allow stop bits to be placed earlier than immediately preceding the -instruction that triggered the stop bit. This can improve instruction -scheduling, but does not always do so. -.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 -.IX Item "-mfixed-range=register-range" -Generate code treating the given register range as fixed registers. -A fixed register is one that the register allocator cannot use. This is -useful when compiling kernel code. A register range is specified as -two registers separated by a dash. Multiple register ranges can be -specified separated by a comma. -.IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4 -.IX Item "-mtls-size=tls-size" -Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and -64. -.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 -.IX Item "-mtune=cpu-type" -Tune the instruction scheduling for a particular \s-1CPU\s0, Valid values are -\&\fBitanium\fR, \fBitanium1\fR, \fBmerced\fR, \fBitanium2\fR, -and \fBmckinley\fR. -.IP "\fB\-milp32\fR" 4 -.IX Item "-milp32" -.PD 0 -.IP "\fB\-mlp64\fR" 4 -.IX Item "-mlp64" -.PD -Generate code for a 32\-bit or 64\-bit environment. -The 32\-bit environment sets int, long and pointer to 32 bits. -The 64\-bit environment sets int to 32 bits and long and pointer -to 64 bits. These are HP-UX specific flags. -.IP "\fB\-mno\-sched\-br\-data\-spec\fR" 4 -.IX Item "-mno-sched-br-data-spec" -.PD 0 -.IP "\fB\-msched\-br\-data\-spec\fR" 4 -.IX Item "-msched-br-data-spec" -.PD -(Dis/En)able data speculative scheduling before reload. -This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and -the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR). -The default is 'disable'. -.IP "\fB\-msched\-ar\-data\-spec\fR" 4 -.IX Item "-msched-ar-data-spec" -.PD 0 -.IP "\fB\-mno\-sched\-ar\-data\-spec\fR" 4 -.IX Item "-mno-sched-ar-data-spec" -.PD -(En/Dis)able data speculative scheduling after reload. -This results in generation of \f(CW\*(C`ld.a\*(C'\fR instructions and -the corresponding check instructions (\f(CW\*(C`ld.c\*(C'\fR / \f(CW\*(C`chk.a\*(C'\fR). -The default is 'enable'. -.IP "\fB\-mno\-sched\-control\-spec\fR" 4 -.IX Item "-mno-sched-control-spec" -.PD 0 -.IP "\fB\-msched\-control\-spec\fR" 4 -.IX Item "-msched-control-spec" -.PD -(Dis/En)able control speculative scheduling. This feature is -available only during region scheduling (i.e. before reload). -This results in generation of the \f(CW\*(C`ld.s\*(C'\fR instructions and -the corresponding check instructions \f(CW\*(C`chk.s\*(C'\fR. -The default is 'disable'. -.IP "\fB\-msched\-br\-in\-data\-spec\fR" 4 -.IX Item "-msched-br-in-data-spec" -.PD 0 -.IP "\fB\-mno\-sched\-br\-in\-data\-spec\fR" 4 -.IX Item "-mno-sched-br-in-data-spec" -.PD -(En/Dis)able speculative scheduling of the instructions that -are dependent on the data speculative loads before reload. -This is effective only with \fB\-msched\-br\-data\-spec\fR enabled. -The default is 'enable'. -.IP "\fB\-msched\-ar\-in\-data\-spec\fR" 4 -.IX Item "-msched-ar-in-data-spec" -.PD 0 -.IP "\fB\-mno\-sched\-ar\-in\-data\-spec\fR" 4 -.IX Item "-mno-sched-ar-in-data-spec" +.IP "\fB\-mno\-sched\-ar\-in\-data\-spec\fR" 4 +.IX Item "-mno-sched-ar-in-data-spec" .PD (En/Dis)able speculative scheduling of the instructions that are dependent on the data speculative loads after reload. @@ -16043,7 +15096,7 @@ have to be emulated by software on the 68060. Use this option if your 68060 does not have code to emulate those instructions. .IP "\fB\-mcpu32\fR" 4 .IX Item "-mcpu32" -Generate output for a \s-1CPU32\s0. This is the default +Generate output for a \s-1CPU32. \s0 This is the default when the compiler is configured for CPU32\-based systems. It is equivalent to \fB\-march=cpu32\fR. .Sp @@ -16052,16 +15105,16 @@ Use this option for microcontrollers with a 68336, 68340, 68341, 68349 and 68360. .IP "\fB\-m5200\fR" 4 .IX Item "-m5200" -Generate output for a 520X ColdFire \s-1CPU\s0. This is the default +Generate output for a 520X ColdFire \s-1CPU. \s0 This is the default when the compiler is configured for 520X\-based systems. It is equivalent to \fB\-mcpu=5206\fR, and is now deprecated in favor of that option. .Sp Use this option for microcontroller with a 5200 core, including -the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5206\s0. +the \s-1MCF5202, MCF5203, MCF5204\s0 and \s-1MCF5206.\s0 .IP "\fB\-m5206e\fR" 4 .IX Item "-m5206e" -Generate output for a 5206e ColdFire \s-1CPU\s0. The option is now +Generate output for a 5206e ColdFire \s-1CPU. \s0 The option is now deprecated in favor of the equivalent \fB\-mcpu=5206e\fR. .IP "\fB\-m528x\fR" 4 .IX Item "-m528x" @@ -16070,15 +15123,15 @@ The option is now deprecated in favor of the equivalent \&\fB\-mcpu=528x\fR. .IP "\fB\-m5307\fR" 4 .IX Item "-m5307" -Generate output for a ColdFire 5307 \s-1CPU\s0. The option is now deprecated +Generate output for a ColdFire 5307 \s-1CPU. \s0 The option is now deprecated in favor of the equivalent \fB\-mcpu=5307\fR. .IP "\fB\-m5407\fR" 4 .IX Item "-m5407" -Generate output for a ColdFire 5407 \s-1CPU\s0. The option is now deprecated +Generate output for a ColdFire 5407 \s-1CPU. \s0 The option is now deprecated in favor of the equivalent \fB\-mcpu=5407\fR. .IP "\fB\-mcfv4e\fR" 4 .IX Item "-mcfv4e" -Generate output for a ColdFire V4e family \s-1CPU\s0 (e.g. 547x/548x). +Generate output for a ColdFire V4e family \s-1CPU \s0(e.g. 547x/548x). This includes use of hardware floating-point instructions. The option is equivalent to \fB\-mcpu=547x\fR, and is now deprecated in favor of that option. @@ -16105,14 +15158,14 @@ The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-60\fR. .IX Item "-m68881" .PD Generate floating-point instructions. This is the default for 68020 -and above, and for ColdFire devices that have an \s-1FPU\s0. It defines the +and above, and for ColdFire devices that have an \s-1FPU. \s0 It defines the macro \f(CW\*(C`_\|_HAVE_68881_\|_\*(C'\fR on M680x0 targets and \f(CW\*(C`_\|_mcffpu_\|_\*(C'\fR on ColdFire targets. .IP "\fB\-msoft\-float\fR" 4 .IX Item "-msoft-float" Do not generate floating-point instructions; use library calls instead. This is the default for 68000, 68010, and 68832 targets. It is also -the default for ColdFire devices that have no \s-1FPU\s0. +the default for ColdFire devices that have no \s-1FPU.\s0 .IP "\fB\-mdiv\fR" 4 .IX Item "-mdiv" .PD 0 @@ -16122,8 +15175,8 @@ the default for ColdFire devices that have no \s-1FPU\s0. Generate (do not generate) ColdFire hardware divide and remainder instructions. If \fB\-march\fR is used without \fB\-mcpu\fR, the default is \*(L"on\*(R" for ColdFire architectures and \*(L"off\*(R" for M680x0 -architectures. Otherwise, the default is taken from the target \s-1CPU\s0 -(either the default \s-1CPU\s0, or the one specified by \fB\-mcpu\fR). For +architectures. Otherwise, the default is taken from the target \s-1CPU +\&\s0(either the default \s-1CPU,\s0 or the one specified by \fB\-mcpu\fR). For example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for \&\fB\-mcpu=5206e\fR. .Sp @@ -16242,7 +15295,7 @@ that works if the \s-1GOT\s0 has more than 8192 entries. This code is larger and slower than code generated without this option. On M680x0 processors, this option is not needed; \fB\-fPIC\fR suffices. .Sp -\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT.\s0 While this is relatively efficient, it only works if the \s-1GOT\s0 is smaller than about 64k. Anything larger causes the linker to report an error such as: @@ -16384,7 +15437,7 @@ useful unless you also provide \fB\-mminmax\fR. Selects one of the built-in core configurations. Each MeP chip has one or more modules in it; each module has a core \s-1CPU\s0 and a variety of coprocessors, optional instructions, and peripherals. The -\&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC\s0, provides these +\&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC,\s0 provides these configurations through this option; using this option is the same as using all the corresponding command-line options. The default configuration is \fBdefault\fR. @@ -16487,7 +15540,7 @@ Do not optimize block moves, use \f(CW\*(C`memcpy\*(C'\fR. This option is deprecated. Use \fB\-fno\-zero\-initialized\-in\-bss\fR instead. .IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 .IX Item "-mcpu=cpu-type" -Use features of, and schedule code for, the given \s-1CPU\s0. +Use features of, and schedule code for, the given \s-1CPU.\s0 Supported values are in the format \fBv\fR\fIX\fR\fB.\fR\fI\s-1YY\s0\fR\fB.\fR\fIZ\fR, where \fIX\fR is a major version, \fI\s-1YY\s0\fR is the minor version, and \&\fIZ\fR is compatibility code. Example values are \fBv3.00.a\fR, @@ -16573,7 +15626,7 @@ configurations. .IP "\fB\-march=\fR\fIarch\fR" 4 .IX Item "-march=arch" Generate code that runs on \fIarch\fR, which can be the name of a -generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor. +generic \s-1MIPS ISA,\s0 or the name of a particular processor. The \s-1ISA\s0 names are: \&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR, \&\fBmips32\fR, \fBmips32r2\fR, \fBmips32r3\fR, \fBmips32r5\fR, @@ -16605,7 +15658,7 @@ The processor names are: \&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR, \&\fBxlr\fR and \fBxlp\fR. The special value \fBfrom-abi\fR selects the -most compatible architecture for the selected \s-1ABI\s0 (that is, +most compatible architecture for the selected \s-1ABI \s0(that is, \&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs). .Sp The native Linux/GNU toolchain also supports the value \fBnative\fR, @@ -16701,7 +15754,7 @@ Equivalent to \fB\-march=mips64r6\fR. .IX Item "-mno-mips16" .PD Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targeting a -\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it makes use of the MIPS16e \s-1ASE\s0. +\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it makes use of the MIPS16e \s-1ASE.\s0 .Sp \&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes. @@ -16716,7 +15769,7 @@ not intended for ordinary use in compiling user code. .IP "\fB\-mno\-interlink\-compressed\fR" 4 .IX Item "-mno-interlink-compressed" .PD -Require (do not require) that code using the standard (uncompressed) \s-1MIPS\s0 \s-1ISA\s0 +Require (do not require) that code using the standard (uncompressed) \s-1MIPS ISA\s0 be link-compatible with \s-1MIPS16\s0 and microMIPS code, and vice versa. .Sp For example, code using the standard \s-1ISA\s0 encoding cannot jump directly @@ -16744,20 +15797,20 @@ and are retained for backwards compatibility. .IP "\fB\-mabi=eabi\fR" 4 .IX Item "-mabi=eabi" .PD -Generate code for the given \s-1ABI\s0. +Generate code for the given \s-1ABI.\s0 .Sp Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant. \s-1GCC\s0 normally generates 64\-bit code when you select a 64\-bit architecture, but you can use \fB\-mgp32\fR to get 32\-bit code instead. .Sp -For information about the O64 \s-1ABI\s0, see +For information about the O64 \s-1ABI,\s0 see <\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>. .Sp \&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers are 64 rather than 32 bits wide. You can select this combination with \&\fB\-mabi=32\fR \fB\-mfp64\fR. This \s-1ABI\s0 relies on the \f(CW\*(C`mthc1\*(C'\fR and \f(CW\*(C`mfhc1\*(C'\fR instructions and is therefore only supported for -\&\s-1MIPS32R2\s0, \s-1MIPS32R3\s0 and \s-1MIPS32R5\s0 processors. +\&\s-1MIPS32R2, MIPS32R3\s0 and \s-1MIPS32R5\s0 processors. .Sp The register assignments for arguments and return values remain the same, but each scalar value is passed in a single 64\-bit register @@ -16768,11 +15821,11 @@ remains the same in that the even-numbered double-precision registers are saved. .Sp Two additional variants of the o32 \s-1ABI\s0 are supported to enable -a transition from 32\-bit to 64\-bit registers. These are \s-1FPXX\s0 -(\fB\-mfpxx\fR) and \s-1FP64A\s0 (\fB\-mfp64\fR \fB\-mno\-odd\-spreg\fR). +a transition from 32\-bit to 64\-bit registers. These are \s-1FPXX +\&\s0(\fB\-mfpxx\fR) and \s-1FP64A \s0(\fB\-mfp64\fR \fB\-mno\-odd\-spreg\fR). The \s-1FPXX\s0 extension mandates that all code must execute correctly when run using 32\-bit or 64\-bit registers. The code can be interlinked -with either \s-1FP32\s0 or \s-1FP64\s0, but not both. +with either \s-1FP32\s0 or \s-1FP64,\s0 but not both. The \s-1FP64A\s0 extension is similar to the \s-1FP64\s0 extension but forbids the use of odd-numbered single-precision registers. This can be used in conjunction with the \f(CW\*(C`FRE\*(C'\fR mode of FPUs in \s-1MIPS32R5\s0 @@ -16819,7 +15872,7 @@ executables both smaller and quicker. .PD Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations. This option only affects -\&\fB\-mno\-shared \-mabicalls\fR. For the n64 \s-1ABI\s0, this option +\&\fB\-mno\-shared \-mabicalls\fR. For the n64 \s-1ABI,\s0 this option has no effect without \fB\-msym32\fR. .Sp You can make \fB\-mplt\fR the default by configuring @@ -16834,7 +15887,7 @@ You can make \fB\-mplt\fR the default by configuring Lift (do not lift) the usual restrictions on the size of the global offset table. .Sp -\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. +\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT.\s0 While this is relatively efficient, it only works if the \s-1GOT\s0 is smaller than about 64k. Anything larger causes the linker to report an error such as: @@ -16902,8 +15955,8 @@ operations. This is the default. .IX Item "-mno-odd-spreg" .PD Enable the use of odd-numbered single-precision floating-point registers -for the o32 \s-1ABI\s0. This is the default for processors that are known to -support these registers. When using the o32 \s-1FPXX\s0 \s-1ABI\s0, \fB\-mno\-odd\-spreg\fR +for the o32 \s-1ABI. \s0 This is the default for processors that are known to +support these registers. When using the o32 \s-1FPXX ABI, \s0\fB\-mno\-odd\-spreg\fR is set by default. .IP "\fB\-mabs=2008\fR" 4 .IX Item "-mabs=2008" @@ -16912,10 +15965,10 @@ is set by default. .IX Item "-mabs=legacy" .PD These options control the treatment of the special not-a-number (NaN) -\&\s-1IEEE\s0 754 floating-point data with the \f(CW\*(C`abs.\f(CIfmt\f(CW\*(C'\fR and +\&\s-1IEEE 754\s0 floating-point data with the \f(CW\*(C`abs.\f(CIfmt\f(CW\*(C'\fR and \&\f(CW\*(C`neg.\f(CIfmt\f(CW\*(C'\fR machine instructions. .Sp -By default or when the \fB\-mabs=legacy\fR is used the legacy +By default or when \fB\-mabs=legacy\fR is used the legacy treatment is selected. In this case these instructions are considered arithmetic and avoided where correct operation is required and the input operand might be a NaN. A longer sequence of instructions that @@ -16923,7 +15976,7 @@ manipulate the sign bit of floating-point datum manually is used instead unless the \fB\-ffinite\-math\-only\fR option has also been specified. .Sp -The \fB\-mabs=2008\fR option selects the \s-1IEEE\s0 754\-2008 treatment. In +The \fB\-mabs=2008\fR option selects the \s-1IEEE 754\-2008\s0 treatment. In this case these instructions are considered non-arithmetic and therefore operating correctly in all cases, including in particular where the input operand is a NaN. These instructions are therefore always used @@ -16935,14 +15988,14 @@ for the respective operations. .IX Item "-mnan=legacy" .PD These options control the encoding of the special not-a-number (NaN) -\&\s-1IEEE\s0 754 floating-point data. +\&\s-1IEEE 754\s0 floating-point data. .Sp The \fB\-mnan=legacy\fR option selects the legacy encoding. In this case quiet NaNs (qNaNs) are denoted by the first bit of their trailing significand field being 0, whereas signalling NaNs (sNaNs) are denoted by the first bit of their trailing significand field being 1. .Sp -The \fB\-mnan=2008\fR option selects the \s-1IEEE\s0 754\-2008 encoding. In +The \fB\-mnan=2008\fR option selects the \s-1IEEE 754\-2008\s0 encoding. In this case qNaNs are denoted by the first bit of their trailing significand field being 1, whereas sNaNs are denoted by the first bit of their trailing significand field being 0. @@ -16972,8 +16025,8 @@ configurations; see the installation documentation for details. .IP "\fB\-mno\-dsp\fR" 4 .IX Item "-mno-dsp" .PD -Use (do not use) revision 1 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. - This option defines the +Use (do not use) revision 1 of the \s-1MIPS DSP ASE. + \s0 This option defines the preprocessor macro \f(CW\*(C`_\|_mips_dsp\*(C'\fR. It also defines \&\f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 1. .IP "\fB\-mdspr2\fR" 4 @@ -16982,8 +16035,8 @@ preprocessor macro \f(CW\*(C`_\|_mips_dsp\*(C'\fR. It also defines .IP "\fB\-mno\-dspr2\fR" 4 .IX Item "-mno-dspr2" .PD -Use (do not use) revision 2 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. - This option defines the +Use (do not use) revision 2 of the \s-1MIPS DSP ASE. + \s0 This option defines the preprocessor macros \f(CW\*(C`_\|_mips_dsp\*(C'\fR and \f(CW\*(C`_\|_mips_dspr2\*(C'\fR. It also defines \f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 2. .IP "\fB\-msmartmips\fR" 4 @@ -16992,7 +16045,7 @@ It also defines \f(CW\*(C`_\|_mips_dsp_rev\*(C'\fR to 2. .IP "\fB\-mno\-smartmips\fR" 4 .IX Item "-mno-smartmips" .PD -Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE\s0. +Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE.\s0 .IP "\fB\-mpaired\-single\fR" 4 .IX Item "-mpaired-single" .PD 0 @@ -17017,7 +16070,7 @@ hardware floating-point support to be enabled. .IP "\fB\-mno\-mips3d\fR" 4 .IX Item "-mno-mips3d" .PD -Use (do not use) the \s-1MIPS\-3D\s0 \s-1ASE\s0. +Use (do not use) the \s-1MIPS\-3D ASE. \s0 The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR. .IP "\fB\-mmicromips\fR" 4 .IX Item "-mmicromips" @@ -17042,7 +16095,7 @@ Use (do not use) \s-1MT\s0 Multithreading instructions. .IP "\fB\-mno\-mcu\fR" 4 .IX Item "-mno-mcu" .PD -Use (do not use) the \s-1MIPS\s0 \s-1MCU\s0 \s-1ASE\s0 instructions. +Use (do not use) the \s-1MIPS MCU ASE\s0 instructions. .IP "\fB\-meva\fR" 4 .IX Item "-meva" .PD 0 @@ -17074,7 +16127,7 @@ determined. Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide. .Sp The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on -the \s-1ABI\s0. All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 +the \s-1ABI. \s0 All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use 32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs, or the same size as integer registers, whichever is smaller. @@ -17085,7 +16138,7 @@ or the same size as integer registers, whichever is smaller. .IX Item "-mno-sym32" .PD Assume (do not assume) that all symbols have 32\-bit values, regardless -of the selected \s-1ABI\s0. This option is useful in combination with +of the selected \s-1ABI. \s0 This option is useful in combination with \&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0 to generate shorter and faster references to symbolic addresses. .IP "\fB\-G\fR \fInum\fR" 4 @@ -17190,13 +16243,13 @@ but other instructions must not do so. This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit set. It is also useful on processors that can be configured to have a dual instruction/data \s-1SRAM\s0 interface and that, like the M4K, automatically -redirect PC-relative loads to the instruction \s-1RAM\s0. +redirect PC-relative loads to the instruction \s-1RAM.\s0 .IP "\fB\-mcode\-readable=no\fR" 4 .IX Item "-mcode-readable=no" Instructions must not access executable sections. This option can be useful on targets that are configured to have a dual instruction/data \&\s-1SRAM\s0 interface but that (unlike the M4K) do not automatically redirect -PC-relative loads to the instruction \s-1RAM\s0. +PC-relative loads to the instruction \s-1RAM.\s0 .RE .RS 4 .RE @@ -17238,7 +16291,7 @@ The default is \fB\-mcheck\-zero\-division\fR. .PD \&\s-1MIPS\s0 systems check for division by zero by generating either a conditional trap or a break instruction. Using traps results in -smaller code, but is only supported on \s-1MIPS\s0 \s-1II\s0 and later. Also, some +smaller code, but is only supported on \s-1MIPS II\s0 and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR). Use \fB\-mdivide\-traps\fR to allow conditional traps on architectures that support them and @@ -17254,7 +16307,7 @@ Divide-by-zero checks can be completely disabled using .IP "\fB\-mno\-memcpy\fR" 4 .IX Item "-mno-memcpy" .PD -Force (do not force) the use of \f(CW\*(C`memcpy()\*(C'\fR for non-trivial block +Force (do not force) the use of \f(CW\*(C`memcpy\*(C'\fR for non-trivial block moves. The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline most constant-sized copies. .IP "\fB\-mlong\-calls\fR" 4 @@ -17276,7 +16329,7 @@ This option has no effect on abicalls code. The default is .IX Item "-mno-mad" .PD Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR -instructions, as provided by the R4650 \s-1ISA\s0. +instructions, as provided by the R4650 \s-1ISA.\s0 .IP "\fB\-mimadd\fR" 4 .IX Item "-mimadd" .PD 0 @@ -17314,7 +16367,7 @@ assembler files (with a \fB.s\fR suffix) when assembling them. .IX Item "-mno-fix-24k" .PD Work around the 24K E48 (lost data on stores during refill) errata. -The workarounds are implemented by the assembler rather than by \s-1GCC\s0. +The workarounds are implemented by the assembler rather than by \s-1GCC.\s0 .IP "\fB\-mfix\-r4000\fR" 4 .IX Item "-mfix-r4000" .PD 0 @@ -17374,8 +16427,8 @@ otherwise. .IP "\fB\-mno\-fix\-rm7000\fR" 4 .IX Item "-mno-fix-rm7000" .PD -Work around the \s-1RM7000\s0 \f(CW\*(C`dmult\*(C'\fR/\f(CW\*(C`dmultu\*(C'\fR errata. The -workarounds are implemented by the assembler rather than by \s-1GCC\s0. +Work around the \s-1RM7000 \s0\f(CW\*(C`dmult\*(C'\fR/\f(CW\*(C`dmultu\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC.\s0 .IP "\fB\-mfix\-vr4120\fR" 4 .IX Item "-mfix-vr4120" .PD 0 @@ -17401,10 +16454,10 @@ instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itse .RE .IP "\fB\-mfix\-vr4130\fR" 4 .IX Item "-mfix-vr4130" -Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The -workarounds are implemented by the assembler rather than by \s-1GCC\s0, +Work around the \s-1VR4130 \s0\f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The +workarounds are implemented by the assembler rather than by \s-1GCC,\s0 although \s-1GCC\s0 avoids using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the -\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR +\&\s-1VR4130 \s0\f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR instructions are available instead. .IP "\fB\-mfix\-sb1\fR" 4 .IX Item "-mfix-sb1" @@ -17412,7 +16465,7 @@ instructions are available instead. .IP "\fB\-mno\-fix\-sb1\fR" 4 .IX Item "-mno-fix-sb1" .PD -Work around certain \s-1SB\-1\s0 \s-1CPU\s0 core errata. +Work around certain \s-1SB\-1 CPU\s0 core errata. (This flag currently works around the \s-1SB\-1\s0 revision 2 \&\*(L"F1\*(R" and \*(L"F2\*(R" floating-point errata.) .IP "\fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR" 4 @@ -17491,7 +16544,7 @@ Disable the insertion of cache barriers. This is the default setting. .PD Specifies the function to call to flush the I and D caches, or to not call any such function. If called, the function must take the same -arguments as the common \f(CW\*(C`_flush_func()\*(C'\fR, that is, the address of the +arguments as the common \f(CW\*(C`_flush_func\*(C'\fR, that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target \s-1GCC\s0 was configured for, but commonly is either @@ -17526,7 +16579,7 @@ Specifies whether \s-1FP\s0 exceptions are enabled. This affects how The default is that \s-1FP\s0 exceptions are enabled. .Sp -For instance, on the \s-1SB\-1\s0, if \s-1FP\s0 exceptions are disabled, and we are emitting +For instance, on the \s-1SB\-1,\s0 if \s-1FP\s0 exceptions are disabled, and we are emitting 64\-bit code, then we can use both \s-1FP\s0 pipes. Otherwise, we can only use one \&\s-1FP\s0 pipe. .IP "\fB\-mvr4130\-align\fR" 4 @@ -17540,7 +16593,7 @@ instructions together if the first one is 8\-byte aligned. When this option is enabled, \s-1GCC\s0 aligns pairs of instructions that it thinks should execute in parallel. .Sp -This option only has an effect when optimizing for the \s-1VR4130\s0. +This option only has an effect when optimizing for the \s-1VR4130.\s0 It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level \fB\-O3\fR. .IP "\fB\-msynci\fR" 4 @@ -17551,7 +16604,7 @@ It is enabled by default at optimization level \fB\-O3\fR. .PD Enable (disable) generation of \f(CW\*(C`synci\*(C'\fR instructions on architectures that support it. The \f(CW\*(C`synci\*(C'\fR instructions (if -enabled) are generated when \f(CW\*(C`_\|_builtin_\|_\|_clear_cache()\*(C'\fR is +enabled) are generated when \f(CW\*(C`_\|_builtin_\|_\|_clear_cache\*(C'\fR is compiled. .Sp This option defaults to \fB\-mno\-synci\fR, but the default can be @@ -17629,7 +16682,7 @@ to the \f(CW\*(C`rE\*(C'\fR epsilon register. .PD Generate code that passes function parameters and return values that (in the called function) are seen as registers \f(CW$0\fR and up, as opposed to -the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW$231\fR and up. +the \s-1GNU ABI\s0 which uses global registers \f(CW$231\fR and up. .IP "\fB\-mzero\-extend\fR" 4 .IX Item "-mzero-extend" .PD 0 @@ -17713,7 +16766,7 @@ Do not generate code using features specific to the \s-1AM33\s0 processor. This is the default. .IP "\fB\-mam33\-2\fR" 4 .IX Item "-mam33-2" -Generate code using features specific to the \s-1AM33/2\s0.0 processor. +Generate code using features specific to the \s-1AM33/2.0\s0 processor. .IP "\fB\-mam34\fR" 4 .IX Item "-mam34" Generate code using features specific to the \s-1AM34\s0 processor. @@ -17798,8 +16851,8 @@ header file. The option also sets the \s-1ISA\s0 to use. If the \s-1MCU\s0 name is one that is known to only support the 430 \s-1ISA\s0 then that is selected, otherwise the 430X \s-1ISA\s0 is selected. A generic \s-1MCU\s0 name of \fBmsp430\fR can also be -used to select the 430 \s-1ISA\s0. Similarly the generic \fBmsp430x\fR \s-1MCU\s0 -name selects the 430X \s-1ISA\s0. +used to select the 430 \s-1ISA. \s0 Similarly the generic \fBmsp430x\fR \s-1MCU\s0 +name selects the 430X \s-1ISA.\s0 .Sp In addition an MCU-specific linker script is added to the linker command line. The script's name is the name of the \s-1MCU\s0 with @@ -17812,7 +16865,7 @@ This option is also passed on to the assembler. .IX Item "-mcpu=" Specifies the \s-1ISA\s0 to use. Accepted values are \fBmsp430\fR, \&\fBmsp430x\fR and \fBmsp430xv2\fR. This option is deprecated. The -\&\fB\-mmcu=\fR option should be used to select the \s-1ISA\s0. +\&\fB\-mmcu=\fR option should be used to select the \s-1ISA.\s0 .IP "\fB\-msim\fR" 4 .IX Item "-msim" Link to the simulator runtime libraries and linker script. Overrides @@ -17896,12 +16949,6 @@ Generate 16\-bit instructions. .IP "\fB\-mno\-16\-bit\fR" 4 .IX Item "-mno-16-bit" Do not generate 16\-bit instructions. -.IP "\fB\-mgp\-direct\fR" 4 -.IX Item "-mgp-direct" -Generate \s-1GP\s0 base instructions directly. -.IP "\fB\-mno\-gp\-direct\fR" 4 -.IX Item "-mno-gp-direct" -Do no generate \s-1GP\s0 base instructions directly. .IP "\fB\-misr\-vector\-size=\fR\fInum\fR" 4 .IX Item "-misr-vector-size=num" Specify the size of each interrupt vector, which must be 4 or 16. @@ -17912,18 +16959,25 @@ which must be a power of 2 between 4 and 512. .IP "\fB\-march=\fR\fIarch\fR" 4 .IX Item "-march=arch" Specify the name of the target architecture. -.IP "\fB\-mforce\-fp\-as\-gp\fR" 4 -.IX Item "-mforce-fp-as-gp" -Prevent \f(CW$fp\fR being allocated during register allocation so that compiler -is able to force performing fp-as-gp optimization. -.IP "\fB\-mforbid\-fp\-as\-gp\fR" 4 -.IX Item "-mforbid-fp-as-gp" -Forbid using \f(CW$fp\fR to access static and global variables. -This option strictly forbids fp-as-gp optimization -regardless of \fB\-mforce\-fp\-as\-gp\fR. -.IP "\fB\-mex9\fR" 4 -.IX Item "-mex9" -Use special directives to guide linker doing ex9 optimization. +.IP "\fB\-mcmodel=\fR\fIcode-model\fR" 4 +.IX Item "-mcmodel=code-model" +Set the code model to one of +.RS 4 +.IP "\fBsmall\fR" 4 +.IX Item "small" +All the data and read-only data segments must be within 512KB addressing space. +The text segment must be within 16MB addressing space. +.IP "\fBmedium\fR" 4 +.IX Item "medium" +The data segment must be within 512KB while the read-only data segment can be +within 4GB addressing space. The text segment should be still within 16MB +addressing space. +.IP "\fBlarge\fR" 4 +.IX Item "large" +All the text and data segments can be within 4GB addressing space. +.RE +.RS 4 +.RE .IP "\fB\-mctor\-dtor\fR" 4 .IX Item "-mctor-dtor" Enable constructor/destructor feature. @@ -17940,23 +16994,63 @@ These are the options defined for the Altera Nios \s-1II\s0 processor. Put global and static objects less than or equal to \fInum\fR bytes into the small data or \s-1BSS\s0 sections instead of the normal data or \s-1BSS\s0 sections. The default value of \fInum\fR is 8. +.IP "\fB\-mgpopt=\fR\fIoption\fR" 4 +.IX Item "-mgpopt=option" +.PD 0 .IP "\fB\-mgpopt\fR" 4 .IX Item "-mgpopt" -.PD 0 .IP "\fB\-mno\-gpopt\fR" 4 .IX Item "-mno-gpopt" .PD -Generate (do not generate) GP-relative accesses for objects in the -small data or \s-1BSS\s0 sections. The default is \fB\-mgpopt\fR except -when \fB\-fpic\fR or \fB\-fPIC\fR is specified to generate -position-independent code. Note that the Nios \s-1II\s0 \s-1ABI\s0 does not permit -GP-relative accesses from shared libraries. +Generate (do not generate) GP-relative accesses. The following +\&\fIoption\fR names are recognized: +.RS 4 +.IP "\fBnone\fR" 4 +.IX Item "none" +Do not generate GP-relative accesses. +.IP "\fBlocal\fR" 4 +.IX Item "local" +Generate GP-relative accesses for small data objects that are not +external or weak. Also use GP-relative addressing for objects that +have been explicitly placed in a small data section via a \f(CW\*(C`section\*(C'\fR +attribute. +.IP "\fBglobal\fR" 4 +.IX Item "global" +As for \fBlocal\fR, but also generate GP-relative accesses for +small data objects that are external or weak. If you use this option, +you must ensure that all parts of your program (including libraries) are +compiled with the same \fB\-G\fR setting. +.IP "\fBdata\fR" 4 +.IX Item "data" +Generate GP-relative accesses for all data objects in the program. If you +use this option, the entire data and \s-1BSS\s0 segments +of your program must fit in 64K of memory and you must use an appropriate +linker script to allocate them within the addressible range of the +global pointer. +.IP "\fBall\fR" 4 +.IX Item "all" +Generate GP-relative addresses for function pointers as well as data +pointers. If you use this option, the entire text, data, and \s-1BSS\s0 segments +of your program must fit in 64K of memory and you must use an appropriate +linker script to allocate them within the addressible range of the +global pointer. +.RE +.RS 4 +.Sp +\&\fB\-mgpopt\fR is equivalent to \fB\-mgpopt=local\fR, and +\&\fB\-mno\-gpopt\fR is equivalent to \fB\-mgpopt=none\fR. +.Sp +The default is \fB\-mgpopt\fR except when \fB\-fpic\fR or +\&\fB\-fPIC\fR is specified to generate position-independent code. +Note that the Nios \s-1II ABI\s0 does not permit GP-relative accesses from +shared libraries. .Sp You may need to specify \fB\-mno\-gpopt\fR explicitly when building programs that include large amounts of small data, including large \&\s-1GOT\s0 data sections. In this case, the 16\-bit offset for GP-relative addressing may not be large enough to allow access to the entire small data section. +.RE .IP "\fB\-mel\fR" 4 .IX Item "-mel" .PD 0 @@ -18021,7 +17115,7 @@ of the default behavior of using a library call. .Sp The following values of \fIinsn\fR are supported. Except as otherwise noted, floating-point operations are expected to be implemented with -normal \s-1IEEE\s0 754 semantics and correspond directly to the C operators or the +normal \s-1IEEE 754\s0 semantics and correspond directly to the C operators or the equivalent \s-1GCC\s0 built-in functions. .Sp Single-precision floating point: @@ -18180,14 +17274,14 @@ configuration by using the \f(CW\*(C`target("custom\-fpu\-cfg=\f(CIname\f(CW")\* function attribute or pragma. .PP -These additional \fB\-m\fR options are available for the Altera Nios \s-1II\s0 -\&\s-1ELF\s0 (bare-metal) target: +These additional \fB\-m\fR options are available for the Altera Nios \s-1II +ELF \s0(bare-metal) target: .IP "\fB\-mhal\fR" 4 .IX Item "-mhal" -Link with \s-1HAL\s0 \s-1BSP\s0. This suppresses linking with the GCC-provided C runtime +Link with \s-1HAL BSP. \s0 This suppresses linking with the GCC-provided C runtime startup and termination code, and is typically used in conjunction with \&\fB\-msys\-crt0=\fR to specify the location of the alternate startup code -provided by the \s-1HAL\s0 \s-1BSP\s0. +provided by the \s-1HAL BSP.\s0 .IP "\fB\-msmallc\fR" 4 .IX Item "-msmallc" Link with a limited version of the C library, \fB\-lsmallc\fR, rather than @@ -18201,7 +17295,23 @@ when linking. This option is only useful in conjunction with \fB\-mhal\fR. \&\fIsystemlib\fR is the library name of the library that provides low-level system calls required by the C library, e.g. \f(CW\*(C`read\*(C'\fR and \f(CW\*(C`write\*(C'\fR. -This option is typically used to link with a library provided by a \s-1HAL\s0 \s-1BSP\s0. +This option is typically used to link with a library provided by a \s-1HAL BSP.\s0 +.PP +\fINvidia \s-1PTX\s0 Options\fR +.IX Subsection "Nvidia PTX Options" +.PP +These options are defined for Nvidia \s-1PTX:\s0 +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for 32\-bit or 64\-bit \s-1ABI.\s0 +.IP "\fB\-mmainkernel\fR" 4 +.IX Item "-mmainkernel" +Link in code for a _\|_main kernel. This is for stand-alone instead of +offloading execution. .PP \fI\s-1PDP\-11\s0 Options\fR .IX Subsection "PDP-11 Options" @@ -18222,13 +17332,13 @@ Return floating-point results in ac0 (fr0 in Unix assembler syntax). Return floating-point results in memory. This is the default. .IP "\fB\-m40\fR" 4 .IX Item "-m40" -Generate code for a \s-1PDP\-11/40\s0. +Generate code for a \s-1PDP\-11/40.\s0 .IP "\fB\-m45\fR" 4 .IX Item "-m45" -Generate code for a \s-1PDP\-11/45\s0. This is the default. +Generate code for a \s-1PDP\-11/45. \s0 This is the default. .IP "\fB\-m10\fR" 4 .IX Item "-m10" -Generate code for a \s-1PDP\-11/10\s0. +Generate code for a \s-1PDP\-11/10.\s0 .IP "\fB\-mbcopy\-builtin\fR" 4 .IX Item "-mbcopy-builtin" Use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory. This is the @@ -18300,14 +17410,14 @@ for \fIae_type\fR are \fB\s-1ANY\s0\fR, \fB\s-1MUL\s0\fR, and \fB\s-1MAC\s0\fR. generated with this option runs on any of the other \s-1AE\s0 types. The code is not as efficient as it would be if compiled for a specific \&\s-1AE\s0 type, and some types of operation (e.g., multiplication) do not -work properly on all types of \s-1AE\s0. +work properly on all types of \s-1AE.\s0 .Sp -\&\fB\-mae=MUL\fR selects a \s-1MUL\s0 \s-1AE\s0 type. This is the most useful \s-1AE\s0 type +\&\fB\-mae=MUL\fR selects a \s-1MUL AE\s0 type. This is the most useful \s-1AE\s0 type for compiled code, and is the default. .Sp -\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC\s0 \s-1AE\s0. Code compiled with this +\&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC AE. \s0 Code compiled with this option may suffer from poor performance of byte (char) manipulation, -since the \s-1DSP\s0 \s-1AE\s0 does not provide hardware support for byte load/stores. +since the \s-1DSP AE\s0 does not provide hardware support for byte load/stores. .IP "\fB\-msymbol\-as\-address\fR" 4 .IX Item "-msymbol-as-address" Enable the compiler to directly use a symbol name as an address in a @@ -18320,7 +17430,7 @@ rather than being permanently enabled. .IX Item "-mno-inefficient-warnings" Disables warnings about the generation of inefficient code. These warnings can be generated, for example, when compiling code that -performs byte-level memory operations on the \s-1MAC\s0 \s-1AE\s0 type. The \s-1MAC\s0 \s-1AE\s0 has +performs byte-level memory operations on the \s-1MAC AE\s0 type. The \s-1MAC AE\s0 has no hardware support for byte-level memory operations, so all byte load/stores must be synthesized from word load/store operations. This is inefficient and a warning is generated to indicate @@ -18362,10 +17472,10 @@ Make the \f(CW\*(C`double\*(C'\fR data type be 64 bits (\fB\-m64bit\-doubles\fR) or 32 bits (\fB\-m32bit\-doubles\fR) in size. The default is \&\fB\-m32bit\-doubles\fR. .PP -\fI\s-1IBM\s0 \s-1RS/6000\s0 and PowerPC Options\fR +\fI\s-1IBM RS/6000\s0 and PowerPC Options\fR .IX Subsection "IBM RS/6000 and PowerPC Options" .PP -These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerPC: +These \fB\-m\fR options are defined for the \s-1IBM RS/6000\s0 and PowerPC: .IP "\fB\-mpowerpc\-gpopt\fR" 4 .IX Item "-mpowerpc-gpopt" .PD 0 @@ -18410,7 +17520,7 @@ These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerP .PD You use these options to specify which instructions are available on the processor you are using. The default value of these options is -determined when configuring \s-1GCC\s0. Specifying the +determined when configuring \s-1GCC. \s0 Specifying the \&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these options. We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option rather than the options listed above. @@ -18464,12 +17574,13 @@ Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR, \&\fBe6500\fR, \fBec603e\fR, \fBG3\fR, \fBG4\fR, \fBG5\fR, \&\fBtitan\fR, \fBpower3\fR, \fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, \&\fBpower6\fR, \fBpower6x\fR, \fBpower7\fR, \fBpower8\fR, \fBpowerpc\fR, -\&\fBpowerpc64\fR, and \fBrs64\fR. +\&\fBpowerpc64\fR, \fBpowerpc64le\fR, and \fBrs64\fR. .Sp -\&\fB\-mcpu=powerpc\fR, and \fB\-mcpu=powerpc64\fR specify pure 32\-bit -PowerPC and 64\-bit PowerPC architecture machine -types, with an appropriate, generic processor model assumed for -scheduling purposes. +\&\fB\-mcpu=powerpc\fR, \fB\-mcpu=powerpc64\fR, and +\&\fB\-mcpu=powerpc64le\fR specify pure 32\-bit PowerPC (either +endian), 64\-bit big endian PowerPC and 64\-bit little endian PowerPC +architecture machine types, with an appropriate, generic processor +model assumed for scheduling purposes. .Sp The other options specify a specific processor. Code generated under those options runs best on that processor, and may not run at all on @@ -18492,7 +17603,7 @@ capabilities. If you wish to set an individual option to a particular value, you may specify it after the \fB\-mcpu\fR option, like \&\fB\-mcpu=970 \-mno\-altivec\fR. .Sp -On \s-1AIX\s0, the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are +On \s-1AIX,\s0 the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are not enabled or disabled by the \fB\-mcpu\fR option at present because \&\s-1AIX\s0 does not have full support for these options. You may still enable or disable them individually if you're sure it'll work in your @@ -18580,14 +17691,14 @@ Generate code that allows \fBld\fR and \fBld.so\fR to build executables and shared libraries with non-executable \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR sections. This is a PowerPC -32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. +32\-bit \s-1SYSV ABI\s0 option. .IP "\fB\-mbss\-plt\fR" 4 .IX Item "-mbss-plt" -Generate code that uses a \s-1BSS\s0 \f(CW\*(C`.plt\*(C'\fR section that \fBld.so\fR +Generate code that uses a \s-1BSS \s0\f(CW\*(C`.plt\*(C'\fR section that \fBld.so\fR fills in, and requires \f(CW\*(C`.plt\*(C'\fR and \f(CW\*(C`.got\*(C'\fR sections that are both writable and executable. -This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. +This is a PowerPC 32\-bit \s-1SYSV ABI\s0 option. .IP "\fB\-misel\fR" 4 .IX Item "-misel" .PD 0 @@ -18636,7 +17747,7 @@ more direct access to the \s-1VSX\s0 instruction set. .PD Enable the use (disable) of the built-in functions that allow direct access to the cryptographic instructions that were added in version -2.07 of the PowerPC \s-1ISA\s0. +2.07 of the PowerPC \s-1ISA.\s0 .IP "\fB\-mdirect\-move\fR" 4 .IX Item "-mdirect-move" .PD 0 @@ -18645,7 +17756,7 @@ access to the cryptographic instructions that were added in version .PD Generate code that uses (does not use) the instructions to move data between the general purpose registers and the vector/scalar (\s-1VSX\s0) -registers that were added in version 2.07 of the PowerPC \s-1ISA\s0. +registers that were added in version 2.07 of the PowerPC \s-1ISA.\s0 .IP "\fB\-mpower8\-fusion\fR" 4 .IX Item "-mpower8-fusion" .PD 0 @@ -18662,7 +17773,7 @@ later processors. .IX Item "-mno-power8-vector" .PD Generate code that uses (does not use) the vector and scalar -instructions that were added in version 2.07 of the PowerPC \s-1ISA\s0. Also +instructions that were added in version 2.07 of the PowerPC \s-1ISA. \s0 Also enable the use of built-in functions that allow more direct access to the vector instructions. .IP "\fB\-mquad\-memory\fR" 4 @@ -18692,8 +17803,8 @@ instructions. The \fB\-mquad\-memory\-atomic\fR option requires use of Generate code that uses (does not use) the scalar double precision instructions that target all 64 registers in the vector/scalar floating point register set that were added in version 2.06 of the -PowerPC \s-1ISA\s0. The \fB\-mupper\-regs\-df\fR turned on by default if you -use either of the \fB\-mcpu=power7\fR, \fB\-mcpu=power8\fR, or +PowerPC \s-1ISA. \s0\fB\-mupper\-regs\-df\fR is turned on by default if you +use any of the \fB\-mcpu=power7\fR, \fB\-mcpu=power8\fR, or \&\fB\-mvsx\fR options. .IP "\fB\-mupper\-regs\-sf\fR" 4 .IX Item "-mupper-regs-sf" @@ -18704,8 +17815,8 @@ use either of the \fB\-mcpu=power7\fR, \fB\-mcpu=power8\fR, or Generate code that uses (does not use) the scalar single precision instructions that target all 64 registers in the vector/scalar floating point register set that were added in version 2.07 of the -PowerPC \s-1ISA\s0. The \fB\-mupper\-regs\-sf\fR turned on by default if you -use either of the \fB\-mcpu=power8\fR, or \fB\-mpower8\-vector\fR +PowerPC \s-1ISA. \s0\fB\-mupper\-regs\-sf\fR is turned on by default if you +use either of the \fB\-mcpu=power8\fR or \fB\-mpower8\-vector\fR options. .IP "\fB\-mupper\-regs\fR" 4 .IX Item "-mupper-regs" @@ -18761,12 +17872,12 @@ pointer to 64 bits, and generates code for PowerPC64, as for .IP "\fB\-mminimal\-toc\fR" 4 .IX Item "-mminimal-toc" .PD -Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for +Modify generation of the \s-1TOC \s0(Table Of Contents), which is created for every executable file. The \fB\-mfull\-toc\fR option is selected by default. In that case, \s-1GCC\s0 allocates at least one \s-1TOC\s0 entry for each unique non-automatic variable reference in your program. \s-1GCC\s0 -also places floating-point constants in the \s-1TOC\s0. However, only -16,384 entries are available in the \s-1TOC\s0. +also places floating-point constants in the \s-1TOC. \s0 However, only +16,384 entries are available in the \s-1TOC.\s0 .Sp If you receive a linker error message that saying you have overflowed the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used @@ -18774,7 +17885,7 @@ with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options. \&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to generate code to calculate the sum of an address and a constant at -run time instead of putting that sum into the \s-1TOC\s0. You may specify one +run time instead of putting that sum into the \s-1TOC. \s0 You may specify one or both of these options. Each causes \s-1GCC\s0 to produce very slightly slower and larger code at the expense of conserving \s-1TOC\s0 space. .Sp @@ -18790,7 +17901,7 @@ only on files that contain less frequently-executed code. .IP "\fB\-maix32\fR" 4 .IX Item "-maix32" .PD -Enable 64\-bit \s-1AIX\s0 \s-1ABI\s0 and calling convention: 64\-bit pointers, 64\-bit +Enable 64\-bit \s-1AIX ABI\s0 and calling convention: 64\-bit pointers, 64\-bit \&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them. Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR, while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and @@ -18801,8 +17912,8 @@ implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR. .IP "\fB\-mno\-xl\-compat\fR" 4 .IX Item "-mno-xl-compat" .PD -Produce code that conforms more closely to \s-1IBM\s0 \s-1XL\s0 compiler semantics -when using AIX-compatible \s-1ABI\s0. Pass floating-point arguments to +Produce code that conforms more closely to \s-1IBM XL\s0 compiler semantics +when using AIX-compatible \s-1ABI. \s0 Pass floating-point arguments to prototyped functions beyond the register save area (\s-1RSA\s0) on the stack in addition to argument FPRs. Do not assume that most significant double in 128\-bit long double value is properly rounded when comparing @@ -18811,16 +17922,16 @@ support routines. .Sp The \s-1AIX\s0 calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the -address of its arguments with fewer arguments than declared. \s-1IBM\s0 \s-1XL\s0 +address of its arguments with fewer arguments than declared. \s-1IBM XL\s0 compilers access floating-point arguments that do not fit in the \&\s-1RSA\s0 from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by -default and only is necessary when calling subroutines compiled by \s-1IBM\s0 -\&\s-1XL\s0 compilers without optimization. +default and only is necessary when calling subroutines compiled by \s-1IBM +XL\s0 compilers without optimization. .IP "\fB\-mpe\fR" 4 .IX Item "-mpe" -Support \fI\s-1IBM\s0 \s-1RS/6000\s0 \s-1SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0). Link an +Support \fI\s-1IBM RS/6000 SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0). Link an application written to use message passing with special startup code to enable the application to run. The system must have \s-1PE\s0 installed in the standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file @@ -18834,11 +17945,11 @@ option are incompatible. .IP "\fB\-malign\-power\fR" 4 .IX Item "-malign-power" .PD -On \s-1AIX\s0, 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option +On \s-1AIX,\s0 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option \&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified -alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI\s0. +alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI.\s0 .Sp On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR is not supported. @@ -18872,7 +17983,7 @@ Specify type of floating-point unit. Valid values for \fIname\fR are and \fBdp_full\fR (equivalent to \fB\-mdouble\-float\fR). .IP "\fB\-mxilinx\-fpu\fR" 4 .IX Item "-mxilinx-fpu" -Perform optimizations for the floating-point unit on Xilinx \s-1PPC\s0 405/440. +Perform optimizations for the floating-point unit on Xilinx \s-1PPC 405/440.\s0 .IP "\fB\-mmultiple\fR" 4 .IX Item "-mmultiple" .PD 0 @@ -18943,7 +18054,7 @@ mapped to \fB\-ffp\-contract=off\fR. .IX Item "-mno-mulhw" .PD Generate code that uses (does not use) the half-word multiply and -multiply-accumulate instructions on the \s-1IBM\s0 405, 440, 464 and 476 processors. +multiply-accumulate instructions on the \s-1IBM 405, 440, 464\s0 and 476 processors. These instructions are generated by default when targeting those processors. .IP "\fB\-mdlmzb\fR" 4 @@ -18953,7 +18064,7 @@ processors. .IX Item "-mno-dlmzb" .PD Generate code that uses (does not use) the string-search \fBdlmzb\fR -instruction on the \s-1IBM\s0 405, 440, 464 and 476 processors. This instruction is +instruction on the \s-1IBM 405, 440, 464\s0 and 476 processors. This instruction is generated by default when targeting those processors. .IP "\fB\-mno\-bit\-align\fR" 4 .IX Item "-mno-bit-align" @@ -19033,7 +18144,7 @@ processor in big-endian mode. The \fB\-mbig\-endian\fR option is the same as \fB\-mbig\fR. .IP "\fB\-mdynamic\-no\-pic\fR" 4 .IX Item "-mdynamic-no-pic" -On Darwin and Mac \s-1OS\s0 X systems, compile code so that it is not +On Darwin and Mac \s-1OS X\s0 systems, compile code so that it is not relocatable, but that its external references are relocatable. The resulting code is suitable for applications, but not shared libraries. @@ -19139,11 +18250,11 @@ On System V.4 and embedded PowerPC systems compile code for the OpenBSD operating system. .IP "\fB\-maix\-struct\-return\fR" 4 .IX Item "-maix-struct-return" -Return all structures in memory (as specified by the \s-1AIX\s0 \s-1ABI\s0). +Return all structures in memory (as specified by the \s-1AIX ABI\s0). .IP "\fB\-msvr4\-struct\-return\fR" 4 .IX Item "-msvr4-struct-return" Return structures smaller than 8 bytes in registers (as specified by the -\&\s-1SVR4\s0 \s-1ABI\s0). +\&\s-1SVR4 ABI\s0). .IP "\fB\-mabi=\fR\fIabi-type\fR" 4 .IX Item "-mabi=abi-type" Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. @@ -19152,29 +18263,29 @@ Valid values are \fBaltivec\fR, \fBno-altivec\fR, \fBspe\fR, \&\fBelfv1\fR, \fBelfv2\fR. .IP "\fB\-mabi=spe\fR" 4 .IX Item "-mabi=spe" -Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change -the default \s-1ABI\s0, instead it adds the \s-1SPE\s0 \s-1ABI\s0 extensions to the current -\&\s-1ABI\s0. +Extend the current \s-1ABI\s0 with \s-1SPE ABI\s0 extensions. This does not change +the default \s-1ABI,\s0 instead it adds the \s-1SPE ABI\s0 extensions to the current +\&\s-1ABI.\s0 .IP "\fB\-mabi=no\-spe\fR" 4 .IX Item "-mabi=no-spe" -Disable Book-E \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0. +Disable Book-E \s-1SPE ABI\s0 extensions for the current \s-1ABI.\s0 .IP "\fB\-mabi=ibmlongdouble\fR" 4 .IX Item "-mabi=ibmlongdouble" Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended-precision long double. -This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. +This is a PowerPC 32\-bit \s-1SYSV ABI\s0 option. .IP "\fB\-mabi=ieeelongdouble\fR" 4 .IX Item "-mabi=ieeelongdouble" Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. .IP "\fB\-mabi=elfv1\fR" 4 .IX Item "-mabi=elfv1" -Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI\s0. +Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI.\s0 This is the default \s-1ABI\s0 for big-endian PowerPC 64\-bit Linux. Overriding the default \s-1ABI\s0 requires special system support and is likely to fail in spectacular ways. .IP "\fB\-mabi=elfv2\fR" 4 .IX Item "-mabi=elfv2" -Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI\s0. +Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI.\s0 This is the default \s-1ABI\s0 for little-endian PowerPC 64\-bit Linux. Overriding the default \s-1ABI\s0 requires special system support and is likely to fail in spectacular ways. @@ -19328,7 +18439,7 @@ On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR generates \f(CW\*(C`jb callee, L42\*(C'\fR, plus a \fIbranch island\fR (glue code). The two target addresses represent the callee and the branch island. The Darwin/PPC linker prefers the first address and generates a \f(CW\*(C`bl -callee\*(C'\fR if the \s-1PPC\s0 \f(CW\*(C`bl\*(C'\fR instruction reaches the callee directly; +callee\*(C'\fR if the \s-1PPC \s0\f(CW\*(C`bl\*(C'\fR instruction reaches the callee directly; otherwise, the linker generates \f(CW\*(C`bl L42\*(C'\fR to call the branch island. The branch island is appended to the body of the calling function; it computes the full 32\-bit address of the callee @@ -19424,7 +18535,7 @@ which handle the double-precision reciprocal square root calculations. .PD Assume (do not assume) that the reciprocal estimate instructions provide higher-precision estimates than is mandated by the PowerPC -\&\s-1ABI\s0. Selecting \fB\-mcpu=power6\fR, \fB\-mcpu=power7\fR or +\&\s-1ABI. \s0 Selecting \fB\-mcpu=power6\fR, \fB\-mcpu=power7\fR or \&\fB\-mcpu=power8\fR automatically selects \fB\-mrecip\-precision\fR. The double-precision square root estimate instructions are not generated by default on low-precision machines, since they do not provide an @@ -19477,7 +18588,7 @@ static chain value to be loaded in register \f(CW\*(C`r11\*(C'\fR. The \&\fB\-mpointers\-to\-nested\-functions\fR is on by default. You cannot call through pointers to nested functions or pointers to functions compiled in other languages that use the static chain if -you use the \fB\-mno\-pointers\-to\-nested\-functions\fR. +you use \fB\-mno\-pointers\-to\-nested\-functions\fR. .IP "\fB\-msave\-toc\-indirect\fR" 4 .IX Item "-msave-toc-indirect" .PD 0 @@ -19497,14 +18608,14 @@ pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. .PD Generate (do not generate) code to pass structure parameters with a maximum alignment of 64 bits, for compatibility with older versions -of \s-1GCC\s0. +of \s-1GCC.\s0 .Sp -Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a +Older versions of \s-1GCC \s0(prior to 4.9.0) incorrectly did not align a structure parameter on a 128\-bit boundary when that structure contained a member requiring 128\-bit alignment. This is corrected in more -recent versions of \s-1GCC\s0. This option may be used to generate code +recent versions of \s-1GCC. \s0 This option may be used to generate code that is compatible with functions compiled with older versions of -\&\s-1GCC\s0. +\&\s-1GCC.\s0 .Sp The \fB\-mno\-compat\-align\-parm\fR option is the default. .PP @@ -19539,12 +18650,12 @@ values, however, so the \s-1FPU\s0 hardware is not used for doubles if the .Sp \&\fINote\fR If the \fB\-fpu\fR option is enabled then \&\fB\-funsafe\-math\-optimizations\fR is also enabled automatically. -This is because the \s-1RX\s0 \s-1FPU\s0 instructions are themselves unsafe. +This is because the \s-1RX FPU\s0 instructions are themselves unsafe. .IP "\fB\-mcpu=\fR\fIname\fR" 4 .IX Item "-mcpu=name" -Selects the type of \s-1RX\s0 \s-1CPU\s0 to be targeted. Currently three types are +Selects the type of \s-1RX CPU\s0 to be targeted. Currently three types are supported, the generic \fB\s-1RX600\s0\fR and \fB\s-1RX200\s0\fR series hardware and -the specific \fB\s-1RX610\s0\fR \s-1CPU\s0. The default is \fB\s-1RX600\s0\fR. +the specific \fB\s-1RX610\s0\fR \s-1CPU. \s0 The default is \fB\s-1RX600\s0\fR. .Sp The only difference between \fB\s-1RX600\s0\fR and \fB\s-1RX610\s0\fR is that the \&\fB\s-1RX610\s0\fR does not support the \f(CW\*(C`MVTIPL\*(C'\fR instruction. @@ -19587,269 +18698,837 @@ actual register to hold the small data area pointer is chosen. .IP "\fB\-msim\fR" 4 .IX Item "-msim" .PD 0 -.IP "\fB\-mno\-sim\fR" 4 -.IX Item "-mno-sim" +.IP "\fB\-mno\-sim\fR" 4 +.IX Item "-mno-sim" +.PD +Use the simulator runtime. The default is to use the libgloss +board-specific runtime. +.IP "\fB\-mas100\-syntax\fR" 4 +.IX Item "-mas100-syntax" +.PD 0 +.IP "\fB\-mno\-as100\-syntax\fR" 4 +.IX Item "-mno-as100-syntax" +.PD +When generating assembler output use a syntax that is compatible with +Renesas's \s-1AS100\s0 assembler. This syntax can also be handled by the \s-1GAS\s0 +assembler, but it has some restrictions so it is not generated by default. +.IP "\fB\-mmax\-constant\-size=\fR\fIN\fR" 4 +.IX Item "-mmax-constant-size=N" +Specifies the maximum size, in bytes, of a constant that can be used as +an operand in a \s-1RX\s0 instruction. Although the \s-1RX\s0 instruction set does +allow constants of up to 4 bytes in length to be used in instructions, +a longer value equates to a longer instruction. Thus in some +circumstances it can be beneficial to restrict the size of constants +that are used in instructions. Constants that are too big are instead +placed into a constant pool and referenced via register indirection. +.Sp +The value \fIN\fR can be between 0 and 4. A value of 0 (the default) +or 4 means that constants of any size are allowed. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" +Enable linker relaxation. Linker relaxation is a process whereby the +linker attempts to reduce the size of a program by finding shorter +versions of various instructions. Disabled by default. +.IP "\fB\-mint\-register=\fR\fIN\fR" 4 +.IX Item "-mint-register=N" +Specify the number of registers to reserve for fast interrupt handler +functions. The value \fIN\fR can be between 0 and 4. A value of 1 +means that register \f(CW\*(C`r13\*(C'\fR is reserved for the exclusive use +of fast interrupt handlers. A value of 2 reserves \f(CW\*(C`r13\*(C'\fR and +\&\f(CW\*(C`r12\*(C'\fR. A value of 3 reserves \f(CW\*(C`r13\*(C'\fR, \f(CW\*(C`r12\*(C'\fR and +\&\f(CW\*(C`r11\*(C'\fR, and a value of 4 reserves \f(CW\*(C`r13\*(C'\fR through \f(CW\*(C`r10\*(C'\fR. +A value of 0, the default, does not reserve any registers. +.IP "\fB\-msave\-acc\-in\-interrupts\fR" 4 +.IX Item "-msave-acc-in-interrupts" +Specifies that interrupt handler functions should preserve the +accumulator register. This is only necessary if normal code might use +the accumulator register, for example because it performs 64\-bit +multiplications. The default is to ignore the accumulator as this +makes the interrupt handlers faster. +.IP "\fB\-mpid\fR" 4 +.IX Item "-mpid" +.PD 0 +.IP "\fB\-mno\-pid\fR" 4 +.IX Item "-mno-pid" +.PD +Enables the generation of position independent data. When enabled any +access to constant data is done via an offset from a base address +held in a register. This allows the location of constant data to be +determined at run time without requiring the executable to be +relocated, which is a benefit to embedded applications with tight +memory constraints. Data that can be modified is not affected by this +option. +.Sp +Note, using this feature reserves a register, usually \f(CW\*(C`r13\*(C'\fR, for +the constant data base address. This can result in slower and/or +larger code, especially in complicated functions. +.Sp +The actual register chosen to hold the constant data base address +depends upon whether the \fB\-msmall\-data\-limit\fR and/or the +\&\fB\-mint\-register\fR command-line options are enabled. Starting +with register \f(CW\*(C`r13\*(C'\fR and proceeding downwards, registers are +allocated first to satisfy the requirements of \fB\-mint\-register\fR, +then \fB\-mpid\fR and finally \fB\-msmall\-data\-limit\fR. Thus it +is possible for the small data area register to be \f(CW\*(C`r8\*(C'\fR if both +\&\fB\-mint\-register=4\fR and \fB\-mpid\fR are specified on the +command line. +.Sp +By default this feature is not enabled. The default can be restored +via the \fB\-mno\-pid\fR command-line option. +.IP "\fB\-mno\-warn\-multiple\-fast\-interrupts\fR" 4 +.IX Item "-mno-warn-multiple-fast-interrupts" +.PD 0 +.IP "\fB\-mwarn\-multiple\-fast\-interrupts\fR" 4 +.IX Item "-mwarn-multiple-fast-interrupts" +.PD +Prevents \s-1GCC\s0 from issuing a warning message if it finds more than one +fast interrupt handler when it is compiling a file. The default is to +issue a warning for each extra fast interrupt handler found, as the \s-1RX\s0 +only supports one such interrupt. +.PP +\&\fINote:\fR The generic \s-1GCC\s0 command-line option \fB\-ffixed\-\fR\fIreg\fR +has special significance to the \s-1RX\s0 port when used with the +\&\f(CW\*(C`interrupt\*(C'\fR function attribute. This attribute indicates a +function intended to process fast interrupts. \s-1GCC\s0 ensures +that it only uses the registers \f(CW\*(C`r10\*(C'\fR, \f(CW\*(C`r11\*(C'\fR, \f(CW\*(C`r12\*(C'\fR +and/or \f(CW\*(C`r13\*(C'\fR and only provided that the normal use of the +corresponding registers have been restricted via the +\&\fB\-ffixed\-\fR\fIreg\fR or \fB\-mint\-register\fR command-line +options. +.PP +\fIS/390 and zSeries Options\fR +.IX Subsection "S/390 and zSeries Options" +.PP +These are the \fB\-m\fR options defined for the S/390 and zSeries architecture. +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Use (do not use) the hardware floating-point instructions and registers +for floating-point operations. When \fB\-msoft\-float\fR is specified, +functions in \fIlibgcc.a\fR are used to perform floating-point +operations. When \fB\-mhard\-float\fR is specified, the compiler +generates \s-1IEEE\s0 floating-point instructions. This is the default. +.IP "\fB\-mhard\-dfp\fR" 4 +.IX Item "-mhard-dfp" +.PD 0 +.IP "\fB\-mno\-hard\-dfp\fR" 4 +.IX Item "-mno-hard-dfp" +.PD +Use (do not use) the hardware decimal-floating-point instructions for +decimal-floating-point operations. When \fB\-mno\-hard\-dfp\fR is +specified, functions in \fIlibgcc.a\fR are used to perform +decimal-floating-point operations. When \fB\-mhard\-dfp\fR is +specified, the compiler generates decimal-floating-point hardware +instructions. This is the default for \fB\-march=z9\-ec\fR or higher. +.IP "\fB\-mlong\-double\-64\fR" 4 +.IX Item "-mlong-double-64" +.PD 0 +.IP "\fB\-mlong\-double\-128\fR" 4 +.IX Item "-mlong-double-128" +.PD +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size +of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR +type. This is the default. +.IP "\fB\-mbackchain\fR" 4 +.IX Item "-mbackchain" +.PD 0 +.IP "\fB\-mno\-backchain\fR" 4 +.IX Item "-mno-backchain" +.PD +Store (do not store) the address of the caller's frame as backchain pointer +into the callee's stack frame. +A backchain may be needed to allow debugging using tools that do not understand +\&\s-1DWARF 2\s0 call frame information. +When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored +at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect, +the backchain is placed into the topmost word of the 96/160 byte register +save area. +.Sp +In general, code compiled with \fB\-mbackchain\fR is call-compatible with +code compiled with \fB\-mmo\-backchain\fR; however, use of the backchain +for debugging purposes usually requires that the whole binary is built with +\&\fB\-mbackchain\fR. Note that the combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not maintain the backchain. +.IP "\fB\-mpacked\-stack\fR" 4 +.IX Item "-mpacked-stack" +.PD 0 +.IP "\fB\-mno\-packed\-stack\fR" 4 +.IX Item "-mno-packed-stack" +.PD +Use (do not use) the packed stack layout. When \fB\-mno\-packed\-stack\fR is +specified, the compiler uses the all fields of the 96/160 byte register save +area only for their default purpose; unused fields still take up stack space. +When \fB\-mpacked\-stack\fR is specified, register save slots are densely +packed at the top of the register save area; unused space is reused for other +purposes, allowing for more efficient use of the available stack space. +However, when \fB\-mbackchain\fR is also in effect, the topmost word of +the save area is always used to store the backchain, and the return address +register is always saved two words below the backchain. +.Sp +As long as the stack frame backchain is not used, code generated with +\&\fB\-mpacked\-stack\fR is call-compatible with code generated with +\&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC 2.95\s0 for +S/390 or zSeries generated code that uses the stack frame backchain at run +time, not just for debugging purposes. Such code is not call-compatible +with code compiled with \fB\-mpacked\-stack\fR. Also, note that the +combination of \fB\-mbackchain\fR, +\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order +to build a linux kernel use \fB\-msoft\-float\fR. +.Sp +The default is to not use the packed stack layout. +.IP "\fB\-msmall\-exec\fR" 4 +.IX Item "-msmall-exec" +.PD 0 +.IP "\fB\-mno\-small\-exec\fR" 4 +.IX Item "-mno-small-exec" +.PD +Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction +to do subroutine calls. +This only works reliably if the total executable size does not +exceed 64k. The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead, +which does not have this limitation. +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD 0 +.IP "\fB\-m31\fR" 4 +.IX Item "-m31" +.PD +When \fB\-m31\fR is specified, generate code compliant to the +GNU/Linux for S/390 \s-1ABI. \s0 When \fB\-m64\fR is specified, generate +code compliant to the GNU/Linux for zSeries \s-1ABI. \s0 This allows \s-1GCC\s0 in +particular to generate 64\-bit instructions. For the \fBs390\fR +targets, the default is \fB\-m31\fR, while the \fBs390x\fR +targets default to \fB\-m64\fR. +.IP "\fB\-mzarch\fR" 4 +.IX Item "-mzarch" +.PD 0 +.IP "\fB\-mesa\fR" 4 +.IX Item "-mesa" +.PD +When \fB\-mzarch\fR is specified, generate code using the +instructions available on z/Architecture. +When \fB\-mesa\fR is specified, generate code using the +instructions available on \s-1ESA/390. \s0 Note that \fB\-mesa\fR is +not possible with \fB\-m64\fR. +When generating code compliant to the GNU/Linux for S/390 \s-1ABI,\s0 +the default is \fB\-mesa\fR. When generating code compliant +to the GNU/Linux for zSeries \s-1ABI,\s0 the default is \fB\-mzarch\fR. +.IP "\fB\-mmvcle\fR" 4 +.IX Item "-mmvcle" +.PD 0 +.IP "\fB\-mno\-mvcle\fR" 4 +.IX Item "-mno-mvcle" +.PD +Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction +to perform block moves. When \fB\-mno\-mvcle\fR is specified, +use a \f(CW\*(C`mvc\*(C'\fR loop instead. This is the default unless optimizing for +size. +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +.PD 0 +.IP "\fB\-mno\-debug\fR" 4 +.IX Item "-mno-debug" +.PD +Print (or do not print) additional debug information when compiling. +The default is to not print debug information. +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate code that runs on \fIcpu-type\fR, which is the name of a system +representing a certain processor type. Possible values for +\&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, \fBz990\fR, +\&\fBz9\-109\fR, \fBz9\-ec\fR, \fBz10\fR, \fBz196\fR, and \fBzEC12\fR. +When generating code using the instructions available on z/Architecture, +the default is \fB\-march=z900\fR. Otherwise, the default is +\&\fB\-march=g5\fR. +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, +except for the \s-1ABI\s0 and the set of available instructions. +The list of \fIcpu-type\fR values is the same as for \fB\-march\fR. +The default is the value used for \fB\-march\fR. +.IP "\fB\-mtpf\-trace\fR" 4 +.IX Item "-mtpf-trace" +.PD 0 +.IP "\fB\-mno\-tpf\-trace\fR" 4 +.IX Item "-mno-tpf-trace" .PD -Use the simulator runtime. The default is to use the libgloss -board-specific runtime. -.IP "\fB\-mas100\-syntax\fR" 4 -.IX Item "-mas100-syntax" +Generate code that adds (does not add) in \s-1TPF OS\s0 specific branches to trace +routines in the operating system. This option is off by default, even +when compiling for the \s-1TPF OS.\s0 +.IP "\fB\-mfused\-madd\fR" 4 +.IX Item "-mfused-madd" .PD 0 -.IP "\fB\-mno\-as100\-syntax\fR" 4 -.IX Item "-mno-as100-syntax" +.IP "\fB\-mno\-fused\-madd\fR" 4 +.IX Item "-mno-fused-madd" .PD -When generating assembler output use a syntax that is compatible with -Renesas's \s-1AS100\s0 assembler. This syntax can also be handled by the \s-1GAS\s0 -assembler, but it has some restrictions so it is not generated by default. -.IP "\fB\-mmax\-constant\-size=\fR\fIN\fR" 4 -.IX Item "-mmax-constant-size=N" -Specifies the maximum size, in bytes, of a constant that can be used as -an operand in a \s-1RX\s0 instruction. Although the \s-1RX\s0 instruction set does -allow constants of up to 4 bytes in length to be used in instructions, -a longer value equates to a longer instruction. Thus in some -circumstances it can be beneficial to restrict the size of constants -that are used in instructions. Constants that are too big are instead -placed into a constant pool and referenced via register indirection. +Generate code that uses (does not use) the floating-point multiply and +accumulate instructions. These instructions are generated by default if +hardware floating point is used. +.IP "\fB\-mwarn\-framesize=\fR\fIframesize\fR" 4 +.IX Item "-mwarn-framesize=framesize" +Emit a warning if the current function exceeds the given frame size. Because +this is a compile-time check it doesn't need to be a real problem when the program +runs. It is intended to identify functions that most probably cause +a stack overflow. It is useful to be used in an environment with limited stack +size e.g. the linux kernel. +.IP "\fB\-mwarn\-dynamicstack\fR" 4 +.IX Item "-mwarn-dynamicstack" +Emit a warning if the function calls \f(CW\*(C`alloca\*(C'\fR or uses dynamically-sized +arrays. This is generally a bad idea with a limited stack size. +.IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4 +.IX Item "-mstack-guard=stack-guard" +.PD 0 +.IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4 +.IX Item "-mstack-size=stack-size" +.PD +If these options are provided the S/390 back end emits additional instructions in +the function prologue that trigger a trap if the stack size is \fIstack-guard\fR +bytes above the \fIstack-size\fR (remember that the stack on S/390 grows downward). +If the \fIstack-guard\fR option is omitted the smallest power of 2 larger than +the frame size of the compiled function is chosen. +These options are intended to be used to help debugging stack overflow problems. +The additionally emitted code causes only little overhead and hence can also be +used in production-like systems without greater performance degradation. The given +values have to be exact powers of 2 and \fIstack-size\fR has to be greater than +\&\fIstack-guard\fR without exceeding 64k. +In order to be efficient the extra code makes the assumption that the stack starts +at an address aligned to the value given by \fIstack-size\fR. +The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.IP "\fB\-mhotpatch=\fR\fIpre-halfwords\fR\fB,\fR\fIpost-halfwords\fR" 4 +.IX Item "-mhotpatch=pre-halfwords,post-halfwords" +If the hotpatch option is enabled, a \*(L"hot-patching\*(R" function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +\&\s-1NOP\s0 instructions (\fIpre-halfwords\fR, maximum 1000000). After +the label, 2 * \fIpost-halfwords\fR bytes are appended, using the +largest \s-1NOP\s0 like instructions the architecture allows (maximum +1000000). .Sp -The value \fIN\fR can be between 0 and 4. A value of 0 (the default) -or 4 means that constants of any size are allowed. +If both arguments are zero, hotpatching is disabled. +.Sp +This option can be overridden for individual functions with the +\&\f(CW\*(C`hotpatch\*(C'\fR attribute. +.PP +\fIScore Options\fR +.IX Subsection "Score Options" +.PP +These options are defined for Score implementations: +.IP "\fB\-meb\fR" 4 +.IX Item "-meb" +Compile code for big-endian mode. This is the default. +.IP "\fB\-mel\fR" 4 +.IX Item "-mel" +Compile code for little-endian mode. +.IP "\fB\-mnhwloop\fR" 4 +.IX Item "-mnhwloop" +Disable generation of \f(CW\*(C`bcnz\*(C'\fR instructions. +.IP "\fB\-muls\fR" 4 +.IX Item "-muls" +Enable generation of unaligned load and store instructions. +.IP "\fB\-mmac\fR" 4 +.IX Item "-mmac" +Enable the use of multiply-accumulate instructions. Disabled by default. +.IP "\fB\-mscore5\fR" 4 +.IX Item "-mscore5" +Specify the \s-1SCORE5\s0 as the target architecture. +.IP "\fB\-mscore5u\fR" 4 +.IX Item "-mscore5u" +Specify the \s-1SCORE5U\s0 of the target architecture. +.IP "\fB\-mscore7\fR" 4 +.IX Item "-mscore7" +Specify the \s-1SCORE7\s0 as the target architecture. This is the default. +.IP "\fB\-mscore7d\fR" 4 +.IX Item "-mscore7d" +Specify the \s-1SCORE7D\s0 as the target architecture. +.PP +\fI\s-1SH\s0 Options\fR +.IX Subsection "SH Options" +.PP +These \fB\-m\fR options are defined for the \s-1SH\s0 implementations: +.IP "\fB\-m1\fR" 4 +.IX Item "-m1" +Generate code for the \s-1SH1.\s0 +.IP "\fB\-m2\fR" 4 +.IX Item "-m2" +Generate code for the \s-1SH2.\s0 +.IP "\fB\-m2e\fR" 4 +.IX Item "-m2e" +Generate code for the SH2e. +.IP "\fB\-m2a\-nofpu\fR" 4 +.IX Item "-m2a-nofpu" +Generate code for the SH2a without \s-1FPU,\s0 or for a SH2a\-FPU in such a way +that the floating-point unit is not used. +.IP "\fB\-m2a\-single\-only\fR" 4 +.IX Item "-m2a-single-only" +Generate code for the SH2a\-FPU, in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m2a\-single\fR" 4 +.IX Item "-m2a-single" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m2a\fR" 4 +.IX Item "-m2a" +Generate code for the SH2a\-FPU assuming the floating-point unit is in +double-precision mode by default. +.IP "\fB\-m3\fR" 4 +.IX Item "-m3" +Generate code for the \s-1SH3.\s0 +.IP "\fB\-m3e\fR" 4 +.IX Item "-m3e" +Generate code for the SH3e. +.IP "\fB\-m4\-nofpu\fR" 4 +.IX Item "-m4-nofpu" +Generate code for the \s-1SH4\s0 without a floating-point unit. +.IP "\fB\-m4\-single\-only\fR" 4 +.IX Item "-m4-single-only" +Generate code for the \s-1SH4\s0 with a floating-point unit that only +supports single-precision arithmetic. +.IP "\fB\-m4\-single\fR" 4 +.IX Item "-m4-single" +Generate code for the \s-1SH4\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\fR" 4 +.IX Item "-m4" +Generate code for the \s-1SH4.\s0 +.IP "\fB\-m4\-100\fR" 4 +.IX Item "-m4-100" +Generate code for \s-1SH4\-100.\s0 +.IP "\fB\-m4\-100\-nofpu\fR" 4 +.IX Item "-m4-100-nofpu" +Generate code for \s-1SH4\-100\s0 in such a way that the +floating-point unit is not used. +.IP "\fB\-m4\-100\-single\fR" 4 +.IX Item "-m4-100-single" +Generate code for \s-1SH4\-100\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\-100\-single\-only\fR" 4 +.IX Item "-m4-100-single-only" +Generate code for \s-1SH4\-100\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-200\fR" 4 +.IX Item "-m4-200" +Generate code for \s-1SH4\-200.\s0 +.IP "\fB\-m4\-200\-nofpu\fR" 4 +.IX Item "-m4-200-nofpu" +Generate code for \s-1SH4\-200\s0 without in such a way that the +floating-point unit is not used. +.IP "\fB\-m4\-200\-single\fR" 4 +.IX Item "-m4-200-single" +Generate code for \s-1SH4\-200\s0 assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4\-200\-single\-only\fR" 4 +.IX Item "-m4-200-single-only" +Generate code for \s-1SH4\-200\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-300\fR" 4 +.IX Item "-m4-300" +Generate code for \s-1SH4\-300.\s0 +.IP "\fB\-m4\-300\-nofpu\fR" 4 +.IX Item "-m4-300-nofpu" +Generate code for \s-1SH4\-300\s0 without in such a way that the +floating-point unit is not used. +.IP "\fB\-m4\-300\-single\fR" 4 +.IX Item "-m4-300-single" +Generate code for \s-1SH4\-300\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-300\-single\-only\fR" 4 +.IX Item "-m4-300-single-only" +Generate code for \s-1SH4\-300\s0 in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4\-340\fR" 4 +.IX Item "-m4-340" +Generate code for \s-1SH4\-340 \s0(no \s-1MMU,\s0 no \s-1FPU\s0). +.IP "\fB\-m4\-500\fR" 4 +.IX Item "-m4-500" +Generate code for \s-1SH4\-500 \s0(no \s-1FPU\s0). Passes \fB\-isa=sh4\-nofpu\fR to the +assembler. +.IP "\fB\-m4a\-nofpu\fR" 4 +.IX Item "-m4a-nofpu" +Generate code for the SH4al\-dsp, or for a SH4a in such a way that the +floating-point unit is not used. +.IP "\fB\-m4a\-single\-only\fR" 4 +.IX Item "-m4a-single-only" +Generate code for the SH4a, in such a way that no double-precision +floating-point operations are used. +.IP "\fB\-m4a\-single\fR" 4 +.IX Item "-m4a-single" +Generate code for the SH4a assuming the floating-point unit is in +single-precision mode by default. +.IP "\fB\-m4a\fR" 4 +.IX Item "-m4a" +Generate code for the SH4a. +.IP "\fB\-m4al\fR" 4 +.IX Item "-m4al" +Same as \fB\-m4a\-nofpu\fR, except that it implicitly passes +\&\fB\-dsp\fR to the assembler. \s-1GCC\s0 doesn't generate any \s-1DSP\s0 +instructions at the moment. +.IP "\fB\-m5\-32media\fR" 4 +.IX Item "-m5-32media" +Generate 32\-bit code for SHmedia. +.IP "\fB\-m5\-32media\-nofpu\fR" 4 +.IX Item "-m5-32media-nofpu" +Generate 32\-bit code for SHmedia in such a way that the +floating-point unit is not used. +.IP "\fB\-m5\-64media\fR" 4 +.IX Item "-m5-64media" +Generate 64\-bit code for SHmedia. +.IP "\fB\-m5\-64media\-nofpu\fR" 4 +.IX Item "-m5-64media-nofpu" +Generate 64\-bit code for SHmedia in such a way that the +floating-point unit is not used. +.IP "\fB\-m5\-compact\fR" 4 +.IX Item "-m5-compact" +Generate code for SHcompact. +.IP "\fB\-m5\-compact\-nofpu\fR" 4 +.IX Item "-m5-compact-nofpu" +Generate code for SHcompact in such a way that the +floating-point unit is not used. +.IP "\fB\-mb\fR" 4 +.IX Item "-mb" +Compile code for the processor in big-endian mode. +.IP "\fB\-ml\fR" 4 +.IX Item "-ml" +Compile code for the processor in little-endian mode. +.IP "\fB\-mdalign\fR" 4 +.IX Item "-mdalign" +Align doubles at 64\-bit boundaries. Note that this changes the calling +conventions, and thus some functions from the standard C library do +not work unless you recompile it first with \fB\-mdalign\fR. .IP "\fB\-mrelax\fR" 4 .IX Item "-mrelax" -Enable linker relaxation. Linker relaxation is a process whereby the -linker attempts to reduce the size of a program by finding shorter -versions of various instructions. Disabled by default. -.IP "\fB\-mint\-register=\fR\fIN\fR" 4 -.IX Item "-mint-register=N" -Specify the number of registers to reserve for fast interrupt handler -functions. The value \fIN\fR can be between 0 and 4. A value of 1 -means that register \f(CW\*(C`r13\*(C'\fR is reserved for the exclusive use -of fast interrupt handlers. A value of 2 reserves \f(CW\*(C`r13\*(C'\fR and -\&\f(CW\*(C`r12\*(C'\fR. A value of 3 reserves \f(CW\*(C`r13\*(C'\fR, \f(CW\*(C`r12\*(C'\fR and -\&\f(CW\*(C`r11\*(C'\fR, and a value of 4 reserves \f(CW\*(C`r13\*(C'\fR through \f(CW\*(C`r10\*(C'\fR. -A value of 0, the default, does not reserve any registers. -.IP "\fB\-msave\-acc\-in\-interrupts\fR" 4 -.IX Item "-msave-acc-in-interrupts" -Specifies that interrupt handler functions should preserve the -accumulator register. This is only necessary if normal code might use -the accumulator register, for example because it performs 64\-bit -multiplications. The default is to ignore the accumulator as this -makes the interrupt handlers faster. -.IP "\fB\-mpid\fR" 4 -.IX Item "-mpid" -.PD 0 -.IP "\fB\-mno\-pid\fR" 4 -.IX Item "-mno-pid" -.PD -Enables the generation of position independent data. When enabled any -access to constant data is done via an offset from a base address -held in a register. This allows the location of constant data to be -determined at run time without requiring the executable to be -relocated, which is a benefit to embedded applications with tight -memory constraints. Data that can be modified is not affected by this -option. -.Sp -Note, using this feature reserves a register, usually \f(CW\*(C`r13\*(C'\fR, for -the constant data base address. This can result in slower and/or -larger code, especially in complicated functions. -.Sp -The actual register chosen to hold the constant data base address -depends upon whether the \fB\-msmall\-data\-limit\fR and/or the -\&\fB\-mint\-register\fR command-line options are enabled. Starting -with register \f(CW\*(C`r13\*(C'\fR and proceeding downwards, registers are -allocated first to satisfy the requirements of \fB\-mint\-register\fR, -then \fB\-mpid\fR and finally \fB\-msmall\-data\-limit\fR. Thus it -is possible for the small data area register to be \f(CW\*(C`r8\*(C'\fR if both -\&\fB\-mint\-register=4\fR and \fB\-mpid\fR are specified on the -command line. -.Sp -By default this feature is not enabled. The default can be restored -via the \fB\-mno\-pid\fR command-line option. -.IP "\fB\-mno\-warn\-multiple\-fast\-interrupts\fR" 4 -.IX Item "-mno-warn-multiple-fast-interrupts" -.PD 0 -.IP "\fB\-mwarn\-multiple\-fast\-interrupts\fR" 4 -.IX Item "-mwarn-multiple-fast-interrupts" -.PD -Prevents \s-1GCC\s0 from issuing a warning message if it finds more than one -fast interrupt handler when it is compiling a file. The default is to -issue a warning for each extra fast interrupt handler found, as the \s-1RX\s0 -only supports one such interrupt. -.PP -\&\fINote:\fR The generic \s-1GCC\s0 command-line option \fB\-ffixed\-\fR\fIreg\fR -has special significance to the \s-1RX\s0 port when used with the -\&\f(CW\*(C`interrupt\*(C'\fR function attribute. This attribute indicates a -function intended to process fast interrupts. \s-1GCC\s0 ensures -that it only uses the registers \f(CW\*(C`r10\*(C'\fR, \f(CW\*(C`r11\*(C'\fR, \f(CW\*(C`r12\*(C'\fR -and/or \f(CW\*(C`r13\*(C'\fR and only provided that the normal use of the -corresponding registers have been restricted via the -\&\fB\-ffixed\-\fR\fIreg\fR or \fB\-mint\-register\fR command-line -options. -.PP -\fIS/390 and zSeries Options\fR -.IX Subsection "S/390 and zSeries Options" -.PP -These are the \fB\-m\fR options defined for the S/390 and zSeries architecture. -.IP "\fB\-mhard\-float\fR" 4 -.IX Item "-mhard-float" +Shorten some address references at link time, when possible; uses the +linker option \fB\-relax\fR. +.IP "\fB\-mbigtable\fR" 4 +.IX Item "-mbigtable" +Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use +16\-bit offsets. +.IP "\fB\-mbitops\fR" 4 +.IX Item "-mbitops" +Enable the use of bit manipulation instructions on \s-1SH2A.\s0 +.IP "\fB\-mfmovd\fR" 4 +.IX Item "-mfmovd" +Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR. Check \fB\-mdalign\fR for +alignment constraints. +.IP "\fB\-mrenesas\fR" 4 +.IX Item "-mrenesas" +Comply with the calling conventions defined by Renesas. +.IP "\fB\-mno\-renesas\fR" 4 +.IX Item "-mno-renesas" +Comply with the calling conventions defined for \s-1GCC\s0 before the Renesas +conventions were available. This option is the default for all +targets of the \s-1SH\s0 toolchain. +.IP "\fB\-mnomacsave\fR" 4 +.IX Item "-mnomacsave" +Mark the \f(CW\*(C`MAC\*(C'\fR register as call-clobbered, even if +\&\fB\-mrenesas\fR is given. +.IP "\fB\-mieee\fR" 4 +.IX Item "-mieee" .PD 0 -.IP "\fB\-msoft\-float\fR" 4 -.IX Item "-msoft-float" +.IP "\fB\-mno\-ieee\fR" 4 +.IX Item "-mno-ieee" .PD -Use (do not use) the hardware floating-point instructions and registers -for floating-point operations. When \fB\-msoft\-float\fR is specified, -functions in \fIlibgcc.a\fR are used to perform floating-point -operations. When \fB\-mhard\-float\fR is specified, the compiler -generates \s-1IEEE\s0 floating-point instructions. This is the default. -.IP "\fB\-mhard\-dfp\fR" 4 -.IX Item "-mhard-dfp" +Control the \s-1IEEE\s0 compliance of floating-point comparisons, which affects the +handling of cases where the result of a comparison is unordered. By default +\&\fB\-mieee\fR is implicitly enabled. If \fB\-ffinite\-math\-only\fR is +enabled \fB\-mno\-ieee\fR is implicitly set, which results in faster +floating-point greater-equal and less-equal comparisons. The implcit settings +can be overridden by specifying either \fB\-mieee\fR or \fB\-mno\-ieee\fR. +.IP "\fB\-minline\-ic_invalidate\fR" 4 +.IX Item "-minline-ic_invalidate" +Inline code to invalidate instruction cache entries after setting up +nested function trampolines. +This option has no effect if \fB\-musermode\fR is in effect and the selected +code generation option (e.g. \fB\-m4\fR) does not allow the use of the \f(CW\*(C`icbi\*(C'\fR +instruction. +If the selected code generation option does not allow the use of the \f(CW\*(C`icbi\*(C'\fR +instruction, and \fB\-musermode\fR is not in effect, the inlined code +manipulates the instruction cache address array directly with an associative +write. This not only requires privileged mode at run time, but it also +fails if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped. +.IP "\fB\-misize\fR" 4 +.IX Item "-misize" +Dump instruction size and location in the assembly code. +.IP "\fB\-mpadstruct\fR" 4 +.IX Item "-mpadstruct" +This option is deprecated. It pads structures to multiple of 4 bytes, +which is incompatible with the \s-1SH ABI.\s0 +.IP "\fB\-matomic\-model=\fR\fImodel\fR" 4 +.IX Item "-matomic-model=model" +Sets the model of atomic operations and additional parameters as a comma +separated list. For details on the atomic built-in functions see +\&\fB_\|_atomic Builtins\fR. The following models and parameters are supported: +.RS 4 +.IP "\fBnone\fR" 4 +.IX Item "none" +Disable compiler generated atomic sequences and emit library calls for atomic +operations. This is the default if the target is not \f(CW\*(C`sh*\-*\-linux*\*(C'\fR. +.IP "\fBsoft-gusa\fR" 4 +.IX Item "soft-gusa" +Generate GNU/Linux compatible gUSA software atomic sequences for the atomic +built-in functions. The generated atomic sequences require additional support +from the interrupt/exception handling code of the system and are only suitable +for SH3* and SH4* single-core systems. This option is enabled by default when +the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH3* or SH4*. When the target is \s-1SH4A,\s0 +this option also partially utilizes the hardware atomic instructions +\&\f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR to create more efficient code, unless +\&\fBstrict\fR is specified. +.IP "\fBsoft-tcb\fR" 4 +.IX Item "soft-tcb" +Generate software atomic sequences that use a variable in the thread control +block. This is a variation of the gUSA sequences which can also be used on +SH1* and SH2* targets. The generated atomic sequences require additional +support from the interrupt/exception handling code of the system and are only +suitable for single-core systems. When using this model, the \fBgbr\-offset=\fR +parameter has to be specified as well. +.IP "\fBsoft-imask\fR" 4 +.IX Item "soft-imask" +Generate software atomic sequences that temporarily disable interrupts by +setting \f(CW\*(C`SR.IMASK = 1111\*(C'\fR. This model works only when the program runs +in privileged mode and is only suitable for single-core systems. Additional +support from the interrupt/exception handling code of the system is not +required. This model is enabled by default when the target is +\&\f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH1* or SH2*. +.IP "\fBhard-llcs\fR" 4 +.IX Item "hard-llcs" +Generate hardware atomic sequences using the \f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR +instructions only. This is only available on \s-1SH4A\s0 and is suitable for +multi-core systems. Since the hardware instructions support only 32 bit atomic +variables access to 8 or 16 bit variables is emulated with 32 bit accesses. +Code compiled with this option is also compatible with other software +atomic model interrupt/exception handling systems if executed on an \s-1SH4A\s0 +system. Additional support from the interrupt/exception handling code of the +system is not required for this model. +.IP "\fBgbr\-offset=\fR" 4 +.IX Item "gbr-offset=" +This parameter specifies the offset in bytes of the variable in the thread +control block structure that should be used by the generated atomic sequences +when the \fBsoft-tcb\fR model has been selected. For other models this +parameter is ignored. The specified value must be an integer multiple of four +and in the range 0\-1020. +.IP "\fBstrict\fR" 4 +.IX Item "strict" +This parameter prevents mixed usage of multiple atomic models, even if they +are compatible, and makes the compiler generate atomic sequences of the +specified model only. +.RE +.RS 4 +.RE +.IP "\fB\-mtas\fR" 4 +.IX Item "-mtas" +Generate the \f(CW\*(C`tas.b\*(C'\fR opcode for \f(CW\*(C`_\|_atomic_test_and_set\*(C'\fR. +Notice that depending on the particular hardware and software configuration +this can degrade overall performance due to the operand cache line flushes +that are implied by the \f(CW\*(C`tas.b\*(C'\fR instruction. On multi-core \s-1SH4A\s0 +processors the \f(CW\*(C`tas.b\*(C'\fR instruction must be used with caution since it +can result in data corruption for certain cache configurations. +.IP "\fB\-mprefergot\fR" 4 +.IX Item "-mprefergot" +When generating position-independent code, emit function calls using +the Global Offset Table instead of the Procedure Linkage Table. +.IP "\fB\-musermode\fR" 4 +.IX Item "-musermode" .PD 0 -.IP "\fB\-mno\-hard\-dfp\fR" 4 -.IX Item "-mno-hard-dfp" +.IP "\fB\-mno\-usermode\fR" 4 +.IX Item "-mno-usermode" .PD -Use (do not use) the hardware decimal-floating-point instructions for -decimal-floating-point operations. When \fB\-mno\-hard\-dfp\fR is -specified, functions in \fIlibgcc.a\fR are used to perform -decimal-floating-point operations. When \fB\-mhard\-dfp\fR is -specified, the compiler generates decimal-floating-point hardware -instructions. This is the default for \fB\-march=z9\-ec\fR or higher. -.IP "\fB\-mlong\-double\-64\fR" 4 -.IX Item "-mlong-double-64" +Don't allow (allow) the compiler generating privileged mode code. Specifying +\&\fB\-musermode\fR also implies \fB\-mno\-inline\-ic_invalidate\fR if the +inlined code would not work in user mode. \fB\-musermode\fR is the default +when the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR. If the target is SH1* or SH2* +\&\fB\-musermode\fR has no effect, since there is no user mode. +.IP "\fB\-multcost=\fR\fInumber\fR" 4 +.IX Item "-multcost=number" +Set the cost to assume for a multiply insn. +.IP "\fB\-mdiv=\fR\fIstrategy\fR" 4 +.IX Item "-mdiv=strategy" +Set the division strategy to be used for integer division operations. +For SHmedia \fIstrategy\fR can be one of: +.RS 4 +.IP "\fBfp\fR" 4 +.IX Item "fp" +Performs the operation in floating point. This has a very high latency, +but needs only a few instructions, so it might be a good choice if +your code has enough easily-exploitable \s-1ILP\s0 to allow the compiler to +schedule the floating-point instructions together with other instructions. +Division by zero causes a floating-point exception. +.IP "\fBinv\fR" 4 +.IX Item "inv" +Uses integer operations to calculate the inverse of the divisor, +and then multiplies the dividend with the inverse. This strategy allows +\&\s-1CSE\s0 and hoisting of the inverse calculation. Division by zero calculates +an unspecified result, but does not trap. +.IP "\fBinv:minlat\fR" 4 +.IX Item "inv:minlat" +A variant of \fBinv\fR where, if no \s-1CSE\s0 or hoisting opportunities +have been found, or if the entire operation has been hoisted to the same +place, the last stages of the inverse calculation are intertwined with the +final multiply to reduce the overall latency, at the expense of using a few +more instructions, and thus offering fewer scheduling opportunities with +other code. +.IP "\fBcall\fR" 4 +.IX Item "call" +Calls a library function that usually implements the \fBinv:minlat\fR +strategy. +This gives high code density for \f(CW\*(C`m5\-*media\-nofpu\*(C'\fR compilations. +.IP "\fBcall2\fR" 4 +.IX Item "call2" +Uses a different entry point of the same library function, where it +assumes that a pointer to a lookup table has already been set up, which +exposes the pointer load to \s-1CSE\s0 and code hoisting optimizations. +.IP "\fBinv:call\fR" 4 +.IX Item "inv:call" .PD 0 -.IP "\fB\-mlong\-double\-128\fR" 4 -.IX Item "-mlong-double-128" +.IP "\fBinv:call2\fR" 4 +.IX Item "inv:call2" +.IP "\fBinv:fp\fR" 4 +.IX Item "inv:fp" .PD -These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size -of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR -type. This is the default. -.IP "\fB\-mbackchain\fR" 4 -.IX Item "-mbackchain" +Use the \fBinv\fR algorithm for initial +code generation, but if the code stays unoptimized, revert to the \fBcall\fR, +\&\fBcall2\fR, or \fBfp\fR strategies, respectively. Note that the +potentially-trapping side effect of division by zero is carried by a +separate instruction, so it is possible that all the integer instructions +are hoisted out, but the marker for the side effect stays where it is. +A recombination to floating-point operations or a call is not possible +in that case. +.IP "\fBinv20u\fR" 4 +.IX Item "inv20u" .PD 0 -.IP "\fB\-mno\-backchain\fR" 4 -.IX Item "-mno-backchain" +.IP "\fBinv20l\fR" 4 +.IX Item "inv20l" .PD -Store (do not store) the address of the caller's frame as backchain pointer -into the callee's stack frame. -A backchain may be needed to allow debugging using tools that do not understand -\&\s-1DWARF\s0 2 call frame information. -When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored -at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect, -the backchain is placed into the topmost word of the 96/160 byte register -save area. -.Sp -In general, code compiled with \fB\-mbackchain\fR is call-compatible with -code compiled with \fB\-mmo\-backchain\fR; however, use of the backchain -for debugging purposes usually requires that the whole binary is built with -\&\fB\-mbackchain\fR. Note that the combination of \fB\-mbackchain\fR, -\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order -to build a linux kernel use \fB\-msoft\-float\fR. +Variants of the \fBinv:minlat\fR strategy. In the case +that the inverse calculation is not separated from the multiply, they speed +up division where the dividend fits into 20 bits (plus sign where applicable) +by inserting a test to skip a number of operations in this case; this test +slows down the case of larger dividends. \fBinv20u\fR assumes the case of a such +a small dividend to be unlikely, and \fBinv20l\fR assumes it to be likely. +.RE +.RS 4 .Sp -The default is to not maintain the backchain. -.IP "\fB\-mpacked\-stack\fR" 4 -.IX Item "-mpacked-stack" -.PD 0 -.IP "\fB\-mno\-packed\-stack\fR" 4 -.IX Item "-mno-packed-stack" -.PD -Use (do not use) the packed stack layout. When \fB\-mno\-packed\-stack\fR is -specified, the compiler uses the all fields of the 96/160 byte register save -area only for their default purpose; unused fields still take up stack space. -When \fB\-mpacked\-stack\fR is specified, register save slots are densely -packed at the top of the register save area; unused space is reused for other -purposes, allowing for more efficient use of the available stack space. -However, when \fB\-mbackchain\fR is also in effect, the topmost word of -the save area is always used to store the backchain, and the return address -register is always saved two words below the backchain. +For targets other than SHmedia \fIstrategy\fR can be one of: +.IP "\fBcall\-div1\fR" 4 +.IX Item "call-div1" +Calls a library function that uses the single-step division instruction +\&\f(CW\*(C`div1\*(C'\fR to perform the operation. Division by zero calculates an +unspecified result and does not trap. This is the default except for \s-1SH4, +SH2A\s0 and SHcompact. +.IP "\fBcall-fp\fR" 4 +.IX Item "call-fp" +Calls a library function that performs the operation in double precision +floating point. Division by zero causes a floating-point exception. This is +the default for SHcompact with \s-1FPU. \s0 Specifying this for targets that do not +have a double precision \s-1FPU\s0 defaults to \f(CW\*(C`call\-div1\*(C'\fR. +.IP "\fBcall-table\fR" 4 +.IX Item "call-table" +Calls a library function that uses a lookup table for small divisors and +the \f(CW\*(C`div1\*(C'\fR instruction with case distinction for larger divisors. Division +by zero calculates an unspecified result and does not trap. This is the default +for \s-1SH4. \s0 Specifying this for targets that do not have dynamic shift +instructions defaults to \f(CW\*(C`call\-div1\*(C'\fR. +.RE +.RS 4 .Sp -As long as the stack frame backchain is not used, code generated with -\&\fB\-mpacked\-stack\fR is call-compatible with code generated with -\&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC\s0 2.95 for -S/390 or zSeries generated code that uses the stack frame backchain at run -time, not just for debugging purposes. Such code is not call-compatible -with code compiled with \fB\-mpacked\-stack\fR. Also, note that the -combination of \fB\-mbackchain\fR, -\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order -to build a linux kernel use \fB\-msoft\-float\fR. +When a division strategy has not been specified the default strategy is +selected based on the current target. For \s-1SH2A\s0 the default strategy is to +use the \f(CW\*(C`divs\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions instead of library function +calls. +.RE +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +Reserve space once for outgoing arguments in the function prologue rather +than around each call. Generally beneficial for performance and size. Also +needed for unwinding to avoid changing the stack frame around conditional code. +.IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4 +.IX Item "-mdivsi3_libfunc=name" +Set the name of the library function used for 32\-bit signed division to +\&\fIname\fR. +This only affects the name used in the \fBcall\fR and \fBinv:call\fR +division strategies, and the compiler still expects the same +sets of input/output/clobbered registers as if this option were not present. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator can not use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mindexed\-addressing\fR" 4 +.IX Item "-mindexed-addressing" +Enable the use of the indexed addressing mode for SHmedia32/SHcompact. +This is only safe if the hardware and/or \s-1OS\s0 implement 32\-bit wrap-around +semantics for the indexed addressing mode. The architecture allows the +implementation of processors with 64\-bit \s-1MMU,\s0 which the \s-1OS\s0 could use to +get 32\-bit addressing, but since no current hardware implementation supports +this or any other way to make the indexed addressing mode safe to use in +the 32\-bit \s-1ABI,\s0 the default is \fB\-mno\-indexed\-addressing\fR. +.IP "\fB\-mgettrcost=\fR\fInumber\fR" 4 +.IX Item "-mgettrcost=number" +Set the cost assumed for the \f(CW\*(C`gettr\*(C'\fR instruction to \fInumber\fR. +The default is 2 if \fB\-mpt\-fixed\fR is in effect, 100 otherwise. +.IP "\fB\-mpt\-fixed\fR" 4 +.IX Item "-mpt-fixed" +Assume \f(CW\*(C`pt*\*(C'\fR instructions won't trap. This generally generates +better-scheduled code, but is unsafe on current hardware. +The current architecture +definition says that \f(CW\*(C`ptabs\*(C'\fR and \f(CW\*(C`ptrel\*(C'\fR trap when the target +anded with 3 is 3. +This has the unintentional effect of making it unsafe to schedule these +instructions before a branch, or hoist them out of a loop. For example, +\&\f(CW\*(C`_\|_do_global_ctors\*(C'\fR, a part of \fIlibgcc\fR +that runs constructors at program +startup, calls functions in a list which is delimited by \-1. With the +\&\fB\-mpt\-fixed\fR option, the \f(CW\*(C`ptabs\*(C'\fR is done before testing against \-1. +That means that all the constructors run a bit more quickly, but when +the loop comes to the end of the list, the program crashes because \f(CW\*(C`ptabs\*(C'\fR +loads \-1 into a target register. .Sp -The default is to not use the packed stack layout. -.IP "\fB\-msmall\-exec\fR" 4 -.IX Item "-msmall-exec" -.PD 0 -.IP "\fB\-mno\-small\-exec\fR" 4 -.IX Item "-mno-small-exec" -.PD -Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction -to do subroutine calls. -This only works reliably if the total executable size does not -exceed 64k. The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead, -which does not have this limitation. -.IP "\fB\-m64\fR" 4 -.IX Item "-m64" -.PD 0 -.IP "\fB\-m31\fR" 4 -.IX Item "-m31" -.PD -When \fB\-m31\fR is specified, generate code compliant to the -GNU/Linux for S/390 \s-1ABI\s0. When \fB\-m64\fR is specified, generate -code compliant to the GNU/Linux for zSeries \s-1ABI\s0. This allows \s-1GCC\s0 in -particular to generate 64\-bit instructions. For the \fBs390\fR -targets, the default is \fB\-m31\fR, while the \fBs390x\fR -targets default to \fB\-m64\fR. -.IP "\fB\-mzarch\fR" 4 -.IX Item "-mzarch" -.PD 0 -.IP "\fB\-mesa\fR" 4 -.IX Item "-mesa" -.PD -When \fB\-mzarch\fR is specified, generate code using the -instructions available on z/Architecture. -When \fB\-mesa\fR is specified, generate code using the -instructions available on \s-1ESA/390\s0. Note that \fB\-mesa\fR is -not possible with \fB\-m64\fR. -When generating code compliant to the GNU/Linux for S/390 \s-1ABI\s0, -the default is \fB\-mesa\fR. When generating code compliant -to the GNU/Linux for zSeries \s-1ABI\s0, the default is \fB\-mzarch\fR. -.IP "\fB\-mmvcle\fR" 4 -.IX Item "-mmvcle" -.PD 0 -.IP "\fB\-mno\-mvcle\fR" 4 -.IX Item "-mno-mvcle" -.PD -Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction -to perform block moves. When \fB\-mno\-mvcle\fR is specified, -use a \f(CW\*(C`mvc\*(C'\fR loop instead. This is the default unless optimizing for -size. -.IP "\fB\-mdebug\fR" 4 -.IX Item "-mdebug" -.PD 0 -.IP "\fB\-mno\-debug\fR" 4 -.IX Item "-mno-debug" -.PD -Print (or do not print) additional debug information when compiling. -The default is to not print debug information. -.IP "\fB\-march=\fR\fIcpu-type\fR" 4 -.IX Item "-march=cpu-type" -Generate code that runs on \fIcpu-type\fR, which is the name of a system -representing a certain processor type. Possible values for -\&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, \fBz990\fR, -\&\fBz9\-109\fR, \fBz9\-ec\fR and \fBz10\fR. -When generating code using the instructions available on z/Architecture, -the default is \fB\-march=z900\fR. Otherwise, the default is -\&\fB\-march=g5\fR. -.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 -.IX Item "-mtune=cpu-type" -Tune to \fIcpu-type\fR everything applicable about the generated code, -except for the \s-1ABI\s0 and the set of available instructions. -The list of \fIcpu-type\fR values is the same as for \fB\-march\fR. -The default is the value used for \fB\-march\fR. -.IP "\fB\-mtpf\-trace\fR" 4 -.IX Item "-mtpf-trace" +Since this option is unsafe for any +hardware implementing the current architecture specification, the default +is \fB\-mno\-pt\-fixed\fR. Unless specified explicitly with +\&\fB\-mgettrcost\fR, \fB\-mno\-pt\-fixed\fR also implies \fB\-mgettrcost=100\fR; +this deters register allocation from using target registers for storing +ordinary integers. +.IP "\fB\-minvalid\-symbols\fR" 4 +.IX Item "-minvalid-symbols" +Assume symbols might be invalid. Ordinary function symbols generated by +the compiler are always valid to load with +\&\f(CW\*(C`movi\*(C'\fR/\f(CW\*(C`shori\*(C'\fR/\f(CW\*(C`ptabs\*(C'\fR or +\&\f(CW\*(C`movi\*(C'\fR/\f(CW\*(C`shori\*(C'\fR/\f(CW\*(C`ptrel\*(C'\fR, +but with assembler and/or linker tricks it is possible +to generate symbols that cause \f(CW\*(C`ptabs\*(C'\fR or \f(CW\*(C`ptrel\*(C'\fR to trap. +This option is only meaningful when \fB\-mno\-pt\-fixed\fR is in effect. +It prevents cross-basic-block \s-1CSE,\s0 hoisting and most scheduling +of symbol loads. The default is \fB\-mno\-invalid\-symbols\fR. +.IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4 +.IX Item "-mbranch-cost=num" +Assume \fInum\fR to be the cost for a branch instruction. Higher numbers +make the compiler try to generate more branch-free code if possible. +If not specified the value is selected depending on the processor type that +is being compiled for. +.IP "\fB\-mzdcbranch\fR" 4 +.IX Item "-mzdcbranch" .PD 0 -.IP "\fB\-mno\-tpf\-trace\fR" 4 -.IX Item "-mno-tpf-trace" +.IP "\fB\-mno\-zdcbranch\fR" 4 +.IX Item "-mno-zdcbranch" .PD -Generate code that adds (does not add) in \s-1TPF\s0 \s-1OS\s0 specific branches to trace -routines in the operating system. This option is off by default, even -when compiling for the \s-1TPF\s0 \s-1OS\s0. +Assume (do not assume) that zero displacement conditional branch instructions +\&\f(CW\*(C`bt\*(C'\fR and \f(CW\*(C`bf\*(C'\fR are fast. If \fB\-mzdcbranch\fR is specified, the +compiler prefers zero displacement branch code sequences. This is +enabled by default when generating code for \s-1SH4\s0 and \s-1SH4A. \s0 It can be explicitly +disabled by specifying \fB\-mno\-zdcbranch\fR. +.IP "\fB\-mcbranch\-force\-delay\-slot\fR" 4 +.IX Item "-mcbranch-force-delay-slot" +Force the usage of delay slots for conditional branches, which stuffs the delay +slot with a \f(CW\*(C`nop\*(C'\fR if a suitable instruction can't be found. By default +this option is disabled. It can be enabled to work around hardware bugs as +found in the original \s-1SH7055.\s0 .IP "\fB\-mfused\-madd\fR" 4 .IX Item "-mfused-madd" .PD 0 @@ -19857,1561 +19536,2194 @@ when compiling for the \s-1TPF\s0 \s-1OS\s0. .IX Item "-mno-fused-madd" .PD Generate code that uses (does not use) the floating-point multiply and -accumulate instructions. These instructions are generated by default if -hardware floating point is used. -.IP "\fB\-mwarn\-framesize=\fR\fIframesize\fR" 4 -.IX Item "-mwarn-framesize=framesize" -Emit a warning if the current function exceeds the given frame size. Because -this is a compile-time check it doesn't need to be a real problem when the program -runs. It is intended to identify functions that most probably cause -a stack overflow. It is useful to be used in an environment with limited stack -size e.g. the linux kernel. -.IP "\fB\-mwarn\-dynamicstack\fR" 4 -.IX Item "-mwarn-dynamicstack" -Emit a warning if the function calls \f(CW\*(C`alloca\*(C'\fR or uses dynamically-sized -arrays. This is generally a bad idea with a limited stack size. -.IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4 -.IX Item "-mstack-guard=stack-guard" -.PD 0 -.IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4 -.IX Item "-mstack-size=stack-size" -.PD -If these options are provided the S/390 back end emits additional instructions in -the function prologue that trigger a trap if the stack size is \fIstack-guard\fR -bytes above the \fIstack-size\fR (remember that the stack on S/390 grows downward). -If the \fIstack-guard\fR option is omitted the smallest power of 2 larger than -the frame size of the compiled function is chosen. -These options are intended to be used to help debugging stack overflow problems. -The additionally emitted code causes only little overhead and hence can also be -used in production-like systems without greater performance degradation. The given -values have to be exact powers of 2 and \fIstack-size\fR has to be greater than -\&\fIstack-guard\fR without exceeding 64k. -In order to be efficient the extra code makes the assumption that the stack starts -at an address aligned to the value given by \fIstack-size\fR. -The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. -.IP "\fB\-mhotpatch[=\fR\fIhalfwords\fR\fB]\fR" 4 -.IX Item "-mhotpatch[=halfwords]" +accumulate instructions. These instructions are generated by default +if hardware floating point is used. The machine-dependent +\&\fB\-mfused\-madd\fR option is now mapped to the machine-independent +\&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is +mapped to \fB\-ffp\-contract=off\fR. +.IP "\fB\-mfsca\fR" 4 +.IX Item "-mfsca" .PD 0 -.IP "\fB\-mno\-hotpatch\fR" 4 -.IX Item "-mno-hotpatch" -.PD -If the hotpatch option is enabled, a \*(L"hot-patching\*(R" function -prologue is generated for all functions in the compilation unit. -The funtion label is prepended with the given number of two-byte -Nop instructions (\fIhalfwords\fR, maximum 1000000) or 12 Nop -instructions if no argument is present. Functions with a -hot-patching prologue are never inlined automatically, and a -hot-patching prologue is never generated for functions -that are explicitly inline. -.Sp -This option can be overridden for individual functions with the -\&\f(CW\*(C`hotpatch\*(C'\fR attribute. -.PP -\fIScore Options\fR -.IX Subsection "Score Options" -.PP -These options are defined for Score implementations: -.IP "\fB\-meb\fR" 4 -.IX Item "-meb" -Compile code for big-endian mode. This is the default. -.IP "\fB\-mel\fR" 4 -.IX Item "-mel" -Compile code for little-endian mode. -.IP "\fB\-mnhwloop\fR" 4 -.IX Item "-mnhwloop" -Disable generation of \f(CW\*(C`bcnz\*(C'\fR instructions. -.IP "\fB\-muls\fR" 4 -.IX Item "-muls" -Enable generation of unaligned load and store instructions. -.IP "\fB\-mmac\fR" 4 -.IX Item "-mmac" -Enable the use of multiply-accumulate instructions. Disabled by default. -.IP "\fB\-mscore5\fR" 4 -.IX Item "-mscore5" -Specify the \s-1SCORE5\s0 as the target architecture. -.IP "\fB\-mscore5u\fR" 4 -.IX Item "-mscore5u" -Specify the \s-1SCORE5U\s0 of the target architecture. -.IP "\fB\-mscore7\fR" 4 -.IX Item "-mscore7" -Specify the \s-1SCORE7\s0 as the target architecture. This is the default. -.IP "\fB\-mscore7d\fR" 4 -.IX Item "-mscore7d" -Specify the \s-1SCORE7D\s0 as the target architecture. -.PP -\fI\s-1SH\s0 Options\fR -.IX Subsection "SH Options" -.PP -These \fB\-m\fR options are defined for the \s-1SH\s0 implementations: -.IP "\fB\-m1\fR" 4 -.IX Item "-m1" -Generate code for the \s-1SH1\s0. -.IP "\fB\-m2\fR" 4 -.IX Item "-m2" -Generate code for the \s-1SH2\s0. -.IP "\fB\-m2e\fR" 4 -.IX Item "-m2e" -Generate code for the SH2e. -.IP "\fB\-m2a\-nofpu\fR" 4 -.IX Item "-m2a-nofpu" -Generate code for the SH2a without \s-1FPU\s0, or for a SH2a\-FPU in such a way -that the floating-point unit is not used. -.IP "\fB\-m2a\-single\-only\fR" 4 -.IX Item "-m2a-single-only" -Generate code for the SH2a\-FPU, in such a way that no double-precision -floating-point operations are used. -.IP "\fB\-m2a\-single\fR" 4 -.IX Item "-m2a-single" -Generate code for the SH2a\-FPU assuming the floating-point unit is in -single-precision mode by default. -.IP "\fB\-m2a\fR" 4 -.IX Item "-m2a" -Generate code for the SH2a\-FPU assuming the floating-point unit is in -double-precision mode by default. -.IP "\fB\-m3\fR" 4 -.IX Item "-m3" -Generate code for the \s-1SH3\s0. -.IP "\fB\-m3e\fR" 4 -.IX Item "-m3e" -Generate code for the SH3e. -.IP "\fB\-m4\-nofpu\fR" 4 -.IX Item "-m4-nofpu" -Generate code for the \s-1SH4\s0 without a floating-point unit. -.IP "\fB\-m4\-single\-only\fR" 4 -.IX Item "-m4-single-only" -Generate code for the \s-1SH4\s0 with a floating-point unit that only -supports single-precision arithmetic. -.IP "\fB\-m4\-single\fR" 4 -.IX Item "-m4-single" -Generate code for the \s-1SH4\s0 assuming the floating-point unit is in -single-precision mode by default. -.IP "\fB\-m4\fR" 4 -.IX Item "-m4" -Generate code for the \s-1SH4\s0. -.IP "\fB\-m4\-100\fR" 4 -.IX Item "-m4-100" -Generate code for \s-1SH4\-100\s0. -.IP "\fB\-m4\-100\-nofpu\fR" 4 -.IX Item "-m4-100-nofpu" -Generate code for \s-1SH4\-100\s0 in such a way that the -floating-point unit is not used. -.IP "\fB\-m4\-100\-single\fR" 4 -.IX Item "-m4-100-single" -Generate code for \s-1SH4\-100\s0 assuming the floating-point unit is in -single-precision mode by default. -.IP "\fB\-m4\-100\-single\-only\fR" 4 -.IX Item "-m4-100-single-only" -Generate code for \s-1SH4\-100\s0 in such a way that no double-precision -floating-point operations are used. -.IP "\fB\-m4\-200\fR" 4 -.IX Item "-m4-200" -Generate code for \s-1SH4\-200\s0. -.IP "\fB\-m4\-200\-nofpu\fR" 4 -.IX Item "-m4-200-nofpu" -Generate code for \s-1SH4\-200\s0 without in such a way that the -floating-point unit is not used. -.IP "\fB\-m4\-200\-single\fR" 4 -.IX Item "-m4-200-single" -Generate code for \s-1SH4\-200\s0 assuming the floating-point unit is in -single-precision mode by default. -.IP "\fB\-m4\-200\-single\-only\fR" 4 -.IX Item "-m4-200-single-only" -Generate code for \s-1SH4\-200\s0 in such a way that no double-precision -floating-point operations are used. -.IP "\fB\-m4\-300\fR" 4 -.IX Item "-m4-300" -Generate code for \s-1SH4\-300\s0. -.IP "\fB\-m4\-300\-nofpu\fR" 4 -.IX Item "-m4-300-nofpu" -Generate code for \s-1SH4\-300\s0 without in such a way that the -floating-point unit is not used. -.IP "\fB\-m4\-300\-single\fR" 4 -.IX Item "-m4-300-single" -Generate code for \s-1SH4\-300\s0 in such a way that no double-precision -floating-point operations are used. -.IP "\fB\-m4\-300\-single\-only\fR" 4 -.IX Item "-m4-300-single-only" -Generate code for \s-1SH4\-300\s0 in such a way that no double-precision -floating-point operations are used. -.IP "\fB\-m4\-340\fR" 4 -.IX Item "-m4-340" -Generate code for \s-1SH4\-340\s0 (no \s-1MMU\s0, no \s-1FPU\s0). -.IP "\fB\-m4\-500\fR" 4 -.IX Item "-m4-500" -Generate code for \s-1SH4\-500\s0 (no \s-1FPU\s0). Passes \fB\-isa=sh4\-nofpu\fR to the -assembler. -.IP "\fB\-m4a\-nofpu\fR" 4 -.IX Item "-m4a-nofpu" -Generate code for the SH4al\-dsp, or for a SH4a in such a way that the -floating-point unit is not used. -.IP "\fB\-m4a\-single\-only\fR" 4 -.IX Item "-m4a-single-only" -Generate code for the SH4a, in such a way that no double-precision -floating-point operations are used. -.IP "\fB\-m4a\-single\fR" 4 -.IX Item "-m4a-single" -Generate code for the SH4a assuming the floating-point unit is in -single-precision mode by default. -.IP "\fB\-m4a\fR" 4 -.IX Item "-m4a" -Generate code for the SH4a. -.IP "\fB\-m4al\fR" 4 -.IX Item "-m4al" -Same as \fB\-m4a\-nofpu\fR, except that it implicitly passes -\&\fB\-dsp\fR to the assembler. \s-1GCC\s0 doesn't generate any \s-1DSP\s0 -instructions at the moment. -.IP "\fB\-m5\-32media\fR" 4 -.IX Item "-m5-32media" -Generate 32\-bit code for SHmedia. -.IP "\fB\-m5\-32media\-nofpu\fR" 4 -.IX Item "-m5-32media-nofpu" -Generate 32\-bit code for SHmedia in such a way that the -floating-point unit is not used. -.IP "\fB\-m5\-64media\fR" 4 -.IX Item "-m5-64media" -Generate 64\-bit code for SHmedia. -.IP "\fB\-m5\-64media\-nofpu\fR" 4 -.IX Item "-m5-64media-nofpu" -Generate 64\-bit code for SHmedia in such a way that the -floating-point unit is not used. -.IP "\fB\-m5\-compact\fR" 4 -.IX Item "-m5-compact" -Generate code for SHcompact. -.IP "\fB\-m5\-compact\-nofpu\fR" 4 -.IX Item "-m5-compact-nofpu" -Generate code for SHcompact in such a way that the -floating-point unit is not used. -.IP "\fB\-mb\fR" 4 -.IX Item "-mb" -Compile code for the processor in big-endian mode. -.IP "\fB\-ml\fR" 4 -.IX Item "-ml" -Compile code for the processor in little-endian mode. -.IP "\fB\-mdalign\fR" 4 -.IX Item "-mdalign" -Align doubles at 64\-bit boundaries. Note that this changes the calling -conventions, and thus some functions from the standard C library do -not work unless you recompile it first with \fB\-mdalign\fR. -.IP "\fB\-mrelax\fR" 4 -.IX Item "-mrelax" -Shorten some address references at link time, when possible; uses the -linker option \fB\-relax\fR. -.IP "\fB\-mbigtable\fR" 4 -.IX Item "-mbigtable" -Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use -16\-bit offsets. -.IP "\fB\-mbitops\fR" 4 -.IX Item "-mbitops" -Enable the use of bit manipulation instructions on \s-1SH2A\s0. -.IP "\fB\-mfmovd\fR" 4 -.IX Item "-mfmovd" -Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR. Check \fB\-mdalign\fR for -alignment constraints. -.IP "\fB\-mrenesas\fR" 4 -.IX Item "-mrenesas" -Comply with the calling conventions defined by Renesas. -.IP "\fB\-mno\-renesas\fR" 4 -.IX Item "-mno-renesas" -Comply with the calling conventions defined for \s-1GCC\s0 before the Renesas -conventions were available. This option is the default for all -targets of the \s-1SH\s0 toolchain. -.IP "\fB\-mnomacsave\fR" 4 -.IX Item "-mnomacsave" -Mark the \f(CW\*(C`MAC\*(C'\fR register as call-clobbered, even if -\&\fB\-mrenesas\fR is given. -.IP "\fB\-mieee\fR" 4 -.IX Item "-mieee" +.IP "\fB\-mno\-fsca\fR" 4 +.IX Item "-mno-fsca" +.PD +Allow or disallow the compiler to emit the \f(CW\*(C`fsca\*(C'\fR instruction for sine +and cosine approximations. The option \fB\-mfsca\fR must be used in +combination with \fB\-funsafe\-math\-optimizations\fR. It is enabled by default +when generating code for \s-1SH4A. \s0 Using \fB\-mno\-fsca\fR disables sine and cosine +approximations even if \fB\-funsafe\-math\-optimizations\fR is in effect. +.IP "\fB\-mfsrra\fR" 4 +.IX Item "-mfsrra" .PD 0 -.IP "\fB\-mno\-ieee\fR" 4 -.IX Item "-mno-ieee" +.IP "\fB\-mno\-fsrra\fR" 4 +.IX Item "-mno-fsrra" .PD -Control the \s-1IEEE\s0 compliance of floating-point comparisons, which affects the -handling of cases where the result of a comparison is unordered. By default -\&\fB\-mieee\fR is implicitly enabled. If \fB\-ffinite\-math\-only\fR is -enabled \fB\-mno\-ieee\fR is implicitly set, which results in faster -floating-point greater-equal and less-equal comparisons. The implcit settings -can be overridden by specifying either \fB\-mieee\fR or \fB\-mno\-ieee\fR. -.IP "\fB\-minline\-ic_invalidate\fR" 4 -.IX Item "-minline-ic_invalidate" -Inline code to invalidate instruction cache entries after setting up -nested function trampolines. -This option has no effect if \fB\-musermode\fR is in effect and the selected -code generation option (e.g. \fB\-m4\fR) does not allow the use of the \f(CW\*(C`icbi\*(C'\fR -instruction. -If the selected code generation option does not allow the use of the \f(CW\*(C`icbi\*(C'\fR -instruction, and \fB\-musermode\fR is not in effect, the inlined code -manipulates the instruction cache address array directly with an associative -write. This not only requires privileged mode at run time, but it also -fails if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped. -.IP "\fB\-misize\fR" 4 -.IX Item "-misize" -Dump instruction size and location in the assembly code. -.IP "\fB\-mpadstruct\fR" 4 -.IX Item "-mpadstruct" -This option is deprecated. It pads structures to multiple of 4 bytes, -which is incompatible with the \s-1SH\s0 \s-1ABI\s0. -.IP "\fB\-matomic\-model=\fR\fImodel\fR" 4 -.IX Item "-matomic-model=model" -Sets the model of atomic operations and additional parameters as a comma -separated list. For details on the atomic built-in functions see -\&\fB_\|_atomic Builtins\fR. The following models and parameters are supported: -.RS 4 -.IP "\fBnone\fR" 4 -.IX Item "none" -Disable compiler generated atomic sequences and emit library calls for atomic -operations. This is the default if the target is not \f(CW\*(C`sh*\-*\-linux*\*(C'\fR. -.IP "\fBsoft-gusa\fR" 4 -.IX Item "soft-gusa" -Generate GNU/Linux compatible gUSA software atomic sequences for the atomic -built-in functions. The generated atomic sequences require additional support -from the interrupt/exception handling code of the system and are only suitable -for SH3* and SH4* single-core systems. This option is enabled by default when -the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH3* or SH4*. When the target is \s-1SH4A\s0, -this option also partially utilizes the hardware atomic instructions -\&\f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR to create more efficient code, unless -\&\fBstrict\fR is specified. -.IP "\fBsoft-tcb\fR" 4 -.IX Item "soft-tcb" -Generate software atomic sequences that use a variable in the thread control -block. This is a variation of the gUSA sequences which can also be used on -SH1* and SH2* targets. The generated atomic sequences require additional -support from the interrupt/exception handling code of the system and are only -suitable for single-core systems. When using this model, the \fBgbr\-offset=\fR -parameter has to be specified as well. -.IP "\fBsoft-imask\fR" 4 -.IX Item "soft-imask" -Generate software atomic sequences that temporarily disable interrupts by -setting \f(CW\*(C`SR.IMASK = 1111\*(C'\fR. This model works only when the program runs -in privileged mode and is only suitable for single-core systems. Additional -support from the interrupt/exception handling code of the system is not -required. This model is enabled by default when the target is -\&\f(CW\*(C`sh*\-*\-linux*\*(C'\fR and SH1* or SH2*. -.IP "\fBhard-llcs\fR" 4 -.IX Item "hard-llcs" -Generate hardware atomic sequences using the \f(CW\*(C`movli.l\*(C'\fR and \f(CW\*(C`movco.l\*(C'\fR -instructions only. This is only available on \s-1SH4A\s0 and is suitable for -multi-core systems. Since the hardware instructions support only 32 bit atomic -variables access to 8 or 16 bit variables is emulated with 32 bit accesses. -Code compiled with this option is also compatible with other software -atomic model interrupt/exception handling systems if executed on an \s-1SH4A\s0 -system. Additional support from the interrupt/exception handling code of the -system is not required for this model. -.IP "\fBgbr\-offset=\fR" 4 -.IX Item "gbr-offset=" -This parameter specifies the offset in bytes of the variable in the thread -control block structure that should be used by the generated atomic sequences -when the \fBsoft-tcb\fR model has been selected. For other models this -parameter is ignored. The specified value must be an integer multiple of four -and in the range 0\-1020. -.IP "\fBstrict\fR" 4 -.IX Item "strict" -This parameter prevents mixed usage of multiple atomic models, even if they -are compatible, and makes the compiler generate atomic sequences of the -specified model only. -.RE -.RS 4 -.RE -.IP "\fB\-mtas\fR" 4 -.IX Item "-mtas" -Generate the \f(CW\*(C`tas.b\*(C'\fR opcode for \f(CW\*(C`_\|_atomic_test_and_set\*(C'\fR. -Notice that depending on the particular hardware and software configuration -this can degrade overall performance due to the operand cache line flushes -that are implied by the \f(CW\*(C`tas.b\*(C'\fR instruction. On multi-core \s-1SH4A\s0 -processors the \f(CW\*(C`tas.b\*(C'\fR instruction must be used with caution since it -can result in data corruption for certain cache configurations. -.IP "\fB\-mprefergot\fR" 4 -.IX Item "-mprefergot" -When generating position-independent code, emit function calls using -the Global Offset Table instead of the Procedure Linkage Table. -.IP "\fB\-musermode\fR" 4 -.IX Item "-musermode" +Allow or disallow the compiler to emit the \f(CW\*(C`fsrra\*(C'\fR instruction for +reciprocal square root approximations. The option \fB\-mfsrra\fR must be used +in combination with \fB\-funsafe\-math\-optimizations\fR and +\&\fB\-ffinite\-math\-only\fR. It is enabled by default when generating code for +\&\s-1SH4A. \s0 Using \fB\-mno\-fsrra\fR disables reciprocal square root approximations +even if \fB\-funsafe\-math\-optimizations\fR and \fB\-ffinite\-math\-only\fR are +in effect. +.IP "\fB\-mpretend\-cmove\fR" 4 +.IX Item "-mpretend-cmove" +Prefer zero-displacement conditional branches for conditional move instruction +patterns. This can result in faster code on the \s-1SH4\s0 processor. +.PP +\fISolaris 2 Options\fR +.IX Subsection "Solaris 2 Options" +.PP +These \fB\-m\fR options are supported on Solaris 2: +.IP "\fB\-mclear\-hwcap\fR" 4 +.IX Item "-mclear-hwcap" +\&\fB\-mclear\-hwcap\fR tells the compiler to remove the hardware +capabilities generated by the Solaris assembler. This is only necessary +when object files use \s-1ISA\s0 extensions not supported by the current +machine, but check at runtime whether or not to use them. +.IP "\fB\-mimpure\-text\fR" 4 +.IX Item "-mimpure-text" +\&\fB\-mimpure\-text\fR, used in addition to \fB\-shared\fR, tells +the compiler to not pass \fB\-z text\fR to the linker when linking a +shared object. Using this option, you can link position-dependent +code into a shared object. +.Sp +\&\fB\-mimpure\-text\fR suppresses the \*(L"relocations remain against +allocatable but non-writable sections\*(R" linker error message. +However, the necessary relocations trigger copy-on-write, and the +shared object is not actually shared across processes. Instead of +using \fB\-mimpure\-text\fR, you should compile all source code with +\&\fB\-fpic\fR or \fB\-fPIC\fR. +.PP +These switches are supported in addition to the above on Solaris 2: +.IP "\fB\-pthreads\fR" 4 +.IX Item "-pthreads" +Add support for multithreading using the \s-1POSIX\s0 threads library. This +option sets flags for both the preprocessor and linker. This option does +not affect the thread safety of object code produced by the compiler or +that of libraries supplied with it. +.IP "\fB\-pthread\fR" 4 +.IX Item "-pthread" +This is a synonym for \fB\-pthreads\fR. +.PP +\fI\s-1SPARC\s0 Options\fR +.IX Subsection "SPARC Options" +.PP +These \fB\-m\fR options are supported on the \s-1SPARC:\s0 +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" .PD 0 -.IP "\fB\-mno\-usermode\fR" 4 -.IX Item "-mno-usermode" +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" .PD -Don't allow (allow) the compiler generating privileged mode code. Specifying -\&\fB\-musermode\fR also implies \fB\-mno\-inline\-ic_invalidate\fR if the -inlined code would not work in user mode. \fB\-musermode\fR is the default -when the target is \f(CW\*(C`sh*\-*\-linux*\*(C'\fR. If the target is SH1* or SH2* -\&\fB\-musermode\fR has no effect, since there is no user mode. -.IP "\fB\-multcost=\fR\fInumber\fR" 4 -.IX Item "-multcost=number" -Set the cost to assume for a multiply insn. -.IP "\fB\-mdiv=\fR\fIstrategy\fR" 4 -.IX Item "-mdiv=strategy" -Set the division strategy to be used for integer division operations. -For SHmedia \fIstrategy\fR can be one of: -.RS 4 -.IP "\fBfp\fR" 4 -.IX Item "fp" -Performs the operation in floating point. This has a very high latency, -but needs only a few instructions, so it might be a good choice if -your code has enough easily-exploitable \s-1ILP\s0 to allow the compiler to -schedule the floating-point instructions together with other instructions. -Division by zero causes a floating-point exception. -.IP "\fBinv\fR" 4 -.IX Item "inv" -Uses integer operations to calculate the inverse of the divisor, -and then multiplies the dividend with the inverse. This strategy allows -\&\s-1CSE\s0 and hoisting of the inverse calculation. Division by zero calculates -an unspecified result, but does not trap. -.IP "\fBinv:minlat\fR" 4 -.IX Item "inv:minlat" -A variant of \fBinv\fR where, if no \s-1CSE\s0 or hoisting opportunities -have been found, or if the entire operation has been hoisted to the same -place, the last stages of the inverse calculation are intertwined with the -final multiply to reduce the overall latency, at the expense of using a few -more instructions, and thus offering fewer scheduling opportunities with -other code. -.IP "\fBcall\fR" 4 -.IX Item "call" -Calls a library function that usually implements the \fBinv:minlat\fR -strategy. -This gives high code density for \f(CW\*(C`m5\-*media\-nofpu\*(C'\fR compilations. -.IP "\fBcall2\fR" 4 -.IX Item "call2" -Uses a different entry point of the same library function, where it -assumes that a pointer to a lookup table has already been set up, which -exposes the pointer load to \s-1CSE\s0 and code hoisting optimizations. -.IP "\fBinv:call\fR" 4 -.IX Item "inv:call" +Specify \fB\-mapp\-regs\fR to generate output using the global registers +2 through 4, which the \s-1SPARC SVR4 ABI\s0 reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. +.Sp +To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss, +specify \fB\-mno\-app\-regs\fR. You should compile libraries and system +software with this option. +.IP "\fB\-mflat\fR" 4 +.IX Item "-mflat" +.PD 0 +.IP "\fB\-mno\-flat\fR" 4 +.IX Item "-mno-flat" +.PD +With \fB\-mflat\fR, the compiler does not generate save/restore instructions +and uses a \*(L"flat\*(R" or single register window model. This model is compatible +with the regular register window model. The local registers and the input +registers (0\-\-5) are still treated as \*(L"call-saved\*(R" registers and are +saved on the stack as needed. +.Sp +With \fB\-mno\-flat\fR (the default), the compiler generates save/restore +instructions (except for leaf functions). This is the normal operating mode. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate output containing floating-point instructions. This is the +default. +.IP "\fB\-mno\-fpu\fR" 4 +.IX Item "-mno-fpu" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate output containing library calls for floating point. +\&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0 +targets. Normally the facilities of the machine's usual C compiler are +used, but this cannot be done directly in cross-compilation. You must make +your own arrangements to provide suitable library functions for +cross-compilation. The embedded targets \fBsparc\-*\-aout\fR and +\&\fBsparclite\-*\-*\fR do provide software floating-point support. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-mhard\-quad\-float\fR" 4 +.IX Item "-mhard-quad-float" +Generate output containing quad-word (long double) floating-point +instructions. +.IP "\fB\-msoft\-quad\-float\fR" 4 +.IX Item "-msoft-quad-float" +Generate output containing library calls for quad-word (long double) +floating-point instructions. The functions called are those specified +in the \s-1SPARC ABI. \s0 This is the default. +.Sp +As of this writing, there are no \s-1SPARC\s0 implementations that have hardware +support for the quad-word floating-point instructions. They all invoke +a trap handler for one of these instructions, and then the trap handler +emulates the effect of the instruction. Because of the trap handler overhead, +this is much slower than calling the \s-1ABI\s0 library routines. Thus the +\&\fB\-msoft\-quad\-float\fR option is the default. +.IP "\fB\-mno\-unaligned\-doubles\fR" 4 +.IX Item "-mno-unaligned-doubles" .PD 0 -.IP "\fBinv:call2\fR" 4 -.IX Item "inv:call2" -.IP "\fBinv:fp\fR" 4 -.IX Item "inv:fp" +.IP "\fB\-munaligned\-doubles\fR" 4 +.IX Item "-munaligned-doubles" .PD -Use the \fBinv\fR algorithm for initial -code generation, but if the code stays unoptimized, revert to the \fBcall\fR, -\&\fBcall2\fR, or \fBfp\fR strategies, respectively. Note that the -potentially-trapping side effect of division by zero is carried by a -separate instruction, so it is possible that all the integer instructions -are hoisted out, but the marker for the side effect stays where it is. -A recombination to floating-point operations or a call is not possible -in that case. -.IP "\fBinv20u\fR" 4 -.IX Item "inv20u" +Assume that doubles have 8\-byte alignment. This is the default. +.Sp +With \fB\-munaligned\-doubles\fR, \s-1GCC\s0 assumes that doubles have 8\-byte +alignment only if they are contained in another type, or if they have an +absolute address. Otherwise, it assumes they have 4\-byte alignment. +Specifying this option avoids some rare compatibility problems with code +generated by other compilers. It is not the default because it results +in a performance loss, especially for floating-point code. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" .PD 0 -.IP "\fBinv20l\fR" 4 -.IX Item "inv20l" +.IP "\fB\-mno\-user\-mode\fR" 4 +.IX Item "-mno-user-mode" .PD -Variants of the \fBinv:minlat\fR strategy. In the case -that the inverse calculation is not separated from the multiply, they speed -up division where the dividend fits into 20 bits (plus sign where applicable) -by inserting a test to skip a number of operations in this case; this test -slows down the case of larger dividends. \fBinv20u\fR assumes the case of a such -a small dividend to be unlikely, and \fBinv20l\fR assumes it to be likely. -.RE -.RS 4 +Do not generate code that can only run in supervisor mode. This is relevant +only for the \f(CW\*(C`casa\*(C'\fR instruction emitted for the \s-1LEON3\s0 processor. The +default is \fB\-mno\-user\-mode\fR. +.IP "\fB\-mno\-faster\-structs\fR" 4 +.IX Item "-mno-faster-structs" +.PD 0 +.IP "\fB\-mfaster\-structs\fR" 4 +.IX Item "-mfaster-structs" +.PD +With \fB\-mfaster\-structs\fR, the compiler assumes that structures +should have 8\-byte alignment. This enables the use of pairs of +\&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure +assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs. +However, the use of this changed alignment directly violates the \s-1SPARC +ABI. \s0 Thus, it's intended only for use on targets where the developer +acknowledges that their resulting code is not directly in line with +the rules of the \s-1ABI.\s0 +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set, register set, and instruction scheduling parameters +for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are +\&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, +\&\fBleon\fR, \fBleon3\fR, \fBleon3v7\fR, \fBsparclite\fR, \fBf930\fR, +\&\fBf934\fR, \fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, +\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, +\&\fBniagara3\fR and \fBniagara4\fR. .Sp -For targets other than SHmedia \fIstrategy\fR can be one of: -.IP "\fBcall\-div1\fR" 4 -.IX Item "call-div1" -Calls a library function that uses the single-step division instruction -\&\f(CW\*(C`div1\*(C'\fR to perform the operation. Division by zero calculates an -unspecified result and does not trap. This is the default except for \s-1SH4\s0, -\&\s-1SH2A\s0 and SHcompact. -.IP "\fBcall-fp\fR" 4 -.IX Item "call-fp" -Calls a library function that performs the operation in double precision -floating point. Division by zero causes a floating-point exception. This is -the default for SHcompact with \s-1FPU\s0. Specifying this for targets that do not -have a double precision \s-1FPU\s0 defaults to \f(CW\*(C`call\-div1\*(C'\fR. -.IP "\fBcall-table\fR" 4 -.IX Item "call-table" -Calls a library function that uses a lookup table for small divisors and -the \f(CW\*(C`div1\*(C'\fR instruction with case distinction for larger divisors. Division -by zero calculates an unspecified result and does not trap. This is the default -for \s-1SH4\s0. Specifying this for targets that do not have dynamic shift -instructions defaults to \f(CW\*(C`call\-div1\*(C'\fR. +Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, +which selects the best architecture option for the host processor. +\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize +the processor. +.Sp +Default instruction scheduling parameters are used for values that select +an architecture and not an implementation. These are \fBv7\fR, \fBv8\fR, +\&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR. +.Sp +Here is a list of each supported architecture and their supported +implementations. +.RS 4 +.IP "v7" 4 +.IX Item "v7" +cypress, leon3v7 +.IP "v8" 4 +.IX Item "v8" +supersparc, hypersparc, leon, leon3 +.IP "sparclite" 4 +.IX Item "sparclite" +f930, f934, sparclite86x +.IP "sparclet" 4 +.IX Item "sparclet" +tsc701 +.IP "v9" 4 +.IX Item "v9" +ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4 .RE .RS 4 .Sp -When a division strategy has not been specified the default strategy is -selected based on the current target. For \s-1SH2A\s0 the default strategy is to -use the \f(CW\*(C`divs\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions instead of library function -calls. +By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7 +variant of the \s-1SPARC\s0 architecture. With \fB\-mcpu=cypress\fR, the compiler +additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the +SPARCStation/SPARCServer 3xx series. This is also appropriate for the older +SPARCStation 1, 2, \s-1IPX\s0 etc. +.Sp +With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0 +architecture. The only difference from V7 code is that the compiler emits +the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0 +but not in \s-1SPARC\-V7. \s0 With \fB\-mcpu=supersparc\fR, the compiler additionally +optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and +2000 series. +.Sp +With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step +and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7.\s0 +With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the +Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU. \s0 With +\&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu +\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU.\s0 +.Sp +With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of +the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate, +integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet +but not in \s-1SPARC\-V7. \s0 With \fB\-mcpu=tsc701\fR, the compiler additionally +optimizes it for the \s-1TEMIC\s0 SPARClet chip. +.Sp +With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0 +architecture. This adds 64\-bit integer and floating-point move instructions, +3 additional floating-point condition code registers and conditional move +instructions. With \fB\-mcpu=ultrasparc\fR, the compiler additionally +optimizes it for the Sun UltraSPARC I/II/IIi chips. With +\&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the +Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With +\&\fB\-mcpu=niagara\fR, the compiler additionally optimizes it for +Sun UltraSPARC T1 chips. With \fB\-mcpu=niagara2\fR, the compiler +additionally optimizes it for Sun UltraSPARC T2 chips. With +\&\fB\-mcpu=niagara3\fR, the compiler additionally optimizes it for Sun +UltraSPARC T3 chips. With \fB\-mcpu=niagara4\fR, the compiler +additionally optimizes it for Sun UltraSPARC T4 chips. .RE -.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 -.IX Item "-maccumulate-outgoing-args" -Reserve space once for outgoing arguments in the function prologue rather -than around each call. Generally beneficial for performance and size. Also -needed for unwinding to avoid changing the stack frame around conditional code. -.IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4 -.IX Item "-mdivsi3_libfunc=name" -Set the name of the library function used for 32\-bit signed division to -\&\fIname\fR. -This only affects the name used in the \fBcall\fR and \fBinv:call\fR -division strategies, and the compiler still expects the same -sets of input/output/clobbered registers as if this option were not present. -.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 -.IX Item "-mfixed-range=register-range" -Generate code treating the given register range as fixed registers. -A fixed register is one that the register allocator can not use. This is -useful when compiling kernel code. A register range is specified as -two registers separated by a dash. Multiple register ranges can be -specified separated by a comma. -.IP "\fB\-mindexed\-addressing\fR" 4 -.IX Item "-mindexed-addressing" -Enable the use of the indexed addressing mode for SHmedia32/SHcompact. -This is only safe if the hardware and/or \s-1OS\s0 implement 32\-bit wrap-around -semantics for the indexed addressing mode. The architecture allows the -implementation of processors with 64\-bit \s-1MMU\s0, which the \s-1OS\s0 could use to -get 32\-bit addressing, but since no current hardware implementation supports -this or any other way to make the indexed addressing mode safe to use in -the 32\-bit \s-1ABI\s0, the default is \fB\-mno\-indexed\-addressing\fR. -.IP "\fB\-mgettrcost=\fR\fInumber\fR" 4 -.IX Item "-mgettrcost=number" -Set the cost assumed for the \f(CW\*(C`gettr\*(C'\fR instruction to \fInumber\fR. -The default is 2 if \fB\-mpt\-fixed\fR is in effect, 100 otherwise. -.IP "\fB\-mpt\-fixed\fR" 4 -.IX Item "-mpt-fixed" -Assume \f(CW\*(C`pt*\*(C'\fR instructions won't trap. This generally generates -better-scheduled code, but is unsafe on current hardware. -The current architecture -definition says that \f(CW\*(C`ptabs\*(C'\fR and \f(CW\*(C`ptrel\*(C'\fR trap when the target -anded with 3 is 3. -This has the unintentional effect of making it unsafe to schedule these -instructions before a branch, or hoist them out of a loop. For example, -\&\f(CW\*(C`_\|_do_global_ctors\*(C'\fR, a part of \fIlibgcc\fR -that runs constructors at program -startup, calls functions in a list which is delimited by \-1. With the -\&\fB\-mpt\-fixed\fR option, the \f(CW\*(C`ptabs\*(C'\fR is done before testing against \-1. -That means that all the constructors run a bit more quickly, but when -the loop comes to the end of the list, the program crashes because \f(CW\*(C`ptabs\*(C'\fR -loads \-1 into a target register. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type +\&\fIcpu_type\fR, but do not set the instruction set or register set that the +option \fB\-mcpu=\fR\fIcpu_type\fR does. .Sp -Since this option is unsafe for any -hardware implementing the current architecture specification, the default -is \fB\-mno\-pt\-fixed\fR. Unless specified explicitly with -\&\fB\-mgettrcost\fR, \fB\-mno\-pt\-fixed\fR also implies \fB\-mgettrcost=100\fR; -this deters register allocation from using target registers for storing -ordinary integers. -.IP "\fB\-minvalid\-symbols\fR" 4 -.IX Item "-minvalid-symbols" -Assume symbols might be invalid. Ordinary function symbols generated by -the compiler are always valid to load with -\&\f(CW\*(C`movi\*(C'\fR/\f(CW\*(C`shori\*(C'\fR/\f(CW\*(C`ptabs\*(C'\fR or -\&\f(CW\*(C`movi\*(C'\fR/\f(CW\*(C`shori\*(C'\fR/\f(CW\*(C`ptrel\*(C'\fR, -but with assembler and/or linker tricks it is possible -to generate symbols that cause \f(CW\*(C`ptabs\*(C'\fR or \f(CW\*(C`ptrel\*(C'\fR to trap. -This option is only meaningful when \fB\-mno\-pt\-fixed\fR is in effect. -It prevents cross-basic-block \s-1CSE\s0, hoisting and most scheduling -of symbol loads. The default is \fB\-mno\-invalid\-symbols\fR. -.IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4 -.IX Item "-mbranch-cost=num" -Assume \fInum\fR to be the cost for a branch instruction. Higher numbers -make the compiler try to generate more branch-free code if possible. -If not specified the value is selected depending on the processor type that -is being compiled for. -.IP "\fB\-mzdcbranch\fR" 4 -.IX Item "-mzdcbranch" +The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for +\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those +that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, +\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBleon3\fR, +\&\fBleon3v7\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, \fBtsc701\fR, +\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, +\&\fBniagara3\fR and \fBniagara4\fR. With native Solaris and GNU/Linux +toolchains, \fBnative\fR can also be used. +.IP "\fB\-mv8plus\fR" 4 +.IX Item "-mv8plus" +.PD 0 +.IP "\fB\-mno\-v8plus\fR" 4 +.IX Item "-mno-v8plus" +.PD +With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+ ABI. \s0 The +difference from the V8 \s-1ABI\s0 is that the global and out registers are +considered 64 bits wide. This is enabled by default on Solaris in 32\-bit +mode for all \s-1SPARC\-V9\s0 processors. +.IP "\fB\-mvis\fR" 4 +.IX Item "-mvis" .PD 0 -.IP "\fB\-mno\-zdcbranch\fR" 4 -.IX Item "-mno-zdcbranch" +.IP "\fB\-mno\-vis\fR" 4 +.IX Item "-mno-vis" .PD -Assume (do not assume) that zero displacement conditional branch instructions -\&\f(CW\*(C`bt\*(C'\fR and \f(CW\*(C`bf\*(C'\fR are fast. If \fB\-mzdcbranch\fR is specified, the -compiler prefers zero displacement branch code sequences. This is -enabled by default when generating code for \s-1SH4\s0 and \s-1SH4A\s0. It can be explicitly -disabled by specifying \fB\-mno\-zdcbranch\fR. -.IP "\fB\-mfused\-madd\fR" 4 -.IX Item "-mfused-madd" +With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Visual Instruction Set extensions. The default is \fB\-mno\-vis\fR. +.IP "\fB\-mvis2\fR" 4 +.IX Item "-mvis2" .PD 0 -.IP "\fB\-mno\-fused\-madd\fR" 4 -.IX Item "-mno-fused-madd" +.IP "\fB\-mno\-vis2\fR" 4 +.IX Item "-mno-vis2" .PD -Generate code that uses (does not use) the floating-point multiply and -accumulate instructions. These instructions are generated by default -if hardware floating point is used. The machine-dependent -\&\fB\-mfused\-madd\fR option is now mapped to the machine-independent -\&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is -mapped to \fB\-ffp\-contract=off\fR. -.IP "\fB\-mfsca\fR" 4 -.IX Item "-mfsca" +With \fB\-mvis2\fR, \s-1GCC\s0 generates code that takes advantage of +version 2.0 of the UltraSPARC Visual Instruction Set extensions. The +default is \fB\-mvis2\fR when targeting a cpu that supports such +instructions, such as UltraSPARC-III and later. Setting \fB\-mvis2\fR +also sets \fB\-mvis\fR. +.IP "\fB\-mvis3\fR" 4 +.IX Item "-mvis3" .PD 0 -.IP "\fB\-mno\-fsca\fR" 4 -.IX Item "-mno-fsca" +.IP "\fB\-mno\-vis3\fR" 4 +.IX Item "-mno-vis3" .PD -Allow or disallow the compiler to emit the \f(CW\*(C`fsca\*(C'\fR instruction for sine -and cosine approximations. The option \fB\-mfsca\fR must be used in -combination with \fB\-funsafe\-math\-optimizations\fR. It is enabled by default -when generating code for \s-1SH4A\s0. Using \fB\-mno\-fsca\fR disables sine and cosine -approximations even if \fB\-funsafe\-math\-optimizations\fR is in effect. -.IP "\fB\-mfsrra\fR" 4 -.IX Item "-mfsrra" +With \fB\-mvis3\fR, \s-1GCC\s0 generates code that takes advantage of +version 3.0 of the UltraSPARC Visual Instruction Set extensions. The +default is \fB\-mvis3\fR when targeting a cpu that supports such +instructions, such as niagara\-3 and later. Setting \fB\-mvis3\fR +also sets \fB\-mvis2\fR and \fB\-mvis\fR. +.IP "\fB\-mcbcond\fR" 4 +.IX Item "-mcbcond" .PD 0 -.IP "\fB\-mno\-fsrra\fR" 4 -.IX Item "-mno-fsrra" +.IP "\fB\-mno\-cbcond\fR" 4 +.IX Item "-mno-cbcond" .PD -Allow or disallow the compiler to emit the \f(CW\*(C`fsrra\*(C'\fR instruction for -reciprocal square root approximations. The option \fB\-mfsrra\fR must be used -in combination with \fB\-funsafe\-math\-optimizations\fR and -\&\fB\-ffinite\-math\-only\fR. It is enabled by default when generating code for -\&\s-1SH4A\s0. Using \fB\-mno\-fsrra\fR disables reciprocal square root approximations -even if \fB\-funsafe\-math\-optimizations\fR and \fB\-ffinite\-math\-only\fR are -in effect. -.IP "\fB\-mpretend\-cmove\fR" 4 -.IX Item "-mpretend-cmove" -Prefer zero-displacement conditional branches for conditional move instruction -patterns. This can result in faster code on the \s-1SH4\s0 processor. -.PP -\fISolaris 2 Options\fR -.IX Subsection "Solaris 2 Options" +With \fB\-mcbcond\fR, \s-1GCC\s0 generates code that takes advantage of +compare-and-branch instructions, as defined in the Sparc Architecture 2011. +The default is \fB\-mcbcond\fR when targeting a cpu that supports such +instructions, such as niagara\-4 and later. +.IP "\fB\-mpopc\fR" 4 +.IX Item "-mpopc" +.PD 0 +.IP "\fB\-mno\-popc\fR" 4 +.IX Item "-mno-popc" +.PD +With \fB\-mpopc\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +population count instruction. The default is \fB\-mpopc\fR +when targeting a cpu that supports such instructions, such as Niagara\-2 and +later. +.IP "\fB\-mfmaf\fR" 4 +.IX Item "-mfmaf" +.PD 0 +.IP "\fB\-mno\-fmaf\fR" 4 +.IX Item "-mno-fmaf" +.PD +With \fB\-mfmaf\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC +Fused Multiply-Add Floating-point extensions. The default is \fB\-mfmaf\fR +when targeting a cpu that supports such instructions, such as Niagara\-3 and +later. +.IP "\fB\-mfix\-at697f\fR" 4 +.IX Item "-mfix-at697f" +Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 +processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.IP "\fB\-mfix\-ut699\fR" 4 +.IX Item "-mfix-ut699" +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the \s-1UT699\s0 processor. .PP -These \fB\-m\fR options are supported on Solaris 2: -.IP "\fB\-mclear\-hwcap\fR" 4 -.IX Item "-mclear-hwcap" -\&\fB\-mclear\-hwcap\fR tells the compiler to remove the hardware -capabilities generated by the Solaris assembler. This is only necessary -when object files use \s-1ISA\s0 extensions not supported by the current -machine, but check at runtime whether or not to use them. -.IP "\fB\-mimpure\-text\fR" 4 -.IX Item "-mimpure-text" -\&\fB\-mimpure\-text\fR, used in addition to \fB\-shared\fR, tells -the compiler to not pass \fB\-z text\fR to the linker when linking a -shared object. Using this option, you can link position-dependent -code into a shared object. +These \fB\-m\fR options are supported in addition to the above +on \s-1SPARC\-V9\s0 processors in 64\-bit environments: +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.PD +Generate code for a 32\-bit or 64\-bit environment. +The 32\-bit environment sets int, long and pointer to 32 bits. +The 64\-bit environment sets int to 32 bits and long and pointer +to 64 bits. +.IP "\fB\-mcmodel=\fR\fIwhich\fR" 4 +.IX Item "-mcmodel=which" +Set the code model to one of +.RS 4 +.IP "\fBmedlow\fR" 4 +.IX Item "medlow" +The Medium/Low code model: 64\-bit addresses, programs +must be linked in the low 32 bits of memory. Programs can be statically +or dynamically linked. +.IP "\fBmedmid\fR" 4 +.IX Item "medmid" +The Medium/Middle code model: 64\-bit addresses, programs +must be linked in the low 44 bits of memory, the text and data segments must +be less than 2GB in size and the data segment must be located within 2GB of +the text segment. +.IP "\fBmedany\fR" 4 +.IX Item "medany" +The Medium/Anywhere code model: 64\-bit addresses, programs +may be linked anywhere in memory, the text and data segments must be less +than 2GB in size and the data segment must be located within 2GB of the +text segment. +.IP "\fBembmedany\fR" 4 +.IX Item "embmedany" +The Medium/Anywhere code model for embedded systems: +64\-bit addresses, the text and data segments must be less than 2GB in +size, both starting anywhere in memory (determined at link time). The +global register \f(CW%g4\fR points to the base of the data segment. Programs +are statically linked and \s-1PIC\s0 is not supported. +.RE +.RS 4 +.RE +.IP "\fB\-mmemory\-model=\fR\fImem-model\fR" 4 +.IX Item "-mmemory-model=mem-model" +Set the memory model in force on the processor to one of +.RS 4 +.IP "\fBdefault\fR" 4 +.IX Item "default" +The default memory model for the processor and operating system. +.IP "\fBrmo\fR" 4 +.IX Item "rmo" +Relaxed Memory Order +.IP "\fBpso\fR" 4 +.IX Item "pso" +Partial Store Order +.IP "\fBtso\fR" 4 +.IX Item "tso" +Total Store Order +.IP "\fBsc\fR" 4 +.IX Item "sc" +Sequential Consistency +.RE +.RS 4 .Sp -\&\fB\-mimpure\-text\fR suppresses the \*(L"relocations remain against -allocatable but non-writable sections\*(R" linker error message. -However, the necessary relocations trigger copy-on-write, and the -shared object is not actually shared across processes. Instead of -using \fB\-mimpure\-text\fR, you should compile all source code with -\&\fB\-fpic\fR or \fB\-fPIC\fR. -.PP -These switches are supported in addition to the above on Solaris 2: -.IP "\fB\-pthreads\fR" 4 -.IX Item "-pthreads" -Add support for multithreading using the \s-1POSIX\s0 threads library. This -option sets flags for both the preprocessor and linker. This option does -not affect the thread safety of object code produced by the compiler or -that of libraries supplied with it. -.IP "\fB\-pthread\fR" 4 -.IX Item "-pthread" -This is a synonym for \fB\-pthreads\fR. +These memory models are formally defined in Appendix D of the Sparc V9 +architecture manual, as set in the processor's \f(CW\*(C`PSTATE.MM\*(C'\fR field. +.RE +.IP "\fB\-mstack\-bias\fR" 4 +.IX Item "-mstack-bias" +.PD 0 +.IP "\fB\-mno\-stack\-bias\fR" 4 +.IX Item "-mno-stack-bias" +.PD +With \fB\-mstack\-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and +frame pointer if present, are offset by \-2047 which must be added back +when making stack frame references. This is the default in 64\-bit mode. +Otherwise, assume no such offset is present. .PP -\fI\s-1SPARC\s0 Options\fR -.IX Subsection "SPARC Options" +\fI\s-1SPU\s0 Options\fR +.IX Subsection "SPU Options" .PP -These \fB\-m\fR options are supported on the \s-1SPARC:\s0 -.IP "\fB\-mno\-app\-regs\fR" 4 -.IX Item "-mno-app-regs" +These \fB\-m\fR options are supported on the \s-1SPU:\s0 +.IP "\fB\-mwarn\-reloc\fR" 4 +.IX Item "-mwarn-reloc" .PD 0 -.IP "\fB\-mapp\-regs\fR" 4 -.IX Item "-mapp-regs" +.IP "\fB\-merror\-reloc\fR" 4 +.IX Item "-merror-reloc" .PD -Specify \fB\-mapp\-regs\fR to generate output using the global registers -2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. Like the -global register 1, each global register 2 through 4 is then treated as an -allocable register that is clobbered by function calls. This is the default. -.Sp -To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss, -specify \fB\-mno\-app\-regs\fR. You should compile libraries and system -software with this option. -.IP "\fB\-mflat\fR" 4 -.IX Item "-mflat" +The loader for \s-1SPU\s0 does not handle dynamic relocations. By default, \s-1GCC\s0 +gives an error when it generates code that requires a dynamic +relocation. \fB\-mno\-error\-reloc\fR disables the error, +\&\fB\-mwarn\-reloc\fR generates a warning instead. +.IP "\fB\-msafe\-dma\fR" 4 +.IX Item "-msafe-dma" .PD 0 -.IP "\fB\-mno\-flat\fR" 4 -.IX Item "-mno-flat" +.IP "\fB\-munsafe\-dma\fR" 4 +.IX Item "-munsafe-dma" .PD -With \fB\-mflat\fR, the compiler does not generate save/restore instructions -and uses a \*(L"flat\*(R" or single register window model. This model is compatible -with the regular register window model. The local registers and the input -registers (0\-\-5) are still treated as \*(L"call-saved\*(R" registers and are -saved on the stack as needed. -.Sp -With \fB\-mno\-flat\fR (the default), the compiler generates save/restore -instructions (except for leaf functions). This is the normal operating mode. -.IP "\fB\-mfpu\fR" 4 -.IX Item "-mfpu" +Instructions that initiate or test completion of \s-1DMA\s0 must not be +reordered with respect to loads and stores of the memory that is being +accessed. +With \fB\-munsafe\-dma\fR you must use the \f(CW\*(C`volatile\*(C'\fR keyword to protect +memory accesses, but that can lead to inefficient code in places where the +memory is known to not change. Rather than mark the memory as volatile, +you can use \fB\-msafe\-dma\fR to tell the compiler to treat +the \s-1DMA\s0 instructions as potentially affecting all memory. +.IP "\fB\-mbranch\-hints\fR" 4 +.IX Item "-mbranch-hints" +By default, \s-1GCC\s0 generates a branch hint instruction to avoid +pipeline stalls for always-taken or probably-taken branches. A hint +is not generated closer than 8 instructions away from its branch. +There is little reason to disable them, except for debugging purposes, +or to make an object a little bit smaller. +.IP "\fB\-msmall\-mem\fR" 4 +.IX Item "-msmall-mem" .PD 0 -.IP "\fB\-mhard\-float\fR" 4 -.IX Item "-mhard-float" +.IP "\fB\-mlarge\-mem\fR" 4 +.IX Item "-mlarge-mem" .PD -Generate output containing floating-point instructions. This is the -default. -.IP "\fB\-mno\-fpu\fR" 4 -.IX Item "-mno-fpu" +By default, \s-1GCC\s0 generates code assuming that addresses are never larger +than 18 bits. With \fB\-mlarge\-mem\fR code is generated that assumes +a full 32\-bit address. +.IP "\fB\-mstdmain\fR" 4 +.IX Item "-mstdmain" +By default, \s-1GCC\s0 links against startup code that assumes the SPU-style +main function interface (which has an unconventional parameter list). +With \fB\-mstdmain\fR, \s-1GCC\s0 links your program against startup +code that assumes a C99\-style interface to \f(CW\*(C`main\*(C'\fR, including a +local copy of \f(CW\*(C`argv\*(C'\fR strings. +.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 +.IX Item "-mfixed-range=register-range" +Generate code treating the given register range as fixed registers. +A fixed register is one that the register allocator cannot use. This is +useful when compiling kernel code. A register range is specified as +two registers separated by a dash. Multiple register ranges can be +specified separated by a comma. +.IP "\fB\-mea32\fR" 4 +.IX Item "-mea32" .PD 0 -.IP "\fB\-msoft\-float\fR" 4 -.IX Item "-msoft-float" +.IP "\fB\-mea64\fR" 4 +.IX Item "-mea64" .PD -Generate output containing library calls for floating point. -\&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0 -targets. Normally the facilities of the machine's usual C compiler are -used, but this cannot be done directly in cross-compilation. You must make -your own arrangements to provide suitable library functions for -cross-compilation. The embedded targets \fBsparc\-*\-aout\fR and -\&\fBsparclite\-*\-*\fR do provide software floating-point support. -.Sp -\&\fB\-msoft\-float\fR changes the calling convention in the output file; -therefore, it is only useful if you compile \fIall\fR of a program with -this option. In particular, you need to compile \fIlibgcc.a\fR, the -library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for -this to work. -.IP "\fB\-mhard\-quad\-float\fR" 4 -.IX Item "-mhard-quad-float" -Generate output containing quad-word (long double) floating-point -instructions. -.IP "\fB\-msoft\-quad\-float\fR" 4 -.IX Item "-msoft-quad-float" -Generate output containing library calls for quad-word (long double) -floating-point instructions. The functions called are those specified -in the \s-1SPARC\s0 \s-1ABI\s0. This is the default. -.Sp -As of this writing, there are no \s-1SPARC\s0 implementations that have hardware -support for the quad-word floating-point instructions. They all invoke -a trap handler for one of these instructions, and then the trap handler -emulates the effect of the instruction. Because of the trap handler overhead, -this is much slower than calling the \s-1ABI\s0 library routines. Thus the -\&\fB\-msoft\-quad\-float\fR option is the default. -.IP "\fB\-mno\-unaligned\-doubles\fR" 4 -.IX Item "-mno-unaligned-doubles" +Compile code assuming that pointers to the \s-1PPU\s0 address space accessed +via the \f(CW\*(C`_\|_ea\*(C'\fR named address space qualifier are either 32 or 64 +bits wide. The default is 32 bits. As this is an ABI-changing option, +all object code in an executable must be compiled with the same setting. +.IP "\fB\-maddress\-space\-conversion\fR" 4 +.IX Item "-maddress-space-conversion" .PD 0 -.IP "\fB\-munaligned\-doubles\fR" 4 -.IX Item "-munaligned-doubles" +.IP "\fB\-mno\-address\-space\-conversion\fR" 4 +.IX Item "-mno-address-space-conversion" .PD -Assume that doubles have 8\-byte alignment. This is the default. -.Sp -With \fB\-munaligned\-doubles\fR, \s-1GCC\s0 assumes that doubles have 8\-byte -alignment only if they are contained in another type, or if they have an -absolute address. Otherwise, it assumes they have 4\-byte alignment. -Specifying this option avoids some rare compatibility problems with code -generated by other compilers. It is not the default because it results -in a performance loss, especially for floating-point code. -.IP "\fB\-muser\-mode\fR" 4 -.IX Item "-muser-mode" +Allow/disallow treating the \f(CW\*(C`_\|_ea\*(C'\fR address space as superset +of the generic address space. This enables explicit type casts +between \f(CW\*(C`_\|_ea\*(C'\fR and generic pointer as well as implicit +conversions of generic pointers to \f(CW\*(C`_\|_ea\*(C'\fR pointers. The +default is to allow address space pointer conversions. +.IP "\fB\-mcache\-size=\fR\fIcache-size\fR" 4 +.IX Item "-mcache-size=cache-size" +This option controls the version of libgcc that the compiler links to an +executable and selects a software-managed cache for accessing variables +in the \f(CW\*(C`_\|_ea\*(C'\fR address space with a particular cache size. Possible +options for \fIcache-size\fR are \fB8\fR, \fB16\fR, \fB32\fR, \fB64\fR +and \fB128\fR. The default cache size is 64KB. +.IP "\fB\-matomic\-updates\fR" 4 +.IX Item "-matomic-updates" .PD 0 -.IP "\fB\-mno\-user\-mode\fR" 4 -.IX Item "-mno-user-mode" +.IP "\fB\-mno\-atomic\-updates\fR" 4 +.IX Item "-mno-atomic-updates" .PD -Do not generate code that can only run in supervisor mode. This is relevant -only for the \f(CW\*(C`casa\*(C'\fR instruction emitted for the \s-1LEON3\s0 processor. The -default is \fB\-mno\-user\-mode\fR. -.IP "\fB\-mno\-faster\-structs\fR" 4 -.IX Item "-mno-faster-structs" +This option controls the version of libgcc that the compiler links to an +executable and selects whether atomic updates to the software-managed +cache of PPU-side variables are used. If you use atomic updates, changes +to a \s-1PPU\s0 variable from \s-1SPU\s0 code using the \f(CW\*(C`_\|_ea\*(C'\fR named address space +qualifier do not interfere with changes to other \s-1PPU\s0 variables residing +in the same cache line from \s-1PPU\s0 code. If you do not use atomic updates, +such interference may occur; however, writing back cache lines is +more efficient. The default behavior is to use atomic updates. +.IP "\fB\-mdual\-nops\fR" 4 +.IX Item "-mdual-nops" .PD 0 -.IP "\fB\-mfaster\-structs\fR" 4 -.IX Item "-mfaster-structs" +.IP "\fB\-mdual\-nops=\fR\fIn\fR" 4 +.IX Item "-mdual-nops=n" .PD -With \fB\-mfaster\-structs\fR, the compiler assumes that structures -should have 8\-byte alignment. This enables the use of pairs of -\&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure -assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs. -However, the use of this changed alignment directly violates the \s-1SPARC\s0 -\&\s-1ABI\s0. Thus, it's intended only for use on targets where the developer -acknowledges that their resulting code is not directly in line with -the rules of the \s-1ABI\s0. -.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 -.IX Item "-mcpu=cpu_type" -Set the instruction set, register set, and instruction scheduling parameters -for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are -\&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, -\&\fBleon\fR, \fBleon3\fR, \fBleon3v7\fR, \fBsparclite\fR, \fBf930\fR, -\&\fBf934\fR, \fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, -\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, -\&\fBniagara3\fR and \fBniagara4\fR. -.Sp -Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, -which selects the best architecture option for the host processor. -\&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize -the processor. -.Sp -Default instruction scheduling parameters are used for values that select -an architecture and not an implementation. These are \fBv7\fR, \fBv8\fR, -\&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR. -.Sp -Here is a list of each supported architecture and their supported -implementations. -.RS 4 -.IP "v7" 4 -.IX Item "v7" -cypress, leon3v7 -.IP "v8" 4 -.IX Item "v8" -supersparc, hypersparc, leon, leon3 -.IP "sparclite" 4 -.IX Item "sparclite" -f930, f934, sparclite86x -.IP "sparclet" 4 -.IX Item "sparclet" -tsc701 -.IP "v9" 4 -.IX Item "v9" -ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4 -.RE -.RS 4 -.Sp -By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7 -variant of the \s-1SPARC\s0 architecture. With \fB\-mcpu=cypress\fR, the compiler -additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the -SPARCStation/SPARCServer 3xx series. This is also appropriate for the older -SPARCStation 1, 2, \s-1IPX\s0 etc. -.Sp -With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0 -architecture. The only difference from V7 code is that the compiler emits -the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0 -but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=supersparc\fR, the compiler additionally -optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and -2000 series. -.Sp -With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of -the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step -and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7\s0. -With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the -Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU\s0. With -\&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu -\&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU\s0. -.Sp -With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of -the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate, -integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet -but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=tsc701\fR, the compiler additionally -optimizes it for the \s-1TEMIC\s0 SPARClet chip. -.Sp -With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0 -architecture. This adds 64\-bit integer and floating-point move instructions, -3 additional floating-point condition code registers and conditional move -instructions. With \fB\-mcpu=ultrasparc\fR, the compiler additionally -optimizes it for the Sun UltraSPARC I/II/IIi chips. With -\&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the -Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With -\&\fB\-mcpu=niagara\fR, the compiler additionally optimizes it for -Sun UltraSPARC T1 chips. With \fB\-mcpu=niagara2\fR, the compiler -additionally optimizes it for Sun UltraSPARC T2 chips. With -\&\fB\-mcpu=niagara3\fR, the compiler additionally optimizes it for Sun -UltraSPARC T3 chips. With \fB\-mcpu=niagara4\fR, the compiler -additionally optimizes it for Sun UltraSPARC T4 chips. -.RE -.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 -.IX Item "-mtune=cpu_type" -Set the instruction scheduling parameters for machine type -\&\fIcpu_type\fR, but do not set the instruction set or register set that the -option \fB\-mcpu=\fR\fIcpu_type\fR does. -.Sp -The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for -\&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those -that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, -\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBleon3\fR, -\&\fBleon3v7\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, \fBtsc701\fR, -\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, -\&\fBniagara3\fR and \fBniagara4\fR. With native Solaris and GNU/Linux -toolchains, \fBnative\fR can also be used. -.IP "\fB\-mv8plus\fR" 4 -.IX Item "-mv8plus" +By default, \s-1GCC\s0 inserts nops to increase dual issue when it expects +it to increase performance. \fIn\fR can be a value from 0 to 10. A +smaller \fIn\fR inserts fewer nops. 10 is the default, 0 is the +same as \fB\-mno\-dual\-nops\fR. Disabled with \fB\-Os\fR. +.IP "\fB\-mhint\-max\-nops=\fR\fIn\fR" 4 +.IX Item "-mhint-max-nops=n" +Maximum number of nops to insert for a branch hint. A branch hint must +be at least 8 instructions away from the branch it is affecting. \s-1GCC\s0 +inserts up to \fIn\fR nops to enforce this, otherwise it does not +generate the branch hint. +.IP "\fB\-mhint\-max\-distance=\fR\fIn\fR" 4 +.IX Item "-mhint-max-distance=n" +The encoding of the branch hint instruction limits the hint to be within +256 instructions of the branch it is affecting. By default, \s-1GCC\s0 makes +sure it is within 125. +.IP "\fB\-msafe\-hints\fR" 4 +.IX Item "-msafe-hints" +Work around a hardware bug that causes the \s-1SPU\s0 to stall indefinitely. +By default, \s-1GCC\s0 inserts the \f(CW\*(C`hbrp\*(C'\fR instruction to make sure +this stall won't happen. +.PP +\fIOptions for System V\fR +.IX Subsection "Options for System V" +.PP +These additional options are available on System V Release 4 for +compatibility with other compilers on those systems: +.IP "\fB\-G\fR" 4 +.IX Item "-G" +Create a shared object. +It is recommended that \fB\-symbolic\fR or \fB\-shared\fR be used instead. +.IP "\fB\-Qy\fR" 4 +.IX Item "-Qy" +Identify the versions of each tool used by the compiler, in a +\&\f(CW\*(C`.ident\*(C'\fR assembler directive in the output. +.IP "\fB\-Qn\fR" 4 +.IX Item "-Qn" +Refrain from adding \f(CW\*(C`.ident\*(C'\fR directives to the output file (this is +the default). +.IP "\fB\-YP,\fR\fIdirs\fR" 4 +.IX Item "-YP,dirs" +Search the directories \fIdirs\fR, and no others, for libraries +specified with \fB\-l\fR. +.IP "\fB\-Ym,\fR\fIdir\fR" 4 +.IX Item "-Ym,dir" +Look in the directory \fIdir\fR to find the M4 preprocessor. +The assembler uses this option. +.PP +\fITILE-Gx Options\fR +.IX Subsection "TILE-Gx Options" +.PP +These \fB\-m\fR options are supported on the TILE-Gx: +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small model. The distance for direct calls is +limited to 500M in either direction. PC-relative addresses are 32 +bits. Absolute addresses support the full address range. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large model. There is no limitation on call +distance, pc-relative addresses, or absolute addresses. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported +type is \fBtilegx\fR. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" .PD 0 -.IP "\fB\-mno\-v8plus\fR" 4 -.IX Item "-mno-v8plus" +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" .PD -With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+\s0 \s-1ABI\s0. The -difference from the V8 \s-1ABI\s0 is that the global and out registers are -considered 64 bits wide. This is enabled by default on Solaris in 32\-bit -mode for all \s-1SPARC\-V9\s0 processors. -.IP "\fB\-mvis\fR" 4 -.IX Item "-mvis" +Generate code for a 32\-bit or 64\-bit environment. The 32\-bit +environment sets int, long, and pointer to 32 bits. The 64\-bit +environment sets int to 32 bits and long and pointer to 64 bits. +.IP "\fB\-mbig\-endian\fR" 4 +.IX Item "-mbig-endian" .PD 0 -.IP "\fB\-mno\-vis\fR" 4 -.IX Item "-mno-vis" +.IP "\fB\-mlittle\-endian\fR" 4 +.IX Item "-mlittle-endian" .PD -With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC -Visual Instruction Set extensions. The default is \fB\-mno\-vis\fR. -.IP "\fB\-mvis2\fR" 4 -.IX Item "-mvis2" +Generate code in big/little endian mode, respectively. +.PP +\fITILEPro Options\fR +.IX Subsection "TILEPro Options" +.PP +These \fB\-m\fR options are supported on the TILEPro: +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported +type is \fBtilepro\fR. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +Generate code for a 32\-bit environment, which sets int, long, and +pointer to 32 bits. This is the only supported behavior so the flag +is essentially ignored. +.PP +\fIV850 Options\fR +.IX Subsection "V850 Options" +.PP +These \fB\-m\fR options are defined for V850 implementations: +.IP "\fB\-mlong\-calls\fR" 4 +.IX Item "-mlong-calls" .PD 0 -.IP "\fB\-mno\-vis2\fR" 4 -.IX Item "-mno-vis2" +.IP "\fB\-mno\-long\-calls\fR" 4 +.IX Item "-mno-long-calls" .PD -With \fB\-mvis2\fR, \s-1GCC\s0 generates code that takes advantage of -version 2.0 of the UltraSPARC Visual Instruction Set extensions. The -default is \fB\-mvis2\fR when targeting a cpu that supports such -instructions, such as UltraSPARC-III and later. Setting \fB\-mvis2\fR -also sets \fB\-mvis\fR. -.IP "\fB\-mvis3\fR" 4 -.IX Item "-mvis3" +Treat all calls as being far away (near). If calls are assumed to be +far away, the compiler always loads the function's address into a +register, and calls indirect through the pointer. +.IP "\fB\-mno\-ep\fR" 4 +.IX Item "-mno-ep" .PD 0 -.IP "\fB\-mno\-vis3\fR" 4 -.IX Item "-mno-vis3" +.IP "\fB\-mep\fR" 4 +.IX Item "-mep" .PD -With \fB\-mvis3\fR, \s-1GCC\s0 generates code that takes advantage of -version 3.0 of the UltraSPARC Visual Instruction Set extensions. The -default is \fB\-mvis3\fR when targeting a cpu that supports such -instructions, such as niagara\-3 and later. Setting \fB\-mvis3\fR -also sets \fB\-mvis2\fR and \fB\-mvis\fR. -.IP "\fB\-mcbcond\fR" 4 -.IX Item "-mcbcond" +Do not optimize (do optimize) basic blocks that use the same index +pointer 4 or more times to copy pointer into the \f(CW\*(C`ep\*(C'\fR register, and +use the shorter \f(CW\*(C`sld\*(C'\fR and \f(CW\*(C`sst\*(C'\fR instructions. The \fB\-mep\fR +option is on by default if you optimize. +.IP "\fB\-mno\-prolog\-function\fR" 4 +.IX Item "-mno-prolog-function" .PD 0 -.IP "\fB\-mno\-cbcond\fR" 4 -.IX Item "-mno-cbcond" +.IP "\fB\-mprolog\-function\fR" 4 +.IX Item "-mprolog-function" .PD -With \fB\-mcbcond\fR, \s-1GCC\s0 generates code that takes advantage of -compare-and-branch instructions, as defined in the Sparc Architecture 2011. -The default is \fB\-mcbcond\fR when targeting a cpu that supports such -instructions, such as niagara\-4 and later. -.IP "\fB\-mpopc\fR" 4 -.IX Item "-mpopc" +Do not use (do use) external functions to save and restore registers +at the prologue and epilogue of a function. The external functions +are slower, but use less code space if more than one function saves +the same number of registers. The \fB\-mprolog\-function\fR option +is on by default if you optimize. +.IP "\fB\-mspace\fR" 4 +.IX Item "-mspace" +Try to make the code as small as possible. At present, this just turns +on the \fB\-mep\fR and \fB\-mprolog\-function\fR options. +.IP "\fB\-mtda=\fR\fIn\fR" 4 +.IX Item "-mtda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the tiny data area that register \f(CW\*(C`ep\*(C'\fR points to. The tiny data +area can hold up to 256 bytes in total (128 bytes for byte references). +.IP "\fB\-msda=\fR\fIn\fR" 4 +.IX Item "-msda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the small data area that register \f(CW\*(C`gp\*(C'\fR points to. The small data +area can hold up to 64 kilobytes. +.IP "\fB\-mzda=\fR\fIn\fR" 4 +.IX Item "-mzda=n" +Put static or global variables whose size is \fIn\fR bytes or less into +the first 32 kilobytes of memory. +.IP "\fB\-mv850\fR" 4 +.IX Item "-mv850" +Specify that the target processor is the V850. +.IP "\fB\-mv850e3v5\fR" 4 +.IX Item "-mv850e3v5" +Specify that the target processor is the V850E3V5. The preprocessor +constant \f(CW\*(C`_\|_v850e3v5_\|_\*(C'\fR is defined if this option is used. +.IP "\fB\-mv850e2v4\fR" 4 +.IX Item "-mv850e2v4" +Specify that the target processor is the V850E3V5. This is an alias for +the \fB\-mv850e3v5\fR option. +.IP "\fB\-mv850e2v3\fR" 4 +.IX Item "-mv850e2v3" +Specify that the target processor is the V850E2V3. The preprocessor +constant \f(CW\*(C`_\|_v850e2v3_\|_\*(C'\fR is defined if this option is used. +.IP "\fB\-mv850e2\fR" 4 +.IX Item "-mv850e2" +Specify that the target processor is the V850E2. The preprocessor +constant \f(CW\*(C`_\|_v850e2_\|_\*(C'\fR is defined if this option is used. +.IP "\fB\-mv850e1\fR" 4 +.IX Item "-mv850e1" +Specify that the target processor is the V850E1. The preprocessor +constants \f(CW\*(C`_\|_v850e1_\|_\*(C'\fR and \f(CW\*(C`_\|_v850e_\|_\*(C'\fR are defined if +this option is used. +.IP "\fB\-mv850es\fR" 4 +.IX Item "-mv850es" +Specify that the target processor is the V850ES. This is an alias for +the \fB\-mv850e1\fR option. +.IP "\fB\-mv850e\fR" 4 +.IX Item "-mv850e" +Specify that the target processor is the V850E. The preprocessor +constant \f(CW\*(C`_\|_v850e_\|_\*(C'\fR is defined if this option is used. +.Sp +If neither \fB\-mv850\fR nor \fB\-mv850e\fR nor \fB\-mv850e1\fR +nor \fB\-mv850e2\fR nor \fB\-mv850e2v3\fR nor \fB\-mv850e3v5\fR +are defined then a default target processor is chosen and the +relevant \fB_\|_v850*_\|_\fR preprocessor constant is defined. +.Sp +The preprocessor constants \f(CW\*(C`_\|_v850\*(C'\fR and \f(CW\*(C`_\|_v851_\|_\*(C'\fR are always +defined, regardless of which processor variant is the target. +.IP "\fB\-mdisable\-callt\fR" 4 +.IX Item "-mdisable-callt" .PD 0 -.IP "\fB\-mno\-popc\fR" 4 -.IX Item "-mno-popc" +.IP "\fB\-mno\-disable\-callt\fR" 4 +.IX Item "-mno-disable-callt" .PD -With \fB\-mpopc\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC -population count instruction. The default is \fB\-mpopc\fR -when targeting a cpu that supports such instructions, such as Niagara\-2 and -later. -.IP "\fB\-mfmaf\fR" 4 -.IX Item "-mfmaf" +This option suppresses generation of the \f(CW\*(C`CALLT\*(C'\fR instruction for the +v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850 +architecture. +.Sp +This option is enabled by default when the \s-1RH850 ABI\s0 is +in use (see \fB\-mrh850\-abi\fR), and disabled by default when the +\&\s-1GCC ABI\s0 is in use. If \f(CW\*(C`CALLT\*(C'\fR instructions are being generated +then the C preprocessor symbol \f(CW\*(C`_\|_V850_CALLT_\|_\*(C'\fR is defined. +.IP "\fB\-mrelax\fR" 4 +.IX Item "-mrelax" .PD 0 -.IP "\fB\-mno\-fmaf\fR" 4 -.IX Item "-mno-fmaf" +.IP "\fB\-mno\-relax\fR" 4 +.IX Item "-mno-relax" .PD -With \fB\-mfmaf\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC -Fused Multiply-Add Floating-point extensions. The default is \fB\-mfmaf\fR -when targeting a cpu that supports such instructions, such as Niagara\-3 and -later. -.IP "\fB\-mfix\-at697f\fR" 4 -.IX Item "-mfix-at697f" -Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 -processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). -.IP "\fB\-mfix\-ut699\fR" 4 -.IX Item "-mfix-ut699" -Enable the documented workarounds for the floating-point errata and the data -cache nullify errata of the \s-1UT699\s0 processor. -.PP -These \fB\-m\fR options are supported in addition to the above -on \s-1SPARC\-V9\s0 processors in 64\-bit environments: -.IP "\fB\-m32\fR" 4 -.IX Item "-m32" +Pass on (or do not pass on) the \fB\-mrelax\fR command-line option +to the assembler. +.IP "\fB\-mlong\-jumps\fR" 4 +.IX Item "-mlong-jumps" .PD 0 -.IP "\fB\-m64\fR" 4 -.IX Item "-m64" +.IP "\fB\-mno\-long\-jumps\fR" 4 +.IX Item "-mno-long-jumps" +.PD +Disable (or re-enable) the generation of PC-relative jump instructions. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Disable (or re-enable) the generation of hardware floating point +instructions. This option is only significant when the target +architecture is \fBV850E2V3\fR or higher. If hardware floating point +instructions are being generated then the C preprocessor symbol +\&\f(CW\*(C`_\|_FPU_OK_\|_\*(C'\fR is defined, otherwise the symbol +\&\f(CW\*(C`_\|_NO_FPU_\|_\*(C'\fR is defined. +.IP "\fB\-mloop\fR" 4 +.IX Item "-mloop" +Enables the use of the e3v5 \s-1LOOP\s0 instruction. The use of this +instruction is not enabled by default when the e3v5 architecture is +selected because its use is still experimental. +.IP "\fB\-mrh850\-abi\fR" 4 +.IX Item "-mrh850-abi" +.PD 0 +.IP "\fB\-mghs\fR" 4 +.IX Item "-mghs" .PD -Generate code for a 32\-bit or 64\-bit environment. -The 32\-bit environment sets int, long and pointer to 32 bits. -The 64\-bit environment sets int to 32 bits and long and pointer -to 64 bits. -.IP "\fB\-mcmodel=\fR\fIwhich\fR" 4 -.IX Item "-mcmodel=which" -Set the code model to one of +Enables support for the \s-1RH850\s0 version of the V850 \s-1ABI. \s0 This is the +default. With this version of the \s-1ABI\s0 the following rules apply: .RS 4 -.IP "\fBmedlow\fR" 4 -.IX Item "medlow" -The Medium/Low code model: 64\-bit addresses, programs -must be linked in the low 32 bits of memory. Programs can be statically -or dynamically linked. -.IP "\fBmedmid\fR" 4 -.IX Item "medmid" -The Medium/Middle code model: 64\-bit addresses, programs -must be linked in the low 44 bits of memory, the text and data segments must -be less than 2GB in size and the data segment must be located within 2GB of -the text segment. -.IP "\fBmedany\fR" 4 -.IX Item "medany" -The Medium/Anywhere code model: 64\-bit addresses, programs -may be linked anywhere in memory, the text and data segments must be less -than 2GB in size and the data segment must be located within 2GB of the -text segment. -.IP "\fBembmedany\fR" 4 -.IX Item "embmedany" -The Medium/Anywhere code model for embedded systems: -64\-bit addresses, the text and data segments must be less than 2GB in -size, both starting anywhere in memory (determined at link time). The -global register \f(CW%g4\fR points to the base of the data segment. Programs -are statically linked and \s-1PIC\s0 is not supported. +.IP "*" 4 +Integer sized structures and unions are returned via a memory pointer +rather than a register. +.IP "*" 4 +Large structures and unions (more than 8 bytes in size) are passed by +value. +.IP "*" 4 +Functions are aligned to 16\-bit boundaries. +.IP "*" 4 +The \fB\-m8byte\-align\fR command-line option is supported. +.IP "*" 4 +The \fB\-mdisable\-callt\fR command-line option is enabled by +default. The \fB\-mno\-disable\-callt\fR command-line option is not +supported. .RE .RS 4 +.Sp +When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol +\&\f(CW\*(C`_\|_V850_RH850_ABI_\|_\*(C'\fR is defined. .RE -.IP "\fB\-mmemory\-model=\fR\fImem-model\fR" 4 -.IX Item "-mmemory-model=mem-model" -Set the memory model in force on the processor to one of +.IP "\fB\-mgcc\-abi\fR" 4 +.IX Item "-mgcc-abi" +Enables support for the old \s-1GCC\s0 version of the V850 \s-1ABI. \s0 With this +version of the \s-1ABI\s0 the following rules apply: .RS 4 -.IP "\fBdefault\fR" 4 -.IX Item "default" -The default memory model for the processor and operating system. -.IP "\fBrmo\fR" 4 -.IX Item "rmo" -Relaxed Memory Order -.IP "\fBpso\fR" 4 -.IX Item "pso" -Partial Store Order -.IP "\fBtso\fR" 4 -.IX Item "tso" -Total Store Order -.IP "\fBsc\fR" 4 -.IX Item "sc" -Sequential Consistency +.IP "*" 4 +Integer sized structures and unions are returned in register \f(CW\*(C`r10\*(C'\fR. +.IP "*" 4 +Large structures and unions (more than 8 bytes in size) are passed by +reference. +.IP "*" 4 +Functions are aligned to 32\-bit boundaries, unless optimizing for +size. +.IP "*" 4 +The \fB\-m8byte\-align\fR command-line option is not supported. +.IP "*" 4 +The \fB\-mdisable\-callt\fR command-line option is supported but not +enabled by default. .RE .RS 4 .Sp -These memory models are formally defined in Appendix D of the Sparc V9 -architecture manual, as set in the processor's \f(CW\*(C`PSTATE.MM\*(C'\fR field. +When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol +\&\f(CW\*(C`_\|_V850_GCC_ABI_\|_\*(C'\fR is defined. .RE -.IP "\fB\-mstack\-bias\fR" 4 -.IX Item "-mstack-bias" +.IP "\fB\-m8byte\-align\fR" 4 +.IX Item "-m8byte-align" +.PD 0 +.IP "\fB\-mno\-8byte\-align\fR" 4 +.IX Item "-mno-8byte-align" +.PD +Enables support for \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long long\*(C'\fR types to be +aligned on 8\-byte boundaries. The default is to restrict the +alignment of all objects to at most 4\-bytes. When +\&\fB\-m8byte\-align\fR is in effect the C preprocessor symbol +\&\f(CW\*(C`_\|_V850_8BYTE_ALIGN_\|_\*(C'\fR is defined. +.IP "\fB\-mbig\-switch\fR" 4 +.IX Item "-mbig-switch" +Generate code suitable for big switch tables. Use this option only if +the assembler/linker complain about out of range branches within a switch +table. +.IP "\fB\-mapp\-regs\fR" 4 +.IX Item "-mapp-regs" +This option causes r2 and r5 to be used in the code generated by +the compiler. This setting is the default. +.IP "\fB\-mno\-app\-regs\fR" 4 +.IX Item "-mno-app-regs" +This option causes r2 and r5 to be treated as fixed registers. +.PP +\fI\s-1VAX\s0 Options\fR +.IX Subsection "VAX Options" +.PP +These \fB\-m\fR options are defined for the \s-1VAX:\s0 +.IP "\fB\-munix\fR" 4 +.IX Item "-munix" +Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on) +that the Unix assembler for the \s-1VAX\s0 cannot handle across long +ranges. +.IP "\fB\-mgnu\fR" 4 +.IX Item "-mgnu" +Do output those jump instructions, on the assumption that the +\&\s-1GNU\s0 assembler is being used. +.IP "\fB\-mg\fR" 4 +.IX Item "-mg" +Output code for G\-format floating-point numbers instead of D\-format. +.PP +\fIVisium Options\fR +.IX Subsection "Visium Options" +.IP "\fB\-mdebug\fR" 4 +.IX Item "-mdebug" +A program which performs file I/O and is destined to run on an \s-1MCM\s0 target +should be linked with this option. It causes the libraries libc.a and +libdebug.a to be linked. The program should be run on the target under +the control of the \s-1GDB\s0 remote debugging stub. +.IP "\fB\-msim\fR" 4 +.IX Item "-msim" +A program which performs file I/O and is destined to run on the simulator +should be linked with option. This causes libraries libc.a and libsim.a to +be linked. +.IP "\fB\-mfpu\fR" 4 +.IX Item "-mfpu" +.PD 0 +.IP "\fB\-mhard\-float\fR" 4 +.IX Item "-mhard-float" +.PD +Generate code containing floating-point instructions. This is the +default. +.IP "\fB\-mno\-fpu\fR" 4 +.IX Item "-mno-fpu" +.PD 0 +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +.PD +Generate code containing library calls for floating-point. +.Sp +\&\fB\-msoft\-float\fR changes the calling convention in the output file; +therefore, it is only useful if you compile \fIall\fR of a program with +this option. In particular, you need to compile \fIlibgcc.a\fR, the +library that comes with \s-1GCC,\s0 with \fB\-msoft\-float\fR in order for +this to work. +.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 +.IX Item "-mcpu=cpu_type" +Set the instruction set, register set, and instruction scheduling parameters +for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are +\&\fBmcm\fR, \fBgr5\fR and \fBgr6\fR. +.Sp +\&\fBmcm\fR is a synonym of \fBgr5\fR present for backward compatibility. +.Sp +By default (unless configured otherwise), \s-1GCC\s0 generates code for the \s-1GR5\s0 +variant of the Visium architecture. +.Sp +With \fB\-mcpu=gr6\fR, \s-1GCC\s0 generates code for the \s-1GR6\s0 variant of the Visium +architecture. The only difference from \s-1GR5\s0 code is that the compiler will +generate block move instructions. +.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 +.IX Item "-mtune=cpu_type" +Set the instruction scheduling parameters for machine type \fIcpu_type\fR, +but do not set the instruction set or register set that the option +\&\fB\-mcpu=\fR\fIcpu_type\fR would. +.IP "\fB\-msv\-mode\fR" 4 +.IX Item "-msv-mode" +Generate code for the supervisor mode, where there are no restrictions on +the access to general registers. This is the default. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +Generate code for the user mode, where the access to some general registers +is forbidden: on the \s-1GR5,\s0 registers r24 to r31 cannot be accessed in this +mode; on the \s-1GR6,\s0 only registers r29 to r31 are affected. +.PP +\fI\s-1VMS\s0 Options\fR +.IX Subsection "VMS Options" +.PP +These \fB\-m\fR options are defined for the \s-1VMS\s0 implementations: +.IP "\fB\-mvms\-return\-codes\fR" 4 +.IX Item "-mvms-return-codes" +Return \s-1VMS\s0 condition codes from \f(CW\*(C`main\*(C'\fR. The default is to return POSIX-style +condition (e.g. error) codes. +.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 +.IX Item "-mdebug-main=prefix" +Flag the first routine whose name starts with \fIprefix\fR as the main +routine for the debugger. +.IP "\fB\-mmalloc64\fR" 4 +.IX Item "-mmalloc64" +Default to 64\-bit memory allocation routines. +.IP "\fB\-mpointer\-size=\fR\fIsize\fR" 4 +.IX Item "-mpointer-size=size" +Set the default size of pointers. Possible options for \fIsize\fR are +\&\fB32\fR or \fBshort\fR for 32 bit pointers, \fB64\fR or \fBlong\fR +for 64 bit pointers, and \fBno\fR for supporting only 32 bit pointers. +The later option disables \f(CW\*(C`pragma pointer_size\*(C'\fR. +.PP +\fIVxWorks Options\fR +.IX Subsection "VxWorks Options" +.PP +The options in this section are defined for all VxWorks targets. +Options specific to the target hardware are listed with the other +options for that target. +.IP "\fB\-mrtp\fR" 4 +.IX Item "-mrtp" +\&\s-1GCC\s0 can generate code for both VxWorks kernels and real time processes +(RTPs). This option switches from the former to the latter. It also +defines the preprocessor macro \f(CW\*(C`_\|_RTP_\|_\*(C'\fR. +.IP "\fB\-non\-static\fR" 4 +.IX Item "-non-static" +Link an \s-1RTP\s0 executable against shared libraries rather than static +libraries. The options \fB\-static\fR and \fB\-shared\fR can +also be used for RTPs; \fB\-static\fR +is the default. +.IP "\fB\-Bstatic\fR" 4 +.IX Item "-Bstatic" +.PD 0 +.IP "\fB\-Bdynamic\fR" 4 +.IX Item "-Bdynamic" +.PD +These options are passed down to the linker. They are defined for +compatibility with Diab. +.IP "\fB\-Xbind\-lazy\fR" 4 +.IX Item "-Xbind-lazy" +Enable lazy binding of function calls. This option is equivalent to +\&\fB\-Wl,\-z,now\fR and is defined for compatibility with Diab. +.IP "\fB\-Xbind\-now\fR" 4 +.IX Item "-Xbind-now" +Disable lazy binding of function calls. This option is the default and +is defined for compatibility with Diab. +.PP +\fIx86 Options\fR +.IX Subsection "x86 Options" +.PP +These \fB\-m\fR options are defined for the x86 family of computers. +.IP "\fB\-march=\fR\fIcpu-type\fR" 4 +.IX Item "-march=cpu-type" +Generate instructions for the machine type \fIcpu-type\fR. In contrast to +\&\fB\-mtune=\fR\fIcpu-type\fR, which merely tunes the generated code +for the specified \fIcpu-type\fR, \fB\-march=\fR\fIcpu-type\fR allows \s-1GCC\s0 +to generate code that may not run at all on processors other than the one +indicated. Specifying \fB\-march=\fR\fIcpu-type\fR implies +\&\fB\-mtune=\fR\fIcpu-type\fR. +.Sp +The choices for \fIcpu-type\fR are: +.RS 4 +.IP "\fBnative\fR" 4 +.IX Item "native" +This selects the \s-1CPU\s0 to generate code for at compilation time by determining +the processor type of the compiling machine. Using \fB\-march=native\fR +enables all instruction subsets supported by the local machine (hence +the result might not run on different machines). Using \fB\-mtune=native\fR +produces code optimized for the local machine under the constraints +of the selected instruction set. +.IP "\fBi386\fR" 4 +.IX Item "i386" +Original Intel i386 \s-1CPU.\s0 +.IP "\fBi486\fR" 4 +.IX Item "i486" +Intel i486 \s-1CPU. \s0(No scheduling is implemented for this chip.) +.IP "\fBi586\fR" 4 +.IX Item "i586" .PD 0 -.IP "\fB\-mno\-stack\-bias\fR" 4 -.IX Item "-mno-stack-bias" +.IP "\fBpentium\fR" 4 +.IX Item "pentium" .PD -With \fB\-mstack\-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and -frame pointer if present, are offset by \-2047 which must be added back -when making stack frame references. This is the default in 64\-bit mode. -Otherwise, assume no such offset is present. -.PP -\fI\s-1SPU\s0 Options\fR -.IX Subsection "SPU Options" -.PP -These \fB\-m\fR options are supported on the \s-1SPU:\s0 -.IP "\fB\-mwarn\-reloc\fR" 4 -.IX Item "-mwarn-reloc" +Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support. +.IP "\fBpentium-mmx\fR" 4 +.IX Item "pentium-mmx" +Intel Pentium \s-1MMX CPU,\s0 based on Pentium core with \s-1MMX\s0 instruction set support. +.IP "\fBpentiumpro\fR" 4 +.IX Item "pentiumpro" +Intel Pentium Pro \s-1CPU.\s0 +.IP "\fBi686\fR" 4 +.IX Item "i686" +When used with \fB\-march\fR, the Pentium Pro +instruction set is used, so the code runs on all i686 family chips. +When used with \fB\-mtune\fR, it has the same meaning as \fBgeneric\fR. +.IP "\fBpentium2\fR" 4 +.IX Item "pentium2" +Intel Pentium \s-1II CPU,\s0 based on Pentium Pro core with \s-1MMX\s0 instruction set +support. +.IP "\fBpentium3\fR" 4 +.IX Item "pentium3" .PD 0 -.IP "\fB\-merror\-reloc\fR" 4 -.IX Item "-merror-reloc" +.IP "\fBpentium3m\fR" 4 +.IX Item "pentium3m" .PD -The loader for \s-1SPU\s0 does not handle dynamic relocations. By default, \s-1GCC\s0 -gives an error when it generates code that requires a dynamic -relocation. \fB\-mno\-error\-reloc\fR disables the error, -\&\fB\-mwarn\-reloc\fR generates a warning instead. -.IP "\fB\-msafe\-dma\fR" 4 -.IX Item "-msafe-dma" +Intel Pentium \s-1III CPU,\s0 based on Pentium Pro core with \s-1MMX\s0 and \s-1SSE\s0 instruction +set support. +.IP "\fBpentium-m\fR" 4 +.IX Item "pentium-m" +Intel Pentium M; low-power version of Intel Pentium \s-1III CPU\s0 +with \s-1MMX, SSE\s0 and \s-1SSE2\s0 instruction set support. Used by Centrino notebooks. +.IP "\fBpentium4\fR" 4 +.IX Item "pentium4" .PD 0 -.IP "\fB\-munsafe\-dma\fR" 4 -.IX Item "-munsafe-dma" +.IP "\fBpentium4m\fR" 4 +.IX Item "pentium4m" .PD -Instructions that initiate or test completion of \s-1DMA\s0 must not be -reordered with respect to loads and stores of the memory that is being -accessed. -With \fB\-munsafe\-dma\fR you must use the \f(CW\*(C`volatile\*(C'\fR keyword to protect -memory accesses, but that can lead to inefficient code in places where the -memory is known to not change. Rather than mark the memory as volatile, -you can use \fB\-msafe\-dma\fR to tell the compiler to treat -the \s-1DMA\s0 instructions as potentially affecting all memory. -.IP "\fB\-mbranch\-hints\fR" 4 -.IX Item "-mbranch-hints" -By default, \s-1GCC\s0 generates a branch hint instruction to avoid -pipeline stalls for always-taken or probably-taken branches. A hint -is not generated closer than 8 instructions away from its branch. -There is little reason to disable them, except for debugging purposes, -or to make an object a little bit smaller. -.IP "\fB\-msmall\-mem\fR" 4 -.IX Item "-msmall-mem" +Intel Pentium 4 \s-1CPU\s0 with \s-1MMX, SSE\s0 and \s-1SSE2\s0 instruction set support. +.IP "\fBprescott\fR" 4 +.IX Item "prescott" +Improved version of Intel Pentium 4 \s-1CPU\s0 with \s-1MMX, SSE, SSE2\s0 and \s-1SSE3\s0 instruction +set support. +.IP "\fBnocona\fR" 4 +.IX Item "nocona" +Improved version of Intel Pentium 4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, +SSE2\s0 and \s-1SSE3\s0 instruction set support. +.IP "\fBcore2\fR" 4 +.IX Item "core2" +Intel Core 2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fBnehalem\fR" 4 +.IX Item "nehalem" +Intel Nehalem \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2\s0 and \s-1POPCNT\s0 instruction set support. +.IP "\fBwestmere\fR" 4 +.IX Item "westmere" +Intel Westmere \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES\s0 and \s-1PCLMUL\s0 instruction set support. +.IP "\fBsandybridge\fR" 4 +.IX Item "sandybridge" +Intel Sandy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AES\s0 and \s-1PCLMUL\s0 instruction set support. +.IP "\fBivybridge\fR" 4 +.IX Item "ivybridge" +Intel Ivy Bridge \s-1CPU\s0 with 64\-bit extensions, \s-1MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND\s0 and F16C +instruction set support. +.IP "\fBhaswell\fR" 4 +.IX Item "haswell" +Intel Haswell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2\s0 and F16C instruction set support. +.IP "\fBbroadwell\fR" 4 +.IX Item "broadwell" +Intel Broadwell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX\s0 and \s-1PREFETCHW\s0 instruction set support. +.IP "\fBbonnell\fR" 4 +.IX Item "bonnell" +Intel Bonnell \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3\s0 and \s-1SSSE3\s0 +instruction set support. +.IP "\fBsilvermont\fR" 4 +.IX Item "silvermont" +Intel Silvermont \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, POPCNT, AES, PCLMUL\s0 and \s-1RDRND\s0 instruction set support. +.IP "\fBknl\fR" 4 +.IX Item "knl" +Intel Knight's Landing \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE, MMX, SSE, SSE2, SSE3, +SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, +BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER\s0 and +\&\s-1AVX512CD\s0 instruction set support. +.IP "\fBk6\fR" 4 +.IX Item "k6" +\&\s-1AMD K6 CPU\s0 with \s-1MMX\s0 instruction set support. +.IP "\fBk6\-2\fR" 4 +.IX Item "k6-2" .PD 0 -.IP "\fB\-mlarge\-mem\fR" 4 -.IX Item "-mlarge-mem" +.IP "\fBk6\-3\fR" 4 +.IX Item "k6-3" .PD -By default, \s-1GCC\s0 generates code assuming that addresses are never larger -than 18 bits. With \fB\-mlarge\-mem\fR code is generated that assumes -a full 32\-bit address. -.IP "\fB\-mstdmain\fR" 4 -.IX Item "-mstdmain" -By default, \s-1GCC\s0 links against startup code that assumes the SPU-style -main function interface (which has an unconventional parameter list). -With \fB\-mstdmain\fR, \s-1GCC\s0 links your program against startup -code that assumes a C99\-style interface to \f(CW\*(C`main\*(C'\fR, including a -local copy of \f(CW\*(C`argv\*(C'\fR strings. -.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 -.IX Item "-mfixed-range=register-range" -Generate code treating the given register range as fixed registers. -A fixed register is one that the register allocator cannot use. This is -useful when compiling kernel code. A register range is specified as -two registers separated by a dash. Multiple register ranges can be -specified separated by a comma. -.IP "\fB\-mea32\fR" 4 -.IX Item "-mea32" +Improved versions of \s-1AMD K6 CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. +.IP "\fBathlon\fR" 4 +.IX Item "athlon" .PD 0 -.IP "\fB\-mea64\fR" 4 -.IX Item "-mea64" +.IP "\fBathlon-tbird\fR" 4 +.IX Item "athlon-tbird" .PD -Compile code assuming that pointers to the \s-1PPU\s0 address space accessed -via the \f(CW\*(C`_\|_ea\*(C'\fR named address space qualifier are either 32 or 64 -bits wide. The default is 32 bits. As this is an ABI-changing option, -all object code in an executable must be compiled with the same setting. -.IP "\fB\-maddress\-space\-conversion\fR" 4 -.IX Item "-maddress-space-conversion" +\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX,\s0 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions +support. +.IP "\fBathlon\-4\fR" 4 +.IX Item "athlon-4" .PD 0 -.IP "\fB\-mno\-address\-space\-conversion\fR" 4 -.IX Item "-mno-address-space-conversion" +.IP "\fBathlon-xp\fR" 4 +.IX Item "athlon-xp" +.IP "\fBathlon-mp\fR" 4 +.IX Item "athlon-mp" .PD -Allow/disallow treating the \f(CW\*(C`_\|_ea\*(C'\fR address space as superset -of the generic address space. This enables explicit type casts -between \f(CW\*(C`_\|_ea\*(C'\fR and generic pointer as well as implicit -conversions of generic pointers to \f(CW\*(C`_\|_ea\*(C'\fR pointers. The -default is to allow address space pointer conversions. -.IP "\fB\-mcache\-size=\fR\fIcache-size\fR" 4 -.IX Item "-mcache-size=cache-size" -This option controls the version of libgcc that the compiler links to an -executable and selects a software-managed cache for accessing variables -in the \f(CW\*(C`_\|_ea\*(C'\fR address space with a particular cache size. Possible -options for \fIcache-size\fR are \fB8\fR, \fB16\fR, \fB32\fR, \fB64\fR -and \fB128\fR. The default cache size is 64KB. -.IP "\fB\-matomic\-updates\fR" 4 -.IX Item "-matomic-updates" +Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX,\s0 3DNow!, enhanced 3DNow! and full \s-1SSE\s0 +instruction set support. +.IP "\fBk8\fR" 4 +.IX Item "k8" +.PD 0 +.IP "\fBopteron\fR" 4 +.IX Item "opteron" +.IP "\fBathlon64\fR" 4 +.IX Item "athlon64" +.IP "\fBathlon-fx\fR" 4 +.IX Item "athlon-fx" +.PD +Processors based on the \s-1AMD K8\s0 core with x86\-64 instruction set support, +including the \s-1AMD\s0 Opteron, Athlon 64, and Athlon 64 \s-1FX\s0 processors. +(This supersets \s-1MMX, SSE, SSE2,\s0 3DNow!, enhanced 3DNow! and 64\-bit +instruction set extensions.) +.IP "\fBk8\-sse3\fR" 4 +.IX Item "k8-sse3" +.PD 0 +.IP "\fBopteron\-sse3\fR" 4 +.IX Item "opteron-sse3" +.IP "\fBathlon64\-sse3\fR" 4 +.IX Item "athlon64-sse3" +.PD +Improved versions of \s-1AMD K8\s0 cores with \s-1SSE3\s0 instruction set support. +.IP "\fBamdfam10\fR" 4 +.IX Item "amdfam10" +.PD 0 +.IP "\fBbarcelona\fR" 4 +.IX Item "barcelona" +.PD +CPUs based on \s-1AMD\s0 Family 10h cores with x86\-64 instruction set support. (This +supersets \s-1MMX, SSE, SSE2, SSE3, SSE4A,\s0 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit +instruction set extensions.) +.IP "\fBbdver1\fR" 4 +.IX Item "bdver1" +CPUs based on \s-1AMD\s0 Family 15h cores with x86\-64 instruction set support. (This +supersets \s-1FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, +SSSE3, SSE4.1, SSE4.2, ABM\s0 and 64\-bit instruction set extensions.) +.IP "\fBbdver2\fR" 4 +.IX Item "bdver2" +\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, +SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM\s0 and 64\-bit instruction set +extensions.) +.IP "\fBbdver3\fR" 4 +.IX Item "bdver3" +\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES, +PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM\s0 and +64\-bit instruction set extensions. +.IP "\fBbdver4\fR" 4 +.IX Item "bdver4" +\&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This +supersets \s-1BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP, +AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, +SSE4.2, ABM\s0 and 64\-bit instruction set extensions. +.IP "\fBbtver1\fR" 4 +.IX Item "btver1" +CPUs based on \s-1AMD\s0 Family 14h cores with x86\-64 instruction set support. (This +supersets \s-1MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM\s0 and 64\-bit +instruction set extensions.) +.IP "\fBbtver2\fR" 4 +.IX Item "btver2" +CPUs based on \s-1AMD\s0 Family 16h cores with x86\-64 instruction set support. This +includes \s-1MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM, +SSE4A, SSSE3, SSE3, SSE2, SSE, MMX\s0 and 64\-bit instruction set extensions. +.IP "\fBwinchip\-c6\fR" 4 +.IX Item "winchip-c6" +\&\s-1IDT\s0 WinChip C6 \s-1CPU,\s0 dealt in same way as i486 with additional \s-1MMX\s0 instruction +set support. +.IP "\fBwinchip2\fR" 4 +.IX Item "winchip2" +\&\s-1IDT\s0 WinChip 2 \s-1CPU,\s0 dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow! +instruction set support. +.IP "\fBc3\fR" 4 +.IX Item "c3" +\&\s-1VIA C3 CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. (No scheduling is +implemented for this chip.) +.IP "\fBc3\-2\fR" 4 +.IX Item "c3-2" +\&\s-1VIA C3\-2 \s0(Nehemiah/C5XL) \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. +(No scheduling is +implemented for this chip.) +.IP "\fBgeode\fR" 4 +.IX Item "geode" +\&\s-1AMD\s0 Geode embedded processor with \s-1MMX\s0 and 3DNow! instruction set support. +.RE +.RS 4 +.RE +.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 +.IX Item "-mtune=cpu-type" +Tune to \fIcpu-type\fR everything applicable about the generated code, except +for the \s-1ABI\s0 and the set of available instructions. +While picking a specific \fIcpu-type\fR schedules things appropriately +for that particular chip, the compiler does not generate any code that +cannot run on the default machine type unless you use a +\&\fB\-march=\fR\fIcpu-type\fR option. +For example, if \s-1GCC\s0 is configured for i686\-pc\-linux\-gnu +then \fB\-mtune=pentium4\fR generates code that is tuned for Pentium 4 +but still runs on i686 machines. +.Sp +The choices for \fIcpu-type\fR are the same as for \fB\-march\fR. +In addition, \fB\-mtune\fR supports 2 extra choices for \fIcpu-type\fR: +.RS 4 +.IP "\fBgeneric\fR" 4 +.IX Item "generic" +Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors. +If you know the \s-1CPU\s0 on which your code will run, then you should use +the corresponding \fB\-mtune\fR or \fB\-march\fR option instead of +\&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users +of your application will have, then you should use this option. +.Sp +As new processors are deployed in the marketplace, the behavior of this +option will change. Therefore, if you upgrade to a newer version of +\&\s-1GCC,\s0 code generation controlled by this option will change to reflect +the processors +that are most common at the time that version of \s-1GCC\s0 is released. +.Sp +There is no \fB\-march=generic\fR option because \fB\-march\fR +indicates the instruction set the compiler can use, and there is no +generic instruction set applicable to all processors. In contrast, +\&\fB\-mtune\fR indicates the processor (or, in this case, collection of +processors) for which the code is optimized. +.IP "\fBintel\fR" 4 +.IX Item "intel" +Produce code optimized for the most current Intel processors, which are +Haswell and Silvermont for this version of \s-1GCC. \s0 If you know the \s-1CPU\s0 +on which your code will run, then you should use the corresponding +\&\fB\-mtune\fR or \fB\-march\fR option instead of \fB\-mtune=intel\fR. +But, if you want your application performs better on both Haswell and +Silvermont, then you should use this option. +.Sp +As new Intel processors are deployed in the marketplace, the behavior of +this option will change. Therefore, if you upgrade to a newer version of +\&\s-1GCC,\s0 code generation controlled by this option will change to reflect +the most current Intel processors at the time that version of \s-1GCC\s0 is +released. +.Sp +There is no \fB\-march=intel\fR option because \fB\-march\fR indicates +the instruction set the compiler can use, and there is no common +instruction set applicable to all processors. In contrast, +\&\fB\-mtune\fR indicates the processor (or, in this case, collection of +processors) for which the code is optimized. +.RE +.RS 4 +.RE +.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 +.IX Item "-mcpu=cpu-type" +A deprecated synonym for \fB\-mtune\fR. +.IP "\fB\-mfpmath=\fR\fIunit\fR" 4 +.IX Item "-mfpmath=unit" +Generate floating-point arithmetic for selected unit \fIunit\fR. The choices +for \fIunit\fR are: +.RS 4 +.IP "\fB387\fR" 4 +.IX Item "387" +Use the standard 387 floating-point coprocessor present on the majority of chips and +emulated otherwise. Code compiled with this option runs almost everywhere. +The temporary results are computed in 80\-bit precision instead of the precision +specified by the type, resulting in slightly different results compared to most +of other chips. See \fB\-ffloat\-store\fR for more detailed description. +.Sp +This is the default choice for x86\-32 targets. +.IP "\fBsse\fR" 4 +.IX Item "sse" +Use scalar floating-point instructions present in the \s-1SSE\s0 instruction set. +This instruction set is supported by Pentium \s-1III\s0 and newer chips, +and in the \s-1AMD\s0 line +by Athlon\-4, Athlon \s-1XP\s0 and Athlon \s-1MP\s0 chips. The earlier version of the \s-1SSE\s0 +instruction set supports only single-precision arithmetic, thus the double and +extended-precision arithmetic are still done using 387. A later version, present +only in Pentium 4 and \s-1AMD\s0 x86\-64 chips, supports double-precision +arithmetic too. +.Sp +For the x86\-32 compiler, you must use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR +or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option +effective. For the x86\-64 compiler, these extensions are enabled by default. +.Sp +The resulting code should be considerably faster in the majority of cases and avoid +the numerical instability problems of 387 code, but may break some existing +code that expects temporaries to be 80 bits. +.Sp +This is the default choice for the x86\-64 compiler. +.IP "\fBsse,387\fR" 4 +.IX Item "sse,387" .PD 0 -.IP "\fB\-mno\-atomic\-updates\fR" 4 -.IX Item "-mno-atomic-updates" +.IP "\fBsse+387\fR" 4 +.IX Item "sse+387" +.IP "\fBboth\fR" 4 +.IX Item "both" .PD -This option controls the version of libgcc that the compiler links to an -executable and selects whether atomic updates to the software-managed -cache of PPU-side variables are used. If you use atomic updates, changes -to a \s-1PPU\s0 variable from \s-1SPU\s0 code using the \f(CW\*(C`_\|_ea\*(C'\fR named address space -qualifier do not interfere with changes to other \s-1PPU\s0 variables residing -in the same cache line from \s-1PPU\s0 code. If you do not use atomic updates, -such interference may occur; however, writing back cache lines is -more efficient. The default behavior is to use atomic updates. -.IP "\fB\-mdual\-nops\fR" 4 -.IX Item "-mdual-nops" +Attempt to utilize both instruction sets at once. This effectively doubles the +amount of available registers, and on chips with separate execution units for +387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is +still experimental, because the \s-1GCC\s0 register allocator does not model separate +functional units well, resulting in unstable performance. +.RE +.RS 4 +.RE +.IP "\fB\-masm=\fR\fIdialect\fR" 4 +.IX Item "-masm=dialect" +Output assembly instructions using selected \fIdialect\fR. Also affects +which dialect is used for basic \f(CW\*(C`asm\*(C'\fR and +extended \f(CW\*(C`asm\*(C'\fR. Supported choices (in dialect +order) are \fBatt\fR or \fBintel\fR. The default is \fBatt\fR. Darwin does +not support \fBintel\fR. +.IP "\fB\-mieee\-fp\fR" 4 +.IX Item "-mieee-fp" .PD 0 -.IP "\fB\-mdual\-nops=\fR\fIn\fR" 4 -.IX Item "-mdual-nops=n" +.IP "\fB\-mno\-ieee\-fp\fR" 4 +.IX Item "-mno-ieee-fp" .PD -By default, \s-1GCC\s0 inserts nops to increase dual issue when it expects -it to increase performance. \fIn\fR can be a value from 0 to 10. A -smaller \fIn\fR inserts fewer nops. 10 is the default, 0 is the -same as \fB\-mno\-dual\-nops\fR. Disabled with \fB\-Os\fR. -.IP "\fB\-mhint\-max\-nops=\fR\fIn\fR" 4 -.IX Item "-mhint-max-nops=n" -Maximum number of nops to insert for a branch hint. A branch hint must -be at least 8 instructions away from the branch it is affecting. \s-1GCC\s0 -inserts up to \fIn\fR nops to enforce this, otherwise it does not -generate the branch hint. -.IP "\fB\-mhint\-max\-distance=\fR\fIn\fR" 4 -.IX Item "-mhint-max-distance=n" -The encoding of the branch hint instruction limits the hint to be within -256 instructions of the branch it is affecting. By default, \s-1GCC\s0 makes -sure it is within 125. -.IP "\fB\-msafe\-hints\fR" 4 -.IX Item "-msafe-hints" -Work around a hardware bug that causes the \s-1SPU\s0 to stall indefinitely. -By default, \s-1GCC\s0 inserts the \f(CW\*(C`hbrp\*(C'\fR instruction to make sure -this stall won't happen. -.PP -\fIOptions for System V\fR -.IX Subsection "Options for System V" -.PP -These additional options are available on System V Release 4 for -compatibility with other compilers on those systems: -.IP "\fB\-G\fR" 4 -.IX Item "-G" -Create a shared object. -It is recommended that \fB\-symbolic\fR or \fB\-shared\fR be used instead. -.IP "\fB\-Qy\fR" 4 -.IX Item "-Qy" -Identify the versions of each tool used by the compiler, in a -\&\f(CW\*(C`.ident\*(C'\fR assembler directive in the output. -.IP "\fB\-Qn\fR" 4 -.IX Item "-Qn" -Refrain from adding \f(CW\*(C`.ident\*(C'\fR directives to the output file (this is -the default). -.IP "\fB\-YP,\fR\fIdirs\fR" 4 -.IX Item "-YP,dirs" -Search the directories \fIdirs\fR, and no others, for libraries -specified with \fB\-l\fR. -.IP "\fB\-Ym,\fR\fIdir\fR" 4 -.IX Item "-Ym,dir" -Look in the directory \fIdir\fR to find the M4 preprocessor. -The assembler uses this option. -.PP -\fITILE-Gx Options\fR -.IX Subsection "TILE-Gx Options" -.PP -These \fB\-m\fR options are supported on the TILE-Gx: -.IP "\fB\-mcmodel=small\fR" 4 -.IX Item "-mcmodel=small" -Generate code for the small model. The distance for direct calls is -limited to 500M in either direction. PC-relative addresses are 32 -bits. Absolute addresses support the full address range. -.IP "\fB\-mcmodel=large\fR" 4 -.IX Item "-mcmodel=large" -Generate code for the large model. There is no limitation on call -distance, pc-relative addresses, or absolute addresses. -.IP "\fB\-mcpu=\fR\fIname\fR" 4 -.IX Item "-mcpu=name" -Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported -type is \fBtilegx\fR. -.IP "\fB\-m32\fR" 4 -.IX Item "-m32" +Control whether or not the compiler uses \s-1IEEE\s0 floating-point +comparisons. These correctly handle the case where the result of a +comparison is unordered. +.IP "\fB\-msoft\-float\fR" 4 +.IX Item "-msoft-float" +Generate output containing library calls for floating point. +.Sp +\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC.\s0 +Normally the facilities of the machine's usual C compiler are used, but +this can't be done directly in cross-compilation. You must make your +own arrangements to provide suitable library functions for +cross-compilation. +.Sp +On machines where a function returns floating-point results in the 80387 +register stack, some floating-point opcodes may be emitted even if +\&\fB\-msoft\-float\fR is used. +.IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4 +.IX Item "-mno-fp-ret-in-387" +Do not use the \s-1FPU\s0 registers for return values of functions. +.Sp +The usual calling convention has functions return values of types +\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there +is no \s-1FPU. \s0 The idea is that the operating system should emulate +an \s-1FPU.\s0 +.Sp +The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned +in ordinary \s-1CPU\s0 registers instead. +.IP "\fB\-mno\-fancy\-math\-387\fR" 4 +.IX Item "-mno-fancy-math-387" +Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and +\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid +generating those instructions. This option is the default on FreeBSD, +OpenBSD and NetBSD. This option is overridden when \fB\-march\fR +indicates that the target \s-1CPU\s0 always has an \s-1FPU\s0 and so the +instruction does not need emulation. These +instructions are not generated unless you also use the +\&\fB\-funsafe\-math\-optimizations\fR switch. +.IP "\fB\-malign\-double\fR" 4 +.IX Item "-malign-double" .PD 0 -.IP "\fB\-m64\fR" 4 -.IX Item "-m64" +.IP "\fB\-mno\-align\-double\fR" 4 +.IX Item "-mno-align-double" .PD -Generate code for a 32\-bit or 64\-bit environment. The 32\-bit -environment sets int, long, and pointer to 32 bits. The 64\-bit -environment sets int to 32 bits and long and pointer to 64 bits. -.IP "\fB\-mbig\-endian\fR" 4 -.IX Item "-mbig-endian" +Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and +\&\f(CW\*(C`long long\*(C'\fR variables on a two-word boundary or a one-word +boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two-word boundary +produces code that runs somewhat faster on a Pentium at the +expense of more memory. +.Sp +On x86\-64, \fB\-malign\-double\fR is enabled by default. +.Sp +\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch, +structures containing the above types are aligned differently than +the published application binary interface specifications for the x86\-32 +and are not binary compatible with structures in code compiled +without that switch. +.IP "\fB\-m96bit\-long\-double\fR" 4 +.IX Item "-m96bit-long-double" .PD 0 -.IP "\fB\-mlittle\-endian\fR" 4 -.IX Item "-mlittle-endian" +.IP "\fB\-m128bit\-long\-double\fR" 4 +.IX Item "-m128bit-long-double" .PD -Generate code in big/little endian mode, respectively. -.PP -\fITILEPro Options\fR -.IX Subsection "TILEPro Options" -.PP -These \fB\-m\fR options are supported on the TILEPro: -.IP "\fB\-mcpu=\fR\fIname\fR" 4 -.IX Item "-mcpu=name" -Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported -type is \fBtilepro\fR. -.IP "\fB\-m32\fR" 4 -.IX Item "-m32" -Generate code for a 32\-bit environment, which sets int, long, and -pointer to 32 bits. This is the only supported behavior so the flag -is essentially ignored. -.PP -\fIV850 Options\fR -.IX Subsection "V850 Options" -.PP -These \fB\-m\fR options are defined for V850 implementations: -.IP "\fB\-mlong\-calls\fR" 4 -.IX Item "-mlong-calls" +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The x86\-32 +application binary interface specifies the size to be 96 bits, +so \fB\-m96bit\-long\-double\fR is the default in 32\-bit mode. +.Sp +Modern architectures (Pentium and newer) prefer \f(CW\*(C`long double\*(C'\fR +to be aligned to an 8\- or 16\-byte boundary. In arrays or structures +conforming to the \s-1ABI,\s0 this is not possible. So specifying +\&\fB\-m128bit\-long\-double\fR aligns \f(CW\*(C`long double\*(C'\fR +to a 16\-byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional +32\-bit zero. +.Sp +In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as +its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is aligned on 16\-byte boundary. +.Sp +Notice that neither of these options enable any extra precision over the x87 +standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR. +.Sp +\&\fBWarning:\fR if you override the default value for your target \s-1ABI,\s0 this +changes the size of +structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, +as well as modifying the function calling convention for functions taking +\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible +with code compiled without that switch. +.IP "\fB\-mlong\-double\-64\fR" 4 +.IX Item "-mlong-double-64" .PD 0 -.IP "\fB\-mno\-long\-calls\fR" 4 -.IX Item "-mno-long-calls" +.IP "\fB\-mlong\-double\-80\fR" 4 +.IX Item "-mlong-double-80" +.IP "\fB\-mlong\-double\-128\fR" 4 +.IX Item "-mlong-double-128" .PD -Treat all calls as being far away (near). If calls are assumed to be -far away, the compiler always loads the function's address into a -register, and calls indirect through the pointer. -.IP "\fB\-mno\-ep\fR" 4 -.IX Item "-mno-ep" +These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size +of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR +type. This is the default for 32\-bit Bionic C library. A size +of 128 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the +\&\f(CW\*(C`_\|_float128\*(C'\fR type. This is the default for 64\-bit Bionic C library. +.Sp +\&\fBWarning:\fR if you override the default value for your target \s-1ABI,\s0 this +changes the size of +structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables, +as well as modifying the function calling convention for functions taking +\&\f(CW\*(C`long double\*(C'\fR. Hence they are not binary-compatible +with code compiled without that switch. +.IP "\fB\-malign\-data=\fR\fItype\fR" 4 +.IX Item "-malign-data=type" +Control how \s-1GCC\s0 aligns variables. Supported values for \fItype\fR are +\&\fBcompat\fR uses increased alignment value compatible uses \s-1GCC 4.8\s0 +and earlier, \fBabi\fR uses alignment value as specified by the +psABI, and \fBcacheline\fR uses increased alignment value to match +the cache line size. \fBcompat\fR is the default. +.IP "\fB\-mlarge\-data\-threshold=\fR\fIthreshold\fR" 4 +.IX Item "-mlarge-data-threshold=threshold" +When \fB\-mcmodel=medium\fR is specified, data objects larger than +\&\fIthreshold\fR are placed in the large data section. This value must be the +same across all objects linked into the binary, and defaults to 65535. +.IP "\fB\-mrtd\fR" 4 +.IX Item "-mrtd" +Use a different function-calling convention, in which functions that +take a fixed number of arguments return with the \f(CW\*(C`ret \f(CInum\f(CW\*(C'\fR +instruction, which pops their arguments while returning. This saves one +instruction in the caller since there is no need to pop the arguments +there. +.Sp +You can specify that an individual function is called with this calling +sequence with the function attribute \f(CW\*(C`stdcall\*(C'\fR. You can also +override the \fB\-mrtd\fR option by using the function attribute +\&\f(CW\*(C`cdecl\*(C'\fR. +.Sp +\&\fBWarning:\fR this calling convention is incompatible with the one +normally used on Unix, so you cannot use it if you need to call +libraries compiled with the Unix compiler. +.Sp +Also, you must provide function prototypes for all functions that +take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); +otherwise incorrect code is generated for calls to those +functions. +.Sp +In addition, seriously incorrect code results if you call a +function with too many arguments. (Normally, extra arguments are +harmlessly ignored.) +.IP "\fB\-mregparm=\fR\fInum\fR" 4 +.IX Item "-mregparm=num" +Control how many registers are used to pass integer arguments. By +default, no registers are used to pass arguments, and at most 3 +registers can be used. You can control this behavior for a specific +function by using the function attribute \f(CW\*(C`regparm\*(C'\fR. +.Sp +\&\fBWarning:\fR if you use this switch, and +\&\fInum\fR is nonzero, then you must build all modules with the same +value, including any libraries. This includes the system libraries and +startup modules. +.IP "\fB\-msseregparm\fR" 4 +.IX Item "-msseregparm" +Use \s-1SSE\s0 register passing conventions for float and double arguments +and return values. You can control this behavior for a specific +function by using the function attribute \f(CW\*(C`sseregparm\*(C'\fR. +.Sp +\&\fBWarning:\fR if you use this switch then you must build all +modules with the same value, including any libraries. This includes +the system libraries and startup modules. +.IP "\fB\-mvect8\-ret\-in\-mem\fR" 4 +.IX Item "-mvect8-ret-in-mem" +Return 8\-byte vectors in memory instead of \s-1MMX\s0 registers. This is the +default on Solaris@tie{}8 and 9 and VxWorks to match the \s-1ABI\s0 of the Sun +Studio compilers until version 12. Later compiler versions (starting +with Studio 12 Update@tie{}1) follow the \s-1ABI\s0 used by other x86 targets, which +is the default on Solaris@tie{}10 and later. \fIOnly\fR use this option if +you need to remain compatible with existing code produced by those +previous compiler versions or older versions of \s-1GCC.\s0 +.IP "\fB\-mpc32\fR" 4 +.IX Item "-mpc32" .PD 0 -.IP "\fB\-mep\fR" 4 -.IX Item "-mep" +.IP "\fB\-mpc64\fR" 4 +.IX Item "-mpc64" +.IP "\fB\-mpc80\fR" 4 +.IX Item "-mpc80" .PD -Do not optimize (do optimize) basic blocks that use the same index -pointer 4 or more times to copy pointer into the \f(CW\*(C`ep\*(C'\fR register, and -use the shorter \f(CW\*(C`sld\*(C'\fR and \f(CW\*(C`sst\*(C'\fR instructions. The \fB\-mep\fR -option is on by default if you optimize. -.IP "\fB\-mno\-prolog\-function\fR" 4 -.IX Item "-mno-prolog-function" +Set 80387 floating-point precision to 32, 64 or 80 bits. When \fB\-mpc32\fR +is specified, the significands of results of floating-point operations are +rounded to 24 bits (single precision); \fB\-mpc64\fR rounds the +significands of results of floating-point operations to 53 bits (double +precision) and \fB\-mpc80\fR rounds the significands of results of +floating-point operations to 64 bits (extended double precision), which is +the default. When this option is used, floating-point operations in higher +precisions are not available to the programmer without setting the \s-1FPU\s0 +control word explicitly. +.Sp +Setting the rounding of floating-point operations to less than the default +80 bits can speed some programs by 2% or more. Note that some mathematical +libraries assume that extended-precision (80\-bit) floating-point operations +are enabled by default; routines in such libraries could suffer significant +loss of accuracy, typically through so-called \*(L"catastrophic cancellation\*(R", +when this option is used to set the precision to less than extended precision. +.IP "\fB\-mstackrealign\fR" 4 +.IX Item "-mstackrealign" +Realign the stack at entry. On the x86, the \fB\-mstackrealign\fR +option generates an alternate prologue and epilogue that realigns the +run-time stack if necessary. This supports mixing legacy codes that keep +4\-byte stack alignment with modern codes that keep 16\-byte stack alignment for +\&\s-1SSE\s0 compatibility. See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR, +applicable to individual functions. +.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mpreferred-stack-boundary=num" +Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR +byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified, +the default is 4 (16 bytes or 128 bits). +.Sp +\&\fBWarning:\fR When generating code for the x86\-64 architecture with +\&\s-1SSE\s0 extensions disabled, \fB\-mpreferred\-stack\-boundary=3\fR can be +used to keep the stack boundary aligned to 8 byte boundary. Since +x86\-64 \s-1ABI\s0 require 16 byte stack alignment, this is \s-1ABI\s0 incompatible and +intended to be used in controlled environment where stack space is +important limitation. This option leads to wrong code when functions +compiled with 16 byte stack alignment (such as functions from a standard +library) are called with misaligned stack. In this case, \s-1SSE\s0 +instructions may lead to misaligned memory access traps. In addition, +variable arguments are handled incorrectly for 16 byte aligned +objects (including x87 long double and _\|_int128), leading to wrong +results. You must build all modules with +\&\fB\-mpreferred\-stack\-boundary=3\fR, including any libraries. This +includes the system libraries and startup modules. +.IP "\fB\-mincoming\-stack\-boundary=\fR\fInum\fR" 4 +.IX Item "-mincoming-stack-boundary=num" +Assume the incoming stack is aligned to a 2 raised to \fInum\fR byte +boundary. If \fB\-mincoming\-stack\-boundary\fR is not specified, +the one specified by \fB\-mpreferred\-stack\-boundary\fR is used. +.Sp +On Pentium and Pentium Pro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values +should be aligned to an 8\-byte boundary (see \fB\-malign\-double\fR) or +suffer significant run time performance penalties. On Pentium \s-1III,\s0 the +Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work +properly if it is not 16\-byte aligned. +.Sp +To ensure proper alignment of this values on the stack, the stack boundary +must be as aligned as that required by any value stored on the stack. +Further, every function must be generated such that it keeps the stack +aligned. Thus calling a function compiled with a higher preferred +stack boundary from a function compiled with a lower preferred stack +boundary most likely misaligns the stack. It is recommended that +libraries that use callbacks always use the default setting. +.Sp +This extra alignment does consume extra stack space, and generally +increases code size. Code that is sensitive to stack space usage, such +as embedded systems and operating system kernels, may want to reduce the +preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR. +.IP "\fB\-mmmx\fR" 4 +.IX Item "-mmmx" .PD 0 -.IP "\fB\-mprolog\-function\fR" 4 -.IX Item "-mprolog-function" +.IP "\fB\-msse\fR" 4 +.IX Item "-msse" +.IP "\fB\-msse2\fR" 4 +.IX Item "-msse2" +.IP "\fB\-msse3\fR" 4 +.IX Item "-msse3" +.IP "\fB\-mssse3\fR" 4 +.IX Item "-mssse3" +.IP "\fB\-msse4\fR" 4 +.IX Item "-msse4" +.IP "\fB\-msse4a\fR" 4 +.IX Item "-msse4a" +.IP "\fB\-msse4.1\fR" 4 +.IX Item "-msse4.1" +.IP "\fB\-msse4.2\fR" 4 +.IX Item "-msse4.2" +.IP "\fB\-mavx\fR" 4 +.IX Item "-mavx" +.IP "\fB\-mavx2\fR" 4 +.IX Item "-mavx2" +.IP "\fB\-mavx512f\fR" 4 +.IX Item "-mavx512f" +.IP "\fB\-mavx512pf\fR" 4 +.IX Item "-mavx512pf" +.IP "\fB\-mavx512er\fR" 4 +.IX Item "-mavx512er" +.IP "\fB\-mavx512cd\fR" 4 +.IX Item "-mavx512cd" +.IP "\fB\-msha\fR" 4 +.IX Item "-msha" +.IP "\fB\-maes\fR" 4 +.IX Item "-maes" +.IP "\fB\-mpclmul\fR" 4 +.IX Item "-mpclmul" +.IP "\fB\-mclfushopt\fR" 4 +.IX Item "-mclfushopt" +.IP "\fB\-mfsgsbase\fR" 4 +.IX Item "-mfsgsbase" +.IP "\fB\-mrdrnd\fR" 4 +.IX Item "-mrdrnd" +.IP "\fB\-mf16c\fR" 4 +.IX Item "-mf16c" +.IP "\fB\-mfma\fR" 4 +.IX Item "-mfma" +.IP "\fB\-mfma4\fR" 4 +.IX Item "-mfma4" +.IP "\fB\-mno\-fma4\fR" 4 +.IX Item "-mno-fma4" +.IP "\fB\-mprefetchwt1\fR" 4 +.IX Item "-mprefetchwt1" +.IP "\fB\-mxop\fR" 4 +.IX Item "-mxop" +.IP "\fB\-mlwp\fR" 4 +.IX Item "-mlwp" +.IP "\fB\-m3dnow\fR" 4 +.IX Item "-m3dnow" +.IP "\fB\-mpopcnt\fR" 4 +.IX Item "-mpopcnt" +.IP "\fB\-mabm\fR" 4 +.IX Item "-mabm" +.IP "\fB\-mbmi\fR" 4 +.IX Item "-mbmi" +.IP "\fB\-mbmi2\fR" 4 +.IX Item "-mbmi2" +.IP "\fB\-mlzcnt\fR" 4 +.IX Item "-mlzcnt" +.IP "\fB\-mfxsr\fR" 4 +.IX Item "-mfxsr" +.IP "\fB\-mxsave\fR" 4 +.IX Item "-mxsave" +.IP "\fB\-mxsaveopt\fR" 4 +.IX Item "-mxsaveopt" +.IP "\fB\-mxsavec\fR" 4 +.IX Item "-mxsavec" +.IP "\fB\-mxsaves\fR" 4 +.IX Item "-mxsaves" +.IP "\fB\-mrtm\fR" 4 +.IX Item "-mrtm" +.IP "\fB\-mtbm\fR" 4 +.IX Item "-mtbm" +.IP "\fB\-mmpx\fR" 4 +.IX Item "-mmpx" .PD -Do not use (do use) external functions to save and restore registers -at the prologue and epilogue of a function. The external functions -are slower, but use less code space if more than one function saves -the same number of registers. The \fB\-mprolog\-function\fR option -is on by default if you optimize. -.IP "\fB\-mspace\fR" 4 -.IX Item "-mspace" -Try to make the code as small as possible. At present, this just turns -on the \fB\-mep\fR and \fB\-mprolog\-function\fR options. -.IP "\fB\-mtda=\fR\fIn\fR" 4 -.IX Item "-mtda=n" -Put static or global variables whose size is \fIn\fR bytes or less into -the tiny data area that register \f(CW\*(C`ep\*(C'\fR points to. The tiny data -area can hold up to 256 bytes in total (128 bytes for byte references). -.IP "\fB\-msda=\fR\fIn\fR" 4 -.IX Item "-msda=n" -Put static or global variables whose size is \fIn\fR bytes or less into -the small data area that register \f(CW\*(C`gp\*(C'\fR points to. The small data -area can hold up to 64 kilobytes. -.IP "\fB\-mzda=\fR\fIn\fR" 4 -.IX Item "-mzda=n" -Put static or global variables whose size is \fIn\fR bytes or less into -the first 32 kilobytes of memory. -.IP "\fB\-mv850\fR" 4 -.IX Item "-mv850" -Specify that the target processor is the V850. -.IP "\fB\-mv850e3v5\fR" 4 -.IX Item "-mv850e3v5" -Specify that the target processor is the V850E3V5. The preprocessor -constant \f(CW\*(C`_\|_v850e3v5_\|_\*(C'\fR is defined if this option is used. -.IP "\fB\-mv850e2v4\fR" 4 -.IX Item "-mv850e2v4" -Specify that the target processor is the V850E3V5. This is an alias for -the \fB\-mv850e3v5\fR option. -.IP "\fB\-mv850e2v3\fR" 4 -.IX Item "-mv850e2v3" -Specify that the target processor is the V850E2V3. The preprocessor -constant \f(CW\*(C`_\|_v850e2v3_\|_\*(C'\fR is defined if this option is used. -.IP "\fB\-mv850e2\fR" 4 -.IX Item "-mv850e2" -Specify that the target processor is the V850E2. The preprocessor -constant \f(CW\*(C`_\|_v850e2_\|_\*(C'\fR is defined if this option is used. -.IP "\fB\-mv850e1\fR" 4 -.IX Item "-mv850e1" -Specify that the target processor is the V850E1. The preprocessor -constants \f(CW\*(C`_\|_v850e1_\|_\*(C'\fR and \f(CW\*(C`_\|_v850e_\|_\*(C'\fR are defined if -this option is used. -.IP "\fB\-mv850es\fR" 4 -.IX Item "-mv850es" -Specify that the target processor is the V850ES. This is an alias for -the \fB\-mv850e1\fR option. -.IP "\fB\-mv850e\fR" 4 -.IX Item "-mv850e" -Specify that the target processor is the V850E. The preprocessor -constant \f(CW\*(C`_\|_v850e_\|_\*(C'\fR is defined if this option is used. +These switches enable the use of instructions in the \s-1MMX, SSE, +SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, +SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, +BMI, BMI2, FXSR, XSAVE, XSAVEOPT, LZCNT, RTM, MPX\s0 or 3DNow! +extended instruction sets. Each has a corresponding \fB\-mno\-\fR option +to disable use of these instructions. .Sp -If neither \fB\-mv850\fR nor \fB\-mv850e\fR nor \fB\-mv850e1\fR -nor \fB\-mv850e2\fR nor \fB\-mv850e2v3\fR nor \fB\-mv850e3v5\fR -are defined then a default target processor is chosen and the -relevant \fB_\|_v850*_\|_\fR preprocessor constant is defined. +These extensions are also available as built-in functions: see +\&\fBx86 Built-in Functions\fR, for details of the functions enabled and +disabled by these switches. .Sp -The preprocessor constants \f(CW\*(C`_\|_v850\*(C'\fR and \f(CW\*(C`_\|_v851_\|_\*(C'\fR are always -defined, regardless of which processor variant is the target. -.IP "\fB\-mdisable\-callt\fR" 4 -.IX Item "-mdisable-callt" -.PD 0 -.IP "\fB\-mno\-disable\-callt\fR" 4 -.IX Item "-mno-disable-callt" -.PD -This option suppresses generation of the \f(CW\*(C`CALLT\*(C'\fR instruction for the -v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850 -architecture. +To generate \s-1SSE/SSE2\s0 instructions automatically from floating-point +code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR. .Sp -This option is enabled by default when the \s-1RH850\s0 \s-1ABI\s0 is -in use (see \fB\-mrh850\-abi\fR), and disabled by default when the -\&\s-1GCC\s0 \s-1ABI\s0 is in use. If \f(CW\*(C`CALLT\*(C'\fR instructions are being generated -then the C preprocessor symbol \f(CW\*(C`_\|_V850_CALLT_\|_\*(C'\fR is defined. -.IP "\fB\-mrelax\fR" 4 -.IX Item "-mrelax" -.PD 0 -.IP "\fB\-mno\-relax\fR" 4 -.IX Item "-mno-relax" -.PD -Pass on (or do not pass on) the \fB\-mrelax\fR command line option -to the assembler. -.IP "\fB\-mlong\-jumps\fR" 4 -.IX Item "-mlong-jumps" +\&\s-1GCC\s0 depresses SSEx instructions when \fB\-mavx\fR is used. Instead, it +generates new \s-1AVX\s0 instructions or \s-1AVX\s0 equivalence for all SSEx instructions +when needed. +.Sp +These options enable \s-1GCC\s0 to use these extended instructions in +generated code, even without \fB\-mfpmath=sse\fR. Applications that +perform run-time \s-1CPU\s0 detection must compile separate files for each +supported architecture, using the appropriate flags. In particular, +the file containing the \s-1CPU\s0 detection code should be compiled without +these options. +.IP "\fB\-mdump\-tune\-features\fR" 4 +.IX Item "-mdump-tune-features" +This option instructs \s-1GCC\s0 to dump the names of the x86 performance +tuning features and default settings. The names can be used in +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR. +.IP "\fB\-mtune\-ctrl=\fR\fIfeature-list\fR" 4 +.IX Item "-mtune-ctrl=feature-list" +This option is used to do fine grain control of x86 code generation features. +\&\fIfeature-list\fR is a comma separated list of \fIfeature\fR names. See also +\&\fB\-mdump\-tune\-features\fR. When specified, the \fIfeature\fR is turned +on if it is not preceded with \fB^\fR, otherwise, it is turned off. +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR is intended to be used by \s-1GCC\s0 +developers. Using it may lead to code paths not covered by testing and can +potentially result in compiler ICEs or runtime errors. +.IP "\fB\-mno\-default\fR" 4 +.IX Item "-mno-default" +This option instructs \s-1GCC\s0 to turn off all tunable features. See also +\&\fB\-mtune\-ctrl=\fR\fIfeature-list\fR and \fB\-mdump\-tune\-features\fR. +.IP "\fB\-mcld\fR" 4 +.IX Item "-mcld" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`cld\*(C'\fR instruction in the prologue +of functions that use string instructions. String instructions depend on +the \s-1DF\s0 flag to select between autoincrement or autodecrement mode. While the +\&\s-1ABI\s0 specifies the \s-1DF\s0 flag to be cleared on function entry, some operating +systems violate this specification by not clearing the \s-1DF\s0 flag in their +exception dispatchers. The exception handler can be invoked with the \s-1DF\s0 flag +set, which leads to wrong direction mode when string instructions are used. +This option can be enabled by default on 32\-bit x86 targets by configuring +\&\s-1GCC\s0 with the \fB\-\-enable\-cld\fR configure option. Generation of \f(CW\*(C`cld\*(C'\fR +instructions can be suppressed with the \fB\-mno\-cld\fR compiler option +in this case. +.IP "\fB\-mvzeroupper\fR" 4 +.IX Item "-mvzeroupper" +This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`vzeroupper\*(C'\fR instruction +before a transfer of control flow out of the function to minimize +the \s-1AVX\s0 to \s-1SSE\s0 transition penalty as well as remove unnecessary \f(CW\*(C`zeroupper\*(C'\fR +intrinsics. +.IP "\fB\-mprefer\-avx128\fR" 4 +.IX Item "-mprefer-avx128" +This option instructs \s-1GCC\s0 to use 128\-bit \s-1AVX\s0 instructions instead of +256\-bit \s-1AVX\s0 instructions in the auto-vectorizer. +.IP "\fB\-mcx16\fR" 4 +.IX Item "-mcx16" +This option enables \s-1GCC\s0 to generate \f(CW\*(C`CMPXCHG16B\*(C'\fR instructions. +\&\f(CW\*(C`CMPXCHG16B\*(C'\fR allows for atomic operations on 128\-bit double quadword +(or oword) data types. +This is useful for high-resolution counters that can be updated +by multiple processors (or cores). This instruction is generated as part of +atomic built-in functions: see \fB_\|_sync Builtins\fR or +\&\fB_\|_atomic Builtins\fR for details. +.IP "\fB\-msahf\fR" 4 +.IX Item "-msahf" +This option enables generation of \f(CW\*(C`SAHF\*(C'\fR instructions in 64\-bit code. +Early Intel Pentium 4 CPUs with Intel 64 support, +prior to the introduction of Pentium 4 G1 step in December 2005, +lacked the \f(CW\*(C`LAHF\*(C'\fR and \f(CW\*(C`SAHF\*(C'\fR instructions +which are supported by \s-1AMD64.\s0 +These are load and store instructions, respectively, for certain status flags. +In 64\-bit mode, the \f(CW\*(C`SAHF\*(C'\fR instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, +\&\f(CW\*(C`drem\*(C'\fR, and \f(CW\*(C`remainder\*(C'\fR built-in functions; +see \fBOther Builtins\fR for details. +.IP "\fB\-mmovbe\fR" 4 +.IX Item "-mmovbe" +This option enables use of the \f(CW\*(C`movbe\*(C'\fR instruction to implement +\&\f(CW\*(C`_\|_builtin_bswap32\*(C'\fR and \f(CW\*(C`_\|_builtin_bswap64\*(C'\fR. +.IP "\fB\-mcrc32\fR" 4 +.IX Item "-mcrc32" +This option enables built-in functions \f(CW\*(C`_\|_builtin_ia32_crc32qi\*(C'\fR, +\&\f(CW\*(C`_\|_builtin_ia32_crc32hi\*(C'\fR, \f(CW\*(C`_\|_builtin_ia32_crc32si\*(C'\fR and +\&\f(CW\*(C`_\|_builtin_ia32_crc32di\*(C'\fR to generate the \f(CW\*(C`crc32\*(C'\fR machine instruction. +.IP "\fB\-mrecip\fR" 4 +.IX Item "-mrecip" +This option enables use of \f(CW\*(C`RCPSS\*(C'\fR and \f(CW\*(C`RSQRTSS\*(C'\fR instructions +(and their vectorized variants \f(CW\*(C`RCPPS\*(C'\fR and \f(CW\*(C`RSQRTPS\*(C'\fR) +with an additional Newton-Raphson step +to increase precision instead of \f(CW\*(C`DIVSS\*(C'\fR and \f(CW\*(C`SQRTSS\*(C'\fR +(and their vectorized +variants) for single-precision floating-point arguments. These instructions +are generated only when \fB\-funsafe\-math\-optimizations\fR is enabled +together with \fB\-finite\-math\-only\fR and \fB\-fno\-trapping\-math\fR. +Note that while the throughput of the sequence is higher than the throughput +of the non-reciprocal instruction, the precision of the sequence can be +decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). +.Sp +Note that \s-1GCC\s0 implements \f(CW\*(C`1.0f/sqrtf(\f(CIx\f(CW)\*(C'\fR in terms of \f(CW\*(C`RSQRTSS\*(C'\fR +(or \f(CW\*(C`RSQRTPS\*(C'\fR) already with \fB\-ffast\-math\fR (or the above option +combination), and doesn't need \fB\-mrecip\fR. +.Sp +Also note that \s-1GCC\s0 emits the above sequence with additional Newton-Raphson step +for vectorized single-float division and vectorized \f(CW\*(C`sqrtf(\f(CIx\f(CW)\*(C'\fR +already with \fB\-ffast\-math\fR (or the above option combination), and +doesn't need \fB\-mrecip\fR. +.IP "\fB\-mrecip=\fR\fIopt\fR" 4 +.IX Item "-mrecip=opt" +This option controls which reciprocal estimate instructions +may be used. \fIopt\fR is a comma-separated list of options, which may +be preceded by a \fB!\fR to invert the option: +.RS 4 +.IP "\fBall\fR" 4 +.IX Item "all" +Enable all estimate instructions. +.IP "\fBdefault\fR" 4 +.IX Item "default" +Enable the default instructions, equivalent to \fB\-mrecip\fR. +.IP "\fBnone\fR" 4 +.IX Item "none" +Disable all estimate instructions, equivalent to \fB\-mno\-recip\fR. +.IP "\fBdiv\fR" 4 +.IX Item "div" +Enable the approximation for scalar division. +.IP "\fBvec-div\fR" 4 +.IX Item "vec-div" +Enable the approximation for vectorized division. +.IP "\fBsqrt\fR" 4 +.IX Item "sqrt" +Enable the approximation for scalar square root. +.IP "\fBvec-sqrt\fR" 4 +.IX Item "vec-sqrt" +Enable the approximation for vectorized square root. +.RE +.RS 4 +.Sp +So, for example, \fB\-mrecip=all,!sqrt\fR enables +all of the reciprocal approximations, except for square root. +.RE +.IP "\fB\-mveclibabi=\fR\fItype\fR" 4 +.IX Item "-mveclibabi=type" +Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an +external library. Supported values for \fItype\fR are \fBsvml\fR +for the Intel short +vector math library and \fBacml\fR for the \s-1AMD\s0 math core library. +To use this option, both \fB\-ftree\-vectorize\fR and +\&\fB\-funsafe\-math\-optimizations\fR have to be enabled, and an \s-1SVML\s0 or \s-1ACML \s0 +ABI-compatible library must be specified at link time. +.Sp +\&\s-1GCC\s0 currently emits calls to \f(CW\*(C`vmldExp2\*(C'\fR, +\&\f(CW\*(C`vmldLn2\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldPow2\*(C'\fR, +\&\f(CW\*(C`vmldTanh2\*(C'\fR, \f(CW\*(C`vmldTan2\*(C'\fR, \f(CW\*(C`vmldAtan2\*(C'\fR, \f(CW\*(C`vmldAtanh2\*(C'\fR, +\&\f(CW\*(C`vmldCbrt2\*(C'\fR, \f(CW\*(C`vmldSinh2\*(C'\fR, \f(CW\*(C`vmldSin2\*(C'\fR, \f(CW\*(C`vmldAsinh2\*(C'\fR, +\&\f(CW\*(C`vmldAsin2\*(C'\fR, \f(CW\*(C`vmldCosh2\*(C'\fR, \f(CW\*(C`vmldCos2\*(C'\fR, \f(CW\*(C`vmldAcosh2\*(C'\fR, +\&\f(CW\*(C`vmldAcos2\*(C'\fR, \f(CW\*(C`vmlsExp4\*(C'\fR, \f(CW\*(C`vmlsLn4\*(C'\fR, \f(CW\*(C`vmlsLog104\*(C'\fR, +\&\f(CW\*(C`vmlsLog104\*(C'\fR, \f(CW\*(C`vmlsPow4\*(C'\fR, \f(CW\*(C`vmlsTanh4\*(C'\fR, \f(CW\*(C`vmlsTan4\*(C'\fR, +\&\f(CW\*(C`vmlsAtan4\*(C'\fR, \f(CW\*(C`vmlsAtanh4\*(C'\fR, \f(CW\*(C`vmlsCbrt4\*(C'\fR, \f(CW\*(C`vmlsSinh4\*(C'\fR, +\&\f(CW\*(C`vmlsSin4\*(C'\fR, \f(CW\*(C`vmlsAsinh4\*(C'\fR, \f(CW\*(C`vmlsAsin4\*(C'\fR, \f(CW\*(C`vmlsCosh4\*(C'\fR, +\&\f(CW\*(C`vmlsCos4\*(C'\fR, \f(CW\*(C`vmlsAcosh4\*(C'\fR and \f(CW\*(C`vmlsAcos4\*(C'\fR for corresponding +function type when \fB\-mveclibabi=svml\fR is used, and \f(CW\*(C`_\|_vrd2_sin\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_cos\*(C'\fR, \f(CW\*(C`_\|_vrd2_exp\*(C'\fR, \f(CW\*(C`_\|_vrd2_log\*(C'\fR, \f(CW\*(C`_\|_vrd2_log2\*(C'\fR, +\&\f(CW\*(C`_\|_vrd2_log10\*(C'\fR, \f(CW\*(C`_\|_vrs4_sinf\*(C'\fR, \f(CW\*(C`_\|_vrs4_cosf\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_expf\*(C'\fR, \f(CW\*(C`_\|_vrs4_logf\*(C'\fR, \f(CW\*(C`_\|_vrs4_log2f\*(C'\fR, +\&\f(CW\*(C`_\|_vrs4_log10f\*(C'\fR and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR for the corresponding function type +when \fB\-mveclibabi=acml\fR is used. +.IP "\fB\-mabi=\fR\fIname\fR" 4 +.IX Item "-mabi=name" +Generate code for the specified calling convention. Permissible values +are \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems, and +\&\fBms\fR for the Microsoft \s-1ABI. \s0 The default is to use the Microsoft +\&\s-1ABI\s0 when targeting Microsoft Windows and the SysV \s-1ABI\s0 on all other systems. +You can control this behavior for specific functions by +using the function attributes \f(CW\*(C`ms_abi\*(C'\fR and \f(CW\*(C`sysv_abi\*(C'\fR. +.IP "\fB\-mtls\-dialect=\fR\fItype\fR" 4 +.IX Item "-mtls-dialect=type" +Generate code to access thread-local storage using the \fBgnu\fR or +\&\fBgnu2\fR conventions. \fBgnu\fR is the conservative default; +\&\fBgnu2\fR is more efficient, but it may add compile\- and run-time +requirements that cannot be satisfied on all systems. +.IP "\fB\-mpush\-args\fR" 4 +.IX Item "-mpush-args" .PD 0 -.IP "\fB\-mno\-long\-jumps\fR" 4 -.IX Item "-mno-long-jumps" +.IP "\fB\-mno\-push\-args\fR" 4 +.IX Item "-mno-push-args" .PD -Disable (or re-enable) the generation of PC-relative jump instructions. -.IP "\fB\-msoft\-float\fR" 4 -.IX Item "-msoft-float" +Use \s-1PUSH\s0 operations to store outgoing parameters. This method is shorter +and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled +by default. In some cases disabling it may improve performance because of +improved scheduling and reduced dependencies. +.IP "\fB\-maccumulate\-outgoing\-args\fR" 4 +.IX Item "-maccumulate-outgoing-args" +If enabled, the maximum amount of space required for outgoing arguments is +computed in the function prologue. This is faster on most modern CPUs +because of reduced dependencies, improved scheduling and reduced stack usage +when the preferred stack boundary is not equal to 2. The drawback is a notable +increase in code size. This switch implies \fB\-mno\-push\-args\fR. +.IP "\fB\-mthreads\fR" 4 +.IX Item "-mthreads" +Support thread-safe exception handling on MinGW. Programs that rely +on thread-safe exception handling must compile and link all code with the +\&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines +\&\fB\-D_MT\fR; when linking, it links in a special thread helper library +\&\fB\-lmingwthrd\fR which cleans up per-thread exception-handling data. +.IP "\fB\-mno\-align\-stringops\fR" 4 +.IX Item "-mno-align-stringops" +Do not align the destination of inlined string operations. This switch reduces +code size and improves performance in case the destination is already aligned, +but \s-1GCC\s0 doesn't know about it. +.IP "\fB\-minline\-all\-stringops\fR" 4 +.IX Item "-minline-all-stringops" +By default \s-1GCC\s0 inlines string operations only when the destination is +known to be aligned to least a 4\-byte boundary. +This enables more inlining and increases code +size, but may improve performance of code that depends on fast +\&\f(CW\*(C`memcpy\*(C'\fR, \f(CW\*(C`strlen\*(C'\fR, +and \f(CW\*(C`memset\*(C'\fR for short lengths. +.IP "\fB\-minline\-stringops\-dynamically\fR" 4 +.IX Item "-minline-stringops-dynamically" +For string operations of unknown size, use run-time checks with +inline code for small blocks and a library call for large blocks. +.IP "\fB\-mstringop\-strategy=\fR\fIalg\fR" 4 +.IX Item "-mstringop-strategy=alg" +Override the internal decision heuristic for the particular algorithm to use +for inlining string operations. The allowed values for \fIalg\fR are: +.RS 4 +.IP "\fBrep_byte\fR" 4 +.IX Item "rep_byte" .PD 0 -.IP "\fB\-mhard\-float\fR" 4 -.IX Item "-mhard-float" +.IP "\fBrep_4byte\fR" 4 +.IX Item "rep_4byte" +.IP "\fBrep_8byte\fR" 4 +.IX Item "rep_8byte" .PD -Disable (or re-enable) the generation of hardware floating point -instructions. This option is only significant when the target -architecture is \fBV850E2V3\fR or higher. If hardware floating point -instructions are being generated then the C preprocessor symbol -\&\f(CW\*(C`_\|_FPU_OK_\|_\*(C'\fR is defined, otherwise the symbol -\&\f(CW\*(C`_\|_NO_FPU_\|_\*(C'\fR is defined. -.IP "\fB\-mloop\fR" 4 -.IX Item "-mloop" -Enables the use of the e3v5 \s-1LOOP\s0 instruction. The use of this -instruction is not enabled by default when the e3v5 architecture is -selected because its use is still experimental. -.IP "\fB\-mrh850\-abi\fR" 4 -.IX Item "-mrh850-abi" +Expand using i386 \f(CW\*(C`rep\*(C'\fR prefix of the specified size. +.IP "\fBbyte_loop\fR" 4 +.IX Item "byte_loop" .PD 0 -.IP "\fB\-mghs\fR" 4 -.IX Item "-mghs" +.IP "\fBloop\fR" 4 +.IX Item "loop" +.IP "\fBunrolled_loop\fR" 4 +.IX Item "unrolled_loop" .PD -Enables support for the \s-1RH850\s0 version of the V850 \s-1ABI\s0. This is the -default. With this version of the \s-1ABI\s0 the following rules apply: -.RS 4 -.IP "*" 4 -Integer sized structures and unions are returned via a memory pointer -rather than a register. -.IP "*" 4 -Large structures and unions (more than 8 bytes in size) are passed by -value. -.IP "*" 4 -Functions are aligned to 16\-bit boundaries. -.IP "*" 4 -The \fB\-m8byte\-align\fR command line option is supported. -.IP "*" 4 -The \fB\-mdisable\-callt\fR command line option is enabled by -default. The \fB\-mno\-disable\-callt\fR command line option is not -supported. -.RE -.RS 4 -.Sp -When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol -\&\f(CW\*(C`_\|_V850_RH850_ABI_\|_\*(C'\fR is defined. +Expand into an inline loop. +.IP "\fBlibcall\fR" 4 +.IX Item "libcall" +Always use a library call. .RE -.IP "\fB\-mgcc\-abi\fR" 4 -.IX Item "-mgcc-abi" -Enables support for the old \s-1GCC\s0 version of the V850 \s-1ABI\s0. With this -version of the \s-1ABI\s0 the following rules apply: .RS 4 -.IP "*" 4 -Integer sized structures and unions are returned in register \f(CW\*(C`r10\*(C'\fR. -.IP "*" 4 -Large structures and unions (more than 8 bytes in size) are passed by -reference. -.IP "*" 4 -Functions are aligned to 32\-bit boundaries, unless optimizing for -size. -.IP "*" 4 -The \fB\-m8byte\-align\fR command line option is not supported. -.IP "*" 4 -The \fB\-mdisable\-callt\fR command line option is supported but not -enabled by default. .RE -.RS 4 +.IP "\fB\-mmemcpy\-strategy=\fR\fIstrategy\fR" 4 +.IX Item "-mmemcpy-strategy=strategy" +Override the internal decision heuristic to decide if \f(CW\*(C`_\|_builtin_memcpy\*(C'\fR +should be inlined and what inline algorithm to use when the expected size +of the copy operation is known. \fIstrategy\fR +is a comma-separated list of \fIalg\fR:\fImax_size\fR:\fIdest_align\fR triplets. +\&\fIalg\fR is specified in \fB\-mstringop\-strategy\fR, \fImax_size\fR specifies +the max byte size with which inline algorithm \fIalg\fR is allowed. For the last +triplet, the \fImax_size\fR must be \f(CW\*(C`\-1\*(C'\fR. The \fImax_size\fR of the triplets +in the list must be specified in increasing order. The minimal byte size for +\&\fIalg\fR is \f(CW0\fR for the first triplet and \f(CW\*(C`\f(CImax_size\f(CW + 1\*(C'\fR of the +preceding range. +.IP "\fB\-mmemset\-strategy=\fR\fIstrategy\fR" 4 +.IX Item "-mmemset-strategy=strategy" +The option is similar to \fB\-mmemcpy\-strategy=\fR except that it is to control +\&\f(CW\*(C`_\|_builtin_memset\*(C'\fR expansion. +.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 +.IX Item "-momit-leaf-frame-pointer" +Don't keep the frame pointer in a register for leaf functions. This +avoids the instructions to save, set up, and restore frame pointers and +makes an extra register available in leaf functions. The option +\&\fB\-fomit\-leaf\-frame\-pointer\fR removes the frame pointer for leaf functions, +which might make debugging harder. +.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4 +.IX Item "-mtls-direct-seg-refs" +.PD 0 +.IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4 +.IX Item "-mno-tls-direct-seg-refs" +.PD +Controls whether \s-1TLS\s0 variables may be accessed with offsets from the +\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit), +or whether the thread base pointer must be added. Whether or not this +is valid depends on the operating system, and whether it maps the +segment to cover the entire \s-1TLS\s0 area. .Sp -When this version of the \s-1ABI\s0 is enabled the C preprocessor symbol -\&\f(CW\*(C`_\|_V850_GCC_ABI_\|_\*(C'\fR is defined. -.RE -.IP "\fB\-m8byte\-align\fR" 4 -.IX Item "-m8byte-align" +For systems that use the \s-1GNU C\s0 Library, the default is on. +.IP "\fB\-msse2avx\fR" 4 +.IX Item "-msse2avx" .PD 0 -.IP "\fB\-mno\-8byte\-align\fR" 4 -.IX Item "-mno-8byte-align" +.IP "\fB\-mno\-sse2avx\fR" 4 +.IX Item "-mno-sse2avx" .PD -Enables support for \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long long\*(C'\fR types to be -aligned on 8\-byte boundaries. The default is to restrict the -alignment of all objects to at most 4\-bytes. When -\&\fB\-m8byte\-align\fR is in effect the C preprocessor symbol -\&\f(CW\*(C`_\|_V850_8BYTE_ALIGN_\|_\*(C'\fR is defined. -.IP "\fB\-mbig\-switch\fR" 4 -.IX Item "-mbig-switch" -Generate code suitable for big switch tables. Use this option only if -the assembler/linker complain about out of range branches within a switch -table. -.IP "\fB\-mapp\-regs\fR" 4 -.IX Item "-mapp-regs" -This option causes r2 and r5 to be used in the code generated by -the compiler. This setting is the default. -.IP "\fB\-mno\-app\-regs\fR" 4 -.IX Item "-mno-app-regs" -This option causes r2 and r5 to be treated as fixed registers. -.PP -\fI\s-1VAX\s0 Options\fR -.IX Subsection "VAX Options" -.PP -These \fB\-m\fR options are defined for the \s-1VAX:\s0 -.IP "\fB\-munix\fR" 4 -.IX Item "-munix" -Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on) -that the Unix assembler for the \s-1VAX\s0 cannot handle across long -ranges. -.IP "\fB\-mgnu\fR" 4 -.IX Item "-mgnu" -Do output those jump instructions, on the assumption that the -\&\s-1GNU\s0 assembler is being used. -.IP "\fB\-mg\fR" 4 -.IX Item "-mg" -Output code for G\-format floating-point numbers instead of D\-format. -.PP -\fIVisium Options\fR -.IX Subsection "Visium Options" -.IP "\fB\-mdebug\fR" 4 -.IX Item "-mdebug" -A program which performs file I/O and is destined to run on an \s-1MCM\s0 target -should be linked with this option. It causes the libraries libc.a and -libdebug.a to be linked. The program should be run on the target under -the control of the \s-1GDB\s0 remote debugging stub. -.IP "\fB\-msim\fR" 4 -.IX Item "-msim" -A program which performs file I/O and is destined to run on the simulator -should be linked with option. This causes libraries libc.a and libsim.a to -be linked. -.IP "\fB\-mfpu\fR" 4 -.IX Item "-mfpu" +Specify that the assembler should encode \s-1SSE\s0 instructions with \s-1VEX\s0 +prefix. The option \fB\-mavx\fR turns this on by default. +.IP "\fB\-mfentry\fR" 4 +.IX Item "-mfentry" .PD 0 -.IP "\fB\-mhard\-float\fR" 4 -.IX Item "-mhard-float" +.IP "\fB\-mno\-fentry\fR" 4 +.IX Item "-mno-fentry" +.PD +If profiling is active (\fB\-pg\fR), put the profiling +counter call before the prologue. +Note: On x86 architectures the attribute \f(CW\*(C`ms_hook_prologue\*(C'\fR +isn't possible at the moment for \fB\-mfentry\fR and \fB\-pg\fR. +.IP "\fB\-mrecord\-mcount\fR" 4 +.IX Item "-mrecord-mcount" +.PD 0 +.IP "\fB\-mno\-record\-mcount\fR" 4 +.IX Item "-mno-record-mcount" +.PD +If profiling is active (\fB\-pg\fR), generate a _\|_mcount_loc section +that contains pointers to each profiling call. This is useful for +automatically patching and out calls. +.IP "\fB\-mnop\-mcount\fR" 4 +.IX Item "-mnop-mcount" +.PD 0 +.IP "\fB\-mno\-nop\-mcount\fR" 4 +.IX Item "-mno-nop-mcount" .PD -Generate code containing floating-point instructions. This is the -default. -.IP "\fB\-mno\-fpu\fR" 4 -.IX Item "-mno-fpu" +If profiling is active (\fB\-pg\fR), generate the calls to +the profiling functions as nops. This is useful when they +should be patched in later dynamically. This is likely only +useful together with \fB\-mrecord\-mcount\fR. +.IP "\fB\-mskip\-rax\-setup\fR" 4 +.IX Item "-mskip-rax-setup" .PD 0 -.IP "\fB\-msoft\-float\fR" 4 -.IX Item "-msoft-float" +.IP "\fB\-mno\-skip\-rax\-setup\fR" 4 +.IX Item "-mno-skip-rax-setup" .PD -Generate code containing library calls for floating-point. +When generating code for the x86\-64 architecture with \s-1SSE\s0 extensions +disabled, \fB\-skip\-rax\-setup\fR can be used to skip setting up \s-1RAX\s0 +register when there are no variable arguments passed in vector registers. .Sp -\&\fB\-msoft\-float\fR changes the calling convention in the output file; -therefore, it is only useful if you compile \fIall\fR of a program with -this option. In particular, you need to compile \fIlibgcc.a\fR, the -library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for -this to work. -.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 -.IX Item "-mcpu=cpu_type" -Set the instruction set, register set, and instruction scheduling parameters -for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are -\&\fBmcm\fR, \fBgr5\fR and \fBgr6\fR. +\&\fBWarning:\fR Since \s-1RAX\s0 register is used to avoid unnecessarily +saving vector registers on stack when passing variable arguments, the +impacts of this option are callees may waste some stack space, +misbehave or jump to a random location. \s-1GCC 4.4\s0 or newer don't have +those issues, regardless the \s-1RAX\s0 register value. +.IP "\fB\-m8bit\-idiv\fR" 4 +.IX Item "-m8bit-idiv" +.PD 0 +.IP "\fB\-mno\-8bit\-idiv\fR" 4 +.IX Item "-mno-8bit-idiv" +.PD +On some processors, like Intel Atom, 8\-bit unsigned integer divide is +much faster than 32\-bit/64\-bit integer divide. This option generates a +run-time check. If both dividend and divisor are within range of 0 +to 255, 8\-bit unsigned integer divide is used instead of +32\-bit/64\-bit integer divide. +.IP "\fB\-mavx256\-split\-unaligned\-load\fR" 4 +.IX Item "-mavx256-split-unaligned-load" +.PD 0 +.IP "\fB\-mavx256\-split\-unaligned\-store\fR" 4 +.IX Item "-mavx256-split-unaligned-store" +.PD +Split 32\-byte \s-1AVX\s0 unaligned load and store. +.IP "\fB\-mstack\-protector\-guard=\fR\fIguard\fR" 4 +.IX Item "-mstack-protector-guard=guard" +Generate stack protection code using canary at \fIguard\fR. Supported +locations are \fBglobal\fR for global canary or \fBtls\fR for per-thread +canary in the \s-1TLS\s0 block (the default). This option has effect only when +\&\fB\-fstack\-protector\fR or \fB\-fstack\-protector\-all\fR is specified. +.PP +These \fB\-m\fR switches are supported in addition to the above +on x86\-64 processors in 64\-bit environments. +.IP "\fB\-m32\fR" 4 +.IX Item "-m32" +.PD 0 +.IP "\fB\-m64\fR" 4 +.IX Item "-m64" +.IP "\fB\-mx32\fR" 4 +.IX Item "-mx32" +.IP "\fB\-m16\fR" 4 +.IX Item "-m16" +.PD +Generate code for a 16\-bit, 32\-bit or 64\-bit environment. +The \fB\-m32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types +to 32 bits, and +generates code that runs on any i386 system. .Sp -\&\fBmcm\fR is a synonym of \fBgr5\fR present for backward compatibility. +The \fB\-m64\fR option sets \f(CW\*(C`int\*(C'\fR to 32 bits and \f(CW\*(C`long\*(C'\fR and pointer +types to 64 bits, and generates code for the x86\-64 architecture. +For Darwin only the \fB\-m64\fR option also turns off the \fB\-fno\-pic\fR +and \fB\-mdynamic\-no\-pic\fR options. .Sp -By default (unless configured otherwise), \s-1GCC\s0 generates code for the \s-1GR5\s0 -variant of the Visium architecture. +The \fB\-mx32\fR option sets \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, and pointer types +to 32 bits, and +generates code for the x86\-64 architecture. .Sp -With \fB\-mcpu=gr6\fR, \s-1GCC\s0 generates code for the \s-1GR6\s0 variant of the Visium -architecture. The only difference from \s-1GR5\s0 code is that the compiler will -generate block move instructions. -.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 -.IX Item "-mtune=cpu_type" -Set the instruction scheduling parameters for machine type \fIcpu_type\fR, -but do not set the instruction set or register set that the option -\&\fB\-mcpu=\fR\fIcpu_type\fR would. -.IP "\fB\-msv\-mode\fR" 4 -.IX Item "-msv-mode" -Generate code for the supervisor mode, where there are no restrictions on -the access to general registers. This is the default. -.IP "\fB\-muser\-mode\fR" 4 -.IX Item "-muser-mode" -Generate code for the user mode, where the access to some general registers -is forbidden: on the \s-1GR5\s0, registers r24 to r31 cannot be accessed in this -mode; on the \s-1GR6\s0, only registers r29 to r31 are affected. -.PP -\fI\s-1VMS\s0 Options\fR -.IX Subsection "VMS Options" -.PP -These \fB\-m\fR options are defined for the \s-1VMS\s0 implementations: -.IP "\fB\-mvms\-return\-codes\fR" 4 -.IX Item "-mvms-return-codes" -Return \s-1VMS\s0 condition codes from \f(CW\*(C`main\*(C'\fR. The default is to return POSIX-style -condition (e.g. error) codes. -.IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 -.IX Item "-mdebug-main=prefix" -Flag the first routine whose name starts with \fIprefix\fR as the main -routine for the debugger. -.IP "\fB\-mmalloc64\fR" 4 -.IX Item "-mmalloc64" -Default to 64\-bit memory allocation routines. -.IP "\fB\-mpointer\-size=\fR\fIsize\fR" 4 -.IX Item "-mpointer-size=size" -Set the default size of pointers. Possible options for \fIsize\fR are -\&\fB32\fR or \fBshort\fR for 32 bit pointers, \fB64\fR or \fBlong\fR -for 64 bit pointers, and \fBno\fR for supporting only 32 bit pointers. -The later option disables \f(CW\*(C`pragma pointer_size\*(C'\fR. -.PP -\fIVxWorks Options\fR -.IX Subsection "VxWorks Options" +The \fB\-m16\fR option is the same as \fB\-m32\fR, except for that +it outputs the \f(CW\*(C`.code16gcc\*(C'\fR assembly directive at the beginning of +the assembly output so that the binary can run in 16\-bit mode. +.IP "\fB\-mno\-red\-zone\fR" 4 +.IX Item "-mno-red-zone" +Do not use a so-called \*(L"red zone\*(R" for x86\-64 code. The red zone is mandated +by the x86\-64 \s-1ABI\s0; it is a 128\-byte area beyond the location of the +stack pointer that is not modified by signal or interrupt handlers +and therefore can be used for temporary data without adjusting the stack +pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone. +.IP "\fB\-mcmodel=small\fR" 4 +.IX Item "-mcmodel=small" +Generate code for the small code model: the program and its symbols must +be linked in the lower 2 \s-1GB\s0 of the address space. Pointers are 64 bits. +Programs can be statically or dynamically linked. This is the default +code model. +.IP "\fB\-mcmodel=kernel\fR" 4 +.IX Item "-mcmodel=kernel" +Generate code for the kernel code model. The kernel runs in the +negative 2 \s-1GB\s0 of the address space. +This model has to be used for Linux kernel code. +.IP "\fB\-mcmodel=medium\fR" 4 +.IX Item "-mcmodel=medium" +Generate code for the medium model: the program is linked in the lower 2 +\&\s-1GB\s0 of the address space. Small symbols are also placed there. Symbols +with sizes larger than \fB\-mlarge\-data\-threshold\fR are put into +large data or \s-1BSS\s0 sections and can be located above 2GB. Programs can +be statically or dynamically linked. +.IP "\fB\-mcmodel=large\fR" 4 +.IX Item "-mcmodel=large" +Generate code for the large model. This model makes no assumptions +about addresses and sizes of sections. +.IP "\fB\-maddress\-mode=long\fR" 4 +.IX Item "-maddress-mode=long" +Generate code for long address mode. This is only supported for 64\-bit +and x32 environments. It is the default address mode for 64\-bit +environments. +.IP "\fB\-maddress\-mode=short\fR" 4 +.IX Item "-maddress-mode=short" +Generate code for short address mode. This is only supported for 32\-bit +and x32 environments. It is the default address mode for 32\-bit and +x32 environments. .PP -The options in this section are defined for all VxWorks targets. -Options specific to the target hardware are listed with the other -options for that target. -.IP "\fB\-mrtp\fR" 4 -.IX Item "-mrtp" -\&\s-1GCC\s0 can generate code for both VxWorks kernels and real time processes -(RTPs). This option switches from the former to the latter. It also -defines the preprocessor macro \f(CW\*(C`_\|_RTP_\|_\*(C'\fR. -.IP "\fB\-non\-static\fR" 4 -.IX Item "-non-static" -Link an \s-1RTP\s0 executable against shared libraries rather than static -libraries. The options \fB\-static\fR and \fB\-shared\fR can -also be used for RTPs; \fB\-static\fR -is the default. -.IP "\fB\-Bstatic\fR" 4 -.IX Item "-Bstatic" -.PD 0 -.IP "\fB\-Bdynamic\fR" 4 -.IX Item "-Bdynamic" -.PD -These options are passed down to the linker. They are defined for -compatibility with Diab. -.IP "\fB\-Xbind\-lazy\fR" 4 -.IX Item "-Xbind-lazy" -Enable lazy binding of function calls. This option is equivalent to -\&\fB\-Wl,\-z,now\fR and is defined for compatibility with Diab. -.IP "\fB\-Xbind\-now\fR" 4 -.IX Item "-Xbind-now" -Disable lazy binding of function calls. This option is the default and -is defined for compatibility with Diab. +\fIx86 Windows Options\fR +.IX Subsection "x86 Windows Options" .PP -\fIx86\-64 Options\fR -.IX Subsection "x86-64 Options" +These additional options are available for Microsoft Windows targets: +.IP "\fB\-mconsole\fR" 4 +.IX Item "-mconsole" +This option +specifies that a console application is to be generated, by +instructing the linker to set the \s-1PE\s0 header subsystem type +required for console applications. +This option is available for Cygwin and MinGW targets and is +enabled by default on those targets. +.IP "\fB\-mdll\fR" 4 +.IX Item "-mdll" +This option is available for Cygwin and MinGW targets. It +specifies that a DLL\-\-\-a dynamic link library\-\-\-is to be +generated, enabling the selection of the required runtime +startup object and entry point. +.IP "\fB\-mnop\-fun\-dllimport\fR" 4 +.IX Item "-mnop-fun-dllimport" +This option is available for Cygwin and MinGW targets. It +specifies that the \f(CW\*(C`dllimport\*(C'\fR attribute should be ignored. +.IP "\fB\-mthread\fR" 4 +.IX Item "-mthread" +This option is available for MinGW targets. It specifies +that MinGW-specific thread support is to be used. +.IP "\fB\-municode\fR" 4 +.IX Item "-municode" +This option is available for MinGW\-w64 targets. It causes +the \f(CW\*(C`UNICODE\*(C'\fR preprocessor macro to be predefined, and +chooses Unicode-capable runtime startup code. +.IP "\fB\-mwin32\fR" 4 +.IX Item "-mwin32" +This option is available for Cygwin and MinGW targets. It +specifies that the typical Microsoft Windows predefined macros are to +be set in the pre-processor, but does not influence the choice +of runtime library/startup code. +.IP "\fB\-mwindows\fR" 4 +.IX Item "-mwindows" +This option is available for Cygwin and MinGW targets. It +specifies that a \s-1GUI\s0 application is to be generated by +instructing the linker to set the \s-1PE\s0 header subsystem type +appropriately. +.IP "\fB\-fno\-set\-stack\-executable\fR" 4 +.IX Item "-fno-set-stack-executable" +This option is available for MinGW targets. It specifies that +the executable flag for the stack used by nested functions isn't +set. This is necessary for binaries running in kernel mode of +Microsoft Windows, as there the User32 \s-1API,\s0 which is used to set executable +privileges, isn't available. +.IP "\fB\-fwritable\-relocated\-rdata\fR" 4 +.IX Item "-fwritable-relocated-rdata" +This option is available for MinGW and Cygwin targets. It specifies +that relocated-data in read-only section is put into .data +section. This is a necessary for older runtimes not supporting +modification of .rdata sections for pseudo-relocation. +.IP "\fB\-mpe\-aligned\-commons\fR" 4 +.IX Item "-mpe-aligned-commons" +This option is available for Cygwin and MinGW targets. It +specifies that the \s-1GNU\s0 extension to the \s-1PE\s0 file format that +permits the correct alignment of \s-1COMMON\s0 variables should be +used when generating code. It is enabled by default if +\&\s-1GCC\s0 detects that the target assembler found during configuration +supports the feature. .PP -These are listed under +See also under \fBx86 Options\fR for standard options. .PP \fIXstormy16 Options\fR .IX Subsection "Xstormy16 Options" @@ -21479,7 +21791,7 @@ kernel code. These options control the treatment of literal pools. The default is \&\fB\-mno\-text\-section\-literals\fR, which places literals in a separate section in the output file. This allows the literal pool to be placed -in a data \s-1RAM/ROM\s0, and it also allows the linker to combine literal +in a data \s-1RAM/ROM,\s0 and it also allows the linker to combine literal pools from separate object files to remove redundant literals and improve code size. With \fB\-mtext\-section\-literals\fR, the literals are interspersed in the text section in order to keep them as close as @@ -21664,7 +21976,7 @@ You normally do not need to enable this option; instead, a language processor that needs this handling enables it on your behalf. .IP "\fB\-fasynchronous\-unwind\-tables\fR" 4 .IX Item "-fasynchronous-unwind-tables" -Generate unwind table in \s-1DWARF\s0 2 format, if supported by target machine. The +Generate unwind table in \s-1DWARF 2\s0 format, if supported by target machine. The table is exact at each instruction boundary, so it can be used for stack unwinding from asynchronous events (such as debugger or garbage collector). .IP "\fB\-fno\-gnu\-unique\fR" 4 @@ -21735,7 +22047,7 @@ Use it to conform to a non-default application binary interface. .IX Item "-fshort-wchar" Override the underlying type for \f(CW\*(C`wchar_t\*(C'\fR to be \f(CW\*(C`short unsigned int\*(C'\fR instead of the default for the target. This option is -useful for building programs to run under \s-1WINE\s0. +useful for building programs to run under \s-1WINE.\s0 .Sp \&\fBWarning:\fR the \fB\-fshort\-wchar\fR switch causes \s-1GCC\s0 to generate code that is not binary compatible with code generated without that switch. @@ -21748,7 +22060,7 @@ such variables in different compilation units by placing the variables in a common block. This is the behavior specified by \fB\-fcommon\fR, and is the default for \s-1GCC\s0 on most targets. -On the other hand, this behavior is not required by \s-1ISO\s0 C, and on some +On the other hand, this behavior is not required by \s-1ISO C,\s0 and on some targets may carry a speed or code size penalty on variable references. The \fB\-fno\-common\fR option specifies that the compiler should place uninitialized global variables in the data section of the object file, @@ -21804,11 +22116,11 @@ the \s-1GOT\s0 size for the linked executable exceeds a machine-specific maximum size, you get an error message from the linker indicating that \&\fB\-fpic\fR does not work; in that case, recompile with \fB\-fPIC\fR instead. (These maximums are 8k on the \s-1SPARC\s0 and 32k -on the m68k and \s-1RS/6000\s0. The 386 has no such limit.) +on the m68k and \s-1RS/6000. \s0 The x86 has no such limit.) .Sp Position-independent code requires special support, and therefore works -only on certain machines. For the 386, \s-1GCC\s0 supports \s-1PIC\s0 for System V -but not for the Sun 386i. Code generated for the \s-1IBM\s0 \s-1RS/6000\s0 is always +only on certain machines. For the x86, \s-1GCC\s0 supports \s-1PIC\s0 for System V +but not for the Sun 386i. Code generated for the \s-1IBM RS/6000\s0 is always position-independent. .Sp When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR @@ -21818,7 +22130,7 @@ are defined to 1. If supported for the target machine, emit position-independent code, suitable for dynamic linking and avoiding any limit on the size of the global offset table. This option makes a difference on the m68k, -PowerPC and \s-1SPARC\s0. +PowerPC and \s-1SPARC.\s0 .Sp Position-independent code requires special support, and therefore works only on certain machines. @@ -21968,7 +22280,7 @@ name, such as \f(CW\*(C`vector blah(const vector &)\*(C'\fR, not the internal mangled name (e.g., \f(CW\*(C`_Z4blahRSt6vectorIiSaIiEE\*(C'\fR). The match is done on substrings: if the \fIsym\fR parameter is a substring of the function name, it is considered to be a match. For C99 and \*(C+ -extended identifiers, the function name must be given in \s-1UTF\-8\s0, not +extended identifiers, the function name must be given in \s-1UTF\-8,\s0 not using universal character names. .IP "\fB\-fstack\-check\fR" 4 .IX Item "-fstack-check" @@ -22035,7 +22347,7 @@ The resulting program has a discontiguous stack which can only overflow if the program is unable to allocate any more memory. This is most useful when running threaded programs, as it is no longer necessary to calculate a good stack size to use for each thread. This -is currently only implemented for the i386 and x86_64 back ends running +is currently only implemented for the x86 targets running GNU/Linux. .Sp When code compiled with \fB\-fsplit\-stack\fR calls code compiled @@ -22082,14 +22394,12 @@ available to be linked against from outside the shared object. \&\fBprotected\fR and \fBinternal\fR are pretty useless in real-world usage so the only other commonly used option is \fBhidden\fR. The default if \fB\-fvisibility\fR isn't specified is -\&\fBdefault\fR, i.e., make every -symbol public\-\-\-this causes the same behavior as previous versions of -\&\s-1GCC\s0. +\&\fBdefault\fR, i.e., make every symbol public. .Sp A good explanation of the benefits offered by ensuring \s-1ELF\s0 symbols have the correct visibility is given by \*(L"How To Write Shared Libraries\*(R" by Ulrich Drepper (which can be found at -<\fBhttp://people.redhat.com/~drepper/\fR>)\-\-\-however a superior +<\fBhttp://www.akkadia.org/drepper/\fR>)\-\-\-however a superior solution made possible by this option to marking things hidden when the default is public is to make the default hidden and mark things public. This is the norm with DLLs on Windows and with \fB\-fvisibility=hidden\fR @@ -22109,7 +22419,7 @@ always specify visibility when it is not the default; i.e., declarations only for use within the local \s-1DSO\s0 should \fBalways\fR be marked explicitly as hidden as so to avoid \s-1PLT\s0 indirection overheads\-\-\-making this abundantly clear also aids readability and self-documentation of the code. -Note that due to \s-1ISO\s0 \*(C+ specification requirements, \f(CW\*(C`operator new\*(C'\fR and +Note that due to \s-1ISO \*(C+\s0 specification requirements, \f(CW\*(C`operator new\*(C'\fR and \&\f(CW\*(C`operator delete\*(C'\fR must always be of default visibility. .Sp Be aware that headers from outside your project, in particular system @@ -22121,7 +22431,7 @@ before including any such headers. \&\f(CW\*(C`extern\*(C'\fR declarations are not affected by \fB\-fvisibility\fR, so a lot of code can be recompiled with \fB\-fvisibility=hidden\fR with no modifications. However, this means that calls to \f(CW\*(C`extern\*(C'\fR -functions with no explicit visibility use the \s-1PLT\s0, so it is more +functions with no explicit visibility use the \s-1PLT,\s0 so it is more effective to use \f(CW\*(C`_\|_attribute ((visibility))\*(C'\fR and/or \&\f(CW\*(C`#pragma GCC visibility\*(C'\fR to tell the compiler which \f(CW\*(C`extern\*(C'\fR declarations should be treated as hidden. @@ -22183,7 +22493,7 @@ aspects of the compilation environment. Note that you can also specify places to search using options such as \&\fB\-B\fR, \fB\-I\fR and \fB\-L\fR. These take precedence over places specified using environment variables, which -in turn take precedence over those specified by the configuration of \s-1GCC\s0. +in turn take precedence over those specified by the configuration of \s-1GCC.\s0 .IP "\fB\s-1LANG\s0\fR" 4 .IX Item "LANG" .PD 0 @@ -22200,7 +22510,7 @@ national conventions. \s-1GCC\s0 inspects the locale categories \&\fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR if it has been configured to do so. These locale categories can be set to any value supported by your installation. A typical value is \fBen_GB.UTF\-8\fR for English in the United -Kingdom encoded in \s-1UTF\-8\s0. +Kingdom encoded in \s-1UTF\-8.\s0 .Sp The \fB\s-1LC_CTYPE\s0\fR environment variable specifies character classification. \s-1GCC\s0 uses it to determine the character boundaries in @@ -22380,7 +22690,7 @@ and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIas\fR, .IX Header "AUTHOR" See the Info entry for \fBgcc\fR, or <\fBhttp://gcc.gnu.org/onlinedocs/gcc/Contributors.html\fR>, -for contributors to \s-1GCC\s0. +for contributors to \s-1GCC.\s0 .SH "COPYRIGHT" .IX Header "COPYRIGHT" Copyright (c) 1988\-2015 Free Software Foundation, Inc. diff --git a/gnu/usr.bin/cc50/drivers/cpp/Makefile b/gnu/usr.bin/cc50/drivers/cpp/Makefile index aeb41d25a6..97e34f7267 100644 --- a/gnu/usr.bin/cc50/drivers/cpp/Makefile +++ b/gnu/usr.bin/cc50/drivers/cpp/Makefile @@ -12,7 +12,7 @@ CFLAGS+= -DCONFIGURE_SPECS="\"\"" \ -DACCEL_DIR_SUFFIX="\"\"" \ -DDEFAULT_REAL_TARGET_MACHINE="\"${target_machine}\"" -DOC_Release= ${GCCDIR}/gcc/doc/cpp.1 +DOC_Release= cpp.1 #${GCCDIR}/gcc/doc/cpp.1 DOC_Snapshot= cpp.1 ${MFILE}: ${DOC_${GCCRELEASE}} diff --git a/gnu/usr.bin/cc50/drivers/cpp/cpp.1 b/gnu/usr.bin/cc50/drivers/cpp/cpp.1 index a1c8ef372d..33a9702c23 100644 --- a/gnu/usr.bin/cc50/drivers/cpp/cpp.1 +++ b/gnu/usr.bin/cc50/drivers/cpp/cpp.1 @@ -1,4 +1,4 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.20) +.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.29) .\" .\" Standard preamble: .\" ======================================================================== @@ -38,6 +38,8 @@ . ds PI \(*p . ds L" `` . ds R" '' +. ds C` +. ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. @@ -48,17 +50,24 @@ .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. -.ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX .. -. nr % 0 -. rr F -.\} -.el \{\ -. de IX +.nr rF 0 +.if \n(.g .if rF .nr rF 1 +.if (\n(rF:(\n(.g==0)) \{ +. if \nF \{ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. +. if !\nF==2 \{ +. nr % 0 +. nr F 2 +. \} +. \} .\} +.rr rF .\" .\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). .\" Fear. Run. Save yourself. No user-serviceable parts. @@ -124,7 +133,7 @@ .\" ======================================================================== .\" .IX Title "CPP 1" -.TH CPP 1 "2015-01-11" "gcc-5.0.0" "GNU" +.TH CPP 1 "2015-04-12" "gcc-5.0.1" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -172,11 +181,11 @@ Wherever possible, you should use a preprocessor geared to the language you are writing in. Modern versions of the \s-1GNU\s0 assembler have macro facilities. Most high level programming languages have their own conditional compilation and inclusion mechanism. If all else fails, -try a true general text processor, such as \s-1GNU\s0 M4. +try a true general text processor, such as \s-1GNU M4.\s0 .PP -C preprocessors vary in some details. This manual discusses the \s-1GNU\s0 C +C preprocessors vary in some details. This manual discusses the \s-1GNU C\s0 preprocessor, which provides a small superset of the features of \s-1ISO\s0 -Standard C. In its default mode, the \s-1GNU\s0 C preprocessor does not do a +Standard C. In its default mode, the \s-1GNU C\s0 preprocessor does not do a few things required by the standard. These are features which are rarely, if ever, used, and may cause surprising changes to the meaning of a program which does not expect them. To get strict \s-1ISO\s0 Standard C, @@ -193,7 +202,7 @@ differences that do exist are detailed in the section \fBTraditional Mode\fR. .PP For clarity, unless noted otherwise, references to \fB\s-1CPP\s0\fR in this -manual refer to \s-1GNU\s0 \s-1CPP\s0. +manual refer to \s-1GNU CPP.\s0 .SH "OPTIONS" .IX Header "OPTIONS" The C preprocessor expects two file names as arguments, \fIinfile\fR and @@ -297,7 +306,7 @@ get trigraph conversion without warnings, but get the other .IP "\fB\-Wtraditional\fR" 4 .IX Item "-Wtraditional" Warn about certain constructs that behave differently in traditional and -\&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C +\&\s-1ISO C. \s0 Also warn about \s-1ISO C\s0 constructs that have no traditional C equivalent, and problematic constructs which should be avoided. .IP "\fB\-Wundef\fR" 4 .IX Item "-Wundef" @@ -350,7 +359,7 @@ in finding bugs in your own code, therefore suppressed. If you are responsible for the system library, you may want to see them. .IP "\fB\-w\fR" 4 .IX Item "-w" -Suppress all warnings, including those which \s-1GNU\s0 \s-1CPP\s0 issues by default. +Suppress all warnings, including those which \s-1GNU CPP\s0 issues by default. .IP "\fB\-pedantic\fR" 4 .IX Item "-pedantic" Issue all the mandatory diagnostics listed in the C standard. Some of @@ -368,7 +377,7 @@ suitable for \fBmake\fR describing the dependencies of the main source file. The preprocessor outputs one \fBmake\fR rule containing the object file name for that source file, a colon, and the names of all the included files, including those coming from \fB\-include\fR or -\&\fB\-imacros\fR command line options. +\&\fB\-imacros\fR command-line options. .Sp Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the object file name consists of the name of the source file with any @@ -522,7 +531,7 @@ may be one of: .el .IP "\f(CWiso9899:1990\fR" 4 .IX Item "iso9899:1990" .PD -The \s-1ISO\s0 C standard from 1990. \fBc90\fR is the customary shorthand for +The \s-1ISO C\s0 standard from 1990. \fBc90\fR is the customary shorthand for this version of the standard. .Sp The \fB\-ansi\fR option is equivalent to \fB\-std=c90\fR. @@ -544,7 +553,7 @@ The 1990 C standard, as amended in 1994. .el .IP "\f(CWc9x\fR" 4 .IX Item "c9x" .PD -The revised \s-1ISO\s0 C standard, published in December 1999. Before +The revised \s-1ISO C\s0 standard, published in December 1999. Before publication, this was known as C9X. .ie n .IP """iso9899:2011""" 4 .el .IP "\f(CWiso9899:2011\fR" 4 @@ -557,7 +566,7 @@ publication, this was known as C9X. .el .IP "\f(CWc1x\fR" 4 .IX Item "c1x" .PD -The revised \s-1ISO\s0 C standard, published in December 2011. Before +The revised \s-1ISO C\s0 standard, published in December 2011. Before publication, this was known as C1X. .ie n .IP """gnu90""" 4 .el .IP "\f(CWgnu90\fR" 4 @@ -589,7 +598,7 @@ The 2011 C standard plus \s-1GNU\s0 extensions. .ie n .IP """c++98""" 4 .el .IP "\f(CWc++98\fR" 4 .IX Item "c++98" -The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. +The 1998 \s-1ISO \*(C+\s0 standard plus amendments. .ie n .IP """gnu++98""" 4 .el .IP "\f(CWgnu++98\fR" 4 .IX Item "gnu++98" @@ -744,7 +753,7 @@ line. If the value is less than 1 or greater than 100, the option is ignored. The default is 8. .IP "\fB\-fdebug\-cpp\fR" 4 .IX Item "-fdebug-cpp" -This option is only useful for debugging \s-1GCC\s0. When used with +This option is only useful for debugging \s-1GCC. \s0 When used with \&\fB\-E\fR, dumps debugging information about location maps. Every token in the output is preceded by the dump of the map its location belongs to. The dump of the map holding the location of a token would @@ -777,12 +786,12 @@ Note that \f(CW\*(C`\-ftrack\-macro\-expansion=2\*(C'\fR is activated by default .IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 .IX Item "-fexec-charset=charset" Set the execution character set, used for string and character -constants. The default is \s-1UTF\-8\s0. \fIcharset\fR can be any encoding +constants. The default is \s-1UTF\-8. \s0\fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. .IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 .IX Item "-fwide-exec-charset=charset" Set the wide execution character set, used for wide string and -character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16\s0, whichever +character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16,\s0 whichever corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with \&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have @@ -790,10 +799,10 @@ problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. .IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 .IX Item "-finput-charset=charset" Set the input character set, used for translation from the character -set of the input file to the source character set used by \s-1GCC\s0. If the +set of the input file to the source character set used by \s-1GCC. \s0 If the locale does not specify, or \s-1GCC\s0 cannot get this information from the -locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale -or this command line option. Currently the command line option takes +locale, the default is \s-1UTF\-8. \s0 This can be overridden by either the locale +or this command-line option. Currently the command-line option takes precedence if there's a conflict. \fIcharset\fR can be any encoding supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. .IP "\fB\-fworking\-directory\fR" 4 @@ -829,7 +838,7 @@ Cancel an assertion with the predicate \fIpredicate\fR and answer .IX Item "-dCHARS" \&\fI\s-1CHARS\s0\fR is a sequence of one or more of the following characters, and must not be preceded by a space. Other characters are interpreted -by the compiler proper, or reserved for future versions of \s-1GCC\s0, and so +by the compiler proper, or reserved for future versions of \s-1GCC,\s0 and so are silently ignored. If you specify characters whose behavior conflicts, the result is undefined. .RS 4 @@ -905,7 +914,7 @@ The \fB\-CC\fR option is generally used to support lint comments. .IP "\fB\-traditional\-cpp\fR" 4 .IX Item "-traditional-cpp" Try to imitate the behavior of old-fashioned C preprocessors, as -opposed to \s-1ISO\s0 C preprocessors. +opposed to \s-1ISO C\s0 preprocessors. .IP "\fB\-trigraphs\fR" 4 .IX Item "-trigraphs" Process trigraph sequences. @@ -919,11 +928,11 @@ short file names, such as MS-DOS. .IP "\fB\-\-target\-help\fR" 4 .IX Item "--target-help" .PD -Print text describing all the command line options instead of +Print text describing all the command-line options instead of preprocessing anything. .IP "\fB\-v\fR" 4 .IX Item "-v" -Verbose mode. Print out \s-1GNU\s0 \s-1CPP\s0's version number at the beginning of +Verbose mode. Print out \s-1GNU CPP\s0's version number at the beginning of execution, and report the final form of the include path. .IP "\fB\-H\fR" 4 .IX Item "-H" @@ -938,7 +947,7 @@ header file is printed with \fB...x\fR and a valid one with \fB...!\fR . .IP "\fB\-\-version\fR" 4 .IX Item "--version" .PD -Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to +Print out \s-1GNU CPP\s0's version number. With one dash, proceed to preprocess as normal. With two dashes, exit immediately. .SH "ENVIRONMENT" .IX Header "ENVIRONMENT" @@ -950,7 +959,7 @@ Note that you can also specify places to search using options such as \&\fB\-I\fR, and control dependency output with options like \&\fB\-M\fR. These take precedence over environment variables, which in turn take precedence over the -configuration of \s-1GCC\s0. +configuration of \s-1GCC.\s0 .IP "\fB\s-1CPATH\s0\fR" 4 .IX Item "CPATH" .PD 0 diff --git a/gnu/usr.bin/cc50/drivers/gcov/Makefile b/gnu/usr.bin/cc50/drivers/gcov/Makefile index 2fdd8e9a89..25ab4ea8e2 100644 --- a/gnu/usr.bin/cc50/drivers/gcov/Makefile +++ b/gnu/usr.bin/cc50/drivers/gcov/Makefile @@ -8,7 +8,7 @@ MAN= ${MFILE} SRCS= gcov.c -DOC_Release= ${GCCDIR}/gcc/doc/gcov.1 +DOC_Release= gcov.1 #${GCCDIR}/gcc/doc/gcov.1 DOC_Snapshot= gcov.1 ${MFILE}: ${DOC_${GCCRELEASE}} diff --git a/gnu/usr.bin/cc50/drivers/gcov/gcov.1 b/gnu/usr.bin/cc50/drivers/gcov/gcov.1 index c7229c4aac..aeb065b1a0 100644 --- a/gnu/usr.bin/cc50/drivers/gcov/gcov.1 +++ b/gnu/usr.bin/cc50/drivers/gcov/gcov.1 @@ -1,4 +1,4 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.20) +.\" Automatically generated by Pod::Man 2.28 (Pod::Simple 3.29) .\" .\" Standard preamble: .\" ======================================================================== @@ -38,6 +38,8 @@ . ds PI \(*p . ds L" `` . ds R" '' +. ds C` +. ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. @@ -48,17 +50,24 @@ .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. -.ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +.\" +.\" Avoid warning from groff about undefined register 'F'. +.de IX .. -. nr % 0 -. rr F -.\} -.el \{\ -. de IX +.nr rF 0 +.if \n(.g .if rF .nr rF 1 +.if (\n(rF:(\n(.g==0)) \{ +. if \nF \{ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. +. if !\nF==2 \{ +. nr % 0 +. nr F 2 +. \} +. \} .\} +.rr rF .\" .\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). .\" Fear. Run. Save yourself. No user-serviceable parts. @@ -124,7 +133,7 @@ .\" ======================================================================== .\" .IX Title "GCOV 1" -.TH GCOV 1 "2015-01-11" "gcc-5.0.0" "GNU" +.TH GCOV 1 "2015-04-12" "gcc-5.0.1" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -201,7 +210,7 @@ in fine-tuning the performance of your programs. \fBgprof\fR gives timing information you can use along with the information you get from \&\fBgcov\fR. .PP -\&\fBgcov\fR works only on code compiled with \s-1GCC\s0. It is not +\&\fBgcov\fR works only on code compiled with \s-1GCC. \s0 It is not compatible with any other profiling or test coverage mechanism. .SH "OPTIONS" .IX Header "OPTIONS" -- 2.41.0