From 4f973f1fac4887dcb8059fe23173e529cbdae3fe Mon Sep 17 00:00:00 2001 From: Hasso Tepper Date: Fri, 31 Jul 2009 21:55:52 +0300 Subject: [PATCH] drm/radeon: add RV740 support Obtained-from: FreeBSD --- sys/dev/drm/drm_pciids.h | 5 +++++ sys/dev/drm/r600_cp.c | 35 ++++++++++++++++++++++++++++++++++- sys/dev/drm/radeon_drv.h | 1 + 3 files changed, 40 insertions(+), 1 deletion(-) diff --git a/sys/dev/drm/drm_pciids.h b/sys/dev/drm/drm_pciids.h index 06cd4a5eb8..2d6a015e16 100644 --- a/sys/dev/drm/drm_pciids.h +++ b/sys/dev/drm/drm_pciids.h @@ -257,6 +257,11 @@ {0x1002, 0x940A, CHIP_R600|RADEON_NEW_MEMMAP, "ATI FireGL V8650"}, \ {0x1002, 0x940B, CHIP_R600|RADEON_NEW_MEMMAP, "ATI FireGL V8600"}, \ {0x1002, 0x940F, CHIP_R600|RADEON_NEW_MEMMAP, "ATI FireGL V7600"}, \ + {0x1002, 0x94A0, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4830"}, \ + {0x1002, 0x94A1, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4850"}, \ + {0x1002, 0x94B1, CHIP_RV740|RADEON_NEW_MEMMAP, "ATI RV740"}, \ + {0x1002, 0x94B3, CHIP_RV740|RADEON_NEW_MEMMAP, "ATI Radeon HD 4770"}, \ + {0x1002, 0x94B5, CHIP_RV740|RADEON_NEW_MEMMAP, "ATI Radeon HD 4770"}, \ {0x1002, 0x94C0, CHIP_RV610|RADEON_NEW_MEMMAP, "RV610"}, \ {0x1002, 0x94C1, CHIP_RV610|RADEON_NEW_MEMMAP, "Radeon HD 2400 XT"}, \ {0x1002, 0x94C3, CHIP_RV610|RADEON_NEW_MEMMAP, "Radeon HD 2400 Pro"}, \ diff --git a/sys/dev/drm/r600_cp.c b/sys/dev/drm/r600_cp.c index f53a5fa6ed..e832af2f03 100644 --- a/sys/dev/drm/r600_cp.c +++ b/sys/dev/drm/r600_cp.c @@ -418,7 +418,8 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) cp = RV770_cp_microcode; break; case CHIP_RV730: - DRM_INFO("Loading RV730 Microcode\n"); + case CHIP_RV740: + DRM_INFO("Loading RV730/RV740 Microcode\n"); pfp = RV730_pfp_microcode; cp = RV730_cp_microcode; break; @@ -1241,6 +1242,31 @@ static void r700_gfx_init(struct drm_device *dev, dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; break; + case CHIP_RV740: + dev_priv->r600_max_pipes = 4; + dev_priv->r600_max_tile_pipes = 4; + dev_priv->r600_max_simds = 8; + dev_priv->r600_max_backends = 4; + dev_priv->r600_max_gprs = 256; + dev_priv->r600_max_threads = 248; + dev_priv->r600_max_stack_entries = 512; + dev_priv->r600_max_hw_contexts = 8; + dev_priv->r600_max_gs_threads = 16 * 2; + dev_priv->r600_sx_max_export_size = 256; + dev_priv->r600_sx_max_export_pos_size = 32; + dev_priv->r600_sx_max_export_smx_size = 224; + dev_priv->r600_sq_num_cf_insts = 2; + + dev_priv->r700_sx_num_of_sets = 7; + dev_priv->r700_sc_prim_fifo_size = 0x100; + dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; + dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; + + if (dev_priv->r600_sx_max_export_pos_size > 16) { + dev_priv->r600_sx_max_export_pos_size -= 16; + dev_priv->r600_sx_max_export_smx_size += 16; + } + break; case CHIP_RV730: dev_priv->r600_max_pipes = 2; dev_priv->r600_max_tile_pipes = 4; @@ -1260,6 +1286,11 @@ static void r700_gfx_init(struct drm_device *dev, dev_priv->r700_sc_prim_fifo_size = 0xf9; dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; + + if (dev_priv->r600_sx_max_export_pos_size > 16) { + dev_priv->r600_sx_max_export_pos_size -= 16; + dev_priv->r600_sx_max_export_smx_size += 16; + } break; case CHIP_RV710: dev_priv->r600_max_pipes = 2; @@ -1427,6 +1458,7 @@ static void r700_gfx_init(struct drm_device *dev, case CHIP_RV770: sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); break; + case CHIP_RV740: case CHIP_RV730: case CHIP_RV710: default: @@ -1504,6 +1536,7 @@ static void r700_gfx_init(struct drm_device *dev, switch (dev_priv->flags & RADEON_FAMILY_MASK) { case CHIP_RV770: + case CHIP_RV740: case CHIP_RV730: gs_prim_buffer_depth = 384; break; diff --git a/sys/dev/drm/radeon_drv.h b/sys/dev/drm/radeon_drv.h index 62c60b35c3..181b00eeff 100644 --- a/sys/dev/drm/radeon_drv.h +++ b/sys/dev/drm/radeon_drv.h @@ -143,6 +143,7 @@ enum radeon_family { CHIP_RV670, CHIP_RS780, CHIP_RV770, + CHIP_RV740, CHIP_RV730, CHIP_RV710, CHIP_LAST, -- 2.41.0