Update to gcc-3.4.6
[dragonfly.git] / contrib / gcc-3.4 / gcc / local-alloc.c
CommitLineData
003757ed
MD
1/* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 2, or (at your option) any later
10version.
11
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING. If not, write to the Free
19Software Foundation, 59 Temple Place - Suite 330, Boston, MA
2002111-1307, USA. */
21
22/* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
29
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
32
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
40
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
47
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
51
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
56 yet implemented. */
57
58/* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
61
62#include "config.h"
63#include "system.h"
64#include "coretypes.h"
65#include "tm.h"
66#include "hard-reg-set.h"
67#include "rtl.h"
68#include "tm_p.h"
69#include "flags.h"
70#include "basic-block.h"
71#include "regs.h"
72#include "function.h"
73#include "insn-config.h"
74#include "insn-attr.h"
75#include "recog.h"
76#include "output.h"
77#include "toplev.h"
78#include "except.h"
79#include "integrate.h"
80\f
81/* Next quantity number available for allocation. */
82
83static int next_qty;
84
85/* Information we maintain about each quantity. */
86struct qty
87{
88 /* The number of refs to quantity Q. */
89
90 int n_refs;
91
92 /* The frequency of uses of quantity Q. */
93
94 int freq;
95
96 /* Insn number (counting from head of basic block)
97 where quantity Q was born. -1 if birth has not been recorded. */
98
99 int birth;
100
101 /* Insn number (counting from head of basic block)
102 where given quantity died. Due to the way tying is done,
103 and the fact that we consider in this pass only regs that die but once,
104 a quantity can die only once. Each quantity's life span
105 is a set of consecutive insns. -1 if death has not been recorded. */
106
107 int death;
108
109 /* Number of words needed to hold the data in given quantity.
110 This depends on its machine mode. It is used for these purposes:
111 1. It is used in computing the relative importance of qtys,
112 which determines the order in which we look for regs for them.
113 2. It is used in rules that prevent tying several registers of
114 different sizes in a way that is geometrically impossible
115 (see combine_regs). */
116
117 int size;
118
119 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
120
121 int n_calls_crossed;
122
1378ea41
SS
123 /* Number of times a reg tied to given qty lives across a CALL_INSN
124 that might throw. */
125
126 int n_throwing_calls_crossed;
127
003757ed
MD
128 /* The register number of one pseudo register whose reg_qty value is Q.
129 This register should be the head of the chain
130 maintained in reg_next_in_qty. */
131
132 int first_reg;
133
134 /* Reg class contained in (smaller than) the preferred classes of all
135 the pseudo regs that are tied in given quantity.
136 This is the preferred class for allocating that quantity. */
137
138 enum reg_class min_class;
139
140 /* Register class within which we allocate given qty if we can't get
141 its preferred class. */
142
143 enum reg_class alternate_class;
144
145 /* This holds the mode of the registers that are tied to given qty,
146 or VOIDmode if registers with differing modes are tied together. */
147
148 enum machine_mode mode;
149
150 /* the hard reg number chosen for given quantity,
151 or -1 if none was found. */
152
153 short phys_reg;
154};
155
156static struct qty *qty;
157
158/* These fields are kept separately to speedup their clearing. */
159
160/* We maintain two hard register sets that indicate suggested hard registers
161 for each quantity. The first, phys_copy_sugg, contains hard registers
162 that are tied to the quantity by a simple copy. The second contains all
163 hard registers that are tied to the quantity via an arithmetic operation.
164
165 The former register set is given priority for allocation. This tends to
166 eliminate copy insns. */
167
168/* Element Q is a set of hard registers that are suggested for quantity Q by
169 copy insns. */
170
171static HARD_REG_SET *qty_phys_copy_sugg;
172
173/* Element Q is a set of hard registers that are suggested for quantity Q by
174 arithmetic insns. */
175
176static HARD_REG_SET *qty_phys_sugg;
177
178/* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
179
180static short *qty_phys_num_copy_sugg;
181
182/* Element Q is the number of suggested registers in qty_phys_sugg. */
183
184static short *qty_phys_num_sugg;
185
186/* If (REG N) has been assigned a quantity number, is a register number
187 of another register assigned the same quantity number, or -1 for the
188 end of the chain. qty->first_reg point to the head of this chain. */
189
190static int *reg_next_in_qty;
191
192/* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
193 if it is >= 0,
194 of -1 if this register cannot be allocated by local-alloc,
195 or -2 if not known yet.
196
197 Note that if we see a use or death of pseudo register N with
198 reg_qty[N] == -2, register N must be local to the current block. If
199 it were used in more than one block, we would have reg_qty[N] == -1.
200 This relies on the fact that if reg_basic_block[N] is >= 0, register N
201 will not appear in any other block. We save a considerable number of
202 tests by exploiting this.
203
204 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
205 be referenced. */
206
207static int *reg_qty;
208
209/* The offset (in words) of register N within its quantity.
210 This can be nonzero if register N is SImode, and has been tied
211 to a subreg of a DImode register. */
212
213static char *reg_offset;
214
215/* Vector of substitutions of register numbers,
216 used to map pseudo regs into hardware regs.
217 This is set up as a result of register allocation.
218 Element N is the hard reg assigned to pseudo reg N,
219 or is -1 if no hard reg was assigned.
220 If N is a hard reg number, element N is N. */
221
222short *reg_renumber;
223
224/* Set of hard registers live at the current point in the scan
225 of the instructions in a basic block. */
226
227static HARD_REG_SET regs_live;
228
229/* Each set of hard registers indicates registers live at a particular
230 point in the basic block. For N even, regs_live_at[N] says which
231 hard registers are needed *after* insn N/2 (i.e., they may not
232 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
233
234 If an object is to conflict with the inputs of insn J but not the
235 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
236 if it is to conflict with the outputs of insn J but not the inputs of
237 insn J + 1, it is said to die at index J*2 + 1. */
238
239static HARD_REG_SET *regs_live_at;
240
241/* Communicate local vars `insn_number' and `insn'
242 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
243static int this_insn_number;
244static rtx this_insn;
245
246struct equivalence
247{
248 /* Set when an attempt should be made to replace a register
249 with the associated src_p entry. */
250
251 char replace;
252
253 /* Set when a REG_EQUIV note is found or created. Use to
254 keep track of what memory accesses might be created later,
255 e.g. by reload. */
256
257 rtx replacement;
258
259 rtx *src_p;
260
261 /* Loop depth is used to recognize equivalences which appear
262 to be present within the same loop (or in an inner loop). */
263
264 int loop_depth;
265
266 /* The list of each instruction which initializes this register. */
267
268 rtx init_insns;
269};
270
271/* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
272 structure for that register. */
273
274static struct equivalence *reg_equiv;
275
276/* Nonzero if we recorded an equivalence for a LABEL_REF. */
277static int recorded_label_ref;
278
279static void alloc_qty (int, enum machine_mode, int, int);
280static void validate_equiv_mem_from_store (rtx, rtx, void *);
281static int validate_equiv_mem (rtx, rtx, rtx);
282static int equiv_init_varies_p (rtx);
283static int equiv_init_movable_p (rtx, int);
284static int contains_replace_regs (rtx);
285static int memref_referenced_p (rtx, rtx);
286static int memref_used_between_p (rtx, rtx, rtx);
287static void update_equiv_regs (void);
288static void no_equiv (rtx, rtx, void *);
289static void block_alloc (int);
290static int qty_sugg_compare (int, int);
291static int qty_sugg_compare_1 (const void *, const void *);
292static int qty_compare (int, int);
293static int qty_compare_1 (const void *, const void *);
294static int combine_regs (rtx, rtx, int, int, rtx, int);
295static int reg_meets_class_p (int, enum reg_class);
296static void update_qty_class (int, int);
297static void reg_is_set (rtx, rtx, void *);
298static void reg_is_born (rtx, int);
299static void wipe_dead_reg (rtx, int);
300static int find_free_reg (enum reg_class, enum machine_mode, int, int, int,
301 int, int);
302static void mark_life (int, enum machine_mode, int);
303static void post_mark_life (int, enum machine_mode, int, int, int);
304static int no_conflict_p (rtx, rtx, rtx);
305static int requires_inout (const char *);
306\f
307/* Allocate a new quantity (new within current basic block)
308 for register number REGNO which is born at index BIRTH
309 within the block. MODE and SIZE are info on reg REGNO. */
310
311static void
312alloc_qty (int regno, enum machine_mode mode, int size, int birth)
313{
314 int qtyno = next_qty++;
315
316 reg_qty[regno] = qtyno;
317 reg_offset[regno] = 0;
318 reg_next_in_qty[regno] = -1;
319
320 qty[qtyno].first_reg = regno;
321 qty[qtyno].size = size;
322 qty[qtyno].mode = mode;
323 qty[qtyno].birth = birth;
324 qty[qtyno].n_calls_crossed = REG_N_CALLS_CROSSED (regno);
1378ea41 325 qty[qtyno].n_throwing_calls_crossed = REG_N_THROWING_CALLS_CROSSED (regno);
003757ed
MD
326 qty[qtyno].min_class = reg_preferred_class (regno);
327 qty[qtyno].alternate_class = reg_alternate_class (regno);
328 qty[qtyno].n_refs = REG_N_REFS (regno);
329 qty[qtyno].freq = REG_FREQ (regno);
330}
331\f
332/* Main entry point of this file. */
333
334int
335local_alloc (void)
336{
337 int i;
338 int max_qty;
339 basic_block b;
340
341 /* We need to keep track of whether or not we recorded a LABEL_REF so
342 that we know if the jump optimizer needs to be rerun. */
343 recorded_label_ref = 0;
344
345 /* Leaf functions and non-leaf functions have different needs.
346 If defined, let the machine say what kind of ordering we
347 should use. */
348#ifdef ORDER_REGS_FOR_LOCAL_ALLOC
349 ORDER_REGS_FOR_LOCAL_ALLOC;
350#endif
351
352 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
353 registers. */
354 if (optimize)
355 update_equiv_regs ();
356
357 /* This sets the maximum number of quantities we can have. Quantity
358 numbers start at zero and we can have one for each pseudo. */
359 max_qty = (max_regno - FIRST_PSEUDO_REGISTER);
360
361 /* Allocate vectors of temporary data.
362 See the declarations of these variables, above,
363 for what they mean. */
364
365 qty = xmalloc (max_qty * sizeof (struct qty));
366 qty_phys_copy_sugg = xmalloc (max_qty * sizeof (HARD_REG_SET));
367 qty_phys_num_copy_sugg = xmalloc (max_qty * sizeof (short));
368 qty_phys_sugg = xmalloc (max_qty * sizeof (HARD_REG_SET));
369 qty_phys_num_sugg = xmalloc (max_qty * sizeof (short));
370
371 reg_qty = xmalloc (max_regno * sizeof (int));
372 reg_offset = xmalloc (max_regno * sizeof (char));
373 reg_next_in_qty = xmalloc (max_regno * sizeof (int));
374
375 /* Determine which pseudo-registers can be allocated by local-alloc.
376 In general, these are the registers used only in a single block and
377 which only die once.
378
379 We need not be concerned with which block actually uses the register
380 since we will never see it outside that block. */
381
382 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
383 {
384 if (REG_BASIC_BLOCK (i) >= 0 && REG_N_DEATHS (i) == 1)
385 reg_qty[i] = -2;
386 else
387 reg_qty[i] = -1;
388 }
389
390 /* Force loop below to initialize entire quantity array. */
391 next_qty = max_qty;
392
393 /* Allocate each block's local registers, block by block. */
394
395 FOR_EACH_BB (b)
396 {
397 /* NEXT_QTY indicates which elements of the `qty_...'
398 vectors might need to be initialized because they were used
399 for the previous block; it is set to the entire array before
400 block 0. Initialize those, with explicit loop if there are few,
401 else with bzero and bcopy. Do not initialize vectors that are
402 explicit set by `alloc_qty'. */
403
404 if (next_qty < 6)
405 {
406 for (i = 0; i < next_qty; i++)
407 {
408 CLEAR_HARD_REG_SET (qty_phys_copy_sugg[i]);
409 qty_phys_num_copy_sugg[i] = 0;
410 CLEAR_HARD_REG_SET (qty_phys_sugg[i]);
411 qty_phys_num_sugg[i] = 0;
412 }
413 }
414 else
415 {
416#define CLEAR(vector) \
417 memset ((vector), 0, (sizeof (*(vector))) * next_qty);
418
419 CLEAR (qty_phys_copy_sugg);
420 CLEAR (qty_phys_num_copy_sugg);
421 CLEAR (qty_phys_sugg);
422 CLEAR (qty_phys_num_sugg);
423 }
424
425 next_qty = 0;
426
427 block_alloc (b->index);
428 }
429
430 free (qty);
431 free (qty_phys_copy_sugg);
432 free (qty_phys_num_copy_sugg);
433 free (qty_phys_sugg);
434 free (qty_phys_num_sugg);
435
436 free (reg_qty);
437 free (reg_offset);
438 free (reg_next_in_qty);
439
440 return recorded_label_ref;
441}
442\f
443/* Used for communication between the following two functions: contains
444 a MEM that we wish to ensure remains unchanged. */
445static rtx equiv_mem;
446
447/* Set nonzero if EQUIV_MEM is modified. */
448static int equiv_mem_modified;
449
450/* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
451 Called via note_stores. */
452
453static void
454validate_equiv_mem_from_store (rtx dest, rtx set ATTRIBUTE_UNUSED,
455 void *data ATTRIBUTE_UNUSED)
456{
457 if ((GET_CODE (dest) == REG
458 && reg_overlap_mentioned_p (dest, equiv_mem))
459 || (GET_CODE (dest) == MEM
460 && true_dependence (dest, VOIDmode, equiv_mem, rtx_varies_p)))
461 equiv_mem_modified = 1;
462}
463
464/* Verify that no store between START and the death of REG invalidates
465 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
466 by storing into an overlapping memory location, or with a non-const
467 CALL_INSN.
468
469 Return 1 if MEMREF remains valid. */
470
471static int
472validate_equiv_mem (rtx start, rtx reg, rtx memref)
473{
474 rtx insn;
475 rtx note;
476
477 equiv_mem = memref;
478 equiv_mem_modified = 0;
479
480 /* If the memory reference has side effects or is volatile, it isn't a
481 valid equivalence. */
482 if (side_effects_p (memref))
483 return 0;
484
485 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn))
486 {
487 if (! INSN_P (insn))
488 continue;
489
490 if (find_reg_note (insn, REG_DEAD, reg))
491 return 1;
492
493 if (GET_CODE (insn) == CALL_INSN && ! RTX_UNCHANGING_P (memref)
494 && ! CONST_OR_PURE_CALL_P (insn))
495 return 0;
496
497 note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL);
498
499 /* If a register mentioned in MEMREF is modified via an
500 auto-increment, we lose the equivalence. Do the same if one
501 dies; although we could extend the life, it doesn't seem worth
502 the trouble. */
503
504 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
505 if ((REG_NOTE_KIND (note) == REG_INC
506 || REG_NOTE_KIND (note) == REG_DEAD)
507 && GET_CODE (XEXP (note, 0)) == REG
508 && reg_overlap_mentioned_p (XEXP (note, 0), memref))
509 return 0;
510 }
511
512 return 0;
513}
514
515/* Returns zero if X is known to be invariant. */
516
517static int
518equiv_init_varies_p (rtx x)
519{
520 RTX_CODE code = GET_CODE (x);
521 int i;
522 const char *fmt;
523
524 switch (code)
525 {
526 case MEM:
527 return ! RTX_UNCHANGING_P (x) || equiv_init_varies_p (XEXP (x, 0));
528
529 case QUEUED:
530 return 1;
531
532 case CONST:
533 case CONST_INT:
534 case CONST_DOUBLE:
535 case CONST_VECTOR:
536 case SYMBOL_REF:
537 case LABEL_REF:
538 return 0;
539
540 case REG:
541 return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0);
542
543 case ASM_OPERANDS:
544 if (MEM_VOLATILE_P (x))
545 return 1;
546
547 /* Fall through. */
548
549 default:
550 break;
551 }
552
553 fmt = GET_RTX_FORMAT (code);
554 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
555 if (fmt[i] == 'e')
556 {
557 if (equiv_init_varies_p (XEXP (x, i)))
558 return 1;
559 }
560 else if (fmt[i] == 'E')
561 {
562 int j;
563 for (j = 0; j < XVECLEN (x, i); j++)
564 if (equiv_init_varies_p (XVECEXP (x, i, j)))
565 return 1;
566 }
567
568 return 0;
569}
570
571/* Returns nonzero if X (used to initialize register REGNO) is movable.
572 X is only movable if the registers it uses have equivalent initializations
573 which appear to be within the same loop (or in an inner loop) and movable
574 or if they are not candidates for local_alloc and don't vary. */
575
576static int
577equiv_init_movable_p (rtx x, int regno)
578{
579 int i, j;
580 const char *fmt;
581 enum rtx_code code = GET_CODE (x);
582
583 switch (code)
584 {
585 case SET:
586 return equiv_init_movable_p (SET_SRC (x), regno);
587
588 case CC0:
589 case CLOBBER:
590 return 0;
591
592 case PRE_INC:
593 case PRE_DEC:
594 case POST_INC:
595 case POST_DEC:
596 case PRE_MODIFY:
597 case POST_MODIFY:
598 return 0;
599
600 case REG:
601 return (reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth
602 && reg_equiv[REGNO (x)].replace)
603 || (REG_BASIC_BLOCK (REGNO (x)) < 0 && ! rtx_varies_p (x, 0));
604
605 case UNSPEC_VOLATILE:
606 return 0;
607
608 case ASM_OPERANDS:
609 if (MEM_VOLATILE_P (x))
610 return 0;
611
612 /* Fall through. */
613
614 default:
615 break;
616 }
617
618 fmt = GET_RTX_FORMAT (code);
619 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
620 switch (fmt[i])
621 {
622 case 'e':
623 if (! equiv_init_movable_p (XEXP (x, i), regno))
624 return 0;
625 break;
626 case 'E':
627 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
628 if (! equiv_init_movable_p (XVECEXP (x, i, j), regno))
629 return 0;
630 break;
631 }
632
633 return 1;
634}
635
636/* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
637
638static int
639contains_replace_regs (rtx x)
640{
641 int i, j;
642 const char *fmt;
643 enum rtx_code code = GET_CODE (x);
644
645 switch (code)
646 {
647 case CONST_INT:
648 case CONST:
649 case LABEL_REF:
650 case SYMBOL_REF:
651 case CONST_DOUBLE:
652 case CONST_VECTOR:
653 case PC:
654 case CC0:
655 case HIGH:
656 return 0;
657
658 case REG:
659 return reg_equiv[REGNO (x)].replace;
660
661 default:
662 break;
663 }
664
665 fmt = GET_RTX_FORMAT (code);
666 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
667 switch (fmt[i])
668 {
669 case 'e':
670 if (contains_replace_regs (XEXP (x, i)))
671 return 1;
672 break;
673 case 'E':
674 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
675 if (contains_replace_regs (XVECEXP (x, i, j)))
676 return 1;
677 break;
678 }
679
680 return 0;
681}
682\f
683/* TRUE if X references a memory location that would be affected by a store
684 to MEMREF. */
685
686static int
687memref_referenced_p (rtx memref, rtx x)
688{
689 int i, j;
690 const char *fmt;
691 enum rtx_code code = GET_CODE (x);
692
693 switch (code)
694 {
695 case CONST_INT:
696 case CONST:
697 case LABEL_REF:
698 case SYMBOL_REF:
699 case CONST_DOUBLE:
700 case CONST_VECTOR:
701 case PC:
702 case CC0:
703 case HIGH:
704 case LO_SUM:
705 return 0;
706
707 case REG:
708 return (reg_equiv[REGNO (x)].replacement
709 && memref_referenced_p (memref,
710 reg_equiv[REGNO (x)].replacement));
711
712 case MEM:
713 if (true_dependence (memref, VOIDmode, x, rtx_varies_p))
714 return 1;
715 break;
716
717 case SET:
718 /* If we are setting a MEM, it doesn't count (its address does), but any
719 other SET_DEST that has a MEM in it is referencing the MEM. */
720 if (GET_CODE (SET_DEST (x)) == MEM)
721 {
722 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0)))
723 return 1;
724 }
725 else if (memref_referenced_p (memref, SET_DEST (x)))
726 return 1;
727
728 return memref_referenced_p (memref, SET_SRC (x));
729
730 default:
731 break;
732 }
733
734 fmt = GET_RTX_FORMAT (code);
735 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
736 switch (fmt[i])
737 {
738 case 'e':
739 if (memref_referenced_p (memref, XEXP (x, i)))
740 return 1;
741 break;
742 case 'E':
743 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
744 if (memref_referenced_p (memref, XVECEXP (x, i, j)))
745 return 1;
746 break;
747 }
748
749 return 0;
750}
751
752/* TRUE if some insn in the range (START, END] references a memory location
753 that would be affected by a store to MEMREF. */
754
755static int
756memref_used_between_p (rtx memref, rtx start, rtx end)
757{
758 rtx insn;
759
760 for (insn = NEXT_INSN (start); insn != NEXT_INSN (end);
761 insn = NEXT_INSN (insn))
762 if (INSN_P (insn) && memref_referenced_p (memref, PATTERN (insn)))
763 return 1;
764
765 return 0;
766}
767\f
768/* Return nonzero if the rtx X is invariant over the current function. */
769/* ??? Actually, the places this is used in reload expect exactly what
770 is tested here, and not everything that is function invariant. In
771 particular, the frame pointer and arg pointer are special cased;
772 pic_offset_table_rtx is not, and this will cause aborts when we
773 go to spill these things to memory. */
774
775int
776function_invariant_p (rtx x)
777{
778 if (CONSTANT_P (x))
779 return 1;
780 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
781 return 1;
782 if (GET_CODE (x) == PLUS
783 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
784 && CONSTANT_P (XEXP (x, 1)))
785 return 1;
786 return 0;
787}
788
789/* Find registers that are equivalent to a single value throughout the
790 compilation (either because they can be referenced in memory or are set once
791 from a single constant). Lower their priority for a register.
792
793 If such a register is only referenced once, try substituting its value
794 into the using insn. If it succeeds, we can eliminate the register
795 completely. */
796
797static void
798update_equiv_regs (void)
799{
800 rtx insn;
801 basic_block bb;
802 int loop_depth;
803 regset_head cleared_regs;
804 int clear_regnos = 0;
805
806 reg_equiv = xcalloc (max_regno, sizeof *reg_equiv);
807 INIT_REG_SET (&cleared_regs);
808
809 init_alias_analysis ();
810
811 /* Scan the insns and find which registers have equivalences. Do this
812 in a separate scan of the insns because (due to -fcse-follow-jumps)
813 a register can be set below its use. */
814 FOR_EACH_BB (bb)
815 {
816 loop_depth = bb->loop_depth;
817
818 for (insn = BB_HEAD (bb);
819 insn != NEXT_INSN (BB_END (bb));
820 insn = NEXT_INSN (insn))
821 {
822 rtx note;
823 rtx set;
824 rtx dest, src;
825 int regno;
826
827 if (! INSN_P (insn))
828 continue;
829
830 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
831 if (REG_NOTE_KIND (note) == REG_INC)
832 no_equiv (XEXP (note, 0), note, NULL);
833
834 set = single_set (insn);
835
836 /* If this insn contains more (or less) than a single SET,
837 only mark all destinations as having no known equivalence. */
838 if (set == 0)
839 {
840 note_stores (PATTERN (insn), no_equiv, NULL);
841 continue;
842 }
843 else if (GET_CODE (PATTERN (insn)) == PARALLEL)
844 {
845 int i;
846
847 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--)
848 {
849 rtx part = XVECEXP (PATTERN (insn), 0, i);
850 if (part != set)
851 note_stores (part, no_equiv, NULL);
852 }
853 }
854
855 dest = SET_DEST (set);
856 src = SET_SRC (set);
857
858 /* If this sets a MEM to the contents of a REG that is only used
859 in a single basic block, see if the register is always equivalent
860 to that memory location and if moving the store from INSN to the
861 insn that set REG is safe. If so, put a REG_EQUIV note on the
862 initializing insn.
863
864 Don't add a REG_EQUIV note if the insn already has one. The existing
865 REG_EQUIV is likely more useful than the one we are adding.
866
867 If one of the regs in the address has reg_equiv[REGNO].replace set,
868 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
869 optimization may move the set of this register immediately before
870 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
871 the mention in the REG_EQUIV note would be to an uninitialized
872 pseudo. */
873 /* ????? This test isn't good enough; we might see a MEM with a use of
874 a pseudo register before we see its setting insn that will cause
875 reg_equiv[].replace for that pseudo to be set.
876 Equivalences to MEMs should be made in another pass, after the
877 reg_equiv[].replace information has been gathered. */
878
879 if (GET_CODE (dest) == MEM && GET_CODE (src) == REG
880 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER
881 && REG_BASIC_BLOCK (regno) >= 0
882 && REG_N_SETS (regno) == 1
883 && reg_equiv[regno].init_insns != 0
884 && reg_equiv[regno].init_insns != const0_rtx
885 && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0),
886 REG_EQUIV, NULL_RTX)
887 && ! contains_replace_regs (XEXP (dest, 0)))
888 {
889 rtx init_insn = XEXP (reg_equiv[regno].init_insns, 0);
890 if (validate_equiv_mem (init_insn, src, dest)
891 && ! memref_used_between_p (dest, init_insn, insn))
892 REG_NOTES (init_insn)
893 = gen_rtx_EXPR_LIST (REG_EQUIV, dest, REG_NOTES (init_insn));
894 }
895
896 /* We only handle the case of a pseudo register being set
897 once, or always to the same value. */
898 /* ??? The mn10200 port breaks if we add equivalences for
899 values that need an ADDRESS_REGS register and set them equivalent
900 to a MEM of a pseudo. The actual problem is in the over-conservative
901 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
902 calculate_needs, but we traditionally work around this problem
903 here by rejecting equivalences when the destination is in a register
904 that's likely spilled. This is fragile, of course, since the
905 preferred class of a pseudo depends on all instructions that set
906 or use it. */
907
908 if (GET_CODE (dest) != REG
909 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER
910 || reg_equiv[regno].init_insns == const0_rtx
911 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno))
912 && GET_CODE (src) == MEM))
913 {
914 /* This might be setting a SUBREG of a pseudo, a pseudo that is
915 also set somewhere else to a constant. */
916 note_stores (set, no_equiv, NULL);
917 continue;
918 }
919
920 note = find_reg_note (insn, REG_EQUAL, NULL_RTX);
921
922 /* cse sometimes generates function invariants, but doesn't put a
923 REG_EQUAL note on the insn. Since this note would be redundant,
924 there's no point creating it earlier than here. */
925 if (! note && ! rtx_varies_p (src, 0))
926 note = set_unique_reg_note (insn, REG_EQUAL, src);
927
928 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
929 since it represents a function call */
930 if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST)
931 note = NULL_RTX;
932
933 if (REG_N_SETS (regno) != 1
934 && (! note
935 || rtx_varies_p (XEXP (note, 0), 0)
936 || (reg_equiv[regno].replacement
937 && ! rtx_equal_p (XEXP (note, 0),
938 reg_equiv[regno].replacement))))
939 {
940 no_equiv (dest, set, NULL);
941 continue;
942 }
943 /* Record this insn as initializing this register. */
944 reg_equiv[regno].init_insns
945 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns);
946
947 /* If this register is known to be equal to a constant, record that
948 it is always equivalent to the constant. */
949 if (note && ! rtx_varies_p (XEXP (note, 0), 0))
950 PUT_MODE (note, (enum machine_mode) REG_EQUIV);
951
952 /* If this insn introduces a "constant" register, decrease the priority
953 of that register. Record this insn if the register is only used once
954 more and the equivalence value is the same as our source.
955
956 The latter condition is checked for two reasons: First, it is an
957 indication that it may be more efficient to actually emit the insn
958 as written (if no registers are available, reload will substitute
959 the equivalence). Secondly, it avoids problems with any registers
960 dying in this insn whose death notes would be missed.
961
962 If we don't have a REG_EQUIV note, see if this insn is loading
963 a register used only in one basic block from a MEM. If so, and the
964 MEM remains unchanged for the life of the register, add a REG_EQUIV
965 note. */
966
967 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
968
969 if (note == 0 && REG_BASIC_BLOCK (regno) >= 0
970 && GET_CODE (SET_SRC (set)) == MEM
971 && validate_equiv_mem (insn, dest, SET_SRC (set)))
972 REG_NOTES (insn) = note = gen_rtx_EXPR_LIST (REG_EQUIV, SET_SRC (set),
973 REG_NOTES (insn));
974
975 if (note)
976 {
977 int regno = REGNO (dest);
978
979 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
980 We might end up substituting the LABEL_REF for uses of the
981 pseudo here or later. That kind of transformation may turn an
982 indirect jump into a direct jump, in which case we must rerun the
983 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
984 if (GET_CODE (XEXP (note, 0)) == LABEL_REF
985 || (GET_CODE (XEXP (note, 0)) == CONST
986 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
987 && (GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0))
988 == LABEL_REF)))
989 recorded_label_ref = 1;
990
991 reg_equiv[regno].replacement = XEXP (note, 0);
992 reg_equiv[regno].src_p = &SET_SRC (set);
993 reg_equiv[regno].loop_depth = loop_depth;
994
995 /* Don't mess with things live during setjmp. */
996 if (REG_LIVE_LENGTH (regno) >= 0 && optimize)
997 {
998 /* Note that the statement below does not affect the priority
999 in local-alloc! */
1000 REG_LIVE_LENGTH (regno) *= 2;
1001
1002
1003 /* If the register is referenced exactly twice, meaning it is
1004 set once and used once, indicate that the reference may be
1005 replaced by the equivalence we computed above. Do this
1006 even if the register is only used in one block so that
1007 dependencies can be handled where the last register is
1008 used in a different block (i.e. HIGH / LO_SUM sequences)
1009 and to reduce the number of registers alive across
1010 calls. */
1011
1012 if (REG_N_REFS (regno) == 2
1013 && (rtx_equal_p (XEXP (note, 0), src)
1014 || ! equiv_init_varies_p (src))
1015 && GET_CODE (insn) == INSN
1016 && equiv_init_movable_p (PATTERN (insn), regno))
1017 reg_equiv[regno].replace = 1;
1018 }
1019 }
1020 }
1021 }
1022
1023 /* Now scan all regs killed in an insn to see if any of them are
1024 registers only used that once. If so, see if we can replace the
1025 reference with the equivalent from. If we can, delete the
1026 initializing reference and this register will go away. If we
1027 can't replace the reference, and the initializing reference is
1028 within the same loop (or in an inner loop), then move the register
1029 initialization just before the use, so that they are in the same
1030 basic block. */
1031 FOR_EACH_BB_REVERSE (bb)
1032 {
1033 loop_depth = bb->loop_depth;
1034 for (insn = BB_END (bb);
1035 insn != PREV_INSN (BB_HEAD (bb));
1036 insn = PREV_INSN (insn))
1037 {
1038 rtx link;
1039
1040 if (! INSN_P (insn))
1041 continue;
1042
1043 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1044 {
1045 if (REG_NOTE_KIND (link) == REG_DEAD
1046 /* Make sure this insn still refers to the register. */
1047 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn)))
1048 {
1049 int regno = REGNO (XEXP (link, 0));
1050 rtx equiv_insn;
1051
1052 if (! reg_equiv[regno].replace
1053 || reg_equiv[regno].loop_depth < loop_depth)
1054 continue;
1055
1056 /* reg_equiv[REGNO].replace gets set only when
1057 REG_N_REFS[REGNO] is 2, i.e. the register is set
1058 once and used once. (If it were only set, but not used,
1059 flow would have deleted the setting insns.) Hence
1060 there can only be one insn in reg_equiv[REGNO].init_insns. */
1061 if (reg_equiv[regno].init_insns == NULL_RTX
1062 || XEXP (reg_equiv[regno].init_insns, 1) != NULL_RTX)
1063 abort ();
1064 equiv_insn = XEXP (reg_equiv[regno].init_insns, 0);
1065
1066 /* We may not move instructions that can throw, since
1067 that changes basic block boundaries and we are not
1068 prepared to adjust the CFG to match. */
1069 if (can_throw_internal (equiv_insn))
1070 continue;
1071
1072 if (asm_noperands (PATTERN (equiv_insn)) < 0
1073 && validate_replace_rtx (regno_reg_rtx[regno],
1074 *(reg_equiv[regno].src_p), insn))
1075 {
1076 rtx equiv_link;
1077 rtx last_link;
1078 rtx note;
1079
1080 /* Find the last note. */
1081 for (last_link = link; XEXP (last_link, 1);
1082 last_link = XEXP (last_link, 1))
1083 ;
1084
1085 /* Append the REG_DEAD notes from equiv_insn. */
1086 equiv_link = REG_NOTES (equiv_insn);
1087 while (equiv_link)
1088 {
1089 note = equiv_link;
1090 equiv_link = XEXP (equiv_link, 1);
1091 if (REG_NOTE_KIND (note) == REG_DEAD)
1092 {
1093 remove_note (equiv_insn, note);
1094 XEXP (last_link, 1) = note;
1095 XEXP (note, 1) = NULL_RTX;
1096 last_link = note;
1097 }
1098 }
1099
1100 remove_death (regno, insn);
1101 REG_N_REFS (regno) = 0;
1102 REG_FREQ (regno) = 0;
1103 delete_insn (equiv_insn);
1104
1105 reg_equiv[regno].init_insns
1106 = XEXP (reg_equiv[regno].init_insns, 1);
1107 }
1108 /* Move the initialization of the register to just before
1109 INSN. Update the flow information. */
1110 else if (PREV_INSN (insn) != equiv_insn)
1111 {
1112 rtx new_insn;
1113
1114 new_insn = emit_insn_before (PATTERN (equiv_insn), insn);
1115 REG_NOTES (new_insn) = REG_NOTES (equiv_insn);
1116 REG_NOTES (equiv_insn) = 0;
1117
1118 /* Make sure this insn is recognized before reload begins,
1119 otherwise eliminate_regs_in_insn will abort. */
1120 INSN_CODE (new_insn) = INSN_CODE (equiv_insn);
1121
1122 delete_insn (equiv_insn);
1123
1124 XEXP (reg_equiv[regno].init_insns, 0) = new_insn;
1125
1126 REG_BASIC_BLOCK (regno) = bb->index;
1127 REG_N_CALLS_CROSSED (regno) = 0;
1378ea41 1128 REG_N_THROWING_CALLS_CROSSED (regno) = 0;
003757ed
MD
1129 REG_LIVE_LENGTH (regno) = 2;
1130
1131 if (insn == BB_HEAD (bb))
1132 BB_HEAD (bb) = PREV_INSN (insn);
1133
1134 /* Remember to clear REGNO from all basic block's live
1135 info. */
1136 SET_REGNO_REG_SET (&cleared_regs, regno);
1137 clear_regnos++;
1138 }
1139 }
1140 }
1141 }
1142 }
1143
1144 /* Clear all dead REGNOs from all basic block's live info. */
1145 if (clear_regnos)
1146 {
1147 int j;
1148 if (clear_regnos > 8)
1149 {
1150 FOR_EACH_BB (bb)
1151 {
1152 AND_COMPL_REG_SET (bb->global_live_at_start, &cleared_regs);
1153 AND_COMPL_REG_SET (bb->global_live_at_end, &cleared_regs);
1154 }
1155 }
1156 else
1157 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs, 0, j,
1158 {
1159 FOR_EACH_BB (bb)
1160 {
1161 CLEAR_REGNO_REG_SET (bb->global_live_at_start, j);
1162 CLEAR_REGNO_REG_SET (bb->global_live_at_end, j);
1163 }
1164 });
1165 }
1166
1167 /* Clean up. */
1168 end_alias_analysis ();
1169 CLEAR_REG_SET (&cleared_regs);
1170 free (reg_equiv);
1171}
1172
1173/* Mark REG as having no known equivalence.
1174 Some instructions might have been processed before and furnished
1175 with REG_EQUIV notes for this register; these notes will have to be
1176 removed.
1177 STORE is the piece of RTL that does the non-constant / conflicting
1178 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1179 but needs to be there because this function is called from note_stores. */
1180static void
1181no_equiv (rtx reg, rtx store ATTRIBUTE_UNUSED, void *data ATTRIBUTE_UNUSED)
1182{
1183 int regno;
1184 rtx list;
1185
1186 if (GET_CODE (reg) != REG)
1187 return;
1188 regno = REGNO (reg);
1189 list = reg_equiv[regno].init_insns;
1190 if (list == const0_rtx)
1191 return;
1192 for (; list; list = XEXP (list, 1))
1193 {
1194 rtx insn = XEXP (list, 0);
1195 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX));
1196 }
1197 reg_equiv[regno].init_insns = const0_rtx;
1198 reg_equiv[regno].replacement = NULL_RTX;
1199}
1200\f
1201/* Allocate hard regs to the pseudo regs used only within block number B.
1202 Only the pseudos that die but once can be handled. */
1203
1204static void
1205block_alloc (int b)
1206{
1207 int i, q;
1208 rtx insn;
1209 rtx note, hard_reg;
1210 int insn_number = 0;
1211 int insn_count = 0;
1212 int max_uid = get_max_uid ();
1213 int *qty_order;
1214 int no_conflict_combined_regno = -1;
1215
1216 /* Count the instructions in the basic block. */
1217
1218 insn = BB_END (BASIC_BLOCK (b));
1219 while (1)
1220 {
1221 if (GET_CODE (insn) != NOTE)
1222 if (++insn_count > max_uid)
1223 abort ();
1224 if (insn == BB_HEAD (BASIC_BLOCK (b)))
1225 break;
1226 insn = PREV_INSN (insn);
1227 }
1228
1229 /* +2 to leave room for a post_mark_life at the last insn and for
1230 the birth of a CLOBBER in the first insn. */
1231 regs_live_at = xcalloc ((2 * insn_count + 2), sizeof (HARD_REG_SET));
1232
1233 /* Initialize table of hardware registers currently live. */
1234
1235 REG_SET_TO_HARD_REG_SET (regs_live, BASIC_BLOCK (b)->global_live_at_start);
1236
1237 /* This loop scans the instructions of the basic block
1238 and assigns quantities to registers.
1239 It computes which registers to tie. */
1240
1241 insn = BB_HEAD (BASIC_BLOCK (b));
1242 while (1)
1243 {
1244 if (GET_CODE (insn) != NOTE)
1245 insn_number++;
1246
1247 if (INSN_P (insn))
1248 {
1249 rtx link, set;
1250 int win = 0;
1251 rtx r0, r1 = NULL_RTX;
1252 int combined_regno = -1;
1253 int i;
1254
1255 this_insn_number = insn_number;
1256 this_insn = insn;
1257
1258 extract_insn (insn);
1259 which_alternative = -1;
1260
1261 /* Is this insn suitable for tying two registers?
1262 If so, try doing that.
1263 Suitable insns are those with at least two operands and where
1264 operand 0 is an output that is a register that is not
1265 earlyclobber.
1266
1267 We can tie operand 0 with some operand that dies in this insn.
1268 First look for operands that are required to be in the same
1269 register as operand 0. If we find such, only try tying that
1270 operand or one that can be put into that operand if the
1271 operation is commutative. If we don't find an operand
1272 that is required to be in the same register as operand 0,
1273 we can tie with any operand.
1274
1275 Subregs in place of regs are also ok.
1276
1277 If tying is done, WIN is set nonzero. */
1278
1279 if (optimize
1280 && recog_data.n_operands > 1
1281 && recog_data.constraints[0][0] == '='
1282 && recog_data.constraints[0][1] != '&')
1283 {
1284 /* If non-negative, is an operand that must match operand 0. */
1285 int must_match_0 = -1;
1286 /* Counts number of alternatives that require a match with
1287 operand 0. */
1288 int n_matching_alts = 0;
1289
1290 for (i = 1; i < recog_data.n_operands; i++)
1291 {
1292 const char *p = recog_data.constraints[i];
1293 int this_match = requires_inout (p);
1294
1295 n_matching_alts += this_match;
1296 if (this_match == recog_data.n_alternatives)
1297 must_match_0 = i;
1298 }
1299
1300 r0 = recog_data.operand[0];
1301 for (i = 1; i < recog_data.n_operands; i++)
1302 {
1303 /* Skip this operand if we found an operand that
1304 must match operand 0 and this operand isn't it
1305 and can't be made to be it by commutativity. */
1306
1307 if (must_match_0 >= 0 && i != must_match_0
1308 && ! (i == must_match_0 + 1
1309 && recog_data.constraints[i-1][0] == '%')
1310 && ! (i == must_match_0 - 1
1311 && recog_data.constraints[i][0] == '%'))
1312 continue;
1313
1314 /* Likewise if each alternative has some operand that
1315 must match operand zero. In that case, skip any
1316 operand that doesn't list operand 0 since we know that
1317 the operand always conflicts with operand 0. We
1318 ignore commutativity in this case to keep things simple. */
1319 if (n_matching_alts == recog_data.n_alternatives
1320 && 0 == requires_inout (recog_data.constraints[i]))
1321 continue;
1322
1323 r1 = recog_data.operand[i];
1324
1325 /* If the operand is an address, find a register in it.
1326 There may be more than one register, but we only try one
1327 of them. */
1328 if (recog_data.constraints[i][0] == 'p'
1329 || EXTRA_ADDRESS_CONSTRAINT (recog_data.constraints[i][0],
1330 recog_data.constraints[i]))
1331 while (GET_CODE (r1) == PLUS || GET_CODE (r1) == MULT)
1332 r1 = XEXP (r1, 0);
1333
1334 /* Avoid making a call-saved register unnecessarily
1335 clobbered. */
1336 hard_reg = get_hard_reg_initial_reg (cfun, r1);
1337 if (hard_reg != NULL_RTX)
1338 {
1339 if (GET_CODE (hard_reg) == REG
1340 && IN_RANGE (REGNO (hard_reg),
1341 0, FIRST_PSEUDO_REGISTER - 1)
1342 && ! call_used_regs[REGNO (hard_reg)])
1343 continue;
1344 }
1345
1346 if (GET_CODE (r0) == REG || GET_CODE (r0) == SUBREG)
1347 {
1348 /* We have two priorities for hard register preferences.
1349 If we have a move insn or an insn whose first input
1350 can only be in the same register as the output, give
1351 priority to an equivalence found from that insn. */
1352 int may_save_copy
1353 = (r1 == recog_data.operand[i] && must_match_0 >= 0);
1354
1355 if (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1356 win = combine_regs (r1, r0, may_save_copy,
1357 insn_number, insn, 0);
1358 }
1359 if (win)
1360 break;
1361 }
1362 }
1363
1364 /* Recognize an insn sequence with an ultimate result
1365 which can safely overlap one of the inputs.
1366 The sequence begins with a CLOBBER of its result,
1367 and ends with an insn that copies the result to itself
1368 and has a REG_EQUAL note for an equivalent formula.
1369 That note indicates what the inputs are.
1370 The result and the input can overlap if each insn in
1371 the sequence either doesn't mention the input
1372 or has a REG_NO_CONFLICT note to inhibit the conflict.
1373
1374 We do the combining test at the CLOBBER so that the
1375 destination register won't have had a quantity number
1376 assigned, since that would prevent combining. */
1377
1378 if (optimize
1379 && GET_CODE (PATTERN (insn)) == CLOBBER
1380 && (r0 = XEXP (PATTERN (insn), 0),
1381 GET_CODE (r0) == REG)
1382 && (link = find_reg_note (insn, REG_LIBCALL, NULL_RTX)) != 0
1383 && XEXP (link, 0) != 0
1384 && GET_CODE (XEXP (link, 0)) == INSN
1385 && (set = single_set (XEXP (link, 0))) != 0
1386 && SET_DEST (set) == r0 && SET_SRC (set) == r0
1387 && (note = find_reg_note (XEXP (link, 0), REG_EQUAL,
1388 NULL_RTX)) != 0)
1389 {
1390 if (r1 = XEXP (note, 0), GET_CODE (r1) == REG
1391 /* Check that we have such a sequence. */
1392 && no_conflict_p (insn, r0, r1))
1393 win = combine_regs (r1, r0, 1, insn_number, insn, 1);
1394 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note, 0)))[0] == 'e'
1395 && (r1 = XEXP (XEXP (note, 0), 0),
1396 GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG)
1397 && no_conflict_p (insn, r0, r1))
1398 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1399
1400 /* Here we care if the operation to be computed is
1401 commutative. */
1402 else if ((GET_CODE (XEXP (note, 0)) == EQ
1403 || GET_CODE (XEXP (note, 0)) == NE
1404 || GET_RTX_CLASS (GET_CODE (XEXP (note, 0))) == 'c')
1405 && (r1 = XEXP (XEXP (note, 0), 1),
1406 (GET_CODE (r1) == REG || GET_CODE (r1) == SUBREG))
1407 && no_conflict_p (insn, r0, r1))
1408 win = combine_regs (r1, r0, 0, insn_number, insn, 1);
1409
1410 /* If we did combine something, show the register number
1411 in question so that we know to ignore its death. */
1412 if (win)
1413 no_conflict_combined_regno = REGNO (r1);
1414 }
1415
1416 /* If registers were just tied, set COMBINED_REGNO
1417 to the number of the register used in this insn
1418 that was tied to the register set in this insn.
1419 This register's qty should not be "killed". */
1420
1421 if (win)
1422 {
1423 while (GET_CODE (r1) == SUBREG)
1424 r1 = SUBREG_REG (r1);
1425 combined_regno = REGNO (r1);
1426 }
1427
1428 /* Mark the death of everything that dies in this instruction,
1429 except for anything that was just combined. */
1430
1431 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1432 if (REG_NOTE_KIND (link) == REG_DEAD
1433 && GET_CODE (XEXP (link, 0)) == REG
1434 && combined_regno != (int) REGNO (XEXP (link, 0))
1435 && (no_conflict_combined_regno != (int) REGNO (XEXP (link, 0))
1436 || ! find_reg_note (insn, REG_NO_CONFLICT,
1437 XEXP (link, 0))))
1438 wipe_dead_reg (XEXP (link, 0), 0);
1439
1440 /* Allocate qty numbers for all registers local to this block
1441 that are born (set) in this instruction.
1442 A pseudo that already has a qty is not changed. */
1443
1444 note_stores (PATTERN (insn), reg_is_set, NULL);
1445
1446 /* If anything is set in this insn and then unused, mark it as dying
1447 after this insn, so it will conflict with our outputs. This
1448 can't match with something that combined, and it doesn't matter
1449 if it did. Do this after the calls to reg_is_set since these
1450 die after, not during, the current insn. */
1451
1452 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1453 if (REG_NOTE_KIND (link) == REG_UNUSED
1454 && GET_CODE (XEXP (link, 0)) == REG)
1455 wipe_dead_reg (XEXP (link, 0), 1);
1456
1457 /* If this is an insn that has a REG_RETVAL note pointing at a
1458 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1459 block, so clear any register number that combined within it. */
1460 if ((note = find_reg_note (insn, REG_RETVAL, NULL_RTX)) != 0
1461 && GET_CODE (XEXP (note, 0)) == INSN
1462 && GET_CODE (PATTERN (XEXP (note, 0))) == CLOBBER)
1463 no_conflict_combined_regno = -1;
1464 }
1465
1466 /* Set the registers live after INSN_NUMBER. Note that we never
1467 record the registers live before the block's first insn, since no
1468 pseudos we care about are live before that insn. */
1469
1470 IOR_HARD_REG_SET (regs_live_at[2 * insn_number], regs_live);
1471 IOR_HARD_REG_SET (regs_live_at[2 * insn_number + 1], regs_live);
1472
1473 if (insn == BB_END (BASIC_BLOCK (b)))
1474 break;
1475
1476 insn = NEXT_INSN (insn);
1477 }
1478
1479 /* Now every register that is local to this basic block
1480 should have been given a quantity, or else -1 meaning ignore it.
1481 Every quantity should have a known birth and death.
1482
1483 Order the qtys so we assign them registers in order of the
1484 number of suggested registers they need so we allocate those with
1485 the most restrictive needs first. */
1486
1487 qty_order = xmalloc (next_qty * sizeof (int));
1488 for (i = 0; i < next_qty; i++)
1489 qty_order[i] = i;
1490
1491#define EXCHANGE(I1, I2) \
1492 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1493
1494 switch (next_qty)
1495 {
1496 case 3:
1497 /* Make qty_order[2] be the one to allocate last. */
1498 if (qty_sugg_compare (0, 1) > 0)
1499 EXCHANGE (0, 1);
1500 if (qty_sugg_compare (1, 2) > 0)
1501 EXCHANGE (2, 1);
1502
1503 /* ... Fall through ... */
1504 case 2:
1505 /* Put the best one to allocate in qty_order[0]. */
1506 if (qty_sugg_compare (0, 1) > 0)
1507 EXCHANGE (0, 1);
1508
1509 /* ... Fall through ... */
1510
1511 case 1:
1512 case 0:
1513 /* Nothing to do here. */
1514 break;
1515
1516 default:
1517 qsort (qty_order, next_qty, sizeof (int), qty_sugg_compare_1);
1518 }
1519
1520 /* Try to put each quantity in a suggested physical register, if it has one.
1521 This may cause registers to be allocated that otherwise wouldn't be, but
1522 this seems acceptable in local allocation (unlike global allocation). */
1523 for (i = 0; i < next_qty; i++)
1524 {
1525 q = qty_order[i];
1526 if (qty_phys_num_sugg[q] != 0 || qty_phys_num_copy_sugg[q] != 0)
1527 qty[q].phys_reg = find_free_reg (qty[q].min_class, qty[q].mode, q,
1528 0, 1, qty[q].birth, qty[q].death);
1529 else
1530 qty[q].phys_reg = -1;
1531 }
1532
1533 /* Order the qtys so we assign them registers in order of
1534 decreasing length of life. Normally call qsort, but if we
1535 have only a very small number of quantities, sort them ourselves. */
1536
1537 for (i = 0; i < next_qty; i++)
1538 qty_order[i] = i;
1539
1540#define EXCHANGE(I1, I2) \
1541 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1542
1543 switch (next_qty)
1544 {
1545 case 3:
1546 /* Make qty_order[2] be the one to allocate last. */
1547 if (qty_compare (0, 1) > 0)
1548 EXCHANGE (0, 1);
1549 if (qty_compare (1, 2) > 0)
1550 EXCHANGE (2, 1);
1551
1552 /* ... Fall through ... */
1553 case 2:
1554 /* Put the best one to allocate in qty_order[0]. */
1555 if (qty_compare (0, 1) > 0)
1556 EXCHANGE (0, 1);
1557
1558 /* ... Fall through ... */
1559
1560 case 1:
1561 case 0:
1562 /* Nothing to do here. */
1563 break;
1564
1565 default:
1566 qsort (qty_order, next_qty, sizeof (int), qty_compare_1);
1567 }
1568
1569 /* Now for each qty that is not a hardware register,
1570 look for a hardware register to put it in.
1571 First try the register class that is cheapest for this qty,
1572 if there is more than one class. */
1573
1574 for (i = 0; i < next_qty; i++)
1575 {
1576 q = qty_order[i];
1577 if (qty[q].phys_reg < 0)
1578 {
1579#ifdef INSN_SCHEDULING
1580 /* These values represent the adjusted lifetime of a qty so
1581 that it conflicts with qtys which appear near the start/end
1582 of this qty's lifetime.
1583
1584 The purpose behind extending the lifetime of this qty is to
1585 discourage the register allocator from creating false
1586 dependencies.
1587
1588 The adjustment value is chosen to indicate that this qty
1589 conflicts with all the qtys in the instructions immediately
1590 before and after the lifetime of this qty.
1591
1592 Experiments have shown that higher values tend to hurt
1593 overall code performance.
1594
1595 If allocation using the extended lifetime fails we will try
1596 again with the qty's unadjusted lifetime. */
1597 int fake_birth = MAX (0, qty[q].birth - 2 + qty[q].birth % 2);
1598 int fake_death = MIN (insn_number * 2 + 1,
1599 qty[q].death + 2 - qty[q].death % 2);
1600#endif
1601
1602 if (N_REG_CLASSES > 1)
1603 {
1604#ifdef INSN_SCHEDULING
1605 /* We try to avoid using hard registers allocated to qtys which
1606 are born immediately after this qty or die immediately before
1607 this qty.
1608
1609 This optimization is only appropriate when we will run
1610 a scheduling pass after reload and we are not optimizing
1611 for code size. */
1612 if (flag_schedule_insns_after_reload
1613 && !optimize_size
1614 && !SMALL_REGISTER_CLASSES)
1615 {
1616 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1617 qty[q].mode, q, 0, 0,
1618 fake_birth, fake_death);
1619 if (qty[q].phys_reg >= 0)
1620 continue;
1621 }
1622#endif
1623 qty[q].phys_reg = find_free_reg (qty[q].min_class,
1624 qty[q].mode, q, 0, 0,
1625 qty[q].birth, qty[q].death);
1626 if (qty[q].phys_reg >= 0)
1627 continue;
1628 }
1629
1630#ifdef INSN_SCHEDULING
1631 /* Similarly, avoid false dependencies. */
1632 if (flag_schedule_insns_after_reload
1633 && !optimize_size
1634 && !SMALL_REGISTER_CLASSES
1635 && qty[q].alternate_class != NO_REGS)
1636 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1637 qty[q].mode, q, 0, 0,
1638 fake_birth, fake_death);
1639#endif
1640 if (qty[q].alternate_class != NO_REGS)
1641 qty[q].phys_reg = find_free_reg (qty[q].alternate_class,
1642 qty[q].mode, q, 0, 0,
1643 qty[q].birth, qty[q].death);
1644 }
1645 }
1646
1647 /* Now propagate the register assignments
1648 to the pseudo regs belonging to the qtys. */
1649
1650 for (q = 0; q < next_qty; q++)
1651 if (qty[q].phys_reg >= 0)
1652 {
1653 for (i = qty[q].first_reg; i >= 0; i = reg_next_in_qty[i])
1654 reg_renumber[i] = qty[q].phys_reg + reg_offset[i];
1655 }
1656
1657 /* Clean up. */
1658 free (regs_live_at);
1659 free (qty_order);
1660}
1661\f
1662/* Compare two quantities' priority for getting real registers.
1663 We give shorter-lived quantities higher priority.
1664 Quantities with more references are also preferred, as are quantities that
1665 require multiple registers. This is the identical prioritization as
1666 done by global-alloc.
1667
1668 We used to give preference to registers with *longer* lives, but using
1669 the same algorithm in both local- and global-alloc can speed up execution
1670 of some programs by as much as a factor of three! */
1671
1672/* Note that the quotient will never be bigger than
1673 the value of floor_log2 times the maximum number of
1674 times a register can occur in one insn (surely less than 100)
1675 weighted by frequency (max REG_FREQ_MAX).
1676 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1677 QTY_CMP_PRI is also used by qty_sugg_compare. */
1678
1679#define QTY_CMP_PRI(q) \
1680 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1681 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1682
1683static int
1684qty_compare (int q1, int q2)
1685{
1686 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1687}
1688
1689static int
1690qty_compare_1 (const void *q1p, const void *q2p)
1691{
1692 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1693 int tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1694
1695 if (tem != 0)
1696 return tem;
1697
1698 /* If qtys are equally good, sort by qty number,
1699 so that the results of qsort leave nothing to chance. */
1700 return q1 - q2;
1701}
1702\f
1703/* Compare two quantities' priority for getting real registers. This version
1704 is called for quantities that have suggested hard registers. First priority
1705 goes to quantities that have copy preferences, then to those that have
1706 normal preferences. Within those groups, quantities with the lower
1707 number of preferences have the highest priority. Of those, we use the same
1708 algorithm as above. */
1709
1710#define QTY_CMP_SUGG(q) \
1711 (qty_phys_num_copy_sugg[q] \
1712 ? qty_phys_num_copy_sugg[q] \
1713 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1714
1715static int
1716qty_sugg_compare (int q1, int q2)
1717{
1718 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1719
1720 if (tem != 0)
1721 return tem;
1722
1723 return QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1724}
1725
1726static int
1727qty_sugg_compare_1 (const void *q1p, const void *q2p)
1728{
1729 int q1 = *(const int *) q1p, q2 = *(const int *) q2p;
1730 int tem = QTY_CMP_SUGG (q1) - QTY_CMP_SUGG (q2);
1731
1732 if (tem != 0)
1733 return tem;
1734
1735 tem = QTY_CMP_PRI (q2) - QTY_CMP_PRI (q1);
1736 if (tem != 0)
1737 return tem;
1738
1739 /* If qtys are equally good, sort by qty number,
1740 so that the results of qsort leave nothing to chance. */
1741 return q1 - q2;
1742}
1743
1744#undef QTY_CMP_SUGG
1745#undef QTY_CMP_PRI
1746\f
1747/* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1748 Returns 1 if have done so, or 0 if cannot.
1749
1750 Combining registers means marking them as having the same quantity
1751 and adjusting the offsets within the quantity if either of
1752 them is a SUBREG.
1753
1754 We don't actually combine a hard reg with a pseudo; instead
1755 we just record the hard reg as the suggestion for the pseudo's quantity.
1756 If we really combined them, we could lose if the pseudo lives
1757 across an insn that clobbers the hard reg (eg, movstr).
1758
1759 ALREADY_DEAD is nonzero if USEDREG is known to be dead even though
1760 there is no REG_DEAD note on INSN. This occurs during the processing
1761 of REG_NO_CONFLICT blocks.
1762
1763 MAY_SAVE_COPY is nonzero if this insn is simply copying USEDREG to
1764 SETREG or if the input and output must share a register.
1765 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1766
1767 There are elaborate checks for the validity of combining. */
1768
1769static int
1770combine_regs (rtx usedreg, rtx setreg, int may_save_copy, int insn_number,
1771 rtx insn, int already_dead)
1772{
1773 int ureg, sreg;
1774 int offset = 0;
1775 int usize, ssize;
1776 int sqty;
1777
1778 /* Determine the numbers and sizes of registers being used. If a subreg
1779 is present that does not change the entire register, don't consider
1780 this a copy insn. */
1781
1782 while (GET_CODE (usedreg) == SUBREG)
1783 {
1784 rtx subreg = SUBREG_REG (usedreg);
1785
1786 if (GET_CODE (subreg) == REG)
1787 {
1788 if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
1789 may_save_copy = 0;
1790
1791 if (REGNO (subreg) < FIRST_PSEUDO_REGISTER)
1792 offset += subreg_regno_offset (REGNO (subreg),
1793 GET_MODE (subreg),
1794 SUBREG_BYTE (usedreg),
1795 GET_MODE (usedreg));
1796 else
1797 offset += (SUBREG_BYTE (usedreg)
1798 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1799 }
1800
1801 usedreg = subreg;
1802 }
1803
1804 if (GET_CODE (usedreg) != REG)
1805 return 0;
1806
1807 ureg = REGNO (usedreg);
1808 if (ureg < FIRST_PSEUDO_REGISTER)
1809 usize = HARD_REGNO_NREGS (ureg, GET_MODE (usedreg));
1810 else
1811 usize = ((GET_MODE_SIZE (GET_MODE (usedreg))
1812 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg)) - 1))
1813 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg)));
1814
1815 while (GET_CODE (setreg) == SUBREG)
1816 {
1817 rtx subreg = SUBREG_REG (setreg);
1818
1819 if (GET_CODE (subreg) == REG)
1820 {
1821 if (GET_MODE_SIZE (GET_MODE (subreg)) > UNITS_PER_WORD)
1822 may_save_copy = 0;
1823
1824 if (REGNO (subreg) < FIRST_PSEUDO_REGISTER)
1825 offset -= subreg_regno_offset (REGNO (subreg),
1826 GET_MODE (subreg),
1827 SUBREG_BYTE (setreg),
1828 GET_MODE (setreg));
1829 else
1830 offset -= (SUBREG_BYTE (setreg)
1831 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1832 }
1833
1834 setreg = subreg;
1835 }
1836
1837 if (GET_CODE (setreg) != REG)
1838 return 0;
1839
1840 sreg = REGNO (setreg);
1841 if (sreg < FIRST_PSEUDO_REGISTER)
1842 ssize = HARD_REGNO_NREGS (sreg, GET_MODE (setreg));
1843 else
1844 ssize = ((GET_MODE_SIZE (GET_MODE (setreg))
1845 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg)) - 1))
1846 / REGMODE_NATURAL_SIZE (GET_MODE (setreg)));
1847
1848 /* If UREG is a pseudo-register that hasn't already been assigned a
1849 quantity number, it means that it is not local to this block or dies
1850 more than once. In either event, we can't do anything with it. */
1851 if ((ureg >= FIRST_PSEUDO_REGISTER && reg_qty[ureg] < 0)
1852 /* Do not combine registers unless one fits within the other. */
1853 || (offset > 0 && usize + offset > ssize)
1854 || (offset < 0 && usize + offset < ssize)
1855 /* Do not combine with a smaller already-assigned object
1856 if that smaller object is already combined with something bigger. */
1857 || (ssize > usize && ureg >= FIRST_PSEUDO_REGISTER
1858 && usize < qty[reg_qty[ureg]].size)
1859 /* Can't combine if SREG is not a register we can allocate. */
1860 || (sreg >= FIRST_PSEUDO_REGISTER && reg_qty[sreg] == -1)
1861 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1862 These have already been taken care of. This probably wouldn't
1863 combine anyway, but don't take any chances. */
1864 || (ureg >= FIRST_PSEUDO_REGISTER
1865 && find_reg_note (insn, REG_NO_CONFLICT, usedreg))
1866 /* Don't tie something to itself. In most cases it would make no
1867 difference, but it would screw up if the reg being tied to itself
1868 also dies in this insn. */
1869 || ureg == sreg
1870 /* Don't try to connect two different hardware registers. */
1871 || (ureg < FIRST_PSEUDO_REGISTER && sreg < FIRST_PSEUDO_REGISTER)
1872 /* Don't connect two different machine modes if they have different
1873 implications as to which registers may be used. */
1874 || !MODES_TIEABLE_P (GET_MODE (usedreg), GET_MODE (setreg)))
1875 return 0;
1876
1877 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1878 qty_phys_sugg for the pseudo instead of tying them.
1879
1880 Return "failure" so that the lifespan of UREG is terminated here;
1881 that way the two lifespans will be disjoint and nothing will prevent
1882 the pseudo reg from being given this hard reg. */
1883
1884 if (ureg < FIRST_PSEUDO_REGISTER)
1885 {
1886 /* Allocate a quantity number so we have a place to put our
1887 suggestions. */
1888 if (reg_qty[sreg] == -2)
1889 reg_is_born (setreg, 2 * insn_number);
1890
1891 if (reg_qty[sreg] >= 0)
1892 {
1893 if (may_save_copy
1894 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg))
1895 {
1896 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[sreg]], ureg);
1897 qty_phys_num_copy_sugg[reg_qty[sreg]]++;
1898 }
1899 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg))
1900 {
1901 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[sreg]], ureg);
1902 qty_phys_num_sugg[reg_qty[sreg]]++;
1903 }
1904 }
1905 return 0;
1906 }
1907
1908 /* Similarly for SREG a hard register and UREG a pseudo register. */
1909
1910 if (sreg < FIRST_PSEUDO_REGISTER)
1911 {
1912 if (may_save_copy
1913 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg))
1914 {
1915 SET_HARD_REG_BIT (qty_phys_copy_sugg[reg_qty[ureg]], sreg);
1916 qty_phys_num_copy_sugg[reg_qty[ureg]]++;
1917 }
1918 else if (! TEST_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg))
1919 {
1920 SET_HARD_REG_BIT (qty_phys_sugg[reg_qty[ureg]], sreg);
1921 qty_phys_num_sugg[reg_qty[ureg]]++;
1922 }
1923 return 0;
1924 }
1925
1926 /* At this point we know that SREG and UREG are both pseudos.
1927 Do nothing if SREG already has a quantity or is a register that we
1928 don't allocate. */
1929 if (reg_qty[sreg] >= -1
1930 /* If we are not going to let any regs live across calls,
1931 don't tie a call-crossing reg to a non-call-crossing reg. */
1932 || (current_function_has_nonlocal_label
1933 && ((REG_N_CALLS_CROSSED (ureg) > 0)
1934 != (REG_N_CALLS_CROSSED (sreg) > 0))))
1935 return 0;
1936
1937 /* We don't already know about SREG, so tie it to UREG
1938 if this is the last use of UREG, provided the classes they want
1939 are compatible. */
1940
1941 if ((already_dead || find_regno_note (insn, REG_DEAD, ureg))
1942 && reg_meets_class_p (sreg, qty[reg_qty[ureg]].min_class))
1943 {
1944 /* Add SREG to UREG's quantity. */
1945 sqty = reg_qty[ureg];
1946 reg_qty[sreg] = sqty;
1947 reg_offset[sreg] = reg_offset[ureg] + offset;
1948 reg_next_in_qty[sreg] = qty[sqty].first_reg;
1949 qty[sqty].first_reg = sreg;
1950
1951 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1952 update_qty_class (sqty, sreg);
1953
1954 /* Update info about quantity SQTY. */
1955 qty[sqty].n_calls_crossed += REG_N_CALLS_CROSSED (sreg);
1378ea41
SS
1956 qty[sqty].n_throwing_calls_crossed
1957 += REG_N_THROWING_CALLS_CROSSED (sreg);
003757ed
MD
1958 qty[sqty].n_refs += REG_N_REFS (sreg);
1959 qty[sqty].freq += REG_FREQ (sreg);
1960 if (usize < ssize)
1961 {
1962 int i;
1963
1964 for (i = qty[sqty].first_reg; i >= 0; i = reg_next_in_qty[i])
1965 reg_offset[i] -= offset;
1966
1967 qty[sqty].size = ssize;
1968 qty[sqty].mode = GET_MODE (setreg);
1969 }
1970 }
1971 else
1972 return 0;
1973
1974 return 1;
1975}
1976\f
1977/* Return 1 if the preferred class of REG allows it to be tied
1978 to a quantity or register whose class is CLASS.
1979 True if REG's reg class either contains or is contained in CLASS. */
1980
1981static int
1982reg_meets_class_p (int reg, enum reg_class class)
1983{
1984 enum reg_class rclass = reg_preferred_class (reg);
1985 return (reg_class_subset_p (rclass, class)
1986 || reg_class_subset_p (class, rclass));
1987}
1988
1989/* Update the class of QTYNO assuming that REG is being tied to it. */
1990
1991static void
1992update_qty_class (int qtyno, int reg)
1993{
1994 enum reg_class rclass = reg_preferred_class (reg);
1995 if (reg_class_subset_p (rclass, qty[qtyno].min_class))
1996 qty[qtyno].min_class = rclass;
1997
1998 rclass = reg_alternate_class (reg);
1999 if (reg_class_subset_p (rclass, qty[qtyno].alternate_class))
2000 qty[qtyno].alternate_class = rclass;
2001}
2002\f
2003/* Handle something which alters the value of an rtx REG.
2004
2005 REG is whatever is set or clobbered. SETTER is the rtx that
2006 is modifying the register.
2007
2008 If it is not really a register, we do nothing.
2009 The file-global variables `this_insn' and `this_insn_number'
2010 carry info from `block_alloc'. */
2011
2012static void
2013reg_is_set (rtx reg, rtx setter, void *data ATTRIBUTE_UNUSED)
2014{
2015 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2016 a hard register. These may actually not exist any more. */
2017
2018 if (GET_CODE (reg) != SUBREG
2019 && GET_CODE (reg) != REG)
2020 return;
2021
2022 /* Mark this register as being born. If it is used in a CLOBBER, mark
2023 it as being born halfway between the previous insn and this insn so that
2024 it conflicts with our inputs but not the outputs of the previous insn. */
2025
2026 reg_is_born (reg, 2 * this_insn_number - (GET_CODE (setter) == CLOBBER));
2027}
2028\f
2029/* Handle beginning of the life of register REG.
2030 BIRTH is the index at which this is happening. */
2031
2032static void
2033reg_is_born (rtx reg, int birth)
2034{
2035 int regno;
2036
2037 if (GET_CODE (reg) == SUBREG)
2038 {
2039 regno = REGNO (SUBREG_REG (reg));
2040 if (regno < FIRST_PSEUDO_REGISTER)
2041 regno = subreg_hard_regno (reg, 1);
2042 }
2043 else
2044 regno = REGNO (reg);
2045
2046 if (regno < FIRST_PSEUDO_REGISTER)
2047 {
2048 mark_life (regno, GET_MODE (reg), 1);
2049
2050 /* If the register was to have been born earlier that the present
2051 insn, mark it as live where it is actually born. */
2052 if (birth < 2 * this_insn_number)
2053 post_mark_life (regno, GET_MODE (reg), 1, birth, 2 * this_insn_number);
2054 }
2055 else
2056 {
2057 if (reg_qty[regno] == -2)
2058 alloc_qty (regno, GET_MODE (reg), PSEUDO_REGNO_SIZE (regno), birth);
2059
2060 /* If this register has a quantity number, show that it isn't dead. */
2061 if (reg_qty[regno] >= 0)
2062 qty[reg_qty[regno]].death = -1;
2063 }
2064}
2065
2066/* Record the death of REG in the current insn. If OUTPUT_P is nonzero,
2067 REG is an output that is dying (i.e., it is never used), otherwise it
2068 is an input (the normal case).
2069 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2070
2071static void
2072wipe_dead_reg (rtx reg, int output_p)
2073{
2074 int regno = REGNO (reg);
2075
2076 /* If this insn has multiple results,
2077 and the dead reg is used in one of the results,
2078 extend its life to after this insn,
2079 so it won't get allocated together with any other result of this insn.
2080
2081 It is unsafe to use !single_set here since it will ignore an unused
2082 output. Just because an output is unused does not mean the compiler
2083 can assume the side effect will not occur. Consider if REG appears
2084 in the address of an output and we reload the output. If we allocate
2085 REG to the same hard register as an unused output we could set the hard
2086 register before the output reload insn. */
2087 if (GET_CODE (PATTERN (this_insn)) == PARALLEL
2088 && multiple_sets (this_insn))
2089 {
2090 int i;
2091 for (i = XVECLEN (PATTERN (this_insn), 0) - 1; i >= 0; i--)
2092 {
2093 rtx set = XVECEXP (PATTERN (this_insn), 0, i);
2094 if (GET_CODE (set) == SET
2095 && GET_CODE (SET_DEST (set)) != REG
2096 && !rtx_equal_p (reg, SET_DEST (set))
2097 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
2098 output_p = 1;
2099 }
2100 }
2101
2102 /* If this register is used in an auto-increment address, then extend its
2103 life to after this insn, so that it won't get allocated together with
2104 the result of this insn. */
2105 if (! output_p && find_regno_note (this_insn, REG_INC, regno))
2106 output_p = 1;
2107
2108 if (regno < FIRST_PSEUDO_REGISTER)
2109 {
2110 mark_life (regno, GET_MODE (reg), 0);
2111
2112 /* If a hard register is dying as an output, mark it as in use at
2113 the beginning of this insn (the above statement would cause this
2114 not to happen). */
2115 if (output_p)
2116 post_mark_life (regno, GET_MODE (reg), 1,
2117 2 * this_insn_number, 2 * this_insn_number + 1);
2118 }
2119
2120 else if (reg_qty[regno] >= 0)
2121 qty[reg_qty[regno]].death = 2 * this_insn_number + output_p;
2122}
2123\f
2124/* Find a block of SIZE words of hard regs in reg_class CLASS
2125 that can hold something of machine-mode MODE
2126 (but actually we test only the first of the block for holding MODE)
2127 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2128 and return the number of the first of them.
2129 Return -1 if such a block cannot be found.
2130 If QTYNO crosses calls, insist on a register preserved by calls,
2131 unless ACCEPT_CALL_CLOBBERED is nonzero.
2132
2133 If JUST_TRY_SUGGESTED is nonzero, only try to see if the suggested
2134 register is available. If not, return -1. */
2135
2136static int
2137find_free_reg (enum reg_class class, enum machine_mode mode, int qtyno,
2138 int accept_call_clobbered, int just_try_suggested,
2139 int born_index, int dead_index)
2140{
2141 int i, ins;
2142 HARD_REG_SET first_used, used;
2143#ifdef ELIMINABLE_REGS
2144 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
2145#endif
2146
2147 /* Validate our parameters. */
2148 if (born_index < 0 || born_index > dead_index)
2149 abort ();
2150
2151 /* Don't let a pseudo live in a reg across a function call
2152 if we might get a nonlocal goto. */
2153 if (current_function_has_nonlocal_label
2154 && qty[qtyno].n_calls_crossed > 0)
2155 return -1;
2156
2157 if (accept_call_clobbered)
2158 COPY_HARD_REG_SET (used, call_fixed_reg_set);
2159 else if (qty[qtyno].n_calls_crossed == 0)
2160 COPY_HARD_REG_SET (used, fixed_reg_set);
2161 else
2162 COPY_HARD_REG_SET (used, call_used_reg_set);
2163
2164 if (accept_call_clobbered)
2165 IOR_HARD_REG_SET (used, losing_caller_save_reg_set);
2166
2167 for (ins = born_index; ins < dead_index; ins++)
2168 IOR_HARD_REG_SET (used, regs_live_at[ins]);
2169
2170 IOR_COMPL_HARD_REG_SET (used, reg_class_contents[(int) class]);
2171
2172 /* Don't use the frame pointer reg in local-alloc even if
2173 we may omit the frame pointer, because if we do that and then we
2174 need a frame pointer, reload won't know how to move the pseudo
2175 to another hard reg. It can move only regs made by global-alloc.
2176
2177 This is true of any register that can be eliminated. */
2178#ifdef ELIMINABLE_REGS
2179 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++)
2180 SET_HARD_REG_BIT (used, eliminables[i].from);
2181#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2182 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2183 that it might be eliminated into. */
2184 SET_HARD_REG_BIT (used, HARD_FRAME_POINTER_REGNUM);
2185#endif
2186#else
2187 SET_HARD_REG_BIT (used, FRAME_POINTER_REGNUM);
2188#endif
2189
2190#ifdef CANNOT_CHANGE_MODE_CLASS
2191 cannot_change_mode_set_regs (&used, mode, qty[qtyno].first_reg);
2192#endif
2193
2194 /* Normally, the registers that can be used for the first register in
2195 a multi-register quantity are the same as those that can be used for
2196 subsequent registers. However, if just trying suggested registers,
2197 restrict our consideration to them. If there are copy-suggested
2198 register, try them. Otherwise, try the arithmetic-suggested
2199 registers. */
2200 COPY_HARD_REG_SET (first_used, used);
2201
2202 if (just_try_suggested)
2203 {
2204 if (qty_phys_num_copy_sugg[qtyno] != 0)
2205 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_copy_sugg[qtyno]);
2206 else
2207 IOR_COMPL_HARD_REG_SET (first_used, qty_phys_sugg[qtyno]);
2208 }
2209
2210 /* If all registers are excluded, we can't do anything. */
2211 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) ALL_REGS], first_used, fail);
2212
2213 /* If at least one would be suitable, test each hard reg. */
2214
2215 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2216 {
2217#ifdef REG_ALLOC_ORDER
2218 int regno = reg_alloc_order[i];
2219#else
2220 int regno = i;
2221#endif
2222 if (! TEST_HARD_REG_BIT (first_used, regno)
2223 && HARD_REGNO_MODE_OK (regno, mode)
2224 && (qty[qtyno].n_calls_crossed == 0
2225 || accept_call_clobbered
2226 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)))
2227 {
2228 int j;
2229 int size1 = HARD_REGNO_NREGS (regno, mode);
2230 for (j = 1; j < size1 && ! TEST_HARD_REG_BIT (used, regno + j); j++);
2231 if (j == size1)
2232 {
2233 /* Mark that this register is in use between its birth and death
2234 insns. */
2235 post_mark_life (regno, mode, 1, born_index, dead_index);
2236 return regno;
2237 }
2238#ifndef REG_ALLOC_ORDER
2239 /* Skip starting points we know will lose. */
2240 i += j;
2241#endif
2242 }
2243 }
2244
2245 fail:
2246 /* If we are just trying suggested register, we have just tried copy-
2247 suggested registers, and there are arithmetic-suggested registers,
2248 try them. */
2249
2250 /* If it would be profitable to allocate a call-clobbered register
2251 and save and restore it around calls, do that. */
2252 if (just_try_suggested && qty_phys_num_copy_sugg[qtyno] != 0
2253 && qty_phys_num_sugg[qtyno] != 0)
2254 {
2255 /* Don't try the copy-suggested regs again. */
2256 qty_phys_num_copy_sugg[qtyno] = 0;
2257 return find_free_reg (class, mode, qtyno, accept_call_clobbered, 1,
2258 born_index, dead_index);
2259 }
2260
2261 /* We need not check to see if the current function has nonlocal
2262 labels because we don't put any pseudos that are live over calls in
1378ea41
SS
2263 registers in that case. Avoid putting pseudos crossing calls that
2264 might throw into call used registers. */
003757ed
MD
2265
2266 if (! accept_call_clobbered
2267 && flag_caller_saves
2268 && ! just_try_suggested
2269 && qty[qtyno].n_calls_crossed != 0
1378ea41 2270 && qty[qtyno].n_throwing_calls_crossed == 0
003757ed
MD
2271 && CALLER_SAVE_PROFITABLE (qty[qtyno].n_refs,
2272 qty[qtyno].n_calls_crossed))
2273 {
2274 i = find_free_reg (class, mode, qtyno, 1, 0, born_index, dead_index);
2275 if (i >= 0)
2276 caller_save_needed = 1;
2277 return i;
2278 }
2279 return -1;
2280}
2281\f
2282/* Mark that REGNO with machine-mode MODE is live starting from the current
2283 insn (if LIFE is nonzero) or dead starting at the current insn (if LIFE
2284 is zero). */
2285
2286static void
2287mark_life (int regno, enum machine_mode mode, int life)
2288{
2289 int j = HARD_REGNO_NREGS (regno, mode);
2290 if (life)
2291 while (--j >= 0)
2292 SET_HARD_REG_BIT (regs_live, regno + j);
2293 else
2294 while (--j >= 0)
2295 CLEAR_HARD_REG_BIT (regs_live, regno + j);
2296}
2297
2298/* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2299 is nonzero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2300 to insn number DEATH (exclusive). */
2301
2302static void
2303post_mark_life (int regno, enum machine_mode mode, int life, int birth,
2304 int death)
2305{
2306 int j = HARD_REGNO_NREGS (regno, mode);
2307 HARD_REG_SET this_reg;
2308
2309 CLEAR_HARD_REG_SET (this_reg);
2310 while (--j >= 0)
2311 SET_HARD_REG_BIT (this_reg, regno + j);
2312
2313 if (life)
2314 while (birth < death)
2315 {
2316 IOR_HARD_REG_SET (regs_live_at[birth], this_reg);
2317 birth++;
2318 }
2319 else
2320 while (birth < death)
2321 {
2322 AND_COMPL_HARD_REG_SET (regs_live_at[birth], this_reg);
2323 birth++;
2324 }
2325}
2326\f
2327/* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2328 is the register being clobbered, and R1 is a register being used in
2329 the equivalent expression.
2330
2331 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2332 in which it is used, return 1.
2333
2334 Otherwise, return 0. */
2335
2336static int
2337no_conflict_p (rtx insn, rtx r0 ATTRIBUTE_UNUSED, rtx r1)
2338{
2339 int ok = 0;
2340 rtx note = find_reg_note (insn, REG_LIBCALL, NULL_RTX);
2341 rtx p, last;
2342
2343 /* If R1 is a hard register, return 0 since we handle this case
2344 when we scan the insns that actually use it. */
2345
2346 if (note == 0
2347 || (GET_CODE (r1) == REG && REGNO (r1) < FIRST_PSEUDO_REGISTER)
2348 || (GET_CODE (r1) == SUBREG && GET_CODE (SUBREG_REG (r1)) == REG
2349 && REGNO (SUBREG_REG (r1)) < FIRST_PSEUDO_REGISTER))
2350 return 0;
2351
2352 last = XEXP (note, 0);
2353
2354 for (p = NEXT_INSN (insn); p && p != last; p = NEXT_INSN (p))
2355 if (INSN_P (p))
2356 {
2357 if (find_reg_note (p, REG_DEAD, r1))
2358 ok = 1;
2359
2360 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2361 some earlier optimization pass has inserted instructions into
2362 the sequence, and it is not safe to perform this optimization.
2363 Note that emit_no_conflict_block always ensures that this is
2364 true when these sequences are created. */
2365 if (! find_reg_note (p, REG_NO_CONFLICT, r1))
2366 return 0;
2367 }
2368
2369 return ok;
2370}
2371\f
2372/* Return the number of alternatives for which the constraint string P
2373 indicates that the operand must be equal to operand 0 and that no register
2374 is acceptable. */
2375
2376static int
2377requires_inout (const char *p)
2378{
2379 char c;
2380 int found_zero = 0;
2381 int reg_allowed = 0;
2382 int num_matching_alts = 0;
2383 int len;
2384
2385 for ( ; (c = *p); p += len)
2386 {
2387 len = CONSTRAINT_LEN (c, p);
2388 switch (c)
2389 {
2390 case '=': case '+': case '?':
2391 case '#': case '&': case '!':
2392 case '*': case '%':
2393 case 'm': case '<': case '>': case 'V': case 'o':
2394 case 'E': case 'F': case 'G': case 'H':
2395 case 's': case 'i': case 'n':
2396 case 'I': case 'J': case 'K': case 'L':
2397 case 'M': case 'N': case 'O': case 'P':
2398 case 'X':
2399 /* These don't say anything we care about. */
2400 break;
2401
2402 case ',':
2403 if (found_zero && ! reg_allowed)
2404 num_matching_alts++;
2405
2406 found_zero = reg_allowed = 0;
2407 break;
2408
2409 case '0':
2410 found_zero = 1;
2411 break;
2412
2413 case '1': case '2': case '3': case '4': case '5':
2414 case '6': case '7': case '8': case '9':
2415 /* Skip the balance of the matching constraint. */
2416 do
2417 p++;
2418 while (ISDIGIT (*p));
2419 len = 0;
2420 break;
2421
2422 default:
2423 if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS
2424 && !EXTRA_ADDRESS_CONSTRAINT (c, p))
2425 break;
2426 /* Fall through. */
2427 case 'p':
2428 case 'g': case 'r':
2429 reg_allowed = 1;
2430 break;
2431 }
2432 }
2433
2434 if (found_zero && ! reg_allowed)
2435 num_matching_alts++;
2436
2437 return num_matching_alts;
2438}
2439\f
2440void
2441dump_local_alloc (FILE *file)
2442{
2443 int i;
2444 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
2445 if (reg_renumber[i] != -1)
2446 fprintf (file, ";; Register %d in %d.\n", i, reg_renumber[i]);
2447}