2 **********************************************************************
3 * emu10k1.h, derived from 8010.h
4 * Copyright 1999-2001 Creative Labs, Inc.
6 **********************************************************************
8 * Date Author Summary of changes
9 * ---- ------ ------------------
10 * October 20, 1999 Bertrand Lee base code release
11 * November 2, 1999 Alan Cox Cleaned of 8bit chars, DOS
13 * December 8, 1999 Jon Taylor Added lots of new register info
14 * May 16, 2001 Daniel Bertrand Added unofficial DBG register info
15 * Oct-Nov 2001 D.B. Added unofficial Audigy registers
17 **********************************************************************
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public
30 * License along with this program; if not, write to the Free
31 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139,
35 **********************************************************************
36 * $FreeBSD: src/sys/gnu/dev/sound/pci/emu10k1.h,v 1.8 2005/01/06 18:27:30 imp Exp $
37 * $DragonFly: src/sys/dev/sound/pci/gnu/emu10k1.h,v 1.4 2007/01/04 21:47:03 corecode Exp $
45 #include <linux/types.h>
51 #define DRIVER_VERSION "0.20a"
54 /* Audigy specify registers are prefixed with 'A_' */
56 /************************************************************************************************/
57 /* PCI function 0 registers, address = <val> + PCIBASE0 */
58 /************************************************************************************************/
60 #define PTR 0x00 /* Indexed register set pointer register */
61 /* NOTE: The CHANNELNUM and ADDRESS words can */
62 /* be modified independently of each other. */
63 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
64 /* channel number of the register to be */
65 /* accessed. For non per-channel registers the */
66 /* value should be set to zero. */
67 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
69 #define DATA 0x04 /* Indexed register set data register */
71 #define IPR 0x08 /* Global interrupt pending register */
72 /* Clear pending interrupts by writing a 1 to */
73 /* the relevant bits and zero to the other bits */
75 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
76 #define A_IPR_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
77 #define A_IPR_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
79 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
80 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
81 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
82 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
83 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
84 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
85 #define IPR_MUTE 0x00040000 /* Mute button pressed */
86 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
87 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
88 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
89 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
90 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
91 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
92 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
93 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
94 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
95 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
96 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
97 #define IPR_CHANNELLOOP 0x00000040 /* One or more channel loop interrupts pending */
98 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
99 /* Highest set channel in CLIPL or CLIPH. When */
100 /* IP is written with CL set, the bit in CLIPL */
101 /* or CLIPH corresponding to the CIN value */
102 /* written will be cleared. */
103 #define A_IPR_MIDITRANSBUFEMPTY1 IPR_MIDITRANSBUFEMPTY /* MIDI UART transmit buffer empty */
104 #define A_IPR_MIDIRECVBUFEMPTY1 IPR_MIDIRECVBUFEMPTY /* MIDI UART receive buffer empty */
108 #define INTE 0x0c /* Interrupt enable register */
109 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
110 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
111 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
112 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
113 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
114 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
115 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
116 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
117 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
118 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
119 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
120 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
121 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
122 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
123 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
124 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
125 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
126 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
128 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
129 /* NOTE: There is no reason to use this under */
130 /* Linux, and it will cause odd hardware */
131 /* behavior and possibly random segfaults and */
132 /* lockups if enabled. */
134 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
135 #define A_INTE_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
136 #define A_INTE_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
139 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
140 /* NOTE: This bit must always be enabled */
141 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
142 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
143 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
144 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
145 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
146 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
147 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
148 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
149 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
150 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
151 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
152 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
153 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
155 /* The next two interrupts are for the midi port on the Audigy (A_MPU2) */
156 #define A_INTE_MIDITXENABLE1 INTE_MIDITXENABLE
157 #define A_INTE_MIDIRXENABLE1 INTE_MIDIRXENABLE
159 #define WC 0x10 /* Wall Clock register */
160 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
161 #define WC_SAMPLECOUNTER 0x14060010
162 #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
163 /* NOTE: Each channel takes 1/64th of a sample */
164 /* period to be serviced. */
166 #define HCFG 0x14 /* Hardware config register */
167 /* NOTE: There is no reason to use the legacy */
168 /* SoundBlaster emulation stuff described below */
169 /* under Linux, and all kinds of weird hardware */
170 /* behavior can result if you try. Don't. */
171 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
172 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
173 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
174 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
175 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
176 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
177 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
178 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
179 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
180 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
181 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
182 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
183 /* NOTE: The rest of the bits in this register */
184 /* _are_ relevant under Linux. */
185 #define HCFG_CODECFORMAT_MASK 0x00070000 /* CODEC format */
186 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
187 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
188 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
189 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
191 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
192 #define HCFG_GPOUT0 0x00001000 /* set to enable digital out on 5.1 cards */
194 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
195 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
196 /* 1 = Force all 3 async digital inputs to use */
197 /* the same async sample rate tracker (ZVIDEO) */
198 #define HCFG_AC3ENABLE_MASK 0x0x0000e0 /* AC3 async input control - Not implemented */
199 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
200 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
201 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
202 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
203 /* will automatically mute their output when */
204 /* they are not rate-locked to the external */
205 /* async audio source */
206 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
207 /* NOTE: This should generally never be used. */
208 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
209 /* NOTE: This should generally never be used. */
210 #define HCFG_LOCKTANKCACHE 0x01020014
211 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
212 /* NOTE: This is a 'cheap' way to implement a */
213 /* master mute function on the mute button, and */
214 /* in general should not be used unless a more */
215 /* sophisticated master mute function has not */
217 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
218 /* Should be set to 1 when the EMU10K1 is */
219 /* completely initialized. */
221 /* For Audigy, MPU port move to 0x70-0x74 ptr register */
223 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
225 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
226 #define MUCMD_RESET 0xff /* RESET command */
227 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
228 /* NOTE: All other commands are ignored */
230 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
231 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
232 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
234 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
235 #define A_GPINPUT_MASK 0xff00
236 #define A_GPOUTPUT_MASK 0x00ff
238 #define TIMER 0x1a /* Timer terminal count register (16-bit) */
239 /* NOTE: After the rate is changed, a maximum */
240 /* of 1024 sample periods should be allowed */
241 /* before the new rate is guaranteed accurate. */
242 #define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */
243 /* 0 == 1024 periods, [1..4] are not useful */
245 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
247 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
248 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
249 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
251 /********************************************************************************************************/
252 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
253 /********************************************************************************************************/
255 #define CPF 0x00 /* Current pitch and fraction register */
256 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
257 #define CPF_CURRENTPITCH 0x10100000
258 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
259 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
260 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
262 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
263 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
264 #define PTRX_PITCHTARGET 0x10100001
265 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
266 #define PTRX_FXSENDAMOUNT_A 0x08080001
267 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
268 #define PTRX_FXSENDAMOUNT_B 0x08000001
270 #define CVCF 0x02 /* Current volume and filter cutoff register */
271 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
272 #define CVCF_CURRENTVOL 0x10100002
273 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
274 #define CVCF_CURRENTFILTER 0x10000002
276 #define VTFT 0x03 /* Volume target and filter cutoff target register */
277 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
278 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
280 #define Z1 0x05 /* Filter delay memory 1 register */
282 #define Z2 0x04 /* Filter delay memory 2 register */
284 #define PSST 0x06 /* Send C amount and loop start address register */
285 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
287 #define PSST_FXSENDAMOUNT_C 0x08180006
289 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
290 #define PSST_LOOPSTARTADDR 0x18000006
292 #define DSL 0x07 /* Send D amount and loop start address register */
293 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
295 #define DSL_FXSENDAMOUNT_D 0x08180007
297 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
298 #define DSL_LOOPENDADDR 0x18000007
300 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
301 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
302 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
303 /* 1 == full band, 7 == lowpass */
304 /* ROM 0 is used when pitch shifting downward or less */
305 /* then 3 semitones upward. Increasingly higher ROM */
306 /* numbers are used, typically in steps of 3 semitones, */
307 /* as upward pitch shifting is performed. */
308 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
309 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
310 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
311 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
312 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
313 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
314 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
315 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
316 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
317 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
318 #define CCCA_CURRADDR 0x18000008
320 #define CCR 0x09 /* Cache control register */
321 #define CCR_CACHEINVALIDSIZE 0x07190009
322 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
323 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
324 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
325 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
326 #define CCR_READADDRESS 0x06100009
327 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
328 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
329 /* NOTE: This is valid only if CACHELOOPFLAG is set */
330 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
331 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
333 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
334 /* NOTE: This register is normally not used */
335 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
337 #define FXRT 0x0b /* Effects send routing register */
338 /* NOTE: It is illegal to assign the same routing to */
339 /* two effects sends. */
340 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
341 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
342 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
343 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
345 #define MAPA 0x0c /* Cache map A */
347 #define MAPB 0x0d /* Cache map B */
349 #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
350 #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
352 #define ENVVOL 0x10 /* Volume envelope register */
353 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
354 /* 0x8000-n == 666*n usec delay */
356 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
357 #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
358 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
359 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
360 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
362 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
363 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
364 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
365 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
366 /* this channel and from writing to pitch, filter and */
367 /* volume targets. */
368 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
369 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
371 #define LFOVAL1 0x13 /* Modulation LFO value */
372 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
373 /* 0x8000-n == 666*n usec delay */
375 #define ENVVAL 0x14 /* Modulation envelope register */
376 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
377 /* 0x8000-n == 666*n usec delay */
379 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
380 #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
381 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
382 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
383 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
385 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
386 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
387 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
388 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
389 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
391 #define LFOVAL2 0x17 /* Vibrato LFO register */
392 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
393 /* 0x8000-n == 666*n usec delay */
395 #define IP 0x18 /* Initial pitch register */
396 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
397 /* 4 bits of octave, 12 bits of fractional octave */
398 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
400 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
401 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
402 /* 6 most significant bits are semitones */
403 /* 2 least significant bits are fractions */
404 #define IFATN_FILTERCUTOFF 0x08080019
405 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
406 #define IFATN_ATTENUATION 0x08000019
409 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
410 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
411 /* Signed 2's complement, +/- one octave peak extremes */
412 #define PEFE_PITCHAMOUNT 0x0808001a
413 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
414 /* Signed 2's complement, +/- six octaves peak extremes */
415 #define PEFE_FILTERAMOUNT 0x0800001a
416 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
417 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
418 /* Signed 2's complement, +/- one octave extremes */
419 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
420 /* Signed 2's complement, +/- three octave extremes */
423 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
424 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
425 /* Signed 2's complement, with +/- 12dB extremes */
426 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
427 /* ??Hz steps, maximum of ?? Hz. */
429 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
430 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
431 /* Signed 2's complement, +/- one octave extremes */
432 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
433 /* 0.039Hz steps, maximum of 9.85 Hz. */
435 #define TEMPENV 0x1e /* Tempory envelope register */
436 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
437 /* NOTE: All channels contain internal variables; do */
438 /* not write to these locations. */
440 #define CD0 0x20 /* Cache data 0 register */
441 #define CD1 0x21 /* Cache data 1 register */
442 #define CD2 0x22 /* Cache data 2 register */
443 #define CD3 0x23 /* Cache data 3 register */
444 #define CD4 0x24 /* Cache data 4 register */
445 #define CD5 0x25 /* Cache data 5 register */
446 #define CD6 0x26 /* Cache data 6 register */
447 #define CD7 0x27 /* Cache data 7 register */
448 #define CD8 0x28 /* Cache data 8 register */
449 #define CD9 0x29 /* Cache data 9 register */
450 #define CDA 0x2a /* Cache data A register */
451 #define CDB 0x2b /* Cache data B register */
452 #define CDC 0x2c /* Cache data C register */
453 #define CDD 0x2d /* Cache data D register */
454 #define CDE 0x2e /* Cache data E register */
455 #define CDF 0x2f /* Cache data F register */
457 #define PTB 0x40 /* Page table base register */
458 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
460 #define TCB 0x41 /* Tank cache base register */
461 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
463 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
464 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
465 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
466 /* NOTE: To guarantee phase coherency, both channels */
467 /* must be disabled prior to enabling both channels. */
468 #define A_ADCCR_RCHANENABLE 0x00000020
469 #define A_ADCCR_LCHANENABLE 0x00000010
471 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
472 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
474 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
475 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
476 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
477 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
478 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
479 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
480 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
481 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
483 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
484 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
485 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
487 #define FXWC 0x43 /* FX output write channels register */
488 /* When set, each bit enables the writing of the */
489 /* corresponding FX output channel (internal registers */
490 /* 0x20-0x3f) into host memory. This mode of recording */
491 /* is 16bit, 48KHz only. All 32 channels can be enabled */
492 /* simultaneously. */
493 #define TCBS 0x44 /* Tank cache buffer size register */
494 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
495 #define TCBS_BUFFSIZE_16K 0x00000000
496 #define TCBS_BUFFSIZE_32K 0x00000001
497 #define TCBS_BUFFSIZE_64K 0x00000002
498 #define TCBS_BUFFSIZE_128K 0x00000003
499 #define TCBS_BUFFSIZE_256K 0x00000004
500 #define TCBS_BUFFSIZE_512K 0x00000005
501 #define TCBS_BUFFSIZE_1024K 0x00000006
502 #define TCBS_BUFFSIZE_2048K 0x00000007
504 #define MICBA 0x45 /* AC97 microphone buffer address register */
505 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
507 #define ADCBA 0x46 /* ADC buffer address register */
508 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
510 #define FXBA 0x47 /* FX Buffer Address */
511 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
513 #define MICBS 0x49 /* Microphone buffer size register */
515 #define ADCBS 0x4a /* ADC buffer size register */
517 #define FXBS 0x4b /* FX buffer size register */
519 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
520 #define ADCBS_BUFSIZE_NONE 0x00000000
521 #define ADCBS_BUFSIZE_384 0x00000001
522 #define ADCBS_BUFSIZE_448 0x00000002
523 #define ADCBS_BUFSIZE_512 0x00000003
524 #define ADCBS_BUFSIZE_640 0x00000004
525 #define ADCBS_BUFSIZE_768 0x00000005
526 #define ADCBS_BUFSIZE_896 0x00000006
527 #define ADCBS_BUFSIZE_1024 0x00000007
528 #define ADCBS_BUFSIZE_1280 0x00000008
529 #define ADCBS_BUFSIZE_1536 0x00000009
530 #define ADCBS_BUFSIZE_1792 0x0000000a
531 #define ADCBS_BUFSIZE_2048 0x0000000b
532 #define ADCBS_BUFSIZE_2560 0x0000000c
533 #define ADCBS_BUFSIZE_3072 0x0000000d
534 #define ADCBS_BUFSIZE_3584 0x0000000e
535 #define ADCBS_BUFSIZE_4096 0x0000000f
536 #define ADCBS_BUFSIZE_5120 0x00000010
537 #define ADCBS_BUFSIZE_6144 0x00000011
538 #define ADCBS_BUFSIZE_7168 0x00000012
539 #define ADCBS_BUFSIZE_8192 0x00000013
540 #define ADCBS_BUFSIZE_10240 0x00000014
541 #define ADCBS_BUFSIZE_12288 0x00000015
542 #define ADCBS_BUFSIZE_14366 0x00000016
543 #define ADCBS_BUFSIZE_16384 0x00000017
544 #define ADCBS_BUFSIZE_20480 0x00000018
545 #define ADCBS_BUFSIZE_24576 0x00000019
546 #define ADCBS_BUFSIZE_28672 0x0000001a
547 #define ADCBS_BUFSIZE_32768 0x0000001b
548 #define ADCBS_BUFSIZE_40960 0x0000001c
549 #define ADCBS_BUFSIZE_49152 0x0000001d
550 #define ADCBS_BUFSIZE_57344 0x0000001e
551 #define ADCBS_BUFSIZE_65536 0x0000001f
554 #define CDCS 0x50 /* CD-ROM digital channel status register */
556 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
558 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
560 /* definitions for debug register - taken from the alsa drivers */
561 #define DBG_ZC 0x80000000 /* zero tram counter */
562 #define DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
563 #define DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
564 #define DBG_SINGLE_STEP 0x00008000 /* single step mode */
565 #define DBG_STEP 0x00004000 /* start single step */
566 #define DBG_CONDITION_CODE 0x00003e00 /* condition code */
567 #define DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
570 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
573 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
574 #define A_DBG_ZC 0x40000000 /* zero tram counter */
575 #define A_DBG_STEP_ADDR 0x000003ff
576 #define A_DBG_SATURATION_OCCURED 0x20000000
577 #define A_DBG_SATURATION_ADDR 0x0ffc0000
579 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
581 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
583 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
585 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
586 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
587 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
588 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
589 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
590 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
591 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
592 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
593 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
594 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
595 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
596 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
597 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
598 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
599 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
600 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
601 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
602 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
603 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
604 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
605 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
606 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
607 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
609 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
610 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
612 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
614 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
616 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
618 #define SOLEL 0x5c /* Stop on loop enable low register */
620 #define SOLEH 0x5d /* Stop on loop enable high register */
622 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
623 #define SPBYPASS_ENABLE 0x00000001 /* Enable SPDIF bypass mode */
625 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
626 #define AC97SLOT_CNTR 0x10 /* Center enable */
627 #define AC97SLOT_LFE 0x20 /* LFE enable */
629 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
631 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
633 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
634 /* NOTE: This one has no SPDIFLOCKED field */
635 /* Assumes sample lock */
637 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
638 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
639 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
640 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
643 /* Note that these values can vary +/- by a small amount */
644 #define SRCS_SPDIFRATE_44 0x0003acd9
645 #define SRCS_SPDIFRATE_48 0x00040000
646 #define SRCS_SPDIFRATE_96 0x00080000
648 #define MICIDX 0x63 /* Microphone recording buffer index register */
649 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
650 #define MICIDX_IDX 0x10000063
652 #define A_ADCIDX 0x63
653 #define A_ADCIDX_IDX 0x10000063
655 #define ADCIDX 0x64 /* ADC recording buffer index register */
656 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
657 #define ADCIDX_IDX 0x10000064
659 #define FXIDX 0x65 /* FX recording buffer index register */
660 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
661 #define FXIDX_IDX 0x10000065
663 /* This is the MPU port on the card (via the game port) */
664 #define A_MUDATA1 0x70
665 #define A_MUCMD1 0x71
666 #define A_MUSTAT1 A_MUCMD1
668 /* This is the MPU port on the Audigy Drive */
669 #define A_MUDATA2 0x72
670 #define A_MUCMD2 0x73
671 #define A_MUSTAT2 A_MUCMD2
673 /* The next two are the Audigy equivalent of FXWC */
674 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
675 /* Each bit selects a channel for recording */
676 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
677 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
679 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
680 #define A_SPDIF_48000 0x00000080
681 #define A_SPDIF_44100 0x00000000
682 #define A_SPDIF_96000 0x00000040
685 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
686 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
687 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
688 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
690 #define A_SENDAMOUNTS 0x7d
691 #define A_FXSENDAMOUNT_E_MASK 0xff000000
692 #define A_FXSENDAMOUNT_F_MASK 0x00ff0000
693 #define A_FXSENDAMOUNT_G_MASK 0x0000ff00
694 #define A_FXSENDAMOUNT_H_MASK 0x000000ff
696 /* The send amounts for this one are the same as used with the emu10k1 */
698 #define A_FXRT_CHANNELA 0x0000003f
699 #define A_FXRT_CHANNELB 0x00003f00
700 #define A_FXRT_CHANNELC 0x003f0000
701 #define A_FXRT_CHANNELD 0x3f000000
704 /* Each FX general purpose register is 32 bits in length, all bits are used */
705 #define FXGPREGBASE 0x100 /* FX general purpose registers base */
706 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
707 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
708 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
709 /* locations are for external TRAM. */
710 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
711 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
713 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
714 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
715 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
716 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
717 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
718 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
719 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
721 #define MICROCODEBASE 0x400 /* Microcode data base address */
723 /* Each DSP microcode instruction is mapped into 2 doublewords */
724 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
725 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
726 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
727 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
728 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
729 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
732 /* Audigy Soundcard have a different instruction format */
733 #define AUDIGY_CODEBASE 0x600
734 #define A_LOWORD_OPY_MASK 0x000007ff
735 #define A_LOWORD_OPX_MASK 0x007ff000
736 #define A_HIWORD_OPCODE_MASK 0x0f000000
737 #define A_HIWORD_RESULT_MASK 0x007ff000
738 #define A_HIWORD_OPA_MASK 0x000007ff
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