2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2004, Scott Long <scottl@kfreebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/i386/pci/pci_cfgreg.c,v 1.124.2.3 2009/05/04 21:04:29 jhb
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/thread2.h>
39 #include <sys/spinlock.h>
40 #include <sys/spinlock2.h>
41 #include <sys/queue.h>
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
44 #include "pci_cfgreg.h"
45 #include <machine/pc/bios.h>
48 #include <vm/vm_param.h>
49 #include <vm/vm_kern.h>
50 #include <vm/vm_extern.h>
52 #include <machine/pmap.h>
54 #if defined(__DragonFly__)
55 #define mtx_init(a, b, c, d) spin_init(a)
56 #define mtx_lock_spin(a) spin_lock(a)
57 #define mtx_unlock_spin(a) spin_unlock(a)
60 #define PRVERB(a) do { \
66 struct pcie_cfg_elem {
67 TAILQ_ENTRY(pcie_cfg_elem) elem;
79 static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
80 static uint64_t pcie_base;
81 static int pcie_minbus, pcie_maxbus;
82 static uint32_t pcie_badslots;
85 #if defined(__DragonFly__)
86 static struct spinlock pcicfg_mtx;
88 static struct mtx pcicfg_mtx;
90 static int mcfg_enable = 0;
92 TUNABLE_INT("hw.pci.mcfg", &mcfg_enable);
94 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg, int bytes);
95 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
96 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
97 static int pcireg_cfgopen(void);
99 static int pciereg_cfgread(int bus, unsigned slot, unsigned func,
100 unsigned reg, unsigned bytes);
101 static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
102 unsigned reg, int data, unsigned bytes);
107 * Some BIOS writers seem to want to ignore the spec and put
108 * 0 in the intline rather than 255 to indicate none. Some use
109 * numbers in the range 128-254 to indicate something strange and
110 * apparently undocumented anywhere. Assume these are completely bogus
111 * and map them to 255, which means "none".
114 pci_i386_map_intline(int line)
116 if (line == 0 || line >= 128)
117 return (PCI_INVALID_IRQ);
122 pcibios_get_version(void)
124 struct bios_regs args;
126 if (PCIbios.ventry == 0) {
127 PRVERB(("pcibios: No call entry point\n"));
130 args.eax = PCIBIOS_BIOS_PRESENT;
131 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
132 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
135 if (args.edx != 0x20494350) {
136 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
139 return (args.ebx & 0xffff);
143 * Initialise access to PCI configuration space
148 static int opened = 0;
155 if (cfgmech == CFGMECH_NONE && pcireg_cfgopen() == 0)
158 v = pcibios_get_version();
160 PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
162 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
165 /* $PIR requires PCI BIOS 2.10 or greater. */
169 if (cfgmech == CFGMECH_PCIE)
173 * Grope around in the PCI config space to see if this is a
174 * chipset that is capable of doing memory-mapped config cycles.
175 * This also implies that it can do PCIe extended config cycles.
178 /* Check for supported chipsets */
179 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
180 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
186 /* Intel 7520 or 7320 */
187 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
188 pcie_cfgregopen(pciebar, 0, 255);
193 /* Intel 915, 925, or 915GM */
194 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
195 pcie_cfgregopen(pciebar, 0, 255);
204 pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
207 if (cfgmech == CFGMECH_PCIE &&
208 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
209 (bus != 0 || !(1 << slot & pcie_badslots)))
210 return (pciereg_cfgread(bus, slot, func, reg, bytes));
212 return (pcireg_cfgread(bus, slot, func, reg, bytes));
216 * Read configuration space register
219 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
224 * Some BIOS writers seem to want to ignore the spec and put
225 * 0 in the intline rather than 255 to indicate none. The rest of
226 * the code uses 255 as an invalid IRQ.
228 if (reg == PCIR_INTLINE && bytes == 1) {
229 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
230 return (pci_i386_map_intline(line));
232 return (pci_docfgregread(bus, slot, func, reg, bytes));
236 * Write configuration space register
239 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
242 if (cfgmech == CFGMECH_PCIE &&
243 (bus >= pcie_minbus && bus <= pcie_maxbus) &&
244 (bus != 0 || !(1 << slot & pcie_badslots)))
245 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
247 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
251 * Configuration space access using direct register operations
254 /* enable configuration space accesses and return data port address */
256 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
261 if (arch_i386_is_xbox) {
263 * The Xbox MCPX chipset is a derivative of the nForce 1
264 * chipset. It almost has the same bus layout; some devices
265 * cannot be used, because they have been removed.
269 * Devices 00:00.1 and 00:00.2 used to be memory controllers on
270 * the nForce chipset, but on the Xbox, using them will lockup
273 if (bus == 0 && slot == 0 && (func == 1 || func == 2))
277 * Bus 1 only contains a VGA controller at 01:00.0. When you try
278 * to probe beyond that device, you only get garbage, which
279 * could cause lockups.
281 if (bus == 1 && (slot != 0 || func != 0))
285 * Bus 2 used to contain the AGP controller, but the Xbox MCPX
286 * doesn't have one. Probing it can cause lockups.
293 if (bus <= PCI_BUSMAX
295 && func <= PCI_FUNCMAX
298 && (unsigned) bytes <= 4
299 && (reg & (bytes - 1)) == 0) {
303 outl(CONF1_ADDR_PORT, (1 << 31)
304 | (bus << 16) | (slot << 11)
305 | (func << 8) | (reg & ~0x03));
306 dataport = CONF1_DATA_PORT + (reg & 0x03);
309 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
310 outb(CONF2_FORWARD_PORT, bus);
311 dataport = 0xc000 | (slot << 8) | reg;
318 /* disable configuration space accesses */
326 * Do nothing for the config mechanism 1 case.
327 * Writing a 0 to the address port can apparently
328 * confuse some bridges and cause spurious
333 outb(CONF2_ENABLE_PORT, 0);
339 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
344 mtx_lock_spin(&pcicfg_mtx);
345 port = pci_cfgenable(bus, slot, func, reg, bytes);
360 mtx_unlock_spin(&pcicfg_mtx);
365 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
369 mtx_lock_spin(&pcicfg_mtx);
370 port = pci_cfgenable(bus, slot, func, reg, bytes);
385 mtx_unlock_spin(&pcicfg_mtx);
388 /* check whether the configuration mechanism has been correctly identified */
390 pci_cfgcheck(int maxdev)
398 kprintf("pci_cfgcheck:\tdevice ");
400 for (device = 0; device < maxdev; device++) {
402 kprintf("%d ", device);
404 port = pci_cfgenable(0, device, 0, 0, 4);
406 if (id == 0 || id == 0xffffffff)
409 port = pci_cfgenable(0, device, 0, 8, 4);
410 class = inl(port) >> 8;
412 kprintf("[class=%06x] ", class);
413 if (class == 0 || (class & 0xf870ff) != 0)
416 port = pci_cfgenable(0, device, 0, 14, 1);
419 kprintf("[hdr=%02x] ", header);
420 if ((header & 0x7e) != 0)
424 kprintf("is there (id=%08x)\n", id);
430 kprintf("-- nothing found\n");
439 uint32_t mode1res, oldval1;
440 uint8_t mode2res, oldval2;
442 /* Check for type #1 first. */
443 oldval1 = inl(CONF1_ADDR_PORT);
446 kprintf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
453 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
455 mode1res = inl(CONF1_ADDR_PORT);
456 outl(CONF1_ADDR_PORT, oldval1);
459 kprintf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
463 if (pci_cfgcheck(32))
467 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
468 mode1res = inl(CONF1_ADDR_PORT);
469 outl(CONF1_ADDR_PORT, oldval1);
472 kprintf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
475 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
476 if (pci_cfgcheck(32))
480 /* Type #1 didn't work, so try type #2. */
481 oldval2 = inb(CONF2_ENABLE_PORT);
484 kprintf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
488 if ((oldval2 & 0xf0) == 0) {
493 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
494 mode2res = inb(CONF2_ENABLE_PORT);
495 outb(CONF2_ENABLE_PORT, oldval2);
498 kprintf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
499 mode2res, CONF2_ENABLE_CHK);
501 if (mode2res == CONF2_ENABLE_RES) {
503 kprintf("pci_open(2a):\tnow trying mechanism 2\n");
505 if (pci_cfgcheck(16))
510 /* Nothing worked, so punt. */
511 cfgmech = CFGMECH_NONE;
517 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
520 struct pcie_cfg_list *pcielist;
521 struct pcie_cfg_elem *pcie_array, *elem;
535 if (base >= 0x100000000) {
538 "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
544 kprintf("PCIe: Memory Mapped configuration base @ 0x%jx\n",
548 SLIST_FOREACH(pc, &cpuhead, pc_allcpu)
552 pcie_array = kmalloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
554 if (pcie_array == NULL)
557 va = kmem_alloc_nofault(&kernel_map, PCIE_CACHE * PAGE_SIZE,
560 kfree(pcie_array, M_DEVBUF);
565 pcielist = &pcie_list[pc->pc_cpuid];
567 pcielist = &pcie_list[0];
569 TAILQ_INIT(pcielist);
570 for (i = 0; i < PCIE_CACHE; i++) {
571 elem = &pcie_array[i];
572 elem->vapage = va + (i * PAGE_SIZE);
574 TAILQ_INSERT_HEAD(pcielist, elem, elem);
579 pcie_minbus = minbus;
580 pcie_maxbus = maxbus;
581 cfgmech = CFGMECH_PCIE;
585 * On some AMD systems, some of the devices on bus 0 are
586 * inaccessible using memory-mapped PCI config access. Walk
587 * bus 0 looking for such devices. For these devices, we will
588 * fall back to using type 1 config access instead.
590 if (pci_cfgregopen() != 0) {
591 for (slot = 0; slot < 32; slot++) {
592 val1 = pcireg_cfgread(0, slot, 0, 0, 4);
593 if (val1 == 0xffffffff)
596 val2 = pciereg_cfgread(0, slot, 0, 0, 4);
598 pcie_badslots |= (1 << slot);
603 #else /* !PCIE_CFG_MECH */
605 #endif /* PCIE_CFG_MECH */
608 #define PCIE_PADDR(bar, reg, bus, slot, func) \
610 (((bus) & 0xff) << 20) | \
611 (((slot) & 0x1f) << 15) | \
612 (((func) & 0x7) << 12) | \
616 * Find an element in the cache that matches the physical page desired, or
617 * create a new mapping from the least recently used element.
618 * A very simple LRU algorithm is used here, does it need to be more
621 static __inline struct pcie_cfg_elem *
622 pciereg_findelem(vm_paddr_t papage)
624 struct pcie_cfg_list *pcielist;
625 struct pcie_cfg_elem *elem;
626 pcielist = &pcie_list[mycpuid];
627 TAILQ_FOREACH(elem, pcielist, elem) {
628 if (elem->papage == papage)
633 elem = TAILQ_LAST(pcielist, pcie_cfg_list);
634 if (elem->papage != 0) {
635 pmap_kremove(elem->vapage);
636 cpu_invlpg(&elem->vapage);
638 pmap_kenter(elem->vapage, papage);
639 elem->papage = papage;
642 if (elem != TAILQ_FIRST(pcielist)) {
643 TAILQ_REMOVE(pcielist, elem, elem);
644 TAILQ_INSERT_HEAD(pcielist, elem, elem);
650 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
653 struct pcie_cfg_elem *elem;
654 volatile vm_offset_t va;
655 vm_paddr_t pa, papage;
658 if (bus < pcie_minbus || bus > pcie_maxbus || slot >= 32 ||
659 func > PCI_FUNCMAX || reg >= 0x1000 || bytes > 4 || bytes == 3)
663 pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
664 papage = pa & ~PAGE_MASK;
665 elem = pciereg_findelem(papage);
666 va = elem->vapage | (pa & PAGE_MASK);
670 data = *(volatile uint32_t *)(va);
673 data = *(volatile uint16_t *)(va);
676 data = *(volatile uint8_t *)(va);
685 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data, unsigned bytes)
687 struct pcie_cfg_elem *elem;
688 volatile vm_offset_t va;
689 vm_paddr_t pa, papage;
692 pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
693 papage = pa & ~PAGE_MASK;
694 elem = pciereg_findelem(papage);
695 va = elem->vapage | (pa & PAGE_MASK);
699 *(volatile uint32_t *)(va) = data;
702 *(volatile uint16_t *)(va) = data;
705 *(volatile uint8_t *)(va) = data;