2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.10 2005/11/02 08:33:24 dillon Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <machine/smptests.h> /** TEST_TEST1, GRAB_LOPRIO */
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <arch/apic/mpapic.h>
35 #include <machine/segments.h>
36 #include <sys/thread2.h>
38 #include <i386/isa/intr_machdep.h> /* Xspuriousint() */
40 /* EISA Edge/Level trigger control registers */
41 #define ELCR0 0x4d0 /* eisa irq 0-7 */
42 #define ELCR1 0x4d1 /* eisa irq 8-15 */
45 * pointers to pmapped apic hardware.
49 volatile ioapic_t **ioapic;
53 * Enable APIC, configure interrupts.
60 /* setup LVT1 as ExtINT */
61 temp = lapic.lvt_lint0;
62 temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM);
63 if (mycpu->gd_cpuid == 0)
64 temp |= 0x00000700; /* process ExtInts */
66 temp |= 0x00010700; /* mask ExtInts */
67 lapic.lvt_lint0 = temp;
69 /* setup LVT2 as NMI, masked till later... */
70 temp = lapic.lvt_lint1;
71 temp &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM);
72 temp |= 0x00010400; /* masked, edge trigger, active hi */
73 lapic.lvt_lint1 = temp;
76 * Set the Task Priority Register as needed. At the moment allow
77 * interrupts on all cpus (the APs will remain CLId until they are
78 * ready to deal). We could disable all but IPIs by setting
79 * temp |= TPR_IPI_ONLY for cpu != 0.
82 temp &= ~APIC_TPR_PRIO; /* clear priority field */
86 /* enable the local APIC */
88 temp |= APIC_SVR_SWEN; /* software enable APIC */
89 temp &= ~APIC_SVR_FOCUS; /* enable 'focus processor' */
91 /* set the 'spurious INT' vector */
92 if ((XSPURIOUSINT_OFFSET & APIC_SVR_VEC_FIX) != APIC_SVR_VEC_FIX)
93 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
94 temp &= ~APIC_SVR_VEC_PROG; /* clear (programmable) vector field */
95 temp |= (XSPURIOUSINT_OFFSET & APIC_SVR_VEC_PROG);
97 #if defined(TEST_TEST1)
98 if (cpuid == GUARD_CPU) {
99 temp &= ~APIC_SVR_SWEN; /* software DISABLE APIC */
101 #endif /** TEST_TEST1 */
106 apic_dump("apic_initialize()");
111 * dump contents of local APIC registers
116 printf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
117 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
118 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
128 #define IOAPIC_ISA_INTS 16
129 #define REDIRCNT_IOAPIC(A) \
130 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
132 static int trigger (int apic, int pin, u_int32_t * flags);
133 static void polarity (int apic, int pin, u_int32_t * flags, int level);
135 #define DEFAULT_FLAGS \
141 #define DEFAULT_ISA_FLAGS \
150 io_apic_set_id(int apic, int id)
154 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
155 if (((ux & APIC_ID_MASK) >> 24) != id) {
156 printf("Changing APIC ID for IO APIC #%d"
157 " from %d to %d on chip\n",
158 apic, ((ux & APIC_ID_MASK) >> 24), id);
159 ux &= ~APIC_ID_MASK; /* clear the ID field */
161 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
162 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
163 if (((ux & APIC_ID_MASK) >> 24) != id)
164 panic("can't control IO APIC #%d ID, reg: 0x%08x",
171 io_apic_get_id(int apic)
173 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
182 extern int apic_pin_trigger; /* 'opaque' */
185 io_apic_setup_intpin(int apic, int pin)
187 int bus, bustype, irq;
188 u_char select; /* the select register is 8 bits */
189 u_int32_t flags; /* the window register is 32 bits */
190 u_int32_t target; /* the window register is 32 bits */
191 u_int32_t vector; /* the window register is 32 bits */
196 select = pin * 2 + IOAPIC_REDTBL0; /* register */
198 * Always disable interrupts, and by default map
199 * pin X to IRQX because the disable doesn't stick
200 * and the uninitialize vector will get translated
203 * This is correct for IRQs 1 and 3-15. In the other cases,
204 * any robust driver will handle the spurious interrupt, and
205 * the effective NOP beats a panic.
207 * A dedicated "bogus interrupt" entry in the IDT would
208 * be a nicer hack, although some one should find out
209 * why some systems are generating interrupts when they
210 * shouldn't and stop the carnage.
212 vector = NRSVIDT + pin; /* IDT vec */
214 io_apic_write(apic, select,
215 (io_apic_read(apic, select) & ~IOART_INTMASK
216 & ~0xff)|IOART_INTMSET|vector);
219 /* we only deal with vectored INTs here */
220 if (apic_int_type(apic, pin) != 0)
223 irq = apic_irq(apic, pin);
227 /* determine the bus type for this pin */
228 bus = apic_src_bus_id(apic, pin);
231 bustype = apic_bus_type(bus);
233 if ((bustype == ISA) &&
234 (pin < IOAPIC_ISA_INTS) &&
236 (apic_polarity(apic, pin) == 0x1) &&
237 (apic_trigger(apic, pin) == 0x3)) {
239 * A broken BIOS might describe some ISA
240 * interrupts as active-high level-triggered.
241 * Use default ISA flags for those interrupts.
243 flags = DEFAULT_ISA_FLAGS;
246 * Program polarity and trigger mode according to
249 flags = DEFAULT_FLAGS;
250 level = trigger(apic, pin, &flags);
252 apic_pin_trigger |= (1 << irq);
253 polarity(apic, pin, &flags, level);
256 /* program the appropriate registers */
258 printf("IOAPIC #%d intpin %d -> irq %d\n",
261 vector = NRSVIDT + irq; /* IDT vec */
263 io_apic_write(apic, select, flags | vector);
264 io_apic_write(apic, select + 1, target);
269 io_apic_setup(int apic)
275 apic_pin_trigger = 0; /* default to edge-triggered */
277 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
278 printf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
280 for (pin = 0; pin < maxpin; ++pin) {
281 io_apic_setup_intpin(apic, pin);
284 /* return GOOD status */
287 #undef DEFAULT_ISA_FLAGS
291 #define DEFAULT_EXTINT_FLAGS \
300 * Setup the source of External INTerrupts.
303 ext_int_setup(int apic, int intr)
305 u_char select; /* the select register is 8 bits */
306 u_int32_t flags; /* the window register is 32 bits */
307 u_int32_t target; /* the window register is 32 bits */
308 u_int32_t vector; /* the window register is 32 bits */
310 if (apic_int_type(apic, intr) != 3)
314 select = IOAPIC_REDTBL0 + (2 * intr);
315 vector = NRSVIDT + intr;
316 flags = DEFAULT_EXTINT_FLAGS;
318 io_apic_write(apic, select, flags | vector);
319 io_apic_write(apic, select + 1, target);
323 #undef DEFAULT_EXTINT_FLAGS
327 * Set the trigger level for an IO APIC pin.
330 trigger(int apic, int pin, u_int32_t * flags)
335 static int intcontrol = -1;
337 switch (apic_trigger(apic, pin)) {
343 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
347 *flags |= IOART_TRGRLVL;
355 if ((id = apic_src_bus_id(apic, pin)) == -1)
358 switch (apic_bus_type(id)) {
360 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
364 eirq = apic_src_bus_irq(apic, pin);
366 if (eirq < 0 || eirq > 15) {
367 printf("EISA IRQ %d?!?!\n", eirq);
371 if (intcontrol == -1) {
372 intcontrol = inb(ELCR1) << 8;
373 intcontrol |= inb(ELCR0);
374 printf("EISA INTCONTROL = %08x\n", intcontrol);
377 /* Use ELCR settings to determine level or edge mode */
378 level = (intcontrol >> eirq) & 1;
381 * Note that on older Neptune chipset based systems, any
382 * pci interrupts often show up here and in the ELCR as well
383 * as level sensitive interrupts attributed to the EISA bus.
387 *flags |= IOART_TRGRLVL;
389 *flags &= ~IOART_TRGRLVL;
394 *flags |= IOART_TRGRLVL;
403 panic("bad APIC IO INT flags");
408 * Set the polarity value for an IO APIC pin.
411 polarity(int apic, int pin, u_int32_t * flags, int level)
415 switch (apic_polarity(apic, pin)) {
421 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
425 *flags |= IOART_INTALO;
433 if ((id = apic_src_bus_id(apic, pin)) == -1)
436 switch (apic_bus_type(id)) {
438 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
442 /* polarity converter always gives active high */
443 *flags &= ~IOART_INTALO;
447 *flags |= IOART_INTALO;
456 panic("bad APIC IO INT flags");
461 * Print contents of apic_imen.
463 extern u_int apic_imen; /* keep apic_imen 'opaque' */
469 printf("SMP: enabled INTs: ");
470 for (x = 0; x < 24; ++x)
471 if ((apic_imen & (1 << x)) == 0)
473 printf("apic_imen: 0x%08x\n", apic_imen);
478 * Inter Processor Interrupt functions.
483 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
485 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
486 * vector is any valid SYSTEM INT vector
487 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
489 * A backlog of requests can create a deadlock between cpus. To avoid this
490 * we have to be able to accept IPIs at the same time we are trying to send
491 * them. The critical section prevents us from attempting to send additional
492 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
493 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
494 * to occur but fortunately it does not happen too often.
497 apic_ipi(int dest_type, int vector, int delivery_mode)
502 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
503 unsigned int eflags = read_eflags();
505 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
508 write_eflags(eflags);
511 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK) | dest_type |
512 delivery_mode | vector;
513 lapic.icr_lo = icr_lo;
519 single_apic_ipi(int cpu, int vector, int delivery_mode)
525 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
526 unsigned int eflags = read_eflags();
528 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
531 write_eflags(eflags);
533 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
534 icr_hi |= (CPU_TO_ID(cpu) << 24);
535 lapic.icr_hi = icr_hi;
538 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
539 | APIC_DEST_DESTFLD | delivery_mode | vector;
542 lapic.icr_lo = icr_lo;
549 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
551 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
552 * to the target, and the scheduler does not 'poll' for IPI messages.
555 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
561 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
565 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
566 icr_hi |= (CPU_TO_ID(cpu) << 24);
567 lapic.icr_hi = icr_hi;
570 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
571 | APIC_DEST_DESTFLD | delivery_mode | vector;
574 lapic.icr_lo = icr_lo;
582 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
584 * target is a bitmask of destination cpus. Vector is any
585 * valid system INT vector. Delivery mode may be either
586 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
589 selected_apic_ipi(u_int target, int vector, int delivery_mode)
593 int n = bsfl(target);
595 single_apic_ipi(n, vector, delivery_mode);
603 * Timer code, in development...
604 * - suggested by rgrimes@gndrsh.aac.dev.com
607 /** XXX FIXME: temp hack till we can determin bus clock */
609 #define BUS_CLOCK 66000000
610 #define bus_clock() 66000000
614 int acquire_apic_timer (void);
615 int release_apic_timer (void);
618 * Acquire the APIC timer for exclusive use.
621 acquire_apic_timer(void)
626 /** XXX FIXME: make this really do something */
627 panic("APIC timer in use when attempting to aquire");
633 * Return the APIC timer.
636 release_apic_timer(void)
641 /** XXX FIXME: make this really do something */
642 panic("APIC timer was already released");
649 * Load a 'downcount time' in uSeconds.
652 set_apic_timer(int value)
655 long ticks_per_microsec;
658 * Calculate divisor and count from value:
660 * timeBase == CPU bus clock divisor == [1,2,4,8,16,32,64,128]
661 * value == time in uS
663 lapic.dcr_timer = APIC_TDCR_1;
664 ticks_per_microsec = bus_clock() / 1000000;
666 /* configure timer as one-shot */
667 lvtt = lapic.lvt_timer;
668 lvtt &= ~(APIC_LVTT_VECTOR | APIC_LVTT_DS | APIC_LVTT_M | APIC_LVTT_TM);
669 lvtt |= APIC_LVTT_M; /* no INT, one-shot */
670 lapic.lvt_timer = lvtt;
673 lapic.icr_timer = value * ticks_per_microsec;
678 * Read remaining time in timer.
681 read_apic_timer(void)
684 /** XXX FIXME: we need to return the actual remaining time,
685 * for now we just return the remaining count.
688 return lapic.ccr_timer;
694 * Spin-style delay, set delay time in uS, spin till it drains.
699 set_apic_timer(count);
700 while (read_apic_timer())