2 * Copyright (c) 1996, Sujal M. Patel
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Sujal M. Patel
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17 * may be used to endorse or promote products derived from this software
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32 * $FreeBSD: src/sys/boot/common/isapnp.h,v 1.7 2002/03/20 07:59:37 alfred Exp $
33 * $DragonFly: src/sys/boot/common/isapnp.h,v 1.4 2003/11/10 06:08:31 dillon Exp $
36 #ifndef _I386_ISA_PNP_H_
37 #define _I386_ISA_PNP_H_
39 /* Maximum Number of PnP Devices. 8 should be plenty */
40 #define MAX_PNP_CARDS 8
42 * the following is the maximum number of PnP Logical devices that
43 * userconfig can handle.
45 #define MAX_PNP_LDN 20
47 /* Static ports to access PnP state machine */
50 /* pnp.h is included from pnpinfo.c. */
51 #define _PNP_ADDRESS 0x259
52 #define _PNP_WRITE_DATA 0xa59
54 #define _PNP_ADDRESS 0x279
55 #define _PNP_WRITE_DATA 0xa79
59 /* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */
60 #define SET_RD_DATA 0x00
62 Writing to this location modifies the address of the port used for
63 reading from the Plug and Play ISA cards. Bits[7:0] become I/O
64 read port address bits[9:2]. Reads from this register are ignored.
67 #define SERIAL_ISOLATION 0x01
69 A read to this register causes a Plug and Play cards in the Isolation
70 state to compare one bit of the boards ID.
71 This register is read only.
74 #define CONFIG_CONTROL 0x02
77 Bit[1] Return to the Wait for Key state
78 Bit[0] Reset all logical devices and restore configuration
79 registers to their power-up values.
81 A write to bit[0] of this register performs a reset function on
82 all logical devices. This resets the contents of configuration
83 registers to their default state. All card's logical devices
84 enter their default state and the CSN is preserved.
86 A write to bit[1] of this register causes all cards to enter the
87 Wait for Key state but all CSNs are preserved and logical devices
90 A write to bit[2] of this register causes all cards to reset their
93 This register is write-only. The values are not sticky, that is,
94 hardware will automatically clear them and there is no need for
95 software to clear the bits.
100 A write to this port will cause all cards that have a CSN that
101 matches the write data[7:0] to go from the Sleep state to the either
102 the Isolation state if the write data for this command is zero or
103 the Config state if the write data is not zero. Additionally, the
104 pointer to the byte-serial device is reset. This register is
108 #define RESOURCE_DATA 0x04
110 A read from this address reads the next byte of resource information.
111 The Status register must be polled until bit[0] is set before this
112 register may be read. This register is read only.
117 Bit[0] when set indicates it is okay to read the next data byte
118 from the Resource Data register. This register is readonly.
123 A write to this port sets a card's CSN. The CSN is a value uniquely
124 assigned to each ISA card after the serial identification process
125 so that each card may be individually selected during a Wake[CSN]
126 command. This register is read/write.
131 Selects the current logical device. All reads and writes of memory,
132 I/O, interrupt and DMA configuration information access the registers
133 of the logical device written here. In addition, the I/O Range
134 Check and Activate commands operate only on the selected logical
135 device. This register is read/write. If a card has only 1 logical
136 device, this location should be a read-only value of 0x00.
139 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
140 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
142 #define ACTIVATE 0x30
144 For each logical device there is one activate register that controls
145 whether or not the logical device is active on the ISA bus. Bit[0],
146 if set, activates the logical device. Bits[7:1] are reserved and
147 must return 0 on reads. This is a read/write register. Before a
148 logical device is activated, I/O range check must be disabled.
151 #define IO_RANGE_CHECK 0x31
153 This register is used to perform a conflict check on the I/O port
154 range programmed for use by a logical device.
156 Bit[7:2] Reserved and must return 0 on reads
157 Bit[1] Enable I/O Range check, if set then I/O Range Check
158 is enabled. I/O range check is only valid when the logical
161 Bit[0], if set, forces the logical device to respond to I/O reads
162 of the logical device's assigned I/O range with a 0x55 when I/O
163 range check is in operation. If clear, the logical device drives
164 0xAA. This register is read/write.
167 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
168 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
170 #define MEM_CONFIG 0x40
172 Four memory resource registers per range, four ranges.
173 Fill with 0 if no ranges are enabled.
175 Offset 0: RW Memory base address bits[23:16]
176 Offset 1: RW Memory base address bits[15:8]
177 Offset 2: Memory control
178 Bit[1] specifies 8/16-bit control. This bit is set to indicate
179 16-bit memory, and cleared to indicate 8-bit memory.
180 Bit[0], if cleared, indicates the next field can be used as a range
181 length for decode (implies range length and base alignment of memory
182 descriptor are equal).
183 Bit[0], if set, indicates the next field is the upper limit for
184 the address. - - Bit[0] is read-only.
185 Offset 3: RW upper limit or range len, bits[23:16]
186 Offset 4: RW upper limit or range len, bits[15:8]
187 Offset 5-Offset 7: filler, unused.
190 #define IO_CONFIG_BASE 0x60
192 Eight ranges, two bytes per range.
193 Offset 0: I/O port base address bits[15:8]
194 Offset 1: I/O port base address bits[7:0]
197 #define IRQ_CONFIG 0x70
199 Two entries, two bytes per entry.
200 Offset 0: RW interrupt level (1..15, 0=unused).
201 Offset 1: Bit[1]: level(1:hi, 0:low),
202 Bit[0]: type (1:level, 0:edge)
203 byte 1 can be readonly if 1 type of int is used.
206 #define DRQ_CONFIG 0x74
208 Two entries, one byte per entry. Bits[2:0] select
209 which DMA channel is in use for DMA 0. Zero selects DMA channel
210 0, seven selects DMA channel 7. DMA channel 4, the cascade channel
211 is used to indicate no DMA channel is active.
214 /*** 32-bit memory accesses are at 0x76 ***/
216 /* Macros to parse Resource IDs */
217 #define PNP_RES_TYPE(a) (a >> 7)
218 #define PNP_SRES_NUM(a) (a >> 3)
219 #define PNP_SRES_LEN(a) (a & 0x07)
220 #define PNP_LRES_NUM(a) (a & 0x7f)
222 /* Small Resource Item names */
223 #define PNP_VERSION 0x1
224 #define LOG_DEVICE_ID 0x2
225 #define COMP_DEVICE_ID 0x3
226 #define IRQ_FORMAT 0x4
227 #define DMA_FORMAT 0x5
228 #define START_DEPEND_FUNC 0x6
229 #define END_DEPEND_FUNC 0x7
230 #define IO_PORT_DESC 0x8
231 #define FIXED_IO_PORT_DESC 0x9
232 #define SM_RES_RESERVED 0xa-0xd
233 #define SM_VENDOR_DEFINED 0xe
236 /* Large Resource Item names */
237 #define MEMORY_RANGE_DESC 0x1
238 #define ID_STRING_ANSI 0x2
239 #define ID_STRING_UNICODE 0x3
240 #define LG_VENDOR_DEFINED 0x4
241 #define _32BIT_MEM_RANGE_DESC 0x5
242 #define _32BIT_FIXED_LOC_DESC 0x6
243 #define LG_RES_RESERVED 0x7-0x7f
246 * pnp_cinfo contains Configuration Information. They are used
247 * to communicate to the device driver the actual configuration
248 * of the device, and also by the userconfig menu to let the
249 * operating system override any configuration set by the bios.
253 u_int vendor_id; /* board id */
254 u_int serial; /* Board's Serial Number */
255 u_long flags; /* OS-reserved flags */
256 u_char csn; /* assigned Card Select Number */
257 u_char ldn; /* Logical Device Number */
258 u_char enable; /* pnp enable */
259 u_char override; /* override bios parms (in userconfig) */
260 u_char irq[2]; /* IRQ Number */
261 u_char irq_type[2]; /* IRQ Type */
263 u_short port[8]; /* The Base Address of the Port */
265 u_long base; /* Memory Base Address */
266 int control; /* Memory Control Register */
267 u_long range; /* Memory Range *OR* Upper Limit */
275 char * (*pd_probe ) (u_long csn, u_long vendor_id);
276 void (*pd_attach ) (u_long csn, u_long vend_id, char * name,
277 struct isa_device *dev);
288 struct pnp_dlist_node {
289 struct pnp_device *pnp;
290 struct isa_device dev;
291 struct pnp_dlist_node *next;
294 typedef struct _pnp_id pnp_id;
295 extern struct pnp_dlist_node *pnp_device_list;
296 extern pnp_id pnp_devices[MAX_PNP_CARDS];
297 extern struct pnp_cinfo pnp_ldn_overrides[MAX_PNP_LDN];
298 extern int pnp_overrides_valid;
301 * these two functions are for use in drivers
303 int read_pnp_parms(struct pnp_cinfo *d, int ldn);
304 int write_pnp_parms(struct pnp_cinfo *d, int ldn);
305 int enable_pnp_card(void);
308 * used by autoconfigure to actually probe and attach drivers
310 void pnp_configure(void);
314 #endif /* !_I386_ISA_PNP_H_ */