2 * Copyright 1996 Massachusetts Institute of Technology
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29 * $FreeBSD: src/sys/i386/i386/perfmon.c,v 1.21 1999/09/25 18:24:04 phk Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/device.h>
37 #include <sys/fcntl.h>
41 #include <machine/cputypes.h>
43 #include <machine/clock.h>
44 #include <machine/perfmon.h>
46 static int perfmon_inuse;
47 static int perfmon_cpuok;
49 static int msr_ctl[NPMC];
51 static int msr_pmc[NPMC];
52 static unsigned int ctl_shadow[NPMC];
53 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
54 static int (*writectl)(int);
56 static int writectl5(int);
57 static int writectl6(int);
60 static d_close_t perfmon_close;
61 static d_open_t perfmon_open;
62 static d_ioctl_t perfmon_ioctl;
64 static struct dev_ops perfmon_ops = {
66 .d_open = perfmon_open,
67 .d_close = perfmon_close,
68 .d_ioctl = perfmon_ioctl,
72 * Initialize the device ops for user access to the perfmon. This must
73 * be done late in the boot sequence.
75 * NOTE: The perfmon is really a minor of the mem major. Perfmon
79 perfmon_driver_init(void *unused __unused)
81 make_dev(&perfmon_ops, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
84 SYSINIT(perfmondrv, SI_SUB_DRIVERS, SI_ORDER_ANY, perfmon_driver_init, NULL)
87 * This is called in early boot, after cpu_class has been set up.
100 writectl = writectl5;
108 writectl = writectl6;
121 return perfmon_cpuok;
125 perfmon_setup(int pmc, unsigned int control)
127 if (pmc < 0 || pmc >= NPMC)
130 perfmon_inuse |= (1 << pmc);
131 control &= ~(PMCF_SYS_FLAGS << 16);
132 mpintr_lock(); /* doesn't have to be mpintr_lock YYY */
133 ctl_shadow[pmc] = control;
135 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
141 perfmon_get(int pmc, unsigned int *control)
143 if (pmc < 0 || pmc >= NPMC)
146 if (perfmon_inuse & (1 << pmc)) {
147 *control = ctl_shadow[pmc];
150 return EBUSY; /* XXX reversed sense */
154 perfmon_fini(int pmc)
156 if (pmc < 0 || pmc >= NPMC)
159 if (perfmon_inuse & (1 << pmc)) {
162 perfmon_inuse &= ~(1 << pmc);
165 return EBUSY; /* XXX reversed sense */
169 perfmon_start(int pmc)
171 if (pmc < 0 || pmc >= NPMC)
174 if (perfmon_inuse & (1 << pmc)) {
175 mpintr_lock(); /* doesn't have to be mpintr YYY */
176 ctl_shadow[pmc] |= (PMCF_EN << 16);
177 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
186 perfmon_stop(int pmc)
188 if (pmc < 0 || pmc >= NPMC)
191 if (perfmon_inuse & (1 << pmc)) {
193 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
194 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
203 perfmon_read(int pmc, quad_t *val)
205 if (pmc < 0 || pmc >= NPMC)
208 if (perfmon_inuse & (1 << pmc)) {
209 if (ctl_shadow[pmc] & (PMCF_EN << 16))
210 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
212 *val = pmc_shadow[pmc];
220 perfmon_reset(int pmc)
222 if (pmc < 0 || pmc >= NPMC)
225 if (perfmon_inuse & (1 << pmc)) {
226 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
234 * Unfortunately, the performance-monitoring registers are laid out
235 * differently in the P5 and P6. We keep everything in P6 format
236 * internally (except for the event code), and convert to P5
237 * format as needed on those CPUs. The writectl function pointer
238 * is set up to point to one of these functions by perfmon_init().
243 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
244 wrmsr(msr_ctl[pmc], 0);
246 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
251 #define P5FLAG_P 0x200
252 #define P5FLAG_E 0x100
253 #define P5FLAG_USR 0x80
254 #define P5FLAG_OS 0x40
261 if (ctl_shadow[1] & (PMCF_EN << 16)) {
262 if (ctl_shadow[1] & (PMCF_USR << 16))
263 newval |= P5FLAG_USR << 16;
264 if (ctl_shadow[1] & (PMCF_OS << 16))
265 newval |= P5FLAG_OS << 16;
266 if (!(ctl_shadow[1] & (PMCF_E << 16)))
267 newval |= P5FLAG_E << 16;
268 newval |= (ctl_shadow[1] & 0x3f) << 16;
270 if (ctl_shadow[0] & (PMCF_EN << 16)) {
271 if (ctl_shadow[0] & (PMCF_USR << 16))
272 newval |= P5FLAG_USR;
273 if (ctl_shadow[0] & (PMCF_OS << 16))
275 if (!(ctl_shadow[0] & (PMCF_E << 16)))
277 newval |= ctl_shadow[0] & 0x3f;
280 wrmsr(msr_ctl[0], newval);
281 return 0; /* XXX should check for unimplemented bits */
286 * Now the user-mode interface, called from a subdevice of mem.c.
289 static int writerpmc;
292 perfmon_open(struct dev_open_args *ap)
297 if (ap->a_oflags & FWRITE) {
309 perfmon_close(struct dev_close_args *ap)
311 if (ap->a_fflag & FWRITE) {
314 for (i = 0; i < NPMC; i++) {
315 if (writerpmc & (1 << i))
324 perfmon_ioctl(struct dev_ioctl_args *ap)
326 caddr_t param = ap->a_data;
328 struct pmc_data *pmcd;
329 struct pmc_tstamp *pmct;
335 if (!(ap->a_fflag & FWRITE))
337 pmc = (struct pmc *)param;
339 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
341 writerpmc |= (1 << pmc->pmc_num);
346 pmc = (struct pmc *)param;
347 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
351 if (!(ap->a_fflag & FWRITE))
355 rv = perfmon_start(*ip);
359 if (!(ap->a_fflag & FWRITE))
363 rv = perfmon_stop(*ip);
367 if (!(ap->a_fflag & FWRITE))
371 rv = perfmon_reset(*ip);
375 pmcd = (struct pmc_data *)param;
376 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
380 if (tsc_frequency == 0) {
384 pmct = (struct pmc_tstamp *)param;
385 /* XXX interface loses precision. */
386 pmct->pmct_rate = (int)(tsc_frequency / 1000000);
387 pmct->pmct_value = rdtsc();