2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
41 * Tigon general information block. This resides in host memory
42 * and contains the status counters, ring control blocks and
47 struct bge_stats bnx_stats;
48 struct bge_rcb bnx_tx_rcb[16];
49 struct bge_rcb bnx_std_rx_rcb;
50 struct bge_rcb bnx_jumbo_rx_rcb;
51 struct bge_rcb bnx_mini_rx_rcb;
52 struct bge_rcb bnx_return_rcb;
55 #define BNX_MIN_FRAMELEN 60
56 #define BNX_MAX_FRAMELEN 1536
57 #define BNX_JUMBO_FRAMELEN 9018
58 #define BNX_JUMBO_MTU (BNX_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
60 #define BNX_TIMEOUT 5000
61 #define BNX_FIRMWARE_TIMEOUT 100000
62 #define BNX_TXCONS_UNSET 0xFFFF /* impossible value */
65 * Other utility macros.
67 #define BNX_INC(x, y) (x) = ((x) + 1) % (y)
70 * Register access macros. The Tigon always uses memory mapped register
71 * accesses and all registers must be accessed with 32 bit operations.
74 #define CSR_WRITE_4(sc, reg, val) \
75 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val)
77 #define CSR_READ_4(sc, reg) \
78 bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
80 #define BNX_SETBIT(sc, reg, x) \
81 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
83 #define BNX_CLRBIT(sc, reg, x) \
84 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
86 #define BNX_MEMWIN_READ(sc, x, val) \
88 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \
89 (0xFFFF0000 & x), 4); \
90 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
93 #define BNX_MEMWIN_WRITE(sc, x, val) \
95 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \
96 (0xFFFF0000 & x), 4); \
97 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
100 #define RCB_WRITE_4(sc, rcb, offset, val) \
101 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, \
102 rcb + offsetof(struct bge_rcb, offset), val)
105 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
106 * values are tuneable. They control the actual amount of buffers
107 * allocated for the standard, mini and jumbo receive rings.
110 #define BNX_SSLOTS 256
111 #define BNX_MSLOTS 256
112 #define BNX_JSLOTS 384
114 #define BNX_JRAWLEN (BNX_JUMBO_FRAMELEN + ETHER_ALIGN)
115 #define BNX_JLEN (BNX_JRAWLEN + \
116 (sizeof(uint64_t) - BNX_JRAWLEN % sizeof(uint64_t)))
117 #define BNX_JPAGESZ PAGE_SIZE
118 #define BNX_RESID (BNX_JPAGESZ - (BNX_JLEN * BNX_JSLOTS) % BNX_JPAGESZ)
119 #define BNX_JMEM ((BNX_JLEN * BNX_JSLOTS) + BNX_RESID)
124 struct bnx_softc *bnx_sc;
126 bus_addr_t bnx_paddr;
129 SLIST_ENTRY(bnx_jslot) jslot_link;
133 * Ring structures. Most of these reside in host memory and we tell
134 * the NIC where they are via the ring control blocks. The exceptions
135 * are the tx and command rings, which live in NIC memory and which
136 * we access via the shared memory window.
138 struct bnx_ring_data {
139 struct bge_rx_bd *bnx_rx_jumbo_ring;
140 bus_addr_t bnx_rx_jumbo_ring_paddr;
142 struct bnx_gib bnx_info;
146 bus_dmamap_t bnx_rx_dmamap;
147 struct mbuf *bnx_rx_mbuf;
148 bus_addr_t bnx_rx_paddr;
152 struct bnx_rx_std_ring {
153 struct lwkt_serialize bnx_rx_std_serialize;
154 struct bnx_softc *bnx_sc;
156 volatile uint16_t bnx_rx_std_stop;
157 uint16_t bnx_rx_std; /* current prod ring head */
158 struct bge_rx_bd *bnx_rx_std_ring;
160 int bnx_rx_std_refill __cachealign;
161 u_int bnx_rx_std_running;
162 struct thread bnx_rx_std_ithread;
164 struct bnx_rx_buf bnx_rx_std_buf[BGE_STD_RX_RING_CNT];
166 bus_dma_tag_t bnx_rx_mtag; /* RX mbuf DMA tag */
168 bus_dma_tag_t bnx_rx_std_ring_tag;
169 bus_dmamap_t bnx_rx_std_ring_map;
170 bus_addr_t bnx_rx_std_ring_paddr;
173 struct bnx_rx_ret_ring {
174 struct lwkt_serialize bnx_rx_ret_serialize;
176 uint32_t bnx_saved_status_tag;
177 volatile uint32_t *bnx_hw_status_tag;
178 struct bnx_softc *bnx_sc;
179 struct bnx_rx_std_ring *bnx_std;
181 /* Shadow of bnx_rx_std_ring's bnx_rx_mtag */
182 bus_dma_tag_t bnx_rx_mtag;
184 volatile uint16_t *bnx_rx_considx;
185 uint16_t bnx_rx_saved_considx;
187 uint16_t bnx_rx_cntmax;
188 uint16_t bnx_rx_mask;
189 struct bge_rx_bd *bnx_rx_ret_ring;
190 bus_dmamap_t bnx_rx_tmpmap;
192 bus_dma_tag_t bnx_rx_ret_ring_tag;
193 bus_dmamap_t bnx_rx_ret_ring_map;
194 bus_addr_t bnx_rx_ret_ring_paddr;
198 * Mbuf pointers. We need these to keep track of the virtual addresses
199 * of our mbuf chains since we can only convert from physical to virtual,
200 * not the other way around.
202 struct bnx_chain_data {
203 bus_dma_tag_t bnx_parent_tag;
204 bus_dma_tag_t bnx_rx_jumbo_ring_tag;
205 bus_dma_tag_t bnx_jumbo_tag;
206 bus_dmamap_t bnx_rx_jumbo_ring_map;
207 bus_dmamap_t bnx_jumbo_map;
208 struct bnx_rx_buf bnx_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
209 /* Stick the jumbo mem management stuff here too. */
210 struct bnx_jslot bnx_jslots[BNX_JSLOTS];
214 bus_dmamap_t bnx_tx_dmamap;
215 struct mbuf *bnx_tx_mbuf;
219 struct lwkt_serialize bnx_tx_serialize;
220 uint32_t bnx_saved_status_tag;
221 struct bnx_softc *bnx_sc;
222 struct ifaltq_subque *bnx_ifsq;
223 volatile uint16_t *bnx_tx_considx;
224 uint16_t bnx_tx_flags;
225 #define BNX_TX_FLAG_SHORTDMA 0x0001
226 #define BNX_TX_FLAG_FORCE_DEFRAG 0x0002
227 uint16_t bnx_tx_saved_considx;
229 uint32_t bnx_tx_prodidx;
232 struct ifsubq_watchdog bnx_tx_watchdog;
234 struct bge_tx_bd *bnx_tx_ring;
236 bus_dma_tag_t bnx_tx_mtag; /* TX mbuf DMA tag */
237 struct bnx_tx_buf bnx_tx_buf[BGE_TX_RING_CNT];
239 bus_dma_tag_t bnx_tx_ring_tag;
240 bus_dmamap_t bnx_tx_ring_map;
241 bus_addr_t bnx_tx_ring_paddr;
245 struct bnx_intr_data {
246 struct bnx_softc *bnx_sc;
247 struct bnx_rx_ret_ring *bnx_ret;
248 struct bnx_tx_ring *bnx_txr;
251 struct lwkt_serialize *bnx_intr_serialize;
252 struct callout bnx_intr_timer;
253 void (*bnx_intr_check)(void *);
254 uint16_t bnx_rx_check_considx;
255 uint16_t bnx_tx_check_considx;
256 boolean_t bnx_intr_maylose;
259 driver_intr_t *bnx_intr_func;
261 struct resource *bnx_intr_res;
263 const uint32_t *bnx_saved_status_tag;
265 const char *bnx_intr_desc;
266 char bnx_intr_desc0[64];
268 bus_dma_tag_t bnx_status_tag;
269 bus_dmamap_t bnx_status_map;
270 struct bge_status_block *bnx_status_block;
271 bus_addr_t bnx_status_block_paddr;
274 #define BNX_INTR_MAX 5
277 struct arpcom arpcom; /* interface info */
280 bus_space_handle_t bnx_bhandle;
281 bus_space_tag_t bnx_btag;
282 struct resource *bnx_res;
283 struct ifmedia bnx_ifmedia; /* TBI media info */
285 uint32_t bnx_flags; /* BNX_FLAG_ */
286 #define BNX_FLAG_TBI 0x00000001
287 #define BNX_FLAG_JUMBO 0x00000002
288 #define BNX_FLAG_5717_PLUS 0x00000008
289 #define BNX_FLAG_MII_SERDES 0x00000010
290 #define BNX_FLAG_CPMU 0x00000020
291 #define BNX_FLAG_57765_PLUS 0x00000040
292 #define BNX_FLAG_57765_FAMILY 0x00000080
293 #define BNX_FLAG_STATUSTAG_BUG 0x00000100
294 #define BNX_FLAG_TSO 0x00000200
295 #define BNX_FLAG_NO_EEPROM 0x10000000
296 #define BNX_FLAG_RXTX_BUNDLE 0x20000000
297 #define BNX_FLAG_STD_THREAD 0x40000000
300 uint32_t bnx_asicrev;
301 uint32_t bnx_chiprev;
302 struct bnx_ring_data bnx_ldata; /* rings */
303 struct bnx_chain_data bnx_cdata; /* mbufs */
305 struct lwkt_serialize bnx_main_serialize;
306 int bnx_serialize_cnt;
307 struct lwkt_serialize **bnx_serialize;
310 struct bnx_tx_ring *bnx_tx_ring;
312 struct bnx_rx_ret_ring *bnx_rx_ret_ring;
313 struct bnx_rx_std_ring bnx_rx_std_ring;
315 uint16_t bnx_jumbo; /* current jumo ring head */
316 SLIST_HEAD(__bnx_jfreehead, bnx_jslot) bnx_jfree_listhead;
317 struct lwkt_serialize bnx_jslot_serializer;
318 uint32_t bnx_rx_coal_ticks;
319 uint32_t bnx_tx_coal_ticks;
320 uint32_t bnx_rx_coal_bds;
321 uint32_t bnx_tx_coal_bds;
322 uint32_t bnx_rx_coal_bds_int;
323 uint32_t bnx_tx_coal_bds_int;
324 uint32_t bnx_mi_mode;
329 struct callout bnx_tick_timer;
336 struct bnx_intr_data bnx_intr_data[BNX_INTR_MAX];
338 struct sysctl_ctx_list bnx_sysctl_ctx;
339 struct sysctl_oid *bnx_sysctl_tree;
342 uint32_t bnx_coal_chg;
343 #define BNX_RX_COAL_TICKS_CHG 0x01
344 #define BNX_TX_COAL_TICKS_CHG 0x02
345 #define BNX_RX_COAL_BDS_CHG 0x04
346 #define BNX_TX_COAL_BDS_CHG 0x08
347 #define BNX_RX_COAL_BDS_INT_CHG 0x40
348 #define BNX_TX_COAL_BDS_INT_CHG 0x80
350 void (*bnx_link_upd)(struct bnx_softc *, uint32_t);
351 uint32_t bnx_link_chg;
353 #define BNX_TSO_NSTATS 45
354 u_long bnx_tsosegs[BNX_TSO_NSTATS];
357 #define BNX_NSEG_NEW 40
358 #define BNX_NSEG_SPARE 33 /* enough for 64K TSO segment */
359 #define BNX_NSEG_RSVD 4
361 /* RX coalesce ticks, unit: us */
362 #define BNX_RX_COAL_TICKS_MIN 0
363 #define BNX_RX_COAL_TICKS_DEF 160
364 #define BNX_RX_COAL_TICKS_MAX 1023
366 /* TX coalesce ticks, unit: us */
367 #define BNX_TX_COAL_TICKS_MIN 0
368 #define BNX_TX_COAL_TICKS_DEF 1023
369 #define BNX_TX_COAL_TICKS_MAX 1023
371 /* RX coalesce BDs */
372 #define BNX_RX_COAL_BDS_MIN 0
373 #define BNX_RX_COAL_BDS_DEF 0
374 #define BNX_RX_COAL_BDS_INT_DEF 80
375 #define BNX_RX_COAL_BDS_MAX 255
377 /* TX coalesce BDs */
378 #define BNX_TX_COAL_BDS_MIN 0
379 #define BNX_TX_COAL_BDS_DEF 64
380 #define BNX_TX_COAL_BDS_INT_DEF 64
381 #define BNX_TX_COAL_BDS_MAX 255
383 /* Number of segments sent before writing to TX related registers */
384 #define BNX_TX_WREG_NSEGS 8
386 /* Return ring descriptor count */
387 #define BNX_RETURN_RING_CNT 512
389 #define BNX_TX_RING_MAX 4
391 #endif /* !_IF_BNXVAR_H_ */