2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
35 * $DragonFly: src/sys/cpu/amd64/include/cpufunc.h,v 1.2 2007/09/23 04:29:30 yanyh Exp $
39 * Functions to provide access to special i386 instructions.
40 * This in included in sys/systm.h, and that file should be
41 * used in preference to this.
44 #ifndef _CPU_CPUFUNC_H_
45 #define _CPU_CPUFUNC_H_
47 #include <sys/cdefs.h>
48 #include <machine/psl.h>
51 struct region_descriptor;
54 #define readb(va) (*(volatile u_int8_t *) (va))
55 #define readw(va) (*(volatile u_int16_t *) (va))
56 #define readl(va) (*(volatile u_int32_t *) (va))
57 #define readq(va) (*(volatile u_int64_t *) (va))
59 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
60 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
61 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
62 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
69 __asm __volatile("int $3");
75 __asm __volatile("pause");
83 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
87 static __inline u_long
92 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
101 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
105 static __inline u_long
110 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
117 __asm __volatile("cli" : : : "memory");
121 do_cpuid(u_int ax, u_int *p)
123 __asm __volatile("cpuid"
124 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
129 cpu_enable_intr(void)
131 __asm __volatile("sti");
135 * Cpu and compiler memory ordering fence. mfence ensures strong read and
138 * A serializing or fence instruction is required here. A locked bus
139 * cycle on data for which we already own cache mastership is the most
146 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
148 __asm __volatile("" : : : "memory");
153 * cpu_lfence() ensures strong read ordering for reads issued prior
154 * to the instruction verses reads issued afterwords.
156 * A serializing or fence instruction is required here. A locked bus
157 * cycle on data for which we already own cache mastership is the most
164 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
166 __asm __volatile("" : : : "memory");
171 * cpu_sfence() ensures strong write ordering for writes issued prior
172 * to the instruction verses writes issued afterwords. Writes are
173 * ordered on intel cpus so we do not actually have to do anything.
178 __asm __volatile("" : : : "memory");
182 * cpu_ccfence() prevents the compiler from reordering instructions, in
183 * particular stores, relative to the current cpu. Use cpu_sfence() if
184 * you need to guarentee ordering by both the compiler and by the cpu.
186 * This also prevents the compiler from caching memory loads into local
187 * variables across the routine.
192 __asm __volatile("" : : : "memory");
197 #define HAVE_INLINE_FFS
204 * Note that gcc-2's builtin ffs would be used if we didn't declare
205 * this inline or turn off the builtin. The builtin is faster but
206 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
209 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
211 /* Actually, the above is way out of date. The builtins use cmov etc */
212 return (__builtin_ffs(mask));
216 #define HAVE_INLINE_FFSL
221 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
224 #define HAVE_INLINE_FLS
229 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
232 #define HAVE_INLINE_FLSL
237 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
245 __asm __volatile("hlt");
249 * The following complications are to get around gcc not having a
250 * constraint letter for the range 0..255. We still put "d" in the
251 * constraint because "i" isn't a valid constraint when the port
252 * isn't constant. This only matters for -O0 because otherwise
253 * the non-working version gets optimized away.
255 * Use an expression-statement instead of a conditional expression
256 * because gcc-2.6.0 would promote the operands of the conditional
257 * and produce poor code for "if ((inb(var) & const1) == const2)".
259 * The unnecessary test `(port) < 0x10000' is to generate a warning if
260 * the `port' has type u_short or smaller. Such types are pessimal.
261 * This actually only works for signed types. The range check is
262 * careful to avoid generating warnings.
264 #define inb(port) __extension__ ({ \
266 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
267 && (port) < 0x10000) \
268 _data = inbc(port); \
270 _data = inbv(port); \
273 #define outb(port, data) ( \
274 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
275 && (port) < 0x10000 \
276 ? outbc(port, data) : outbv(port, data))
278 static __inline u_char
283 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
288 outbc(u_int port, u_char data)
290 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
293 static __inline u_char
298 * We use %%dx and not %1 here because i/o is done at %dx and not at
299 * %edx, while gcc generates inferior code (movw instead of movl)
300 * if we tell it to load (u_short) port.
302 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
306 static __inline u_int
311 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
316 insb(u_int port, void *addr, size_t cnt)
318 __asm __volatile("cld; rep; insb"
319 : "+D" (addr), "+c" (cnt)
325 insw(u_int port, void *addr, size_t cnt)
327 __asm __volatile("cld; rep; insw"
328 : "+D" (addr), "+c" (cnt)
334 insl(u_int port, void *addr, size_t cnt)
336 __asm __volatile("cld; rep; insl"
337 : "+D" (addr), "+c" (cnt)
345 __asm __volatile("invd");
348 static __inline u_short
353 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
357 static __inline u_int
358 loadandclear(volatile u_int *addr)
362 __asm __volatile("xorl %0,%0; xchgl %1,%0"
363 : "=&r" (result) : "m" (*addr));
368 outbv(u_int port, u_char data)
372 * Use an unnecessary assignment to help gcc's register allocator.
373 * This make a large difference for gcc-1.40 and a tiny difference
374 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
375 * best results. gcc-2.6.0 can't handle this.
378 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
382 outl(u_int port, u_int data)
385 * outl() and outw() aren't used much so we haven't looked at
386 * possible micro-optimizations such as the unnecessary
387 * assignment for them.
389 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
393 outsb(u_int port, const void *addr, size_t cnt)
395 __asm __volatile("cld; rep; outsb"
396 : "+S" (addr), "+c" (cnt)
401 outsw(u_int port, const void *addr, size_t cnt)
403 __asm __volatile("cld; rep; outsw"
404 : "+S" (addr), "+c" (cnt)
409 outsl(u_int port, const void *addr, size_t cnt)
411 __asm __volatile("cld; rep; outsl"
412 : "+S" (addr), "+c" (cnt)
417 outw(u_int port, u_short data)
419 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
425 __asm __volatile("pause");
428 static __inline u_long
433 __asm __volatile("pushfq; popq %0" : "=r" (rf));
437 static __inline u_int64_t
442 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
443 return (low | ((u_int64_t)high << 32));
446 static __inline u_int64_t
451 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
452 return (low | ((u_int64_t)high << 32));
455 static __inline u_int64_t
460 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
461 return (low | ((u_int64_t)high << 32));
467 __asm __volatile("wbinvd");
471 write_rflags(u_long rf)
473 __asm __volatile("pushq %0; popfq" : : "r" (rf));
477 wrmsr(u_int msr, u_int64_t newval)
483 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
487 load_cr0(u_long data)
490 __asm __volatile("movq %0,%%cr0" : : "r" (data));
493 static __inline u_long
498 __asm __volatile("movq %%cr0,%0" : "=r" (data));
502 static __inline u_long
507 __asm __volatile("movq %%cr2,%0" : "=r" (data));
512 load_cr3(u_long data)
515 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
518 static __inline u_long
523 __asm __volatile("movq %%cr3,%0" : "=r" (data));
528 load_cr4(u_long data)
530 __asm __volatile("movq %0,%%cr4" : : "r" (data));
533 static __inline u_long
538 __asm __volatile("movq %%cr4,%0" : "=r" (data));
543 * Global TLB flush (except for thise for pages marked PG_G)
553 * TLB flush for an individual page (even if it has PG_G).
554 * Only works on 486+ CPUs (i386 does not have PG_G).
560 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
563 static __inline u_int
567 __asm __volatile("movl %%fs,%0" : "=rm" (sel));
571 static __inline u_int
575 __asm __volatile("movl %%gs,%0" : "=rm" (sel));
582 __asm __volatile("movl %0,%%ds" : : "rm" (sel));
588 __asm __volatile("movl %0,%%es" : : "rm" (sel));
592 /* This is defined in <machine/specialreg.h> but is too painful to get to */
594 #define MSR_FSBASE 0xc0000100
599 register u_int32_t fsbase __asm("ecx");
601 /* Preserve the fsbase value across the selector load */
603 __asm __volatile("rdmsr; movl %0,%%fs; wrmsr"
604 : : "rm" (sel), "c" (fsbase) : "eax", "edx");
608 #define MSR_GSBASE 0xc0000101
613 register u_int32_t gsbase __asm("ecx");
616 * Preserve the gsbase value across the selector load.
617 * Note that we have to disable interrupts because the gsbase
618 * being trashed happens to be the kernel gsbase at the time.
621 __asm __volatile("pushfq; cli; rdmsr; movl %0,%%gs; wrmsr; popfq"
622 : : "rm" (sel), "c" (gsbase) : "eax", "edx");
625 /* Usable by userland */
629 __asm __volatile("movl %0,%%fs" : : "rm" (sel));
635 __asm __volatile("movl %0,%%gs" : : "rm" (sel));
639 /* void lidt(struct region_descriptor *addr); */
641 lidt(struct region_descriptor *addr)
643 __asm __volatile("lidt (%0)" : : "r" (addr));
646 /* void lldt(u_short sel); */
650 __asm __volatile("lldt %0" : : "r" (sel));
653 /* void ltr(u_short sel); */
657 __asm __volatile("ltr %0" : : "r" (sel));
660 static __inline u_int64_t
664 __asm __volatile("movq %%dr0,%0" : "=r" (data));
669 load_dr0(u_int64_t dr0)
671 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
674 static __inline u_int64_t
678 __asm __volatile("movq %%dr1,%0" : "=r" (data));
683 load_dr1(u_int64_t dr1)
685 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
688 static __inline u_int64_t
692 __asm __volatile("movq %%dr2,%0" : "=r" (data));
697 load_dr2(u_int64_t dr2)
699 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
702 static __inline u_int64_t
706 __asm __volatile("movq %%dr3,%0" : "=r" (data));
711 load_dr3(u_int64_t dr3)
713 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
716 static __inline u_int64_t
720 __asm __volatile("movq %%dr4,%0" : "=r" (data));
725 load_dr4(u_int64_t dr4)
727 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
730 static __inline u_int64_t
734 __asm __volatile("movq %%dr5,%0" : "=r" (data));
739 load_dr5(u_int64_t dr5)
741 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
744 static __inline u_int64_t
748 __asm __volatile("movq %%dr6,%0" : "=r" (data));
753 load_dr6(u_int64_t dr6)
755 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
758 static __inline u_int64_t
762 __asm __volatile("movq %%dr7,%0" : "=r" (data));
767 load_dr7(u_int64_t dr7)
769 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
772 static __inline register_t
777 rflags = read_rflags();
783 intr_restore(register_t rflags)
785 write_rflags(rflags);
788 #else /* !__GNUC__ */
790 int breakpoint(void);
791 void cpu_pause(void);
792 u_int bsfl(u_int mask);
793 u_int bsrl(u_int mask);
794 void cpu_invlpg(u_long addr);
795 void cpu_invlpg_range(u_long start, u_long end);
796 void disable_intr(void);
797 void do_cpuid(u_int ax, u_int *p);
798 void enable_intr(void);
800 u_char inb(u_int port);
801 u_int inl(u_int port);
802 void insb(u_int port, void *addr, size_t cnt);
803 void insl(u_int port, void *addr, size_t cnt);
804 void insw(u_int port, void *addr, size_t cnt);
806 void invlpg(u_int addr);
807 void invlpg_range(u_int start, u_int end);
809 u_short inw(u_int port);
810 void load_cr0(u_int cr0);
811 void load_cr3(u_int cr3);
812 void load_cr4(u_int cr4);
813 void load_fs(u_int sel);
814 void load_gs(u_int sel);
815 struct region_descriptor;
816 void lidt(struct region_descriptor *addr);
817 void lldt(u_short sel);
818 void ltr(u_short sel);
819 void outb(u_int port, u_char data);
820 void outl(u_int port, u_int data);
821 void outsb(u_int port, void *addr, size_t cnt);
822 void outsl(u_int port, void *addr, size_t cnt);
823 void outsw(u_int port, void *addr, size_t cnt);
824 void outw(u_int port, u_short data);
825 void ia32_pause(void);
832 u_int64_t rdmsr(u_int msr);
833 u_int64_t rdpmc(u_int pmc);
834 u_int64_t rdtsc(void);
835 u_int read_rflags(void);
837 void write_rflags(u_int rf);
838 void wrmsr(u_int msr, u_int64_t newval);
839 u_int64_t rdr0(void);
840 void load_dr0(u_int64_t dr0);
841 u_int64_t rdr1(void);
842 void load_dr1(u_int64_t dr1);
843 u_int64_t rdr2(void);
844 void load_dr2(u_int64_t dr2);
845 u_int64_t rdr3(void);
846 void load_dr3(u_int64_t dr3);
847 u_int64_t rdr4(void);
848 void load_dr4(u_int64_t dr4);
849 u_int64_t rdr5(void);
850 void load_dr5(u_int64_t dr5);
851 u_int64_t rdr6(void);
852 void load_dr6(u_int64_t dr6);
853 u_int64_t rdr7(void);
854 void load_dr7(u_int64_t dr7);
855 register_t intr_disable(void);
856 void intr_restore(register_t rf);
858 #endif /* __GNUC__ */
860 void reset_dbregs(void);
864 #endif /* !_CPU_CPUFUNC_H_ */