sys/dev/drm/r600_cp.c

   1 /*-
   2  * Copyright 2008-2009 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Dave Airlie <airlied@redhat.com>
  26  *     Alex Deucher <alexander.deucher@amd.com>
  27  */
  28
  29 #include "dev/drm/drmP.h"
  30 #include "dev/drm/drm.h"
  31 #include "dev/drm/radeon_drm.h"
  32 #include "dev/drm/radeon_drv.h"
  33
  34 #include "dev/drm/r600_microcode.h"
  35
  36 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  37 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  38
  39 #define R600_PTE_VALID     (1 << 0)
  40 #define R600_PTE_SYSTEM    (1 << 1)
  41 #define R600_PTE_SNOOPED   (1 << 2)
  42 #define R600_PTE_READABLE  (1 << 5)
  43 #define R600_PTE_WRITEABLE (1 << 6)
  44
  45 /* MAX values used for gfx init */
  46 #define R6XX_MAX_SH_GPRS           256
  47 #define R6XX_MAX_TEMP_GPRS         16
  48 #define R6XX_MAX_SH_THREADS        256
  49 #define R6XX_MAX_SH_STACK_ENTRIES  4096
  50 #define R6XX_MAX_BACKENDS          8
  51 #define R6XX_MAX_BACKENDS_MASK     0xff
  52 #define R6XX_MAX_SIMDS             8
  53 #define R6XX_MAX_SIMDS_MASK        0xff
  54 #define R6XX_MAX_PIPES             8
  55 #define R6XX_MAX_PIPES_MASK        0xff
  56
  57 #define R7XX_MAX_SH_GPRS           256
  58 #define R7XX_MAX_TEMP_GPRS         16
  59 #define R7XX_MAX_SH_THREADS        256
  60 #define R7XX_MAX_SH_STACK_ENTRIES  4096
  61 #define R7XX_MAX_BACKENDS          8
  62 #define R7XX_MAX_BACKENDS_MASK     0xff
  63 #define R7XX_MAX_SIMDS             16
  64 #define R7XX_MAX_SIMDS_MASK        0xffff
  65 #define R7XX_MAX_PIPES             8
  66 #define R7XX_MAX_PIPES_MASK        0xff
  67
  68 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
  69 {
  70         int i;
  71
  72         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  73
  74         for (i = 0; i < dev_priv->usec_timeout; i++) {
  75                 int slots;
  76                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
  77                         slots = (RADEON_READ(R600_GRBM_STATUS)
  78                                  & R700_CMDFIFO_AVAIL_MASK);
  79                 else
  80                         slots = (RADEON_READ(R600_GRBM_STATUS)
  81                                  & R600_CMDFIFO_AVAIL_MASK);
  82                 if (slots >= entries)
  83                         return 0;
  84                 DRM_UDELAY(1);
  85         }
  86         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
  87                  RADEON_READ(R600_GRBM_STATUS),
  88                  RADEON_READ(R600_GRBM_STATUS2));
  89
  90         return -EBUSY;
  91 }
  92
  93 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
  94 {
  95         int i, ret;
  96
  97         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  98
  99         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 100                 ret = r600_do_wait_for_fifo(dev_priv, 8);
 101         else
 102                 ret = r600_do_wait_for_fifo(dev_priv, 16);
 103         if (ret)
 104                 return ret;
 105         for (i = 0; i < dev_priv->usec_timeout; i++) {
 106                 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
 107                         return 0;
 108                 DRM_UDELAY(1);
 109         }
 110         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 111                  RADEON_READ(R600_GRBM_STATUS),
 112                  RADEON_READ(R600_GRBM_STATUS2));
 113
 114         return -EBUSY;
 115 }
 116
 117 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 118 {
 119 #ifdef __linux__
 120         struct drm_sg_mem *entry = dev->sg;
 121         int max_pages;
 122         int pages;
 123         int i;
 124 #endif
 125         if (gart_info->bus_addr) {
 126 #ifdef __linux__
 127                 max_pages = (gart_info->table_size / sizeof(u32));
 128                 pages = (entry->pages <= max_pages)
 129                   ? entry->pages : max_pages;
 130
 131                 for (i = 0; i < pages; i++) {
 132                         if (!entry->busaddr[i])
 133                                 break;
 134                         pci_unmap_single(dev->pdev, entry->busaddr[i],
 135                                          PAGE_SIZE, PCI_DMA_TODEVICE);
 136                 }
 137 #endif
 138                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
 139                         gart_info->bus_addr = 0;
 140         }
 141 }
 142
 143 /* R600 has page table setup */
 144 int r600_page_table_init(struct drm_device *dev)
 145 {
 146         drm_radeon_private_t *dev_priv = dev->dev_private;
 147         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 148         struct drm_sg_mem *entry = dev->sg;
 149         int ret = 0;
 150         int i, j;
 151         int max_pages, pages;
 152         u64 *pci_gart, page_base;
 153         dma_addr_t entry_addr;
 154
 155         /* okay page table is available - lets rock */
 156
 157         /* PTEs are 64-bits */
 158         pci_gart = (u64 *)gart_info->addr;
 159
 160         max_pages = (gart_info->table_size / sizeof(u64));
 161         pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
 162
 163         memset(pci_gart, 0, max_pages * sizeof(u64));
 164
 165         for (i = 0; i < pages; i++) {
 166 #ifdef __linux__
 167                 entry->busaddr[i] = pci_map_single(dev->pdev,
 168                                                    page_address(entry->
 169                                                                 pagelist[i]),
 170                                                    PAGE_SIZE, PCI_DMA_TODEVICE);
 171                 if (entry->busaddr[i] == 0) {
 172                         DRM_ERROR("unable to map PCIGART pages!\n");
 173                         r600_page_table_cleanup(dev, gart_info);
 174                         goto done;
 175                 }
 176 #endif
 177                 entry_addr = entry->busaddr[i];
 178                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 179                         page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
 180                         page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 181                         page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 182
 183                         *pci_gart = page_base;
 184
 185                         if ((i % 128) == 0)
 186                                 DRM_DEBUG("page entry %d: 0x%016llx\n",
 187                                     i, (unsigned long long)page_base);
 188                         pci_gart++;
 189                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 190                 }
 191         }
 192         ret = 1;
 193 #ifdef __linux__
 194 done:
 195 #endif
 196         return ret;
 197 }
 198
 199 static void r600_vm_flush_gart_range(struct drm_device *dev)
 200 {
 201         drm_radeon_private_t *dev_priv = dev->dev_private;
 202         u32 resp, countdown = 1000;
 203         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 204         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 205         RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
 206
 207         do {
 208                 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
 209                 countdown--;
 210                 DRM_UDELAY(1);
 211         } while (((resp & 0xf0) == 0) && countdown);
 212 }
 213
 214 static void r600_vm_init(struct drm_device *dev)
 215 {
 216         drm_radeon_private_t *dev_priv = dev->dev_private;
 217         /* initialise the VM to use the page table we constructed up there */
 218         u32 vm_c0, i;
 219         u32 mc_rd_a;
 220         u32 vm_l2_cntl, vm_l2_cntl3;
 221         /* okay set up the PCIE aperture type thingo */
 222         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 223         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 224         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 225
 226         /* setup MC RD a */
 227         mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
 228                 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
 229                 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
 230
 231         RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
 232         RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
 233
 234         RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
 235         RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
 236
 237         RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
 238         RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
 239
 240         RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
 241         RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
 242
 243         RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
 244         RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
 245
 246         RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
 247         RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
 248
 249         RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
 250         RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
 251
 252         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 253         vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
 254         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 255
 256         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 257         vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
 258                        R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
 259                        R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
 260         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 261
 262         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 263
 264         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 265
 266         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 267
 268         /* disable all other contexts */
 269         for (i = 1; i < 8; i++)
 270                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 271
 272         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 273         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 274         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 275
 276         r600_vm_flush_gart_range(dev);
 277 }
 278
 279 /* load r600 microcode */
 280 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 281 {
 282         int i;
 283
 284         r600_do_cp_stop(dev_priv);
 285
 286         RADEON_WRITE(R600_CP_RB_CNTL,
 287                      R600_RB_NO_UPDATE |
 288                      R600_RB_BLKSZ(15) |
 289                      R600_RB_BUFSZ(3));
 290
 291         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 292         RADEON_READ(R600_GRBM_SOFT_RESET);
 293         DRM_UDELAY(15000);
 294         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 295
 296         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 297
 298         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) {
 299                 DRM_INFO("Loading R600 CP Microcode\n");
 300                 for (i = 0; i < PM4_UCODE_SIZE; i++) {
 301                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 302                                      R600_cp_microcode[i][0]);
 303                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 304                                      R600_cp_microcode[i][1]);
 305                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 306                                      R600_cp_microcode[i][2]);
 307                 }
 308
 309                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 310                 DRM_INFO("Loading R600 PFP Microcode\n");
 311                 for (i = 0; i < PFP_UCODE_SIZE; i++)
 312                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]);
 313         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) {
 314                 DRM_INFO("Loading RV610 CP Microcode\n");
 315                 for (i = 0; i < PM4_UCODE_SIZE; i++) {
 316                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 317                                      RV610_cp_microcode[i][0]);
 318                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 319                                      RV610_cp_microcode[i][1]);
 320                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 321                                      RV610_cp_microcode[i][2]);
 322                 }
 323
 324                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 325                 DRM_INFO("Loading RV610 PFP Microcode\n");
 326                 for (i = 0; i < PFP_UCODE_SIZE; i++)
 327                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]);
 328         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
 329                 DRM_INFO("Loading RV630 CP Microcode\n");
 330                 for (i = 0; i < PM4_UCODE_SIZE; i++) {
 331                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 332                                      RV630_cp_microcode[i][0]);
 333                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 334                                      RV630_cp_microcode[i][1]);
 335                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 336                                      RV630_cp_microcode[i][2]);
 337                 }
 338
 339                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 340                 DRM_INFO("Loading RV630 PFP Microcode\n");
 341                 for (i = 0; i < PFP_UCODE_SIZE; i++)
 342                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]);
 343         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) {
 344                 DRM_INFO("Loading RV620 CP Microcode\n");
 345                 for (i = 0; i < PM4_UCODE_SIZE; i++) {
 346                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 347                                      RV620_cp_microcode[i][0]);
 348                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 349                                      RV620_cp_microcode[i][1]);
 350                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 351                                      RV620_cp_microcode[i][2]);
 352                 }
 353
 354                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 355                 DRM_INFO("Loading RV620 PFP Microcode\n");
 356                 for (i = 0; i < PFP_UCODE_SIZE; i++)
 357                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]);
 358         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
 359                 DRM_INFO("Loading RV635 CP Microcode\n");
 360                 for (i = 0; i < PM4_UCODE_SIZE; i++) {
 361                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 362                                      RV635_cp_microcode[i][0]);
 363                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 364                                      RV635_cp_microcode[i][1]);
 365                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 366                                      RV635_cp_microcode[i][2]);
 367                 }
 368
 369                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 370                 DRM_INFO("Loading RV635 PFP Microcode\n");
 371                 for (i = 0; i < PFP_UCODE_SIZE; i++)
 372                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]);
 373         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) {
 374                 DRM_INFO("Loading RV670 CP Microcode\n");
 375                 for (i = 0; i < PM4_UCODE_SIZE; i++) {
 376                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 377                                      RV670_cp_microcode[i][0]);
 378                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 379                                      RV670_cp_microcode[i][1]);
 380                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 381                                      RV670_cp_microcode[i][2]);
 382                 }
 383
 384                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 385                 DRM_INFO("Loading RV670 PFP Microcode\n");
 386                 for (i = 0; i < PFP_UCODE_SIZE; i++)
 387                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
 388         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
 389                 DRM_INFO("Loading RS780 CP Microcode\n");
 390                 for (i = 0; i < PM4_UCODE_SIZE; i++) {
 391                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 392                                      RV670_cp_microcode[i][0]);
 393                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 394                                      RV670_cp_microcode[i][1]);
 395                         RADEON_WRITE(R600_CP_ME_RAM_DATA,
 396                                      RV670_cp_microcode[i][2]);
 397                 }
 398
 399                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 400                 DRM_INFO("Loading RS780 PFP Microcode\n");
 401                 for (i = 0; i < PFP_UCODE_SIZE; i++)
 402                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
 403         }
 404         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 405         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 406         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 407
 408 }
 409
 410 static void r700_vm_init(struct drm_device *dev)
 411 {
 412         drm_radeon_private_t *dev_priv = dev->dev_private;
 413         /* initialise the VM to use the page table we constructed up there */
 414         u32 vm_c0, i;
 415         u32 mc_vm_md_l1;
 416         u32 vm_l2_cntl, vm_l2_cntl3;
 417         /* okay set up the PCIE aperture type thingo */
 418         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 419         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 420         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 421
 422         mc_vm_md_l1 = R700_ENABLE_L1_TLB |
 423             R700_ENABLE_L1_FRAGMENT_PROCESSING |
 424             R700_SYSTEM_ACCESS_MODE_IN_SYS |
 425             R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 426             R700_EFFECTIVE_L1_TLB_SIZE(5) |
 427             R700_EFFECTIVE_L1_QUEUE_SIZE(5);
 428
 429         RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
 430         RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
 431         RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
 432         RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
 433         RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
 434         RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
 435         RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
 436
 437         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 438         vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
 439         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 440
 441         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 442         vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
 443         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 444
 445         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 446
 447         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 448
 449         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 450
 451         /* disable all other contexts */
 452         for (i = 1; i < 8; i++)
 453                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 454
 455         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 456         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 457         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 458
 459         r600_vm_flush_gart_range(dev);
 460 }
 461
 462 /* load r600 microcode */
 463 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 464 {
 465         int i;
 466
 467         r600_do_cp_stop(dev_priv);
 468
 469         RADEON_WRITE(R600_CP_RB_CNTL,
 470                      R600_RB_NO_UPDATE |
 471                      (15 << 8) |
 472                      (3 << 0));
 473
 474         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 475         RADEON_READ(R600_GRBM_SOFT_RESET);
 476         DRM_UDELAY(15000);
 477         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 478
 479
 480         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) {
 481                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 482                 DRM_INFO("Loading RV770 PFP Microcode\n");
 483                 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 484                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]);
 485                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 486
 487                 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 488                 DRM_INFO("Loading RV770 CP Microcode\n");
 489                 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 490                         RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
 491                 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 492
 493         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) {
 494                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 495                 DRM_INFO("Loading RV730 PFP Microcode\n");
 496                 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 497                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
 498                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 499
 500                 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 501                 DRM_INFO("Loading RV730 CP Microcode\n");
 502                 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 503                         RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
 504                 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 505
 506         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) {
 507                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 508                 DRM_INFO("Loading RV710 PFP Microcode\n");
 509                 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 510                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]);
 511                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 512
 513                 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 514                 DRM_INFO("Loading RV710 CP Microcode\n");
 515                 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 516                         RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]);
 517                 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 518
 519         }
 520         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 521         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 522         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 523
 524 }
 525
 526 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
 527 {
 528         u32 tmp;
 529
 530         /* Start with assuming that writeback doesn't work */
 531         dev_priv->writeback_works = 0;
 532
 533         /* Writeback doesn't seem to work everywhere, test it here and possibly
 534          * enable it if it appears to work
 535          */
 536         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
 537
 538         RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
 539
 540         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 541                 u32 val;
 542
 543                 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
 544                 if (val == 0xdeadbeef)
 545                         break;
 546                 DRM_UDELAY(1);
 547         }
 548
 549         if (tmp < dev_priv->usec_timeout) {
 550                 dev_priv->writeback_works = 1;
 551                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 552         } else {
 553                 dev_priv->writeback_works = 0;
 554                 DRM_INFO("writeback test failed\n");
 555         }
 556         if (radeon_no_wb == 1) {
 557                 dev_priv->writeback_works = 0;
 558                 DRM_INFO("writeback forced off\n");
 559         }
 560
 561         if (!dev_priv->writeback_works) {
 562                 /* Disable writeback to avoid unnecessary bus master transfer */
 563                 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
 564                              RADEON_RB_NO_UPDATE);
 565                 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
 566         }
 567 }
 568
 569 int r600_do_engine_reset(struct drm_device *dev)
 570 {
 571         drm_radeon_private_t *dev_priv = dev->dev_private;
 572         u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
 573
 574         DRM_INFO("Resetting GPU\n");
 575
 576         cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
 577         cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
 578         RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
 579
 580         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
 581         RADEON_READ(R600_GRBM_SOFT_RESET);
 582         DRM_UDELAY(50);
 583         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 584         RADEON_READ(R600_GRBM_SOFT_RESET);
 585
 586         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
 587         cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
 588         RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
 589
 590         RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
 591         RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
 592         RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
 593         RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
 594
 595         /* Reset the CP ring */
 596         r600_do_cp_reset(dev_priv);
 597
 598         /* The CP is no longer running after an engine reset */
 599         dev_priv->cp_running = 0;
 600
 601         /* Reset any pending vertex, indirect buffers */
 602         radeon_freelist_reset(dev);
 603
 604         return 0;
 605
 606 }
 607
 608 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 609                                              u32 num_backends,
 610                                              u32 backend_disable_mask)
 611 {
 612         u32 backend_map = 0;
 613         u32 enabled_backends_mask;
 614         u32 enabled_backends_count;
 615         u32 cur_pipe;
 616         u32 swizzle_pipe[R6XX_MAX_PIPES];
 617         u32 cur_backend;
 618         u32 i;
 619
 620         if (num_tile_pipes > R6XX_MAX_PIPES)
 621                 num_tile_pipes = R6XX_MAX_PIPES;
 622         if (num_tile_pipes < 1)
 623                 num_tile_pipes = 1;
 624         if (num_backends > R6XX_MAX_BACKENDS)
 625                 num_backends = R6XX_MAX_BACKENDS;
 626         if (num_backends < 1)
 627                 num_backends = 1;
 628
 629         enabled_backends_mask = 0;
 630         enabled_backends_count = 0;
 631         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 632                 if (((backend_disable_mask >> i) & 1) == 0) {
 633                         enabled_backends_mask |= (1 << i);
 634                         ++enabled_backends_count;
 635                 }
 636                 if (enabled_backends_count == num_backends)
 637                         break;
 638         }
 639
 640         if (enabled_backends_count == 0) {
 641                 enabled_backends_mask = 1;
 642                 enabled_backends_count = 1;
 643         }
 644
 645         if (enabled_backends_count != num_backends)
 646                 num_backends = enabled_backends_count;
 647
 648         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 649         switch (num_tile_pipes) {
 650         case 1:
 651                 swizzle_pipe[0] = 0;
 652                 break;
 653         case 2:
 654                 swizzle_pipe[0] = 0;
 655                 swizzle_pipe[1] = 1;
 656                 break;
 657         case 3:
 658                 swizzle_pipe[0] = 0;
 659                 swizzle_pipe[1] = 1;
 660                 swizzle_pipe[2] = 2;
 661                 break;
 662         case 4:
 663                 swizzle_pipe[0] = 0;
 664                 swizzle_pipe[1] = 1;
 665                 swizzle_pipe[2] = 2;
 666                 swizzle_pipe[3] = 3;
 667                 break;
 668         case 5:
 669                 swizzle_pipe[0] = 0;
 670                 swizzle_pipe[1] = 1;
 671                 swizzle_pipe[2] = 2;
 672                 swizzle_pipe[3] = 3;
 673                 swizzle_pipe[4] = 4;
 674                 break;
 675         case 6:
 676                 swizzle_pipe[0] = 0;
 677                 swizzle_pipe[1] = 2;
 678                 swizzle_pipe[2] = 4;
 679                 swizzle_pipe[3] = 5;
 680                 swizzle_pipe[4] = 1;
 681                 swizzle_pipe[5] = 3;
 682                 break;
 683         case 7:
 684                 swizzle_pipe[0] = 0;
 685                 swizzle_pipe[1] = 2;
 686                 swizzle_pipe[2] = 4;
 687                 swizzle_pipe[3] = 6;
 688                 swizzle_pipe[4] = 1;
 689                 swizzle_pipe[5] = 3;
 690                 swizzle_pipe[6] = 5;
 691                 break;
 692         case 8:
 693                 swizzle_pipe[0] = 0;
 694                 swizzle_pipe[1] = 2;
 695                 swizzle_pipe[2] = 4;
 696                 swizzle_pipe[3] = 6;
 697                 swizzle_pipe[4] = 1;
 698                 swizzle_pipe[5] = 3;
 699                 swizzle_pipe[6] = 5;
 700                 swizzle_pipe[7] = 7;
 701                 break;
 702         }
 703
 704         cur_backend = 0;
 705         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 706                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 707                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 708
 709                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 710
 711                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 712         }
 713
 714         return backend_map;
 715 }
 716
 717 static int r600_count_pipe_bits(uint32_t val)
 718 {
 719         int i, ret = 0;
 720         for (i = 0; i < 32; i++) {
 721                 ret += val & 1;
 722                 val >>= 1;
 723         }
 724         return ret;
 725 }
 726
 727 static void r600_gfx_init(struct drm_device *dev,
 728                           drm_radeon_private_t *dev_priv)
 729 {
 730         int i, j, num_qd_pipes;
 731         u32 sx_debug_1;
 732         u32 tc_cntl;
 733         u32 arb_pop;
 734         u32 num_gs_verts_per_thread;
 735         u32 vgt_gs_per_es;
 736         u32 gs_prim_buffer_depth = 0;
 737         u32 sq_ms_fifo_sizes;
 738         u32 sq_config;
 739         u32 sq_gpr_resource_mgmt_1 = 0;
 740         u32 sq_gpr_resource_mgmt_2 = 0;
 741         u32 sq_thread_resource_mgmt = 0;
 742         u32 sq_stack_resource_mgmt_1 = 0;
 743         u32 sq_stack_resource_mgmt_2 = 0;
 744         u32 hdp_host_path_cntl;
 745         u32 backend_map;
 746         u32 gb_tiling_config = 0;
 747         u32 cc_rb_backend_disable = 0;
 748         u32 cc_gc_shader_pipe_config = 0;
 749         u32 ramcfg;
 750
 751         /* setup chip specs */
 752         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 753         case CHIP_R600:
 754                 dev_priv->r600_max_pipes = 4;
 755                 dev_priv->r600_max_tile_pipes = 8;
 756                 dev_priv->r600_max_simds = 4;
 757                 dev_priv->r600_max_backends = 4;
 758                 dev_priv->r600_max_gprs = 256;
 759                 dev_priv->r600_max_threads = 192;
 760                 dev_priv->r600_max_stack_entries = 256;
 761                 dev_priv->r600_max_hw_contexts = 8;
 762                 dev_priv->r600_max_gs_threads = 16;
 763                 dev_priv->r600_sx_max_export_size = 128;
 764                 dev_priv->r600_sx_max_export_pos_size = 16;
 765                 dev_priv->r600_sx_max_export_smx_size = 128;
 766                 dev_priv->r600_sq_num_cf_insts = 2;
 767                 break;
 768         case CHIP_RV630:
 769         case CHIP_RV635:
 770                 dev_priv->r600_max_pipes = 2;
 771                 dev_priv->r600_max_tile_pipes = 2;
 772                 dev_priv->r600_max_simds = 3;
 773                 dev_priv->r600_max_backends = 1;
 774                 dev_priv->r600_max_gprs = 128;
 775                 dev_priv->r600_max_threads = 192;
 776                 dev_priv->r600_max_stack_entries = 128;
 777                 dev_priv->r600_max_hw_contexts = 8;
 778                 dev_priv->r600_max_gs_threads = 4;
 779                 dev_priv->r600_sx_max_export_size = 128;
 780                 dev_priv->r600_sx_max_export_pos_size = 16;
 781                 dev_priv->r600_sx_max_export_smx_size = 128;
 782                 dev_priv->r600_sq_num_cf_insts = 2;
 783                 break;
 784         case CHIP_RV610:
 785         case CHIP_RS780:
 786         case CHIP_RV620:
 787                 dev_priv->r600_max_pipes = 1;
 788                 dev_priv->r600_max_tile_pipes = 1;
 789                 dev_priv->r600_max_simds = 2;
 790                 dev_priv->r600_max_backends = 1;
 791                 dev_priv->r600_max_gprs = 128;
 792                 dev_priv->r600_max_threads = 192;
 793                 dev_priv->r600_max_stack_entries = 128;
 794                 dev_priv->r600_max_hw_contexts = 4;
 795                 dev_priv->r600_max_gs_threads = 4;
 796                 dev_priv->r600_sx_max_export_size = 128;
 797                 dev_priv->r600_sx_max_export_pos_size = 16;
 798                 dev_priv->r600_sx_max_export_smx_size = 128;
 799                 dev_priv->r600_sq_num_cf_insts = 1;
 800                 break;
 801         case CHIP_RV670:
 802                 dev_priv->r600_max_pipes = 4;
 803                 dev_priv->r600_max_tile_pipes = 4;
 804                 dev_priv->r600_max_simds = 4;
 805                 dev_priv->r600_max_backends = 4;
 806                 dev_priv->r600_max_gprs = 192;
 807                 dev_priv->r600_max_threads = 192;
 808                 dev_priv->r600_max_stack_entries = 256;
 809                 dev_priv->r600_max_hw_contexts = 8;
 810                 dev_priv->r600_max_gs_threads = 16;
 811                 dev_priv->r600_sx_max_export_size = 128;
 812                 dev_priv->r600_sx_max_export_pos_size = 16;
 813                 dev_priv->r600_sx_max_export_smx_size = 128;
 814                 dev_priv->r600_sq_num_cf_insts = 2;
 815                 break;
 816         default:
 817                 break;
 818         }
 819
 820         /* Initialize HDP */
 821         j = 0;
 822         for (i = 0; i < 32; i++) {
 823                 RADEON_WRITE((0x2c14 + j), 0x00000000);
 824                 RADEON_WRITE((0x2c18 + j), 0x00000000);
 825                 RADEON_WRITE((0x2c1c + j), 0x00000000);
 826                 RADEON_WRITE((0x2c20 + j), 0x00000000);
 827                 RADEON_WRITE((0x2c24 + j), 0x00000000);
 828                 j += 0x18;
 829         }
 830
 831         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
 832
 833         /* setup tiling, simd, pipe config */
 834         ramcfg = RADEON_READ(R600_RAMCFG);
 835
 836         switch (dev_priv->r600_max_tile_pipes) {
 837         case 1:
 838                 gb_tiling_config |= R600_PIPE_TILING(0);
 839                 break;
 840         case 2:
 841                 gb_tiling_config |= R600_PIPE_TILING(1);
 842                 break;
 843         case 4:
 844                 gb_tiling_config |= R600_PIPE_TILING(2);
 845                 break;
 846         case 8:
 847                 gb_tiling_config |= R600_PIPE_TILING(3);
 848                 break;
 849         default:
 850                 break;
 851         }
 852
 853         gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
 854
 855         gb_tiling_config |= R600_GROUP_SIZE(0);
 856
 857         if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
 858                 gb_tiling_config |= R600_ROW_TILING(3);
 859                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
 860         } else {
 861                 gb_tiling_config |=
 862                         R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 863                 gb_tiling_config |=
 864                         R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 865         }
 866
 867         gb_tiling_config |= R600_BANK_SWAPS(1);
 868
 869         backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
 870                                                         dev_priv->r600_max_backends,
 871                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
 872         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
 873
 874         cc_gc_shader_pipe_config =
 875                 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
 876         cc_gc_shader_pipe_config |=
 877                 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
 878
 879         cc_rb_backend_disable =
 880                 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
 881
 882         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
 883         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 884         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 885
 886         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 887         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 888         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 889
 890         num_qd_pipes =
 891                 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
 892         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
 893         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
 894
 895         /* set HW defaults for 3D engine */
 896         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
 897                                                 R600_ROQ_IB2_START(0x2b)));
 898
 899         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
 900                                               R600_ROQ_END(0x40)));
 901
 902         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
 903                                         R600_SYNC_GRADIENT |
 904                                         R600_SYNC_WALKER |
 905                                         R600_SYNC_ALIGNER));
 906
 907         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
 908                 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
 909
 910         sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
 911         sx_debug_1 |= R600_SMX_EVENT_RELEASE;
 912         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
 913                 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
 914         RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
 915
 916         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 917             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 918             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 919             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 920             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
 921                 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 922         else
 923                 RADEON_WRITE(R600_DB_DEBUG, 0);
 924
 925         RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
 926                                           R600_DEPTH_FLUSH(16) |
 927                                           R600_DEPTH_PENDING_FREE(4) |
 928                                           R600_DEPTH_CACHELINE_FREE(16)));
 929         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
 930         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
 931
 932         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
 933         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
 934
 935         sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
 936         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 937             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 938             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
 939                 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
 940                                     R600_FETCH_FIFO_HIWATER(0xa) |
 941                                     R600_DONE_FIFO_HIWATER(0xe0) |
 942                                     R600_ALU_UPDATE_FIFO_HIWATER(0x8));
 943         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 944                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
 945                 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
 946                 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
 947         }
 948         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 949
 950         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 951          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 952          */
 953         sq_config = RADEON_READ(R600_SQ_CONFIG);
 954         sq_config &= ~(R600_PS_PRIO(3) |
 955                        R600_VS_PRIO(3) |
 956                        R600_GS_PRIO(3) |
 957                        R600_ES_PRIO(3));
 958         sq_config |= (R600_DX9_CONSTS |
 959                       R600_VC_ENABLE |
 960                       R600_PS_PRIO(0) |
 961                       R600_VS_PRIO(1) |
 962                       R600_GS_PRIO(2) |
 963                       R600_ES_PRIO(3));
 964
 965         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
 966                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
 967                                           R600_NUM_VS_GPRS(124) |
 968                                           R600_NUM_CLAUSE_TEMP_GPRS(4));
 969                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
 970                                           R600_NUM_ES_GPRS(0));
 971                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
 972                                            R600_NUM_VS_THREADS(48) |
 973                                            R600_NUM_GS_THREADS(4) |
 974                                            R600_NUM_ES_THREADS(4));
 975                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
 976                                             R600_NUM_VS_STACK_ENTRIES(128));
 977                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
 978                                             R600_NUM_ES_STACK_ENTRIES(0));
 979         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 980                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 981                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
 982                 /* no vertex cache */
 983                 sq_config &= ~R600_VC_ENABLE;
 984
 985                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 986                                           R600_NUM_VS_GPRS(44) |
 987                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 988                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 989                                           R600_NUM_ES_GPRS(17));
 990                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 991                                            R600_NUM_VS_THREADS(78) |
 992                                            R600_NUM_GS_THREADS(4) |
 993                                            R600_NUM_ES_THREADS(31));
 994                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
 995                                             R600_NUM_VS_STACK_ENTRIES(40));
 996                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
 997                                             R600_NUM_ES_STACK_ENTRIES(16));
 998         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 999                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1000                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1001                                           R600_NUM_VS_GPRS(44) |
1002                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
1003                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
1004                                           R600_NUM_ES_GPRS(18));
1005                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1006                                            R600_NUM_VS_THREADS(78) |
1007                                            R600_NUM_GS_THREADS(4) |
1008                                            R600_NUM_ES_THREADS(31));
1009                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1010                                             R600_NUM_VS_STACK_ENTRIES(40));
1011                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1012                                             R600_NUM_ES_STACK_ENTRIES(16));
1013         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1014                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1015                                           R600_NUM_VS_GPRS(44) |
1016                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
1017                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1018                                           R600_NUM_ES_GPRS(17));
1019                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1020                                            R600_NUM_VS_THREADS(78) |
1021                                            R600_NUM_GS_THREADS(4) |
1022                                            R600_NUM_ES_THREADS(31));
1023                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1024                                             R600_NUM_VS_STACK_ENTRIES(64));
1025                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1026                                             R600_NUM_ES_STACK_ENTRIES(64));
1027         }
1028
1029         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1030         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1031         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1032         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1033         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1034         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1035
1036         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1037             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1038             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
1039                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1040         else
1041                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1042
1043         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1044                                                     R600_S0_Y(0x4) |
1045                                                     R600_S1_X(0x4) |
1046                                                     R600_S1_Y(0xc)));
1047         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1048                                                     R600_S0_Y(0xe) |
1049                                                     R600_S1_X(0x2) |
1050                                                     R600_S1_Y(0x2) |
1051                                                     R600_S2_X(0xa) |
1052                                                     R600_S2_Y(0x6) |
1053                                                     R600_S3_X(0x6) |
1054                                                     R600_S3_Y(0xa)));
1055         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1056                                                         R600_S0_Y(0xb) |
1057                                                         R600_S1_X(0x4) |
1058                                                         R600_S1_Y(0xc) |
1059                                                         R600_S2_X(0x1) |
1060                                                         R600_S2_Y(0x6) |
1061                                                         R600_S3_X(0xa) |
1062                                                         R600_S3_Y(0xe)));
1063         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1064                                                         R600_S4_Y(0x1) |
1065                                                         R600_S5_X(0x0) |
1066                                                         R600_S5_Y(0x0) |
1067                                                         R600_S6_X(0xb) |
1068                                                         R600_S6_Y(0x4) |
1069                                                         R600_S7_X(0x7) |
1070                                                         R600_S7_Y(0x8)));
1071
1072
1073         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1074         case CHIP_R600:
1075         case CHIP_RV630:
1076         case CHIP_RV635:
1077                 gs_prim_buffer_depth = 0;
1078                 break;
1079         case CHIP_RV610:
1080         case CHIP_RS780:
1081         case CHIP_RV620:
1082                 gs_prim_buffer_depth = 32;
1083                 break;
1084         case CHIP_RV670:
1085                 gs_prim_buffer_depth = 128;
1086                 break;
1087         default:
1088                 break;
1089         }
1090
1091         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1092         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1093         /* Max value for this is 256 */
1094         if (vgt_gs_per_es > 256)
1095                 vgt_gs_per_es = 256;
1096
1097         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1098         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1099         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1100         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1101
1102         /* more default values. 2D/3D driver should adjust as needed */
1103         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1104         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1105         RADEON_WRITE(R600_SX_MISC, 0);
1106         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1107         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1108         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1109         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1110         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1111         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1112
1113         /* clear render buffer base addresses */
1114         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1115         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1116         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1117         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1118         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1119         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1120         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1121         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1122
1123         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1124         case CHIP_RV610:
1125         case CHIP_RS780:
1126         case CHIP_RV620:
1127                 tc_cntl = R600_TC_L2_SIZE(8);
1128                 break;
1129         case CHIP_RV630:
1130         case CHIP_RV635:
1131                 tc_cntl = R600_TC_L2_SIZE(4);
1132                 break;
1133         case CHIP_R600:
1134                 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1135                 break;
1136         default:
1137                 tc_cntl = R600_TC_L2_SIZE(0);
1138                 break;
1139         }
1140
1141         RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1142
1143         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1144         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1145
1146         arb_pop = RADEON_READ(R600_ARB_POP);
1147         arb_pop |= R600_ENABLE_TC128;
1148         RADEON_WRITE(R600_ARB_POP, arb_pop);
1149
1150         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1151         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1152                                           R600_NUM_CLIP_SEQ(3)));
1153         RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1154
1155 }
1156
1157 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1158                                              u32 num_backends,
1159                                              u32 backend_disable_mask)
1160 {
1161         u32 backend_map = 0;
1162         u32 enabled_backends_mask;
1163         u32 enabled_backends_count;
1164         u32 cur_pipe;
1165         u32 swizzle_pipe[R7XX_MAX_PIPES];
1166         u32 cur_backend;
1167         u32 i;
1168
1169         if (num_tile_pipes > R7XX_MAX_PIPES)
1170                 num_tile_pipes = R7XX_MAX_PIPES;
1171         if (num_tile_pipes < 1)
1172                 num_tile_pipes = 1;
1173         if (num_backends > R7XX_MAX_BACKENDS)
1174                 num_backends = R7XX_MAX_BACKENDS;
1175         if (num_backends < 1)
1176                 num_backends = 1;
1177
1178         enabled_backends_mask = 0;
1179         enabled_backends_count = 0;
1180         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1181                 if (((backend_disable_mask >> i) & 1) == 0) {
1182                         enabled_backends_mask |= (1 << i);
1183                         ++enabled_backends_count;
1184                 }
1185                 if (enabled_backends_count == num_backends)
1186                         break;
1187         }
1188
1189         if (enabled_backends_count == 0) {
1190                 enabled_backends_mask = 1;
1191                 enabled_backends_count = 1;
1192         }
1193
1194         if (enabled_backends_count != num_backends)
1195                 num_backends = enabled_backends_count;
1196
1197         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1198         switch (num_tile_pipes) {
1199         case 1:
1200                 swizzle_pipe[0] = 0;
1201                 break;
1202         case 2:
1203                 swizzle_pipe[0] = 0;
1204                 swizzle_pipe[1] = 1;
1205                 break;
1206         case 3:
1207                 swizzle_pipe[0] = 0;
1208                 swizzle_pipe[1] = 2;
1209                 swizzle_pipe[2] = 1;
1210                 break;
1211         case 4:
1212                 swizzle_pipe[0] = 0;
1213                 swizzle_pipe[1] = 2;
1214                 swizzle_pipe[2] = 3;
1215                 swizzle_pipe[3] = 1;
1216                 break;
1217         case 5:
1218                 swizzle_pipe[0] = 0;
1219                 swizzle_pipe[1] = 2;
1220                 swizzle_pipe[2] = 4;
1221                 swizzle_pipe[3] = 1;
1222                 swizzle_pipe[4] = 3;
1223                 break;
1224         case 6:
1225                 swizzle_pipe[0] = 0;
1226                 swizzle_pipe[1] = 2;
1227                 swizzle_pipe[2] = 4;
1228                 swizzle_pipe[3] = 5;
1229                 swizzle_pipe[4] = 3;
1230                 swizzle_pipe[5] = 1;
1231                 break;
1232         case 7:
1233                 swizzle_pipe[0] = 0;
1234                 swizzle_pipe[1] = 2;
1235                 swizzle_pipe[2] = 4;
1236                 swizzle_pipe[3] = 6;
1237                 swizzle_pipe[4] = 3;
1238                 swizzle_pipe[5] = 1;
1239                 swizzle_pipe[6] = 5;
1240                 break;
1241         case 8:
1242                 swizzle_pipe[0] = 0;
1243                 swizzle_pipe[1] = 2;
1244                 swizzle_pipe[2] = 4;
1245                 swizzle_pipe[3] = 6;
1246                 swizzle_pipe[4] = 3;
1247                 swizzle_pipe[5] = 1;
1248                 swizzle_pipe[6] = 7;
1249                 swizzle_pipe[7] = 5;
1250                 break;
1251         }
1252
1253         cur_backend = 0;
1254         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1255                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1256                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1257
1258                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1259
1260                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1261         }
1262
1263         return backend_map;
1264 }
1265
1266 static void r700_gfx_init(struct drm_device *dev,
1267                           drm_radeon_private_t *dev_priv)
1268 {
1269         int i, j, num_qd_pipes;
1270         u32 sx_debug_1;
1271         u32 smx_dc_ctl0;
1272         u32 num_gs_verts_per_thread;
1273         u32 vgt_gs_per_es;
1274         u32 gs_prim_buffer_depth = 0;
1275         u32 sq_ms_fifo_sizes;
1276         u32 sq_config;
1277         u32 sq_thread_resource_mgmt;
1278         u32 hdp_host_path_cntl;
1279         u32 sq_dyn_gpr_size_simd_ab_0;
1280         u32 backend_map;
1281         u32 gb_tiling_config = 0;
1282         u32 cc_rb_backend_disable = 0;
1283         u32 cc_gc_shader_pipe_config = 0;
1284         u32 mc_arb_ramcfg;
1285         u32 db_debug4;
1286
1287         /* setup chip specs */
1288         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1289         case CHIP_RV770:
1290                 dev_priv->r600_max_pipes = 4;
1291                 dev_priv->r600_max_tile_pipes = 8;
1292                 dev_priv->r600_max_simds = 10;
1293                 dev_priv->r600_max_backends = 4;
1294                 dev_priv->r600_max_gprs = 256;
1295                 dev_priv->r600_max_threads = 248;
1296                 dev_priv->r600_max_stack_entries = 512;
1297                 dev_priv->r600_max_hw_contexts = 8;
1298                 dev_priv->r600_max_gs_threads = 16 * 2;
1299                 dev_priv->r600_sx_max_export_size = 128;
1300                 dev_priv->r600_sx_max_export_pos_size = 16;
1301                 dev_priv->r600_sx_max_export_smx_size = 112;
1302                 dev_priv->r600_sq_num_cf_insts = 2;
1303
1304                 dev_priv->r700_sx_num_of_sets = 7;
1305                 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1306                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1307                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1308                 break;
1309         case CHIP_RV730:
1310                 dev_priv->r600_max_pipes = 2;
1311                 dev_priv->r600_max_tile_pipes = 4;
1312                 dev_priv->r600_max_simds = 8;
1313                 dev_priv->r600_max_backends = 2;
1314                 dev_priv->r600_max_gprs = 128;
1315                 dev_priv->r600_max_threads = 248;
1316                 dev_priv->r600_max_stack_entries = 256;
1317                 dev_priv->r600_max_hw_contexts = 8;
1318                 dev_priv->r600_max_gs_threads = 16 * 2;
1319                 dev_priv->r600_sx_max_export_size = 256;
1320                 dev_priv->r600_sx_max_export_pos_size = 32;
1321                 dev_priv->r600_sx_max_export_smx_size = 224;
1322                 dev_priv->r600_sq_num_cf_insts = 2;
1323
1324                 dev_priv->r700_sx_num_of_sets = 7;
1325                 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1326                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1327                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1328                 break;
1329         case CHIP_RV710:
1330                 dev_priv->r600_max_pipes = 2;
1331                 dev_priv->r600_max_tile_pipes = 2;
1332                 dev_priv->r600_max_simds = 2;
1333                 dev_priv->r600_max_backends = 1;
1334                 dev_priv->r600_max_gprs = 256;
1335                 dev_priv->r600_max_threads = 192;
1336                 dev_priv->r600_max_stack_entries = 256;
1337                 dev_priv->r600_max_hw_contexts = 4;
1338                 dev_priv->r600_max_gs_threads = 8 * 2;
1339                 dev_priv->r600_sx_max_export_size = 128;
1340                 dev_priv->r600_sx_max_export_pos_size = 16;
1341                 dev_priv->r600_sx_max_export_smx_size = 112;
1342                 dev_priv->r600_sq_num_cf_insts = 1;
1343
1344                 dev_priv->r700_sx_num_of_sets = 7;
1345                 dev_priv->r700_sc_prim_fifo_size = 0x40;
1346                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1347                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1348                 break;
1349         default:
1350                 break;
1351         }
1352
1353         /* Initialize HDP */
1354         j = 0;
1355         for (i = 0; i < 32; i++) {
1356                 RADEON_WRITE((0x2c14 + j), 0x00000000);
1357                 RADEON_WRITE((0x2c18 + j), 0x00000000);
1358                 RADEON_WRITE((0x2c1c + j), 0x00000000);
1359                 RADEON_WRITE((0x2c20 + j), 0x00000000);
1360                 RADEON_WRITE((0x2c24 + j), 0x00000000);
1361                 j += 0x18;
1362         }
1363
1364         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1365
1366         /* setup tiling, simd, pipe config */
1367         mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1368
1369         switch (dev_priv->r600_max_tile_pipes) {
1370         case 1:
1371                 gb_tiling_config |= R600_PIPE_TILING(0);
1372                 break;
1373         case 2:
1374                 gb_tiling_config |= R600_PIPE_TILING(1);
1375                 break;
1376         case 4:
1377                 gb_tiling_config |= R600_PIPE_TILING(2);
1378                 break;
1379         case 8:
1380                 gb_tiling_config |= R600_PIPE_TILING(3);
1381                 break;
1382         default:
1383                 break;
1384         }
1385
1386         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1387                 gb_tiling_config |= R600_BANK_TILING(1);
1388         else
1389                 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1390
1391         gb_tiling_config |= R600_GROUP_SIZE(0);
1392
1393         if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1394                 gb_tiling_config |= R600_ROW_TILING(3);
1395                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1396         } else {
1397                 gb_tiling_config |=
1398                         R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1399                 gb_tiling_config |=
1400                         R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1401         }
1402
1403         gb_tiling_config |= R600_BANK_SWAPS(1);
1404
1405         backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1406                                                         dev_priv->r600_max_backends,
1407                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
1408         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1409
1410         cc_gc_shader_pipe_config =
1411                 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1412         cc_gc_shader_pipe_config |=
1413                 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1414
1415         cc_rb_backend_disable =
1416                 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1417
1418         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
1419         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1420         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1421
1422         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
1423         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
1424         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1425
1426         RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1427         RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1428         RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1429         RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1430         RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1431
1432         num_qd_pipes =
1433                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1434         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1435         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1436
1437         /* set HW defaults for 3D engine */
1438         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1439                                                 R600_ROQ_IB2_START(0x2b)));
1440
1441         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1442
1443         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1444                                         R600_SYNC_GRADIENT |
1445                                         R600_SYNC_WALKER |
1446                                         R600_SYNC_ALIGNER));
1447
1448         sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1449         sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1450         RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1451
1452         smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1453         smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1454         smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1455         RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1456
1457         RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1458                                           R700_GS_FLUSH_CTL(4) |
1459                                           R700_ACK_FLUSH_CTL(3) |
1460                                           R700_SYNC_FLUSH_CTL));
1461
1462         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1463                 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1464         else {
1465                 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1466                 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1467                 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1468         }
1469
1470         RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1471                                                    R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1472                                                    R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1473
1474         RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1475                                                  R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1476                                                  R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1477
1478         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1479
1480         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1481
1482         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1483
1484         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1485
1486         RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1487
1488         sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1489                             R600_DONE_FIFO_HIWATER(0xe0) |
1490                             R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1491         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1492         case CHIP_RV770:
1493                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1494                 break;
1495         case CHIP_RV730:
1496         case CHIP_RV710:
1497         default:
1498                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1499                 break;
1500         }
1501         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1502
1503         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1504          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1505          */
1506         sq_config = RADEON_READ(R600_SQ_CONFIG);
1507         sq_config &= ~(R600_PS_PRIO(3) |
1508                        R600_VS_PRIO(3) |
1509                        R600_GS_PRIO(3) |
1510                        R600_ES_PRIO(3));
1511         sq_config |= (R600_DX9_CONSTS |
1512                       R600_VC_ENABLE |
1513                       R600_EXPORT_SRC_C |
1514                       R600_PS_PRIO(0) |
1515                       R600_VS_PRIO(1) |
1516                       R600_GS_PRIO(2) |
1517                       R600_ES_PRIO(3));
1518         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1519                 /* no vertex cache */
1520                 sq_config &= ~R600_VC_ENABLE;
1521
1522         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1523
1524         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1525                                                     R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1526                                                     R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1527
1528         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1529                                                     R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1530
1531         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1532                                    R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1533                                    R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1534         if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1535                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1536         else
1537                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1538         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1539
1540         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1541                                                      R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1542
1543         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1544                                                      R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1545
1546         sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1547                                      R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1548                                      R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1549                                      R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1550
1551         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1552         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1553         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1554         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1555         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1556         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1557         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1558         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1559
1560         RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1561                                                      R700_FORCE_EOV_MAX_REZ_CNT(255)));
1562
1563         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1564                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1565                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1566         else
1567                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1568                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1569
1570         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1571         case CHIP_RV770:
1572         case CHIP_RV730:
1573                 gs_prim_buffer_depth = 384;
1574                 break;
1575         case CHIP_RV710:
1576                 gs_prim_buffer_depth = 128;
1577                 break;
1578         default:
1579                 break;
1580         }
1581
1582         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1583         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1584         /* Max value for this is 256 */
1585         if (vgt_gs_per_es > 256)
1586                 vgt_gs_per_es = 256;
1587
1588         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1589         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1590         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1591
1592         /* more default values. 2D/3D driver should adjust as needed */
1593         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1594         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1595         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1596         RADEON_WRITE(R600_SX_MISC, 0);
1597         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1598         RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1599         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1600         RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1601         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1602         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1603         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1604         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1605
1606         /* clear render buffer base addresses */
1607         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1608         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1609         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1610         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1611         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1612         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1613         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1614         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1615
1616         RADEON_WRITE(R700_TCP_CNTL, 0);
1617
1618         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1619         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1620
1621         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1622
1623         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1624                                           R600_NUM_CLIP_SEQ(3)));
1625
1626 }
1627
1628 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1629                                        drm_radeon_private_t *dev_priv,
1630                                        struct drm_file *file_priv)
1631 {
1632         u32 ring_start;
1633         u64 rptr_addr;
1634
1635         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1636                 r700_gfx_init(dev, dev_priv);
1637         else
1638                 r600_gfx_init(dev, dev_priv);
1639
1640         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1641         RADEON_READ(R600_GRBM_SOFT_RESET);
1642         DRM_UDELAY(15000);
1643         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1644
1645
1646         /* Set ring buffer size */
1647 #ifdef __BIG_ENDIAN
1648         RADEON_WRITE(R600_CP_RB_CNTL,
1649                      RADEON_BUF_SWAP_32BIT |
1650                      RADEON_RB_NO_UPDATE |
1651                      (dev_priv->ring.rptr_update_l2qw << 8) |
1652                      dev_priv->ring.size_l2qw);
1653 #else
1654         RADEON_WRITE(R600_CP_RB_CNTL,
1655                      RADEON_RB_NO_UPDATE |
1656                      (dev_priv->ring.rptr_update_l2qw << 8) |
1657                      dev_priv->ring.size_l2qw);
1658 #endif
1659
1660         RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1661
1662         /* Set the write pointer delay */
1663         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1664
1665 #ifdef __BIG_ENDIAN
1666         RADEON_WRITE(R600_CP_RB_CNTL,
1667                      RADEON_BUF_SWAP_32BIT |
1668                      RADEON_RB_NO_UPDATE |
1669                      RADEON_RB_RPTR_WR_ENA |
1670                      (dev_priv->ring.rptr_update_l2qw << 8) |
1671                      dev_priv->ring.size_l2qw);
1672 #else
1673         RADEON_WRITE(R600_CP_RB_CNTL,
1674                      RADEON_RB_NO_UPDATE |
1675                      RADEON_RB_RPTR_WR_ENA |
1676                      (dev_priv->ring.rptr_update_l2qw << 8) |
1677                      dev_priv->ring.size_l2qw);
1678 #endif
1679
1680         /* Initialize the ring buffer's read and write pointers */
1681         RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1682         RADEON_WRITE(R600_CP_RB_WPTR, 0);
1683         SET_RING_HEAD(dev_priv, 0);
1684         dev_priv->ring.tail = 0;
1685
1686 #if __OS_HAS_AGP
1687         if (dev_priv->flags & RADEON_IS_AGP) {
1688                 rptr_addr = dev_priv->ring_rptr->offset
1689                         - dev->agp->base +
1690                         dev_priv->gart_vm_start;
1691         } else
1692 #endif
1693         {
1694                 rptr_addr = dev_priv->ring_rptr->offset
1695                         - ((unsigned long) dev->sg->virtual)
1696                         + dev_priv->gart_vm_start;
1697         }
1698         RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1699                      rptr_addr & 0xffffffff);
1700         RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1701                      upper_32_bits(rptr_addr));
1702
1703 #ifdef __BIG_ENDIAN
1704         RADEON_WRITE(R600_CP_RB_CNTL,
1705                      RADEON_BUF_SWAP_32BIT |
1706                      (dev_priv->ring.rptr_update_l2qw << 8) |
1707                      dev_priv->ring.size_l2qw);
1708 #else
1709         RADEON_WRITE(R600_CP_RB_CNTL,
1710                      (dev_priv->ring.rptr_update_l2qw << 8) |
1711                      dev_priv->ring.size_l2qw);
1712 #endif
1713
1714 #if __OS_HAS_AGP
1715         if (dev_priv->flags & RADEON_IS_AGP) {
1716                 /* XXX */
1717                 radeon_write_agp_base(dev_priv, dev->agp->base);
1718
1719                 /* XXX */
1720                 radeon_write_agp_location(dev_priv,
1721                              (((dev_priv->gart_vm_start - 1 +
1722                                 dev_priv->gart_size) & 0xffff0000) |
1723                               (dev_priv->gart_vm_start >> 16)));
1724
1725                 ring_start = (dev_priv->cp_ring->offset
1726                               - dev->agp->base
1727                               + dev_priv->gart_vm_start);
1728         } else
1729 #endif
1730                 ring_start = (dev_priv->cp_ring->offset
1731                               - (unsigned long)dev->sg->virtual
1732                               + dev_priv->gart_vm_start);
1733
1734         RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1735
1736         RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1737
1738         RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1739
1740         /* Initialize the scratch register pointer.  This will cause
1741          * the scratch register values to be written out to memory
1742          * whenever they are updated.
1743          *
1744          * We simply put this behind the ring read pointer, this works
1745          * with PCI GART as well as (whatever kind of) AGP GART
1746          */
1747         {
1748                 u64 scratch_addr;
1749
1750                 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1751                 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1752                 scratch_addr += R600_SCRATCH_REG_OFFSET;
1753                 scratch_addr >>= 8;
1754                 scratch_addr &= 0xffffffff;
1755
1756                 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1757         }
1758
1759         RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1760
1761         /* Turn on bus mastering */
1762         radeon_enable_bm(dev_priv);
1763
1764         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1765         RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1766
1767         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1768         RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1769
1770         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1771         RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1772
1773         /* reset sarea copies of these */
1774         if (dev_priv->sarea_priv) {
1775                 dev_priv->sarea_priv->last_frame = 0;
1776                 dev_priv->sarea_priv->last_dispatch = 0;
1777                 dev_priv->sarea_priv->last_clear = 0;
1778         }
1779
1780         r600_do_wait_for_idle(dev_priv);
1781
1782 }
1783
1784 int r600_do_cleanup_cp(struct drm_device *dev)
1785 {
1786         drm_radeon_private_t *dev_priv = dev->dev_private;
1787         DRM_DEBUG("\n");
1788
1789         /* Make sure interrupts are disabled here because the uninstall ioctl
1790          * may not have been called from userspace and after dev_private
1791          * is freed, it's too late.
1792          */
1793         if (dev->irq_enabled)
1794                 drm_irq_uninstall(dev);
1795
1796 #if __OS_HAS_AGP
1797         if (dev_priv->flags & RADEON_IS_AGP) {
1798                 if (dev_priv->cp_ring != NULL) {
1799                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1800                         dev_priv->cp_ring = NULL;
1801                 }
1802                 if (dev_priv->ring_rptr != NULL) {
1803                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1804                         dev_priv->ring_rptr = NULL;
1805                 }
1806                 if (dev->agp_buffer_map != NULL) {
1807                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1808                         dev->agp_buffer_map = NULL;
1809                 }
1810         } else
1811 #endif
1812         {
1813
1814                 if (dev_priv->gart_info.bus_addr)
1815                         r600_page_table_cleanup(dev, &dev_priv->gart_info);
1816
1817                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1818                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1819                         dev_priv->gart_info.addr = 0;
1820                 }
1821         }
1822         /* only clear to the start of flags */
1823         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1824
1825         return 0;
1826 }
1827
1828 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1829                     struct drm_file *file_priv)
1830 {
1831         drm_radeon_private_t *dev_priv = dev->dev_private;
1832
1833         DRM_DEBUG("\n");
1834
1835         /* if we require new memory map but we don't have it fail */
1836         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1837                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1838                 r600_do_cleanup_cp(dev);
1839                 return -EINVAL;
1840         }
1841
1842         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1843                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1844                 dev_priv->flags &= ~RADEON_IS_AGP;
1845                 /* The writeback test succeeds, but when writeback is enabled,
1846                  * the ring buffer read ptr update fails after first 128 bytes.
1847                  */
1848                 radeon_no_wb = 1;
1849         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1850                  && !init->is_pci) {
1851                 DRM_DEBUG("Restoring AGP flag\n");
1852                 dev_priv->flags |= RADEON_IS_AGP;
1853         }
1854
1855         dev_priv->usec_timeout = init->usec_timeout;
1856         if (dev_priv->usec_timeout < 1 ||
1857             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1858                 DRM_DEBUG("TIMEOUT problem!\n");
1859                 r600_do_cleanup_cp(dev);
1860                 return -EINVAL;
1861         }
1862
1863         /* Enable vblank on CRTC1 for older X servers
1864          */
1865         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1866
1867         dev_priv->cp_mode = init->cp_mode;
1868
1869         /* We don't support anything other than bus-mastering ring mode,
1870          * but the ring can be in either AGP or PCI space for the ring
1871          * read pointer.
1872          */
1873         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1874             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1875                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1876                 r600_do_cleanup_cp(dev);
1877                 return -EINVAL;
1878         }
1879
1880         switch (init->fb_bpp) {
1881         case 16:
1882                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1883                 break;
1884         case 32:
1885         default:
1886                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1887                 break;
1888         }
1889         dev_priv->front_offset = init->front_offset;
1890         dev_priv->front_pitch = init->front_pitch;
1891         dev_priv->back_offset = init->back_offset;
1892         dev_priv->back_pitch = init->back_pitch;
1893
1894         dev_priv->ring_offset = init->ring_offset;
1895         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1896         dev_priv->buffers_offset = init->buffers_offset;
1897         dev_priv->gart_textures_offset = init->gart_textures_offset;
1898
1899         dev_priv->sarea = drm_getsarea(dev);
1900         if (!dev_priv->sarea) {
1901                 DRM_ERROR("could not find sarea!\n");
1902                 r600_do_cleanup_cp(dev);
1903                 return -EINVAL;
1904         }
1905
1906         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1907         if (!dev_priv->cp_ring) {
1908                 DRM_ERROR("could not find cp ring region!\n");
1909                 r600_do_cleanup_cp(dev);
1910                 return -EINVAL;
1911         }
1912         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1913         if (!dev_priv->ring_rptr) {
1914                 DRM_ERROR("could not find ring read pointer!\n");
1915                 r600_do_cleanup_cp(dev);
1916                 return -EINVAL;
1917         }
1918         dev->agp_buffer_token = init->buffers_offset;
1919         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1920         if (!dev->agp_buffer_map) {
1921                 DRM_ERROR("could not find dma buffer region!\n");
1922                 r600_do_cleanup_cp(dev);
1923                 return -EINVAL;
1924         }
1925
1926         if (init->gart_textures_offset) {
1927                 dev_priv->gart_textures =
1928                     drm_core_findmap(dev, init->gart_textures_offset);
1929                 if (!dev_priv->gart_textures) {
1930                         DRM_ERROR("could not find GART texture region!\n");
1931                         r600_do_cleanup_cp(dev);
1932                         return -EINVAL;
1933                 }
1934         }
1935
1936         dev_priv->sarea_priv =
1937             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1938                                     init->sarea_priv_offset);
1939
1940 #if __OS_HAS_AGP
1941         /* XXX */
1942         if (dev_priv->flags & RADEON_IS_AGP) {
1943                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1944                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1945                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1946                 if (!dev_priv->cp_ring->handle ||
1947                     !dev_priv->ring_rptr->handle ||
1948                     !dev->agp_buffer_map->handle) {
1949                         DRM_ERROR("could not find ioremap agp regions!\n");
1950                         r600_do_cleanup_cp(dev);
1951                         return -EINVAL;
1952                 }
1953         } else
1954 #endif
1955         {
1956                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1957                 dev_priv->ring_rptr->handle =
1958                     (void *)dev_priv->ring_rptr->offset;
1959                 dev->agp_buffer_map->handle =
1960                     (void *)dev->agp_buffer_map->offset;
1961
1962                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1963                           dev_priv->cp_ring->handle);
1964                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1965                           dev_priv->ring_rptr->handle);
1966                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1967                           dev->agp_buffer_map->handle);
1968         }
1969
1970         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1971         dev_priv->fb_size =
1972                 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1973                 - dev_priv->fb_location;
1974
1975         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1976                                         ((dev_priv->front_offset
1977                                           + dev_priv->fb_location) >> 10));
1978
1979         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1980                                        ((dev_priv->back_offset
1981                                          + dev_priv->fb_location) >> 10));
1982
1983         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1984                                         ((dev_priv->depth_offset
1985                                           + dev_priv->fb_location) >> 10));
1986
1987         dev_priv->gart_size = init->gart_size;
1988
1989         /* New let's set the memory map ... */
1990         if (dev_priv->new_memmap) {
1991                 u32 base = 0;
1992
1993                 DRM_INFO("Setting GART location based on new memory map\n");
1994
1995                 /* If using AGP, try to locate the AGP aperture at the same
1996                  * location in the card and on the bus, though we have to
1997                  * align it down.
1998                  */
1999 #if __OS_HAS_AGP
2000                 /* XXX */
2001                 if (dev_priv->flags & RADEON_IS_AGP) {
2002                         base = dev->agp->base;
2003                         /* Check if valid */
2004                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2005                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2006                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2007                                          dev->agp->base);
2008                                 base = 0;
2009                         }
2010                 }
2011 #endif
2012                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2013                 if (base == 0) {
2014                         base = dev_priv->fb_location + dev_priv->fb_size;
2015                         if (base < dev_priv->fb_location ||
2016                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2017                                 base = dev_priv->fb_location
2018                                         - dev_priv->gart_size;
2019                 }
2020                 dev_priv->gart_vm_start = base & 0xffc00000u;
2021                 if (dev_priv->gart_vm_start != base)
2022                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2023                                  base, dev_priv->gart_vm_start);
2024         }
2025
2026 #if __OS_HAS_AGP
2027         /* XXX */
2028         if (dev_priv->flags & RADEON_IS_AGP)
2029                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2030                                                  - dev->agp->base
2031                                                  + dev_priv->gart_vm_start);
2032         else
2033 #endif
2034                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2035                                                  - (unsigned long)dev->sg->virtual
2036                                                  + dev_priv->gart_vm_start);
2037
2038         DRM_DEBUG("fb 0x%08x size %d\n",
2039                   (unsigned int) dev_priv->fb_location,
2040                   (unsigned int) dev_priv->fb_size);
2041         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2042         DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2043                   (unsigned int) dev_priv->gart_vm_start);
2044         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2045                   dev_priv->gart_buffers_offset);
2046
2047         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2048         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2049                               + init->ring_size / sizeof(u32));
2050         dev_priv->ring.size = init->ring_size;
2051         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2052
2053         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2054         dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2055
2056         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2057         dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2058
2059         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2060
2061         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2062
2063 #if __OS_HAS_AGP
2064         if (dev_priv->flags & RADEON_IS_AGP) {
2065                 /* XXX turn off pcie gart */
2066         } else
2067 #endif
2068         {
2069                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2070                 /* if we have an offset set from userspace */
2071                 if (!dev_priv->pcigart_offset_set) {
2072                         DRM_ERROR("Need gart offset from userspace\n");
2073                         r600_do_cleanup_cp(dev);
2074                         return -EINVAL;
2075                 }
2076
2077                 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2078
2079                 dev_priv->gart_info.bus_addr =
2080                         dev_priv->pcigart_offset + dev_priv->fb_location;
2081                 dev_priv->gart_info.mapping.offset =
2082                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2083                 dev_priv->gart_info.mapping.size =
2084                         dev_priv->gart_info.table_size;
2085
2086                 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2087                 if (!dev_priv->gart_info.mapping.handle) {
2088                         DRM_ERROR("ioremap failed.\n");
2089                         r600_do_cleanup_cp(dev);
2090                         return -EINVAL;
2091                 }
2092
2093                 dev_priv->gart_info.addr =
2094                         dev_priv->gart_info.mapping.handle;
2095
2096                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2097                           dev_priv->gart_info.addr,
2098                           dev_priv->pcigart_offset);
2099
2100                 if (!r600_page_table_init(dev)) {
2101                         DRM_ERROR("Failed to init GART table\n");
2102                         r600_do_cleanup_cp(dev);
2103                         return -EINVAL;
2104                 }
2105
2106                 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2107                         r700_vm_init(dev);
2108                 else
2109                         r600_vm_init(dev);
2110         }
2111
2112         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2113                 r700_cp_load_microcode(dev_priv);
2114         else
2115                 r600_cp_load_microcode(dev_priv);
2116
2117         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2118
2119         dev_priv->last_buf = 0;
2120
2121         r600_do_engine_reset(dev);
2122         r600_test_writeback(dev_priv);
2123
2124         return 0;
2125 }
2126
2127 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2128 {
2129         drm_radeon_private_t *dev_priv = dev->dev_private;
2130
2131         DRM_DEBUG("\n");
2132         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2133                 r700_vm_init(dev);
2134                 r700_cp_load_microcode(dev_priv);
2135         } else {
2136                 r600_vm_init(dev);
2137                 r600_cp_load_microcode(dev_priv);
2138         }
2139         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2140         r600_do_engine_reset(dev);
2141
2142         return 0;
2143 }
2144
2145 /* Wait for the CP to go idle.
2146  */
2147 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2148 {
2149         RING_LOCALS;
2150         DRM_DEBUG("\n");
2151
2152         BEGIN_RING(5);
2153         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2154         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2155         /* wait for 3D idle clean */
2156         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2157         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2158         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2159
2160         ADVANCE_RING();
2161         COMMIT_RING();
2162
2163         return r600_do_wait_for_idle(dev_priv);
2164 }
2165
2166 /* Start the Command Processor.
2167  */
2168 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2169 {
2170         u32 cp_me;
2171         RING_LOCALS;
2172         DRM_DEBUG("\n");
2173
2174         BEGIN_RING(7);
2175         OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2176         OUT_RING(0x00000001);
2177         if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2178                 OUT_RING(0x00000003);
2179         else
2180                 OUT_RING(0x00000000);
2181         OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2182         OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2183         OUT_RING(0x00000000);
2184         OUT_RING(0x00000000);
2185         ADVANCE_RING();
2186         COMMIT_RING();
2187
2188         /* set the mux and reset the halt bit */
2189         cp_me = 0xff;
2190         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2191
2192         dev_priv->cp_running = 1;
2193
2194 }
2195
2196 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2197 {
2198         u32 cur_read_ptr;
2199         DRM_DEBUG("\n");
2200
2201         cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2202         RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2203         SET_RING_HEAD(dev_priv, cur_read_ptr);
2204         dev_priv->ring.tail = cur_read_ptr;
2205 }
2206
2207 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2208 {
2209         uint32_t cp_me;
2210
2211         DRM_DEBUG("\n");
2212
2213         cp_me = 0xff | R600_CP_ME_HALT;
2214
2215         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2216
2217         dev_priv->cp_running = 0;
2218 }
2219
2220 int r600_cp_dispatch_indirect(struct drm_device *dev,
2221                               struct drm_buf *buf, int start, int end)
2222 {
2223         drm_radeon_private_t *dev_priv = dev->dev_private;
2224         RING_LOCALS;
2225
2226         if (start != end) {
2227                 unsigned long offset = (dev_priv->gart_buffers_offset
2228                                         + buf->offset + start);
2229                 int dwords = (end - start + 3) / sizeof(u32);
2230
2231                 DRM_DEBUG("dwords:%d\n", dwords);
2232                 DRM_DEBUG("offset 0x%lx\n", offset);
2233
2234
2235                 /* Indirect buffer data must be a multiple of 16 dwords.
2236                  * pad the data with a Type-2 CP packet.
2237                  */
2238                 while (dwords & 0xf) {
2239                         u32 *data = (u32 *)
2240                             ((char *)dev->agp_buffer_map->handle
2241                              + buf->offset + start);
2242                         data[dwords++] = RADEON_CP_PACKET2;
2243                 }
2244
2245                 /* Fire off the indirect buffer */
2246                 BEGIN_RING(4);
2247                 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2248                 OUT_RING((offset & 0xfffffffc));
2249                 OUT_RING((upper_32_bits(offset) & 0xff));
2250                 OUT_RING(dwords);
2251                 ADVANCE_RING();
2252         }
2253
2254         return 0;
2255 }