2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
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15 * may be used to endorse or promote products derived from this software
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18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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30 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
31 * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.39 2007/05/31 11:26:44 des Exp $
32 * $DragonFly: src/sys/cpu/amd64/include/specialreg.h,v 1.2 2008/08/29 17:07:06 dillon Exp $
35 #ifndef _CPU_SPECIALREG_H_
36 #define _CPU_SPECIALREG_H_
39 * Bits in 386 special registers:
41 #define CR0_PE 0x00000001 /* Protected mode Enable */
42 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
43 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
44 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
45 #define CR0_PG 0x80000000 /* PaGing enable */
48 * Bits in 486 special registers:
50 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
51 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
53 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
54 #define CR0_NW 0x20000000 /* Not Write-through */
55 #define CR0_CD 0x40000000 /* Cache Disable */
58 * Bits in PPro special registers
60 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
61 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
62 #define CR4_TSD 0x00000004 /* Time stamp disable */
63 #define CR4_DE 0x00000008 /* Debugging extensions */
64 #define CR4_PSE 0x00000010 /* Page size extensions */
65 #define CR4_PAE 0x00000020 /* Physical address extension */
66 #define CR4_MCE 0x00000040 /* Machine check enable */
67 #define CR4_PGE 0x00000080 /* Page global enable */
68 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
69 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
70 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
73 * Bits in AMD64 special registers. EFER is 64 bits wide.
75 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
76 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
77 #define EFER_LMA 0x000000400 /* Long mode active (R) */
78 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
81 * CPUID instruction features register
83 #define CPUID_FPU 0x00000001
84 #define CPUID_VME 0x00000002
85 #define CPUID_DE 0x00000004
86 #define CPUID_PSE 0x00000008
87 #define CPUID_TSC 0x00000010
88 #define CPUID_MSR 0x00000020
89 #define CPUID_PAE 0x00000040
90 #define CPUID_MCE 0x00000080
91 #define CPUID_CX8 0x00000100
92 #define CPUID_APIC 0x00000200
93 #define CPUID_B10 0x00000400
94 #define CPUID_SEP 0x00000800
95 #define CPUID_MTRR 0x00001000
96 #define CPUID_PGE 0x00002000
97 #define CPUID_MCA 0x00004000
98 #define CPUID_CMOV 0x00008000
99 #define CPUID_PAT 0x00010000
100 #define CPUID_PSE36 0x00020000
101 #define CPUID_PSN 0x00040000
102 #define CPUID_CLFSH 0x00080000
103 #define CPUID_B20 0x00100000
104 #define CPUID_DS 0x00200000
105 #define CPUID_ACPI 0x00400000
106 #define CPUID_MMX 0x00800000
107 #define CPUID_FXSR 0x01000000
108 #define CPUID_SSE 0x02000000
109 #define CPUID_XMM 0x02000000
110 #define CPUID_SSE2 0x04000000
111 #define CPUID_SS 0x08000000
112 #define CPUID_HTT 0x10000000
113 #define CPUID_TM 0x20000000
114 #define CPUID_IA64 0x40000000
115 #define CPUID_PBE 0x80000000
117 #define CPUID2_SSE3 0x00000001
118 #define CPUID2_MON 0x00000008
119 #define CPUID2_DS_CPL 0x00000010
120 #define CPUID2_VMX 0x00000020
121 #define CPUID2_SMX 0x00000040
122 #define CPUID2_EST 0x00000080
123 #define CPUID2_TM2 0x00000100
124 #define CPUID2_SSSE3 0x00000200
125 #define CPUID2_CNXTID 0x00000400
126 #define CPUID2_CX16 0x00002000
127 #define CPUID2_XTPR 0x00004000
128 #define CPUID2_PDCM 0x00008000
129 #define CPUID2_DCA 0x00040000
132 * Important bits in the AMD extended cpuid flags
134 #define AMDID_SYSCALL 0x00000800
135 #define AMDID_MP 0x00080000
136 #define AMDID_NX 0x00100000
137 #define AMDID_EXT_MMX 0x00400000
138 #define AMDID_FFXSR 0x01000000
139 #define AMDID_PAGE1GB 0x04000000
140 #define AMDID_RDTSCP 0x08000000
141 #define AMDID_LM 0x20000000
142 #define AMDID_EXT_3DNOW 0x40000000
143 #define AMDID_3DNOW 0x80000000
145 #define AMDID2_LAHF 0x00000001
146 #define AMDID2_CMP 0x00000002
147 #define AMDID2_SVM 0x00000004
148 #define AMDID2_EXT_APIC 0x00000008
149 #define AMDID2_CR8 0x00000010
150 #define AMDID2_PREFETCH 0x00000100
153 * CPUID instruction 1 ebx info
155 #define CPUID_BRAND_INDEX 0x000000ff
156 #define CPUID_CLFUSH_SIZE 0x0000ff00
157 #define CPUID_HTT_CORES 0x00ff0000
158 #define CPUID_LOCAL_APIC_ID 0xff000000
161 * AMD extended function 8000_0008h ecx info
163 #define AMDID_CMP_CORES 0x000000ff
166 * Model-specific registers for the i386 family
168 #define MSR_P5_MC_ADDR 0x000
169 #define MSR_P5_MC_TYPE 0x001
170 #define MSR_TSC 0x010
171 #define MSR_P5_CESR 0x011
172 #define MSR_P5_CTR0 0x012
173 #define MSR_P5_CTR1 0x013
174 #define MSR_IA32_PLATFORM_ID 0x017
175 #define MSR_APICBASE 0x01b
176 #define MSR_EBL_CR_POWERON 0x02a
177 #define MSR_TEST_CTL 0x033
178 #define MSR_BIOS_UPDT_TRIG 0x079
179 #define MSR_BBL_CR_D0 0x088
180 #define MSR_BBL_CR_D1 0x089
181 #define MSR_BBL_CR_D2 0x08a
182 #define MSR_BIOS_SIGN 0x08b
183 #define MSR_PERFCTR0 0x0c1
184 #define MSR_PERFCTR1 0x0c2
185 #define MSR_MTRRcap 0x0fe
186 #define MSR_BBL_CR_ADDR 0x116
187 #define MSR_BBL_CR_DECC 0x118
188 #define MSR_BBL_CR_CTL 0x119
189 #define MSR_BBL_CR_TRIG 0x11a
190 #define MSR_BBL_CR_BUSY 0x11b
191 #define MSR_BBL_CR_CTL3 0x11e
192 #define MSR_SYSENTER_CS_MSR 0x174
193 #define MSR_SYSENTER_ESP_MSR 0x175
194 #define MSR_SYSENTER_EIP_MSR 0x176
195 #define MSR_MCG_CAP 0x179
196 #define MSR_MCG_STATUS 0x17a
197 #define MSR_MCG_CTL 0x17b
198 #define MSR_EVNTSEL0 0x186
199 #define MSR_EVNTSEL1 0x187
200 #define MSR_THERM_CONTROL 0x19a
201 #define MSR_THERM_INTERRUPT 0x19b
202 #define MSR_THERM_STATUS 0x19c
203 #define MSR_IA32_MISC_ENABLE 0x1a0
204 #define MSR_DEBUGCTLMSR 0x1d9
205 #define MSR_LASTBRANCHFROMIP 0x1db
206 #define MSR_LASTBRANCHTOIP 0x1dc
207 #define MSR_LASTINTFROMIP 0x1dd
208 #define MSR_LASTINTTOIP 0x1de
209 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
210 #define MSR_MTRRVarBase 0x200
211 #define MSR_MTRR64kBase 0x250
212 #define MSR_MTRR16kBase 0x258
213 #define MSR_MTRR4kBase 0x268
214 #define MSR_PAT 0x277
215 #define MSR_MTRRdefType 0x2ff
216 #define MSR_MC0_CTL 0x400
217 #define MSR_MC0_STATUS 0x401
218 #define MSR_MC0_ADDR 0x402
219 #define MSR_MC0_MISC 0x403
220 #define MSR_MC1_CTL 0x404
221 #define MSR_MC1_STATUS 0x405
222 #define MSR_MC1_ADDR 0x406
223 #define MSR_MC1_MISC 0x407
224 #define MSR_MC2_CTL 0x408
225 #define MSR_MC2_STATUS 0x409
226 #define MSR_MC2_ADDR 0x40a
227 #define MSR_MC2_MISC 0x40b
228 #define MSR_MC3_CTL 0x40c
229 #define MSR_MC3_STATUS 0x40d
230 #define MSR_MC3_ADDR 0x40e
231 #define MSR_MC3_MISC 0x40f
232 #define MSR_MC4_CTL 0x410
233 #define MSR_MC4_STATUS 0x411
234 #define MSR_MC4_ADDR 0x412
235 #define MSR_MC4_MISC 0x413
238 * Constants related to MSR's.
240 #define APICBASE_RESERVED 0x000006ff
241 #define APICBASE_BSP 0x00000100
242 #define APICBASE_ENABLED 0x00000800
243 #define APICBASE_ADDRESS 0xfffff000
248 #define PAT_UNCACHEABLE 0x00
249 #define PAT_WRITE_COMBINING 0x01
250 #define PAT_WRITE_THROUGH 0x04
251 #define PAT_WRITE_PROTECTED 0x05
252 #define PAT_WRITE_BACK 0x06
253 #define PAT_UNCACHED 0x07
254 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i)))
255 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
258 * Constants related to MTRRs
260 #define MTRR_N64K 8 /* numbers of fixed-size entries */
264 /* Performance Control Register (5x86 only). */
266 #define PCR0_RSTK 0x01 /* Enables return stack */
267 #define PCR0_BTB 0x02 /* Enables branch target buffer */
268 #define PCR0_LOOP 0x04 /* Enables loop */
269 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
271 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
272 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
273 #define PCR0_LSSER 0x80 /* Disable reorder */
275 /* Device Identification Registers */
280 * The following four 3-byte registers control the non-cacheable regions.
281 * These registers must be written as three separate bytes.
283 * NCRx+0: A31-A24 of starting address
284 * NCRx+1: A23-A16 of starting address
285 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
287 * The non-cacheable region's starting address must be aligned to the
288 * size indicated by the NCR_SIZE_xx field.
295 #define NCR_SIZE_0K 0
296 #define NCR_SIZE_4K 1
297 #define NCR_SIZE_8K 2
298 #define NCR_SIZE_16K 3
299 #define NCR_SIZE_32K 4
300 #define NCR_SIZE_64K 5
301 #define NCR_SIZE_128K 6
302 #define NCR_SIZE_256K 7
303 #define NCR_SIZE_512K 8
304 #define NCR_SIZE_1M 9
305 #define NCR_SIZE_2M 10
306 #define NCR_SIZE_4M 11
307 #define NCR_SIZE_8M 12
308 #define NCR_SIZE_16M 13
309 #define NCR_SIZE_32M 14
310 #define NCR_SIZE_4G 15
313 * The address region registers are used to specify the location and
314 * size for the eight address regions.
316 * ARRx + 0: A31-A24 of start address
317 * ARRx + 1: A23-A16 of start address
318 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
329 #define ARR_SIZE_0K 0
330 #define ARR_SIZE_4K 1
331 #define ARR_SIZE_8K 2
332 #define ARR_SIZE_16K 3
333 #define ARR_SIZE_32K 4
334 #define ARR_SIZE_64K 5
335 #define ARR_SIZE_128K 6
336 #define ARR_SIZE_256K 7
337 #define ARR_SIZE_512K 8
338 #define ARR_SIZE_1M 9
339 #define ARR_SIZE_2M 10
340 #define ARR_SIZE_4M 11
341 #define ARR_SIZE_8M 12
342 #define ARR_SIZE_16M 13
343 #define ARR_SIZE_32M 14
344 #define ARR_SIZE_4G 15
347 * The region control registers specify the attributes associated with
348 * the ARRx addres regions.
359 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
360 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
361 #define RCR_WWO 0x02 /* Weak write ordering. */
362 #define RCR_WL 0x04 /* Weak locking. */
363 #define RCR_WG 0x08 /* Write gathering. */
364 #define RCR_WT 0x10 /* Write-through. */
365 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
367 /* AMD Write Allocate Top-Of-Memory and Control Register */
368 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
369 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
370 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
373 #define MSR_EFER 0xc0000080 /* extended features */
374 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
375 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
376 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
377 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
378 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
379 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
380 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
381 #define MSR_PERFEVSEL0 0xc0010000
382 #define MSR_PERFEVSEL1 0xc0010001
383 #define MSR_PERFEVSEL2 0xc0010002
384 #define MSR_PERFEVSEL3 0xc0010003
387 #define MSR_PERFCTR0 0xc0010004
388 #define MSR_PERFCTR1 0xc0010005
389 #define MSR_PERFCTR2 0xc0010006
390 #define MSR_PERFCTR3 0xc0010007
391 #define MSR_SYSCFG 0xc0010010
392 #define MSR_IORRBASE0 0xc0010016
393 #define MSR_IORRMASK0 0xc0010017
394 #define MSR_IORRBASE1 0xc0010018
395 #define MSR_IORRMASK1 0xc0010019
396 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
397 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
399 #endif /* !_CPU_SPECIALREG_H_ */