2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.39 2007/08/16 11:20:37 sephe Exp $
37 * Winbond fast ethernet PCI NIC driver
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The Winbond W89C840F chip is a bus master; in some ways it resembles
50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
51 * one major difference which is that while the registers do many of
52 * the same things as a tulip adapter, the offsets are different: where
53 * tulip registers are typically spaced 8 bytes apart, the Winbond
54 * registers are spaced 4 bytes apart. The receiver filter is also
55 * programmed differently.
57 * Like the tulip, the Winbond chip uses small descriptors containing
58 * a status word, a control word and 32-bit areas that can either be used
59 * to point to two external data blocks, or to point to a single block
60 * and another descriptor in a linked list. Descriptors can be grouped
61 * together in blocks to form fixed length rings or can be chained
62 * together in linked lists. A single packet may be spread out over
63 * several descriptors if necessary.
65 * For the receive ring, this driver uses a linked list of descriptors,
66 * each pointing to a single mbuf cluster buffer, which us large enough
67 * to hold an entire packet. The link list is looped back to created a
70 * For transmission, the driver creates a linked list of 'super descriptors'
71 * which each contain several individual descriptors linked toghether.
72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
73 * abuse as fragment pointers. This allows us to use a buffer managment
74 * scheme very similar to that used in the ThunderLAN and Etherlink XL
77 * Autonegotiation is performed using the external PHY via the MII bus.
78 * The sample boards I have all use a Davicom PHY.
80 * Note: the author of the Linux driver for the Winbond chip alludes
81 * to some sort of flaw in the chip's design that seems to mandate some
82 * drastic workaround which signigicantly impairs transmit performance.
83 * I have no idea what he's on about: transmit performance with all
84 * three of my test boards seems fine.
87 #include <sys/param.h>
88 #include <sys/systm.h>
89 #include <sys/sockio.h>
91 #include <sys/malloc.h>
92 #include <sys/kernel.h>
93 #include <sys/socket.h>
94 #include <sys/queue.h>
95 #include <sys/serialize.h>
98 #include <sys/thread2.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
109 #include <vm/vm.h> /* for vtophys */
110 #include <vm/pmap.h> /* for vtophys */
112 #include <bus/pci/pcidevs.h>
113 #include <bus/pci/pcireg.h>
114 #include <bus/pci/pcivar.h>
116 #include <dev/netif/mii_layer/mii.h>
117 #include <dev/netif/mii_layer/miivar.h>
119 /* "controller miibus0" required. See GENERIC if you get errors here. */
120 #include "miibus_if.h"
122 #define WB_USEIOSPACE
124 #include "if_wbreg.h"
127 * Various supported device vendors/types and their names.
129 static struct wb_type wb_devs[] = {
130 { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F,
131 "Winbond W89C840F 10/100BaseTX" },
132 { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX,
133 "Compex RL100-ATX 10/100baseTX" },
137 static int wb_probe(device_t);
138 static int wb_attach(device_t);
139 static int wb_detach(device_t);
141 static void wb_bfree(void *);
142 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
144 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
146 static void wb_rxeof(struct wb_softc *);
147 static void wb_rxeoc(struct wb_softc *);
148 static void wb_txeof(struct wb_softc *);
149 static void wb_txeoc(struct wb_softc *);
150 static void wb_intr(void *);
151 static void wb_tick(void *);
152 static void wb_start(struct ifnet *);
153 static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
154 static void wb_init(void *);
155 static void wb_stop(struct wb_softc *);
156 static void wb_watchdog(struct ifnet *);
157 static void wb_shutdown(device_t);
158 static int wb_ifmedia_upd(struct ifnet *);
159 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
161 static void wb_eeprom_putbyte(struct wb_softc *, int);
162 static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *);
163 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int);
164 static void wb_mii_sync(struct wb_softc *);
165 static void wb_mii_send(struct wb_softc *, uint32_t, int);
166 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
167 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
169 static void wb_setcfg(struct wb_softc *, uint32_t);
170 static void wb_setmulti(struct wb_softc *);
171 static void wb_reset(struct wb_softc *);
172 static void wb_fixmedia(struct wb_softc *);
173 static int wb_list_rx_init(struct wb_softc *);
174 static int wb_list_tx_init(struct wb_softc *);
176 static int wb_miibus_readreg(device_t, int, int);
177 static int wb_miibus_writereg(device_t, int, int, int);
178 static void wb_miibus_statchg(device_t);
181 #define WB_RES SYS_RES_IOPORT
182 #define WB_RID WB_PCI_LOIO
184 #define WB_RES SYS_RES_MEMORY
185 #define WB_RID WB_PCI_LOMEM
188 static device_method_t wb_methods[] = {
189 /* Device interface */
190 DEVMETHOD(device_probe, wb_probe),
191 DEVMETHOD(device_attach, wb_attach),
192 DEVMETHOD(device_detach, wb_detach),
193 DEVMETHOD(device_shutdown, wb_shutdown),
195 /* bus interface, for miibus */
196 DEVMETHOD(bus_print_child, bus_generic_print_child),
197 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
200 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
201 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
202 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
206 static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc));
207 static devclass_t wb_devclass;
209 DECLARE_DUMMY_MODULE(if_wb);
210 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
211 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
213 #define WB_SETBIT(sc, reg, x) \
214 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
216 #define WB_CLRBIT(sc, reg, x) \
217 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
220 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x))
223 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x))
226 * Send a read command and address to the EEPROM, check for ACK.
229 wb_eeprom_putbyte(struct wb_softc *sc, int addr)
233 d = addr | WB_EECMD_READ;
236 * Feed in each bit and stobe the clock.
238 for (i = 0x400; i; i >>= 1) {
240 SIO_SET(WB_SIO_EE_DATAIN);
242 SIO_CLR(WB_SIO_EE_DATAIN);
244 SIO_SET(WB_SIO_EE_CLK);
246 SIO_CLR(WB_SIO_EE_CLK);
252 * Read a word of data stored in the EEPROM at address 'addr.'
255 wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest)
260 /* Enter EEPROM access mode. */
261 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
264 * Send address of word we want to read.
266 wb_eeprom_putbyte(sc, addr);
268 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
271 * Start reading bits from EEPROM.
273 for (i = 0x8000; i; i >>= 1) {
274 SIO_SET(WB_SIO_EE_CLK);
276 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
278 SIO_CLR(WB_SIO_EE_CLK);
282 /* Turn off EEPROM access mode. */
283 CSR_WRITE_4(sc, WB_SIO, 0);
289 * Read a sequence of words from the EEPROM.
292 wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt)
295 uint16_t word = 0, *ptr;
297 for (i = 0; i < cnt; i++) {
298 wb_eeprom_getword(sc, off + i, &word);
299 ptr = (uint16_t *)(dest + (i * 2));
305 * Sync the PHYs by setting data bit and strobing the clock 32 times.
308 wb_mii_sync(struct wb_softc *sc)
312 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN);
314 for (i = 0; i < 32; i++) {
315 SIO_SET(WB_SIO_MII_CLK);
317 SIO_CLR(WB_SIO_MII_CLK);
323 * Clock a series of bits through the MII.
326 wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt)
330 SIO_CLR(WB_SIO_MII_CLK);
332 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
334 SIO_SET(WB_SIO_MII_DATAIN);
336 SIO_CLR(WB_SIO_MII_DATAIN);
338 SIO_CLR(WB_SIO_MII_CLK);
340 SIO_SET(WB_SIO_MII_CLK);
345 * Read an PHY register through the MII.
348 wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame)
355 * Set up frame for RX.
357 frame->mii_stdelim = WB_MII_STARTDELIM;
358 frame->mii_opcode = WB_MII_READOP;
359 frame->mii_turnaround = 0;
362 CSR_WRITE_4(sc, WB_SIO, 0);
367 SIO_SET(WB_SIO_MII_DIR);
372 * Send command/address info.
374 wb_mii_send(sc, frame->mii_stdelim, 2);
375 wb_mii_send(sc, frame->mii_opcode, 2);
376 wb_mii_send(sc, frame->mii_phyaddr, 5);
377 wb_mii_send(sc, frame->mii_regaddr, 5);
380 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN));
382 SIO_SET(WB_SIO_MII_CLK);
386 SIO_CLR(WB_SIO_MII_DIR);
388 SIO_CLR(WB_SIO_MII_CLK);
390 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
391 SIO_SET(WB_SIO_MII_CLK);
393 SIO_CLR(WB_SIO_MII_CLK);
395 SIO_SET(WB_SIO_MII_CLK);
399 * Now try reading data bits. If the ack failed, we still
400 * need to clock through 16 cycles to keep the PHY(s) in sync.
403 for(i = 0; i < 16; i++) {
404 SIO_CLR(WB_SIO_MII_CLK);
406 SIO_SET(WB_SIO_MII_CLK);
412 for (i = 0x8000; i; i >>= 1) {
413 SIO_CLR(WB_SIO_MII_CLK);
416 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
417 frame->mii_data |= i;
420 SIO_SET(WB_SIO_MII_CLK);
426 SIO_CLR(WB_SIO_MII_CLK);
428 SIO_SET(WB_SIO_MII_CLK);
439 * Write to a PHY register through the MII.
442 wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame)
447 * Set up frame for TX.
450 frame->mii_stdelim = WB_MII_STARTDELIM;
451 frame->mii_opcode = WB_MII_WRITEOP;
452 frame->mii_turnaround = WB_MII_TURNAROUND;
455 * Turn on data output.
457 SIO_SET(WB_SIO_MII_DIR);
461 wb_mii_send(sc, frame->mii_stdelim, 2);
462 wb_mii_send(sc, frame->mii_opcode, 2);
463 wb_mii_send(sc, frame->mii_phyaddr, 5);
464 wb_mii_send(sc, frame->mii_regaddr, 5);
465 wb_mii_send(sc, frame->mii_turnaround, 2);
466 wb_mii_send(sc, frame->mii_data, 16);
469 SIO_SET(WB_SIO_MII_CLK);
471 SIO_CLR(WB_SIO_MII_CLK);
477 SIO_CLR(WB_SIO_MII_DIR);
485 wb_miibus_readreg(device_t dev, int phy, int reg)
487 struct wb_softc *sc = device_get_softc(dev);
488 struct wb_mii_frame frame;
490 bzero(&frame, sizeof(frame));
492 frame.mii_phyaddr = phy;
493 frame.mii_regaddr = reg;
494 wb_mii_readreg(sc, &frame);
496 return(frame.mii_data);
500 wb_miibus_writereg(device_t dev, int phy, int reg, int data)
502 struct wb_softc *sc = device_get_softc(dev);
503 struct wb_mii_frame frame;
505 bzero(&frame, sizeof(frame));
507 frame.mii_phyaddr = phy;
508 frame.mii_regaddr = reg;
509 frame.mii_data = data;
511 wb_mii_writereg(sc, &frame);
517 wb_miibus_statchg(device_t dev)
519 struct wb_softc *sc = device_get_softc(dev);
520 struct mii_data *mii;
522 mii = device_get_softc(sc->wb_miibus);
523 wb_setcfg(sc, mii->mii_media_active);
527 * Program the 64-bit multicast hash filter.
530 wb_setmulti(struct wb_softc *sc)
532 struct ifnet *ifp = &sc->arpcom.ac_if;
534 uint32_t hashes[2] = { 0, 0 };
535 struct ifmultiaddr *ifma;
538 rxfilt = CSR_READ_4(sc, WB_NETCFG);
540 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
541 rxfilt |= WB_NETCFG_RX_MULTI;
542 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
543 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
544 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
548 /* first, zot all the existing hash bits */
549 CSR_WRITE_4(sc, WB_MAR0, 0);
550 CSR_WRITE_4(sc, WB_MAR1, 0);
552 /* now program new ones */
553 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
554 if (ifma->ifma_addr->sa_family != AF_LINK)
556 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
557 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
559 hashes[0] |= (1 << h);
561 hashes[1] |= (1 << (h - 32));
566 rxfilt |= WB_NETCFG_RX_MULTI;
568 rxfilt &= ~WB_NETCFG_RX_MULTI;
570 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
571 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
572 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
576 * The Winbond manual states that in order to fiddle with the
577 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
578 * first have to put the transmit and/or receive logic in the idle state.
581 wb_setcfg(struct wb_softc *sc, uint32_t media)
585 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) {
587 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON));
589 for (i = 0; i < WB_TIMEOUT; i++) {
591 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
592 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
596 if (i == WB_TIMEOUT) {
597 if_printf(&sc->arpcom.ac_if, "failed to force tx and "
598 "rx to idle state\n");
602 if (IFM_SUBTYPE(media) == IFM_10_T)
603 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
605 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
607 if ((media & IFM_GMASK) == IFM_FDX)
608 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
610 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
613 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON);
617 wb_reset(struct wb_softc *sc)
620 struct mii_data *mii;
622 CSR_WRITE_4(sc, WB_NETCFG, 0);
623 CSR_WRITE_4(sc, WB_BUSCTL, 0);
624 CSR_WRITE_4(sc, WB_TXADDR, 0);
625 CSR_WRITE_4(sc, WB_RXADDR, 0);
627 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
628 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
630 for (i = 0; i < WB_TIMEOUT; i++) {
632 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0)
636 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
638 /* Wait a little while for the chip to get its brains in order. */
641 if (sc->wb_miibus == NULL)
644 mii = device_get_softc(sc->wb_miibus);
648 if (mii->mii_instance) {
649 struct mii_softc *miisc;
650 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
651 mii_phy_reset(miisc);
656 wb_fixmedia(struct wb_softc *sc)
658 struct mii_data *mii;
661 if (sc->wb_miibus == NULL)
664 mii = device_get_softc(sc->wb_miibus);
667 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
668 media = mii->mii_media_active & ~IFM_10_T;
670 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
671 media = mii->mii_media_active & ~IFM_100_TX;
676 ifmedia_set(&mii->mii_media, media);
680 * Probe for a Winbond chip. Check the PCI vendor and device
681 * IDs against our list and return a device name if we find a match.
684 wb_probe(device_t dev)
687 uint16_t vendor, product;
689 vendor = pci_get_vendor(dev);
690 product = pci_get_device(dev);
692 for (t = wb_devs; t->wb_name != NULL; t++) {
693 if (vendor == t->wb_vid && product == t->wb_did) {
694 device_set_desc(dev, t->wb_name);
703 * Attach the interface. Allocate softc structures, do ifmedia
704 * setup and ethernet/BPF attach.
707 wb_attach(device_t dev)
709 u_char eaddr[ETHER_ADDR_LEN];
714 sc = device_get_softc(dev);
715 callout_init(&sc->wb_stat_timer);
718 * Handle power management nonsense.
720 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
721 uint32_t iobase, membase, irq;
723 /* Save important PCI config data. */
724 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
725 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
726 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
728 /* Reset the power state. */
729 device_printf(dev, "chip is in D%d power mode "
730 "-- setting to D0\n", pci_get_powerstate(dev));
731 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
733 /* Restore PCI config data. */
734 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
735 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
736 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
739 pci_enable_busmaster(dev);
742 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
744 if (sc->wb_res == NULL) {
745 device_printf(dev, "couldn't map ports/memory\n");
750 sc->wb_btag = rman_get_bustag(sc->wb_res);
751 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
753 /* Allocate interrupt */
755 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
756 RF_SHAREABLE | RF_ACTIVE);
758 if (sc->wb_irq == NULL) {
759 device_printf(dev, "couldn't map interrupt\n");
764 /* Save the cache line size. */
765 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
767 ifp = &sc->arpcom.ac_if;
768 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
770 /* Reset the adapter. */
774 * Get station address from the EEPROM.
776 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3);
778 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
779 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
781 if (sc->wb_ldata == NULL) {
782 device_printf(dev, "no memory for list buffers!\n");
787 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
790 ifp->if_mtu = ETHERMTU;
791 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
792 ifp->if_ioctl = wb_ioctl;
793 ifp->if_start = wb_start;
794 ifp->if_watchdog = wb_watchdog;
795 ifp->if_init = wb_init;
796 ifp->if_baudrate = 10000000;
797 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1);
798 ifq_set_ready(&ifp->if_snd);
803 if (mii_phy_probe(dev, &sc->wb_miibus,
804 wb_ifmedia_upd, wb_ifmedia_sts)) {
810 * Call MI attach routine.
812 ether_ifattach(ifp, eaddr, NULL);
814 error = bus_setup_intr(dev, sc->wb_irq, INTR_NETSAFE,
815 wb_intr, sc, &sc->wb_intrhand,
819 device_printf(dev, "couldn't set up irq\n");
832 wb_detach(device_t dev)
834 struct wb_softc *sc = device_get_softc(dev);
835 struct ifnet *ifp = &sc->arpcom.ac_if;
838 if (device_is_attached(dev)) {
839 lwkt_serialize_enter(ifp->if_serializer);
841 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
842 lwkt_serialize_exit(ifp->if_serializer);
848 device_delete_child(dev, sc->wb_miibus);
849 bus_generic_detach(dev);
852 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
854 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
855 if (sc->wb_ldata_ptr) {
856 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
864 * Initialize the transmit descriptors.
867 wb_list_tx_init(struct wb_softc *sc)
869 struct wb_chain_data *cd;
870 struct wb_list_data *ld;
876 for (i = 0; i < WB_TX_LIST_CNT; i++) {
877 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1;
878 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
879 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti];
882 cd->wb_tx_free = &cd->wb_tx_chain[0];
883 cd->wb_tx_tail = cd->wb_tx_head = NULL;
889 * Initialize the RX descriptors and allocate mbufs for them. Note that
890 * we arrange the descriptors in a closed ring, so that the last descriptor
891 * points back to the first.
894 wb_list_rx_init(struct wb_softc *sc)
896 struct wb_chain_data *cd;
897 struct wb_list_data *ld;
903 for (i = 0; i < WB_RX_LIST_CNT; i++) {
904 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i];
905 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i];
906 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
908 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1;
909 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti];
910 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]);
913 cd->wb_rx_head = &cd->wb_rx_chain[0];
924 * Initialize an RX descriptor and attach an MBUF cluster.
927 wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m)
929 struct mbuf *m_new = NULL;
932 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
936 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
937 m_new->m_flags |= M_EXT;
938 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
939 m_new->m_len = WB_BUFBYTES;
940 m_new->m_ext.ext_free = wb_bfree;
941 m_new->m_ext.ext_ref = wb_bfree;
944 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
945 m_new->m_data = m_new->m_ext.ext_buf;
948 m_adj(m_new, sizeof(uint64_t));
951 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
952 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
953 c->wb_ptr->wb_status = WB_RXSTAT;
959 * A frame has been uploaded: pass the resulting mbuf chain up to
960 * the higher level protocols.
963 wb_rxeof(struct wb_softc *sc)
965 struct ifnet *ifp = &sc->arpcom.ac_if;
967 struct wb_chain_onefrag *cur_rx;
972 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status;
973 if ((rxstat & WB_RXSTAT_OWN) == 0)
976 cur_rx = sc->wb_cdata.wb_rx_head;
977 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
981 if ((rxstat & WB_RXSTAT_MIIERR) ||
982 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
983 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
984 (rxstat & WB_RXSTAT_LASTFRAG) == 0||
985 (rxstat & WB_RXSTAT_RXCMP) == 0) {
987 wb_newbuf(sc, cur_rx, m);
988 if_printf(ifp, "receiver babbling: possible chip "
989 "bug, forcing reset\n");
996 if (rxstat & WB_RXSTAT_RXERR) {
998 wb_newbuf(sc, cur_rx, m);
1002 /* No errors; receive the packet. */
1003 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1006 * XXX The Winbond chip includes the CRC with every
1007 * received frame, and there's no way to turn this
1008 * behavior off (at least, I can't find anything in
1009 * the manual that explains how to do it) so we have
1010 * to trim off the CRC manually.
1012 total_len -= ETHER_CRC_LEN;
1014 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1015 total_len + ETHER_ALIGN, 0, ifp, NULL);
1016 wb_newbuf(sc, cur_rx, m);
1021 m_adj(m0, ETHER_ALIGN);
1025 ifp->if_input(ifp, m);
1030 wb_rxeoc(struct wb_softc *sc)
1034 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1035 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1036 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1037 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1038 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1042 * A frame was downloaded to the chip. It's safe for us to clean up
1046 wb_txeof(struct wb_softc *sc)
1048 struct ifnet *ifp = &sc->arpcom.ac_if;
1049 struct wb_chain *cur_tx;
1051 /* Clear the timeout timer. */
1054 if (sc->wb_cdata.wb_tx_head == NULL)
1058 * Go through our tx list and free mbufs for those
1059 * frames that have been transmitted.
1061 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1064 cur_tx = sc->wb_cdata.wb_tx_head;
1065 txstat = WB_TXSTATUS(cur_tx);
1067 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1070 if (txstat & WB_TXSTAT_TXERR) {
1072 if (txstat & WB_TXSTAT_ABORT)
1073 ifp->if_collisions++;
1074 if (txstat & WB_TXSTAT_LATECOLL)
1075 ifp->if_collisions++;
1078 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1081 m_freem(cur_tx->wb_mbuf);
1082 cur_tx->wb_mbuf = NULL;
1084 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1085 sc->wb_cdata.wb_tx_head = NULL;
1086 sc->wb_cdata.wb_tx_tail = NULL;
1090 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1095 * TX 'end of channel' interrupt handler.
1098 wb_txeoc(struct wb_softc *sc)
1100 struct ifnet *ifp = &sc->arpcom.ac_if;
1104 if (sc->wb_cdata.wb_tx_head == NULL) {
1105 ifp->if_flags &= ~IFF_OACTIVE;
1106 sc->wb_cdata.wb_tx_tail = NULL;
1107 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1108 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1110 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1117 struct wb_softc *sc = arg;
1118 struct ifnet *ifp = &sc->arpcom.ac_if;
1121 if ((ifp->if_flags & IFF_UP) == 0)
1124 /* Disable interrupts. */
1125 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1128 status = CSR_READ_4(sc, WB_ISR);
1130 CSR_WRITE_4(sc, WB_ISR, status);
1132 if ((status & WB_INTRS) == 0)
1135 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1138 if (status & WB_ISR_RX_ERR)
1144 if (status & WB_ISR_RX_OK)
1147 if (status & WB_ISR_RX_IDLE)
1150 if (status & WB_ISR_TX_OK)
1153 if (status & WB_ISR_TX_NOBUF)
1156 if (status & WB_ISR_TX_IDLE) {
1158 if (sc->wb_cdata.wb_tx_head != NULL) {
1159 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1160 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1164 if (status & WB_ISR_TX_UNDERRUN) {
1167 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1168 /* Jack up TX threshold */
1169 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1170 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1171 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1172 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1175 if (status & WB_ISR_BUS_ERR) {
1181 /* Re-enable interrupts. */
1182 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1184 if (!ifq_is_empty(&ifp->if_snd))
1191 struct wb_softc *sc = xsc;
1192 struct ifnet *ifp = &sc->arpcom.ac_if;
1193 struct mii_data *mii = device_get_softc(sc->wb_miibus);
1195 lwkt_serialize_enter(ifp->if_serializer);
1197 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1198 lwkt_serialize_exit(ifp->if_serializer);
1202 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1203 * pointers to the fragment pointers.
1206 wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head)
1208 struct wb_desc *f = NULL;
1210 int frag, total_len;
1213 * Start packing the mbufs in this chain into
1214 * the fragment pointers. Stop when we run out
1215 * of fragments or hit the end of the mbuf chain.
1219 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1220 if (m->m_len != 0) {
1221 if (frag == WB_MAXFRAGS)
1223 total_len += m->m_len;
1224 f = &c->wb_ptr->wb_frag[frag];
1225 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1227 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1230 f->wb_status = WB_TXSTAT_OWN;
1232 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1233 f->wb_data = vtophys(mtod(m, vm_offset_t));
1239 * Handle special case: we used up all 16 fragments,
1240 * but we have more mbufs left in the chain. Copy the
1241 * data into an mbuf cluster. Note that we don't
1242 * bother clearing the values in the other fragment
1243 * pointers/counters; it wouldn't gain us anything,
1244 * and would waste cycles.
1247 struct mbuf *m_new = NULL;
1249 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1252 if (m_head->m_pkthdr.len > MHLEN) {
1253 MCLGET(m_new, MB_DONTWAIT);
1254 if ((m_new->m_flags & M_EXT) == 0) {
1259 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1260 mtod(m_new, caddr_t));
1261 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1264 f = &c->wb_ptr->wb_frag[0];
1266 f->wb_data = vtophys(mtod(m_new, caddr_t));
1267 f->wb_ctl = total_len = m_new->m_len;
1268 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1272 if (total_len < WB_MIN_FRAMELEN) {
1273 f = &c->wb_ptr->wb_frag[frag];
1274 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1275 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1276 f->wb_ctl |= WB_TXCTL_TLINK;
1277 f->wb_status = WB_TXSTAT_OWN;
1281 c->wb_mbuf = m_head;
1282 c->wb_lastdesc = frag - 1;
1283 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1284 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1290 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1291 * to the mbuf data regions directly in the transmit lists. We also save a
1292 * copy of the pointers since the transmit list fragment pointers are
1293 * physical addresses.
1296 wb_start(struct ifnet *ifp)
1298 struct wb_softc *sc = ifp->if_softc;
1299 struct mbuf *m_head = NULL;
1300 struct wb_chain *cur_tx = NULL, *start_tx;
1303 * Check for an available queue slot. If there are none,
1306 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1307 ifp->if_flags |= IFF_OACTIVE;
1311 start_tx = sc->wb_cdata.wb_tx_free;
1313 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1314 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1318 /* Pick a descriptor off the free list. */
1319 cur_tx = sc->wb_cdata.wb_tx_free;
1320 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1322 /* Pack the data into the descriptor. */
1323 wb_encap(sc, cur_tx, m_head);
1325 if (cur_tx != start_tx)
1326 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1328 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1332 * If there are no packets queued, bail.
1338 * Place the request for the upload interrupt
1339 * in the last descriptor in the chain. This way, if
1340 * we're chaining several packets at once, we'll only
1341 * get an interupt once for the whole chain rather than
1342 * once for each packet.
1344 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1345 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1346 sc->wb_cdata.wb_tx_tail = cur_tx;
1348 if (sc->wb_cdata.wb_tx_head == NULL) {
1349 sc->wb_cdata.wb_tx_head = start_tx;
1350 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1351 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1354 * We need to distinguish between the case where
1355 * the own bit is clear because the chip cleared it
1356 * and where the own bit is clear because we haven't
1357 * set it yet. The magic value WB_UNSET is just some
1358 * ramdomly chosen number which doesn't have the own
1359 * bit set. When we actually transmit the frame, the
1360 * status word will have _only_ the own bit set, so
1361 * the txeoc handler will be able to tell if it needs
1362 * to initiate another transmission to flush out pending
1365 WB_TXOWN(start_tx) = WB_UNSENT;
1369 * Set a timeout in case the chip goes out to lunch.
1377 struct wb_softc *sc = xsc;
1378 struct ifnet *ifp = &sc->arpcom.ac_if;
1380 struct mii_data *mii;
1384 mii = device_get_softc(sc->wb_miibus);
1387 * Cancel pending I/O and free all RX/TX buffers.
1392 sc->wb_txthresh = WB_TXTHRESH_INIT;
1395 * Set cache alignment and burst length.
1398 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1399 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1400 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1403 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION);
1404 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1405 switch(sc->wb_cachesize) {
1407 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1410 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1413 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1417 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1421 /* This doesn't tend to work too well at 100Mbps. */
1422 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1424 /* Init our MAC address */
1425 for (i = 0; i < ETHER_ADDR_LEN; i++)
1426 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1428 /* Init circular RX list. */
1429 if (wb_list_rx_init(sc) == ENOBUFS) {
1430 if_printf(ifp, "initialization failed: no "
1431 "memory for rx buffers\n");
1437 /* Init TX descriptors. */
1438 wb_list_tx_init(sc);
1440 /* If we want promiscuous mode, set the allframes bit. */
1441 if (ifp->if_flags & IFF_PROMISC)
1442 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1444 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1447 * Set capture broadcast bit to capture broadcast frames.
1449 if (ifp->if_flags & IFF_BROADCAST)
1450 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1452 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1455 * Program the multicast filter, if necessary.
1460 * Load the address of the RX list.
1462 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1463 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1466 * Enable interrupts.
1468 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1469 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1471 /* Enable receiver and transmitter. */
1472 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1473 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1475 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1476 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1477 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1481 ifp->if_flags |= IFF_RUNNING;
1482 ifp->if_flags &= ~IFF_OACTIVE;
1486 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1490 * Set media options.
1493 wb_ifmedia_upd(struct ifnet *ifp)
1495 struct wb_softc *sc = ifp->if_softc;
1497 if (ifp->if_flags & IFF_UP)
1504 * Report current media status.
1507 wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1509 struct wb_softc *sc = ifp->if_softc;
1510 struct mii_data *mii = device_get_softc(sc->wb_miibus);
1513 ifmr->ifm_active = mii->mii_media_active;
1514 ifmr->ifm_status = mii->mii_media_status;
1518 wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1520 struct wb_softc *sc = ifp->if_softc;
1521 struct mii_data *mii;
1522 struct ifreq *ifr = (struct ifreq *) data;
1529 if (ifp->if_flags & IFF_UP)
1531 else if (ifp->if_flags & IFF_RUNNING)
1542 mii = device_get_softc(sc->wb_miibus);
1543 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1546 error = ether_ioctl(ifp, command, data);
1556 wb_watchdog(struct ifnet *ifp)
1558 struct wb_softc *sc = ifp->if_softc;
1561 if_printf(ifp, "watchdog timeout\n");
1563 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0)
1564 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1570 if (!ifq_is_empty(&ifp->if_snd))
1575 * Stop the adapter and free any mbufs allocated to the
1579 wb_stop(struct wb_softc *sc)
1581 struct ifnet *ifp = &sc->arpcom.ac_if;
1586 callout_stop(&sc->wb_stat_timer);
1588 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON));
1589 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1590 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1591 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1594 * Free data in the RX lists.
1596 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1597 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1598 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1599 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1602 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list));
1605 * Free the TX list buffers.
1607 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1608 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1609 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1610 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1614 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list));
1616 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1620 * Stop all chip I/O so that the kernel's probe routines don't
1621 * get confused by errant DMAs when rebooting.
1624 wb_shutdown(device_t dev)
1626 struct wb_softc *sc = device_get_softc(dev);
1627 struct ifnet *ifp = &sc->arpcom.ac_if;
1629 lwkt_serialize_enter(ifp->if_serializer);
1631 lwkt_serialize_exit(ifp->if_serializer);