1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
322 insns made by reload. */
323 HOST_WIDE_INT offset; /* Current offset between the two regs. */
324 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
325 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
326 rtx from_rtx; /* REG rtx for the register to be eliminated.
327 We cannot simply compare the number since
328 we might then spuriously replace a hard
329 register corresponding to a pseudo
330 assigned to the reg to be eliminated. */
331 rtx to_rtx; /* REG rtx for the replacement. */
334 static struct elim_table *reg_eliminate = 0;
336 /* This is an intermediate structure to initialize the table. It has
337 exactly the members provided by ELIMINABLE_REGS. */
338 static const struct elim_table_1
342 } reg_eliminate_1[] =
344 /* If a set of eliminable registers was specified, define the table from it.
345 Otherwise, default to the normal case of the frame pointer being
346 replaced by the stack pointer. */
348 #ifdef ELIMINABLE_REGS
351 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
354 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
356 /* Record the number of pending eliminations that have an offset not equal
357 to their initial offset. If nonzero, we use a new copy of each
358 replacement result in any insns encountered. */
359 int num_not_at_initial_offset;
361 /* Count the number of registers that we may be able to eliminate. */
362 static int num_eliminable;
363 /* And the number of registers that are equivalent to a constant that
364 can be eliminated to frame_pointer / arg_pointer + constant. */
365 static int num_eliminable_invariants;
367 /* For each label, we record the offset of each elimination. If we reach
368 a label by more than one path and an offset differs, we cannot do the
369 elimination. This information is indexed by the difference of the
370 number of the label and the first label number. We can't offset the
371 pointer itself as this can cause problems on machines with segmented
372 memory. The first table is an array of flags that records whether we
373 have yet encountered a label and the second table is an array of arrays,
374 one entry in the latter array for each elimination. */
376 static int first_label_num;
377 static char *offsets_known_at;
378 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
380 /* Number of labels in the current function. */
382 static int num_labels;
384 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain *);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain *, int);
389 static void find_reload_regs (struct insn_chain *);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx, enum reg_class);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx, rtx, int);
398 static void check_eliminable_occurrences (rtx);
399 static void elimination_effects (rtx, enum machine_mode);
400 static int eliminate_regs_in_insn (rtx, int);
401 static void update_eliminable_offsets (void);
402 static void mark_not_eliminable (rtx, const_rtx, void *);
403 static void set_initial_elim_offsets (void);
404 static bool verify_initial_elim_offsets (void);
405 static void set_initial_label_offsets (void);
406 static void set_offsets_for_label (rtx);
407 static void init_elim_table (void);
408 static void update_eliminables (HARD_REG_SET *);
409 static void spill_hard_reg (unsigned int, int);
410 static int finish_spills (int);
411 static void scan_paradoxical_subregs (rtx);
412 static void count_pseudo (int);
413 static void order_regs_for_reload (struct insn_chain *);
414 static void reload_as_needed (int);
415 static void forget_old_reloads_1 (rtx, const_rtx, void *);
416 static void forget_marked_reloads (regset);
417 static int reload_reg_class_lower (const void *, const void *);
418 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
420 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
422 static int reload_reg_free_p (unsigned int, int, enum reload_type);
423 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
425 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
427 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
428 static int allocate_reload_reg (struct insn_chain *, int, int);
429 static int conflicts_with_override (rtx);
430 static void failed_reload (rtx, int);
431 static int set_reload_reg (int, int);
432 static void choose_reload_regs_init (struct insn_chain *, rtx *);
433 static void choose_reload_regs (struct insn_chain *);
434 static void merge_assigned_reloads (rtx);
435 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
437 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
439 static void do_input_reload (struct insn_chain *, struct reload *, int);
440 static void do_output_reload (struct insn_chain *, struct reload *, int);
441 static void emit_reload_insns (struct insn_chain *);
442 static void delete_output_reload (rtx, int, int, rtx);
443 static void delete_address_reloads (rtx, rtx);
444 static void delete_address_reloads_1 (rtx, rtx, rtx);
445 static rtx inc_for_reload (rtx, rtx, rtx, int);
447 static void add_auto_inc_notes (rtx, rtx);
449 static void copy_eh_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert (ira_conflicts_p || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
1002 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1004 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1005 else if (CONSTANT_P (XEXP (x, 0))
1006 || (REG_P (XEXP (x, 0))
1007 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1008 || (GET_CODE (XEXP (x, 0)) == PLUS
1009 && REG_P (XEXP (XEXP (x, 0), 0))
1010 && (REGNO (XEXP (XEXP (x, 0), 0))
1011 < FIRST_PSEUDO_REGISTER)
1012 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1013 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1016 /* Make a new stack slot. Then indicate that something
1017 changed so we go back and recompute offsets for
1018 eliminable registers because the allocation of memory
1019 below might change some offset. reg_equiv_{mem,address}
1020 will be set up for this pseudo on the next pass around
1022 reg_equiv_memory_loc[i] = 0;
1023 reg_equiv_init[i] = 0;
1024 alter_reg (i, -1, true);
1028 if (caller_save_needed)
1029 setup_save_areas ();
1031 /* If we allocated another stack slot, redo elimination bookkeeping. */
1032 if (starting_frame_size != get_frame_size ())
1034 if (starting_frame_size && crtl->stack_alignment_needed)
1036 /* If we have a stack frame, we must align it now. The
1037 stack size may be a part of the offset computation for
1038 register elimination. So if this changes the stack size,
1039 then repeat the elimination bookkeeping. We don't
1040 realign when there is no stack, as that will cause a
1041 stack frame when none is needed should
1042 STARTING_FRAME_OFFSET not be already aligned to
1044 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1045 if (starting_frame_size != get_frame_size ())
1049 if (caller_save_needed)
1051 save_call_clobbered_regs ();
1052 /* That might have allocated new insn_chain structures. */
1053 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1056 calculate_needs_all_insns (global);
1058 if (! ira_conflicts_p)
1059 /* Don't do it for IRA. We need this info because we don't
1060 change live_throughout and dead_or_set for chains when IRA
1062 CLEAR_REG_SET (&spilled_pseudos);
1066 something_changed = 0;
1068 /* If we allocated any new memory locations, make another pass
1069 since it might have changed elimination offsets. */
1070 if (starting_frame_size != get_frame_size ())
1071 something_changed = 1;
1073 /* Even if the frame size remained the same, we might still have
1074 changed elimination offsets, e.g. if find_reloads called
1075 force_const_mem requiring the back end to allocate a constant
1076 pool base register that needs to be saved on the stack. */
1077 else if (!verify_initial_elim_offsets ())
1078 something_changed = 1;
1081 HARD_REG_SET to_spill;
1082 CLEAR_HARD_REG_SET (to_spill);
1083 update_eliminables (&to_spill);
1084 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1086 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1087 if (TEST_HARD_REG_BIT (to_spill, i))
1089 spill_hard_reg (i, 1);
1092 /* Regardless of the state of spills, if we previously had
1093 a register that we thought we could eliminate, but now can
1094 not eliminate, we must run another pass.
1096 Consider pseudos which have an entry in reg_equiv_* which
1097 reference an eliminable register. We must make another pass
1098 to update reg_equiv_* so that we do not substitute in the
1099 old value from when we thought the elimination could be
1101 something_changed = 1;
1105 select_reload_regs ();
1109 if (insns_need_reload != 0 || did_spill)
1110 something_changed |= finish_spills (global);
1112 if (! something_changed)
1115 if (caller_save_needed)
1116 delete_caller_save_insns ();
1118 obstack_free (&reload_obstack, reload_firstobj);
1121 /* If global-alloc was run, notify it of any register eliminations we have
1124 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1125 if (ep->can_eliminate)
1126 mark_elimination (ep->from, ep->to);
1128 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1129 If that insn didn't set the register (i.e., it copied the register to
1130 memory), just delete that insn instead of the equivalencing insn plus
1131 anything now dead. If we call delete_dead_insn on that insn, we may
1132 delete the insn that actually sets the register if the register dies
1133 there and that is incorrect. */
1135 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1137 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1140 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1142 rtx equiv_insn = XEXP (list, 0);
1144 /* If we already deleted the insn or if it may trap, we can't
1145 delete it. The latter case shouldn't happen, but can
1146 if an insn has a variable address, gets a REG_EH_REGION
1147 note added to it, and then gets converted into a load
1148 from a constant address. */
1149 if (NOTE_P (equiv_insn)
1150 || can_throw_internal (equiv_insn))
1152 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1153 delete_dead_insn (equiv_insn);
1155 SET_INSN_DELETED (equiv_insn);
1160 /* Use the reload registers where necessary
1161 by generating move instructions to move the must-be-register
1162 values into or out of the reload registers. */
1164 if (insns_need_reload != 0 || something_needs_elimination
1165 || something_needs_operands_changed)
1167 HOST_WIDE_INT old_frame_size = get_frame_size ();
1169 reload_as_needed (global);
1171 gcc_assert (old_frame_size == get_frame_size ());
1173 gcc_assert (verify_initial_elim_offsets ());
1176 /* If we were able to eliminate the frame pointer, show that it is no
1177 longer live at the start of any basic block. If it ls live by
1178 virtue of being in a pseudo, that pseudo will be marked live
1179 and hence the frame pointer will be known to be live via that
1182 if (! frame_pointer_needed)
1184 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1186 /* Come here (with failure set nonzero) if we can't get enough spill
1190 CLEAR_REG_SET (&changed_allocation_pseudos);
1191 CLEAR_REG_SET (&spilled_pseudos);
1192 reload_in_progress = 0;
1194 /* Now eliminate all pseudo regs by modifying them into
1195 their equivalent memory references.
1196 The REG-rtx's for the pseudos are modified in place,
1197 so all insns that used to refer to them now refer to memory.
1199 For a reg that has a reg_equiv_address, all those insns
1200 were changed by reloading so that no insns refer to it any longer;
1201 but the DECL_RTL of a variable decl may refer to it,
1202 and if so this causes the debugging info to mention the variable. */
1204 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1208 if (reg_equiv_mem[i])
1209 addr = XEXP (reg_equiv_mem[i], 0);
1211 if (reg_equiv_address[i])
1212 addr = reg_equiv_address[i];
1216 if (reg_renumber[i] < 0)
1218 rtx reg = regno_reg_rtx[i];
1220 REG_USERVAR_P (reg) = 0;
1221 PUT_CODE (reg, MEM);
1222 XEXP (reg, 0) = addr;
1223 if (reg_equiv_memory_loc[i])
1224 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1227 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1228 MEM_ATTRS (reg) = 0;
1230 MEM_NOTRAP_P (reg) = 1;
1232 else if (reg_equiv_mem[i])
1233 XEXP (reg_equiv_mem[i], 0) = addr;
1237 /* We must set reload_completed now since the cleanup_subreg_operands call
1238 below will re-recognize each insn and reload may have generated insns
1239 which are only valid during and after reload. */
1240 reload_completed = 1;
1242 /* Make a pass over all the insns and delete all USEs which we inserted
1243 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1244 notes. Delete all CLOBBER insns, except those that refer to the return
1245 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1246 from misarranging variable-array code, and simplify (subreg (reg))
1247 operands. Strip and regenerate REG_INC notes that may have been moved
1250 for (insn = first; insn; insn = NEXT_INSN (insn))
1256 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1257 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1259 if ((GET_CODE (PATTERN (insn)) == USE
1260 /* We mark with QImode USEs introduced by reload itself. */
1261 && (GET_MODE (insn) == QImode
1262 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1263 || (GET_CODE (PATTERN (insn)) == CLOBBER
1264 && (!MEM_P (XEXP (PATTERN (insn), 0))
1265 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1266 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1267 && XEXP (XEXP (PATTERN (insn), 0), 0)
1268 != stack_pointer_rtx))
1269 && (!REG_P (XEXP (PATTERN (insn), 0))
1270 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1276 /* Some CLOBBERs may survive until here and still reference unassigned
1277 pseudos with const equivalent, which may in turn cause ICE in later
1278 passes if the reference remains in place. */
1279 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1280 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1281 VOIDmode, PATTERN (insn));
1283 /* Discard obvious no-ops, even without -O. This optimization
1284 is fast and doesn't interfere with debugging. */
1285 if (NONJUMP_INSN_P (insn)
1286 && GET_CODE (PATTERN (insn)) == SET
1287 && REG_P (SET_SRC (PATTERN (insn)))
1288 && REG_P (SET_DEST (PATTERN (insn)))
1289 && (REGNO (SET_SRC (PATTERN (insn)))
1290 == REGNO (SET_DEST (PATTERN (insn)))))
1296 pnote = ®_NOTES (insn);
1299 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1300 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1301 || REG_NOTE_KIND (*pnote) == REG_INC)
1302 *pnote = XEXP (*pnote, 1);
1304 pnote = &XEXP (*pnote, 1);
1308 add_auto_inc_notes (insn, PATTERN (insn));
1311 /* Simplify (subreg (reg)) if it appears as an operand. */
1312 cleanup_subreg_operands (insn);
1314 /* Clean up invalid ASMs so that they don't confuse later passes.
1316 if (asm_noperands (PATTERN (insn)) >= 0)
1318 extract_insn (insn);
1319 if (!constrain_operands (1))
1321 error_for_asm (insn,
1322 "%<asm%> operand has impossible constraints");
1329 /* If we are doing generic stack checking, give a warning if this
1330 function's frame size is larger than we expect. */
1331 if (flag_stack_check == GENERIC_STACK_CHECK)
1333 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1334 static int verbose_warned = 0;
1336 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1337 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1338 size += UNITS_PER_WORD;
1340 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1342 warning (0, "frame size too large for reliable stack checking");
1343 if (! verbose_warned)
1345 warning (0, "try reducing the number of local variables");
1351 /* Indicate that we no longer have known memory locations or constants. */
1352 if (reg_equiv_constant)
1353 free (reg_equiv_constant);
1354 if (reg_equiv_invariant)
1355 free (reg_equiv_invariant);
1356 reg_equiv_constant = 0;
1357 reg_equiv_invariant = 0;
1358 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1359 reg_equiv_memory_loc = 0;
1361 free (temp_pseudo_reg_arr);
1363 if (offsets_known_at)
1364 free (offsets_known_at);
1368 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1369 if (reg_equiv_alt_mem_list[i])
1370 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1371 free (reg_equiv_alt_mem_list);
1373 free (reg_equiv_mem);
1375 free (reg_equiv_address);
1376 free (reg_max_ref_width);
1377 free (reg_old_renumber);
1378 free (pseudo_previous_regs);
1379 free (pseudo_forbidden_regs);
1381 CLEAR_HARD_REG_SET (used_spill_regs);
1382 for (i = 0; i < n_spills; i++)
1383 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1385 /* Free all the insn_chain structures at once. */
1386 obstack_free (&reload_obstack, reload_startobj);
1387 unused_insn_chains = 0;
1388 fixup_abnormal_edges ();
1390 /* Replacing pseudos with their memory equivalents might have
1391 created shared rtx. Subsequent passes would get confused
1392 by this, so unshare everything here. */
1393 unshare_all_rtl_again (first);
1395 #ifdef STACK_BOUNDARY
1396 /* init_emit has set the alignment of the hard frame pointer
1397 to STACK_BOUNDARY. It is very likely no longer valid if
1398 the hard frame pointer was used for register allocation. */
1399 if (!frame_pointer_needed)
1400 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1406 /* Yet another special case. Unfortunately, reg-stack forces people to
1407 write incorrect clobbers in asm statements. These clobbers must not
1408 cause the register to appear in bad_spill_regs, otherwise we'll call
1409 fatal_insn later. We clear the corresponding regnos in the live
1410 register sets to avoid this.
1411 The whole thing is rather sick, I'm afraid. */
1414 maybe_fix_stack_asms (void)
1417 const char *constraints[MAX_RECOG_OPERANDS];
1418 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1419 struct insn_chain *chain;
1421 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1424 HARD_REG_SET clobbered, allowed;
1427 if (! INSN_P (chain->insn)
1428 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1430 pat = PATTERN (chain->insn);
1431 if (GET_CODE (pat) != PARALLEL)
1434 CLEAR_HARD_REG_SET (clobbered);
1435 CLEAR_HARD_REG_SET (allowed);
1437 /* First, make a mask of all stack regs that are clobbered. */
1438 for (i = 0; i < XVECLEN (pat, 0); i++)
1440 rtx t = XVECEXP (pat, 0, i);
1441 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1442 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1445 /* Get the operand values and constraints out of the insn. */
1446 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1447 constraints, operand_mode, NULL);
1449 /* For every operand, see what registers are allowed. */
1450 for (i = 0; i < noperands; i++)
1452 const char *p = constraints[i];
1453 /* For every alternative, we compute the class of registers allowed
1454 for reloading in CLS, and merge its contents into the reg set
1456 int cls = (int) NO_REGS;
1462 if (c == '\0' || c == ',' || c == '#')
1464 /* End of one alternative - mark the regs in the current
1465 class, and reset the class. */
1466 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1472 } while (c != '\0' && c != ',');
1480 case '=': case '+': case '*': case '%': case '?': case '!':
1481 case '0': case '1': case '2': case '3': case '4': case '<':
1482 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1483 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1484 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1485 case TARGET_MEM_CONSTRAINT:
1489 cls = (int) reg_class_subunion[cls]
1490 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1495 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1499 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1500 cls = (int) reg_class_subunion[cls]
1501 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1503 cls = (int) reg_class_subunion[cls]
1504 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1506 p += CONSTRAINT_LEN (c, p);
1509 /* Those of the registers which are clobbered, but allowed by the
1510 constraints, must be usable as reload registers. So clear them
1511 out of the life information. */
1512 AND_HARD_REG_SET (allowed, clobbered);
1513 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1514 if (TEST_HARD_REG_BIT (allowed, i))
1516 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1517 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1524 /* Copy the global variables n_reloads and rld into the corresponding elts
1527 copy_reloads (struct insn_chain *chain)
1529 chain->n_reloads = n_reloads;
1530 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1531 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1532 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1535 /* Walk the chain of insns, and determine for each whether it needs reloads
1536 and/or eliminations. Build the corresponding insns_need_reload list, and
1537 set something_needs_elimination as appropriate. */
1539 calculate_needs_all_insns (int global)
1541 struct insn_chain **pprev_reload = &insns_need_reload;
1542 struct insn_chain *chain, *next = 0;
1544 something_needs_elimination = 0;
1546 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1547 for (chain = reload_insn_chain; chain != 0; chain = next)
1549 rtx insn = chain->insn;
1553 /* Clear out the shortcuts. */
1554 chain->n_reloads = 0;
1555 chain->need_elim = 0;
1556 chain->need_reload = 0;
1557 chain->need_operand_change = 0;
1559 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1560 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1561 what effects this has on the known offsets at labels. */
1563 if (LABEL_P (insn) || JUMP_P (insn)
1564 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1565 set_label_offsets (insn, insn, 0);
1569 rtx old_body = PATTERN (insn);
1570 int old_code = INSN_CODE (insn);
1571 rtx old_notes = REG_NOTES (insn);
1572 int did_elimination = 0;
1573 int operands_changed = 0;
1574 rtx set = single_set (insn);
1576 /* Skip insns that only set an equivalence. */
1577 if (set && REG_P (SET_DEST (set))
1578 && reg_renumber[REGNO (SET_DEST (set))] < 0
1579 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1580 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1581 && reg_equiv_init[REGNO (SET_DEST (set))])
1584 /* If needed, eliminate any eliminable registers. */
1585 if (num_eliminable || num_eliminable_invariants)
1586 did_elimination = eliminate_regs_in_insn (insn, 0);
1588 /* Analyze the instruction. */
1589 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1590 global, spill_reg_order);
1592 /* If a no-op set needs more than one reload, this is likely
1593 to be something that needs input address reloads. We
1594 can't get rid of this cleanly later, and it is of no use
1595 anyway, so discard it now.
1596 We only do this when expensive_optimizations is enabled,
1597 since this complements reload inheritance / output
1598 reload deletion, and it can make debugging harder. */
1599 if (flag_expensive_optimizations && n_reloads > 1)
1601 rtx set = single_set (insn);
1604 ((SET_SRC (set) == SET_DEST (set)
1605 && REG_P (SET_SRC (set))
1606 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1607 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1608 && reg_renumber[REGNO (SET_SRC (set))] < 0
1609 && reg_renumber[REGNO (SET_DEST (set))] < 0
1610 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1611 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1612 && rtx_equal_p (reg_equiv_memory_loc
1613 [REGNO (SET_SRC (set))],
1614 reg_equiv_memory_loc
1615 [REGNO (SET_DEST (set))]))))
1617 if (ira_conflicts_p)
1618 /* Inform IRA about the insn deletion. */
1619 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1620 REGNO (SET_SRC (set)));
1622 /* Delete it from the reload chain. */
1624 chain->prev->next = next;
1626 reload_insn_chain = next;
1628 next->prev = chain->prev;
1629 chain->next = unused_insn_chains;
1630 unused_insn_chains = chain;
1635 update_eliminable_offsets ();
1637 /* Remember for later shortcuts which insns had any reloads or
1638 register eliminations. */
1639 chain->need_elim = did_elimination;
1640 chain->need_reload = n_reloads > 0;
1641 chain->need_operand_change = operands_changed;
1643 /* Discard any register replacements done. */
1644 if (did_elimination)
1646 obstack_free (&reload_obstack, reload_insn_firstobj);
1647 PATTERN (insn) = old_body;
1648 INSN_CODE (insn) = old_code;
1649 REG_NOTES (insn) = old_notes;
1650 something_needs_elimination = 1;
1653 something_needs_operands_changed |= operands_changed;
1657 copy_reloads (chain);
1658 *pprev_reload = chain;
1659 pprev_reload = &chain->next_need_reload;
1666 /* Comparison function for qsort to decide which of two reloads
1667 should be handled first. *P1 and *P2 are the reload numbers. */
1670 reload_reg_class_lower (const void *r1p, const void *r2p)
1672 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1675 /* Consider required reloads before optional ones. */
1676 t = rld[r1].optional - rld[r2].optional;
1680 /* Count all solitary classes before non-solitary ones. */
1681 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1682 - (reg_class_size[(int) rld[r1].rclass] == 1));
1686 /* Aside from solitaires, consider all multi-reg groups first. */
1687 t = rld[r2].nregs - rld[r1].nregs;
1691 /* Consider reloads in order of increasing reg-class number. */
1692 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1696 /* If reloads are equally urgent, sort by reload number,
1697 so that the results of qsort leave nothing to chance. */
1701 /* The cost of spilling each hard reg. */
1702 static int spill_cost[FIRST_PSEUDO_REGISTER];
1704 /* When spilling multiple hard registers, we use SPILL_COST for the first
1705 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1706 only the first hard reg for a multi-reg pseudo. */
1707 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1709 /* Map of hard regno to pseudo regno currently occupying the hard
1711 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1713 /* Update the spill cost arrays, considering that pseudo REG is live. */
1716 count_pseudo (int reg)
1718 int freq = REG_FREQ (reg);
1719 int r = reg_renumber[reg];
1722 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1723 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1724 /* Ignore spilled pseudo-registers which can be here only if IRA
1726 || (ira_conflicts_p && r < 0))
1729 SET_REGNO_REG_SET (&pseudos_counted, reg);
1731 gcc_assert (r >= 0);
1733 spill_add_cost[r] += freq;
1734 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1737 hard_regno_to_pseudo_regno[r + nregs] = reg;
1738 spill_cost[r + nregs] += freq;
1742 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1743 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1746 order_regs_for_reload (struct insn_chain *chain)
1749 HARD_REG_SET used_by_pseudos;
1750 HARD_REG_SET used_by_pseudos2;
1751 reg_set_iterator rsi;
1753 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1755 memset (spill_cost, 0, sizeof spill_cost);
1756 memset (spill_add_cost, 0, sizeof spill_add_cost);
1757 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1758 hard_regno_to_pseudo_regno[i] = -1;
1760 /* Count number of uses of each hard reg by pseudo regs allocated to it
1761 and then order them by decreasing use. First exclude hard registers
1762 that are live in or across this insn. */
1764 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1765 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1766 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1767 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1769 /* Now find out which pseudos are allocated to it, and update
1771 CLEAR_REG_SET (&pseudos_counted);
1773 EXECUTE_IF_SET_IN_REG_SET
1774 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1778 EXECUTE_IF_SET_IN_REG_SET
1779 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1783 CLEAR_REG_SET (&pseudos_counted);
1786 /* Vector of reload-numbers showing the order in which the reloads should
1788 static short reload_order[MAX_RELOADS];
1790 /* This is used to keep track of the spill regs used in one insn. */
1791 static HARD_REG_SET used_spill_regs_local;
1793 /* We decided to spill hard register SPILLED, which has a size of
1794 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1795 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1796 update SPILL_COST/SPILL_ADD_COST. */
1799 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1801 int freq = REG_FREQ (reg);
1802 int r = reg_renumber[reg];
1803 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1805 /* Ignore spilled pseudo-registers which can be here only if IRA is
1807 if ((ira_conflicts_p && r < 0)
1808 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1809 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1812 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1814 spill_add_cost[r] -= freq;
1817 hard_regno_to_pseudo_regno[r + nregs] = -1;
1818 spill_cost[r + nregs] -= freq;
1822 /* Find reload register to use for reload number ORDER. */
1825 find_reg (struct insn_chain *chain, int order)
1827 int rnum = reload_order[order];
1828 struct reload *rl = rld + rnum;
1829 int best_cost = INT_MAX;
1831 unsigned int i, j, n;
1833 HARD_REG_SET not_usable;
1834 HARD_REG_SET used_by_other_reload;
1835 reg_set_iterator rsi;
1836 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1837 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1839 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1840 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1841 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1843 CLEAR_HARD_REG_SET (used_by_other_reload);
1844 for (k = 0; k < order; k++)
1846 int other = reload_order[k];
1848 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1849 for (j = 0; j < rld[other].nregs; j++)
1850 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1853 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1855 #ifdef REG_ALLOC_ORDER
1856 unsigned int regno = reg_alloc_order[i];
1858 unsigned int regno = i;
1861 if (! TEST_HARD_REG_BIT (not_usable, regno)
1862 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1863 && HARD_REGNO_MODE_OK (regno, rl->mode))
1865 int this_cost = spill_cost[regno];
1867 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1869 for (j = 1; j < this_nregs; j++)
1871 this_cost += spill_add_cost[regno + j];
1872 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1873 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1879 if (ira_conflicts_p)
1881 /* Ask IRA to find a better pseudo-register for
1883 for (n = j = 0; j < this_nregs; j++)
1885 int r = hard_regno_to_pseudo_regno[regno + j];
1889 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1890 regno_pseudo_regs[n++] = r;
1892 regno_pseudo_regs[n++] = -1;
1894 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1895 best_regno_pseudo_regs,
1902 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1903 if (regno_pseudo_regs[j] < 0)
1910 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1912 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1914 if (this_cost < best_cost
1915 /* Among registers with equal cost, prefer caller-saved ones, or
1916 use REG_ALLOC_ORDER if it is defined. */
1917 || (this_cost == best_cost
1918 #ifdef REG_ALLOC_ORDER
1919 && (inv_reg_alloc_order[regno]
1920 < inv_reg_alloc_order[best_reg])
1922 && call_used_regs[regno]
1923 && ! call_used_regs[best_reg]
1928 best_cost = this_cost;
1936 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1938 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1939 rl->regno = best_reg;
1941 EXECUTE_IF_SET_IN_REG_SET
1942 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1944 count_spilled_pseudo (best_reg, rl->nregs, j);
1947 EXECUTE_IF_SET_IN_REG_SET
1948 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1950 count_spilled_pseudo (best_reg, rl->nregs, j);
1953 for (i = 0; i < rl->nregs; i++)
1955 gcc_assert (spill_cost[best_reg + i] == 0);
1956 gcc_assert (spill_add_cost[best_reg + i] == 0);
1957 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1958 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1963 /* Find more reload regs to satisfy the remaining need of an insn, which
1965 Do it by ascending class number, since otherwise a reg
1966 might be spilled for a big class and might fail to count
1967 for a smaller class even though it belongs to that class. */
1970 find_reload_regs (struct insn_chain *chain)
1974 /* In order to be certain of getting the registers we need,
1975 we must sort the reloads into order of increasing register class.
1976 Then our grabbing of reload registers will parallel the process
1977 that provided the reload registers. */
1978 for (i = 0; i < chain->n_reloads; i++)
1980 /* Show whether this reload already has a hard reg. */
1981 if (chain->rld[i].reg_rtx)
1983 int regno = REGNO (chain->rld[i].reg_rtx);
1984 chain->rld[i].regno = regno;
1986 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1989 chain->rld[i].regno = -1;
1990 reload_order[i] = i;
1993 n_reloads = chain->n_reloads;
1994 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1996 CLEAR_HARD_REG_SET (used_spill_regs_local);
1999 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2001 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2003 /* Compute the order of preference for hard registers to spill. */
2005 order_regs_for_reload (chain);
2007 for (i = 0; i < n_reloads; i++)
2009 int r = reload_order[i];
2011 /* Ignore reloads that got marked inoperative. */
2012 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2013 && ! rld[r].optional
2014 && rld[r].regno == -1)
2015 if (! find_reg (chain, i))
2018 fprintf (dump_file, "reload failure for reload %d\n", r);
2019 spill_failure (chain->insn, rld[r].rclass);
2025 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2026 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2028 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2032 select_reload_regs (void)
2034 struct insn_chain *chain;
2036 /* Try to satisfy the needs for each insn. */
2037 for (chain = insns_need_reload; chain != 0;
2038 chain = chain->next_need_reload)
2039 find_reload_regs (chain);
2042 /* Delete all insns that were inserted by emit_caller_save_insns during
2045 delete_caller_save_insns (void)
2047 struct insn_chain *c = reload_insn_chain;
2051 while (c != 0 && c->is_caller_save_insn)
2053 struct insn_chain *next = c->next;
2056 if (c == reload_insn_chain)
2057 reload_insn_chain = next;
2061 next->prev = c->prev;
2063 c->prev->next = next;
2064 c->next = unused_insn_chains;
2065 unused_insn_chains = c;
2073 /* Handle the failure to find a register to spill.
2074 INSN should be one of the insns which needed this particular spill reg. */
2077 spill_failure (rtx insn, enum reg_class rclass)
2079 if (asm_noperands (PATTERN (insn)) >= 0)
2080 error_for_asm (insn, "can't find a register in class %qs while "
2081 "reloading %<asm%>",
2082 reg_class_names[rclass]);
2085 error ("unable to find a register to spill in class %qs",
2086 reg_class_names[rclass]);
2090 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2091 debug_reload_to_stream (dump_file);
2093 fatal_insn ("this is the insn:", insn);
2097 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2098 data that is dead in INSN. */
2101 delete_dead_insn (rtx insn)
2103 rtx prev = prev_real_insn (insn);
2106 /* If the previous insn sets a register that dies in our insn, delete it
2108 if (prev && GET_CODE (PATTERN (prev)) == SET
2109 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2110 && reg_mentioned_p (prev_dest, PATTERN (insn))
2111 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2112 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2113 delete_dead_insn (prev);
2115 SET_INSN_DELETED (insn);
2118 /* Modify the home of pseudo-reg I.
2119 The new home is present in reg_renumber[I].
2121 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2122 or it may be -1, meaning there is none or it is not relevant.
2123 This is used so that all pseudos spilled from a given hard reg
2124 can share one stack slot. */
2127 alter_reg (int i, int from_reg, bool dont_share_p)
2129 /* When outputting an inline function, this can happen
2130 for a reg that isn't actually used. */
2131 if (regno_reg_rtx[i] == 0)
2134 /* If the reg got changed to a MEM at rtl-generation time,
2136 if (!REG_P (regno_reg_rtx[i]))
2139 /* Modify the reg-rtx to contain the new hard reg
2140 number or else to contain its pseudo reg number. */
2141 SET_REGNO (regno_reg_rtx[i],
2142 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2144 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2145 allocate a stack slot for it. */
2147 if (reg_renumber[i] < 0
2148 && REG_N_REFS (i) > 0
2149 && reg_equiv_constant[i] == 0
2150 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2151 && reg_equiv_memory_loc[i] == 0)
2154 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2155 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2156 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2157 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2158 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2161 if (ira_conflicts_p)
2163 /* Mark the spill for IRA. */
2164 SET_REGNO_REG_SET (&spilled_pseudos, i);
2166 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2172 /* Each pseudo reg has an inherent size which comes from its own mode,
2173 and a total size which provides room for paradoxical subregs
2174 which refer to the pseudo reg in wider modes.
2176 We can use a slot already allocated if it provides both
2177 enough inherent space and enough total space.
2178 Otherwise, we allocate a new slot, making sure that it has no less
2179 inherent space, and no less total space, then the previous slot. */
2180 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2184 /* No known place to spill from => no slot to reuse. */
2185 x = assign_stack_local (mode, total_size,
2186 min_align > inherent_align
2187 || total_size > inherent_size ? -1 : 0);
2191 /* Cancel the big-endian correction done in assign_stack_local.
2192 Get the address of the beginning of the slot. This is so we
2193 can do a big-endian correction unconditionally below. */
2194 if (BYTES_BIG_ENDIAN)
2196 adjust = inherent_size - total_size;
2199 = adjust_address_nv (x, mode_for_size (total_size
2205 if (! dont_share_p && ira_conflicts_p)
2206 /* Inform IRA about allocation a new stack slot. */
2207 ira_mark_new_stack_slot (stack_slot, i, total_size);
2210 /* Reuse a stack slot if possible. */
2211 else if (spill_stack_slot[from_reg] != 0
2212 && spill_stack_slot_width[from_reg] >= total_size
2213 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2215 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2216 x = spill_stack_slot[from_reg];
2218 /* Allocate a bigger slot. */
2221 /* Compute maximum size needed, both for inherent size
2222 and for total size. */
2225 if (spill_stack_slot[from_reg])
2227 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2229 mode = GET_MODE (spill_stack_slot[from_reg]);
2230 if (spill_stack_slot_width[from_reg] > total_size)
2231 total_size = spill_stack_slot_width[from_reg];
2232 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2233 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2236 /* Make a slot with that size. */
2237 x = assign_stack_local (mode, total_size,
2238 min_align > inherent_align
2239 || total_size > inherent_size ? -1 : 0);
2242 /* Cancel the big-endian correction done in assign_stack_local.
2243 Get the address of the beginning of the slot. This is so we
2244 can do a big-endian correction unconditionally below. */
2245 if (BYTES_BIG_ENDIAN)
2247 adjust = GET_MODE_SIZE (mode) - total_size;
2250 = adjust_address_nv (x, mode_for_size (total_size
2256 spill_stack_slot[from_reg] = stack_slot;
2257 spill_stack_slot_width[from_reg] = total_size;
2260 /* On a big endian machine, the "address" of the slot
2261 is the address of the low part that fits its inherent mode. */
2262 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2263 adjust += (total_size - inherent_size);
2265 /* If we have any adjustment to make, or if the stack slot is the
2266 wrong mode, make a new stack slot. */
2267 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2269 /* Set all of the memory attributes as appropriate for a spill. */
2270 set_mem_attrs_for_spill (x);
2272 /* Save the stack slot for later. */
2273 reg_equiv_memory_loc[i] = x;
2277 /* Mark the slots in regs_ever_live for the hard regs used by
2278 pseudo-reg number REGNO, accessed in MODE. */
2281 mark_home_live_1 (int regno, enum machine_mode mode)
2285 i = reg_renumber[regno];
2288 lim = end_hard_regno (mode, i);
2290 df_set_regs_ever_live(i++, true);
2293 /* Mark the slots in regs_ever_live for the hard regs
2294 used by pseudo-reg number REGNO. */
2297 mark_home_live (int regno)
2299 if (reg_renumber[regno] >= 0)
2300 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2303 /* This function handles the tracking of elimination offsets around branches.
2305 X is a piece of RTL being scanned.
2307 INSN is the insn that it came from, if any.
2309 INITIAL_P is nonzero if we are to set the offset to be the initial
2310 offset and zero if we are setting the offset of the label to be the
2314 set_label_offsets (rtx x, rtx insn, int initial_p)
2316 enum rtx_code code = GET_CODE (x);
2319 struct elim_table *p;
2324 if (LABEL_REF_NONLOCAL_P (x))
2329 /* ... fall through ... */
2332 /* If we know nothing about this label, set the desired offsets. Note
2333 that this sets the offset at a label to be the offset before a label
2334 if we don't know anything about the label. This is not correct for
2335 the label after a BARRIER, but is the best guess we can make. If
2336 we guessed wrong, we will suppress an elimination that might have
2337 been possible had we been able to guess correctly. */
2339 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2341 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2342 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2343 = (initial_p ? reg_eliminate[i].initial_offset
2344 : reg_eliminate[i].offset);
2345 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2348 /* Otherwise, if this is the definition of a label and it is
2349 preceded by a BARRIER, set our offsets to the known offset of
2353 && (tem = prev_nonnote_insn (insn)) != 0
2355 set_offsets_for_label (insn);
2357 /* If neither of the above cases is true, compare each offset
2358 with those previously recorded and suppress any eliminations
2359 where the offsets disagree. */
2361 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2362 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2363 != (initial_p ? reg_eliminate[i].initial_offset
2364 : reg_eliminate[i].offset))
2365 reg_eliminate[i].can_eliminate = 0;
2370 set_label_offsets (PATTERN (insn), insn, initial_p);
2372 /* ... fall through ... */
2376 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2377 to indirectly and hence must have all eliminations at their
2379 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2380 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2381 set_label_offsets (XEXP (tem, 0), insn, 1);
2387 /* Each of the labels in the parallel or address vector must be
2388 at their initial offsets. We want the first field for PARALLEL
2389 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2391 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2392 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2397 /* We only care about setting PC. If the source is not RETURN,
2398 IF_THEN_ELSE, or a label, disable any eliminations not at
2399 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2400 isn't one of those possibilities. For branches to a label,
2401 call ourselves recursively.
2403 Note that this can disable elimination unnecessarily when we have
2404 a non-local goto since it will look like a non-constant jump to
2405 someplace in the current function. This isn't a significant
2406 problem since such jumps will normally be when all elimination
2407 pairs are back to their initial offsets. */
2409 if (SET_DEST (x) != pc_rtx)
2412 switch (GET_CODE (SET_SRC (x)))
2419 set_label_offsets (SET_SRC (x), insn, initial_p);
2423 tem = XEXP (SET_SRC (x), 1);
2424 if (GET_CODE (tem) == LABEL_REF)
2425 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2426 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2429 tem = XEXP (SET_SRC (x), 2);
2430 if (GET_CODE (tem) == LABEL_REF)
2431 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2432 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2440 /* If we reach here, all eliminations must be at their initial
2441 offset because we are doing a jump to a variable address. */
2442 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2443 if (p->offset != p->initial_offset)
2444 p->can_eliminate = 0;
2452 /* Scan X and replace any eliminable registers (such as fp) with a
2453 replacement (such as sp), plus an offset.
2455 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2456 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2457 MEM, we are allowed to replace a sum of a register and the constant zero
2458 with the register, which we cannot do outside a MEM. In addition, we need
2459 to record the fact that a register is referenced outside a MEM.
2461 If INSN is an insn, it is the insn containing X. If we replace a REG
2462 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2463 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2464 the REG is being modified.
2466 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2467 That's used when we eliminate in expressions stored in notes.
2468 This means, do not set ref_outside_mem even if the reference
2471 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2472 replacements done assuming all offsets are at their initial values. If
2473 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2474 encounter, return the actual location so that find_reloads will do
2475 the proper thing. */
2478 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2479 bool may_use_invariant)
2481 enum rtx_code code = GET_CODE (x);
2482 struct elim_table *ep;
2489 if (! current_function_decl)
2512 /* First handle the case where we encounter a bare register that
2513 is eliminable. Replace it with a PLUS. */
2514 if (regno < FIRST_PSEUDO_REGISTER)
2516 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2518 if (ep->from_rtx == x && ep->can_eliminate)
2519 return plus_constant (ep->to_rtx, ep->previous_offset);
2522 else if (reg_renumber && reg_renumber[regno] < 0
2523 && reg_equiv_invariant && reg_equiv_invariant[regno])
2525 if (may_use_invariant)
2526 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2527 mem_mode, insn, true);
2528 /* There exists at least one use of REGNO that cannot be
2529 eliminated. Prevent the defining insn from being deleted. */
2530 reg_equiv_init[regno] = NULL_RTX;
2531 alter_reg (regno, -1, true);
2535 /* You might think handling MINUS in a manner similar to PLUS is a
2536 good idea. It is not. It has been tried multiple times and every
2537 time the change has had to have been reverted.
2539 Other parts of reload know a PLUS is special (gen_reload for example)
2540 and require special code to handle code a reloaded PLUS operand.
2542 Also consider backends where the flags register is clobbered by a
2543 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2544 lea instruction comes to mind). If we try to reload a MINUS, we
2545 may kill the flags register that was holding a useful value.
2547 So, please before trying to handle MINUS, consider reload as a
2548 whole instead of this little section as well as the backend issues. */
2550 /* If this is the sum of an eliminable register and a constant, rework
2552 if (REG_P (XEXP (x, 0))
2553 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2554 && CONSTANT_P (XEXP (x, 1)))
2556 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2558 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2560 /* The only time we want to replace a PLUS with a REG (this
2561 occurs when the constant operand of the PLUS is the negative
2562 of the offset) is when we are inside a MEM. We won't want
2563 to do so at other times because that would change the
2564 structure of the insn in a way that reload can't handle.
2565 We special-case the commonest situation in
2566 eliminate_regs_in_insn, so just replace a PLUS with a
2567 PLUS here, unless inside a MEM. */
2568 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2569 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2572 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2573 plus_constant (XEXP (x, 1),
2574 ep->previous_offset));
2577 /* If the register is not eliminable, we are done since the other
2578 operand is a constant. */
2582 /* If this is part of an address, we want to bring any constant to the
2583 outermost PLUS. We will do this by doing register replacement in
2584 our operands and seeing if a constant shows up in one of them.
2586 Note that there is no risk of modifying the structure of the insn,
2587 since we only get called for its operands, thus we are either
2588 modifying the address inside a MEM, or something like an address
2589 operand of a load-address insn. */
2592 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2593 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2595 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2597 /* If one side is a PLUS and the other side is a pseudo that
2598 didn't get a hard register but has a reg_equiv_constant,
2599 we must replace the constant here since it may no longer
2600 be in the position of any operand. */
2601 if (GET_CODE (new0) == PLUS && REG_P (new1)
2602 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2603 && reg_renumber[REGNO (new1)] < 0
2604 && reg_equiv_constant != 0
2605 && reg_equiv_constant[REGNO (new1)] != 0)
2606 new1 = reg_equiv_constant[REGNO (new1)];
2607 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2608 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2609 && reg_renumber[REGNO (new0)] < 0
2610 && reg_equiv_constant[REGNO (new0)] != 0)
2611 new0 = reg_equiv_constant[REGNO (new0)];
2613 new_rtx = form_sum (new0, new1);
2615 /* As above, if we are not inside a MEM we do not want to
2616 turn a PLUS into something else. We might try to do so here
2617 for an addition of 0 if we aren't optimizing. */
2618 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2619 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2627 /* If this is the product of an eliminable register and a
2628 constant, apply the distribute law and move the constant out
2629 so that we have (plus (mult ..) ..). This is needed in order
2630 to keep load-address insns valid. This case is pathological.
2631 We ignore the possibility of overflow here. */
2632 if (REG_P (XEXP (x, 0))
2633 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2634 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2635 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2637 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2640 /* Refs inside notes don't count for this purpose. */
2641 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2642 || GET_CODE (insn) == INSN_LIST)))
2643 ep->ref_outside_mem = 1;
2646 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2647 ep->previous_offset * INTVAL (XEXP (x, 1)));
2650 /* ... fall through ... */
2654 /* See comments before PLUS about handling MINUS. */
2656 case DIV: case UDIV:
2657 case MOD: case UMOD:
2658 case AND: case IOR: case XOR:
2659 case ROTATERT: case ROTATE:
2660 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2662 case GE: case GT: case GEU: case GTU:
2663 case LE: case LT: case LEU: case LTU:
2665 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2666 rtx new1 = XEXP (x, 1)
2667 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2669 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2670 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2675 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2678 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2679 if (new_rtx != XEXP (x, 0))
2681 /* If this is a REG_DEAD note, it is not valid anymore.
2682 Using the eliminated version could result in creating a
2683 REG_DEAD note for the stack or frame pointer. */
2684 if (REG_NOTE_KIND (x) == REG_DEAD)
2686 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2689 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2693 /* ... fall through ... */
2696 /* Now do eliminations in the rest of the chain. If this was
2697 an EXPR_LIST, this might result in allocating more memory than is
2698 strictly needed, but it simplifies the code. */
2701 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2702 if (new_rtx != XEXP (x, 1))
2704 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2712 /* We do not support elimination of a register that is modified.
2713 elimination_effects has already make sure that this does not
2719 /* We do not support elimination of a register that is modified.
2720 elimination_effects has already make sure that this does not
2721 happen. The only remaining case we need to consider here is
2722 that the increment value may be an eliminable register. */
2723 if (GET_CODE (XEXP (x, 1)) == PLUS
2724 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2726 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2729 if (new_rtx != XEXP (XEXP (x, 1), 1))
2730 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2731 gen_rtx_PLUS (GET_MODE (x),
2732 XEXP (x, 0), new_rtx));
2736 case STRICT_LOW_PART:
2738 case SIGN_EXTEND: case ZERO_EXTEND:
2739 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2740 case FLOAT: case FIX:
2741 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2750 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2751 if (new_rtx != XEXP (x, 0))
2752 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2756 /* Similar to above processing, but preserve SUBREG_BYTE.
2757 Convert (subreg (mem)) to (mem) if not paradoxical.
2758 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2759 pseudo didn't get a hard reg, we must replace this with the
2760 eliminated version of the memory location because push_reload
2761 may do the replacement in certain circumstances. */
2762 if (REG_P (SUBREG_REG (x))
2763 && (GET_MODE_SIZE (GET_MODE (x))
2764 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2765 && reg_equiv_memory_loc != 0
2766 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2768 new_rtx = SUBREG_REG (x);
2771 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2773 if (new_rtx != SUBREG_REG (x))
2775 int x_size = GET_MODE_SIZE (GET_MODE (x));
2776 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2779 && ((x_size < new_size
2780 #ifdef WORD_REGISTER_OPERATIONS
2781 /* On these machines, combine can create rtl of the form
2782 (set (subreg:m1 (reg:m2 R) 0) ...)
2783 where m1 < m2, and expects something interesting to
2784 happen to the entire word. Moreover, it will use the
2785 (reg:m2 R) later, expecting all bits to be preserved.
2786 So if the number of words is the same, preserve the
2787 subreg so that push_reload can see it. */
2788 && ! ((x_size - 1) / UNITS_PER_WORD
2789 == (new_size -1 ) / UNITS_PER_WORD)
2792 || x_size == new_size)
2794 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2796 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2802 /* Our only special processing is to pass the mode of the MEM to our
2803 recursive call and copy the flags. While we are here, handle this
2804 case more efficiently. */
2806 replace_equiv_address_nv (x,
2807 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2811 /* Handle insn_list USE that a call to a pure function may generate. */
2812 new_rtx = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2813 if (new_rtx != XEXP (x, 0))
2814 return gen_rtx_USE (GET_MODE (x), new_rtx);
2826 /* Process each of our operands recursively. If any have changed, make a
2828 fmt = GET_RTX_FORMAT (code);
2829 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2833 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2834 if (new_rtx != XEXP (x, i) && ! copied)
2836 x = shallow_copy_rtx (x);
2839 XEXP (x, i) = new_rtx;
2841 else if (*fmt == 'E')
2844 for (j = 0; j < XVECLEN (x, i); j++)
2846 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2847 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2849 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2853 x = shallow_copy_rtx (x);
2856 XVEC (x, i) = new_v;
2859 XVECEXP (x, i, j) = new_rtx;
2868 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2870 return eliminate_regs_1 (x, mem_mode, insn, false);
2873 /* Scan rtx X for modifications of elimination target registers. Update
2874 the table of eliminables to reflect the changed state. MEM_MODE is
2875 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2878 elimination_effects (rtx x, enum machine_mode mem_mode)
2880 enum rtx_code code = GET_CODE (x);
2881 struct elim_table *ep;
2906 /* First handle the case where we encounter a bare register that
2907 is eliminable. Replace it with a PLUS. */
2908 if (regno < FIRST_PSEUDO_REGISTER)
2910 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2912 if (ep->from_rtx == x && ep->can_eliminate)
2915 ep->ref_outside_mem = 1;
2920 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2921 && reg_equiv_constant[regno]
2922 && ! function_invariant_p (reg_equiv_constant[regno]))
2923 elimination_effects (reg_equiv_constant[regno], mem_mode);
2932 /* If we modify the source of an elimination rule, disable it. */
2933 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2934 if (ep->from_rtx == XEXP (x, 0))
2935 ep->can_eliminate = 0;
2937 /* If we modify the target of an elimination rule by adding a constant,
2938 update its offset. If we modify the target in any other way, we'll
2939 have to disable the rule as well. */
2940 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2941 if (ep->to_rtx == XEXP (x, 0))
2943 int size = GET_MODE_SIZE (mem_mode);
2945 /* If more bytes than MEM_MODE are pushed, account for them. */
2946 #ifdef PUSH_ROUNDING
2947 if (ep->to_rtx == stack_pointer_rtx)
2948 size = PUSH_ROUNDING (size);
2950 if (code == PRE_DEC || code == POST_DEC)
2952 else if (code == PRE_INC || code == POST_INC)
2954 else if (code == PRE_MODIFY || code == POST_MODIFY)
2956 if (GET_CODE (XEXP (x, 1)) == PLUS
2957 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2958 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2959 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2961 ep->can_eliminate = 0;
2965 /* These two aren't unary operators. */
2966 if (code == POST_MODIFY || code == PRE_MODIFY)
2969 /* Fall through to generic unary operation case. */
2970 case STRICT_LOW_PART:
2972 case SIGN_EXTEND: case ZERO_EXTEND:
2973 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2974 case FLOAT: case FIX:
2975 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2984 elimination_effects (XEXP (x, 0), mem_mode);
2988 if (REG_P (SUBREG_REG (x))
2989 && (GET_MODE_SIZE (GET_MODE (x))
2990 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2991 && reg_equiv_memory_loc != 0
2992 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2995 elimination_effects (SUBREG_REG (x), mem_mode);
2999 /* If using a register that is the source of an eliminate we still
3000 think can be performed, note it cannot be performed since we don't
3001 know how this register is used. */
3002 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3003 if (ep->from_rtx == XEXP (x, 0))
3004 ep->can_eliminate = 0;
3006 elimination_effects (XEXP (x, 0), mem_mode);
3010 /* If clobbering a register that is the replacement register for an
3011 elimination we still think can be performed, note that it cannot
3012 be performed. Otherwise, we need not be concerned about it. */
3013 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3014 if (ep->to_rtx == XEXP (x, 0))
3015 ep->can_eliminate = 0;
3017 elimination_effects (XEXP (x, 0), mem_mode);
3021 /* Check for setting a register that we know about. */
3022 if (REG_P (SET_DEST (x)))
3024 /* See if this is setting the replacement register for an
3027 If DEST is the hard frame pointer, we do nothing because we
3028 assume that all assignments to the frame pointer are for
3029 non-local gotos and are being done at a time when they are valid
3030 and do not disturb anything else. Some machines want to
3031 eliminate a fake argument pointer (or even a fake frame pointer)
3032 with either the real frame or the stack pointer. Assignments to
3033 the hard frame pointer must not prevent this elimination. */
3035 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3037 if (ep->to_rtx == SET_DEST (x)
3038 && SET_DEST (x) != hard_frame_pointer_rtx)
3040 /* If it is being incremented, adjust the offset. Otherwise,
3041 this elimination can't be done. */
3042 rtx src = SET_SRC (x);
3044 if (GET_CODE (src) == PLUS
3045 && XEXP (src, 0) == SET_DEST (x)
3046 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3047 ep->offset -= INTVAL (XEXP (src, 1));
3049 ep->can_eliminate = 0;
3053 elimination_effects (SET_DEST (x), 0);
3054 elimination_effects (SET_SRC (x), 0);
3058 /* Our only special processing is to pass the mode of the MEM to our
3060 elimination_effects (XEXP (x, 0), GET_MODE (x));
3067 fmt = GET_RTX_FORMAT (code);
3068 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3071 elimination_effects (XEXP (x, i), mem_mode);
3072 else if (*fmt == 'E')
3073 for (j = 0; j < XVECLEN (x, i); j++)
3074 elimination_effects (XVECEXP (x, i, j), mem_mode);
3078 /* Descend through rtx X and verify that no references to eliminable registers
3079 remain. If any do remain, mark the involved register as not
3083 check_eliminable_occurrences (rtx x)
3092 code = GET_CODE (x);
3094 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3096 struct elim_table *ep;
3098 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3099 if (ep->from_rtx == x)
3100 ep->can_eliminate = 0;
3104 fmt = GET_RTX_FORMAT (code);
3105 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3108 check_eliminable_occurrences (XEXP (x, i));
3109 else if (*fmt == 'E')
3112 for (j = 0; j < XVECLEN (x, i); j++)
3113 check_eliminable_occurrences (XVECEXP (x, i, j));
3118 /* Scan INSN and eliminate all eliminable registers in it.
3120 If REPLACE is nonzero, do the replacement destructively. Also
3121 delete the insn as dead it if it is setting an eliminable register.
3123 If REPLACE is zero, do all our allocations in reload_obstack.
3125 If no eliminations were done and this insn doesn't require any elimination
3126 processing (these are not identical conditions: it might be updating sp,
3127 but not referencing fp; this needs to be seen during reload_as_needed so
3128 that the offset between fp and sp can be taken into consideration), zero
3129 is returned. Otherwise, 1 is returned. */
3132 eliminate_regs_in_insn (rtx insn, int replace)
3134 int icode = recog_memoized (insn);
3135 rtx old_body = PATTERN (insn);
3136 int insn_is_asm = asm_noperands (old_body) >= 0;
3137 rtx old_set = single_set (insn);
3141 rtx substed_operand[MAX_RECOG_OPERANDS];
3142 rtx orig_operand[MAX_RECOG_OPERANDS];
3143 struct elim_table *ep;
3144 rtx plus_src, plus_cst_src;
3146 if (! insn_is_asm && icode < 0)
3148 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3149 || GET_CODE (PATTERN (insn)) == CLOBBER
3150 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3151 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3152 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3156 if (old_set != 0 && REG_P (SET_DEST (old_set))
3157 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3159 /* Check for setting an eliminable register. */
3160 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3161 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3163 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3164 /* If this is setting the frame pointer register to the
3165 hardware frame pointer register and this is an elimination
3166 that will be done (tested above), this insn is really
3167 adjusting the frame pointer downward to compensate for
3168 the adjustment done before a nonlocal goto. */
3169 if (ep->from == FRAME_POINTER_REGNUM
3170 && ep->to == HARD_FRAME_POINTER_REGNUM)
3172 rtx base = SET_SRC (old_set);
3173 rtx base_insn = insn;
3174 HOST_WIDE_INT offset = 0;
3176 while (base != ep->to_rtx)
3178 rtx prev_insn, prev_set;
3180 if (GET_CODE (base) == PLUS
3181 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3183 offset += INTVAL (XEXP (base, 1));
3184 base = XEXP (base, 0);
3186 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3187 && (prev_set = single_set (prev_insn)) != 0
3188 && rtx_equal_p (SET_DEST (prev_set), base))
3190 base = SET_SRC (prev_set);
3191 base_insn = prev_insn;
3197 if (base == ep->to_rtx)
3200 = plus_constant (ep->to_rtx, offset - ep->offset);
3202 new_body = old_body;
3205 new_body = copy_insn (old_body);
3206 if (REG_NOTES (insn))
3207 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3209 PATTERN (insn) = new_body;
3210 old_set = single_set (insn);
3212 /* First see if this insn remains valid when we
3213 make the change. If not, keep the INSN_CODE
3214 the same and let reload fit it up. */
3215 validate_change (insn, &SET_SRC (old_set), src, 1);
3216 validate_change (insn, &SET_DEST (old_set),
3218 if (! apply_change_group ())
3220 SET_SRC (old_set) = src;
3221 SET_DEST (old_set) = ep->to_rtx;
3230 /* In this case this insn isn't serving a useful purpose. We
3231 will delete it in reload_as_needed once we know that this
3232 elimination is, in fact, being done.
3234 If REPLACE isn't set, we can't delete this insn, but needn't
3235 process it since it won't be used unless something changes. */
3238 delete_dead_insn (insn);
3246 /* We allow one special case which happens to work on all machines we
3247 currently support: a single set with the source or a REG_EQUAL
3248 note being a PLUS of an eliminable register and a constant. */
3249 plus_src = plus_cst_src = 0;
3250 if (old_set && REG_P (SET_DEST (old_set)))
3252 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3253 plus_src = SET_SRC (old_set);
3254 /* First see if the source is of the form (plus (...) CST). */
3256 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3257 plus_cst_src = plus_src;
3258 else if (REG_P (SET_SRC (old_set))
3261 /* Otherwise, see if we have a REG_EQUAL note of the form
3262 (plus (...) CST). */
3264 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3266 if ((REG_NOTE_KIND (links) == REG_EQUAL
3267 || REG_NOTE_KIND (links) == REG_EQUIV)
3268 && GET_CODE (XEXP (links, 0)) == PLUS
3269 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3271 plus_cst_src = XEXP (links, 0);
3277 /* Check that the first operand of the PLUS is a hard reg or
3278 the lowpart subreg of one. */
3281 rtx reg = XEXP (plus_cst_src, 0);
3282 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3283 reg = SUBREG_REG (reg);
3285 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3291 rtx reg = XEXP (plus_cst_src, 0);
3292 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3294 if (GET_CODE (reg) == SUBREG)
3295 reg = SUBREG_REG (reg);
3297 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3298 if (ep->from_rtx == reg && ep->can_eliminate)
3300 rtx to_rtx = ep->to_rtx;
3301 offset += ep->offset;
3302 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3304 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3305 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3307 /* If we have a nonzero offset, and the source is already
3308 a simple REG, the following transformation would
3309 increase the cost of the insn by replacing a simple REG
3310 with (plus (reg sp) CST). So try only when we already
3311 had a PLUS before. */
3312 if (offset == 0 || plus_src)
3314 rtx new_src = plus_constant (to_rtx, offset);
3316 new_body = old_body;
3319 new_body = copy_insn (old_body);
3320 if (REG_NOTES (insn))
3321 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3323 PATTERN (insn) = new_body;
3324 old_set = single_set (insn);
3326 /* First see if this insn remains valid when we make the
3327 change. If not, try to replace the whole pattern with
3328 a simple set (this may help if the original insn was a
3329 PARALLEL that was only recognized as single_set due to
3330 REG_UNUSED notes). If this isn't valid either, keep
3331 the INSN_CODE the same and let reload fix it up. */
3332 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3334 rtx new_pat = gen_rtx_SET (VOIDmode,
3335 SET_DEST (old_set), new_src);
3337 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3338 SET_SRC (old_set) = new_src;
3345 /* This can't have an effect on elimination offsets, so skip right
3351 /* Determine the effects of this insn on elimination offsets. */
3352 elimination_effects (old_body, 0);
3354 /* Eliminate all eliminable registers occurring in operands that
3355 can be handled by reload. */
3356 extract_insn (insn);
3357 for (i = 0; i < recog_data.n_operands; i++)
3359 orig_operand[i] = recog_data.operand[i];
3360 substed_operand[i] = recog_data.operand[i];
3362 /* For an asm statement, every operand is eliminable. */
3363 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3365 bool is_set_src, in_plus;
3367 /* Check for setting a register that we know about. */
3368 if (recog_data.operand_type[i] != OP_IN
3369 && REG_P (orig_operand[i]))
3371 /* If we are assigning to a register that can be eliminated, it
3372 must be as part of a PARALLEL, since the code above handles
3373 single SETs. We must indicate that we can no longer
3374 eliminate this reg. */
3375 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3377 if (ep->from_rtx == orig_operand[i])
3378 ep->can_eliminate = 0;
3381 /* Companion to the above plus substitution, we can allow
3382 invariants as the source of a plain move. */
3384 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3388 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3389 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3393 = eliminate_regs_1 (recog_data.operand[i], 0,
3394 replace ? insn : NULL_RTX,
3395 is_set_src || in_plus);
3396 if (substed_operand[i] != orig_operand[i])
3398 /* Terminate the search in check_eliminable_occurrences at
3400 *recog_data.operand_loc[i] = 0;
3402 /* If an output operand changed from a REG to a MEM and INSN is an
3403 insn, write a CLOBBER insn. */
3404 if (recog_data.operand_type[i] != OP_IN
3405 && REG_P (orig_operand[i])
3406 && MEM_P (substed_operand[i])
3408 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3412 for (i = 0; i < recog_data.n_dups; i++)
3413 *recog_data.dup_loc[i]
3414 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3416 /* If any eliminable remain, they aren't eliminable anymore. */
3417 check_eliminable_occurrences (old_body);
3419 /* Substitute the operands; the new values are in the substed_operand
3421 for (i = 0; i < recog_data.n_operands; i++)
3422 *recog_data.operand_loc[i] = substed_operand[i];
3423 for (i = 0; i < recog_data.n_dups; i++)
3424 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3426 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3427 re-recognize the insn. We do this in case we had a simple addition
3428 but now can do this as a load-address. This saves an insn in this
3430 If re-recognition fails, the old insn code number will still be used,
3431 and some register operands may have changed into PLUS expressions.
3432 These will be handled by find_reloads by loading them into a register
3437 /* If we aren't replacing things permanently and we changed something,
3438 make another copy to ensure that all the RTL is new. Otherwise
3439 things can go wrong if find_reload swaps commutative operands
3440 and one is inside RTL that has been copied while the other is not. */
3441 new_body = old_body;
3444 new_body = copy_insn (old_body);
3445 if (REG_NOTES (insn))
3446 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3448 PATTERN (insn) = new_body;
3450 /* If we had a move insn but now we don't, rerecognize it. This will
3451 cause spurious re-recognition if the old move had a PARALLEL since
3452 the new one still will, but we can't call single_set without
3453 having put NEW_BODY into the insn and the re-recognition won't
3454 hurt in this rare case. */
3455 /* ??? Why this huge if statement - why don't we just rerecognize the
3459 && ((REG_P (SET_SRC (old_set))
3460 && (GET_CODE (new_body) != SET
3461 || !REG_P (SET_SRC (new_body))))
3462 /* If this was a load from or store to memory, compare
3463 the MEM in recog_data.operand to the one in the insn.
3464 If they are not equal, then rerecognize the insn. */
3466 && ((MEM_P (SET_SRC (old_set))
3467 && SET_SRC (old_set) != recog_data.operand[1])
3468 || (MEM_P (SET_DEST (old_set))
3469 && SET_DEST (old_set) != recog_data.operand[0])))
3470 /* If this was an add insn before, rerecognize. */
3471 || GET_CODE (SET_SRC (old_set)) == PLUS))
3473 int new_icode = recog (PATTERN (insn), insn, 0);
3475 INSN_CODE (insn) = new_icode;
3479 /* Restore the old body. If there were any changes to it, we made a copy
3480 of it while the changes were still in place, so we'll correctly return
3481 a modified insn below. */
3484 /* Restore the old body. */
3485 for (i = 0; i < recog_data.n_operands; i++)
3486 *recog_data.operand_loc[i] = orig_operand[i];
3487 for (i = 0; i < recog_data.n_dups; i++)
3488 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3491 /* Update all elimination pairs to reflect the status after the current
3492 insn. The changes we make were determined by the earlier call to
3493 elimination_effects.
3495 We also detect cases where register elimination cannot be done,
3496 namely, if a register would be both changed and referenced outside a MEM
3497 in the resulting insn since such an insn is often undefined and, even if
3498 not, we cannot know what meaning will be given to it. Note that it is
3499 valid to have a register used in an address in an insn that changes it
3500 (presumably with a pre- or post-increment or decrement).
3502 If anything changes, return nonzero. */
3504 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3506 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3507 ep->can_eliminate = 0;
3509 ep->ref_outside_mem = 0;
3511 if (ep->previous_offset != ep->offset)
3516 /* If we changed something, perform elimination in REG_NOTES. This is
3517 needed even when REPLACE is zero because a REG_DEAD note might refer
3518 to a register that we eliminate and could cause a different number
3519 of spill registers to be needed in the final reload pass than in
3521 if (val && REG_NOTES (insn) != 0)
3523 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3528 /* Loop through all elimination pairs.
3529 Recalculate the number not at initial offset.
3531 Compute the maximum offset (minimum offset if the stack does not
3532 grow downward) for each elimination pair. */
3535 update_eliminable_offsets (void)
3537 struct elim_table *ep;
3539 num_not_at_initial_offset = 0;
3540 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3542 ep->previous_offset = ep->offset;
3543 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3544 num_not_at_initial_offset++;
3548 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3549 replacement we currently believe is valid, mark it as not eliminable if X
3550 modifies DEST in any way other than by adding a constant integer to it.
3552 If DEST is the frame pointer, we do nothing because we assume that
3553 all assignments to the hard frame pointer are nonlocal gotos and are being
3554 done at a time when they are valid and do not disturb anything else.
3555 Some machines want to eliminate a fake argument pointer with either the
3556 frame or stack pointer. Assignments to the hard frame pointer must not
3557 prevent this elimination.
3559 Called via note_stores from reload before starting its passes to scan
3560 the insns of the function. */
3563 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3567 /* A SUBREG of a hard register here is just changing its mode. We should
3568 not see a SUBREG of an eliminable hard register, but check just in
3570 if (GET_CODE (dest) == SUBREG)
3571 dest = SUBREG_REG (dest);
3573 if (dest == hard_frame_pointer_rtx)
3576 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3577 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3578 && (GET_CODE (x) != SET
3579 || GET_CODE (SET_SRC (x)) != PLUS
3580 || XEXP (SET_SRC (x), 0) != dest
3581 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3583 reg_eliminate[i].can_eliminate_previous
3584 = reg_eliminate[i].can_eliminate = 0;
3589 /* Verify that the initial elimination offsets did not change since the
3590 last call to set_initial_elim_offsets. This is used to catch cases
3591 where something illegal happened during reload_as_needed that could
3592 cause incorrect code to be generated if we did not check for it. */
3595 verify_initial_elim_offsets (void)
3599 if (!num_eliminable)
3602 #ifdef ELIMINABLE_REGS
3604 struct elim_table *ep;
3606 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3608 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3609 if (t != ep->initial_offset)
3614 INITIAL_FRAME_POINTER_OFFSET (t);
3615 if (t != reg_eliminate[0].initial_offset)
3622 /* Reset all offsets on eliminable registers to their initial values. */
3625 set_initial_elim_offsets (void)
3627 struct elim_table *ep = reg_eliminate;
3629 #ifdef ELIMINABLE_REGS
3630 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3632 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3633 ep->previous_offset = ep->offset = ep->initial_offset;
3636 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3637 ep->previous_offset = ep->offset = ep->initial_offset;
3640 num_not_at_initial_offset = 0;
3643 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3646 set_initial_eh_label_offset (rtx label)
3648 set_label_offsets (label, NULL_RTX, 1);
3651 /* Initialize the known label offsets.
3652 Set a known offset for each forced label to be at the initial offset
3653 of each elimination. We do this because we assume that all
3654 computed jumps occur from a location where each elimination is
3655 at its initial offset.
3656 For all other labels, show that we don't know the offsets. */
3659 set_initial_label_offsets (void)
3662 memset (offsets_known_at, 0, num_labels);
3664 for (x = forced_labels; x; x = XEXP (x, 1))
3666 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3668 for_each_eh_label (set_initial_eh_label_offset);
3671 /* Set all elimination offsets to the known values for the code label given
3675 set_offsets_for_label (rtx insn)
3678 int label_nr = CODE_LABEL_NUMBER (insn);
3679 struct elim_table *ep;
3681 num_not_at_initial_offset = 0;
3682 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3684 ep->offset = ep->previous_offset
3685 = offsets_at[label_nr - first_label_num][i];
3686 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3687 num_not_at_initial_offset++;
3691 /* See if anything that happened changes which eliminations are valid.
3692 For example, on the SPARC, whether or not the frame pointer can
3693 be eliminated can depend on what registers have been used. We need
3694 not check some conditions again (such as flag_omit_frame_pointer)
3695 since they can't have changed. */
3698 update_eliminables (HARD_REG_SET *pset)
3700 int previous_frame_pointer_needed = frame_pointer_needed;
3701 struct elim_table *ep;
3703 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3704 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3705 #ifdef ELIMINABLE_REGS
3706 || ! CAN_ELIMINATE (ep->from, ep->to)
3709 ep->can_eliminate = 0;
3711 /* Look for the case where we have discovered that we can't replace
3712 register A with register B and that means that we will now be
3713 trying to replace register A with register C. This means we can
3714 no longer replace register C with register B and we need to disable
3715 such an elimination, if it exists. This occurs often with A == ap,
3716 B == sp, and C == fp. */
3718 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3720 struct elim_table *op;
3723 if (! ep->can_eliminate && ep->can_eliminate_previous)
3725 /* Find the current elimination for ep->from, if there is a
3727 for (op = reg_eliminate;
3728 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3729 if (op->from == ep->from && op->can_eliminate)
3735 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3737 for (op = reg_eliminate;
3738 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3739 if (op->from == new_to && op->to == ep->to)
3740 op->can_eliminate = 0;
3744 /* See if any registers that we thought we could eliminate the previous
3745 time are no longer eliminable. If so, something has changed and we
3746 must spill the register. Also, recompute the number of eliminable
3747 registers and see if the frame pointer is needed; it is if there is
3748 no elimination of the frame pointer that we can perform. */
3750 frame_pointer_needed = 1;
3751 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3753 if (ep->can_eliminate
3754 && ep->from == FRAME_POINTER_REGNUM
3755 && ep->to != HARD_FRAME_POINTER_REGNUM
3756 && (! SUPPORTS_STACK_ALIGNMENT
3757 || ! crtl->stack_realign_needed))
3758 frame_pointer_needed = 0;
3760 if (! ep->can_eliminate && ep->can_eliminate_previous)
3762 ep->can_eliminate_previous = 0;
3763 SET_HARD_REG_BIT (*pset, ep->from);
3768 /* If we didn't need a frame pointer last time, but we do now, spill
3769 the hard frame pointer. */
3770 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3771 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3774 /* Return true if X is used as the target register of an elimination. */
3777 elimination_target_reg_p (rtx x)
3779 struct elim_table *ep;
3781 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3782 if (ep->to_rtx == x && ep->can_eliminate)
3788 /* Initialize the table of registers to eliminate.
3789 Pre-condition: global flag frame_pointer_needed has been set before
3790 calling this function. */
3793 init_elim_table (void)
3795 struct elim_table *ep;
3796 #ifdef ELIMINABLE_REGS
3797 const struct elim_table_1 *ep1;
3801 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3805 #ifdef ELIMINABLE_REGS
3806 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3807 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3809 ep->from = ep1->from;
3811 ep->can_eliminate = ep->can_eliminate_previous
3812 = (CAN_ELIMINATE (ep->from, ep->to)
3813 && ! (ep->to == STACK_POINTER_REGNUM
3814 && frame_pointer_needed
3815 && (! SUPPORTS_STACK_ALIGNMENT
3816 || ! stack_realign_fp)));
3819 reg_eliminate[0].from = reg_eliminate_1[0].from;
3820 reg_eliminate[0].to = reg_eliminate_1[0].to;
3821 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3822 = ! frame_pointer_needed;
3825 /* Count the number of eliminable registers and build the FROM and TO
3826 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3827 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3828 We depend on this. */
3829 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3831 num_eliminable += ep->can_eliminate;
3832 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3833 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3837 /* Kick all pseudos out of hard register REGNO.
3839 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3840 because we found we can't eliminate some register. In the case, no pseudos
3841 are allowed to be in the register, even if they are only in a block that
3842 doesn't require spill registers, unlike the case when we are spilling this
3843 hard reg to produce another spill register.
3845 Return nonzero if any pseudos needed to be kicked out. */
3848 spill_hard_reg (unsigned int regno, int cant_eliminate)
3854 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3855 df_set_regs_ever_live (regno, true);
3858 /* Spill every pseudo reg that was allocated to this reg
3859 or to something that overlaps this reg. */
3861 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3862 if (reg_renumber[i] >= 0
3863 && (unsigned int) reg_renumber[i] <= regno
3864 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3865 SET_REGNO_REG_SET (&spilled_pseudos, i);
3868 /* After find_reload_regs has been run for all insn that need reloads,
3869 and/or spill_hard_regs was called, this function is used to actually
3870 spill pseudo registers and try to reallocate them. It also sets up the
3871 spill_regs array for use by choose_reload_regs. */
3874 finish_spills (int global)
3876 struct insn_chain *chain;
3877 int something_changed = 0;
3879 reg_set_iterator rsi;
3881 /* Build the spill_regs array for the function. */
3882 /* If there are some registers still to eliminate and one of the spill regs
3883 wasn't ever used before, additional stack space may have to be
3884 allocated to store this register. Thus, we may have changed the offset
3885 between the stack and frame pointers, so mark that something has changed.
3887 One might think that we need only set VAL to 1 if this is a call-used
3888 register. However, the set of registers that must be saved by the
3889 prologue is not identical to the call-used set. For example, the
3890 register used by the call insn for the return PC is a call-used register,
3891 but must be saved by the prologue. */
3894 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3895 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3897 spill_reg_order[i] = n_spills;
3898 spill_regs[n_spills++] = i;
3899 if (num_eliminable && ! df_regs_ever_live_p (i))
3900 something_changed = 1;
3901 df_set_regs_ever_live (i, true);
3904 spill_reg_order[i] = -1;
3906 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3907 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3909 /* Record the current hard register the pseudo is allocated to
3910 in pseudo_previous_regs so we avoid reallocating it to the
3911 same hard reg in a later pass. */
3912 gcc_assert (reg_renumber[i] >= 0);
3914 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3915 /* Mark it as no longer having a hard register home. */
3916 reg_renumber[i] = -1;
3917 if (ira_conflicts_p)
3918 /* Inform IRA about the change. */
3919 ira_mark_allocation_change (i);
3920 /* We will need to scan everything again. */
3921 something_changed = 1;
3924 /* Retry global register allocation if possible. */
3925 if (global && ira_conflicts_p)
3929 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3930 /* For every insn that needs reloads, set the registers used as spill
3931 regs in pseudo_forbidden_regs for every pseudo live across the
3933 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3935 EXECUTE_IF_SET_IN_REG_SET
3936 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3938 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3939 chain->used_spill_regs);
3941 EXECUTE_IF_SET_IN_REG_SET
3942 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3944 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3945 chain->used_spill_regs);
3949 /* Retry allocating the pseudos spilled in IRA and the
3950 reload. For each reg, merge the various reg sets that
3951 indicate which hard regs can't be used, and call
3952 ira_reassign_pseudos. */
3953 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
3954 if (reg_old_renumber[i] != reg_renumber[i])
3956 if (reg_renumber[i] < 0)
3957 temp_pseudo_reg_arr[n++] = i;
3959 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3961 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
3962 bad_spill_regs_global,
3963 pseudo_forbidden_regs, pseudo_previous_regs,
3965 something_changed = 1;
3967 /* Fix up the register information in the insn chain.
3968 This involves deleting those of the spilled pseudos which did not get
3969 a new hard register home from the live_{before,after} sets. */
3970 for (chain = reload_insn_chain; chain; chain = chain->next)
3972 HARD_REG_SET used_by_pseudos;
3973 HARD_REG_SET used_by_pseudos2;
3975 if (! ira_conflicts_p)
3977 /* Don't do it for IRA because IRA and the reload still can
3978 assign hard registers to the spilled pseudos on next
3979 reload iterations. */
3980 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3981 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3983 /* Mark any unallocated hard regs as available for spills. That
3984 makes inheritance work somewhat better. */
3985 if (chain->need_reload)
3987 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3988 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3989 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3991 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3992 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3993 /* Value of chain->used_spill_regs from previous iteration
3994 may be not included in the value calculated here because
3995 of possible removing caller-saves insns (see function
3996 delete_caller_save_insns. */
3997 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3998 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4002 CLEAR_REG_SET (&changed_allocation_pseudos);
4003 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4004 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4006 int regno = reg_renumber[i];
4007 if (reg_old_renumber[i] == regno)
4010 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4012 alter_reg (i, reg_old_renumber[i], false);
4013 reg_old_renumber[i] = regno;
4017 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4019 fprintf (dump_file, " Register %d now in %d.\n\n",
4020 i, reg_renumber[i]);
4024 return something_changed;
4027 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4030 scan_paradoxical_subregs (rtx x)
4034 enum rtx_code code = GET_CODE (x);
4045 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4053 if (REG_P (SUBREG_REG (x))
4054 && (GET_MODE_SIZE (GET_MODE (x))
4055 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4057 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4058 = GET_MODE_SIZE (GET_MODE (x));
4059 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4067 fmt = GET_RTX_FORMAT (code);
4068 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4071 scan_paradoxical_subregs (XEXP (x, i));
4072 else if (fmt[i] == 'E')
4075 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4076 scan_paradoxical_subregs (XVECEXP (x, i, j));
4081 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4082 examine all of the reload insns between PREV and NEXT exclusive, and
4083 annotate all that may trap. */
4086 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4088 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4089 unsigned int trap_count;
4095 if (may_trap_p (PATTERN (insn)))
4099 remove_note (insn, note);
4103 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4104 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4107 add_reg_note (i, REG_EH_REGION, XEXP (note, 0));
4111 /* Reload pseudo-registers into hard regs around each insn as needed.
4112 Additional register load insns are output before the insn that needs it
4113 and perhaps store insns after insns that modify the reloaded pseudo reg.
4115 reg_last_reload_reg and reg_reloaded_contents keep track of
4116 which registers are already available in reload registers.
4117 We update these for the reloads that we perform,
4118 as the insns are scanned. */
4121 reload_as_needed (int live_known)
4123 struct insn_chain *chain;
4124 #if defined (AUTO_INC_DEC)
4129 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4130 memset (spill_reg_store, 0, sizeof spill_reg_store);
4131 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4132 INIT_REG_SET (®_has_output_reload);
4133 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4134 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4136 set_initial_elim_offsets ();
4138 for (chain = reload_insn_chain; chain; chain = chain->next)
4141 rtx insn = chain->insn;
4142 rtx old_next = NEXT_INSN (insn);
4144 rtx old_prev = PREV_INSN (insn);
4147 /* If we pass a label, copy the offsets from the label information
4148 into the current offsets of each elimination. */
4150 set_offsets_for_label (insn);
4152 else if (INSN_P (insn))
4154 regset_head regs_to_forget;
4155 INIT_REG_SET (®s_to_forget);
4156 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4158 /* If this is a USE and CLOBBER of a MEM, ensure that any
4159 references to eliminable registers have been removed. */
4161 if ((GET_CODE (PATTERN (insn)) == USE
4162 || GET_CODE (PATTERN (insn)) == CLOBBER)
4163 && MEM_P (XEXP (PATTERN (insn), 0)))
4164 XEXP (XEXP (PATTERN (insn), 0), 0)
4165 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4166 GET_MODE (XEXP (PATTERN (insn), 0)),
4169 /* If we need to do register elimination processing, do so.
4170 This might delete the insn, in which case we are done. */
4171 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4173 eliminate_regs_in_insn (insn, 1);
4176 update_eliminable_offsets ();
4177 CLEAR_REG_SET (®s_to_forget);
4182 /* If need_elim is nonzero but need_reload is zero, one might think
4183 that we could simply set n_reloads to 0. However, find_reloads
4184 could have done some manipulation of the insn (such as swapping
4185 commutative operands), and these manipulations are lost during
4186 the first pass for every insn that needs register elimination.
4187 So the actions of find_reloads must be redone here. */
4189 if (! chain->need_elim && ! chain->need_reload
4190 && ! chain->need_operand_change)
4192 /* First find the pseudo regs that must be reloaded for this insn.
4193 This info is returned in the tables reload_... (see reload.h).
4194 Also modify the body of INSN by substituting RELOAD
4195 rtx's for those pseudo regs. */
4198 CLEAR_REG_SET (®_has_output_reload);
4199 CLEAR_HARD_REG_SET (reg_is_output_reload);
4201 find_reloads (insn, 1, spill_indirect_levels, live_known,
4207 rtx next = NEXT_INSN (insn);
4210 prev = PREV_INSN (insn);
4212 /* Now compute which reload regs to reload them into. Perhaps
4213 reusing reload regs from previous insns, or else output
4214 load insns to reload them. Maybe output store insns too.
4215 Record the choices of reload reg in reload_reg_rtx. */
4216 choose_reload_regs (chain);
4218 /* Merge any reloads that we didn't combine for fear of
4219 increasing the number of spill registers needed but now
4220 discover can be safely merged. */
4221 if (SMALL_REGISTER_CLASSES)
4222 merge_assigned_reloads (insn);
4224 /* Generate the insns to reload operands into or out of
4225 their reload regs. */
4226 emit_reload_insns (chain);
4228 /* Substitute the chosen reload regs from reload_reg_rtx
4229 into the insn's body (or perhaps into the bodies of other
4230 load and store insn that we just made for reloading
4231 and that we moved the structure into). */
4232 subst_reloads (insn);
4234 /* Adjust the exception region notes for loads and stores. */
4235 if (flag_non_call_exceptions && !CALL_P (insn))
4236 fixup_eh_region_note (insn, prev, next);
4238 /* If this was an ASM, make sure that all the reload insns
4239 we have generated are valid. If not, give an error
4241 if (asm_noperands (PATTERN (insn)) >= 0)
4242 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4243 if (p != insn && INSN_P (p)
4244 && GET_CODE (PATTERN (p)) != USE
4245 && (recog_memoized (p) < 0
4246 || (extract_insn (p), ! constrain_operands (1))))
4248 error_for_asm (insn,
4249 "%<asm%> operand requires "
4250 "impossible reload");
4255 if (num_eliminable && chain->need_elim)
4256 update_eliminable_offsets ();
4258 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4259 is no longer validly lying around to save a future reload.
4260 Note that this does not detect pseudos that were reloaded
4261 for this insn in order to be stored in
4262 (obeying register constraints). That is correct; such reload
4263 registers ARE still valid. */
4264 forget_marked_reloads (®s_to_forget);
4265 CLEAR_REG_SET (®s_to_forget);
4267 /* There may have been CLOBBER insns placed after INSN. So scan
4268 between INSN and NEXT and use them to forget old reloads. */
4269 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4270 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4271 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4274 /* Likewise for regs altered by auto-increment in this insn.
4275 REG_INC notes have been changed by reloading:
4276 find_reloads_address_1 records substitutions for them,
4277 which have been performed by subst_reloads above. */
4278 for (i = n_reloads - 1; i >= 0; i--)
4280 rtx in_reg = rld[i].in_reg;
4283 enum rtx_code code = GET_CODE (in_reg);
4284 /* PRE_INC / PRE_DEC will have the reload register ending up
4285 with the same value as the stack slot, but that doesn't
4286 hold true for POST_INC / POST_DEC. Either we have to
4287 convert the memory access to a true POST_INC / POST_DEC,
4288 or we can't use the reload register for inheritance. */
4289 if ((code == POST_INC || code == POST_DEC)
4290 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4291 REGNO (rld[i].reg_rtx))
4292 /* Make sure it is the inc/dec pseudo, and not
4293 some other (e.g. output operand) pseudo. */
4294 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4295 == REGNO (XEXP (in_reg, 0))))
4298 rtx reload_reg = rld[i].reg_rtx;
4299 enum machine_mode mode = GET_MODE (reload_reg);
4303 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4305 /* We really want to ignore REG_INC notes here, so
4306 use PATTERN (p) as argument to reg_set_p . */
4307 if (reg_set_p (reload_reg, PATTERN (p)))
4309 n = count_occurrences (PATTERN (p), reload_reg, 0);
4314 n = validate_replace_rtx (reload_reg,
4315 gen_rtx_fmt_e (code,
4320 /* We must also verify that the constraints
4321 are met after the replacement. */
4324 n = constrain_operands (1);
4328 /* If the constraints were not met, then
4329 undo the replacement. */
4332 validate_replace_rtx (gen_rtx_fmt_e (code,
4344 add_reg_note (p, REG_INC, reload_reg);
4345 /* Mark this as having an output reload so that the
4346 REG_INC processing code below won't invalidate
4347 the reload for inheritance. */
4348 SET_HARD_REG_BIT (reg_is_output_reload,
4349 REGNO (reload_reg));
4350 SET_REGNO_REG_SET (®_has_output_reload,
4351 REGNO (XEXP (in_reg, 0)));
4354 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4357 else if ((code == PRE_INC || code == PRE_DEC)
4358 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4359 REGNO (rld[i].reg_rtx))
4360 /* Make sure it is the inc/dec pseudo, and not
4361 some other (e.g. output operand) pseudo. */
4362 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4363 == REGNO (XEXP (in_reg, 0))))
4365 SET_HARD_REG_BIT (reg_is_output_reload,
4366 REGNO (rld[i].reg_rtx));
4367 SET_REGNO_REG_SET (®_has_output_reload,
4368 REGNO (XEXP (in_reg, 0)));
4370 else if (code == PRE_INC || code == PRE_DEC
4371 || code == POST_INC || code == POST_DEC)
4373 int in_regno = REGNO (XEXP (in_reg, 0));
4375 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4378 bool forget_p = true;
4380 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4381 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4384 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4387 if (x == reg_reloaded_insn[in_hard_regno])
4393 /* If for some reasons, we didn't set up
4394 reg_last_reload_reg in this insn,
4395 invalidate inheritance from previous
4396 insns for the incremented/decremented
4397 register. Such registers will be not in
4398 reg_has_output_reload. Invalidate it
4399 also if the corresponding element in
4400 reg_reloaded_insn is also
4403 forget_old_reloads_1 (XEXP (in_reg, 0),
4409 /* If a pseudo that got a hard register is auto-incremented,
4410 we must purge records of copying it into pseudos without
4412 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4413 if (REG_NOTE_KIND (x) == REG_INC)
4415 /* See if this pseudo reg was reloaded in this insn.
4416 If so, its last-reload info is still valid
4417 because it is based on this insn's reload. */
4418 for (i = 0; i < n_reloads; i++)
4419 if (rld[i].out == XEXP (x, 0))
4423 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4427 /* A reload reg's contents are unknown after a label. */
4429 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4431 /* Don't assume a reload reg is still good after a call insn
4432 if it is a call-used reg, or if it contains a value that will
4433 be partially clobbered by the call. */
4434 else if (CALL_P (insn))
4436 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4437 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4442 free (reg_last_reload_reg);
4443 CLEAR_REG_SET (®_has_output_reload);
4446 /* Discard all record of any value reloaded from X,
4447 or reloaded in X from someplace else;
4448 unless X is an output reload reg of the current insn.
4450 X may be a hard reg (the reload reg)
4451 or it may be a pseudo reg that was reloaded from.
4453 When DATA is non-NULL just mark the registers in regset
4454 to be forgotten later. */
4457 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4462 regset regs = (regset) data;
4464 /* note_stores does give us subregs of hard regs,
4465 subreg_regno_offset requires a hard reg. */
4466 while (GET_CODE (x) == SUBREG)
4468 /* We ignore the subreg offset when calculating the regno,
4469 because we are using the entire underlying hard register
4479 if (regno >= FIRST_PSEUDO_REGISTER)
4485 nr = hard_regno_nregs[regno][GET_MODE (x)];
4486 /* Storing into a spilled-reg invalidates its contents.
4487 This can happen if a block-local pseudo is allocated to that reg
4488 and it wasn't spilled because this block's total need is 0.
4489 Then some insn might have an optional reload and use this reg. */
4491 for (i = 0; i < nr; i++)
4492 /* But don't do this if the reg actually serves as an output
4493 reload reg in the current instruction. */
4495 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4497 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4498 spill_reg_store[regno + i] = 0;
4504 SET_REGNO_REG_SET (regs, regno + nr);
4507 /* Since value of X has changed,
4508 forget any value previously copied from it. */
4511 /* But don't forget a copy if this is the output reload
4512 that establishes the copy's validity. */
4514 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4515 reg_last_reload_reg[regno + nr] = 0;
4519 /* Forget the reloads marked in regset by previous function. */
4521 forget_marked_reloads (regset regs)
4524 reg_set_iterator rsi;
4525 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4527 if (reg < FIRST_PSEUDO_REGISTER
4528 /* But don't do this if the reg actually serves as an output
4529 reload reg in the current instruction. */
4531 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4533 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4534 spill_reg_store[reg] = 0;
4537 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4538 reg_last_reload_reg[reg] = 0;
4542 /* The following HARD_REG_SETs indicate when each hard register is
4543 used for a reload of various parts of the current insn. */
4545 /* If reg is unavailable for all reloads. */
4546 static HARD_REG_SET reload_reg_unavailable;
4547 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4548 static HARD_REG_SET reload_reg_used;
4549 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4550 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4551 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4552 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4553 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4554 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4555 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4556 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4557 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4558 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4559 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4560 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4561 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4562 static HARD_REG_SET reload_reg_used_in_op_addr;
4563 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4564 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4565 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4566 static HARD_REG_SET reload_reg_used_in_insn;
4567 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4568 static HARD_REG_SET reload_reg_used_in_other_addr;
4570 /* If reg is in use as a reload reg for any sort of reload. */
4571 static HARD_REG_SET reload_reg_used_at_all;
4573 /* If reg is use as an inherited reload. We just mark the first register
4575 static HARD_REG_SET reload_reg_used_for_inherit;
4577 /* Records which hard regs are used in any way, either as explicit use or
4578 by being allocated to a pseudo during any point of the current insn. */
4579 static HARD_REG_SET reg_used_in_insn;
4581 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4582 TYPE. MODE is used to indicate how many consecutive regs are
4586 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4587 enum machine_mode mode)
4589 unsigned int nregs = hard_regno_nregs[regno][mode];
4592 for (i = regno; i < nregs + regno; i++)
4597 SET_HARD_REG_BIT (reload_reg_used, i);
4600 case RELOAD_FOR_INPUT_ADDRESS:
4601 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4604 case RELOAD_FOR_INPADDR_ADDRESS:
4605 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4608 case RELOAD_FOR_OUTPUT_ADDRESS:
4609 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4612 case RELOAD_FOR_OUTADDR_ADDRESS:
4613 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4616 case RELOAD_FOR_OPERAND_ADDRESS:
4617 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4620 case RELOAD_FOR_OPADDR_ADDR:
4621 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4624 case RELOAD_FOR_OTHER_ADDRESS:
4625 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4628 case RELOAD_FOR_INPUT:
4629 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4632 case RELOAD_FOR_OUTPUT:
4633 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4636 case RELOAD_FOR_INSN:
4637 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4641 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4645 /* Similarly, but show REGNO is no longer in use for a reload. */
4648 clear_reload_reg_in_use (unsigned int regno, int opnum,
4649 enum reload_type type, enum machine_mode mode)
4651 unsigned int nregs = hard_regno_nregs[regno][mode];
4652 unsigned int start_regno, end_regno, r;
4654 /* A complication is that for some reload types, inheritance might
4655 allow multiple reloads of the same types to share a reload register.
4656 We set check_opnum if we have to check only reloads with the same
4657 operand number, and check_any if we have to check all reloads. */
4658 int check_opnum = 0;
4660 HARD_REG_SET *used_in_set;
4665 used_in_set = &reload_reg_used;
4668 case RELOAD_FOR_INPUT_ADDRESS:
4669 used_in_set = &reload_reg_used_in_input_addr[opnum];
4672 case RELOAD_FOR_INPADDR_ADDRESS:
4674 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4677 case RELOAD_FOR_OUTPUT_ADDRESS:
4678 used_in_set = &reload_reg_used_in_output_addr[opnum];
4681 case RELOAD_FOR_OUTADDR_ADDRESS:
4683 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4686 case RELOAD_FOR_OPERAND_ADDRESS:
4687 used_in_set = &reload_reg_used_in_op_addr;
4690 case RELOAD_FOR_OPADDR_ADDR:
4692 used_in_set = &reload_reg_used_in_op_addr_reload;
4695 case RELOAD_FOR_OTHER_ADDRESS:
4696 used_in_set = &reload_reg_used_in_other_addr;
4700 case RELOAD_FOR_INPUT:
4701 used_in_set = &reload_reg_used_in_input[opnum];
4704 case RELOAD_FOR_OUTPUT:
4705 used_in_set = &reload_reg_used_in_output[opnum];
4708 case RELOAD_FOR_INSN:
4709 used_in_set = &reload_reg_used_in_insn;
4714 /* We resolve conflicts with remaining reloads of the same type by
4715 excluding the intervals of reload registers by them from the
4716 interval of freed reload registers. Since we only keep track of
4717 one set of interval bounds, we might have to exclude somewhat
4718 more than what would be necessary if we used a HARD_REG_SET here.
4719 But this should only happen very infrequently, so there should
4720 be no reason to worry about it. */
4722 start_regno = regno;
4723 end_regno = regno + nregs;
4724 if (check_opnum || check_any)
4726 for (i = n_reloads - 1; i >= 0; i--)
4728 if (rld[i].when_needed == type
4729 && (check_any || rld[i].opnum == opnum)
4732 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4733 unsigned int conflict_end
4734 = end_hard_regno (rld[i].mode, conflict_start);
4736 /* If there is an overlap with the first to-be-freed register,
4737 adjust the interval start. */
4738 if (conflict_start <= start_regno && conflict_end > start_regno)
4739 start_regno = conflict_end;
4740 /* Otherwise, if there is a conflict with one of the other
4741 to-be-freed registers, adjust the interval end. */
4742 if (conflict_start > start_regno && conflict_start < end_regno)
4743 end_regno = conflict_start;
4748 for (r = start_regno; r < end_regno; r++)
4749 CLEAR_HARD_REG_BIT (*used_in_set, r);
4752 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4753 specified by OPNUM and TYPE. */
4756 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4760 /* In use for a RELOAD_OTHER means it's not available for anything. */
4761 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4762 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4768 /* In use for anything means we can't use it for RELOAD_OTHER. */
4769 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4770 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4771 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4772 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4775 for (i = 0; i < reload_n_operands; i++)
4776 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4777 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4778 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4779 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4780 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4781 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4786 case RELOAD_FOR_INPUT:
4787 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4788 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4791 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4794 /* If it is used for some other input, can't use it. */
4795 for (i = 0; i < reload_n_operands; i++)
4796 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4799 /* If it is used in a later operand's address, can't use it. */
4800 for (i = opnum + 1; i < reload_n_operands; i++)
4801 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4802 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4807 case RELOAD_FOR_INPUT_ADDRESS:
4808 /* Can't use a register if it is used for an input address for this
4809 operand or used as an input in an earlier one. */
4810 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4814 for (i = 0; i < opnum; i++)
4815 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4820 case RELOAD_FOR_INPADDR_ADDRESS:
4821 /* Can't use a register if it is used for an input address
4822 for this operand or used as an input in an earlier
4824 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4827 for (i = 0; i < opnum; i++)
4828 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4833 case RELOAD_FOR_OUTPUT_ADDRESS:
4834 /* Can't use a register if it is used for an output address for this
4835 operand or used as an output in this or a later operand. Note
4836 that multiple output operands are emitted in reverse order, so
4837 the conflicting ones are those with lower indices. */
4838 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4841 for (i = 0; i <= opnum; i++)
4842 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4847 case RELOAD_FOR_OUTADDR_ADDRESS:
4848 /* Can't use a register if it is used for an output address
4849 for this operand or used as an output in this or a
4850 later operand. Note that multiple output operands are
4851 emitted in reverse order, so the conflicting ones are
4852 those with lower indices. */
4853 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4856 for (i = 0; i <= opnum; i++)
4857 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4862 case RELOAD_FOR_OPERAND_ADDRESS:
4863 for (i = 0; i < reload_n_operands; i++)
4864 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4867 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4868 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4870 case RELOAD_FOR_OPADDR_ADDR:
4871 for (i = 0; i < reload_n_operands; i++)
4872 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4875 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4877 case RELOAD_FOR_OUTPUT:
4878 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4879 outputs, or an operand address for this or an earlier output.
4880 Note that multiple output operands are emitted in reverse order,
4881 so the conflicting ones are those with higher indices. */
4882 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4885 for (i = 0; i < reload_n_operands; i++)
4886 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4889 for (i = opnum; i < reload_n_operands; i++)
4890 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4891 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4896 case RELOAD_FOR_INSN:
4897 for (i = 0; i < reload_n_operands; i++)
4898 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4899 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4902 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4903 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4905 case RELOAD_FOR_OTHER_ADDRESS:
4906 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4913 /* Return 1 if the value in reload reg REGNO, as used by a reload
4914 needed for the part of the insn specified by OPNUM and TYPE,
4915 is still available in REGNO at the end of the insn.
4917 We can assume that the reload reg was already tested for availability
4918 at the time it is needed, and we should not check this again,
4919 in case the reg has already been marked in use. */
4922 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4929 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4930 its value must reach the end. */
4933 /* If this use is for part of the insn,
4934 its value reaches if no subsequent part uses the same register.
4935 Just like the above function, don't try to do this with lots
4938 case RELOAD_FOR_OTHER_ADDRESS:
4939 /* Here we check for everything else, since these don't conflict
4940 with anything else and everything comes later. */
4942 for (i = 0; i < reload_n_operands; i++)
4943 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4944 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4945 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4946 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4947 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4948 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4951 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4952 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4953 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4954 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4956 case RELOAD_FOR_INPUT_ADDRESS:
4957 case RELOAD_FOR_INPADDR_ADDRESS:
4958 /* Similar, except that we check only for this and subsequent inputs
4959 and the address of only subsequent inputs and we do not need
4960 to check for RELOAD_OTHER objects since they are known not to
4963 for (i = opnum; i < reload_n_operands; i++)
4964 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4967 for (i = opnum + 1; i < reload_n_operands; i++)
4968 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4969 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4972 for (i = 0; i < reload_n_operands; i++)
4973 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4974 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4975 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4978 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4981 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4982 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4983 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4985 case RELOAD_FOR_INPUT:
4986 /* Similar to input address, except we start at the next operand for
4987 both input and input address and we do not check for
4988 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4991 for (i = opnum + 1; i < reload_n_operands; i++)
4992 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4993 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4994 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4997 /* ... fall through ... */
4999 case RELOAD_FOR_OPERAND_ADDRESS:
5000 /* Check outputs and their addresses. */
5002 for (i = 0; i < reload_n_operands; i++)
5003 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5004 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5005 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5008 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5010 case RELOAD_FOR_OPADDR_ADDR:
5011 for (i = 0; i < reload_n_operands; i++)
5012 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5013 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5014 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5017 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5018 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5019 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5021 case RELOAD_FOR_INSN:
5022 /* These conflict with other outputs with RELOAD_OTHER. So
5023 we need only check for output addresses. */
5025 opnum = reload_n_operands;
5027 /* ... fall through ... */
5029 case RELOAD_FOR_OUTPUT:
5030 case RELOAD_FOR_OUTPUT_ADDRESS:
5031 case RELOAD_FOR_OUTADDR_ADDRESS:
5032 /* We already know these can't conflict with a later output. So the
5033 only thing to check are later output addresses.
5034 Note that multiple output operands are emitted in reverse order,
5035 so the conflicting ones are those with lower indices. */
5036 for (i = 0; i < opnum; i++)
5037 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5048 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5049 every register in the range [REGNO, REGNO + NREGS). */
5052 reload_regs_reach_end_p (unsigned int regno, int nregs,
5053 int opnum, enum reload_type type)
5057 for (i = 0; i < nregs; i++)
5058 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5064 /* Returns whether R1 and R2 are uniquely chained: the value of one
5065 is used by the other, and that value is not used by any other
5066 reload for this insn. This is used to partially undo the decision
5067 made in find_reloads when in the case of multiple
5068 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5069 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5070 reloads. This code tries to avoid the conflict created by that
5071 change. It might be cleaner to explicitly keep track of which
5072 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5073 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5074 this after the fact. */
5076 reloads_unique_chain_p (int r1, int r2)
5080 /* We only check input reloads. */
5081 if (! rld[r1].in || ! rld[r2].in)
5084 /* Avoid anything with output reloads. */
5085 if (rld[r1].out || rld[r2].out)
5088 /* "chained" means one reload is a component of the other reload,
5089 not the same as the other reload. */
5090 if (rld[r1].opnum != rld[r2].opnum
5091 || rtx_equal_p (rld[r1].in, rld[r2].in)
5092 || rld[r1].optional || rld[r2].optional
5093 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5094 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5097 for (i = 0; i < n_reloads; i ++)
5098 /* Look for input reloads that aren't our two */
5099 if (i != r1 && i != r2 && rld[i].in)
5101 /* If our reload is mentioned at all, it isn't a simple chain. */
5102 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5109 /* The recursive function change all occurrences of WHAT in *WHERE
5112 substitute (rtx *where, const_rtx what, rtx repl)
5121 if (*where == what || rtx_equal_p (*where, what))
5127 code = GET_CODE (*where);
5128 fmt = GET_RTX_FORMAT (code);
5129 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5135 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5136 substitute (&XVECEXP (*where, i, j), what, repl);
5138 else if (fmt[i] == 'e')
5139 substitute (&XEXP (*where, i), what, repl);
5143 /* The function returns TRUE if chain of reload R1 and R2 (in any
5144 order) can be evaluated without usage of intermediate register for
5145 the reload containing another reload. It is important to see
5146 gen_reload to understand what the function is trying to do. As an
5147 example, let us have reload chain
5150 r1: <something> + const
5152 and reload R2 got reload reg HR. The function returns true if
5153 there is a correct insn HR = HR + <something>. Otherwise,
5154 gen_reload will use intermediate register (and this is the reload
5155 reg for R1) to reload <something>.
5157 We need this function to find a conflict for chain reloads. In our
5158 example, if HR = HR + <something> is incorrect insn, then we cannot
5159 use HR as a reload register for R2. If we do use it then we get a
5168 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5172 rtx out, in, tem, insn;
5173 rtx last = get_last_insn ();
5175 /* Make r2 a component of r1. */
5176 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5182 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5183 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5184 gcc_assert (regno >= 0);
5185 out = gen_rtx_REG (rld[r1].mode, regno);
5186 in = copy_rtx (rld[r1].in);
5187 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5189 /* If IN is a paradoxical SUBREG, remove it and try to put the
5190 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5191 if (GET_CODE (in) == SUBREG
5192 && (GET_MODE_SIZE (GET_MODE (in))
5193 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5194 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5195 in = SUBREG_REG (in), out = tem;
5197 if (GET_CODE (in) == PLUS
5198 && (REG_P (XEXP (in, 0))
5199 || GET_CODE (XEXP (in, 0)) == SUBREG
5200 || MEM_P (XEXP (in, 0)))
5201 && (REG_P (XEXP (in, 1))
5202 || GET_CODE (XEXP (in, 1)) == SUBREG
5203 || CONSTANT_P (XEXP (in, 1))
5204 || MEM_P (XEXP (in, 1))))
5206 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5207 code = recog_memoized (insn);
5212 extract_insn (insn);
5213 /* We want constrain operands to treat this insn strictly in
5214 its validity determination, i.e., the way it would after
5215 reload has completed. */
5216 result = constrain_operands (1);
5219 delete_insns_since (last);
5223 /* It looks like other cases in gen_reload are not possible for
5224 chain reloads or do need an intermediate hard registers. */
5228 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5231 This function uses the same algorithm as reload_reg_free_p above. */
5234 reloads_conflict (int r1, int r2)
5236 enum reload_type r1_type = rld[r1].when_needed;
5237 enum reload_type r2_type = rld[r2].when_needed;
5238 int r1_opnum = rld[r1].opnum;
5239 int r2_opnum = rld[r2].opnum;
5241 /* RELOAD_OTHER conflicts with everything. */
5242 if (r2_type == RELOAD_OTHER)
5245 /* Otherwise, check conflicts differently for each type. */
5249 case RELOAD_FOR_INPUT:
5250 return (r2_type == RELOAD_FOR_INSN
5251 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5252 || r2_type == RELOAD_FOR_OPADDR_ADDR
5253 || r2_type == RELOAD_FOR_INPUT
5254 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5255 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5256 && r2_opnum > r1_opnum));
5258 case RELOAD_FOR_INPUT_ADDRESS:
5259 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5260 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5262 case RELOAD_FOR_INPADDR_ADDRESS:
5263 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5264 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5266 case RELOAD_FOR_OUTPUT_ADDRESS:
5267 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5268 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5270 case RELOAD_FOR_OUTADDR_ADDRESS:
5271 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5272 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5274 case RELOAD_FOR_OPERAND_ADDRESS:
5275 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5276 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5277 && (!reloads_unique_chain_p (r1, r2)
5278 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5280 case RELOAD_FOR_OPADDR_ADDR:
5281 return (r2_type == RELOAD_FOR_INPUT
5282 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5284 case RELOAD_FOR_OUTPUT:
5285 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5286 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5287 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5288 && r2_opnum >= r1_opnum));
5290 case RELOAD_FOR_INSN:
5291 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5292 || r2_type == RELOAD_FOR_INSN
5293 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5295 case RELOAD_FOR_OTHER_ADDRESS:
5296 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5306 /* Indexed by reload number, 1 if incoming value
5307 inherited from previous insns. */
5308 static char reload_inherited[MAX_RELOADS];
5310 /* For an inherited reload, this is the insn the reload was inherited from,
5311 if we know it. Otherwise, this is 0. */
5312 static rtx reload_inheritance_insn[MAX_RELOADS];
5314 /* If nonzero, this is a place to get the value of the reload,
5315 rather than using reload_in. */
5316 static rtx reload_override_in[MAX_RELOADS];
5318 /* For each reload, the hard register number of the register used,
5319 or -1 if we did not need a register for this reload. */
5320 static int reload_spill_index[MAX_RELOADS];
5322 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5323 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5325 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5326 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5328 /* Subroutine of free_for_value_p, used to check a single register.
5329 START_REGNO is the starting regno of the full reload register
5330 (possibly comprising multiple hard registers) that we are considering. */
5333 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5334 enum reload_type type, rtx value, rtx out,
5335 int reloadnum, int ignore_address_reloads)
5338 /* Set if we see an input reload that must not share its reload register
5339 with any new earlyclobber, but might otherwise share the reload
5340 register with an output or input-output reload. */
5341 int check_earlyclobber = 0;
5345 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5348 if (out == const0_rtx)
5354 /* We use some pseudo 'time' value to check if the lifetimes of the
5355 new register use would overlap with the one of a previous reload
5356 that is not read-only or uses a different value.
5357 The 'time' used doesn't have to be linear in any shape or form, just
5359 Some reload types use different 'buckets' for each operand.
5360 So there are MAX_RECOG_OPERANDS different time values for each
5362 We compute TIME1 as the time when the register for the prospective
5363 new reload ceases to be live, and TIME2 for each existing
5364 reload as the time when that the reload register of that reload
5366 Where there is little to be gained by exact lifetime calculations,
5367 we just make conservative assumptions, i.e. a longer lifetime;
5368 this is done in the 'default:' cases. */
5371 case RELOAD_FOR_OTHER_ADDRESS:
5372 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5373 time1 = copy ? 0 : 1;
5376 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5378 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5379 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5380 respectively, to the time values for these, we get distinct time
5381 values. To get distinct time values for each operand, we have to
5382 multiply opnum by at least three. We round that up to four because
5383 multiply by four is often cheaper. */
5384 case RELOAD_FOR_INPADDR_ADDRESS:
5385 time1 = opnum * 4 + 2;
5387 case RELOAD_FOR_INPUT_ADDRESS:
5388 time1 = opnum * 4 + 3;
5390 case RELOAD_FOR_INPUT:
5391 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5392 executes (inclusive). */
5393 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5395 case RELOAD_FOR_OPADDR_ADDR:
5397 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5398 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5400 case RELOAD_FOR_OPERAND_ADDRESS:
5401 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5403 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5405 case RELOAD_FOR_OUTADDR_ADDRESS:
5406 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5408 case RELOAD_FOR_OUTPUT_ADDRESS:
5409 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5412 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5415 for (i = 0; i < n_reloads; i++)
5417 rtx reg = rld[i].reg_rtx;
5418 if (reg && REG_P (reg)
5419 && ((unsigned) regno - true_regnum (reg)
5420 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5423 rtx other_input = rld[i].in;
5425 /* If the other reload loads the same input value, that
5426 will not cause a conflict only if it's loading it into
5427 the same register. */
5428 if (true_regnum (reg) != start_regno)
5429 other_input = NULL_RTX;
5430 if (! other_input || ! rtx_equal_p (other_input, value)
5431 || rld[i].out || out)
5434 switch (rld[i].when_needed)
5436 case RELOAD_FOR_OTHER_ADDRESS:
5439 case RELOAD_FOR_INPADDR_ADDRESS:
5440 /* find_reloads makes sure that a
5441 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5442 by at most one - the first -
5443 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5444 address reload is inherited, the address address reload
5445 goes away, so we can ignore this conflict. */
5446 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5447 && ignore_address_reloads
5448 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5449 Then the address address is still needed to store
5450 back the new address. */
5451 && ! rld[reloadnum].out)
5453 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5454 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5456 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5457 && ignore_address_reloads
5458 /* Unless we are reloading an auto_inc expression. */
5459 && ! rld[reloadnum].out)
5461 time2 = rld[i].opnum * 4 + 2;
5463 case RELOAD_FOR_INPUT_ADDRESS:
5464 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5465 && ignore_address_reloads
5466 && ! rld[reloadnum].out)
5468 time2 = rld[i].opnum * 4 + 3;
5470 case RELOAD_FOR_INPUT:
5471 time2 = rld[i].opnum * 4 + 4;
5472 check_earlyclobber = 1;
5474 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5475 == MAX_RECOG_OPERAND * 4 */
5476 case RELOAD_FOR_OPADDR_ADDR:
5477 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5478 && ignore_address_reloads
5479 && ! rld[reloadnum].out)
5481 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5483 case RELOAD_FOR_OPERAND_ADDRESS:
5484 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5485 check_earlyclobber = 1;
5487 case RELOAD_FOR_INSN:
5488 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5490 case RELOAD_FOR_OUTPUT:
5491 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5492 instruction is executed. */
5493 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5495 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5496 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5498 case RELOAD_FOR_OUTADDR_ADDRESS:
5499 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5500 && ignore_address_reloads
5501 && ! rld[reloadnum].out)
5503 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5505 case RELOAD_FOR_OUTPUT_ADDRESS:
5506 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5509 /* If there is no conflict in the input part, handle this
5510 like an output reload. */
5511 if (! rld[i].in || rtx_equal_p (other_input, value))
5513 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5514 /* Earlyclobbered outputs must conflict with inputs. */
5515 if (earlyclobber_operand_p (rld[i].out))
5516 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5521 /* RELOAD_OTHER might be live beyond instruction execution,
5522 but this is not obvious when we set time2 = 1. So check
5523 here if there might be a problem with the new reload
5524 clobbering the register used by the RELOAD_OTHER. */
5532 && (! rld[i].in || rld[i].out
5533 || ! rtx_equal_p (other_input, value)))
5534 || (out && rld[reloadnum].out_reg
5535 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5541 /* Earlyclobbered outputs must conflict with inputs. */
5542 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5548 /* Return 1 if the value in reload reg REGNO, as used by a reload
5549 needed for the part of the insn specified by OPNUM and TYPE,
5550 may be used to load VALUE into it.
5552 MODE is the mode in which the register is used, this is needed to
5553 determine how many hard regs to test.
5555 Other read-only reloads with the same value do not conflict
5556 unless OUT is nonzero and these other reloads have to live while
5557 output reloads live.
5558 If OUT is CONST0_RTX, this is a special case: it means that the
5559 test should not be for using register REGNO as reload register, but
5560 for copying from register REGNO into the reload register.
5562 RELOADNUM is the number of the reload we want to load this value for;
5563 a reload does not conflict with itself.
5565 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5566 reloads that load an address for the very reload we are considering.
5568 The caller has to make sure that there is no conflict with the return
5572 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5573 enum reload_type type, rtx value, rtx out, int reloadnum,
5574 int ignore_address_reloads)
5576 int nregs = hard_regno_nregs[regno][mode];
5578 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5579 value, out, reloadnum,
5580 ignore_address_reloads))
5585 /* Return nonzero if the rtx X is invariant over the current function. */
5586 /* ??? Actually, the places where we use this expect exactly what is
5587 tested here, and not everything that is function invariant. In
5588 particular, the frame pointer and arg pointer are special cased;
5589 pic_offset_table_rtx is not, and we must not spill these things to
5593 function_invariant_p (const_rtx x)
5597 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5599 if (GET_CODE (x) == PLUS
5600 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5601 && CONSTANT_P (XEXP (x, 1)))
5606 /* Determine whether the reload reg X overlaps any rtx'es used for
5607 overriding inheritance. Return nonzero if so. */
5610 conflicts_with_override (rtx x)
5613 for (i = 0; i < n_reloads; i++)
5614 if (reload_override_in[i]
5615 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5620 /* Give an error message saying we failed to find a reload for INSN,
5621 and clear out reload R. */
5623 failed_reload (rtx insn, int r)
5625 if (asm_noperands (PATTERN (insn)) < 0)
5626 /* It's the compiler's fault. */
5627 fatal_insn ("could not find a spill register", insn);
5629 /* It's the user's fault; the operand's mode and constraint
5630 don't match. Disable this reload so we don't crash in final. */
5631 error_for_asm (insn,
5632 "%<asm%> operand constraint incompatible with operand size");
5636 rld[r].optional = 1;
5637 rld[r].secondary_p = 1;
5640 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5641 for reload R. If it's valid, get an rtx for it. Return nonzero if
5644 set_reload_reg (int i, int r)
5647 rtx reg = spill_reg_rtx[i];
5649 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5650 spill_reg_rtx[i] = reg
5651 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5653 regno = true_regnum (reg);
5655 /* Detect when the reload reg can't hold the reload mode.
5656 This used to be one `if', but Sequent compiler can't handle that. */
5657 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5659 enum machine_mode test_mode = VOIDmode;
5661 test_mode = GET_MODE (rld[r].in);
5662 /* If rld[r].in has VOIDmode, it means we will load it
5663 in whatever mode the reload reg has: to wit, rld[r].mode.
5664 We have already tested that for validity. */
5665 /* Aside from that, we need to test that the expressions
5666 to reload from or into have modes which are valid for this
5667 reload register. Otherwise the reload insns would be invalid. */
5668 if (! (rld[r].in != 0 && test_mode != VOIDmode
5669 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5670 if (! (rld[r].out != 0
5671 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5673 /* The reg is OK. */
5676 /* Mark as in use for this insn the reload regs we use
5678 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5679 rld[r].when_needed, rld[r].mode);
5681 rld[r].reg_rtx = reg;
5682 reload_spill_index[r] = spill_regs[i];
5689 /* Find a spill register to use as a reload register for reload R.
5690 LAST_RELOAD is nonzero if this is the last reload for the insn being
5693 Set rld[R].reg_rtx to the register allocated.
5695 We return 1 if successful, or 0 if we couldn't find a spill reg and
5696 we didn't change anything. */
5699 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5704 /* If we put this reload ahead, thinking it is a group,
5705 then insist on finding a group. Otherwise we can grab a
5706 reg that some other reload needs.
5707 (That can happen when we have a 68000 DATA_OR_FP_REG
5708 which is a group of data regs or one fp reg.)
5709 We need not be so restrictive if there are no more reloads
5712 ??? Really it would be nicer to have smarter handling
5713 for that kind of reg class, where a problem like this is normal.
5714 Perhaps those classes should be avoided for reloading
5715 by use of more alternatives. */
5717 int force_group = rld[r].nregs > 1 && ! last_reload;
5719 /* If we want a single register and haven't yet found one,
5720 take any reg in the right class and not in use.
5721 If we want a consecutive group, here is where we look for it.
5723 We use two passes so we can first look for reload regs to
5724 reuse, which are already in use for other reloads in this insn,
5725 and only then use additional registers.
5726 I think that maximizing reuse is needed to make sure we don't
5727 run out of reload regs. Suppose we have three reloads, and
5728 reloads A and B can share regs. These need two regs.
5729 Suppose A and B are given different regs.
5730 That leaves none for C. */
5731 for (pass = 0; pass < 2; pass++)
5733 /* I is the index in spill_regs.
5734 We advance it round-robin between insns to use all spill regs
5735 equally, so that inherited reloads have a chance
5736 of leapfrogging each other. */
5740 for (count = 0; count < n_spills; count++)
5742 int rclass = (int) rld[r].rclass;
5748 regnum = spill_regs[i];
5750 if ((reload_reg_free_p (regnum, rld[r].opnum,
5753 /* We check reload_reg_used to make sure we
5754 don't clobber the return register. */
5755 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5756 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5757 rld[r].when_needed, rld[r].in,
5759 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5760 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5761 /* Look first for regs to share, then for unshared. But
5762 don't share regs used for inherited reloads; they are
5763 the ones we want to preserve. */
5765 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5767 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5770 int nr = hard_regno_nregs[regnum][rld[r].mode];
5771 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5772 (on 68000) got us two FP regs. If NR is 1,
5773 we would reject both of them. */
5776 /* If we need only one reg, we have already won. */
5779 /* But reject a single reg if we demand a group. */
5784 /* Otherwise check that as many consecutive regs as we need
5785 are available here. */
5788 int regno = regnum + nr - 1;
5789 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5790 && spill_reg_order[regno] >= 0
5791 && reload_reg_free_p (regno, rld[r].opnum,
5792 rld[r].when_needed)))
5801 /* If we found something on pass 1, omit pass 2. */
5802 if (count < n_spills)
5806 /* We should have found a spill register by now. */
5807 if (count >= n_spills)
5810 /* I is the index in SPILL_REG_RTX of the reload register we are to
5811 allocate. Get an rtx for it and find its register number. */
5813 return set_reload_reg (i, r);
5816 /* Initialize all the tables needed to allocate reload registers.
5817 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5818 is the array we use to restore the reg_rtx field for every reload. */
5821 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5825 for (i = 0; i < n_reloads; i++)
5826 rld[i].reg_rtx = save_reload_reg_rtx[i];
5828 memset (reload_inherited, 0, MAX_RELOADS);
5829 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5830 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5832 CLEAR_HARD_REG_SET (reload_reg_used);
5833 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5834 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5835 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5836 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5837 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5839 CLEAR_HARD_REG_SET (reg_used_in_insn);
5842 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5843 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5844 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5845 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5846 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5847 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5850 for (i = 0; i < reload_n_operands; i++)
5852 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5853 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5854 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5855 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5856 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5857 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5860 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5862 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5864 for (i = 0; i < n_reloads; i++)
5865 /* If we have already decided to use a certain register,
5866 don't use it in another way. */
5868 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5869 rld[i].when_needed, rld[i].mode);
5872 /* Assign hard reg targets for the pseudo-registers we must reload
5873 into hard regs for this insn.
5874 Also output the instructions to copy them in and out of the hard regs.
5876 For machines with register classes, we are responsible for
5877 finding a reload reg in the proper class. */
5880 choose_reload_regs (struct insn_chain *chain)
5882 rtx insn = chain->insn;
5884 unsigned int max_group_size = 1;
5885 enum reg_class group_class = NO_REGS;
5886 int pass, win, inheritance;
5888 rtx save_reload_reg_rtx[MAX_RELOADS];
5890 /* In order to be certain of getting the registers we need,
5891 we must sort the reloads into order of increasing register class.
5892 Then our grabbing of reload registers will parallel the process
5893 that provided the reload registers.
5895 Also note whether any of the reloads wants a consecutive group of regs.
5896 If so, record the maximum size of the group desired and what
5897 register class contains all the groups needed by this insn. */
5899 for (j = 0; j < n_reloads; j++)
5901 reload_order[j] = j;
5902 if (rld[j].reg_rtx != NULL_RTX)
5904 gcc_assert (REG_P (rld[j].reg_rtx)
5905 && HARD_REGISTER_P (rld[j].reg_rtx));
5906 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5909 reload_spill_index[j] = -1;
5911 if (rld[j].nregs > 1)
5913 max_group_size = MAX (rld[j].nregs, max_group_size);
5915 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5918 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5922 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5924 /* If -O, try first with inheritance, then turning it off.
5925 If not -O, don't do inheritance.
5926 Using inheritance when not optimizing leads to paradoxes
5927 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5928 because one side of the comparison might be inherited. */
5930 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5932 choose_reload_regs_init (chain, save_reload_reg_rtx);
5934 /* Process the reloads in order of preference just found.
5935 Beyond this point, subregs can be found in reload_reg_rtx.
5937 This used to look for an existing reloaded home for all of the
5938 reloads, and only then perform any new reloads. But that could lose
5939 if the reloads were done out of reg-class order because a later
5940 reload with a looser constraint might have an old home in a register
5941 needed by an earlier reload with a tighter constraint.
5943 To solve this, we make two passes over the reloads, in the order
5944 described above. In the first pass we try to inherit a reload
5945 from a previous insn. If there is a later reload that needs a
5946 class that is a proper subset of the class being processed, we must
5947 also allocate a spill register during the first pass.
5949 Then make a second pass over the reloads to allocate any reloads
5950 that haven't been given registers yet. */
5952 for (j = 0; j < n_reloads; j++)
5954 int r = reload_order[j];
5955 rtx search_equiv = NULL_RTX;
5957 /* Ignore reloads that got marked inoperative. */
5958 if (rld[r].out == 0 && rld[r].in == 0
5959 && ! rld[r].secondary_p)
5962 /* If find_reloads chose to use reload_in or reload_out as a reload
5963 register, we don't need to chose one. Otherwise, try even if it
5964 found one since we might save an insn if we find the value lying
5966 Try also when reload_in is a pseudo without a hard reg. */
5967 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5968 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5969 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5970 && !MEM_P (rld[r].in)
5971 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5974 #if 0 /* No longer needed for correct operation.
5975 It might give better code, or might not; worth an experiment? */
5976 /* If this is an optional reload, we can't inherit from earlier insns
5977 until we are sure that any non-optional reloads have been allocated.
5978 The following code takes advantage of the fact that optional reloads
5979 are at the end of reload_order. */
5980 if (rld[r].optional != 0)
5981 for (i = 0; i < j; i++)
5982 if ((rld[reload_order[i]].out != 0
5983 || rld[reload_order[i]].in != 0
5984 || rld[reload_order[i]].secondary_p)
5985 && ! rld[reload_order[i]].optional
5986 && rld[reload_order[i]].reg_rtx == 0)
5987 allocate_reload_reg (chain, reload_order[i], 0);
5990 /* First see if this pseudo is already available as reloaded
5991 for a previous insn. We cannot try to inherit for reloads
5992 that are smaller than the maximum number of registers needed
5993 for groups unless the register we would allocate cannot be used
5996 We could check here to see if this is a secondary reload for
5997 an object that is already in a register of the desired class.
5998 This would avoid the need for the secondary reload register.
5999 But this is complex because we can't easily determine what
6000 objects might want to be loaded via this reload. So let a
6001 register be allocated here. In `emit_reload_insns' we suppress
6002 one of the loads in the case described above. */
6008 enum machine_mode mode = VOIDmode;
6012 else if (REG_P (rld[r].in))
6014 regno = REGNO (rld[r].in);
6015 mode = GET_MODE (rld[r].in);
6017 else if (REG_P (rld[r].in_reg))
6019 regno = REGNO (rld[r].in_reg);
6020 mode = GET_MODE (rld[r].in_reg);
6022 else if (GET_CODE (rld[r].in_reg) == SUBREG
6023 && REG_P (SUBREG_REG (rld[r].in_reg)))
6025 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6026 if (regno < FIRST_PSEUDO_REGISTER)
6027 regno = subreg_regno (rld[r].in_reg);
6029 byte = SUBREG_BYTE (rld[r].in_reg);
6030 mode = GET_MODE (rld[r].in_reg);
6033 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6034 && REG_P (XEXP (rld[r].in_reg, 0)))
6036 regno = REGNO (XEXP (rld[r].in_reg, 0));
6037 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6038 rld[r].out = rld[r].in;
6042 /* This won't work, since REGNO can be a pseudo reg number.
6043 Also, it takes much more hair to keep track of all the things
6044 that can invalidate an inherited reload of part of a pseudoreg. */
6045 else if (GET_CODE (rld[r].in) == SUBREG
6046 && REG_P (SUBREG_REG (rld[r].in)))
6047 regno = subreg_regno (rld[r].in);
6051 && reg_last_reload_reg[regno] != 0
6052 #ifdef CANNOT_CHANGE_MODE_CLASS
6053 /* Verify that the register it's in can be used in
6055 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6056 GET_MODE (reg_last_reload_reg[regno]),
6061 enum reg_class rclass = rld[r].rclass, last_class;
6062 rtx last_reg = reg_last_reload_reg[regno];
6063 enum machine_mode need_mode;
6065 i = REGNO (last_reg);
6066 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6067 last_class = REGNO_REG_CLASS (i);
6073 = smallest_mode_for_size
6074 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6075 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6076 ? MODE_INT : GET_MODE_CLASS (mode));
6078 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6079 >= GET_MODE_SIZE (need_mode))
6080 && reg_reloaded_contents[i] == regno
6081 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6082 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6083 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6084 /* Even if we can't use this register as a reload
6085 register, we might use it for reload_override_in,
6086 if copying it to the desired class is cheap
6088 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6089 < MEMORY_MOVE_COST (mode, rclass, 1))
6090 && (secondary_reload_class (1, rclass, mode,
6093 #ifdef SECONDARY_MEMORY_NEEDED
6094 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6099 && (rld[r].nregs == max_group_size
6100 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6102 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6103 rld[r].when_needed, rld[r].in,
6106 /* If a group is needed, verify that all the subsequent
6107 registers still have their values intact. */
6108 int nr = hard_regno_nregs[i][rld[r].mode];
6111 for (k = 1; k < nr; k++)
6112 if (reg_reloaded_contents[i + k] != regno
6113 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6121 last_reg = (GET_MODE (last_reg) == mode
6122 ? last_reg : gen_rtx_REG (mode, i));
6125 for (k = 0; k < nr; k++)
6126 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6129 /* We found a register that contains the
6130 value we need. If this register is the
6131 same as an `earlyclobber' operand of the
6132 current insn, just mark it as a place to
6133 reload from since we can't use it as the
6134 reload register itself. */
6136 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6137 if (reg_overlap_mentioned_for_reload_p
6138 (reg_last_reload_reg[regno],
6139 reload_earlyclobbers[i1]))
6142 if (i1 != n_earlyclobbers
6143 || ! (free_for_value_p (i, rld[r].mode,
6145 rld[r].when_needed, rld[r].in,
6147 /* Don't use it if we'd clobber a pseudo reg. */
6148 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6150 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6151 /* Don't clobber the frame pointer. */
6152 || (i == HARD_FRAME_POINTER_REGNUM
6153 && frame_pointer_needed
6155 /* Don't really use the inherited spill reg
6156 if we need it wider than we've got it. */
6157 || (GET_MODE_SIZE (rld[r].mode)
6158 > GET_MODE_SIZE (mode))
6161 /* If find_reloads chose reload_out as reload
6162 register, stay with it - that leaves the
6163 inherited register for subsequent reloads. */
6164 || (rld[r].out && rld[r].reg_rtx
6165 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6167 if (! rld[r].optional)
6169 reload_override_in[r] = last_reg;
6170 reload_inheritance_insn[r]
6171 = reg_reloaded_insn[i];
6177 /* We can use this as a reload reg. */
6178 /* Mark the register as in use for this part of
6180 mark_reload_reg_in_use (i,
6184 rld[r].reg_rtx = last_reg;
6185 reload_inherited[r] = 1;
6186 reload_inheritance_insn[r]
6187 = reg_reloaded_insn[i];
6188 reload_spill_index[r] = i;
6189 for (k = 0; k < nr; k++)
6190 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6198 /* Here's another way to see if the value is already lying around. */
6201 && ! reload_inherited[r]
6203 && (CONSTANT_P (rld[r].in)
6204 || GET_CODE (rld[r].in) == PLUS
6205 || REG_P (rld[r].in)
6206 || MEM_P (rld[r].in))
6207 && (rld[r].nregs == max_group_size
6208 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6209 search_equiv = rld[r].in;
6210 /* If this is an output reload from a simple move insn, look
6211 if an equivalence for the input is available. */
6212 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6214 rtx set = single_set (insn);
6217 && rtx_equal_p (rld[r].out, SET_DEST (set))
6218 && CONSTANT_P (SET_SRC (set)))
6219 search_equiv = SET_SRC (set);
6225 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6226 -1, NULL, 0, rld[r].mode);
6232 regno = REGNO (equiv);
6235 /* This must be a SUBREG of a hard register.
6236 Make a new REG since this might be used in an
6237 address and not all machines support SUBREGs
6239 gcc_assert (GET_CODE (equiv) == SUBREG);
6240 regno = subreg_regno (equiv);
6241 equiv = gen_rtx_REG (rld[r].mode, regno);
6242 /* If we choose EQUIV as the reload register, but the
6243 loop below decides to cancel the inheritance, we'll
6244 end up reloading EQUIV in rld[r].mode, not the mode
6245 it had originally. That isn't safe when EQUIV isn't
6246 available as a spill register since its value might
6247 still be live at this point. */
6248 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6249 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6254 /* If we found a spill reg, reject it unless it is free
6255 and of the desired class. */
6259 int bad_for_class = 0;
6260 int max_regno = regno + rld[r].nregs;
6262 for (i = regno; i < max_regno; i++)
6264 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6266 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6271 && ! free_for_value_p (regno, rld[r].mode,
6272 rld[r].opnum, rld[r].when_needed,
6273 rld[r].in, rld[r].out, r, 1))
6278 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6281 /* We found a register that contains the value we need.
6282 If this register is the same as an `earlyclobber' operand
6283 of the current insn, just mark it as a place to reload from
6284 since we can't use it as the reload register itself. */
6287 for (i = 0; i < n_earlyclobbers; i++)
6288 if (reg_overlap_mentioned_for_reload_p (equiv,
6289 reload_earlyclobbers[i]))
6291 if (! rld[r].optional)
6292 reload_override_in[r] = equiv;
6297 /* If the equiv register we have found is explicitly clobbered
6298 in the current insn, it depends on the reload type if we
6299 can use it, use it for reload_override_in, or not at all.
6300 In particular, we then can't use EQUIV for a
6301 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6305 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6306 switch (rld[r].when_needed)
6308 case RELOAD_FOR_OTHER_ADDRESS:
6309 case RELOAD_FOR_INPADDR_ADDRESS:
6310 case RELOAD_FOR_INPUT_ADDRESS:
6311 case RELOAD_FOR_OPADDR_ADDR:
6314 case RELOAD_FOR_INPUT:
6315 case RELOAD_FOR_OPERAND_ADDRESS:
6316 if (! rld[r].optional)
6317 reload_override_in[r] = equiv;
6323 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6324 switch (rld[r].when_needed)
6326 case RELOAD_FOR_OTHER_ADDRESS:
6327 case RELOAD_FOR_INPADDR_ADDRESS:
6328 case RELOAD_FOR_INPUT_ADDRESS:
6329 case RELOAD_FOR_OPADDR_ADDR:
6330 case RELOAD_FOR_OPERAND_ADDRESS:
6331 case RELOAD_FOR_INPUT:
6334 if (! rld[r].optional)
6335 reload_override_in[r] = equiv;
6343 /* If we found an equivalent reg, say no code need be generated
6344 to load it, and use it as our reload reg. */
6346 && (regno != HARD_FRAME_POINTER_REGNUM
6347 || !frame_pointer_needed))
6349 int nr = hard_regno_nregs[regno][rld[r].mode];
6351 rld[r].reg_rtx = equiv;
6352 reload_spill_index[r] = regno;
6353 reload_inherited[r] = 1;
6355 /* If reg_reloaded_valid is not set for this register,
6356 there might be a stale spill_reg_store lying around.
6357 We must clear it, since otherwise emit_reload_insns
6358 might delete the store. */
6359 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6360 spill_reg_store[regno] = NULL_RTX;
6361 /* If any of the hard registers in EQUIV are spill
6362 registers, mark them as in use for this insn. */
6363 for (k = 0; k < nr; k++)
6365 i = spill_reg_order[regno + k];
6368 mark_reload_reg_in_use (regno, rld[r].opnum,
6371 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6378 /* If we found a register to use already, or if this is an optional
6379 reload, we are done. */
6380 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6384 /* No longer needed for correct operation. Might or might
6385 not give better code on the average. Want to experiment? */
6387 /* See if there is a later reload that has a class different from our
6388 class that intersects our class or that requires less register
6389 than our reload. If so, we must allocate a register to this
6390 reload now, since that reload might inherit a previous reload
6391 and take the only available register in our class. Don't do this
6392 for optional reloads since they will force all previous reloads
6393 to be allocated. Also don't do this for reloads that have been
6396 for (i = j + 1; i < n_reloads; i++)
6398 int s = reload_order[i];
6400 if ((rld[s].in == 0 && rld[s].out == 0
6401 && ! rld[s].secondary_p)
6405 if ((rld[s].rclass != rld[r].rclass
6406 && reg_classes_intersect_p (rld[r].rclass,
6408 || rld[s].nregs < rld[r].nregs)
6415 allocate_reload_reg (chain, r, j == n_reloads - 1);
6419 /* Now allocate reload registers for anything non-optional that
6420 didn't get one yet. */
6421 for (j = 0; j < n_reloads; j++)
6423 int r = reload_order[j];
6425 /* Ignore reloads that got marked inoperative. */
6426 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6429 /* Skip reloads that already have a register allocated or are
6431 if (rld[r].reg_rtx != 0 || rld[r].optional)
6434 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6438 /* If that loop got all the way, we have won. */
6445 /* Loop around and try without any inheritance. */
6450 /* First undo everything done by the failed attempt
6451 to allocate with inheritance. */
6452 choose_reload_regs_init (chain, save_reload_reg_rtx);
6454 /* Some sanity tests to verify that the reloads found in the first
6455 pass are identical to the ones we have now. */
6456 gcc_assert (chain->n_reloads == n_reloads);
6458 for (i = 0; i < n_reloads; i++)
6460 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6462 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6463 for (j = 0; j < n_spills; j++)
6464 if (spill_regs[j] == chain->rld[i].regno)
6465 if (! set_reload_reg (j, i))
6466 failed_reload (chain->insn, i);
6470 /* If we thought we could inherit a reload, because it seemed that
6471 nothing else wanted the same reload register earlier in the insn,
6472 verify that assumption, now that all reloads have been assigned.
6473 Likewise for reloads where reload_override_in has been set. */
6475 /* If doing expensive optimizations, do one preliminary pass that doesn't
6476 cancel any inheritance, but removes reloads that have been needed only
6477 for reloads that we know can be inherited. */
6478 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6480 for (j = 0; j < n_reloads; j++)
6482 int r = reload_order[j];
6484 if (reload_inherited[r] && rld[r].reg_rtx)
6485 check_reg = rld[r].reg_rtx;
6486 else if (reload_override_in[r]
6487 && (REG_P (reload_override_in[r])
6488 || GET_CODE (reload_override_in[r]) == SUBREG))
6489 check_reg = reload_override_in[r];
6492 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6493 rld[r].opnum, rld[r].when_needed, rld[r].in,
6494 (reload_inherited[r]
6495 ? rld[r].out : const0_rtx),
6500 reload_inherited[r] = 0;
6501 reload_override_in[r] = 0;
6503 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6504 reload_override_in, then we do not need its related
6505 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6506 likewise for other reload types.
6507 We handle this by removing a reload when its only replacement
6508 is mentioned in reload_in of the reload we are going to inherit.
6509 A special case are auto_inc expressions; even if the input is
6510 inherited, we still need the address for the output. We can
6511 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6512 If we succeeded removing some reload and we are doing a preliminary
6513 pass just to remove such reloads, make another pass, since the
6514 removal of one reload might allow us to inherit another one. */
6516 && rld[r].out != rld[r].in
6517 && remove_address_replacements (rld[r].in) && pass)
6522 /* Now that reload_override_in is known valid,
6523 actually override reload_in. */
6524 for (j = 0; j < n_reloads; j++)
6525 if (reload_override_in[j])
6526 rld[j].in = reload_override_in[j];
6528 /* If this reload won't be done because it has been canceled or is
6529 optional and not inherited, clear reload_reg_rtx so other
6530 routines (such as subst_reloads) don't get confused. */
6531 for (j = 0; j < n_reloads; j++)
6532 if (rld[j].reg_rtx != 0
6533 && ((rld[j].optional && ! reload_inherited[j])
6534 || (rld[j].in == 0 && rld[j].out == 0
6535 && ! rld[j].secondary_p)))
6537 int regno = true_regnum (rld[j].reg_rtx);
6539 if (spill_reg_order[regno] >= 0)
6540 clear_reload_reg_in_use (regno, rld[j].opnum,
6541 rld[j].when_needed, rld[j].mode);
6543 reload_spill_index[j] = -1;
6546 /* Record which pseudos and which spill regs have output reloads. */
6547 for (j = 0; j < n_reloads; j++)
6549 int r = reload_order[j];
6551 i = reload_spill_index[r];
6553 /* I is nonneg if this reload uses a register.
6554 If rld[r].reg_rtx is 0, this is an optional reload
6555 that we opted to ignore. */
6556 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6557 && rld[r].reg_rtx != 0)
6559 int nregno = REGNO (rld[r].out_reg);
6562 if (nregno < FIRST_PSEUDO_REGISTER)
6563 nr = hard_regno_nregs[nregno][rld[r].mode];
6566 SET_REGNO_REG_SET (®_has_output_reload,
6571 nr = hard_regno_nregs[i][rld[r].mode];
6573 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6576 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6577 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6578 || rld[r].when_needed == RELOAD_FOR_INSN);
6583 /* Deallocate the reload register for reload R. This is called from
6584 remove_address_replacements. */
6587 deallocate_reload_reg (int r)
6591 if (! rld[r].reg_rtx)
6593 regno = true_regnum (rld[r].reg_rtx);
6595 if (spill_reg_order[regno] >= 0)
6596 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6598 reload_spill_index[r] = -1;
6601 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6602 reloads of the same item for fear that we might not have enough reload
6603 registers. However, normally they will get the same reload register
6604 and hence actually need not be loaded twice.
6606 Here we check for the most common case of this phenomenon: when we have
6607 a number of reloads for the same object, each of which were allocated
6608 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6609 reload, and is not modified in the insn itself. If we find such,
6610 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6611 This will not increase the number of spill registers needed and will
6612 prevent redundant code. */
6615 merge_assigned_reloads (rtx insn)
6619 /* Scan all the reloads looking for ones that only load values and
6620 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6621 assigned and not modified by INSN. */
6623 for (i = 0; i < n_reloads; i++)
6625 int conflicting_input = 0;
6626 int max_input_address_opnum = -1;
6627 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6629 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6630 || rld[i].out != 0 || rld[i].reg_rtx == 0
6631 || reg_set_p (rld[i].reg_rtx, insn))
6634 /* Look at all other reloads. Ensure that the only use of this
6635 reload_reg_rtx is in a reload that just loads the same value
6636 as we do. Note that any secondary reloads must be of the identical
6637 class since the values, modes, and result registers are the
6638 same, so we need not do anything with any secondary reloads. */
6640 for (j = 0; j < n_reloads; j++)
6642 if (i == j || rld[j].reg_rtx == 0
6643 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6647 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6648 && rld[j].opnum > max_input_address_opnum)
6649 max_input_address_opnum = rld[j].opnum;
6651 /* If the reload regs aren't exactly the same (e.g, different modes)
6652 or if the values are different, we can't merge this reload.
6653 But if it is an input reload, we might still merge
6654 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6656 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6657 || rld[j].out != 0 || rld[j].in == 0
6658 || ! rtx_equal_p (rld[i].in, rld[j].in))
6660 if (rld[j].when_needed != RELOAD_FOR_INPUT
6661 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6662 || rld[i].opnum > rld[j].opnum)
6663 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6665 conflicting_input = 1;
6666 if (min_conflicting_input_opnum > rld[j].opnum)
6667 min_conflicting_input_opnum = rld[j].opnum;
6671 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6672 we, in fact, found any matching reloads. */
6675 && max_input_address_opnum <= min_conflicting_input_opnum)
6677 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6679 for (j = 0; j < n_reloads; j++)
6680 if (i != j && rld[j].reg_rtx != 0
6681 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6682 && (! conflicting_input
6683 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6684 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6686 rld[i].when_needed = RELOAD_OTHER;
6688 reload_spill_index[j] = -1;
6689 transfer_replacements (i, j);
6692 /* If this is now RELOAD_OTHER, look for any reloads that
6693 load parts of this operand and set them to
6694 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6695 RELOAD_OTHER for outputs. Note that this test is
6696 equivalent to looking for reloads for this operand
6699 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6700 it may share registers with a RELOAD_FOR_INPUT, so we can
6701 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6702 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6704 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6705 instruction is assigned the same register as the earlier
6706 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6707 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6708 instruction to be deleted later on. */
6710 if (rld[i].when_needed == RELOAD_OTHER)
6711 for (j = 0; j < n_reloads; j++)
6713 && rld[j].when_needed != RELOAD_OTHER
6714 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6715 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6716 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6717 && (! conflicting_input
6718 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6719 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6720 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6726 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6727 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6728 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6730 /* Check to see if we accidentally converted two
6731 reloads that use the same reload register with
6732 different inputs to the same type. If so, the
6733 resulting code won't work. */
6735 for (k = 0; k < j; k++)
6736 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6737 || rld[k].when_needed != rld[j].when_needed
6738 || !rtx_equal_p (rld[k].reg_rtx,
6740 || rtx_equal_p (rld[k].in,
6747 /* These arrays are filled by emit_reload_insns and its subroutines. */
6748 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6749 static rtx other_input_address_reload_insns = 0;
6750 static rtx other_input_reload_insns = 0;
6751 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6752 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6753 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6754 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6755 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6756 static rtx operand_reload_insns = 0;
6757 static rtx other_operand_reload_insns = 0;
6758 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6760 /* Values to be put in spill_reg_store are put here first. */
6761 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6762 static HARD_REG_SET reg_reloaded_died;
6764 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6765 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6766 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6767 adjusted register, and return true. Otherwise, return false. */
6769 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6770 enum reg_class new_class,
6771 enum machine_mode new_mode)
6776 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6778 unsigned regno = REGNO (reg);
6780 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6782 if (GET_MODE (reg) != new_mode)
6784 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6786 if (hard_regno_nregs[regno][new_mode]
6787 > hard_regno_nregs[regno][GET_MODE (reg)])
6789 reg = reload_adjust_reg_for_mode (reg, new_mode);
6797 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6798 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6799 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6800 adjusted register, and return true. Otherwise, return false. */
6802 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6803 enum insn_code icode)
6806 enum reg_class new_class = scratch_reload_class (icode);
6807 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6809 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6810 new_class, new_mode);
6813 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6814 has the number J. OLD contains the value to be used as input. */
6817 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6820 rtx insn = chain->insn;
6822 rtx oldequiv_reg = 0;
6825 enum machine_mode mode;
6828 /* delete_output_reload is only invoked properly if old contains
6829 the original pseudo register. Since this is replaced with a
6830 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6831 find the pseudo in RELOAD_IN_REG. */
6832 if (reload_override_in[j]
6833 && REG_P (rl->in_reg))
6840 else if (REG_P (oldequiv))
6841 oldequiv_reg = oldequiv;
6842 else if (GET_CODE (oldequiv) == SUBREG)
6843 oldequiv_reg = SUBREG_REG (oldequiv);
6845 reloadreg = reload_reg_rtx_for_input[j];
6846 mode = GET_MODE (reloadreg);
6848 /* If we are reloading from a register that was recently stored in
6849 with an output-reload, see if we can prove there was
6850 actually no need to store the old value in it. */
6852 if (optimize && REG_P (oldequiv)
6853 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6854 && spill_reg_store[REGNO (oldequiv)]
6856 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6857 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6859 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6861 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6864 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6865 oldequiv = SUBREG_REG (oldequiv);
6866 if (GET_MODE (oldequiv) != VOIDmode
6867 && mode != GET_MODE (oldequiv))
6868 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6870 /* Switch to the right place to emit the reload insns. */
6871 switch (rl->when_needed)
6874 where = &other_input_reload_insns;
6876 case RELOAD_FOR_INPUT:
6877 where = &input_reload_insns[rl->opnum];
6879 case RELOAD_FOR_INPUT_ADDRESS:
6880 where = &input_address_reload_insns[rl->opnum];
6882 case RELOAD_FOR_INPADDR_ADDRESS:
6883 where = &inpaddr_address_reload_insns[rl->opnum];
6885 case RELOAD_FOR_OUTPUT_ADDRESS:
6886 where = &output_address_reload_insns[rl->opnum];
6888 case RELOAD_FOR_OUTADDR_ADDRESS:
6889 where = &outaddr_address_reload_insns[rl->opnum];
6891 case RELOAD_FOR_OPERAND_ADDRESS:
6892 where = &operand_reload_insns;
6894 case RELOAD_FOR_OPADDR_ADDR:
6895 where = &other_operand_reload_insns;
6897 case RELOAD_FOR_OTHER_ADDRESS:
6898 where = &other_input_address_reload_insns;
6904 push_to_sequence (*where);
6906 /* Auto-increment addresses must be reloaded in a special way. */
6907 if (rl->out && ! rl->out_reg)
6909 /* We are not going to bother supporting the case where a
6910 incremented register can't be copied directly from
6911 OLDEQUIV since this seems highly unlikely. */
6912 gcc_assert (rl->secondary_in_reload < 0);
6914 if (reload_inherited[j])
6915 oldequiv = reloadreg;
6917 old = XEXP (rl->in_reg, 0);
6919 if (optimize && REG_P (oldequiv)
6920 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6921 && spill_reg_store[REGNO (oldequiv)]
6923 && (dead_or_set_p (insn,
6924 spill_reg_stored_to[REGNO (oldequiv)])
6925 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6927 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6929 /* Prevent normal processing of this reload. */
6931 /* Output a special code sequence for this case. */
6932 new_spill_reg_store[REGNO (reloadreg)]
6933 = inc_for_reload (reloadreg, oldequiv, rl->out,
6937 /* If we are reloading a pseudo-register that was set by the previous
6938 insn, see if we can get rid of that pseudo-register entirely
6939 by redirecting the previous insn into our reload register. */
6941 else if (optimize && REG_P (old)
6942 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6943 && dead_or_set_p (insn, old)
6944 /* This is unsafe if some other reload
6945 uses the same reg first. */
6946 && ! conflicts_with_override (reloadreg)
6947 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6948 rl->when_needed, old, rl->out, j, 0))
6950 rtx temp = PREV_INSN (insn);
6951 while (temp && NOTE_P (temp))
6952 temp = PREV_INSN (temp);
6954 && NONJUMP_INSN_P (temp)
6955 && GET_CODE (PATTERN (temp)) == SET
6956 && SET_DEST (PATTERN (temp)) == old
6957 /* Make sure we can access insn_operand_constraint. */
6958 && asm_noperands (PATTERN (temp)) < 0
6959 /* This is unsafe if operand occurs more than once in current
6960 insn. Perhaps some occurrences aren't reloaded. */
6961 && count_occurrences (PATTERN (insn), old, 0) == 1)
6963 rtx old = SET_DEST (PATTERN (temp));
6964 /* Store into the reload register instead of the pseudo. */
6965 SET_DEST (PATTERN (temp)) = reloadreg;
6967 /* Verify that resulting insn is valid. */
6968 extract_insn (temp);
6969 if (constrain_operands (1))
6971 /* If the previous insn is an output reload, the source is
6972 a reload register, and its spill_reg_store entry will
6973 contain the previous destination. This is now
6975 if (REG_P (SET_SRC (PATTERN (temp)))
6976 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6978 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6979 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6982 /* If these are the only uses of the pseudo reg,
6983 pretend for GDB it lives in the reload reg we used. */
6984 if (REG_N_DEATHS (REGNO (old)) == 1
6985 && REG_N_SETS (REGNO (old)) == 1)
6987 reg_renumber[REGNO (old)] = REGNO (reloadreg);
6988 if (ira_conflicts_p)
6989 /* Inform IRA about the change. */
6990 ira_mark_allocation_change (REGNO (old));
6991 alter_reg (REGNO (old), -1, false);
6997 SET_DEST (PATTERN (temp)) = old;
7002 /* We can't do that, so output an insn to load RELOADREG. */
7004 /* If we have a secondary reload, pick up the secondary register
7005 and icode, if any. If OLDEQUIV and OLD are different or
7006 if this is an in-out reload, recompute whether or not we
7007 still need a secondary register and what the icode should
7008 be. If we still need a secondary register and the class or
7009 icode is different, go back to reloading from OLD if using
7010 OLDEQUIV means that we got the wrong type of register. We
7011 cannot have different class or icode due to an in-out reload
7012 because we don't make such reloads when both the input and
7013 output need secondary reload registers. */
7015 if (! special && rl->secondary_in_reload >= 0)
7017 rtx second_reload_reg = 0;
7018 rtx third_reload_reg = 0;
7019 int secondary_reload = rl->secondary_in_reload;
7020 rtx real_oldequiv = oldequiv;
7023 enum insn_code icode;
7024 enum insn_code tertiary_icode = CODE_FOR_nothing;
7026 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7027 and similarly for OLD.
7028 See comments in get_secondary_reload in reload.c. */
7029 /* If it is a pseudo that cannot be replaced with its
7030 equivalent MEM, we must fall back to reload_in, which
7031 will have all the necessary substitutions registered.
7032 Likewise for a pseudo that can't be replaced with its
7033 equivalent constant.
7035 Take extra care for subregs of such pseudos. Note that
7036 we cannot use reg_equiv_mem in this case because it is
7037 not in the right mode. */
7040 if (GET_CODE (tmp) == SUBREG)
7041 tmp = SUBREG_REG (tmp);
7043 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7044 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7045 || reg_equiv_constant[REGNO (tmp)] != 0))
7047 if (! reg_equiv_mem[REGNO (tmp)]
7048 || num_not_at_initial_offset
7049 || GET_CODE (oldequiv) == SUBREG)
7050 real_oldequiv = rl->in;
7052 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7056 if (GET_CODE (tmp) == SUBREG)
7057 tmp = SUBREG_REG (tmp);
7059 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7060 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7061 || reg_equiv_constant[REGNO (tmp)] != 0))
7063 if (! reg_equiv_mem[REGNO (tmp)]
7064 || num_not_at_initial_offset
7065 || GET_CODE (old) == SUBREG)
7068 real_old = reg_equiv_mem[REGNO (tmp)];
7071 second_reload_reg = rld[secondary_reload].reg_rtx;
7072 if (rld[secondary_reload].secondary_in_reload >= 0)
7074 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7076 third_reload_reg = rld[tertiary_reload].reg_rtx;
7077 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7078 /* We'd have to add more code for quartary reloads. */
7079 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7081 icode = rl->secondary_in_icode;
7083 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7084 || (rl->in != 0 && rl->out != 0))
7086 secondary_reload_info sri, sri2;
7087 enum reg_class new_class, new_t_class;
7089 sri.icode = CODE_FOR_nothing;
7090 sri.prev_sri = NULL;
7091 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7094 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7095 second_reload_reg = 0;
7096 else if (new_class == NO_REGS)
7098 if (reload_adjust_reg_for_icode (&second_reload_reg,
7099 third_reload_reg, sri.icode))
7100 icode = sri.icode, third_reload_reg = 0;
7102 oldequiv = old, real_oldequiv = real_old;
7104 else if (sri.icode != CODE_FOR_nothing)
7105 /* We currently lack a way to express this in reloads. */
7109 sri2.icode = CODE_FOR_nothing;
7110 sri2.prev_sri = &sri;
7111 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7112 new_class, mode, &sri);
7113 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7115 if (reload_adjust_reg_for_temp (&second_reload_reg,
7118 third_reload_reg = 0, tertiary_icode = sri2.icode;
7120 oldequiv = old, real_oldequiv = real_old;
7122 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7124 rtx intermediate = second_reload_reg;
7126 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7128 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7131 second_reload_reg = intermediate;
7132 tertiary_icode = sri2.icode;
7135 oldequiv = old, real_oldequiv = real_old;
7137 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7139 rtx intermediate = second_reload_reg;
7141 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7143 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7146 second_reload_reg = intermediate;
7147 tertiary_icode = sri2.icode;
7150 oldequiv = old, real_oldequiv = real_old;
7153 /* This could be handled more intelligently too. */
7154 oldequiv = old, real_oldequiv = real_old;
7158 /* If we still need a secondary reload register, check
7159 to see if it is being used as a scratch or intermediate
7160 register and generate code appropriately. If we need
7161 a scratch register, use REAL_OLDEQUIV since the form of
7162 the insn may depend on the actual address if it is
7165 if (second_reload_reg)
7167 if (icode != CODE_FOR_nothing)
7169 /* We'd have to add extra code to handle this case. */
7170 gcc_assert (!third_reload_reg);
7172 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7173 second_reload_reg));
7178 /* See if we need a scratch register to load the
7179 intermediate register (a tertiary reload). */
7180 if (tertiary_icode != CODE_FOR_nothing)
7182 emit_insn ((GEN_FCN (tertiary_icode)
7183 (second_reload_reg, real_oldequiv,
7184 third_reload_reg)));
7186 else if (third_reload_reg)
7188 gen_reload (third_reload_reg, real_oldequiv,
7191 gen_reload (second_reload_reg, third_reload_reg,
7196 gen_reload (second_reload_reg, real_oldequiv,
7200 oldequiv = second_reload_reg;
7205 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7207 rtx real_oldequiv = oldequiv;
7209 if ((REG_P (oldequiv)
7210 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7211 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7212 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7213 || (GET_CODE (oldequiv) == SUBREG
7214 && REG_P (SUBREG_REG (oldequiv))
7215 && (REGNO (SUBREG_REG (oldequiv))
7216 >= FIRST_PSEUDO_REGISTER)
7217 && ((reg_equiv_memory_loc
7218 [REGNO (SUBREG_REG (oldequiv))] != 0)
7219 || (reg_equiv_constant
7220 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7221 || (CONSTANT_P (oldequiv)
7222 && (PREFERRED_RELOAD_CLASS (oldequiv,
7223 REGNO_REG_CLASS (REGNO (reloadreg)))
7225 real_oldequiv = rl->in;
7226 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7230 if (flag_non_call_exceptions)
7231 copy_eh_notes (insn, get_insns ());
7233 /* End this sequence. */
7234 *where = get_insns ();
7237 /* Update reload_override_in so that delete_address_reloads_1
7238 can see the actual register usage. */
7240 reload_override_in[j] = oldequiv;
7243 /* Generate insns to for the output reload RL, which is for the insn described
7244 by CHAIN and has the number J. */
7246 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7250 rtx insn = chain->insn;
7253 enum machine_mode mode;
7257 if (rl->when_needed == RELOAD_OTHER)
7260 push_to_sequence (output_reload_insns[rl->opnum]);
7262 rl_reg_rtx = reload_reg_rtx_for_output[j];
7263 mode = GET_MODE (rl_reg_rtx);
7265 reloadreg = rl_reg_rtx;
7267 /* If we need two reload regs, set RELOADREG to the intermediate
7268 one, since it will be stored into OLD. We might need a secondary
7269 register only for an input reload, so check again here. */
7271 if (rl->secondary_out_reload >= 0)
7274 int secondary_reload = rl->secondary_out_reload;
7275 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7277 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7278 && reg_equiv_mem[REGNO (old)] != 0)
7279 real_old = reg_equiv_mem[REGNO (old)];
7281 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7283 rtx second_reloadreg = reloadreg;
7284 reloadreg = rld[secondary_reload].reg_rtx;
7286 /* See if RELOADREG is to be used as a scratch register
7287 or as an intermediate register. */
7288 if (rl->secondary_out_icode != CODE_FOR_nothing)
7290 /* We'd have to add extra code to handle this case. */
7291 gcc_assert (tertiary_reload < 0);
7293 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7294 (real_old, second_reloadreg, reloadreg)));
7299 /* See if we need both a scratch and intermediate reload
7302 enum insn_code tertiary_icode
7303 = rld[secondary_reload].secondary_out_icode;
7305 /* We'd have to add more code for quartary reloads. */
7306 gcc_assert (tertiary_reload < 0
7307 || rld[tertiary_reload].secondary_out_reload < 0);
7309 if (GET_MODE (reloadreg) != mode)
7310 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7312 if (tertiary_icode != CODE_FOR_nothing)
7314 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7317 /* Copy primary reload reg to secondary reload reg.
7318 (Note that these have been swapped above, then
7319 secondary reload reg to OLD using our insn.) */
7321 /* If REAL_OLD is a paradoxical SUBREG, remove it
7322 and try to put the opposite SUBREG on
7324 if (GET_CODE (real_old) == SUBREG
7325 && (GET_MODE_SIZE (GET_MODE (real_old))
7326 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7327 && 0 != (tem = gen_lowpart_common
7328 (GET_MODE (SUBREG_REG (real_old)),
7330 real_old = SUBREG_REG (real_old), reloadreg = tem;
7332 gen_reload (reloadreg, second_reloadreg,
7333 rl->opnum, rl->when_needed);
7334 emit_insn ((GEN_FCN (tertiary_icode)
7335 (real_old, reloadreg, third_reloadreg)));
7341 /* Copy between the reload regs here and then to
7344 gen_reload (reloadreg, second_reloadreg,
7345 rl->opnum, rl->when_needed);
7346 if (tertiary_reload >= 0)
7348 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7350 gen_reload (third_reloadreg, reloadreg,
7351 rl->opnum, rl->when_needed);
7352 reloadreg = third_reloadreg;
7359 /* Output the last reload insn. */
7364 /* Don't output the last reload if OLD is not the dest of
7365 INSN and is in the src and is clobbered by INSN. */
7366 if (! flag_expensive_optimizations
7368 || !(set = single_set (insn))
7369 || rtx_equal_p (old, SET_DEST (set))
7370 || !reg_mentioned_p (old, SET_SRC (set))
7371 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7372 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7373 gen_reload (old, reloadreg, rl->opnum,
7377 /* Look at all insns we emitted, just to be safe. */
7378 for (p = get_insns (); p; p = NEXT_INSN (p))
7381 rtx pat = PATTERN (p);
7383 /* If this output reload doesn't come from a spill reg,
7384 clear any memory of reloaded copies of the pseudo reg.
7385 If this output reload comes from a spill reg,
7386 reg_has_output_reload will make this do nothing. */
7387 note_stores (pat, forget_old_reloads_1, NULL);
7389 if (reg_mentioned_p (rl_reg_rtx, pat))
7391 rtx set = single_set (insn);
7392 if (reload_spill_index[j] < 0
7394 && SET_SRC (set) == rl_reg_rtx)
7396 int src = REGNO (SET_SRC (set));
7398 reload_spill_index[j] = src;
7399 SET_HARD_REG_BIT (reg_is_output_reload, src);
7400 if (find_regno_note (insn, REG_DEAD, src))
7401 SET_HARD_REG_BIT (reg_reloaded_died, src);
7403 if (HARD_REGISTER_P (rl_reg_rtx))
7405 int s = rl->secondary_out_reload;
7406 set = single_set (p);
7407 /* If this reload copies only to the secondary reload
7408 register, the secondary reload does the actual
7410 if (s >= 0 && set == NULL_RTX)
7411 /* We can't tell what function the secondary reload
7412 has and where the actual store to the pseudo is
7413 made; leave new_spill_reg_store alone. */
7416 && SET_SRC (set) == rl_reg_rtx
7417 && SET_DEST (set) == rld[s].reg_rtx)
7419 /* Usually the next instruction will be the
7420 secondary reload insn; if we can confirm
7421 that it is, setting new_spill_reg_store to
7422 that insn will allow an extra optimization. */
7423 rtx s_reg = rld[s].reg_rtx;
7424 rtx next = NEXT_INSN (p);
7425 rld[s].out = rl->out;
7426 rld[s].out_reg = rl->out_reg;
7427 set = single_set (next);
7428 if (set && SET_SRC (set) == s_reg
7429 && ! new_spill_reg_store[REGNO (s_reg)])
7431 SET_HARD_REG_BIT (reg_is_output_reload,
7433 new_spill_reg_store[REGNO (s_reg)] = next;
7437 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7442 if (rl->when_needed == RELOAD_OTHER)
7444 emit_insn (other_output_reload_insns[rl->opnum]);
7445 other_output_reload_insns[rl->opnum] = get_insns ();
7448 output_reload_insns[rl->opnum] = get_insns ();
7450 if (flag_non_call_exceptions)
7451 copy_eh_notes (insn, get_insns ());
7456 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7457 and has the number J. */
7459 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7461 rtx insn = chain->insn;
7462 rtx old = (rl->in && MEM_P (rl->in)
7463 ? rl->in_reg : rl->in);
7464 rtx reg_rtx = rl->reg_rtx;
7468 enum machine_mode mode;
7470 /* Determine the mode to reload in.
7471 This is very tricky because we have three to choose from.
7472 There is the mode the insn operand wants (rl->inmode).
7473 There is the mode of the reload register RELOADREG.
7474 There is the intrinsic mode of the operand, which we could find
7475 by stripping some SUBREGs.
7476 It turns out that RELOADREG's mode is irrelevant:
7477 we can change that arbitrarily.
7479 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7480 then the reload reg may not support QImode moves, so use SImode.
7481 If foo is in memory due to spilling a pseudo reg, this is safe,
7482 because the QImode value is in the least significant part of a
7483 slot big enough for a SImode. If foo is some other sort of
7484 memory reference, then it is impossible to reload this case,
7485 so previous passes had better make sure this never happens.
7487 Then consider a one-word union which has SImode and one of its
7488 members is a float, being fetched as (SUBREG:SF union:SI).
7489 We must fetch that as SFmode because we could be loading into
7490 a float-only register. In this case OLD's mode is correct.
7492 Consider an immediate integer: it has VOIDmode. Here we need
7493 to get a mode from something else.
7495 In some cases, there is a fourth mode, the operand's
7496 containing mode. If the insn specifies a containing mode for
7497 this operand, it overrides all others.
7499 I am not sure whether the algorithm here is always right,
7500 but it does the right things in those cases. */
7502 mode = GET_MODE (old);
7503 if (mode == VOIDmode)
7506 /* We cannot use gen_lowpart_common since it can do the wrong thing
7507 when REG_RTX has a multi-word mode. Note that REG_RTX must
7508 always be a REG here. */
7509 if (GET_MODE (reg_rtx) != mode)
7510 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7512 reload_reg_rtx_for_input[j] = reg_rtx;
7515 /* AUTO_INC reloads need to be handled even if inherited. We got an
7516 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7517 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7518 && ! rtx_equal_p (reg_rtx, old)
7520 emit_input_reload_insns (chain, rld + j, old, j);
7522 /* When inheriting a wider reload, we have a MEM in rl->in,
7523 e.g. inheriting a SImode output reload for
7524 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7525 if (optimize && reload_inherited[j] && rl->in
7527 && MEM_P (rl->in_reg)
7528 && reload_spill_index[j] >= 0
7529 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7530 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7532 /* If we are reloading a register that was recently stored in with an
7533 output-reload, see if we can prove there was
7534 actually no need to store the old value in it. */
7537 && (reload_inherited[j] || reload_override_in[j])
7540 && spill_reg_store[REGNO (reg_rtx)] != 0
7542 /* There doesn't seem to be any reason to restrict this to pseudos
7543 and doing so loses in the case where we are copying from a
7544 register of the wrong class. */
7545 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7547 /* The insn might have already some references to stackslots
7548 replaced by MEMs, while reload_out_reg still names the
7550 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7551 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7552 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7555 /* Do output reloading for reload RL, which is for the insn described by
7556 CHAIN and has the number J.
7557 ??? At some point we need to support handling output reloads of
7558 JUMP_INSNs or insns that set cc0. */
7560 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7563 rtx insn = chain->insn;
7564 /* If this is an output reload that stores something that is
7565 not loaded in this same reload, see if we can eliminate a previous
7567 rtx pseudo = rl->out_reg;
7568 rtx reg_rtx = rl->reg_rtx;
7570 if (rl->out && reg_rtx)
7572 enum machine_mode mode;
7574 /* Determine the mode to reload in.
7575 See comments above (for input reloading). */
7576 mode = GET_MODE (rl->out);
7577 if (mode == VOIDmode)
7579 /* VOIDmode should never happen for an output. */
7580 if (asm_noperands (PATTERN (insn)) < 0)
7581 /* It's the compiler's fault. */
7582 fatal_insn ("VOIDmode on an output", insn);
7583 error_for_asm (insn, "output operand is constant in %<asm%>");
7584 /* Prevent crash--use something we know is valid. */
7586 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7588 if (GET_MODE (reg_rtx) != mode)
7589 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7591 reload_reg_rtx_for_output[j] = reg_rtx;
7596 && ! rtx_equal_p (rl->in_reg, pseudo)
7597 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7598 && reg_last_reload_reg[REGNO (pseudo)])
7600 int pseudo_no = REGNO (pseudo);
7601 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7603 /* We don't need to test full validity of last_regno for
7604 inherit here; we only want to know if the store actually
7605 matches the pseudo. */
7606 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7607 && reg_reloaded_contents[last_regno] == pseudo_no
7608 && spill_reg_store[last_regno]
7609 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7610 delete_output_reload (insn, j, last_regno, reg_rtx);
7616 || rtx_equal_p (old, reg_rtx))
7619 /* An output operand that dies right away does need a reload,
7620 but need not be copied from it. Show the new location in the
7622 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7623 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7625 XEXP (note, 0) = reg_rtx;
7628 /* Likewise for a SUBREG of an operand that dies. */
7629 else if (GET_CODE (old) == SUBREG
7630 && REG_P (SUBREG_REG (old))
7631 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7634 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7637 else if (GET_CODE (old) == SCRATCH)
7638 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7639 but we don't want to make an output reload. */
7642 /* If is a JUMP_INSN, we can't support output reloads yet. */
7643 gcc_assert (NONJUMP_INSN_P (insn));
7645 emit_output_reload_insns (chain, rld + j, j);
7648 /* A reload copies values of MODE from register SRC to register DEST.
7649 Return true if it can be treated for inheritance purposes like a
7650 group of reloads, each one reloading a single hard register. The
7651 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7652 occupy the same number of hard registers. */
7655 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7656 int src ATTRIBUTE_UNUSED,
7657 enum machine_mode mode ATTRIBUTE_UNUSED)
7659 #ifdef CANNOT_CHANGE_MODE_CLASS
7660 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7661 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7667 /* Output insns to reload values in and out of the chosen reload regs. */
7670 emit_reload_insns (struct insn_chain *chain)
7672 rtx insn = chain->insn;
7676 CLEAR_HARD_REG_SET (reg_reloaded_died);
7678 for (j = 0; j < reload_n_operands; j++)
7679 input_reload_insns[j] = input_address_reload_insns[j]
7680 = inpaddr_address_reload_insns[j]
7681 = output_reload_insns[j] = output_address_reload_insns[j]
7682 = outaddr_address_reload_insns[j]
7683 = other_output_reload_insns[j] = 0;
7684 other_input_address_reload_insns = 0;
7685 other_input_reload_insns = 0;
7686 operand_reload_insns = 0;
7687 other_operand_reload_insns = 0;
7689 /* Dump reloads into the dump file. */
7692 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7693 debug_reload_to_stream (dump_file);
7696 /* Now output the instructions to copy the data into and out of the
7697 reload registers. Do these in the order that the reloads were reported,
7698 since reloads of base and index registers precede reloads of operands
7699 and the operands may need the base and index registers reloaded. */
7701 for (j = 0; j < n_reloads; j++)
7703 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7707 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7708 new_spill_reg_store[i] = 0;
7711 do_input_reload (chain, rld + j, j);
7712 do_output_reload (chain, rld + j, j);
7715 /* Now write all the insns we made for reloads in the order expected by
7716 the allocation functions. Prior to the insn being reloaded, we write
7717 the following reloads:
7719 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7721 RELOAD_OTHER reloads.
7723 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7724 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7725 RELOAD_FOR_INPUT reload for the operand.
7727 RELOAD_FOR_OPADDR_ADDRS reloads.
7729 RELOAD_FOR_OPERAND_ADDRESS reloads.
7731 After the insn being reloaded, we write the following:
7733 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7734 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7735 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7736 reloads for the operand. The RELOAD_OTHER output reloads are
7737 output in descending order by reload number. */
7739 emit_insn_before (other_input_address_reload_insns, insn);
7740 emit_insn_before (other_input_reload_insns, insn);
7742 for (j = 0; j < reload_n_operands; j++)
7744 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7745 emit_insn_before (input_address_reload_insns[j], insn);
7746 emit_insn_before (input_reload_insns[j], insn);
7749 emit_insn_before (other_operand_reload_insns, insn);
7750 emit_insn_before (operand_reload_insns, insn);
7752 for (j = 0; j < reload_n_operands; j++)
7754 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7755 x = emit_insn_after (output_address_reload_insns[j], x);
7756 x = emit_insn_after (output_reload_insns[j], x);
7757 emit_insn_after (other_output_reload_insns[j], x);
7760 /* For all the spill regs newly reloaded in this instruction,
7761 record what they were reloaded from, so subsequent instructions
7762 can inherit the reloads.
7764 Update spill_reg_store for the reloads of this insn.
7765 Copy the elements that were updated in the loop above. */
7767 for (j = 0; j < n_reloads; j++)
7769 int r = reload_order[j];
7770 int i = reload_spill_index[r];
7772 /* If this is a non-inherited input reload from a pseudo, we must
7773 clear any memory of a previous store to the same pseudo. Only do
7774 something if there will not be an output reload for the pseudo
7776 if (rld[r].in_reg != 0
7777 && ! (reload_inherited[r] || reload_override_in[r]))
7779 rtx reg = rld[r].in_reg;
7781 if (GET_CODE (reg) == SUBREG)
7782 reg = SUBREG_REG (reg);
7785 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7786 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7788 int nregno = REGNO (reg);
7790 if (reg_last_reload_reg[nregno])
7792 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7794 if (reg_reloaded_contents[last_regno] == nregno)
7795 spill_reg_store[last_regno] = 0;
7800 /* I is nonneg if this reload used a register.
7801 If rld[r].reg_rtx is 0, this is an optional reload
7802 that we opted to ignore. */
7804 if (i >= 0 && rld[r].reg_rtx != 0)
7806 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7809 /* For a multi register reload, we need to check if all or part
7810 of the value lives to the end. */
7811 for (k = 0; k < nr; k++)
7812 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7813 rld[r].when_needed))
7814 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7816 /* Maybe the spill reg contains a copy of reload_out. */
7818 && (REG_P (rld[r].out)
7822 || REG_P (rld[r].out_reg)))
7825 enum machine_mode mode;
7828 reg = reload_reg_rtx_for_output[r];
7829 mode = GET_MODE (reg);
7830 regno = REGNO (reg);
7831 nregs = hard_regno_nregs[regno][mode];
7832 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7833 rld[r].when_needed))
7835 rtx out = (REG_P (rld[r].out)
7839 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7840 int out_regno = REGNO (out);
7841 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7842 : hard_regno_nregs[out_regno][mode]);
7845 spill_reg_store[regno] = new_spill_reg_store[regno];
7846 spill_reg_stored_to[regno] = out;
7847 reg_last_reload_reg[out_regno] = reg;
7849 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7850 && nregs == out_nregs
7851 && inherit_piecemeal_p (out_regno, regno, mode));
7853 /* If OUT_REGNO is a hard register, it may occupy more than
7854 one register. If it does, say what is in the
7855 rest of the registers assuming that both registers
7856 agree on how many words the object takes. If not,
7857 invalidate the subsequent registers. */
7859 if (HARD_REGISTER_NUM_P (out_regno))
7860 for (k = 1; k < out_nregs; k++)
7861 reg_last_reload_reg[out_regno + k]
7862 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7864 /* Now do the inverse operation. */
7865 for (k = 0; k < nregs; k++)
7867 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7868 reg_reloaded_contents[regno + k]
7869 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7872 reg_reloaded_insn[regno + k] = insn;
7873 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7874 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7875 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7878 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7883 /* Maybe the spill reg contains a copy of reload_in. Only do
7884 something if there will not be an output reload for
7885 the register being reloaded. */
7886 else if (rld[r].out_reg == 0
7888 && ((REG_P (rld[r].in)
7889 && !HARD_REGISTER_P (rld[r].in)
7890 && !REGNO_REG_SET_P (®_has_output_reload,
7892 || (REG_P (rld[r].in_reg)
7893 && !REGNO_REG_SET_P (®_has_output_reload,
7894 REGNO (rld[r].in_reg))))
7895 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7898 enum machine_mode mode;
7901 reg = reload_reg_rtx_for_input[r];
7902 mode = GET_MODE (reg);
7903 regno = REGNO (reg);
7904 nregs = hard_regno_nregs[regno][mode];
7905 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7906 rld[r].when_needed))
7913 if (REG_P (rld[r].in)
7914 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7916 else if (REG_P (rld[r].in_reg))
7919 in = XEXP (rld[r].in_reg, 0);
7920 in_regno = REGNO (in);
7922 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7923 : hard_regno_nregs[in_regno][mode]);
7925 reg_last_reload_reg[in_regno] = reg;
7927 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7928 && nregs == in_nregs
7929 && inherit_piecemeal_p (regno, in_regno, mode));
7931 if (HARD_REGISTER_NUM_P (in_regno))
7932 for (k = 1; k < in_nregs; k++)
7933 reg_last_reload_reg[in_regno + k]
7934 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7936 /* Unless we inherited this reload, show we haven't
7937 recently done a store.
7938 Previous stores of inherited auto_inc expressions
7939 also have to be discarded. */
7940 if (! reload_inherited[r]
7941 || (rld[r].out && ! rld[r].out_reg))
7942 spill_reg_store[regno] = 0;
7944 for (k = 0; k < nregs; k++)
7946 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7947 reg_reloaded_contents[regno + k]
7948 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7951 reg_reloaded_insn[regno + k] = insn;
7952 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7953 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7954 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7957 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7964 /* The following if-statement was #if 0'd in 1.34 (or before...).
7965 It's reenabled in 1.35 because supposedly nothing else
7966 deals with this problem. */
7968 /* If a register gets output-reloaded from a non-spill register,
7969 that invalidates any previous reloaded copy of it.
7970 But forget_old_reloads_1 won't get to see it, because
7971 it thinks only about the original insn. So invalidate it here.
7972 Also do the same thing for RELOAD_OTHER constraints where the
7973 output is discarded. */
7975 && ((rld[r].out != 0
7976 && (REG_P (rld[r].out)
7977 || (MEM_P (rld[r].out)
7978 && REG_P (rld[r].out_reg))))
7979 || (rld[r].out == 0 && rld[r].out_reg
7980 && REG_P (rld[r].out_reg))))
7982 rtx out = ((rld[r].out && REG_P (rld[r].out))
7983 ? rld[r].out : rld[r].out_reg);
7984 int out_regno = REGNO (out);
7985 enum machine_mode mode = GET_MODE (out);
7987 /* REG_RTX is now set or clobbered by the main instruction.
7988 As the comment above explains, forget_old_reloads_1 only
7989 sees the original instruction, and there is no guarantee
7990 that the original instruction also clobbered REG_RTX.
7991 For example, if find_reloads sees that the input side of
7992 a matched operand pair dies in this instruction, it may
7993 use the input register as the reload register.
7995 Calling forget_old_reloads_1 is a waste of effort if
7996 REG_RTX is also the output register.
7998 If we know that REG_RTX holds the value of a pseudo
7999 register, the code after the call will record that fact. */
8000 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8001 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8003 if (!HARD_REGISTER_NUM_P (out_regno))
8005 rtx src_reg, store_insn = NULL_RTX;
8007 reg_last_reload_reg[out_regno] = 0;
8009 /* If we can find a hard register that is stored, record
8010 the storing insn so that we may delete this insn with
8011 delete_output_reload. */
8012 src_reg = reload_reg_rtx_for_output[r];
8014 /* If this is an optional reload, try to find the source reg
8015 from an input reload. */
8018 rtx set = single_set (insn);
8019 if (set && SET_DEST (set) == rld[r].out)
8023 src_reg = SET_SRC (set);
8025 for (k = 0; k < n_reloads; k++)
8027 if (rld[k].in == src_reg)
8029 src_reg = reload_reg_rtx_for_input[k];
8036 store_insn = new_spill_reg_store[REGNO (src_reg)];
8037 if (src_reg && REG_P (src_reg)
8038 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8040 int src_regno, src_nregs, k;
8043 gcc_assert (GET_MODE (src_reg) == mode);
8044 src_regno = REGNO (src_reg);
8045 src_nregs = hard_regno_nregs[src_regno][mode];
8046 /* The place where to find a death note varies with
8047 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8048 necessarily checked exactly in the code that moves
8049 notes, so just check both locations. */
8050 note = find_regno_note (insn, REG_DEAD, src_regno);
8051 if (! note && store_insn)
8052 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8053 for (k = 0; k < src_nregs; k++)
8055 spill_reg_store[src_regno + k] = store_insn;
8056 spill_reg_stored_to[src_regno + k] = out;
8057 reg_reloaded_contents[src_regno + k] = out_regno;
8058 reg_reloaded_insn[src_regno + k] = store_insn;
8059 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8060 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8061 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8063 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8066 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8068 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8070 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8072 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8074 reg_last_reload_reg[out_regno] = src_reg;
8075 /* We have to set reg_has_output_reload here, or else
8076 forget_old_reloads_1 will clear reg_last_reload_reg
8078 SET_REGNO_REG_SET (®_has_output_reload,
8084 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8086 for (k = 0; k < out_nregs; k++)
8087 reg_last_reload_reg[out_regno + k] = 0;
8091 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8094 /* Go through the motions to emit INSN and test if it is strictly valid.
8095 Return the emitted insn if valid, else return NULL. */
8098 emit_insn_if_valid_for_reload (rtx insn)
8100 rtx last = get_last_insn ();
8103 insn = emit_insn (insn);
8104 code = recog_memoized (insn);
8108 extract_insn (insn);
8109 /* We want constrain operands to treat this insn strictly in its
8110 validity determination, i.e., the way it would after reload has
8112 if (constrain_operands (1))
8116 delete_insns_since (last);
8120 /* Emit code to perform a reload from IN (which may be a reload register) to
8121 OUT (which may also be a reload register). IN or OUT is from operand
8122 OPNUM with reload type TYPE.
8124 Returns first insn emitted. */
8127 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8129 rtx last = get_last_insn ();
8132 /* If IN is a paradoxical SUBREG, remove it and try to put the
8133 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8134 if (GET_CODE (in) == SUBREG
8135 && (GET_MODE_SIZE (GET_MODE (in))
8136 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8137 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8138 in = SUBREG_REG (in), out = tem;
8139 else if (GET_CODE (out) == SUBREG
8140 && (GET_MODE_SIZE (GET_MODE (out))
8141 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8142 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8143 out = SUBREG_REG (out), in = tem;
8145 /* How to do this reload can get quite tricky. Normally, we are being
8146 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8147 register that didn't get a hard register. In that case we can just
8148 call emit_move_insn.
8150 We can also be asked to reload a PLUS that adds a register or a MEM to
8151 another register, constant or MEM. This can occur during frame pointer
8152 elimination and while reloading addresses. This case is handled by
8153 trying to emit a single insn to perform the add. If it is not valid,
8154 we use a two insn sequence.
8156 Or we can be asked to reload an unary operand that was a fragment of
8157 an addressing mode, into a register. If it isn't recognized as-is,
8158 we try making the unop operand and the reload-register the same:
8159 (set reg:X (unop:X expr:Y))
8160 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8162 Finally, we could be called to handle an 'o' constraint by putting
8163 an address into a register. In that case, we first try to do this
8164 with a named pattern of "reload_load_address". If no such pattern
8165 exists, we just emit a SET insn and hope for the best (it will normally
8166 be valid on machines that use 'o').
8168 This entire process is made complex because reload will never
8169 process the insns we generate here and so we must ensure that
8170 they will fit their constraints and also by the fact that parts of
8171 IN might be being reloaded separately and replaced with spill registers.
8172 Because of this, we are, in some sense, just guessing the right approach
8173 here. The one listed above seems to work.
8175 ??? At some point, this whole thing needs to be rethought. */
8177 if (GET_CODE (in) == PLUS
8178 && (REG_P (XEXP (in, 0))
8179 || GET_CODE (XEXP (in, 0)) == SUBREG
8180 || MEM_P (XEXP (in, 0)))
8181 && (REG_P (XEXP (in, 1))
8182 || GET_CODE (XEXP (in, 1)) == SUBREG
8183 || CONSTANT_P (XEXP (in, 1))
8184 || MEM_P (XEXP (in, 1))))
8186 /* We need to compute the sum of a register or a MEM and another
8187 register, constant, or MEM, and put it into the reload
8188 register. The best possible way of doing this is if the machine
8189 has a three-operand ADD insn that accepts the required operands.
8191 The simplest approach is to try to generate such an insn and see if it
8192 is recognized and matches its constraints. If so, it can be used.
8194 It might be better not to actually emit the insn unless it is valid,
8195 but we need to pass the insn as an operand to `recog' and
8196 `extract_insn' and it is simpler to emit and then delete the insn if
8197 not valid than to dummy things up. */
8199 rtx op0, op1, tem, insn;
8202 op0 = find_replacement (&XEXP (in, 0));
8203 op1 = find_replacement (&XEXP (in, 1));
8205 /* Since constraint checking is strict, commutativity won't be
8206 checked, so we need to do that here to avoid spurious failure
8207 if the add instruction is two-address and the second operand
8208 of the add is the same as the reload reg, which is frequently
8209 the case. If the insn would be A = B + A, rearrange it so
8210 it will be A = A + B as constrain_operands expects. */
8212 if (REG_P (XEXP (in, 1))
8213 && REGNO (out) == REGNO (XEXP (in, 1)))
8214 tem = op0, op0 = op1, op1 = tem;
8216 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8217 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8219 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8223 /* If that failed, we must use a conservative two-insn sequence.
8225 Use a move to copy one operand into the reload register. Prefer
8226 to reload a constant, MEM or pseudo since the move patterns can
8227 handle an arbitrary operand. If OP1 is not a constant, MEM or
8228 pseudo and OP1 is not a valid operand for an add instruction, then
8231 After reloading one of the operands into the reload register, add
8232 the reload register to the output register.
8234 If there is another way to do this for a specific machine, a
8235 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8238 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8240 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8242 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8243 || (code != CODE_FOR_nothing
8244 && ! ((*insn_data[code].operand[2].predicate)
8245 (op1, insn_data[code].operand[2].mode))))
8246 tem = op0, op0 = op1, op1 = tem;
8248 gen_reload (out, op0, opnum, type);
8250 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8251 This fixes a problem on the 32K where the stack pointer cannot
8252 be used as an operand of an add insn. */
8254 if (rtx_equal_p (op0, op1))
8257 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8260 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8261 set_unique_reg_note (insn, REG_EQUIV, in);
8265 /* If that failed, copy the address register to the reload register.
8266 Then add the constant to the reload register. */
8268 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8269 gen_reload (out, op1, opnum, type);
8270 insn = emit_insn (gen_add2_insn (out, op0));
8271 set_unique_reg_note (insn, REG_EQUIV, in);
8274 #ifdef SECONDARY_MEMORY_NEEDED
8275 /* If we need a memory location to do the move, do it that way. */
8276 else if ((REG_P (in)
8277 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8278 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8280 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8281 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8282 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8283 REGNO_REG_CLASS (reg_or_subregno (out)),
8286 /* Get the memory to use and rewrite both registers to its mode. */
8287 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8289 if (GET_MODE (loc) != GET_MODE (out))
8290 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8292 if (GET_MODE (loc) != GET_MODE (in))
8293 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8295 gen_reload (loc, in, opnum, type);
8296 gen_reload (out, loc, opnum, type);
8299 else if (REG_P (out) && UNARY_P (in))
8306 op1 = find_replacement (&XEXP (in, 0));
8307 if (op1 != XEXP (in, 0))
8308 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8310 /* First, try a plain SET. */
8311 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8315 /* If that failed, move the inner operand to the reload
8316 register, and try the same unop with the inner expression
8317 replaced with the reload register. */
8319 if (GET_MODE (op1) != GET_MODE (out))
8320 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8324 gen_reload (out_moded, op1, opnum, type);
8327 = gen_rtx_SET (VOIDmode, out,
8328 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8330 insn = emit_insn_if_valid_for_reload (insn);
8333 set_unique_reg_note (insn, REG_EQUIV, in);
8337 fatal_insn ("Failure trying to reload:", set);
8339 /* If IN is a simple operand, use gen_move_insn. */
8340 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8342 tem = emit_insn (gen_move_insn (out, in));
8343 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8344 mark_jump_label (in, tem, 0);
8347 #ifdef HAVE_reload_load_address
8348 else if (HAVE_reload_load_address)
8349 emit_insn (gen_reload_load_address (out, in));
8352 /* Otherwise, just write (set OUT IN) and hope for the best. */
8354 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8356 /* Return the first insn emitted.
8357 We can not just return get_last_insn, because there may have
8358 been multiple instructions emitted. Also note that gen_move_insn may
8359 emit more than one insn itself, so we can not assume that there is one
8360 insn emitted per emit_insn_before call. */
8362 return last ? NEXT_INSN (last) : get_insns ();
8365 /* Delete a previously made output-reload whose result we now believe
8366 is not needed. First we double-check.
8368 INSN is the insn now being processed.
8369 LAST_RELOAD_REG is the hard register number for which we want to delete
8370 the last output reload.
8371 J is the reload-number that originally used REG. The caller has made
8372 certain that reload J doesn't use REG any longer for input.
8373 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8376 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8378 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8379 rtx reg = spill_reg_stored_to[last_reload_reg];
8382 int n_inherited = 0;
8386 /* It is possible that this reload has been only used to set another reload
8387 we eliminated earlier and thus deleted this instruction too. */
8388 if (INSN_DELETED_P (output_reload_insn))
8391 /* Get the raw pseudo-register referred to. */
8393 while (GET_CODE (reg) == SUBREG)
8394 reg = SUBREG_REG (reg);
8395 substed = reg_equiv_memory_loc[REGNO (reg)];
8397 /* This is unsafe if the operand occurs more often in the current
8398 insn than it is inherited. */
8399 for (k = n_reloads - 1; k >= 0; k--)
8401 rtx reg2 = rld[k].in;
8404 if (MEM_P (reg2) || reload_override_in[k])
8405 reg2 = rld[k].in_reg;
8407 if (rld[k].out && ! rld[k].out_reg)
8408 reg2 = XEXP (rld[k].in_reg, 0);
8410 while (GET_CODE (reg2) == SUBREG)
8411 reg2 = SUBREG_REG (reg2);
8412 if (rtx_equal_p (reg2, reg))
8414 if (reload_inherited[k] || reload_override_in[k] || k == j)
8420 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8421 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8422 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8425 n_occurrences += count_occurrences (PATTERN (insn),
8426 eliminate_regs (substed, 0,
8428 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8430 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8431 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8433 if (n_occurrences > n_inherited)
8436 /* If the pseudo-reg we are reloading is no longer referenced
8437 anywhere between the store into it and here,
8438 and we're within the same basic block, then the value can only
8439 pass through the reload reg and end up here.
8440 Otherwise, give up--return. */
8441 for (i1 = NEXT_INSN (output_reload_insn);
8442 i1 != insn; i1 = NEXT_INSN (i1))
8444 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8446 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8447 && reg_mentioned_p (reg, PATTERN (i1)))
8449 /* If this is USE in front of INSN, we only have to check that
8450 there are no more references than accounted for by inheritance. */
8451 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8453 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8454 i1 = NEXT_INSN (i1);
8456 if (n_occurrences <= n_inherited && i1 == insn)
8462 /* We will be deleting the insn. Remove the spill reg information. */
8463 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8465 spill_reg_store[last_reload_reg + k] = 0;
8466 spill_reg_stored_to[last_reload_reg + k] = 0;
8469 /* The caller has already checked that REG dies or is set in INSN.
8470 It has also checked that we are optimizing, and thus some
8471 inaccuracies in the debugging information are acceptable.
8472 So we could just delete output_reload_insn. But in some cases
8473 we can improve the debugging information without sacrificing
8474 optimization - maybe even improving the code: See if the pseudo
8475 reg has been completely replaced with reload regs. If so, delete
8476 the store insn and forget we had a stack slot for the pseudo. */
8477 if (rld[j].out != rld[j].in
8478 && REG_N_DEATHS (REGNO (reg)) == 1
8479 && REG_N_SETS (REGNO (reg)) == 1
8480 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8481 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8485 /* We know that it was used only between here and the beginning of
8486 the current basic block. (We also know that the last use before
8487 INSN was the output reload we are thinking of deleting, but never
8488 mind that.) Search that range; see if any ref remains. */
8489 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8491 rtx set = single_set (i2);
8493 /* Uses which just store in the pseudo don't count,
8494 since if they are the only uses, they are dead. */
8495 if (set != 0 && SET_DEST (set) == reg)
8500 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8501 && reg_mentioned_p (reg, PATTERN (i2)))
8503 /* Some other ref remains; just delete the output reload we
8505 delete_address_reloads (output_reload_insn, insn);
8506 delete_insn (output_reload_insn);
8511 /* Delete the now-dead stores into this pseudo. Note that this
8512 loop also takes care of deleting output_reload_insn. */
8513 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8515 rtx set = single_set (i2);
8517 if (set != 0 && SET_DEST (set) == reg)
8519 delete_address_reloads (i2, insn);
8527 /* For the debugging info, say the pseudo lives in this reload reg. */
8528 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8529 if (ira_conflicts_p)
8530 /* Inform IRA about the change. */
8531 ira_mark_allocation_change (REGNO (reg));
8532 alter_reg (REGNO (reg), -1, false);
8536 delete_address_reloads (output_reload_insn, insn);
8537 delete_insn (output_reload_insn);
8541 /* We are going to delete DEAD_INSN. Recursively delete loads of
8542 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8543 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8545 delete_address_reloads (rtx dead_insn, rtx current_insn)
8547 rtx set = single_set (dead_insn);
8548 rtx set2, dst, prev, next;
8551 rtx dst = SET_DEST (set);
8553 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8555 /* If we deleted the store from a reloaded post_{in,de}c expression,
8556 we can delete the matching adds. */
8557 prev = PREV_INSN (dead_insn);
8558 next = NEXT_INSN (dead_insn);
8559 if (! prev || ! next)
8561 set = single_set (next);
8562 set2 = single_set (prev);
8564 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8565 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8566 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8568 dst = SET_DEST (set);
8569 if (! rtx_equal_p (dst, SET_DEST (set2))
8570 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8571 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8572 || (INTVAL (XEXP (SET_SRC (set), 1))
8573 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8575 delete_related_insns (prev);
8576 delete_related_insns (next);
8579 /* Subfunction of delete_address_reloads: process registers found in X. */
8581 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8583 rtx prev, set, dst, i2;
8585 enum rtx_code code = GET_CODE (x);
8589 const char *fmt = GET_RTX_FORMAT (code);
8590 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8593 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8594 else if (fmt[i] == 'E')
8596 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8597 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8604 if (spill_reg_order[REGNO (x)] < 0)
8607 /* Scan backwards for the insn that sets x. This might be a way back due
8609 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8611 code = GET_CODE (prev);
8612 if (code == CODE_LABEL || code == JUMP_INSN)
8616 if (reg_set_p (x, PATTERN (prev)))
8618 if (reg_referenced_p (x, PATTERN (prev)))
8621 if (! prev || INSN_UID (prev) < reload_first_uid)
8623 /* Check that PREV only sets the reload register. */
8624 set = single_set (prev);
8627 dst = SET_DEST (set);
8629 || ! rtx_equal_p (dst, x))
8631 if (! reg_set_p (dst, PATTERN (dead_insn)))
8633 /* Check if DST was used in a later insn -
8634 it might have been inherited. */
8635 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8641 if (reg_referenced_p (dst, PATTERN (i2)))
8643 /* If there is a reference to the register in the current insn,
8644 it might be loaded in a non-inherited reload. If no other
8645 reload uses it, that means the register is set before
8647 if (i2 == current_insn)
8649 for (j = n_reloads - 1; j >= 0; j--)
8650 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8651 || reload_override_in[j] == dst)
8653 for (j = n_reloads - 1; j >= 0; j--)
8654 if (rld[j].in && rld[j].reg_rtx == dst)
8663 /* If DST is still live at CURRENT_INSN, check if it is used for
8664 any reload. Note that even if CURRENT_INSN sets DST, we still
8665 have to check the reloads. */
8666 if (i2 == current_insn)
8668 for (j = n_reloads - 1; j >= 0; j--)
8669 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8670 || reload_override_in[j] == dst)
8672 /* ??? We can't finish the loop here, because dst might be
8673 allocated to a pseudo in this block if no reload in this
8674 block needs any of the classes containing DST - see
8675 spill_hard_reg. There is no easy way to tell this, so we
8676 have to scan till the end of the basic block. */
8678 if (reg_set_p (dst, PATTERN (i2)))
8682 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8683 reg_reloaded_contents[REGNO (dst)] = -1;
8687 /* Output reload-insns to reload VALUE into RELOADREG.
8688 VALUE is an autoincrement or autodecrement RTX whose operand
8689 is a register or memory location;
8690 so reloading involves incrementing that location.
8691 IN is either identical to VALUE, or some cheaper place to reload from.
8693 INC_AMOUNT is the number to increment or decrement by (always positive).
8694 This cannot be deduced from VALUE.
8696 Return the instruction that stores into RELOADREG. */
8699 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8701 /* REG or MEM to be copied and incremented. */
8702 rtx incloc = find_replacement (&XEXP (value, 0));
8703 /* Nonzero if increment after copying. */
8704 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8705 || GET_CODE (value) == POST_MODIFY);
8711 rtx real_in = in == value ? incloc : in;
8713 /* No hard register is equivalent to this register after
8714 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8715 we could inc/dec that register as well (maybe even using it for
8716 the source), but I'm not sure it's worth worrying about. */
8718 reg_last_reload_reg[REGNO (incloc)] = 0;
8720 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8722 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8723 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8727 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8728 inc_amount = -inc_amount;
8730 inc = GEN_INT (inc_amount);
8733 /* If this is post-increment, first copy the location to the reload reg. */
8734 if (post && real_in != reloadreg)
8735 emit_insn (gen_move_insn (reloadreg, real_in));
8739 /* See if we can directly increment INCLOC. Use a method similar to
8740 that in gen_reload. */
8742 last = get_last_insn ();
8743 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8744 gen_rtx_PLUS (GET_MODE (incloc),
8747 code = recog_memoized (add_insn);
8750 extract_insn (add_insn);
8751 if (constrain_operands (1))
8753 /* If this is a pre-increment and we have incremented the value
8754 where it lives, copy the incremented value to RELOADREG to
8755 be used as an address. */
8758 emit_insn (gen_move_insn (reloadreg, incloc));
8763 delete_insns_since (last);
8766 /* If couldn't do the increment directly, must increment in RELOADREG.
8767 The way we do this depends on whether this is pre- or post-increment.
8768 For pre-increment, copy INCLOC to the reload register, increment it
8769 there, then save back. */
8773 if (in != reloadreg)
8774 emit_insn (gen_move_insn (reloadreg, real_in));
8775 emit_insn (gen_add2_insn (reloadreg, inc));
8776 store = emit_insn (gen_move_insn (incloc, reloadreg));
8781 Because this might be a jump insn or a compare, and because RELOADREG
8782 may not be available after the insn in an input reload, we must do
8783 the incrementation before the insn being reloaded for.
8785 We have already copied IN to RELOADREG. Increment the copy in
8786 RELOADREG, save that back, then decrement RELOADREG so it has
8787 the original value. */
8789 emit_insn (gen_add2_insn (reloadreg, inc));
8790 store = emit_insn (gen_move_insn (incloc, reloadreg));
8791 if (GET_CODE (inc) == CONST_INT)
8792 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8794 emit_insn (gen_sub2_insn (reloadreg, inc));
8802 add_auto_inc_notes (rtx insn, rtx x)
8804 enum rtx_code code = GET_CODE (x);
8808 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8810 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8814 /* Scan all the operand sub-expressions. */
8815 fmt = GET_RTX_FORMAT (code);
8816 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8819 add_auto_inc_notes (insn, XEXP (x, i));
8820 else if (fmt[i] == 'E')
8821 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8822 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8827 /* Copy EH notes from an insn to its reloads. */
8829 copy_eh_notes (rtx insn, rtx x)
8831 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8834 for (; x != 0; x = NEXT_INSN (x))
8836 if (may_trap_p (PATTERN (x)))
8837 add_reg_note (x, REG_EH_REGION, XEXP (eh_note, 0));
8842 /* This is used by reload pass, that does emit some instructions after
8843 abnormal calls moving basic block end, but in fact it wants to emit
8844 them on the edge. Looks for abnormal call edges, find backward the
8845 proper call and fix the damage.
8847 Similar handle instructions throwing exceptions internally. */
8849 fixup_abnormal_edges (void)
8851 bool inserted = false;
8859 /* Look for cases we are interested in - calls or instructions causing
8861 FOR_EACH_EDGE (e, ei, bb->succs)
8863 if (e->flags & EDGE_ABNORMAL_CALL)
8865 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8866 == (EDGE_ABNORMAL | EDGE_EH))
8869 if (e && !CALL_P (BB_END (bb))
8870 && !can_throw_internal (BB_END (bb)))
8874 /* Get past the new insns generated. Allow notes, as the insns
8875 may be already deleted. */
8877 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8878 && !can_throw_internal (insn)
8879 && insn != BB_HEAD (bb))
8880 insn = PREV_INSN (insn);
8882 if (CALL_P (insn) || can_throw_internal (insn))
8886 stop = NEXT_INSN (BB_END (bb));
8888 insn = NEXT_INSN (insn);
8890 FOR_EACH_EDGE (e, ei, bb->succs)
8891 if (e->flags & EDGE_FALLTHRU)
8894 while (insn && insn != stop)
8896 next = NEXT_INSN (insn);
8901 /* Sometimes there's still the return value USE.
8902 If it's placed after a trapping call (i.e. that
8903 call is the last insn anyway), we have no fallthru
8904 edge. Simply delete this use and don't try to insert
8905 on the non-existent edge. */
8906 if (GET_CODE (PATTERN (insn)) != USE)
8908 /* We're not deleting it, we're moving it. */
8909 INSN_DELETED_P (insn) = 0;
8910 PREV_INSN (insn) = NULL_RTX;
8911 NEXT_INSN (insn) = NULL_RTX;
8913 insert_insn_on_edge (insn, e);
8917 else if (!BARRIER_P (insn))
8918 set_block_for_insn (insn, NULL);
8923 /* It may be that we don't find any such trapping insn. In this
8924 case we discovered quite late that the insn that had been
8925 marked as can_throw_internal in fact couldn't trap at all.
8926 So we should in fact delete the EH edges out of the block. */
8928 purge_dead_edges (bb);
8932 /* We've possibly turned single trapping insn into multiple ones. */
8933 if (flag_non_call_exceptions)
8936 blocks = sbitmap_alloc (last_basic_block);
8937 sbitmap_ones (blocks);
8938 find_many_sub_basic_blocks (blocks);
8939 sbitmap_free (blocks);
8943 commit_edge_insertions ();
8945 #ifdef ENABLE_CHECKING
8946 /* Verify that we didn't turn one trapping insn into many, and that
8947 we found and corrected all of the problems wrt fixups on the
8949 verify_flow_info ();
polachok's projects / dragonfly.git / blob