From: Hasso Tepper <hasso@estpak.ee>
Date: Thu, 26 Mar 2009 08:34:49 +0000 (+0200)
Subject: Sync DRM code with FreeBSD trunk rev 190433.
X-Git-Url: https://gitweb.dragonflybsd.org/~polachok/dragonfly.git/commitdiff_plain/b3705d716ab5621c5cac8741394ad6cab7e5c99b

Sync DRM code with FreeBSD trunk rev 190433.
---

diff --git a/sys/conf/files b/sys/conf/files
index 66724411cb..ce3ebf8aa4 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -1521,6 +1521,7 @@ dev/drm/i915_dma.c			optional i915drm drm
 dev/drm/i915_drv.c			optional i915drm drm
 dev/drm/i915_irq.c			optional i915drm drm
 dev/drm/i915_mem.c			optional i915drm drm
+dev/drm/i915_suspend.c			optional i915drm drm
 dev/drm/mach64_dma.c			optional mach64drm drm
 dev/drm/mach64_drv.c			optional mach64drm drm
 dev/drm/mach64_irq.c			optional mach64drm drm
@@ -1535,6 +1536,7 @@ dev/drm/r128_drv.c			optional r128drm drm
 dev/drm/r128_state.c			optional r128drm drm
 dev/drm/r128_irq.c			optional r128drm drm
 dev/drm/r300_cmdbuf.c			optional radeondrm drm
+dev/drm/r600_cp.c			optional radeondrm drm
 dev/drm/radeon_cp.c			optional radeondrm drm
 dev/drm/radeon_drv.c			optional radeondrm drm
 dev/drm/radeon_state.c			optional radeondrm drm
diff --git a/sys/dev/drm/ati_pcigart.c b/sys/dev/drm/ati_pcigart.c
index 487348fb68..e75eafd75e 100644
--- a/sys/dev/drm/ati_pcigart.c
+++ b/sys/dev/drm/ati_pcigart.c
@@ -24,7 +24,6 @@
  * Authors:
  *   Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/ati_pcigart.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file ati_pcigart.c
@@ -32,77 +31,193 @@
  * address space with addresses remapped to system memory.
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
 #define ATI_PCIGART_PAGE_SIZE		4096	/* PCI GART page size */
+#define ATI_PCIGART_PAGE_MASK		(~(ATI_PCIGART_PAGE_SIZE-1))
 
-int drm_ati_pcigart_init(drm_device_t *dev, struct drm_ati_pcigart_info *gart_info)
+#define ATI_PCIE_WRITE 0x4
+#define ATI_PCIE_READ 0x8
+
+static void
+drm_ati_alloc_pcigart_table_cb(void *arg, bus_dma_segment_t *segs,
+			       int nsegs, int error)
 {
-	unsigned long pages;
-	u32 *pci_gart = NULL, page_base;
-	int i, j;
+	struct drm_dma_handle *dmah = arg;
+
+	if (error != 0)
+		return;
+
+	KASSERT(nsegs == 1,
+	    ("drm_ati_alloc_pcigart_table_cb: bad dma segment count"));
+
+	dmah->busaddr = segs[0].ds_addr;
+}
+
+static int
+drm_ati_alloc_pcigart_table(struct drm_device *dev,
+			    struct drm_ati_pcigart_info *gart_info)
+{
+	struct drm_dma_handle *dmah;
+	int flags, ret;
+
+	dmah = malloc(sizeof(struct drm_dma_handle), DRM_MEM_DMA,
+	    M_ZERO | M_NOWAIT);
+	if (dmah == NULL)
+		return ENOMEM;
+
+	DRM_UNLOCK();
+	ret = bus_dma_tag_create(NULL, PAGE_SIZE, 0, /* tag, align, boundary */
+	    gart_info->table_mask, BUS_SPACE_MAXADDR, /* lowaddr, highaddr */
+	    NULL, NULL, /* filtfunc, filtfuncargs */
+	    gart_info->table_size, 1, /* maxsize, nsegs */
+	    gart_info->table_size, /* maxsegsize */
+	    0, /* flags */
+	    &dmah->tag);
+	if (ret != 0) {
+		free(dmah, DRM_MEM_DMA);
+		return ENOMEM;
+	}
 
+	flags = BUS_DMA_WAITOK | BUS_DMA_ZERO;
+
+#if 0
+	if (gart_info->gart_reg_if == DRM_ATI_GART_IGP)
+	    flags |= BUS_DMA_NOCACHE;
+#endif
+	
+	ret = bus_dmamem_alloc(dmah->tag, &dmah->vaddr, flags, &dmah->map);
+	if (ret != 0) {
+		bus_dma_tag_destroy(dmah->tag);
+		free(dmah, DRM_MEM_DMA);
+		return ENOMEM;
+	}
+	DRM_LOCK();
+
+	ret = bus_dmamap_load(dmah->tag, dmah->map, dmah->vaddr,
+	    gart_info->table_size, drm_ati_alloc_pcigart_table_cb, dmah,
+	    BUS_DMA_NOWAIT);
+	if (ret != 0) {
+		bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
+		bus_dma_tag_destroy(dmah->tag);
+		free(dmah, DRM_MEM_DMA);
+		return ENOMEM;
+	}
+
+	gart_info->dmah = dmah;
+
+	return 0;
+}
+
+static void
+drm_ati_free_pcigart_table(struct drm_device *dev,
+			   struct drm_ati_pcigart_info *gart_info)
+{
+	struct drm_dma_handle *dmah = gart_info->dmah;
+
+	bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
+	bus_dma_tag_destroy(dmah->tag);
+	free(dmah, DRM_MEM_DMA);
+	gart_info->dmah = NULL;
+}
+
+int
+drm_ati_pcigart_cleanup(struct drm_device *dev,
+			struct drm_ati_pcigart_info *gart_info)
+{
+	/* we need to support large memory configurations */
 	if (dev->sg == NULL) {
-		DRM_ERROR( "no scatter/gather memory!\n" );
+		DRM_ERROR("no scatter/gather memory!\n");
 		return 0;
 	}
 
+	if (gart_info->bus_addr) {
+		if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
+			gart_info->bus_addr = 0;
+			if (gart_info->dmah)
+				drm_ati_free_pcigart_table(dev, gart_info);
+		}
+	}
+
+	return 1;
+}
+
+int
+drm_ati_pcigart_init(struct drm_device *dev,
+		     struct drm_ati_pcigart_info *gart_info)
+{
+	void *address = NULL;
+	unsigned long pages;
+	u32 *pci_gart, page_base;
+	dma_addr_t bus_address = 0;
+	dma_addr_t entry_addr;
+	int i, j, ret = 0;
+	int max_pages;
+
+	/* we need to support large memory configurations */
+	if (dev->sg == NULL) {
+		DRM_ERROR("no scatter/gather memory!\n");
+		goto done;
+	}
+
 	if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
-		/* GART table in system memory */
-		dev->sg->dmah = drm_pci_alloc(dev, gart_info->table_size, 0,
-		    0xfffffffful);
-		if (dev->sg->dmah == NULL) {
-			DRM_ERROR("cannot allocate PCI GART table!\n");
-			return 0;
+		DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
+
+		ret = drm_ati_alloc_pcigart_table(dev, gart_info);
+		if (ret) {
+			DRM_ERROR("cannot allocate PCI GART page!\n");
+			goto done;
 		}
-	
-		gart_info->addr = (void *)dev->sg->dmah->vaddr;
-		gart_info->bus_addr = dev->sg->dmah->busaddr;
-		pci_gart = (u32 *)dev->sg->dmah->vaddr;
+
+		address = (void *)gart_info->dmah->vaddr;
+		bus_address = gart_info->dmah->busaddr;
 	} else {
-		/* GART table in framebuffer memory */
-		pci_gart = gart_info->addr;
+		address = gart_info->addr;
+		bus_address = gart_info->bus_addr;
+		DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n",
+			  (unsigned int)bus_address, (unsigned long)address);
 	}
-	
-	pages = DRM_MIN(dev->sg->pages, gart_info->table_size / sizeof(u32));
 
-	bzero(pci_gart, gart_info->table_size);
+	pci_gart = (u32 *) address;
 
-	KASSERT(PAGE_SIZE >= ATI_PCIGART_PAGE_SIZE, ("page size too small"));
+	max_pages = (gart_info->table_size / sizeof(u32));
+	pages = (dev->sg->pages <= max_pages)
+	    ? dev->sg->pages : max_pages;
+
+	memset(pci_gart, 0, max_pages * sizeof(u32));
 
-	for ( i = 0 ; i < pages ; i++ ) {
-		page_base = (u32) dev->sg->busaddr[i];
+	KASSERT(PAGE_SIZE >= ATI_PCIGART_PAGE_SIZE, ("page size too small"));
 
+	for (i = 0; i < pages; i++) {
+		entry_addr = dev->sg->busaddr[i];
 		for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
+			page_base = (u32) entry_addr & ATI_PCIGART_PAGE_MASK;
 			switch(gart_info->gart_reg_if) {
 			case DRM_ATI_GART_IGP:
-				*pci_gart = cpu_to_le32(page_base | 0xc);
+				page_base |=
+				    (upper_32_bits(entry_addr) & 0xff) << 4;
+				page_base |= 0xc;
 				break;
 			case DRM_ATI_GART_PCIE:
-				*pci_gart = cpu_to_le32((page_base >> 8) | 0xc);
+				page_base >>= 8;
+				page_base |=
+				    (upper_32_bits(entry_addr) & 0xff) << 24;
+				page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE;
 				break;
 			default:
-				*pci_gart = cpu_to_le32(page_base);
+			case DRM_ATI_GART_PCI:
 				break;
 			}
+			*pci_gart = cpu_to_le32(page_base);
 			pci_gart++;
-			page_base += ATI_PCIGART_PAGE_SIZE;
+			entry_addr += ATI_PCIGART_PAGE_SIZE;
 		}
 	}
 
-	DRM_MEMORYBARRIER();
+	ret = 1;
 
-	return 1;
-}
-
-int drm_ati_pcigart_cleanup(drm_device_t *dev, struct drm_ati_pcigart_info *gart_info)
-{
-	if (dev->sg == NULL) {
-		DRM_ERROR( "no scatter/gather memory!\n" );
-		return 0;
-	}
-
-	drm_pci_free(dev, dev->sg->dmah);
-
-	return 1;
+    done:
+	gart_info->addr = address;
+	gart_info->bus_addr = bus_address;
+	return ret;
 }
diff --git a/sys/dev/drm/drm.h b/sys/dev/drm/drm.h
index c50f843b2d..d4e8c9041e 100644
--- a/sys/dev/drm/drm.h
+++ b/sys/dev/drm/drm.h
@@ -8,7 +8,7 @@
  * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
  */
 
-/*
+/*-
  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All rights reserved.
@@ -31,8 +31,6 @@
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/drm.h,v 1.4 2008/04/05 18:12:29 hasso Exp $
  */
 
 /**
@@ -557,6 +555,20 @@ union drm_wait_vblank {
 	struct drm_wait_vblank_reply reply;
 };
 
+
+#define _DRM_PRE_MODESET 1
+#define _DRM_POST_MODESET 2
+
+/**
+ * DRM_IOCTL_MODESET_CTL ioctl argument type
+ *
+ * \sa drmModesetCtl().
+ */
+struct drm_modeset_ctl {
+	uint32_t crtc;
+	uint32_t cmd;
+};
+
 /**
  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
  *
@@ -632,8 +644,14 @@ struct drm_set_version {
 
 #define DRM_FENCE_FLAG_EMIT                0x00000001
 #define DRM_FENCE_FLAG_SHAREABLE           0x00000002
+/**
+ * On hardware with no interrupt events for operation completion,
+ * indicates that the kernel should sleep while waiting for any blocking
+ * operation to complete rather than spinning.
+ *
+ * Has no effect otherwise.
+ */
 #define DRM_FENCE_FLAG_WAIT_LAZY           0x00000004
-#define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
 #define DRM_FENCE_FLAG_NO_USER             0x00000010
 
 /* Reserved for driver use */
@@ -707,7 +725,14 @@ struct drm_fence_arg {
  */
 #define DRM_BO_FLAG_NO_MOVE     (1ULL << 8)
 
-/* Mask: Make sure the buffer is in cached memory when mapped
+/* Mask: Make sure the buffer is in cached memory when mapped.  In conjunction
+ * with DRM_BO_FLAG_CACHED it also allows the buffer to be bound into the GART
+ * with unsnooped PTEs instead of snooped, by using chipset-specific cache
+ * flushing at bind time.  A better name might be DRM_BO_FLAG_TT_UNSNOOPED,
+ * as the eviction to local memory (TTM unbind) on map is just a side effect
+ * to prevent aggressive cache prefetch from the GPU disturbing the cache
+ * management that the DRM is doing.
+ *
  * Flags: Acknowledge.
  * Buffers allocated with this flag should not be used for suballocators
  * This type may have issues on CPUs with over-aggressive caching
@@ -775,13 +800,12 @@ struct drm_fence_arg {
  * with it as a result of this operation
  */
 #define DRM_BO_HINT_DONT_FENCE  0x00000004
-/*
- * Sleep while waiting for the operation to complete.
- * Without this flag, the kernel will, instead, spin
- * until this operation has completed. I'm not sure
- * why you would ever want this, so please always
- * provide DRM_BO_HINT_WAIT_LAZY to any operation
- * which may block
+/**
+ * On hardware with no interrupt events for operation completion,
+ * indicates that the kernel should sleep while waiting for any blocking
+ * operation to complete rather than spinning.
+ *
+ * Has no effect otherwise.
  */
 #define DRM_BO_HINT_WAIT_LAZY   0x00000008
 /*
@@ -930,6 +954,36 @@ struct drm_mm_init_arg {
 	uint64_t p_size;
 };
 
+struct drm_mm_info_arg {
+	unsigned int mem_type;
+	uint64_t p_size;
+};
+
+struct drm_gem_close {
+	/** Handle of the object to be closed. */
+	uint32_t handle;
+	uint32_t pad;
+};
+
+struct drm_gem_flink {
+	/** Handle for the object being named */
+	uint32_t handle;
+
+	/** Returned global name */
+	uint32_t name;
+};
+
+struct drm_gem_open {
+	/** Name of object being opened */
+	uint32_t name;
+
+	/** Returned handle for the object */
+	uint32_t handle;
+	
+	/** Returned size of the object */
+	uint64_t size;
+};
+
 /**
  * \name Ioctls Definitions
  */
@@ -949,6 +1003,11 @@ struct drm_mm_init_arg {
 #define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
 #define DRM_IOCTL_SET_VERSION		DRM_IOWR(0x07, struct drm_set_version)
+#define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08,  struct drm_modeset_ctl)
+
+#define DRM_IOCTL_GEM_CLOSE		DRM_IOW (0x09, struct drm_gem_close)
+#define DRM_IOCTL_GEM_FLINK		DRM_IOWR(0x0a, struct drm_gem_flink)
+#define DRM_IOCTL_GEM_OPEN		DRM_IOWR(0x0b, struct drm_gem_open)
 
 #define DRM_IOCTL_SET_UNIQUE		DRM_IOW( 0x10, struct drm_unique)
 #define DRM_IOCTL_AUTH_MAGIC		DRM_IOW( 0x11, struct drm_auth)
@@ -990,7 +1049,7 @@ struct drm_mm_init_arg {
 #define DRM_IOCTL_AGP_BIND		DRM_IOW( 0x36, struct drm_agp_binding)
 #define DRM_IOCTL_AGP_UNBIND		DRM_IOW( 0x37, struct drm_agp_binding)
 
-#define DRM_IOCTL_SG_ALLOC		DRM_IOW( 0x38, struct drm_scatter_gather)
+#define DRM_IOCTL_SG_ALLOC		DRM_IOWR(0x38, struct drm_scatter_gather)
 #define DRM_IOCTL_SG_FREE		DRM_IOW( 0x39, struct drm_scatter_gather)
 
 #define DRM_IOCTL_WAIT_VBLANK		DRM_IOWR(0x3a, union drm_wait_vblank)
@@ -1020,7 +1079,7 @@ struct drm_mm_init_arg {
 #define DRM_IOCTL_BO_INFO               DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
 #define DRM_IOCTL_BO_WAIT_IDLE          DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
 #define DRM_IOCTL_BO_VERSION          DRM_IOR(0xd6, struct drm_bo_version_arg)
-
+#define DRM_IOCTL_MM_INFO               DRM_IOWR(0xd7, struct drm_mm_info_arg)
 
 /*@}*/
 
@@ -1036,8 +1095,7 @@ struct drm_mm_init_arg {
 #define DRM_COMMAND_END                 0xA0
 
 /* typedef area */
-#if !defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || \
-    defined(__NetBSD__) || defined(__DragonFly__)
+#ifndef __KERNEL__
 typedef struct drm_clip_rect drm_clip_rect_t;
 typedef struct drm_tex_region drm_tex_region_t;
 typedef struct drm_hw_lock drm_hw_lock_t;
diff --git a/sys/dev/drm/drmP.h b/sys/dev/drm/drmP.h
index 859e639e25..23ec340ec1 100644
--- a/sys/dev/drm/drmP.h
+++ b/sys/dev/drm/drmP.h
@@ -29,7 +29,6 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drmP.h,v 1.7 2008/07/24 01:27:47 swildner Exp $
  */
 
 #ifndef _DRM_P_H_
@@ -37,8 +36,8 @@
 
 #if defined(_KERNEL) || defined(__KERNEL__)
 
-typedef struct drm_device drm_device_t;
-typedef struct drm_file drm_file_t;
+struct drm_device;
+struct drm_file;
 
 #include <sys/param.h>
 #include <sys/queue.h>
@@ -67,72 +66,36 @@ typedef struct drm_file drm_file_t;
 #include <vm/vm_param.h>
 #include <machine/param.h>
 #include <machine/pmap.h>
-#ifdef __DragonFly__
 #include <sys/bus.h>
 #include <sys/resource.h>
-#else
-#include <machine/bus.h>
-#include <machine/resource.h>
-#endif
+#include <machine/specialreg.h>
 #include <machine/sysarch.h>
 #include <sys/endian.h>
 #include <sys/mman.h>
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 #include <sys/rman.h>
 #include <sys/memrange.h>
-#if __FreeBSD_version >= 800004 || defined(__DragonFly__)
 #include <dev/agp/agpvar.h>
-#else /* __FreeBSD_version >= 800004 */
-#include <pci/agpvar.h>
-#endif /* __FreeBSD_version >= 800004 */
-#include <sys/agpio.h>
-#if defined(__DragonFly__)
-#include <sys/thread2.h>
 #include <sys/device.h>
+#include <sys/agpio.h>
+#include <sys/spinlock.h>
 #include <sys/spinlock2.h>
 #include <bus/pci/pcivar.h>
+#include <bus/pci/pcireg.h>
 #include <sys/selinfo.h>
-#elif __FreeBSD_version >= 500000
-#include <sys/mutex.h>
-#include <dev/pci/pcivar.h>
-#include <sys/selinfo.h>
-#else /* __FreeBSD_version >= 500000 */
-#include <pci/pcivar.h>
-#include <sys/select.h>
-#endif /* __FreeBSD_version < 500000 */
-#elif defined(__NetBSD__)
-#include <machine/mtrr.h>
-#include <sys/vnode.h>
-#include <sys/select.h>
-#include <sys/device.h>
-#include <sys/resourcevar.h>
-#include <sys/lkm.h>
-#include <sys/agpio.h>
-#include <sys/ttycom.h>
-#include <uvm/uvm.h>
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-#include <dev/pci/agpvar.h>
-#elif defined(__OpenBSD__)
-#include <sys/lkm.h>
-#include <uvm/uvm.h>
-#endif
 #include <sys/bus.h>
 
-#include "drm.h"
-#include "drm_linux_list.h"
-#include "drm_atomic.h"
-#include "drm_internal.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/drm_linux_list.h"
+#include "dev/drm/drm_atomic.h"
+#include "dev/drm/drm_internal.h"
 
-#ifdef __FreeBSD__
 #include <opt_drm.h>
 #ifdef DRM_DEBUG
 #undef DRM_DEBUG
 #define DRM_DEBUG_DEFAULT_ON 1
 #endif /* DRM_DEBUG */
-#endif
 
-#if defined(DRM_LINUX) && DRM_LINUX && !defined(__amd64__)
+#if defined(DRM_LINUX) && DRM_LINUX && !defined(__amd64__) && !defined(__DragonFly__) /* XXX */
 #include <sys/file.h>
 #include <sys/proc.h>
 #include <machine/../linux/linux.h>
@@ -145,31 +108,39 @@ typedef struct drm_file drm_file_t;
 #define DRM_LINUX 0
 #endif
 
+/* driver capabilities and requirements mask */
+#define DRIVER_USE_AGP     0x1
+#define DRIVER_REQUIRE_AGP 0x2
+#define DRIVER_USE_MTRR    0x4
+#define DRIVER_PCI_DMA     0x8
+#define DRIVER_SG          0x10
+#define DRIVER_HAVE_DMA    0x20
+#define DRIVER_HAVE_IRQ    0x40
+#define DRIVER_DMA_QUEUE   0x100
+
+
 #define DRM_HASH_SIZE	      16 /* Size of key hash table		  */
 #define DRM_KERNEL_CONTEXT    0	 /* Change drm_resctx if changed	  */
 #define DRM_RESERVED_CONTEXTS 1	 /* Change drm_resctx if changed	  */
 
-#define DRM_MEM_DMA	   0
-#define DRM_MEM_SAREA	   1
-#define DRM_MEM_DRIVER	   2
-#define DRM_MEM_MAGIC	   3
-#define DRM_MEM_IOCTLS	   4
-#define DRM_MEM_MAPS	   5
-#define DRM_MEM_BUFS	   6
-#define DRM_MEM_SEGS	   7
-#define DRM_MEM_PAGES	   8
-#define DRM_MEM_FILES	  9
-#define DRM_MEM_QUEUES	  10
-#define DRM_MEM_CMDS	  11
-#define DRM_MEM_MAPPINGS  12
-#define DRM_MEM_BUFLISTS  13
-#define DRM_MEM_AGPLISTS  14
-#define DRM_MEM_TOTALAGP  15
-#define DRM_MEM_BOUNDAGP  16
-#define DRM_MEM_CTXBITMAP 17
-#define DRM_MEM_STUB	  18
-#define DRM_MEM_SGLISTS	  19
-#define DRM_MEM_DRAWABLE  20
+MALLOC_DECLARE(DRM_MEM_DMA);
+MALLOC_DECLARE(DRM_MEM_SAREA);
+MALLOC_DECLARE(DRM_MEM_DRIVER);
+MALLOC_DECLARE(DRM_MEM_MAGIC);
+MALLOC_DECLARE(DRM_MEM_IOCTLS);
+MALLOC_DECLARE(DRM_MEM_MAPS);
+MALLOC_DECLARE(DRM_MEM_BUFS);
+MALLOC_DECLARE(DRM_MEM_SEGS);
+MALLOC_DECLARE(DRM_MEM_PAGES);
+MALLOC_DECLARE(DRM_MEM_FILES);
+MALLOC_DECLARE(DRM_MEM_QUEUES);
+MALLOC_DECLARE(DRM_MEM_CMDS);
+MALLOC_DECLARE(DRM_MEM_MAPPINGS);
+MALLOC_DECLARE(DRM_MEM_BUFLISTS);
+MALLOC_DECLARE(DRM_MEM_AGPLISTS);
+MALLOC_DECLARE(DRM_MEM_CTXBITMAP);
+MALLOC_DECLARE(DRM_MEM_SGLISTS);
+MALLOC_DECLARE(DRM_MEM_DRAWABLE);
 
 #define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8)
 
@@ -180,8 +151,6 @@ typedef struct drm_file drm_file_t;
 
 #define DRM_IF_VERSION(maj, min) (maj << 16 | min)
 
-MALLOC_DECLARE(M_DRM);
-
 #define __OS_HAS_AGP	1
 
 #define DRM_DEV_MODE	(S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
@@ -193,62 +162,23 @@ MALLOC_DECLARE(M_DRM);
 #define DRM_WAKEUP_INT(w)	wakeup(w)
 #define DRM_INIT_WAITQUEUE(queue) do {(void)(queue);} while (0)
 
-#if defined(__FreeBSD__) && __FreeBSD_version < 502109
-#define bus_alloc_resource_any(dev, type, rid, flags) \
-	bus_alloc_resource(dev, type, rid, 0ul, ~0ul, 1, flags)
-#endif
-
-#if defined(__FreeBSD__) && __FreeBSD_version >= 500000
-#define DRM_CURPROC		curthread
-#define DRM_STRUCTPROC		struct thread
-#define DRM_SPINTYPE		struct mtx
-#define DRM_SPININIT(l,name)	mtx_init(l, name, NULL, MTX_DEF)
-#define DRM_SPINUNINIT(l)	mtx_destroy(l)
-#define DRM_SPINLOCK(l)		mtx_lock(l)
-#define DRM_SPINUNLOCK(u)	mtx_unlock(u)
-#define DRM_SPINLOCK_IRQSAVE(l, irqflags) do {		\
-	mtx_lock(l);					\
-	(void)irqflags;					\
-} while (0)
-#define DRM_SPINUNLOCK_IRQRESTORE(u, irqflags) mtx_unlock(u)
-#define DRM_SPINLOCK_ASSERT(l)	mtx_assert(l, MA_OWNED)
-#define DRM_CURRENTPID		curthread->td_proc->p_pid
-#define DRM_LOCK()		mtx_lock(&dev->dev_lock)
-#define DRM_UNLOCK() 		mtx_unlock(&dev->dev_lock)
-#define DRM_SYSCTL_HANDLER_ARGS	(SYSCTL_HANDLER_ARGS)
-#elif defined(__DragonFly__)
 #define DRM_CURPROC		curthread
 #define DRM_STRUCTPROC		struct thread
-#define DRM_SPINTYPE		struct spinlock
-#define DRM_SPININIT(l,name)	spin_init(l)
-#define DRM_SPINUNINIT(l)	spin_uninit(l)
-#define DRM_SPINLOCK(l)		spin_lock_wr(l)
-#define DRM_SPINUNLOCK(u)	spin_unlock_wr(u)
+#define DRM_SPINTYPE		struct lock
+#define DRM_SPININIT(l,name)	lockinit(l, name, 0, LK_CANRECURSE)
+#define DRM_SPINUNINIT(l)
+#define DRM_SPINLOCK(l)		lockmgr(l, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE)
+#define DRM_SPINUNLOCK(u)	lockmgr(u, LK_RELEASE)
 #define DRM_SPINLOCK_IRQSAVE(l, irqflags) do {		\
-	DRM_SPINLOCK(l);					\
+	DRM_SPINLOCK(l);				\
 	(void)irqflags;					\
 } while (0)
 #define DRM_SPINUNLOCK_IRQRESTORE(u, irqflags) DRM_SPINUNLOCK(u)
 #define DRM_SPINLOCK_ASSERT(l)
 #define DRM_CURRENTPID		curthread->td_proc->p_pid
 #define DRM_LOCK()		DRM_SPINLOCK(&dev->dev_lock)
-#define DRM_UNLOCK() 		DRM_SPINUNLOCK(&dev->dev_lock)
+#define DRM_UNLOCK()		DRM_SPINUNLOCK(&dev->dev_lock)
 #define DRM_SYSCTL_HANDLER_ARGS	(SYSCTL_HANDLER_ARGS)
-#else /* __FreeBSD__ && __FreeBSD_version >= 500000 || __DragonFly__ */
-#define DRM_CURPROC		curproc
-#define DRM_STRUCTPROC		struct proc
-#define DRM_SPINTYPE		struct simplelock
-#define DRM_SPININIT(l,name)
-#define DRM_SPINUNINIT(l)
-#define DRM_SPINLOCK(l)	
-#define DRM_SPINUNLOCK(u)
-#define DRM_SPINLOCK_ASSERT(l)
-#define DRM_CURRENTPID		curproc->p_pid
-#define DRM_LOCK()
-#define DRM_UNLOCK()
-#define DRM_SYSCTL_HANDLER_ARGS	SYSCTL_HANDLER_ARGS
-#define spldrm()		spltty()
-#endif /* __NetBSD__ || __OpenBSD__ */
 
 #define DRM_IRQ_ARGS		void *arg
 typedef void			irqreturn_t;
@@ -262,16 +192,8 @@ enum {
 };
 #define DRM_AGP_MEM		struct agp_memory_info
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 #define drm_get_device_from_kdev(_kdev) (_kdev->si_drv1)
-#elif defined(__NetBSD__)
-#define drm_get_device_from_kdev(_kdev) device_lookup(&drm_cd, minor(_kdev))
-#elif defined(__OpenBSD__)
-#define drm_get_device_from_kdev(_kdev) device_lookup(&drm_cd, \
-    minor(_kdev)))->dv_cfdata->cf_driver->cd_devs[minor(_kdev)]
-#endif
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 #define PAGE_ALIGN(addr) round_page(addr)
 /* DRM_SUSER returns true if the user is superuser */
 #define DRM_SUSER(p)		(priv_check(p, PRIV_DRIVER) == 0)
@@ -279,29 +201,6 @@ enum {
 #define DRM_MTRR_WC		MDF_WRITECOMBINE
 #define jiffies			ticks
 
-#else /* __FreeBSD__ || __DragonFly__ */
-
-#define CDEV_MAJOR		34
-#define PAGE_ALIGN(addr)	(((addr) + PAGE_SIZE - 1) & PAGE_MASK)
-/* DRM_SUSER returns true if the user is superuser */
-#define DRM_SUSER(p)		(suser(p->p_ucred, &p->p_acflag) == 0)
-#define DRM_AGP_FIND_DEVICE()	agp_find_device(0)
-#define DRM_MTRR_WC		MTRR_TYPE_WC
-#define jiffies			hardclock_ticks
-
-typedef drm_device_t *device_t;
-extern struct cfdriver drm_cd;
-#endif /* !__FreeBSD__ && !__DragonFly__ */
-
-/* Capabilities taken from src/sys/dev/pci/pcireg.h. */
-#ifndef PCIY_AGP
-#define PCIY_AGP	0x02
-#endif
-
-#ifndef PCIY_EXPRESS
-#define PCIY_EXPRESS	0x10
-#endif
-
 typedef unsigned long dma_addr_t;
 typedef u_int64_t u64;
 typedef u_int32_t u32;
@@ -330,44 +229,28 @@ typedef u_int8_t u8;
 					"lock; addl $0,0(%%rsp)" : : : "memory");
 #endif
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 #define DRM_READ8(map, offset)						\
-	*(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset))
+	*(volatile u_int8_t *)(((vm_offset_t)(map)->handle) +		\
+	    (vm_offset_t)(offset))
 #define DRM_READ16(map, offset)						\
-	*(volatile u_int16_t *) (((unsigned long)(map)->handle) + (offset))
+	*(volatile u_int16_t *)(((vm_offset_t)(map)->handle) +		\
+	    (vm_offset_t)(offset))
 #define DRM_READ32(map, offset)						\
-	*(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset))
+	*(volatile u_int32_t *)(((vm_offset_t)(map)->handle) +		\
+	    (vm_offset_t)(offset))
 #define DRM_WRITE8(map, offset, val)					\
-	*(volatile u_int8_t *) (((unsigned long)(map)->handle) + (offset)) = val
+	*(volatile u_int8_t *)(((vm_offset_t)(map)->handle) +		\
+	    (vm_offset_t)(offset)) = val
 #define DRM_WRITE16(map, offset, val)					\
-	*(volatile u_int16_t *) (((unsigned long)(map)->handle) + (offset)) = val
+	*(volatile u_int16_t *)(((vm_offset_t)(map)->handle) +		\
+	    (vm_offset_t)(offset)) = val
 #define DRM_WRITE32(map, offset, val)					\
-	*(volatile u_int32_t *)(((unsigned long)(map)->handle) + (offset)) = val
+	*(volatile u_int32_t *)(((vm_offset_t)(map)->handle) +		\
+	    (vm_offset_t)(offset)) = val
 
 #define DRM_VERIFYAREA_READ( uaddr, size )		\
 	(!useracc(__DECONST(caddr_t, uaddr), size, VM_PROT_READ))
 
-#else /* __FreeBSD__ || __DragonFly__ */
-
-typedef vaddr_t vm_offset_t;
-
-#define DRM_READ8(map, offset)		\
-	bus_space_read_1( (map)->bst, (map)->bsh, (offset))
-#define DRM_READ16(map, offset)		\
-	bus_space_read_2( (map)->bst, (map)->bsh, (offset))
-#define DRM_READ32(map, offset)		\
-	bus_space_read_4( (map)->bst, (map)->bsh, (offset))
-#define DRM_WRITE8(map, offset, val)	\
-	bus_space_write_1((map)->bst, (map)->bsh, (offset), (val))
-#define DRM_WRITE16(map, offset, val)	\
-	bus_space_write_2((map)->bst, (map)->bsh, (offset), (val))
-#define DRM_WRITE32(map, offset, val)	\
-	bus_space_write_4((map)->bst, (map)->bsh, (offset), (val))
-
-#define DRM_VERIFYAREA_READ( uaddr, size )		\
-	(!uvm_useracc((caddr_t)uaddr, size, VM_PROT_READ))
-#endif /* !__FreeBSD__ && !__DragonFly__ */
-
 #define DRM_COPY_TO_USER(user, kern, size) \
 	copyout(kern, user, size)
 #define DRM_COPY_FROM_USER(kern, user, size) \
@@ -376,13 +259,8 @@ typedef vaddr_t vm_offset_t;
 	copyin(arg2, arg1, arg3)
 #define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3)	\
 	copyout(arg2, arg1, arg3)
-#if __FreeBSD_version > 500000
 #define DRM_GET_USER_UNCHECKED(val, uaddr)		\
 	((val) = fuword32(uaddr), 0)
-#else
-#define DRM_GET_USER_UNCHECKED(val, uaddr)		\
-	((val) = fuword(uaddr), 0)
-#endif
 
 #define cpu_to_le32(x) htole32(x)
 #define le32_to_cpu(x) le32toh(x)
@@ -405,53 +283,30 @@ do {									\
 	}								\
 } while (0)
 
-#if defined(__FreeBSD__) && __FreeBSD_version > 500000
 /* Returns -errno to shared code */
 #define DRM_WAIT_ON( ret, queue, timeout, condition )		\
-for ( ret = 0 ; !ret && !(condition) ; ) {			\
-	DRM_UNLOCK();						\
-	mtx_lock(&dev->irq_lock);				\
-	if (!(condition))					\
-	   ret = -mtx_sleep(&(queue), &dev->irq_lock, 		\
-			 PZERO | PCATCH, "drmwtq", (timeout));	\
-	mtx_unlock(&dev->irq_lock);				\
-	DRM_LOCK();						\
-}
-#elif defined(__DragonFly__)
-#define DRM_WAIT_ON( ret, queue, timeout, condition )		\
 for ( ret = 0 ; !ret && !(condition) ; ) {			\
 	DRM_UNLOCK();						\
 	lwkt_serialize_enter(&dev->irq_lock);			\
 	if (!(condition)) {					\
-	   crit_enter();					\
-	   tsleep_interlock(&(queue));				\
-	   lwkt_serialize_exit(&dev->irq_lock);			\
-	   ret = -tsleep(&(queue), PCATCH,			\
-			 "drmwtq", (timeout));			\
-	   crit_exit();						\
+            crit_enter();					\
+            tsleep_interlock(&(queue));				\
+            lwkt_serialize_exit(&dev->irq_lock);		\
+            ret = -tsleep(&(queue), PCATCH,			\
+			  "drmwtq", (timeout));			\
+            crit_exit();					\
 	} else {						\
 		lwkt_serialize_exit(&dev->irq_lock);		\
 	}							\
 	DRM_LOCK();						\
 }
-#else
-/* Returns -errno to shared code */
-#define DRM_WAIT_ON( ret, queue, timeout, condition )	\
-for ( ret = 0 ; !ret && !(condition) ; ) {		\
-        int s = spldrm();				\
-	if (!(condition))				\
-	   ret = -tsleep( &(queue), PZERO | PCATCH, 	\
-			 "drmwtq", (timeout) );		\
-	splx(s);					\
-}
-#endif
 
-#ifdef __DragonFly__
 #define printf	kprintf
 #define snprintf ksnprintf
 #define sscanf	ksscanf
 #define malloc	kmalloc
 #define realloc	krealloc
+#define reallocf krealloc	/* XXX XXX XXX */
 
 __inline static void
 free(void *addr, struct malloc_type *type)
@@ -459,18 +314,17 @@ free(void *addr, struct malloc_type *type)
 	if (addr != NULL)
 		kfree(addr, type);
 }
-#endif
 
-#define DRM_ERROR(fmt, arg...) \
+#define DRM_ERROR(fmt, ...) \
 	printf("error: [" DRM_NAME ":pid%d:%s] *ERROR* " fmt,		\
-	    DRM_CURRENTPID, __func__ , ## arg)
-
-#define DRM_INFO(fmt, arg...)  printf("info: [" DRM_NAME "] " fmt , ## arg)
+	    DRM_CURRENTPID, __func__ , ##__VA_ARGS__)
 
-#define DRM_DEBUG(fmt, arg...) do {					\
+#define DRM_INFO(fmt, ...)  printf("info: [" DRM_NAME "] " fmt , ##__VA_ARGS__)
+	
+#define DRM_DEBUG(fmt, ...) do {					\
 	if (drm_debug_flag)						\
 		printf("[" DRM_NAME ":pid%d:%s] " fmt, DRM_CURRENTPID,	\
-			__func__ , ## arg);				\
+			__func__ , ##__VA_ARGS__);			\
 } while (0)
 
 typedef struct drm_pci_id_list
@@ -481,12 +335,19 @@ typedef struct drm_pci_id_list
 	char *name;
 } drm_pci_id_list_t;
 
+struct drm_msi_blacklist_entry
+{
+	int vendor;
+	int device;
+};
+
 #define DRM_AUTH	0x1
 #define DRM_MASTER	0x2
 #define DRM_ROOT_ONLY	0x4
 typedef struct drm_ioctl_desc {
 	unsigned long cmd;
-	int (*func)(drm_device_t *dev, void *data, struct drm_file *file_priv);
+	int (*func)(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv);
 	int flags;
 } drm_ioctl_desc_t;
 /**
@@ -544,12 +405,8 @@ typedef struct drm_freelist {
 typedef struct drm_dma_handle {
 	void *vaddr;
 	bus_addr_t busaddr;
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	bus_dma_tag_t tag;
 	bus_dmamap_t map;
-#elif defined(__NetBSD__)
-	bus_dma_segment_t seg;
-#endif
 } drm_dma_handle_t;
 
 typedef struct drm_buf_entry {
@@ -566,6 +423,7 @@ typedef struct drm_buf_entry {
 typedef TAILQ_HEAD(drm_file_list, drm_file) drm_file_list_t;
 struct drm_file {
 	TAILQ_ENTRY(drm_file) link;
+	struct drm_device *dev;
 	int		  authenticated;
 	int		  master;
 	int		  minor;
@@ -578,13 +436,14 @@ struct drm_file {
 };
 
 typedef struct drm_lock_data {
-	drm_hw_lock_t	  *hw_lock;	/* Hardware lock		   */
+	struct drm_hw_lock	*hw_lock;	/* Hardware lock		   */
 	struct drm_file   *file_priv;   /* Unique identifier of holding process (NULL is kernel)*/
 	int		  lock_queue;	/* Queue of blocked processes	   */
 	unsigned long	  lock_time;	/* Time of last lock in jiffies	   */
 } drm_lock_data_t;
 
-/* This structure, in the drm_device_t, is always initialized while the device
+/* This structure, in the struct drm_device, is always initialized while the
+ * device
  * is open.  dev->dma_lock protects the incrementing of dev->buf_use, which
  * when set marks that no further bufs may be allocated until device teardown
  * occurs (when the last open of the device has closed).  The high/low
@@ -628,11 +487,11 @@ typedef struct drm_agp_head {
 } drm_agp_head_t;
 
 typedef struct drm_sg_mem {
-	unsigned long   handle;
-	void            *virtual;
-	int             pages;
-	dma_addr_t	*busaddr;
-	drm_dma_handle_t *dmah;	/* Handle to PCI memory for ATI PCIGART table */
+	unsigned long		  handle;
+	void			 *virtual;
+	int			  pages;
+	dma_addr_t		 *busaddr;
+	struct drm_dma_handle	 *dmah;		/* Handle to PCI memory  */
 } drm_sg_mem_t;
 
 typedef TAILQ_HEAD(drm_map_list, drm_local_map) drm_map_list_t;
@@ -640,8 +499,8 @@ typedef TAILQ_HEAD(drm_map_list, drm_local_map) drm_map_list_t;
 typedef struct drm_local_map {
 	unsigned long	offset;	 /* Physical address (0 for SAREA)*/
 	unsigned long	size;	 /* Physical size (bytes)	    */
-	drm_map_type_t	type;	 /* Type of memory mapped		    */
-	drm_map_flags_t flags;	 /* Flags				    */
+	enum drm_map_type	type;	 /* Type of memory mapped		    */
+	enum drm_map_flags	flags;	 /* Flags				    */
 	void		*handle; /* User-space: "Handle" to pass to mmap    */
 				 /* Kernel-space: kernel-virtual address    */
 	int		mtrr;	 /* Boolean: MTRR used */
@@ -662,6 +521,19 @@ typedef struct drm_vbl_sig {
 	int		pid;
 } drm_vbl_sig_t;
 
+struct drm_vblank_info {
+	wait_queue_head_t queue;	/* vblank wait queue */
+	atomic_t count;			/* number of VBLANK interrupts */
+					/* (driver must alloc the right number of counters) */
+	struct drm_vbl_sig_list sigs;	/* signal list to send on VBLANK */
+	atomic_t refcount;		/* number of users of vblank interrupts */
+	u32 last;			/* protected by dev->vbl_lock, used */
+					/* for wraparound handling */
+	int enabled;			/* so we don't call enable more than */
+					/* once per disable */
+	int inmodeset;			/* Display driver is setting mode */
+};
+
 /* location of GART table */
 #define DRM_ATI_GART_MAIN 1
 #define DRM_ATI_GART_FB   2
@@ -675,38 +547,50 @@ struct drm_ati_pcigart_info {
 	int gart_reg_if;
 	void *addr;
 	dma_addr_t bus_addr;
+	dma_addr_t table_mask;
+	dma_addr_t member_mask;
+	struct drm_dma_handle *table_handle;
 	drm_local_map_t mapping;
 	int table_size;
+	struct drm_dma_handle *dmah; /* handle for ATI PCIGART table */
 };
 
+#ifndef DMA_BIT_MASK
+#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : (1ULL<<(n)) - 1)
+#endif
+
+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))
+
 struct drm_driver_info {
 	int	(*load)(struct drm_device *, unsigned long flags);
 	int	(*firstopen)(struct drm_device *);
-	int	(*open)(struct drm_device *, drm_file_t *);
+	int	(*open)(struct drm_device *, struct drm_file *);
 	void	(*preclose)(struct drm_device *, struct drm_file *file_priv);
-	void	(*postclose)(struct drm_device *, drm_file_t *);
+	void	(*postclose)(struct drm_device *, struct drm_file *);
 	void	(*lastclose)(struct drm_device *);
 	int	(*unload)(struct drm_device *);
 	void	(*reclaim_buffers_locked)(struct drm_device *,
 					  struct drm_file *file_priv);
-	int	(*dma_ioctl)(drm_device_t *dev, void *data, struct drm_file *file_priv);
+	int	(*dma_ioctl)(struct drm_device *dev, void *data,
+			     struct drm_file *file_priv);
 	void	(*dma_ready)(struct drm_device *);
 	int	(*dma_quiescent)(struct drm_device *);
 	int	(*dma_flush_block_and_flush)(struct drm_device *, int context,
-					     drm_lock_flags_t flags);
+					     enum drm_lock_flags flags);
 	int	(*dma_flush_unblock)(struct drm_device *, int context,
-				     drm_lock_flags_t flags);
+				     enum drm_lock_flags flags);
 	int	(*context_ctor)(struct drm_device *dev, int context);
 	int	(*context_dtor)(struct drm_device *dev, int context);
 	int	(*kernel_context_switch)(struct drm_device *dev, int old,
 					 int new);
 	int	(*kernel_context_switch_unlock)(struct drm_device *dev);
-	void	(*irq_preinstall)(drm_device_t *dev);
-	void	(*irq_postinstall)(drm_device_t *dev);
-	void	(*irq_uninstall)(drm_device_t *dev);
+	void	(*irq_preinstall)(struct drm_device *dev);
+	int	(*irq_postinstall)(struct drm_device *dev);
+	void	(*irq_uninstall)(struct drm_device *dev);
 	void	(*irq_handler)(DRM_IRQ_ARGS);
-	int	(*vblank_wait)(drm_device_t *dev, unsigned int *sequence);
-	int	(*vblank_wait2)(drm_device_t *dev, unsigned int *sequence);
+	u32	(*get_vblank_counter)(struct drm_device *dev, int crtc);
+	int	(*enable_vblank)(struct drm_device *dev, int crtc);
+	void	(*disable_vblank)(struct drm_device *dev, int crtc);
 
 	drm_pci_id_list_t *id_entry;	/* PCI ID, name, and chipset private */
 
@@ -735,30 +619,17 @@ struct drm_driver_info {
 	const char *desc;		/* Longer driver name		   */
 	const char *date;		/* Date of last major changes.	   */
 
-	unsigned use_agp :1;
-	unsigned require_agp :1;
-	unsigned use_sg :1;
-	unsigned use_dma :1;
-	unsigned use_pci_dma :1;
-	unsigned use_dma_queue :1;
-	unsigned use_irq :1;
-	unsigned use_vbl_irq :1;
-	unsigned use_vbl_irq2 :1;
-	unsigned use_mtrr :1;
+	u32 driver_features;
 };
 
 /* Length for the array of resource pointers for drm_get_resource_*. */
-#define DRM_MAX_PCI_RESOURCE	3
+#define DRM_MAX_PCI_RESOURCE	6
 
 /** 
  * DRM device functions structure
  */
 struct drm_device {
-#if defined(__NetBSD__) || defined(__OpenBSD__)
-	struct device	  device; /* softc is an extension of struct device */
-#endif
-
-	struct drm_driver_info driver;
+	struct drm_driver_info *driver;
 	drm_pci_id_list_t *id_entry;	/* PCI ID, name, and chipset private */
 
 	u_int16_t pci_device;		/* PCI device id */
@@ -766,24 +637,17 @@ struct drm_device {
 
 	char		  *unique;	/* Unique identifier: e.g., busid  */
 	int		  unique_len;	/* Length of unique field	   */
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	device_t	  device;	/* Device instance from newbus     */
-#endif
 	struct cdev	  *devnode;	/* Device number for mknod	   */
 	int		  if_version;	/* Highest interface version set */
 
 	int		  flags;	/* Flags to open(2)		   */
 
 				/* Locks */
-#if defined(__FreeBSD__) && __FreeBSD_version > 500000
-	struct mtx	  dma_lock;	/* protects dev->dma */
-	struct mtx	  irq_lock;	/* protects irq condition checks */
-	struct mtx	  dev_lock;	/* protects everything else */
-#elif defined(__DragonFly__)
-	struct spinlock	  dma_lock;	/* protects dev->dma */
+	DRM_SPINTYPE	  vbl_lock;	/* protects vblank operations */
+	DRM_SPINTYPE	  dma_lock;	/* protects dev->dma */
 	struct lwkt_serialize irq_lock;	/* protects irq condition checks */
-	struct spinlock	  dev_lock;	/* protects everything else */
-#endif
+	DRM_SPINTYPE	  dev_lock;	/* protects everything else */
 	DRM_SPINTYPE	  drw_lock;
 
 				/* Usage Counters */
@@ -792,7 +656,7 @@ struct drm_device {
 
 				/* Performance counters */
 	unsigned long     counters;
-	drm_stat_type_t   types[15];
+	enum drm_stat_type	types[15];
 	atomic_t          counts[15];
 
 				/* Authentication */
@@ -813,12 +677,9 @@ struct drm_device {
 				/* Context support */
 	int		  irq;		/* Interrupt used by board	   */
 	int		  irq_enabled;	/* True if the irq handler is enabled */
-#if defined(__FreeBSD__) || defined(__DragonFly__)
+	int		  msi_enabled;	/* MSI enabled */
 	int		  irqrid;	/* Interrupt used by board */
 	struct resource   *irqr;	/* Resource for interrupt used by board	   */
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	struct pci_attach_args  pa;
-#endif
 	void		  *irqh;	/* Handle from bus_setup_intr      */
 
 	/* Storage of resource pointers for drm_get_resource_* */
@@ -832,15 +693,15 @@ struct drm_device {
 
 	atomic_t	  context_flag;	/* Context swapping flag	   */
 	int		  last_context;	/* Last current context		   */
-   	int		  vbl_queue;	/* vbl wait channel */
-   	atomic_t          vbl_received;
-   	atomic_t          vbl_received2;
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
+	int		  vblank_disable_allowed;
+	atomic_t 	  vbl_signal_pending;	/* number of signals pending on all crtcs */
+	struct callout	  vblank_disable_timer;
+	u32		  max_vblank_count;	/* size of vblank counter register */
+	struct drm_vblank_info *vblank;		/* per crtc vblank info */
+	int		  num_crtcs;
+
 	struct sigio      *buf_sigio;	/* Processes waiting for SIGIO     */
-#elif defined(__NetBSD__)
-	pid_t		  buf_pgid;
-#endif
 
 				/* Sysctl support */
 	struct drm_sysctl_info *sysctl;
@@ -852,232 +713,307 @@ struct drm_device {
 	unsigned int	  agp_buffer_token;
 	drm_local_map_t   *agp_buffer_map;
 
-#ifdef __FreeBSD__
-	struct unrhdr	  *drw_unrhdr;
-#endif
 	/* RB tree of drawable infos */
 	RB_HEAD(drawable_tree, bsd_drm_drawable_info) drw_head;
-
-	struct task	  locked_task;
-	void		  (*locked_task_call)(drm_device_t *dev);
 };
 
+static __inline__ int drm_core_check_feature(struct drm_device *dev,
+					     int feature)
+{
+	return ((dev->driver->driver_features & feature) ? 1 : 0);
+}
+
+#if __OS_HAS_AGP
+static inline int drm_core_has_AGP(struct drm_device *dev)
+{
+	return drm_core_check_feature(dev, DRIVER_USE_AGP);
+}
+#else
+#define drm_core_has_AGP(dev) (0)
+#endif
+
 extern int	drm_debug_flag;
 
 /* Device setup support (drm_drv.c) */
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-int	drm_probe(device_t nbdev, drm_pci_id_list_t *idlist);
-int	drm_attach(device_t nbdev, drm_pci_id_list_t *idlist);
-int	drm_detach(device_t nbdev);
+int	drm_probe(device_t kdev, drm_pci_id_list_t *idlist);
+int	drm_attach(device_t kdev, drm_pci_id_list_t *idlist);
+void	drm_close(void *data);
+int	drm_detach(device_t kdev);
 d_ioctl_t drm_ioctl;
 d_open_t drm_open;
-d_close_t drm_close;
 d_read_t drm_read;
 d_poll_t drm_poll;
 d_mmap_t drm_mmap;
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-int	drm_probe(struct pci_attach_args *pa, drm_pci_id_list_t *idlist);
-int	drm_attach(struct pci_attach_args *pa, dev_t kdev, drm_pci_id_list_t *idlist);
-dev_type_ioctl(drm_ioctl);
-dev_type_open(drm_open);
-dev_type_close(drm_close);
-dev_type_read(drm_read);
-dev_type_poll(drm_poll);
-dev_type_mmap(drm_mmap);
-#endif
-extern drm_local_map_t	*drm_getsarea(drm_device_t *dev);
+extern drm_local_map_t	*drm_getsarea(struct drm_device *dev);
 
 /* File operations helpers (drm_fops.c) */
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-extern int		drm_open_helper(struct cdev *kdev, int flags, int fmt, 
-					 DRM_STRUCTPROC *p, drm_device_t *dev);
-extern drm_file_t	*drm_find_file_by_proc(drm_device_t *dev, 
-					 DRM_STRUCTPROC *p);
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-extern int		drm_open_helper(dev_t kdev, int flags, int fmt, 
-					DRM_STRUCTPROC *p, drm_device_t *dev);
-extern drm_file_t	*drm_find_file_by_proc(drm_device_t *dev, 
-					       DRM_STRUCTPROC *p);
-#endif /* __NetBSD__ || __OpenBSD__ */
+extern int		drm_open_helper(struct cdev *kdev, int flags, int fmt,
+					 DRM_STRUCTPROC *p,
+					struct drm_device *dev);
+extern struct drm_file	*drm_find_file_by_proc(struct drm_device *dev,
+					DRM_STRUCTPROC *p);
 
 /* Memory management support (drm_memory.c) */
 void	drm_mem_init(void);
 void	drm_mem_uninit(void);
-void	*drm_alloc(size_t size, int area);
-void	*drm_calloc(size_t nmemb, size_t size, int area);
-void	*drm_realloc(void *oldpt, size_t oldsize, size_t size,
-				   int area);
-void	drm_free(void *pt, size_t size, int area);
-void	*drm_ioremap(drm_device_t *dev, drm_local_map_t *map);
+void	*drm_ioremap_wc(struct drm_device *dev, drm_local_map_t *map);
+void	*drm_ioremap(struct drm_device *dev, drm_local_map_t *map);
 void	drm_ioremapfree(drm_local_map_t *map);
 int	drm_mtrr_add(unsigned long offset, size_t size, int flags);
 int	drm_mtrr_del(int handle, unsigned long offset, size_t size, int flags);
 
-int	drm_context_switch(drm_device_t *dev, int old, int new);
-int	drm_context_switch_complete(drm_device_t *dev, int new);
+int	drm_context_switch(struct drm_device *dev, int old, int new);
+int	drm_context_switch_complete(struct drm_device *dev, int new);
 
-int	drm_ctxbitmap_init(drm_device_t *dev);
-void	drm_ctxbitmap_cleanup(drm_device_t *dev);
-void	drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle);
-int	drm_ctxbitmap_next(drm_device_t *dev);
+int	drm_ctxbitmap_init(struct drm_device *dev);
+void	drm_ctxbitmap_cleanup(struct drm_device *dev);
+void	drm_ctxbitmap_free(struct drm_device *dev, int ctx_handle);
+int	drm_ctxbitmap_next(struct drm_device *dev);
 
 /* Locking IOCTL support (drm_lock.c) */
-int	drm_lock_take(__volatile__ unsigned int *lock,
-				    unsigned int context);
-int	drm_lock_transfer(drm_device_t *dev,
-					__volatile__ unsigned int *lock,
-					unsigned int context);
-int	drm_lock_free(drm_device_t *dev,
-				    __volatile__ unsigned int *lock,
-				    unsigned int context);
+int	drm_lock_take(struct drm_lock_data *lock_data,
+		      unsigned int context);
+int	drm_lock_transfer(struct drm_lock_data *lock_data,
+			  unsigned int context);
+int	drm_lock_free(struct drm_lock_data *lock_data,
+		      unsigned int context);
 
 /* Buffer management support (drm_bufs.c) */
-unsigned long drm_get_resource_start(drm_device_t *dev, unsigned int resource);
-unsigned long drm_get_resource_len(drm_device_t *dev, unsigned int resource);
-void	drm_rmmap(drm_device_t *dev, drm_local_map_t *map);
+unsigned long drm_get_resource_start(struct drm_device *dev,
+				     unsigned int resource);
+unsigned long drm_get_resource_len(struct drm_device *dev,
+				   unsigned int resource);
+void	drm_rmmap(struct drm_device *dev, drm_local_map_t *map);
 int	drm_order(unsigned long size);
-int	drm_addmap(drm_device_t * dev, unsigned long offset, unsigned long size,
-		   drm_map_type_t type, drm_map_flags_t flags,
+int	drm_addmap(struct drm_device *dev, unsigned long offset,
+		   unsigned long size,
+		   enum drm_map_type type, enum drm_map_flags flags,
 		   drm_local_map_t **map_ptr);
-int	drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request);
-int	drm_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request);
-int	drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request);
+int	drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc *request);
+int	drm_addbufs_sg(struct drm_device *dev, struct drm_buf_desc *request);
+int	drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc *request);
 
 /* DMA support (drm_dma.c) */
-int	drm_dma_setup(drm_device_t *dev);
-void	drm_dma_takedown(drm_device_t *dev);
-void	drm_free_buffer(drm_device_t *dev, drm_buf_t *buf);
-void	drm_reclaim_buffers(drm_device_t *dev, struct drm_file *file_priv);
+int	drm_dma_setup(struct drm_device *dev);
+void	drm_dma_takedown(struct drm_device *dev);
+void	drm_free_buffer(struct drm_device *dev, drm_buf_t *buf);
+void	drm_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv);
 #define drm_core_reclaim_buffers drm_reclaim_buffers
 
 /* IRQ support (drm_irq.c) */
-int	drm_irq_install(drm_device_t *dev);
-int	drm_irq_uninstall(drm_device_t *dev);
+int	drm_irq_install(struct drm_device *dev);
+int	drm_irq_uninstall(struct drm_device *dev);
 irqreturn_t drm_irq_handler(DRM_IRQ_ARGS);
-void	drm_driver_irq_preinstall(drm_device_t *dev);
-void	drm_driver_irq_postinstall(drm_device_t *dev);
-void	drm_driver_irq_uninstall(drm_device_t *dev);
-int	drm_vblank_wait(drm_device_t *dev, unsigned int *vbl_seq);
-void	drm_vbl_send_signals(drm_device_t *dev);
+void	drm_driver_irq_preinstall(struct drm_device *dev);
+void	drm_driver_irq_postinstall(struct drm_device *dev);
+void	drm_driver_irq_uninstall(struct drm_device *dev);
+void	drm_handle_vblank(struct drm_device *dev, int crtc);
+u32	drm_vblank_count(struct drm_device *dev, int crtc);
+int	drm_vblank_get(struct drm_device *dev, int crtc);
+void	drm_vblank_put(struct drm_device *dev, int crtc);
+void	drm_vblank_cleanup(struct drm_device *dev);
+int	drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq);
+int	drm_vblank_init(struct drm_device *dev, int num_crtcs);
+void	drm_vbl_send_signals(struct drm_device *dev, int crtc);
+int 	drm_modeset_ctl(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
 
 /* AGP/PCI Express/GART support (drm_agpsupport.c) */
-int	drm_device_is_agp(drm_device_t *dev);
-int	drm_device_is_pcie(drm_device_t *dev);
+int	drm_device_is_agp(struct drm_device *dev);
+int	drm_device_is_pcie(struct drm_device *dev);
 drm_agp_head_t *drm_agp_init(void);
-int	drm_agp_acquire(drm_device_t *dev);
-int	drm_agp_release(drm_device_t *dev);
-int	drm_agp_info(drm_device_t * dev, drm_agp_info_t *info);
-int	drm_agp_enable(drm_device_t *dev, drm_agp_mode_t mode);
+int	drm_agp_acquire(struct drm_device *dev);
+int	drm_agp_release(struct drm_device *dev);
+int	drm_agp_info(struct drm_device * dev, struct drm_agp_info *info);
+int	drm_agp_enable(struct drm_device *dev, struct drm_agp_mode mode);
 void	*drm_agp_allocate_memory(size_t pages, u32 type);
 int	drm_agp_free_memory(void *handle);
 int	drm_agp_bind_memory(void *handle, off_t start);
 int	drm_agp_unbind_memory(void *handle);
-int	drm_agp_alloc(drm_device_t *dev, drm_agp_buffer_t *request);
-int	drm_agp_free(drm_device_t *dev, drm_agp_buffer_t *request);
-int	drm_agp_bind(drm_device_t *dev, drm_agp_binding_t *request);
-int	drm_agp_unbind(drm_device_t *dev, drm_agp_binding_t *request);
+int	drm_agp_alloc(struct drm_device *dev, struct drm_agp_buffer *request);
+int	drm_agp_free(struct drm_device *dev, struct drm_agp_buffer *request);
+int	drm_agp_bind(struct drm_device *dev, struct drm_agp_binding *request);
+int	drm_agp_unbind(struct drm_device *dev, struct drm_agp_binding *request);
 
 /* Scatter Gather Support (drm_scatter.c) */
 void	drm_sg_cleanup(drm_sg_mem_t *entry);
-int	drm_sg_alloc(drm_device_t * dev, drm_scatter_gather_t * request);
+int	drm_sg_alloc(struct drm_device *dev, struct drm_scatter_gather * request);
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 /* sysctl support (drm_sysctl.h) */
-extern int		drm_sysctl_init(drm_device_t *dev);
-extern int		drm_sysctl_cleanup(drm_device_t *dev);
-#endif /* __FreeBSD__ || __DragonFly__ */
+extern int		drm_sysctl_init(struct drm_device *dev);
+extern int		drm_sysctl_cleanup(struct drm_device *dev);
 
 /* ATI PCIGART support (ati_pcigart.c) */
-int	drm_ati_pcigart_init(drm_device_t *dev,
+int	drm_ati_pcigart_init(struct drm_device *dev,
 				struct drm_ati_pcigart_info *gart_info);
-int	drm_ati_pcigart_cleanup(drm_device_t *dev,
+int	drm_ati_pcigart_cleanup(struct drm_device *dev,
 				struct drm_ati_pcigart_info *gart_info);
 
 /* Locking IOCTL support (drm_drv.c) */
-int	drm_lock(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_unlock(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_version(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_setversion(drm_device_t *dev, void *data, struct drm_file *file_priv);
+int	drm_lock(struct drm_device *dev, void *data,
+		 struct drm_file *file_priv);
+int	drm_unlock(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv);
+int	drm_version(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv);
+int	drm_setversion(struct drm_device *dev, void *data,
+		       struct drm_file *file_priv);
 
 /* Misc. IOCTL support (drm_ioctl.c) */
-int	drm_irq_by_busid(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_getunique(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_setunique(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_getmap(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_getclient(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_getstats(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_noop(drm_device_t *dev, void *data, struct drm_file *file_priv);
+int	drm_irq_by_busid(struct drm_device *dev, void *data,
+			 struct drm_file *file_priv);
+int	drm_getunique(struct drm_device *dev, void *data,
+		      struct drm_file *file_priv);
+int	drm_setunique(struct drm_device *dev, void *data,
+		      struct drm_file *file_priv);
+int	drm_getmap(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv);
+int	drm_getclient(struct drm_device *dev, void *data,
+		      struct drm_file *file_priv);
+int	drm_getstats(struct drm_device *dev, void *data,
+		     struct drm_file *file_priv);
+int	drm_noop(struct drm_device *dev, void *data,
+		 struct drm_file *file_priv);
 
 /* Context IOCTL support (drm_context.c) */
-int	drm_resctx(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_addctx(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_modctx(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_getctx(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_switchctx(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_newctx(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_rmctx(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_setsareactx(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_getsareactx(drm_device_t *dev, void *data, struct drm_file *file_priv);
+int	drm_resctx(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv);
+int	drm_addctx(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv);
+int	drm_modctx(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv);
+int	drm_getctx(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv);
+int	drm_switchctx(struct drm_device *dev, void *data,
+		      struct drm_file *file_priv);
+int	drm_newctx(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv);
+int	drm_rmctx(struct drm_device *dev, void *data,
+		  struct drm_file *file_priv);
+int	drm_setsareactx(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+int	drm_getsareactx(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
 
 /* Drawable IOCTL support (drm_drawable.c) */
-int	drm_adddraw(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_rmdraw(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_update_draw(drm_device_t *dev, void *data, struct drm_file *file_priv);
-struct drm_drawable_info *drm_get_drawable_info(drm_device_t *dev, int handle);
+int	drm_adddraw(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv);
+int	drm_rmdraw(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv);
+int	drm_update_draw(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+struct drm_drawable_info *drm_get_drawable_info(struct drm_device *dev,
+						int handle);
+
+/* Drawable support (drm_drawable.c) */
+void drm_drawable_free_all(struct drm_device *dev);
 
 /* Authentication IOCTL support (drm_auth.c) */
-int	drm_getmagic(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_authmagic(drm_device_t *dev, void *data, struct drm_file *file_priv);
+int	drm_getmagic(struct drm_device *dev, void *data,
+		     struct drm_file *file_priv);
+int	drm_authmagic(struct drm_device *dev, void *data,
+		      struct drm_file *file_priv);
 
 /* Buffer management support (drm_bufs.c) */
-int	drm_addmap_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_rmmap_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_addbufs_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_infobufs(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_markbufs(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_freebufs(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_mapbufs(drm_device_t *dev, void *data, struct drm_file *file_priv);
+int	drm_addmap_ioctl(struct drm_device *dev, void *data,
+			 struct drm_file *file_priv);
+int	drm_rmmap_ioctl(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+int	drm_addbufs(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv);
+int	drm_infobufs(struct drm_device *dev, void *data,
+		     struct drm_file *file_priv);
+int	drm_markbufs(struct drm_device *dev, void *data,
+		     struct drm_file *file_priv);
+int	drm_freebufs(struct drm_device *dev, void *data,
+		     struct drm_file *file_priv);
+int	drm_mapbufs(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv);
 
 /* DMA support (drm_dma.c) */
-int	drm_dma(drm_device_t *dev, void *data, struct drm_file *file_priv);
+int	drm_dma(struct drm_device *dev, void *data, struct drm_file *file_priv);
 
 /* IRQ support (drm_irq.c) */
-int	drm_control(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_wait_vblank(drm_device_t *dev, void *data, struct drm_file *file_priv);
-void	drm_locked_tasklet(drm_device_t *dev,
-			   void (*tasklet)(drm_device_t *dev));
+int	drm_control(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv);
+int	drm_wait_vblank(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
 
 /* AGP/GART support (drm_agpsupport.c) */
-int	drm_agp_acquire_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_agp_release_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_agp_enable_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_agp_info_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_agp_alloc_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_agp_free_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_agp_unbind_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_agp_bind_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
+int	drm_agp_acquire_ioctl(struct drm_device *dev, void *data,
+			      struct drm_file *file_priv);
+int	drm_agp_release_ioctl(struct drm_device *dev, void *data,
+			      struct drm_file *file_priv);
+int	drm_agp_enable_ioctl(struct drm_device *dev, void *data,
+			     struct drm_file *file_priv);
+int	drm_agp_info_ioctl(struct drm_device *dev, void *data,
+			   struct drm_file *file_priv);
+int	drm_agp_alloc_ioctl(struct drm_device *dev, void *data,
+			    struct drm_file *file_priv);
+int	drm_agp_free_ioctl(struct drm_device *dev, void *data,
+			   struct drm_file *file_priv);
+int	drm_agp_unbind_ioctl(struct drm_device *dev, void *data,
+			     struct drm_file *file_priv);
+int	drm_agp_bind_ioctl(struct drm_device *dev, void *data,
+			   struct drm_file *file_priv);
 
 /* Scatter Gather Support (drm_scatter.c) */
-int	drm_sg_alloc_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv);
-int	drm_sg_free(drm_device_t *dev, void *data, struct drm_file *file_priv);
+int	drm_sg_alloc_ioctl(struct drm_device *dev, void *data,
+			   struct drm_file *file_priv);
+int	drm_sg_free(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv);
 
 /* consistent PCI memory functions (drm_pci.c) */
-drm_dma_handle_t *drm_pci_alloc(drm_device_t *dev, size_t size, size_t align,
-				dma_addr_t maxaddr);
-void	drm_pci_free(drm_device_t *dev, drm_dma_handle_t *dmah);
+drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size,
+				size_t align, dma_addr_t maxaddr);
+void	drm_pci_free(struct drm_device *dev, drm_dma_handle_t *dmah);
+
+/* Inline replacements for drm_alloc and friends */
+static __inline__ void *
+drm_alloc(size_t size, struct malloc_type *area)
+{
+	return malloc(size, area, M_NOWAIT);
+}
+
+static __inline__ void *
+drm_calloc(size_t nmemb, size_t size, struct malloc_type *area)
+{
+	return malloc(size * nmemb, area, M_NOWAIT | M_ZERO);
+}
+
+static __inline__ void *
+drm_realloc(void *oldpt, size_t oldsize, size_t size,
+    struct malloc_type *area)
+{
+	return reallocf(oldpt, size, area, M_NOWAIT);
+}
+
+static __inline__ void
+drm_free(void *pt, size_t size, struct malloc_type *area)
+{
+	free(pt, area);
+}
 
 /* Inline replacements for DRM_IOREMAP macros */
-static __inline__ void drm_core_ioremap(struct drm_local_map *map, struct drm_device *dev)
+static __inline__ void
+drm_core_ioremap_wc(struct drm_local_map *map, struct drm_device *dev)
+{
+	map->handle = drm_ioremap_wc(dev, map);
+}
+static __inline__ void
+drm_core_ioremap(struct drm_local_map *map, struct drm_device *dev)
 {
 	map->handle = drm_ioremap(dev, map);
 }
-static __inline__ void drm_core_ioremapfree(struct drm_local_map *map, struct drm_device *dev)
+static __inline__ void
+drm_core_ioremapfree(struct drm_local_map *map, struct drm_device *dev)
 {
 	if ( map->handle && map->size )
 		drm_ioremapfree(map);
 }
 
-static __inline__ struct drm_local_map *drm_core_findmap(struct drm_device *dev, unsigned long offset)
+static __inline__ struct drm_local_map *
+drm_core_findmap(struct drm_device *dev, unsigned long offset)
 {
 	drm_local_map_t *map;
 
diff --git a/sys/dev/drm/drm_agpsupport.c b/sys/dev/drm/drm_agpsupport.c
index 36bc2deb7e..c610c03df7 100644
--- a/sys/dev/drm/drm_agpsupport.c
+++ b/sys/dev/drm/drm_agpsupport.c
@@ -26,7 +26,6 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_agpsupport.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_agpsupport.c
@@ -34,29 +33,15 @@
  * the DRM's AGP ioctls.
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
-#ifdef __FreeBSD__
-#if __FreeBSD_version >= 800004
-#include <dev/agp/agpreg.h>
-#else /* __FreeBSD_version >= 800004 */
-#include <pci/agpreg.h>
-#endif /* __FreeBSD_version >= 800004 */
-#include <dev/pci/pcireg.h>
-#elif defined(__DragonFly__)
 #include <dev/agp/agpreg.h>
 #include <bus/pci/pcireg.h>
-#endif
 
 /* Returns 1 if AGP or 0 if not. */
 static int
-drm_device_find_capability(drm_device_t *dev, int cap)
+drm_device_find_capability(struct drm_device *dev, int cap)
 {
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-#if __FreeBSD_version >= 602102
-
-	return (pci_find_extcap(dev->device, cap, NULL) == 0);
-#else
 	/* Code taken from agp.c.  IWBNI that was a public interface. */
 	u_int32_t status;
 	u_int8_t ptr, next;
@@ -85,22 +70,17 @@ drm_device_find_capability(drm_device_t *dev, int cap)
 	}
 
 	return 0;
-#endif
-#else
-	/* XXX: fill me in for non-FreeBSD */
-	return 1;
-#endif
 }
 
-int drm_device_is_agp(drm_device_t *dev)
+int drm_device_is_agp(struct drm_device *dev)
 {
-	if (dev->driver.device_is_agp != NULL) {
+	if (dev->driver->device_is_agp != NULL) {
 		int ret;
 
 		/* device_is_agp returns a tristate, 0 = not AGP, 1 = definitely
 		 * AGP, 2 = fall back to PCI capability
 		 */
-		ret = (*dev->driver.device_is_agp)(dev);
+		ret = (*dev->driver->device_is_agp)(dev);
 		if (ret != DRM_MIGHT_BE_AGP)
 			return ret;
 	}
@@ -108,12 +88,12 @@ int drm_device_is_agp(drm_device_t *dev)
 	return (drm_device_find_capability(dev, PCIY_AGP));
 }
 
-int drm_device_is_pcie(drm_device_t *dev)
+int drm_device_is_pcie(struct drm_device *dev)
 {
 	return (drm_device_find_capability(dev, PCIY_EXPRESS));
 }
 
-int drm_agp_info(drm_device_t * dev, drm_agp_info_t *info)
+int drm_agp_info(struct drm_device * dev, struct drm_agp_info *info)
 {
 	struct agp_info *kern;
 
@@ -135,26 +115,28 @@ int drm_agp_info(drm_device_t * dev, drm_agp_info_t *info)
 	return 0;
 }
 
-int drm_agp_info_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_agp_info_ioctl(struct drm_device *dev, void *data,
+		       struct drm_file *file_priv)
 {
 	int err;
-	drm_agp_info_t info;
+	struct drm_agp_info info;
 
 	err = drm_agp_info(dev, &info);
 	if (err != 0)
 		return err;
 
-	*(drm_agp_info_t *) data = info;
+	*(struct drm_agp_info *) data = info;
 	return 0;
 }
 
-int drm_agp_acquire_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_agp_acquire_ioctl(struct drm_device *dev, void *data,
+			  struct drm_file *file_priv)
 {
 
 	return drm_agp_acquire(dev);
 }
 
-int drm_agp_acquire(drm_device_t *dev)
+int drm_agp_acquire(struct drm_device *dev)
 {
 	int retcode;
 
@@ -169,13 +151,14 @@ int drm_agp_acquire(drm_device_t *dev)
 	return 0;
 }
 
-int drm_agp_release_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_agp_release_ioctl(struct drm_device *dev, void *data,
+			  struct drm_file *file_priv)
 {
 
 	return drm_agp_release(dev);
 }
 
-int drm_agp_release(drm_device_t * dev)
+int drm_agp_release(struct drm_device * dev)
 {
 	if (!dev->agp || !dev->agp->acquired)
 		return EINVAL;
@@ -184,7 +167,7 @@ int drm_agp_release(drm_device_t * dev)
 	return 0;
 }
 
-int drm_agp_enable(drm_device_t *dev, drm_agp_mode_t mode)
+int drm_agp_enable(struct drm_device *dev, struct drm_agp_mode mode)
 {
 
 	if (!dev->agp || !dev->agp->acquired)
@@ -196,16 +179,17 @@ int drm_agp_enable(drm_device_t *dev, drm_agp_mode_t mode)
 	return 0;
 }
 
-int drm_agp_enable_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_agp_enable_ioctl(struct drm_device *dev, void *data,
+			 struct drm_file *file_priv)
 {
-	drm_agp_mode_t mode;
+	struct drm_agp_mode mode;
 
-	mode = *(drm_agp_mode_t *) data;
+	mode = *(struct drm_agp_mode *) data;
 
 	return drm_agp_enable(dev, mode);
 }
 
-int drm_agp_alloc(drm_device_t *dev, drm_agp_buffer_t *request)
+int drm_agp_alloc(struct drm_device *dev, struct drm_agp_buffer *request)
 {
 	drm_agp_mem_t    *entry;
 	void	         *handle;
@@ -216,7 +200,7 @@ int drm_agp_alloc(drm_device_t *dev, drm_agp_buffer_t *request)
 	if (!dev->agp || !dev->agp->acquired)
 		return EINVAL;
 
-	entry = malloc(sizeof(*entry), M_DRM, M_NOWAIT | M_ZERO);
+	entry = malloc(sizeof(*entry), DRM_MEM_AGPLISTS, M_NOWAIT | M_ZERO);
 	if (entry == NULL)
 		return ENOMEM;
 
@@ -227,7 +211,7 @@ int drm_agp_alloc(drm_device_t *dev, drm_agp_buffer_t *request)
 	handle = drm_agp_allocate_memory(pages, type);
 	DRM_LOCK();
 	if (handle == NULL) {
-		free(entry, M_DRM);
+		free(entry, DRM_MEM_AGPLISTS);
 		return ENOMEM;
 	}
 	
@@ -248,23 +232,25 @@ int drm_agp_alloc(drm_device_t *dev, drm_agp_buffer_t *request)
 	return 0;
 }
 
-int drm_agp_alloc_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_agp_alloc_ioctl(struct drm_device *dev, void *data,
+			struct drm_file *file_priv)
 {
-	drm_agp_buffer_t request;
+	struct drm_agp_buffer request;
 	int retcode;
 
-	request = *(drm_agp_buffer_t *) data;
+	request = *(struct drm_agp_buffer *) data;
 
 	DRM_LOCK();
 	retcode = drm_agp_alloc(dev, &request);
 	DRM_UNLOCK();
 
-	*(drm_agp_buffer_t *) data = request;
+	*(struct drm_agp_buffer *) data = request;
 
 	return retcode;
 }
 
-static drm_agp_mem_t * drm_agp_lookup_entry(drm_device_t *dev, void *handle)
+static drm_agp_mem_t * drm_agp_lookup_entry(struct drm_device *dev,
+					    void *handle)
 {
 	drm_agp_mem_t *entry;
 
@@ -274,7 +260,7 @@ static drm_agp_mem_t * drm_agp_lookup_entry(drm_device_t *dev, void *handle)
 	return NULL;
 }
 
-int drm_agp_unbind(drm_device_t *dev, drm_agp_binding_t *request)
+int drm_agp_unbind(struct drm_device *dev, struct drm_agp_binding *request)
 {
 	drm_agp_mem_t     *entry;
 	int retcode;
@@ -296,12 +282,13 @@ int drm_agp_unbind(drm_device_t *dev, drm_agp_binding_t *request)
 	return retcode;
 }
 
-int drm_agp_unbind_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_agp_unbind_ioctl(struct drm_device *dev, void *data,
+			 struct drm_file *file_priv)
 {
-	drm_agp_binding_t request;
+	struct drm_agp_binding request;
 	int retcode;
 
-	request = *(drm_agp_binding_t *) data;
+	request = *(struct drm_agp_binding *) data;
 
 	DRM_LOCK();
 	retcode = drm_agp_unbind(dev, &request);
@@ -310,7 +297,7 @@ int drm_agp_unbind_ioctl(drm_device_t *dev, void *data, struct drm_file *file_pr
 	return retcode;
 }
 
-int drm_agp_bind(drm_device_t *dev, drm_agp_binding_t *request)
+int drm_agp_bind(struct drm_device *dev, struct drm_agp_binding *request)
 {
 	drm_agp_mem_t     *entry;
 	int               retcode;
@@ -336,12 +323,13 @@ int drm_agp_bind(drm_device_t *dev, drm_agp_binding_t *request)
 	return retcode;
 }
 
-int drm_agp_bind_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_agp_bind_ioctl(struct drm_device *dev, void *data,
+		       struct drm_file *file_priv)
 {
-	drm_agp_binding_t request;
+	struct drm_agp_binding request;
 	int retcode;
 
-	request = *(drm_agp_binding_t *) data;
+	request = *(struct drm_agp_binding *) data;
 
 	DRM_LOCK();
 	retcode = drm_agp_bind(dev, &request);
@@ -350,7 +338,7 @@ int drm_agp_bind_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv
 	return retcode;
 }
 
-int drm_agp_free(drm_device_t *dev, drm_agp_buffer_t *request)
+int drm_agp_free(struct drm_device *dev, struct drm_agp_buffer *request)
 {
 	drm_agp_mem_t    *entry;
 	
@@ -374,18 +362,19 @@ int drm_agp_free(drm_device_t *dev, drm_agp_buffer_t *request)
 	drm_agp_free_memory(entry->handle);
 	DRM_LOCK();
 
-	free(entry, M_DRM);
+	free(entry, DRM_MEM_AGPLISTS);
 
 	return 0;
 
 }
 
-int drm_agp_free_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_agp_free_ioctl(struct drm_device *dev, void *data,
+		       struct drm_file *file_priv)
 {
-	drm_agp_buffer_t request;
+	struct drm_agp_buffer request;
 	int retcode;
 
-	request = *(drm_agp_buffer_t *) data;
+	request = *(struct drm_agp_buffer *) data;
 
 	DRM_LOCK();
 	retcode = drm_agp_free(dev, &request);
@@ -407,7 +396,8 @@ drm_agp_head_t *drm_agp_init(void)
 	DRM_DEBUG("agp_available = %d\n", agp_available);
 
 	if (agp_available) {
-		head = malloc(sizeof(*head), M_DRM, M_NOWAIT | M_ZERO);
+		head = malloc(sizeof(*head), DRM_MEM_AGPLISTS,
+		    M_NOWAIT | M_ZERO);
 		if (head == NULL)
 			return NULL;
 		head->agpdev = agpdev;
diff --git a/sys/dev/drm/drm_atomic.h b/sys/dev/drm/drm_atomic.h
index 0f69dc2bc0..10576d5add 100644
--- a/sys/dev/drm/drm_atomic.h
+++ b/sys/dev/drm/drm_atomic.h
@@ -27,87 +27,18 @@
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/drm_atomic.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /* Many of these implementations are rather fake, but good enough. */
 
 typedef u_int32_t atomic_t;
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 #define atomic_set(p, v)	(*(p) = (v))
 #define atomic_read(p)		(*(p))
 #define atomic_inc(p)		atomic_add_int(p, 1)
 #define atomic_dec(p)		atomic_subtract_int(p, 1)
 #define atomic_add(n, p)	atomic_add_int(p, n)
 #define atomic_sub(n, p)	atomic_subtract_int(p, n)
-#else /* __FreeBSD__ || __DragonFly__ */
-/* FIXME */
-#define atomic_set(p, v)	(*(p) = (v))
-#define atomic_read(p)		(*(p))
-#define atomic_inc(p)		(*(p) += 1)
-#define atomic_dec(p)		(*(p) -= 1)
-#define atomic_add(n, p)	(*(p) += (n))
-#define atomic_sub(n, p)	(*(p) -= (n))
-/* FIXME */
-#define atomic_add_int(p, v)      *(p) += v
-#define atomic_subtract_int(p, v) *(p) -= v
-#define atomic_set_int(p, bits)   *(p) |= (bits)
-#define atomic_clear_int(p, bits) *(p) &= ~(bits)
-#endif /* !__FreeBSD__ && !__DragonFly__ */
-
-#ifndef __DragonFly__
-#if !defined(__FreeBSD_version) || (__FreeBSD_version < 500000)
-#if defined(__i386__)
-/* The extra atomic functions from 5.0 haven't been merged to 4.x */
-static __inline int
-atomic_cmpset_int(volatile u_int *dst, u_int exp, u_int src)
-{
-	int res = exp;
-
-	__asm __volatile (
-	"	lock ;			"
-	"	cmpxchgl %1,%2 ;	"
-	"       setz	%%al ;		"
-	"	movzbl	%%al,%0 ;	"
-	"1:				"
-	"# atomic_cmpset_int"
-	: "+a" (res)			/* 0 (result) */
-	: "r" (src),			/* 1 */
-	  "m" (*(dst))			/* 2 */
-	: "memory");				 
-
-	return (res);
-}
-#else /* __i386__ */
-static __inline int
-atomic_cmpset_int(__volatile__ int *dst, int old, int new)
-{
-	int s = splhigh();
-	if (*dst==old) {
-		*dst = new;
-		splx(s);
-		return 1;
-	}
-	splx(s);
-	return 0;
-}
-#endif /* !__i386__ */
-#endif /* !__FreeBSD_version || __FreeBSD_version < 500000 */
-
-static __inline atomic_t
-test_and_set_bit(int b, volatile void *p)
-{
-	int s = splhigh();
-	unsigned int m = 1<<b;
-	unsigned int r = *(volatile int *)p & m;
-	*(volatile int *)p |= m;
-	splx(s);
-	return r;
-}
-
-#else  /* __DragonFly__ */
 
 static __inline atomic_t
 test_and_set_bit(int b, volatile void *p)
@@ -123,8 +54,6 @@ test_and_set_bit(int b, volatile void *p)
 	return (o & m);
 }
 
-#endif /* __DragonFly__ */
-
 static __inline void
 clear_bit(int b, volatile void *p)
 {
diff --git a/sys/dev/drm/drm_auth.c b/sys/dev/drm/drm_auth.c
index 9d3d7df80f..303722c205 100644
--- a/sys/dev/drm/drm_auth.c
+++ b/sys/dev/drm/drm_auth.c
@@ -26,7 +26,6 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_auth.c,v 1.2 2008/06/10 06:35:59 hasso Exp $
  */
 
 /** @file drm_auth.c
@@ -34,7 +33,7 @@
  * scheme between the master and clients.
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
 static int drm_hash_magic(drm_magic_t magic)
 {
@@ -44,7 +43,7 @@ static int drm_hash_magic(drm_magic_t magic)
 /**
  * Returns the file private associated with the given magic number.
  */
-static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic)
+static struct drm_file *drm_find_file(struct drm_device *dev, drm_magic_t magic)
 {
 	drm_magic_entry_t *pt;
 	int hash = drm_hash_magic(magic);
@@ -64,7 +63,8 @@ static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic)
  * Inserts the given magic number into the hash table of used magic number
  * lists.
  */
-static int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic)
+static int drm_add_magic(struct drm_device *dev, struct drm_file *priv,
+			 drm_magic_t magic)
 {
 	int		  hash;
 	drm_magic_entry_t *entry;
@@ -74,8 +74,9 @@ static int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic)
 	DRM_SPINLOCK_ASSERT(&dev->dev_lock);
 
 	hash = drm_hash_magic(magic);
-	entry = malloc(sizeof(*entry), M_DRM, M_ZERO | M_NOWAIT);
-	if (!entry) return ENOMEM;
+	entry = malloc(sizeof(*entry), DRM_MEM_MAGIC, M_ZERO | M_NOWAIT);
+	if (!entry)
+		return ENOMEM;
 	entry->magic = magic;
 	entry->priv  = priv;
 	entry->next  = NULL;
@@ -95,7 +96,7 @@ static int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic)
  * Removes the given magic number from the hash table of used magic number
  * lists.
  */
-static int drm_remove_magic(drm_device_t *dev, drm_magic_t magic)
+static int drm_remove_magic(struct drm_device *dev, drm_magic_t magic)
 {
 	drm_magic_entry_t *prev = NULL;
 	drm_magic_entry_t *pt;
@@ -117,11 +118,11 @@ static int drm_remove_magic(drm_device_t *dev, drm_magic_t magic)
 			if (prev) {
 				prev->next = pt->next;
 			}
+			free(pt, DRM_MEM_MAGIC);
 			return 0;
 		}
 	}
 
-	free(pt, M_DRM);
 	return EINVAL;
 }
 
@@ -133,12 +134,12 @@ static int drm_remove_magic(drm_device_t *dev, drm_magic_t magic)
  * connection that the magic is passed over) to determine if the magic number
  * should be authenticated.
  */
-int drm_getmagic(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_getmagic(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	static drm_magic_t sequence = 0;
-	drm_auth_t *auth = data;
+	struct drm_auth *auth = data;
 
-				/* Find unique magic */
+	/* Find unique magic */
 	if (file_priv->magic) {
 		auth->magic = file_priv->magic;
 	} else {
@@ -164,10 +165,11 @@ int drm_getmagic(drm_device_t *dev, void *data, struct drm_file *file_priv)
 /**
  * Marks the client associated with the given magic number as authenticated.
  */
-int drm_authmagic(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_authmagic(struct drm_device *dev, void *data,
+		  struct drm_file *file_priv)
 {
-	drm_auth_t *auth = data;
-	drm_file_t *priv;
+	struct drm_auth *auth = data;
+	struct drm_file *priv;
 
 	DRM_DEBUG("%u\n", auth->magic);
 
diff --git a/sys/dev/drm/drm_bufs.c b/sys/dev/drm/drm_bufs.c
index 4912c3f22e..97224831d4 100644
--- a/sys/dev/drm/drm_bufs.c
+++ b/sys/dev/drm/drm_bufs.c
@@ -26,43 +26,21 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_bufs.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_bufs.c
  * Implementation of the ioctls for setup of DRM mappings and DMA buffers.
  */
 
-#ifdef __DragonFly__
-#include <bus/pci/pcireg.h>
-#else
-#include "dev/pci/pcireg.h"
-#endif
-
-#include "drmP.h"
-
-
-/*
- * Compute order.  Can be made faster.
- */
-int drm_order(unsigned long size)
-{
-	int order;
-	unsigned long tmp;
-
-	for ( order = 0, tmp = size ; tmp >>= 1 ; ++order );
+#include "bus/pci/pcireg.h"
 
-	if ( size & ~(1 << order) )
-		++order;
-
-	return order;
-}
+#include "dev/drm/drmP.h"
 
 /* Allocation of PCI memory resources (framebuffer, registers, etc.) for
  * drm_get_resource_*.  Note that they are not RF_ACTIVE, so there's no virtual
  * address for accessing them.  Cleaned up at unload.
  */
-static int drm_alloc_resource(drm_device_t *dev, int resource)
+static int drm_alloc_resource(struct drm_device *dev, int resource)
 {
 	if (resource >= DRM_MAX_PCI_RESOURCE) {
 		DRM_ERROR("Resource %d too large\n", resource);
@@ -88,7 +66,8 @@ static int drm_alloc_resource(drm_device_t *dev, int resource)
 	return 0;
 }
 
-unsigned long drm_get_resource_start(drm_device_t *dev, unsigned int resource)
+unsigned long drm_get_resource_start(struct drm_device *dev,
+				     unsigned int resource)
 {
 	if (drm_alloc_resource(dev, resource) != 0)
 		return 0;
@@ -96,7 +75,8 @@ unsigned long drm_get_resource_start(drm_device_t *dev, unsigned int resource)
 	return rman_get_start(dev->pcir[resource]);
 }
 
-unsigned long drm_get_resource_len(drm_device_t *dev, unsigned int resource)
+unsigned long drm_get_resource_len(struct drm_device *dev,
+				   unsigned int resource)
 {
 	if (drm_alloc_resource(dev, resource) != 0)
 		return 0;
@@ -104,8 +84,9 @@ unsigned long drm_get_resource_len(drm_device_t *dev, unsigned int resource)
 	return rman_get_size(dev->pcir[resource]);
 }
 
-int drm_addmap(drm_device_t * dev, unsigned long offset, unsigned long size,
-    drm_map_type_t type, drm_map_flags_t flags, drm_local_map_t **map_ptr)
+int drm_addmap(struct drm_device * dev, unsigned long offset,
+	       unsigned long size,
+    enum drm_map_type type, enum drm_map_flags flags, drm_local_map_t **map_ptr)
 {
 	drm_local_map_t *map;
 	int align;
@@ -154,16 +135,18 @@ int drm_addmap(drm_device_t * dev, unsigned long offset, unsigned long size,
 	/* Allocate a new map structure, fill it in, and do any type-specific
 	 * initialization necessary.
 	 */
-	map = malloc(sizeof(*map), M_DRM, M_ZERO | M_NOWAIT);
-	if ( !map )
+	map = malloc(sizeof(*map), DRM_MEM_MAPS, M_ZERO | M_NOWAIT);
+	if (!map) {
+		DRM_LOCK();
 		return ENOMEM;
+	}
 
 	map->offset = offset;
 	map->size = size;
 	map->type = type;
 	map->flags = flags;
 
-	switch ( map->type ) {
+	switch (map->type) {
 	case _DRM_REGISTERS:
 		map->handle = drm_ioremap(dev, map);
 		if (!(map->flags & _DRM_WRITE_COMBINING))
@@ -174,21 +157,22 @@ int drm_addmap(drm_device_t * dev, unsigned long offset, unsigned long size,
 			map->mtrr = 1;
 		break;
 	case _DRM_SHM:
-		map->handle = malloc(map->size, M_DRM, M_NOWAIT);
-		DRM_DEBUG( "%lu %d %p\n",
-			   map->size, drm_order(map->size), map->handle );
-		if ( !map->handle ) {
-			free(map, M_DRM);
+		map->handle = malloc(map->size, DRM_MEM_MAPS, M_NOWAIT);
+		DRM_DEBUG("%lu %d %p\n",
+		    map->size, drm_order(map->size), map->handle);
+		if (!map->handle) {
+			free(map, DRM_MEM_MAPS);
+			DRM_LOCK();
 			return ENOMEM;
 		}
 		map->offset = (unsigned long)map->handle;
-		if ( map->flags & _DRM_CONTAINS_LOCK ) {
+		if (map->flags & _DRM_CONTAINS_LOCK) {
 			/* Prevent a 2nd X Server from creating a 2nd lock */
 			DRM_LOCK();
 			if (dev->lock.hw_lock != NULL) {
 				DRM_UNLOCK();
-				free(map->handle, M_DRM);
-				free(map, M_DRM);
+				free(map->handle, DRM_MEM_MAPS);
+				free(map, DRM_MEM_MAPS);
 				return EBUSY;
 			}
 			dev->lock.hw_lock = map->handle; /* Pointer to lock */
@@ -218,16 +202,18 @@ int drm_addmap(drm_device_t * dev, unsigned long offset, unsigned long size,
 			}
 		}
 		if (!valid) {
-			free(map, M_DRM);
+			free(map, DRM_MEM_MAPS);
+			DRM_LOCK();
 			return EACCES;
 		}*/
 		break;
 	case _DRM_SCATTER_GATHER:
 		if (!dev->sg) {
-			free(map, M_DRM);
+			free(map, DRM_MEM_MAPS);
+			DRM_LOCK();
 			return EINVAL;
 		}
-		map->offset = map->offset + dev->sg->handle;
+		map->offset += dev->sg->handle;
 		break;
 	case _DRM_CONSISTENT:
 		/* Unfortunately, we don't get any alignment specification from
@@ -241,7 +227,8 @@ int drm_addmap(drm_device_t * dev, unsigned long offset, unsigned long size,
 			align = PAGE_SIZE;
 		map->dmah = drm_pci_alloc(dev, map->size, align, 0xfffffffful);
 		if (map->dmah == NULL) {
-			free(map, M_DRM);
+			free(map, DRM_MEM_MAPS);
+			DRM_LOCK();
 			return ENOMEM;
 		}
 		map->handle = map->dmah->vaddr;
@@ -249,7 +236,8 @@ int drm_addmap(drm_device_t * dev, unsigned long offset, unsigned long size,
 		break;
 	default:
 		DRM_ERROR("Bad map type %d\n", map->type);
-		free(map, M_DRM);
+		free(map, DRM_MEM_MAPS);
+		DRM_LOCK();
 		return EINVAL;
 	}
 
@@ -267,9 +255,10 @@ done:
 	return 0;
 }
 
-int drm_addmap_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_addmap_ioctl(struct drm_device *dev, void *data,
+		     struct drm_file *file_priv)
 {
-	drm_map_t *request = data;
+	struct drm_map *request = data;
 	drm_local_map_t *map;
 	int err;
 
@@ -300,7 +289,7 @@ int drm_addmap_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return 0;
 }
 
-void drm_rmmap(drm_device_t *dev, drm_local_map_t *map)
+void drm_rmmap(struct drm_device *dev, drm_local_map_t *map)
 {
 	DRM_SPINLOCK_ASSERT(&dev->dev_lock);
 
@@ -321,7 +310,7 @@ void drm_rmmap(drm_device_t *dev, drm_local_map_t *map)
 		}
 		break;
 	case _DRM_SHM:
-		free(map->handle, M_DRM);
+		free(map->handle, DRM_MEM_MAPS);
 		break;
 	case _DRM_AGP:
 	case _DRM_SCATTER_GATHER:
@@ -339,17 +328,18 @@ void drm_rmmap(drm_device_t *dev, drm_local_map_t *map)
 		    map->bsr);
 	}
 
-	free(map, M_DRM);
+	free(map, DRM_MEM_MAPS);
 }
 
 /* Remove a map private from list and deallocate resources if the mapping
  * isn't in use.
  */
 
-int drm_rmmap_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_rmmap_ioctl(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv)
 {
 	drm_local_map_t *map;
-	drm_map_t *request = data;
+	struct drm_map *request = data;
 
 	DRM_LOCK();
 	TAILQ_FOREACH(map, &dev->maplist, link) {
@@ -372,7 +362,8 @@ int drm_rmmap_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
 }
 
 
-static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry)
+static void drm_cleanup_buf_error(struct drm_device *dev,
+				  drm_buf_entry_t *entry)
 {
 	int i;
 
@@ -380,22 +371,22 @@ static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry)
 		for (i = 0; i < entry->seg_count; i++) {
 			drm_pci_free(dev, entry->seglist[i]);
 		}
-		free(entry->seglist, M_DRM);
+		free(entry->seglist, DRM_MEM_SEGS);
 
 		entry->seg_count = 0;
 	}
 
    	if (entry->buf_count) {
 	   	for (i = 0; i < entry->buf_count; i++) {
-			free(entry->buflist[i].dev_private, M_DRM);
+			free(entry->buflist[i].dev_private, DRM_MEM_BUFS);
 		}
-		free(entry->buflist, M_DRM);
+		free(entry->buflist, DRM_MEM_BUFS);
 
 		entry->buf_count = 0;
 	}
 }
 
-static int drm_do_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
+static int drm_do_addbufs_agp(struct drm_device *dev, struct drm_buf_desc *request)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_buf_entry_t *entry;
@@ -419,20 +410,20 @@ static int drm_do_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
 	size = 1 << order;
 
 	alignment  = (request->flags & _DRM_PAGE_ALIGN)
-		? round_page(size) : size;
+	    ? round_page(size) : size;
 	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
 	total = PAGE_SIZE << page_order;
 
 	byte_count = 0;
 	agp_offset = dev->agp->base + request->agp_start;
 
-	DRM_DEBUG( "count:      %d\n",  count );
-	DRM_DEBUG( "order:      %d\n",  order );
-	DRM_DEBUG( "size:       %d\n",  size );
-	DRM_DEBUG( "agp_offset: 0x%lx\n", agp_offset );
-	DRM_DEBUG( "alignment:  %d\n",  alignment );
-	DRM_DEBUG( "page_order: %d\n",  page_order );
-	DRM_DEBUG( "total:      %d\n",  total );
+	DRM_DEBUG("count:      %d\n",  count);
+	DRM_DEBUG("order:      %d\n",  order);
+	DRM_DEBUG("size:       %d\n",  size);
+	DRM_DEBUG("agp_offset: 0x%lx\n", agp_offset);
+	DRM_DEBUG("alignment:  %d\n",  alignment);
+	DRM_DEBUG("page_order: %d\n",  page_order);
+	DRM_DEBUG("total:      %d\n",  total);
 
 	/* Make sure buffers are located in AGP memory that we own */
 	/* Breaks MGA due to drm_alloc_agp not setting up entries for the
@@ -456,9 +447,9 @@ static int drm_do_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
 
 	entry = &dma->bufs[order];
 
-	entry->buflist = malloc(count * sizeof(*entry->buflist), M_DRM,
+	entry->buflist = malloc(count * sizeof(*entry->buflist), DRM_MEM_BUFS,
 	    M_NOWAIT | M_ZERO);
-	if ( !entry->buflist ) {
+	if (!entry->buflist) {
 		return ENOMEM;
 	}
 
@@ -467,7 +458,7 @@ static int drm_do_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
 
 	offset = 0;
 
-	while ( entry->buf_count < count ) {
+	while (entry->buf_count < count) {
 		buf          = &entry->buflist[entry->buf_count];
 		buf->idx     = dma->buf_count + entry->buf_count;
 		buf->total   = alignment;
@@ -481,8 +472,8 @@ static int drm_do_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
 		buf->pending = 0;
 		buf->file_priv = NULL;
 
-		buf->dev_priv_size = dev->driver.buf_priv_size;
-		buf->dev_private = malloc(buf->dev_priv_size, M_DRM,
+		buf->dev_priv_size = dev->driver->buf_priv_size;
+		buf->dev_private = malloc(buf->dev_priv_size, DRM_MEM_BUFS,
 		    M_NOWAIT | M_ZERO);
 		if (buf->dev_private == NULL) {
 			/* Set count correctly so we free the proper amount. */
@@ -496,11 +487,11 @@ static int drm_do_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
 		byte_count += PAGE_SIZE << page_order;
 	}
 
-	DRM_DEBUG( "byte_count: %d\n", byte_count );
+	DRM_DEBUG("byte_count: %d\n", byte_count);
 
 	temp_buflist = realloc(dma->buflist,
-	    (dma->buf_count + entry->buf_count) * sizeof(*dma->buflist), M_DRM,
-	    M_NOWAIT);
+	    (dma->buf_count + entry->buf_count) * sizeof(*dma->buflist),
+	    DRM_MEM_BUFS, M_NOWAIT);
 	if (temp_buflist == NULL) {
 		/* Free the entry because it isn't valid */
 		drm_cleanup_buf_error(dev, entry);
@@ -508,15 +499,15 @@ static int drm_do_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
 	}
 	dma->buflist = temp_buflist;
 
-	for ( i = 0 ; i < entry->buf_count ; i++ ) {
+	for (i = 0; i < entry->buf_count; i++) {
 		dma->buflist[i + dma->buf_count] = &entry->buflist[i];
 	}
 
 	dma->buf_count += entry->buf_count;
 	dma->byte_count += byte_count;
 
-	DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count );
-	DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count );
+	DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count);
+	DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count);
 
 	request->count = entry->buf_count;
 	request->size = size;
@@ -526,7 +517,7 @@ static int drm_do_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
 	return 0;
 }
 
-static int drm_do_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request)
+static int drm_do_addbufs_pci(struct drm_device *dev, struct drm_buf_desc *request)
 {
 	drm_device_dma_t *dma = dev->dma;
 	int count;
@@ -548,68 +539,71 @@ static int drm_do_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request)
 	order = drm_order(request->size);
 	size = 1 << order;
 
-	DRM_DEBUG( "count=%d, size=%d (%d), order=%d\n",
-		   request->count, request->size, size, order );
+	DRM_DEBUG("count=%d, size=%d (%d), order=%d\n",
+	    request->count, request->size, size, order);
 
 	alignment = (request->flags & _DRM_PAGE_ALIGN)
-		? round_page(size) : size;
+	    ? round_page(size) : size;
 	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
 	total = PAGE_SIZE << page_order;
 
 	entry = &dma->bufs[order];
 
-	entry->buflist = malloc(count * sizeof(*entry->buflist), M_DRM,
+	entry->buflist = malloc(count * sizeof(*entry->buflist), DRM_MEM_BUFS,
 	    M_NOWAIT | M_ZERO);
-	entry->seglist = malloc(count * sizeof(*entry->seglist), M_DRM,
+	entry->seglist = malloc(count * sizeof(*entry->seglist), DRM_MEM_SEGS,
 	    M_NOWAIT | M_ZERO);
 
 	/* Keep the original pagelist until we know all the allocations
 	 * have succeeded
 	 */
 	temp_pagelist = malloc((dma->page_count + (count << page_order)) *
-	    sizeof(*dma->pagelist), M_DRM, M_NOWAIT);
+	    sizeof(*dma->pagelist), DRM_MEM_PAGES, M_NOWAIT);
 
 	if (entry->buflist == NULL || entry->seglist == NULL || 
 	    temp_pagelist == NULL) {
-		free(entry->buflist, M_DRM);
-		free(entry->seglist, M_DRM);
+		free(temp_pagelist, DRM_MEM_PAGES);
+		free(entry->seglist, DRM_MEM_SEGS);
+		free(entry->buflist, DRM_MEM_BUFS);
 		return ENOMEM;
 	}
-	
+
 	memcpy(temp_pagelist, dma->pagelist, dma->page_count * 
 	    sizeof(*dma->pagelist));
 
-	DRM_DEBUG( "pagelist: %d entries\n",
-		   dma->page_count + (count << page_order) );
+	DRM_DEBUG("pagelist: %d entries\n",
+	    dma->page_count + (count << page_order));
 
 	entry->buf_size	= size;
 	entry->page_order = page_order;
 	byte_count = 0;
 	page_count = 0;
 
-	while ( entry->buf_count < count ) {
+	while (entry->buf_count < count) {
+		DRM_SPINUNLOCK(&dev->dma_lock);
 		drm_dma_handle_t *dmah = drm_pci_alloc(dev, size, alignment,
 		    0xfffffffful);
+		DRM_SPINLOCK(&dev->dma_lock);
 		if (dmah == NULL) {
 			/* Set count correctly so we free the proper amount. */
 			entry->buf_count = count;
 			entry->seg_count = count;
 			drm_cleanup_buf_error(dev, entry);
-			free(temp_pagelist, M_DRM);
+			free(temp_pagelist, DRM_MEM_PAGES);
 			return ENOMEM;
 		}
 
 		entry->seglist[entry->seg_count++] = dmah;
-		for ( i = 0 ; i < (1 << page_order) ; i++ ) {
-			DRM_DEBUG( "page %d @ %p\n",
-				   dma->page_count + page_count,
-				   (char *)dmah->vaddr + PAGE_SIZE * i );
+		for (i = 0; i < (1 << page_order); i++) {
+			DRM_DEBUG("page %d @ %p\n",
+			    dma->page_count + page_count,
+			    (char *)dmah->vaddr + PAGE_SIZE * i);
 			temp_pagelist[dma->page_count + page_count++] = 
 			    (long)dmah->vaddr + PAGE_SIZE * i;
 		}
-		for ( offset = 0 ;
-		      offset + size <= total && entry->buf_count < count ;
-		      offset += alignment, ++entry->buf_count ) {
+		for (offset = 0;
+		    offset + size <= total && entry->buf_count < count;
+		    offset += alignment, ++entry->buf_count) {
 			buf	     = &entry->buflist[entry->buf_count];
 			buf->idx     = dma->buf_count + entry->buf_count;
 			buf->total   = alignment;
@@ -622,43 +616,43 @@ static int drm_do_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request)
 			buf->pending = 0;
 			buf->file_priv = NULL;
 
-			buf->dev_priv_size = dev->driver.buf_priv_size;
-			buf->dev_private = malloc(buf->dev_priv_size, M_DRM,
-			    M_NOWAIT | M_ZERO);
+			buf->dev_priv_size = dev->driver->buf_priv_size;
+			buf->dev_private = malloc(buf->dev_priv_size,
+			    DRM_MEM_BUFS, M_NOWAIT | M_ZERO);
 			if (buf->dev_private == NULL) {
 				/* Set count correctly so we free the proper amount. */
 				entry->buf_count = count;
 				entry->seg_count = count;
 				drm_cleanup_buf_error(dev, entry);
-				free(temp_pagelist, M_DRM);
+				free(temp_pagelist, DRM_MEM_PAGES);
 				return ENOMEM;
 			}
 
-			DRM_DEBUG( "buffer %d @ %p\n",
-				   entry->buf_count, buf->address );
+			DRM_DEBUG("buffer %d @ %p\n",
+			    entry->buf_count, buf->address);
 		}
 		byte_count += PAGE_SIZE << page_order;
 	}
 
 	temp_buflist = realloc(dma->buflist,
-	    (dma->buf_count + entry->buf_count) * sizeof(*dma->buflist), M_DRM,
-	    M_NOWAIT);
+	    (dma->buf_count + entry->buf_count) * sizeof(*dma->buflist),
+	    DRM_MEM_BUFS, M_NOWAIT);
 	if (temp_buflist == NULL) {
 		/* Free the entry because it isn't valid */
 		drm_cleanup_buf_error(dev, entry);
-		free(temp_pagelist, M_DRM);
+		free(temp_pagelist, DRM_MEM_PAGES);
 		return ENOMEM;
 	}
 	dma->buflist = temp_buflist;
 
-	for ( i = 0 ; i < entry->buf_count ; i++ ) {
+	for (i = 0; i < entry->buf_count; i++) {
 		dma->buflist[i + dma->buf_count] = &entry->buflist[i];
 	}
 
 	/* No allocations failed, so now we can replace the orginal pagelist
 	 * with the new one.
 	 */
-	free(dma->pagelist, M_DRM);
+	free(dma->pagelist, DRM_MEM_PAGES);
 	dma->pagelist = temp_pagelist;
 
 	dma->buf_count += entry->buf_count;
@@ -673,7 +667,7 @@ static int drm_do_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request)
 
 }
 
-static int drm_do_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
+static int drm_do_addbufs_sg(struct drm_device *dev, struct drm_buf_desc *request)
 {
 	drm_device_dma_t *dma = dev->dma;
 	drm_buf_entry_t *entry;
@@ -695,24 +689,24 @@ static int drm_do_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
 	size = 1 << order;
 
 	alignment  = (request->flags & _DRM_PAGE_ALIGN)
-		? round_page(size) : size;
+	    ? round_page(size) : size;
 	page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0;
 	total = PAGE_SIZE << page_order;
 
 	byte_count = 0;
 	agp_offset = request->agp_start;
 
-	DRM_DEBUG( "count:      %d\n",  count );
-	DRM_DEBUG( "order:      %d\n",  order );
-	DRM_DEBUG( "size:       %d\n",  size );
-	DRM_DEBUG( "agp_offset: %ld\n", agp_offset );
-	DRM_DEBUG( "alignment:  %d\n",  alignment );
-	DRM_DEBUG( "page_order: %d\n",  page_order );
-	DRM_DEBUG( "total:      %d\n",  total );
+	DRM_DEBUG("count:      %d\n",  count);
+	DRM_DEBUG("order:      %d\n",  order);
+	DRM_DEBUG("size:       %d\n",  size);
+	DRM_DEBUG("agp_offset: %ld\n", agp_offset);
+	DRM_DEBUG("alignment:  %d\n",  alignment);
+	DRM_DEBUG("page_order: %d\n",  page_order);
+	DRM_DEBUG("total:      %d\n",  total);
 
 	entry = &dma->bufs[order];
 
-	entry->buflist = malloc(count * sizeof(*entry->buflist), M_DRM,
+	entry->buflist = malloc(count * sizeof(*entry->buflist), DRM_MEM_BUFS,
 	    M_NOWAIT | M_ZERO);
 	if (entry->buflist == NULL)
 		return ENOMEM;
@@ -722,7 +716,7 @@ static int drm_do_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
 
 	offset = 0;
 
-	while ( entry->buf_count < count ) {
+	while (entry->buf_count < count) {
 		buf          = &entry->buflist[entry->buf_count];
 		buf->idx     = dma->buf_count + entry->buf_count;
 		buf->total   = alignment;
@@ -736,8 +730,8 @@ static int drm_do_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
 		buf->pending = 0;
 		buf->file_priv = NULL;
 
-		buf->dev_priv_size = dev->driver.buf_priv_size;
-		buf->dev_private = malloc(buf->dev_priv_size, M_DRM,
+		buf->dev_priv_size = dev->driver->buf_priv_size;
+		buf->dev_private = malloc(buf->dev_priv_size, DRM_MEM_BUFS,
 		    M_NOWAIT | M_ZERO);
 		if (buf->dev_private == NULL) {
 			/* Set count correctly so we free the proper amount. */
@@ -746,19 +740,19 @@ static int drm_do_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
 			return ENOMEM;
 		}
 
-		DRM_DEBUG( "buffer %d @ %p\n",
-			   entry->buf_count, buf->address );
+		DRM_DEBUG("buffer %d @ %p\n",
+		    entry->buf_count, buf->address);
 
 		offset += alignment;
 		entry->buf_count++;
 		byte_count += PAGE_SIZE << page_order;
 	}
 
-	DRM_DEBUG( "byte_count: %d\n", byte_count );
+	DRM_DEBUG("byte_count: %d\n", byte_count);
 
 	temp_buflist = realloc(dma->buflist,
-	    (dma->buf_count + entry->buf_count) * sizeof(*dma->buflist), M_DRM,
-	    M_NOWAIT);
+	    (dma->buf_count + entry->buf_count) * sizeof(*dma->buflist),
+	    DRM_MEM_BUFS, M_NOWAIT);
 	if (temp_buflist == NULL) {
 		/* Free the entry because it isn't valid */
 		drm_cleanup_buf_error(dev, entry);
@@ -766,15 +760,15 @@ static int drm_do_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
 	}
 	dma->buflist = temp_buflist;
 
-	for ( i = 0 ; i < entry->buf_count ; i++ ) {
+	for (i = 0; i < entry->buf_count; i++) {
 		dma->buflist[i + dma->buf_count] = &entry->buflist[i];
 	}
 
 	dma->buf_count += entry->buf_count;
 	dma->byte_count += byte_count;
 
-	DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count );
-	DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count );
+	DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count);
+	DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count);
 
 	request->count = entry->buf_count;
 	request->size = size;
@@ -784,12 +778,10 @@ static int drm_do_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
 	return 0;
 }
 
-int drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
+int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc *request)
 {
 	int order, ret;
 
-	DRM_SPINLOCK(&dev->dma_lock);
-
 	if (request->count < 0 || request->count > 4096)
 		return EINVAL;
 	
@@ -797,6 +789,8 @@ int drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
 	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER)
 		return EINVAL;
 
+	DRM_SPINLOCK(&dev->dma_lock);
+
 	/* No more allocations after first buffer-using ioctl. */
 	if (dev->buf_use != 0) {
 		DRM_SPINUNLOCK(&dev->dma_lock);
@@ -815,22 +809,22 @@ int drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request)
 	return ret;
 }
 
-int drm_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
+int drm_addbufs_sg(struct drm_device *dev, struct drm_buf_desc *request)
 {
 	int order, ret;
 
-	DRM_SPINLOCK(&dev->dma_lock);
-
 	if (!DRM_SUSER(DRM_CURPROC))
 		return EACCES;
 
 	if (request->count < 0 || request->count > 4096)
 		return EINVAL;
-	
+
 	order = drm_order(request->size);
 	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER)
 		return EINVAL;
 
+	DRM_SPINLOCK(&dev->dma_lock);
+
 	/* No more allocations after first buffer-using ioctl. */
 	if (dev->buf_use != 0) {
 		DRM_SPINUNLOCK(&dev->dma_lock);
@@ -849,22 +843,22 @@ int drm_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request)
 	return ret;
 }
 
-int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request)
+int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc *request)
 {
 	int order, ret;
 
-	DRM_SPINLOCK(&dev->dma_lock);
-
 	if (!DRM_SUSER(DRM_CURPROC))
 		return EACCES;
 
 	if (request->count < 0 || request->count > 4096)
 		return EINVAL;
-	
+
 	order = drm_order(request->size);
 	if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER)
 		return EINVAL;
 
+	DRM_SPINLOCK(&dev->dma_lock);
+
 	/* No more allocations after first buffer-using ioctl. */
 	if (dev->buf_use != 0) {
 		DRM_SPINUNLOCK(&dev->dma_lock);
@@ -883,9 +877,9 @@ int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request)
 	return ret;
 }
 
-int drm_addbufs_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_addbufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_buf_desc_t *request = data;
+	struct drm_buf_desc *request = data;
 	int err;
 
 	if (request->flags & _DRM_AGP_BUFFER)
@@ -898,10 +892,10 @@ int drm_addbufs_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return err;
 }
 
-int drm_infobufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_infobufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_device_dma_t *dma = dev->dma;
-	drm_buf_info_t *request = data;
+	struct drm_buf_info *request = data;
 	int i;
 	int count;
 	int retcode = 0;
@@ -910,16 +904,17 @@ int drm_infobufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	++dev->buf_use;		/* Can't allocate more after this call */
 	DRM_SPINUNLOCK(&dev->dma_lock);
 
-	for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) {
-		if ( dma->bufs[i].buf_count ) ++count;
+	for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) {
+		if (dma->bufs[i].buf_count)
+			++count;
 	}
 
-	DRM_DEBUG( "count = %d\n", count );
+	DRM_DEBUG("count = %d\n", count);
 
-	if ( request->count >= count ) {
-		for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) {
-			if ( dma->bufs[i].buf_count ) {
-				drm_buf_desc_t from;
+	if (request->count >= count) {
+		for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) {
+			if (dma->bufs[i].buf_count) {
+				struct drm_buf_desc from;
 
 				from.count = dma->bufs[i].buf_count;
 				from.size = dma->bufs[i].buf_size;
@@ -927,17 +922,16 @@ int drm_infobufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
 				from.high_mark = dma->bufs[i].freelist.high_mark;
 
 				if (DRM_COPY_TO_USER(&request->list[count], &from,
-				    sizeof(drm_buf_desc_t)) != 0) {
+				    sizeof(struct drm_buf_desc)) != 0) {
 					retcode = EFAULT;
 					break;
 				}
 
-				DRM_DEBUG( "%d %d %d %d %d\n",
-					   i,
-					   dma->bufs[i].buf_count,
-					   dma->bufs[i].buf_size,
-					   dma->bufs[i].freelist.low_mark,
-					   dma->bufs[i].freelist.high_mark );
+				DRM_DEBUG("%d %d %d %d %d\n",
+				    i, dma->bufs[i].buf_count,
+				    dma->bufs[i].buf_size,
+				    dma->bufs[i].freelist.low_mark,
+				    dma->bufs[i].freelist.high_mark);
 				++count;
 			}
 		}
@@ -947,14 +941,14 @@ int drm_infobufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return retcode;
 }
 
-int drm_markbufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_markbufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_device_dma_t *dma = dev->dma;
-	drm_buf_desc_t *request = data;
+	struct drm_buf_desc *request = data;
 	int order;
 
-	DRM_DEBUG( "%d, %d, %d\n",
-		   request->size, request->low_mark, request->high_mark );
+	DRM_DEBUG("%d, %d, %d\n",
+		  request->size, request->low_mark, request->high_mark);
 	
 
 	order = drm_order(request->size);	
@@ -966,6 +960,7 @@ int drm_markbufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	DRM_SPINLOCK(&dev->dma_lock);
 	if (request->low_mark > dma->bufs[order].buf_count ||
 	    request->high_mark > dma->bufs[order].buf_count) {
+		DRM_SPINUNLOCK(&dev->dma_lock);
 		return EINVAL;
 	}
 
@@ -976,33 +971,33 @@ int drm_markbufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return 0;
 }
 
-int drm_freebufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_freebufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_device_dma_t *dma = dev->dma;
-	drm_buf_free_t *request = data;
+	struct drm_buf_free *request = data;
 	int i;
 	int idx;
 	drm_buf_t *buf;
 	int retcode = 0;
 
-	DRM_DEBUG( "%d\n", request->count );
+	DRM_DEBUG("%d\n", request->count);
 	
 	DRM_SPINLOCK(&dev->dma_lock);
-	for ( i = 0 ; i < request->count ; i++ ) {
+	for (i = 0; i < request->count; i++) {
 		if (DRM_COPY_FROM_USER(&idx, &request->list[i], sizeof(idx))) {
 			retcode = EFAULT;
 			break;
 		}
-		if ( idx < 0 || idx >= dma->buf_count ) {
-			DRM_ERROR( "Index %d (of %d max)\n",
-				   idx, dma->buf_count - 1 );
+		if (idx < 0 || idx >= dma->buf_count) {
+			DRM_ERROR("Index %d (of %d max)\n",
+			    idx, dma->buf_count - 1);
 			retcode = EINVAL;
 			break;
 		}
 		buf = dma->buflist[idx];
-		if ( buf->file_priv != file_priv ) {
+		if (buf->file_priv != file_priv) {
 			DRM_ERROR("Process %d freeing buffer not owned\n",
-				   DRM_CURRENTPID);
+			    DRM_CURRENTPID);
 			retcode = EINVAL;
 			break;
 		}
@@ -1013,37 +1008,20 @@ int drm_freebufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return retcode;
 }
 
-int drm_mapbufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_mapbufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	drm_device_dma_t *dma = dev->dma;
 	int retcode = 0;
 	const int zero = 0;
 	vm_offset_t address;
 	struct vmspace *vms;
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	vm_ooffset_t foff;
 	vm_size_t size;
 	vm_offset_t vaddr;
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	struct vnode *vn;
-	voff_t foff;
-	vsize_t size;
-	vaddr_t vaddr;
-#endif /* __NetBSD__ || __OpenBSD__ */
-
-	drm_buf_map_t *request = data;
+	struct drm_buf_map *request = data;
 	int i;
 
-#if defined(__NetBSD__) || defined(__OpenBSD__)
-	if (!vfinddev(kdev, VCHR, &vn))
-		return 0;	/* FIXME: Shouldn't this be EINVAL or something? */
-#endif /* __NetBSD__ || __OpenBSD */
-
-#if defined(__FreeBSD__) && __FreeBSD_version >= 500000 || defined(__DragonFly__)
 	vms = DRM_CURPROC->td_proc->p_vmspace;
-#else
-	vms = DRM_CURPROC->p_vmspace;
-#endif
 
 	DRM_SPINLOCK(&dev->dma_lock);
 	dev->buf_use++;		/* Can't allocate more after this call */
@@ -1052,8 +1030,9 @@ int drm_mapbufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	if (request->count < dma->buf_count)
 		goto done;
 
-	if ((dev->driver.use_agp && (dma->flags & _DRM_DMA_USE_AGP)) ||
-	    (dev->driver.use_sg && (dma->flags & _DRM_DMA_USE_SG))) {
+	if ((drm_core_has_AGP(dev) && (dma->flags & _DRM_DMA_USE_AGP)) ||
+	    (drm_core_check_feature(dev, DRIVER_SG) &&
+	    (dma->flags & _DRM_DMA_USE_SG))) {
 		drm_local_map_t *map = dev->agp_buffer_map;
 
 		if (map == NULL) {
@@ -1067,28 +1046,22 @@ int drm_mapbufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
 		foff = 0;
 	}
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	vaddr = round_page((vm_offset_t)vms->vm_daddr + MAXDSIZ);
 #if __FreeBSD_version >= 600023
 	retcode = vm_mmap(&vms->vm_map, &vaddr, size, PROT_READ | PROT_WRITE,
-	    VM_PROT_ALL, MAP_SHARED, OBJT_DEVICE, dev->devnode, foff);
+	    VM_PROT_ALL, MAP_SHARED | MAP_NOSYNC, OBJT_DEVICE,
+	    dev->devnode, foff);
 #else
 	retcode = vm_mmap(&vms->vm_map, &vaddr, size, PROT_READ | PROT_WRITE,
-	    VM_PROT_ALL, MAP_SHARED, SLIST_FIRST(&dev->devnode->si_hlist),
-	    foff);
+	    VM_PROT_ALL, MAP_SHARED | MAP_NOSYNC,
+	    SLIST_FIRST(&dev->devnode->si_hlist), foff);
 #endif
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	vaddr = round_page((vaddr_t)vms->vm_daddr + MAXDSIZ);
-	retcode = uvm_mmap(&vms->vm_map, &vaddr, size,
-	    UVM_PROT_READ | UVM_PROT_WRITE, UVM_PROT_ALL, MAP_SHARED,
-	    &vn->v_uobj, foff, p->p_rlimit[RLIMIT_MEMLOCK].rlim_cur);
-#endif /* __NetBSD__ || __OpenBSD */
 	if (retcode)
 		goto done;
 
 	request->virtual = (void *)vaddr;
 
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
+	for (i = 0; i < dma->buf_count; i++) {
 		if (DRM_COPY_TO_USER(&request->list[i].idx,
 		    &dma->buflist[i]->idx, sizeof(request->list[0].idx))) {
 			retcode = EFAULT;
@@ -1115,7 +1088,24 @@ int drm_mapbufs(drm_device_t *dev, void *data, struct drm_file *file_priv)
  done:
 	request->count = dma->buf_count;
 
-	DRM_DEBUG( "%d buffers, retcode = %d\n", request->count, retcode );
+	DRM_DEBUG("%d buffers, retcode = %d\n", request->count, retcode);
 
 	return retcode;
 }
+
+/*
+ * Compute order.  Can be made faster.
+ */
+int drm_order(unsigned long size)
+{
+	int order;
+
+	if (size == 0)
+		return 0;
+
+	order = flsl(size) - 1;
+	if (size & ~(1ul << order))
+		++order;
+
+	return order;
+}
diff --git a/sys/dev/drm/drm_context.c b/sys/dev/drm/drm_context.c
index 2319bc7371..ecc468d53a 100644
--- a/sys/dev/drm/drm_context.c
+++ b/sys/dev/drm/drm_context.c
@@ -26,20 +26,19 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_context.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_context.c
  * Implementation of the context management ioctls.
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
 /* ================================================================
  * Context bitmap support
  */
 
-void drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle)
+void drm_ctxbitmap_free(struct drm_device *dev, int ctx_handle)
 {
 	if (ctx_handle < 0 || ctx_handle >= DRM_MAX_CTXBITMAP || 
 	    dev->ctx_bitmap == NULL) {
@@ -55,7 +54,7 @@ void drm_ctxbitmap_free(drm_device_t *dev, int ctx_handle)
 	return;
 }
 
-int drm_ctxbitmap_next(drm_device_t *dev)
+int drm_ctxbitmap_next(struct drm_device *dev)
 {
 	int bit;
 
@@ -63,7 +62,7 @@ int drm_ctxbitmap_next(drm_device_t *dev)
 		return -1;
 
 	DRM_LOCK();
-	bit = find_first_zero_bit( dev->ctx_bitmap, DRM_MAX_CTXBITMAP );
+	bit = find_first_zero_bit(dev->ctx_bitmap, DRM_MAX_CTXBITMAP);
 	if (bit >= DRM_MAX_CTXBITMAP) {
 		DRM_UNLOCK();
 		return -1;
@@ -78,7 +77,7 @@ int drm_ctxbitmap_next(drm_device_t *dev)
 
 			ctx_sareas = realloc(dev->context_sareas,
 			    dev->max_context * sizeof(*dev->context_sareas),
-			    M_DRM, M_NOWAIT);
+			    DRM_MEM_SAREA, M_NOWAIT);
 			if (ctx_sareas == NULL) {
 				clear_bit(bit, dev->ctx_bitmap);
 				DRM_UNLOCK();
@@ -89,7 +88,8 @@ int drm_ctxbitmap_next(drm_device_t *dev)
 		} else {
 			/* max_context == 1 at this point */
 			dev->context_sareas = malloc(dev->max_context * 
-			    sizeof(*dev->context_sareas), M_DRM, M_NOWAIT);
+			    sizeof(*dev->context_sareas), DRM_MEM_SAREA,
+			    M_NOWAIT);
 			if (dev->context_sareas == NULL) {
 				clear_bit(bit, dev->ctx_bitmap);
 				DRM_UNLOCK();
@@ -102,14 +102,15 @@ int drm_ctxbitmap_next(drm_device_t *dev)
 	return bit;
 }
 
-int drm_ctxbitmap_init(drm_device_t *dev)
+int drm_ctxbitmap_init(struct drm_device *dev)
 {
 	int i;
    	int temp;
 
 	DRM_LOCK();
-	dev->ctx_bitmap = malloc(PAGE_SIZE, M_DRM, M_NOWAIT | M_ZERO);
-	if ( dev->ctx_bitmap == NULL ) {
+	dev->ctx_bitmap = malloc(PAGE_SIZE, DRM_MEM_CTXBITMAP,
+	    M_NOWAIT | M_ZERO);
+	if (dev->ctx_bitmap == NULL) {
 		DRM_UNLOCK();
 		return ENOMEM;
 	}
@@ -117,20 +118,20 @@ int drm_ctxbitmap_init(drm_device_t *dev)
 	dev->max_context = -1;
 	DRM_UNLOCK();
 
-	for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) {
+	for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
 		temp = drm_ctxbitmap_next(dev);
-	   	DRM_DEBUG( "drm_ctxbitmap_init : %d\n", temp );
+		DRM_DEBUG("drm_ctxbitmap_init : %d\n", temp);
 	}
 
 	return 0;
 }
 
-void drm_ctxbitmap_cleanup(drm_device_t *dev)
+void drm_ctxbitmap_cleanup(struct drm_device *dev)
 {
 	DRM_LOCK();
 	if (dev->context_sareas != NULL)
-		free(dev->context_sareas, M_DRM);
-	free(dev->ctx_bitmap, M_DRM);
+		free(dev->context_sareas, DRM_MEM_SAREA);
+	free(dev->ctx_bitmap, DRM_MEM_CTXBITMAP);
 	DRM_UNLOCK();
 }
 
@@ -138,9 +139,10 @@ void drm_ctxbitmap_cleanup(drm_device_t *dev)
  * Per Context SAREA Support
  */
 
-int drm_getsareactx( drm_device_t *dev, void *data, struct drm_file *file_priv )
+int drm_getsareactx(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv)
 {
-	drm_ctx_priv_map_t *request = data;
+	struct drm_ctx_priv_map *request = data;
 	drm_local_map_t *map;
 
 	DRM_LOCK();
@@ -158,9 +160,10 @@ int drm_getsareactx( drm_device_t *dev, void *data, struct drm_file *file_priv )
 	return 0;
 }
 
-int drm_setsareactx(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_setsareactx(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv)
 {
-	drm_ctx_priv_map_t *request = data;
+	struct drm_ctx_priv_map *request = data;
 	drm_local_map_t *map = NULL;
 
 	DRM_LOCK();
@@ -185,51 +188,51 @@ bad:
  * The actual DRM context handling routines
  */
 
-int drm_context_switch(drm_device_t *dev, int old, int new)
+int drm_context_switch(struct drm_device *dev, int old, int new)
 {
-        if ( test_and_set_bit( 0, &dev->context_flag ) ) {
-                DRM_ERROR( "Reentering -- FIXME\n" );
-                return EBUSY;
-        }
+	if (test_and_set_bit(0, &dev->context_flag)) {
+		DRM_ERROR("Reentering -- FIXME\n");
+		return EBUSY;
+	}
 
-        DRM_DEBUG( "Context switch from %d to %d\n", old, new );
+	DRM_DEBUG("Context switch from %d to %d\n", old, new);
 
-        if ( new == dev->last_context ) {
-                clear_bit( 0, &dev->context_flag );
-                return 0;
-        }
+	if (new == dev->last_context) {
+		clear_bit(0, &dev->context_flag);
+		return 0;
+	}
 
-        return 0;
+	return 0;
 }
 
-int drm_context_switch_complete(drm_device_t *dev, int new)
+int drm_context_switch_complete(struct drm_device *dev, int new)
 {
-        dev->last_context = new;  /* PRE/POST: This is the _only_ writer. */
+	dev->last_context = new;  /* PRE/POST: This is the _only_ writer. */
 
-        if ( !_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) ) {
-                DRM_ERROR( "Lock isn't held after context switch\n" );
-        }
+	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
+		DRM_ERROR("Lock isn't held after context switch\n");
+	}
 
-				/* If a context switch is ever initiated
-                                   when the kernel holds the lock, release
-                                   that lock here. */
-        clear_bit( 0, &dev->context_flag );
+	/* If a context switch is ever initiated
+	   when the kernel holds the lock, release
+	   that lock here. */
+	clear_bit(0, &dev->context_flag);
 
-        return 0;
+	return 0;
 }
 
-int drm_resctx(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_resctx(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_ctx_res_t *res = data;
-	drm_ctx_t ctx;
+	struct drm_ctx_res *res = data;
+	struct drm_ctx ctx;
 	int i;
 
-	if ( res->count >= DRM_RESERVED_CONTEXTS ) {
+	if (res->count >= DRM_RESERVED_CONTEXTS) {
 		bzero(&ctx, sizeof(ctx));
-		for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) {
+		for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) {
 			ctx.handle = i;
-			if ( DRM_COPY_TO_USER( &res->contexts[i],
-					   &ctx, sizeof(ctx) ) )
+			if (DRM_COPY_TO_USER(&res->contexts[i],
+			    &ctx, sizeof(ctx)))
 				return EFAULT;
 		}
 	}
@@ -238,40 +241,40 @@ int drm_resctx(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return 0;
 }
 
-int drm_addctx(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_addctx(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_ctx_t *ctx = data;
+	struct drm_ctx *ctx = data;
 
 	ctx->handle = drm_ctxbitmap_next(dev);
-	if ( ctx->handle == DRM_KERNEL_CONTEXT ) {
-				/* Skip kernel's context and get a new one. */
+	if (ctx->handle == DRM_KERNEL_CONTEXT) {
+		/* Skip kernel's context and get a new one. */
 		ctx->handle = drm_ctxbitmap_next(dev);
 	}
-	DRM_DEBUG( "%d\n", ctx->handle );
-	if ( ctx->handle == -1 ) {
-		DRM_DEBUG( "Not enough free contexts.\n" );
-				/* Should this return -EBUSY instead? */
+	DRM_DEBUG("%d\n", ctx->handle);
+	if (ctx->handle == -1) {
+		DRM_DEBUG("Not enough free contexts.\n");
+		/* Should this return -EBUSY instead? */
 		return ENOMEM;
 	}
 
-	if (dev->driver.context_ctor && ctx->handle != DRM_KERNEL_CONTEXT) {
+	if (dev->driver->context_ctor && ctx->handle != DRM_KERNEL_CONTEXT) {
 		DRM_LOCK();
-		dev->driver.context_ctor(dev, ctx->handle);
+		dev->driver->context_ctor(dev, ctx->handle);
 		DRM_UNLOCK();
 	}
 
 	return 0;
 }
 
-int drm_modctx(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_modctx(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	/* This does nothing */
 	return 0;
 }
 
-int drm_getctx(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_getctx(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_ctx_t *ctx = data;
+	struct drm_ctx *ctx = data;
 
 	/* This is 0, because we don't handle any context flags */
 	ctx->flags = 0;
@@ -279,33 +282,34 @@ int drm_getctx(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return 0;
 }
 
-int drm_switchctx(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_switchctx(struct drm_device *dev, void *data,
+		  struct drm_file *file_priv)
 {
-	drm_ctx_t *ctx = data;
+	struct drm_ctx *ctx = data;
 
-	DRM_DEBUG( "%d\n", ctx->handle );
+	DRM_DEBUG("%d\n", ctx->handle);
 	return drm_context_switch(dev, dev->last_context, ctx->handle);
 }
 
-int drm_newctx(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_newctx(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_ctx_t *ctx = data;
+	struct drm_ctx *ctx = data;
 
-	DRM_DEBUG( "%d\n", ctx->handle );
+	DRM_DEBUG("%d\n", ctx->handle);
 	drm_context_switch_complete(dev, ctx->handle);
 
 	return 0;
 }
 
-int drm_rmctx(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_rmctx(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_ctx_t *ctx = data;
+	struct drm_ctx *ctx = data;
 
-	DRM_DEBUG( "%d\n", ctx->handle );
-	if ( ctx->handle != DRM_KERNEL_CONTEXT ) {
-		if (dev->driver.context_dtor) {
+	DRM_DEBUG("%d\n", ctx->handle);
+	if (ctx->handle != DRM_KERNEL_CONTEXT) {
+		if (dev->driver->context_dtor) {
 			DRM_LOCK();
-			dev->driver.context_dtor(dev, ctx->handle);
+			dev->driver->context_dtor(dev, ctx->handle);
 			DRM_UNLOCK();
 		}
 
diff --git a/sys/dev/drm/drm_dma.c b/sys/dev/drm/drm_dma.c
index 82dff2faae..0cc5f7276f 100644
--- a/sys/dev/drm/drm_dma.c
+++ b/sys/dev/drm/drm_dma.c
@@ -26,7 +26,6 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_dma.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_dma.c
@@ -37,12 +36,12 @@
  * schemes evolved.
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
-int drm_dma_setup(drm_device_t *dev)
+int drm_dma_setup(struct drm_device *dev)
 {
 
-	dev->dma = malloc(sizeof(*dev->dma), M_DRM, M_NOWAIT | M_ZERO);
+	dev->dma = malloc(sizeof(*dev->dma), DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
 	if (dev->dma == NULL)
 		return ENOMEM;
 
@@ -51,7 +50,7 @@ int drm_dma_setup(drm_device_t *dev)
 	return 0;
 }
 
-void drm_dma_takedown(drm_device_t *dev)
+void drm_dma_takedown(struct drm_device *dev)
 {
 	drm_device_dma_t  *dma = dev->dma;
 	int		  i, j;
@@ -59,52 +58,53 @@ void drm_dma_takedown(drm_device_t *dev)
 	if (dma == NULL)
 		return;
 
-				/* Clear dma buffers */
+	/* Clear dma buffers */
 	for (i = 0; i <= DRM_MAX_ORDER; i++) {
 		if (dma->bufs[i].seg_count) {
 			DRM_DEBUG("order %d: buf_count = %d,"
-				  " seg_count = %d\n",
-				  i,
-				  dma->bufs[i].buf_count,
-				  dma->bufs[i].seg_count);
+			    " seg_count = %d\n", i, dma->bufs[i].buf_count,
+			    dma->bufs[i].seg_count);
 			for (j = 0; j < dma->bufs[i].seg_count; j++) {
 				drm_pci_free(dev, dma->bufs[i].seglist[j]);
 			}
-			free(dma->bufs[i].seglist, M_DRM);
+			free(dma->bufs[i].seglist, DRM_MEM_SEGS);
 		}
 
 	   	if (dma->bufs[i].buf_count) {
 		   	for (j = 0; j < dma->bufs[i].buf_count; j++) {
 				free(dma->bufs[i].buflist[j].dev_private,
-				    M_DRM);
+				    DRM_MEM_BUFS);
 			}
-		   	free(dma->bufs[i].buflist, M_DRM);
+		   	free(dma->bufs[i].buflist, DRM_MEM_BUFS);
 		}
 	}
 
-	free(dma->buflist, M_DRM);
-	free(dma->pagelist, M_DRM);
-	free(dev->dma, M_DRM);
+	free(dma->buflist, DRM_MEM_BUFS);
+	free(dma->pagelist, DRM_MEM_PAGES);
+	free(dev->dma, DRM_MEM_DRIVER);
 	dev->dma = NULL;
 	DRM_SPINUNINIT(&dev->dma_lock);
 }
 
 
-void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf)
+void drm_free_buffer(struct drm_device *dev, drm_buf_t *buf)
 {
-	if (!buf) return;
+	if (!buf)
+		return;
 
 	buf->pending  = 0;
 	buf->file_priv= NULL;
 	buf->used     = 0;
 }
 
-void drm_reclaim_buffers(drm_device_t *dev, struct drm_file *file_priv)
+void drm_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv)
 {
 	drm_device_dma_t *dma = dev->dma;
 	int		 i;
 
-	if (!dma) return;
+	if (!dma)
+		return;
+
 	for (i = 0; i < dma->buf_count; i++) {
 		if (dma->buflist[i]->file_priv == file_priv) {
 			switch (dma->buflist[i]->list) {
@@ -123,12 +123,12 @@ void drm_reclaim_buffers(drm_device_t *dev, struct drm_file *file_priv)
 }
 
 /* Call into the driver-specific DMA handler */
-int drm_dma(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_dma(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 
-	if (dev->driver.dma_ioctl) {
+	if (dev->driver->dma_ioctl) {
 		/* shared code returns -errno */
-		return -dev->driver.dma_ioctl(dev, data, file_priv);
+		return -dev->driver->dma_ioctl(dev, data, file_priv);
 	} else {
 		DRM_DEBUG("DMA ioctl on driver with no dma handler\n");
 		return EINVAL;
diff --git a/sys/dev/drm/drm_drawable.c b/sys/dev/drm/drm_drawable.c
index c525a67ea3..3ad40ea065 100644
--- a/sys/dev/drm/drm_drawable.c
+++ b/sys/dev/drm/drm_drawable.c
@@ -26,7 +26,6 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_drawable.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_drawable.c
@@ -34,7 +33,7 @@
  * such as the current set of cliprects for vblank-synced buffer swaps.
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
 struct bsd_drm_drawable_info {
 	struct drm_drawable_info info;
@@ -52,13 +51,14 @@ drm_drawable_compare(struct bsd_drm_drawable_info *a,
 		return -1;
 	return 0;
 }
+
 RB_PROTOTYPE_STATIC(drawable_tree, bsd_drm_drawable_info, tree,
     drm_drawable_compare);
 RB_GENERATE_STATIC(drawable_tree, bsd_drm_drawable_info, tree,
     drm_drawable_compare);
 
 struct drm_drawable_info *
-drm_get_drawable_info(drm_device_t *dev, int handle)
+drm_get_drawable_info(struct drm_device *dev, int handle)
 {
 	struct bsd_drm_drawable_info find, *result;
 
@@ -68,24 +68,21 @@ drm_get_drawable_info(drm_device_t *dev, int handle)
 	return &result->info;
 }
 
-int drm_adddraw(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_adddraw(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_draw_t *draw = data;
+	struct drm_draw *draw = data;
 	struct bsd_drm_drawable_info *info;
 
-	info = drm_calloc(1, sizeof(struct bsd_drm_drawable_info),
-	    DRM_MEM_DRAWABLE);
+	info = malloc(sizeof(struct bsd_drm_drawable_info), DRM_MEM_DRAWABLE,
+	    M_NOWAIT | M_ZERO);
 	if (info == NULL)
 		return ENOMEM;
 
-#ifdef __FreeBSD__
-	info->handle = alloc_unr(dev->drw_unrhdr);
-#else
 	/*
 	 * XXX Only valid for sizeof(int) == sizeof(void *)
 	 */
 	info->handle = (int)info;
-#endif
+
 	DRM_SPINLOCK(&dev->drw_lock);
 	RB_INSERT(drawable_tree, &dev->drw_head, info);
 	draw->handle = info->handle;
@@ -96,9 +93,9 @@ int drm_adddraw(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return 0;
 }
 
-int drm_rmdraw(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_rmdraw(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_draw_t *draw = (drm_draw_t *)data;
+	struct drm_draw *draw = (struct drm_draw *)data;
 	struct drm_drawable_info *info;
 
 	DRM_SPINLOCK(&dev->drw_lock);
@@ -107,11 +104,8 @@ int drm_rmdraw(drm_device_t *dev, void *data, struct drm_file *file_priv)
 		RB_REMOVE(drawable_tree, &dev->drw_head,
 		    (struct bsd_drm_drawable_info *)info);
 		DRM_SPINUNLOCK(&dev->drw_lock);
-#ifdef __FreeBSD__
-		free_unr(dev->drw_unrhdr, draw->handle);
-#endif
-		drm_free(info, sizeof(struct bsd_drm_drawable_info),
-		    DRM_MEM_DRAWABLE);
+		free(info->rects, DRM_MEM_DRAWABLE);
+		free(info, DRM_MEM_DRAWABLE);
 		return 0;
 	} else {
 		DRM_SPINUNLOCK(&dev->drw_lock);
@@ -119,7 +113,8 @@ int drm_rmdraw(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	}
 }
 
-int drm_update_draw(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_update_draw(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv)
 {
 	struct drm_drawable_info *info;
 	struct drm_update_draw *update = (struct drm_update_draw *)data;
@@ -133,9 +128,7 @@ int drm_update_draw(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	case DRM_DRAWABLE_CLIPRECTS:
 		DRM_SPINLOCK(&dev->drw_lock);
 		if (update->num != info->num_rects) {
-			drm_free(info->rects,
-			    sizeof(*info->rects) * info->num_rects,
-			    DRM_MEM_DRAWABLE);
+			free(info->rects, DRM_MEM_DRAWABLE);
 			info->rects = NULL;
 			info->num_rects = 0;
 		}
@@ -144,10 +137,12 @@ int drm_update_draw(drm_device_t *dev, void *data, struct drm_file *file_priv)
 			return 0;
 		}
 		if (info->rects == NULL) {
-			info->rects = drm_alloc(sizeof(*info->rects) *
-			    update->num, DRM_MEM_DRAWABLE);
-			if (info->rects == NULL)
+			info->rects = malloc(sizeof(*info->rects) *
+			    update->num, DRM_MEM_DRAWABLE, M_NOWAIT);
+			if (info->rects == NULL) {
+				DRM_SPINUNLOCK(&dev->drw_lock);
 				return ENOMEM;
+			}
 			info->num_rects = update->num;
 		}
 		/* For some reason the pointer arg is unsigned long long. */
@@ -159,3 +154,21 @@ int drm_update_draw(drm_device_t *dev, void *data, struct drm_file *file_priv)
 		return EINVAL;
 	}
 }
+
+void drm_drawable_free_all(struct drm_device *dev)
+{
+	struct bsd_drm_drawable_info *info, *next;
+
+	DRM_SPINLOCK(&dev->drw_lock);
+	for (info = RB_MIN(drawable_tree, &dev->drw_head);
+	    info != NULL ; info = next) {
+		next = RB_NEXT(drawable_tree, &dev->drw_head, info);
+		RB_REMOVE(drawable_tree, &dev->drw_head,
+		    (struct bsd_drm_drawable_info *)info);
+		DRM_SPINUNLOCK(&dev->drw_lock);
+		free(info->info.rects, DRM_MEM_DRAWABLE);
+		free(info, DRM_MEM_DRAWABLE);
+		DRM_SPINLOCK(&dev->drw_lock);
+	}
+	DRM_SPINUNLOCK(&dev->drw_lock);
+}
diff --git a/sys/dev/drm/drm_drv.c b/sys/dev/drm/drm_drv.c
index 1fc007d6bf..482990bf5a 100644
--- a/sys/dev/drm/drm_drv.c
+++ b/sys/dev/drm/drm_drv.c
@@ -26,7 +26,6 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_drv.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_drv.c
@@ -34,14 +33,10 @@
  * open/close, and ioctl dispatch.
  */
 
-#ifdef __DragonFly__
 #include <machine/limits.h>
-#else
-#include <sys/limits.h>
-#endif
-#include "drmP.h"
-#include "drm.h"
-#include "drm_sarea.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/drm_sarea.h"
 
 #ifdef DRM_DEBUG_DEFAULT_ON
 int drm_debug_flag = 1;
@@ -49,27 +44,18 @@ int drm_debug_flag = 1;
 int drm_debug_flag = 0;
 #endif
 
-static int drm_load(drm_device_t *dev);
-static void drm_unload(drm_device_t *dev);
+static int drm_load(struct drm_device *dev);
+static void drm_unload(struct drm_device *dev);
 static drm_pci_id_list_t *drm_find_description(int vendor, int device,
     drm_pci_id_list_t *idlist);
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 #define DRIVER_SOFTC(unit) \
-	((drm_device_t *)devclass_get_softc(drm_devclass, unit))
+	((struct drm_device *)devclass_get_softc(drm_devclass, unit))
 
 MODULE_VERSION(drm, 1);
 MODULE_DEPEND(drm, agp, 1, 1, 1);
 MODULE_DEPEND(drm, pci, 1, 1, 1);
-#if __FreeBSD_version > 502127
 MODULE_DEPEND(drm, mem, 1, 1, 1);
-#endif
-#endif /* __FreeBSD__ || __DragonFly__ */
-
-#if defined(__NetBSD__) || defined(__OpenBSD__)
-#define DRIVER_SOFTC(unit) \
-	((drm_device_t *)device_lookup(&drm_cd, unit))
-#endif /* __NetBSD__ || __OpenBSD__ */
 
 static drm_ioctl_desc_t		  drm_ioctls[256] = {
 	DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, 0),
@@ -92,7 +78,7 @@ static drm_ioctl_desc_t		  drm_ioctls[256] = {
 	DRM_IOCTL_DEF(DRM_IOCTL_SET_SAREA_CTX, drm_setsareactx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_IOCTL_GET_SAREA_CTX, drm_getsareactx, DRM_AUTH),
 
-	DRM_IOCTL_DEF(DRM_IOCTL_ADD_CTX, drm_addctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_IOCTL_ADD_CTX, drm_addctx, DRM_AUTH|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_IOCTL_RM_CTX, drm_rmctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_IOCTL_MOD_CTX, drm_modctx, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_IOCTL_GET_CTX, drm_getctx, DRM_AUTH),
@@ -105,10 +91,11 @@ static drm_ioctl_desc_t		  drm_ioctls[256] = {
 
 	DRM_IOCTL_DEF(DRM_IOCTL_LOCK, drm_lock, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_IOCTL_UNLOCK, drm_unlock, DRM_AUTH),
+
 	DRM_IOCTL_DEF(DRM_IOCTL_FINISH, drm_noop, DRM_AUTH),
 
-	DRM_IOCTL_DEF(DRM_IOCTL_ADD_BUFS, drm_addbufs_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
-	DRM_IOCTL_DEF(DRM_IOCTL_MARK_BUFS, drm_markbufs, DRM_AUTH|DRM_MASTER),
+	DRM_IOCTL_DEF(DRM_IOCTL_ADD_BUFS, drm_addbufs, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_IOCTL_MARK_BUFS, drm_markbufs, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_IOCTL_INFO_BUFS, drm_infobufs, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_IOCTL_MAP_BUFS, drm_mapbufs, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_IOCTL_FREE_BUFS, drm_freebufs, DRM_AUTH),
@@ -127,265 +114,169 @@ static drm_ioctl_desc_t		  drm_ioctls[256] = {
 
 	DRM_IOCTL_DEF(DRM_IOCTL_SG_ALLOC, drm_sg_alloc_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_IOCTL_SG_FREE, drm_sg_free, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
-
 	DRM_IOCTL_DEF(DRM_IOCTL_WAIT_VBLANK, drm_wait_vblank, 0),
+	DRM_IOCTL_DEF(DRM_IOCTL_MODESET_CTL, drm_modeset_ctl, 0),
 	DRM_IOCTL_DEF(DRM_IOCTL_UPDATE_DRAW, drm_update_draw, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 };
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-#ifdef __FreeBSD__
-static struct cdevsw drm_cdevsw = {
-#if __FreeBSD_version >= 502103
-	.d_version =	D_VERSION,
-#endif
-	.d_open =	drm_open,
-	.d_close =	drm_close,
-	.d_read =	drm_read,
-	.d_ioctl =	drm_ioctl,
-	.d_poll =	drm_poll,
-	.d_mmap =	drm_mmap,
-	.d_name =	"drm",
-#if __FreeBSD_version >= 502103
-	.d_flags =	D_TRACKCLOSE | D_NEEDGIANT,
-#else
-	.d_maj =	145,
-	.d_flags =	D_TRACKCLOSE,
-#endif
-#if __FreeBSD_version < 500000
-	.d_bmaj =	-1
-#endif
-};
-#else	/* __FreeBSD__ */
 static struct dev_ops drm_cdevsw = {
 	{ "drm", 145, D_TRACKCLOSE },
-	.d_open =	drm_open,
-	.d_close =	drm_close,
-	.d_read =	drm_read,
-	.d_ioctl =	drm_ioctl,
-	.d_poll =	drm_poll,
-	.d_mmap =	drm_mmap
+	.d_open =       drm_open,
+	.d_read =       drm_read,
+	.d_ioctl =      drm_ioctl,
+	.d_poll =       drm_poll,
+	.d_mmap =       drm_mmap
+};
+
+int drm_msi = 1;	/* Enable by default. */
+TUNABLE_INT("hw.drm.msi", &drm_msi);
+
+static struct drm_msi_blacklist_entry drm_msi_blacklist[] = {
+	{0x8086, 0x2772}, /* Intel i945G	*/ \
+	{0x8086, 0x27A2}, /* Intel i945GM	*/ \
+	{0x8086, 0x27AE}, /* Intel i945GME	*/ \
+	{0, 0}
 };
-#endif	/* !__FreeBSD__ */
 
-int drm_probe(device_t dev, drm_pci_id_list_t *idlist)
+static int drm_msi_is_blacklisted(int vendor, int device)
+{
+	int i = 0;
+	
+	for (i = 0; drm_msi_blacklist[i].vendor != 0; i++) {
+		if ((drm_msi_blacklist[i].vendor == vendor) &&
+		    (drm_msi_blacklist[i].device == device)) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+int drm_probe(device_t kdev, drm_pci_id_list_t *idlist)
 {
 	drm_pci_id_list_t *id_entry;
 	int vendor, device;
-#if __FreeBSD_version < 700010
 	device_t realdev;
 
-	if (!strcmp(device_get_name(dev), "drmsub"))
-		realdev = device_get_parent(dev);
+	if (!strcmp(device_get_name(kdev), "drmsub"))
+		realdev = device_get_parent(kdev);
 	else
-		realdev = dev;
+		realdev = kdev;
 	vendor = pci_get_vendor(realdev);
 	device = pci_get_device(realdev);
-#else
-	vendor = pci_get_vendor(dev);
-	device = pci_get_device(dev);
+
+#if 0 /* XXX */
+	if (pci_get_class(kdev) != PCIC_DISPLAY
+	    || pci_get_subclass(kdev) != PCIS_DISPLAY_VGA)
+		return ENXIO;
 #endif
 
 	id_entry = drm_find_description(vendor, device, idlist);
 	if (id_entry != NULL) {
-		device_set_desc(dev, id_entry->name);
+		if (!device_get_desc(kdev)) {
+			DRM_DEBUG("desc : %s\n", device_get_desc(kdev));
+			device_set_desc(kdev, id_entry->name);
+		}
 		return 0;
 	}
 
 	return ENXIO;
 }
 
-int drm_attach(device_t nbdev, drm_pci_id_list_t *idlist)
+int drm_attach(device_t kdev, drm_pci_id_list_t *idlist)
 {
-	drm_device_t *dev;
+	struct drm_device *dev;
 	drm_pci_id_list_t *id_entry;
 	int unit;
+#if 0
+	int msicount;
+#endif
 
-	unit = device_get_unit(nbdev);
-	dev = device_get_softc(nbdev);
+	unit = device_get_unit(kdev);
+	dev = device_get_softc(kdev);
 
-#if __FreeBSD_version < 700010
-	if (!strcmp(device_get_name(nbdev), "drmsub"))
-		dev->device = device_get_parent(nbdev);
+	if (!strcmp(device_get_name(kdev), "drmsub"))
+		dev->device = device_get_parent(kdev);
 	else
-		dev->device = nbdev;
-#else
-	dev->device = nbdev;
-#endif
-#ifdef __DragonFly__
+		dev->device = kdev;
+
 	dev_ops_add(&drm_cdevsw, -1, unit);
-#endif
 	dev->devnode = make_dev(&drm_cdevsw,
 			unit,
 			DRM_DEV_UID,
 			DRM_DEV_GID,
 			DRM_DEV_MODE,
 			"dri/card%d", unit);
-#if __FreeBSD_version >= 500000
-	mtx_init(&dev->dev_lock, "drm device", NULL, MTX_DEF);
-	mtx_init(&dev->drw_lock, "drmdrw", NULL, MTX_DEF);
-#elif defined(__DragonFly__)
-	DRM_SPININIT(&dev->dev_lock, "drm device");
-	DRM_SPININIT(&dev->drw_lock, "drmdrw");
-#endif
-
-	id_entry = drm_find_description(pci_get_vendor(dev->device),
-	    pci_get_device(dev->device), idlist);
-	dev->id_entry = id_entry;
-
-	return drm_load(dev);
-}
-
-int drm_detach(device_t dev)
-{
-	drm_unload(device_get_softc(dev));
-	return 0;
-}
 
-#ifndef DRM_DEV_NAME
-#define DRM_DEV_NAME "drm"
-#endif
-
-devclass_t drm_devclass;
-
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-
-static struct cdevsw drm_cdevsw = {
-	drm_open,
-	drm_close,
-	drm_read,
-	nowrite,
-	drm_ioctl,
-	nostop,
-	notty,
-	drm_poll,
-	drm_mmap,
-	nokqfilter,
-	D_TTY
-};
+	dev->pci_domain = 0;
+	dev->pci_bus = pci_get_bus(dev->device);
+	dev->pci_slot = pci_get_slot(dev->device);
+	dev->pci_func = pci_get_function(dev->device);
 
-int drm_refcnt = 0;
+	dev->pci_vendor = pci_get_vendor(dev->device);
+	dev->pci_device = pci_get_device(dev->device);
 
-#if defined(__NetBSD__) && __NetBSD_Version__ >= 106080000
-MOD_DEV("drm", DRIVER_NAME, NULL, -1, &drm_cdevsw, CDEV_MAJOR);
-#else
-MOD_DEV("drm", LM_DT_CHAR, CDEV_MAJOR, &drm_cdevsw);
+	if (drm_msi &&
+	    !drm_msi_is_blacklisted(dev->pci_vendor, dev->pci_device)) {
+#if 0
+		msicount = pci_msi_count(dev->device);
+		DRM_DEBUG("MSI count = %d\n", msicount);
+		if (msicount > 1)
+			msicount = 1;
+
+		if (pci_alloc_msi(dev->device, &msicount) == 0) {
+			DRM_INFO("MSI enabled %d message(s)\n", msicount);
+			dev->msi_enabled = 1;
+			dev->irqrid = 1;
+		}
 #endif
+	}
 
-int drm_lkmentry(struct lkm_table *lkmtp, int cmd, int ver);
-static int drm_lkmhandle(struct lkm_table *lkmtp, int cmd);
-
-int drm_modprobe(void);
-int drm_probe(struct pci_attach_args *pa);
-void drm_attach(struct pci_attach_args *pa, dev_t kdev);
-
-int drm_lkmentry(struct lkm_table *lkmtp, int cmd, int ver) {
-	DISPATCH(lkmtp, cmd, ver, drm_lkmhandle, drm_lkmhandle, drm_lkmhandle);
-}
-
-static int drm_lkmhandle(struct lkm_table *lkmtp, int cmd)
-{
-	int error = 0;
-
-	switch(cmd) {
-	case LKM_E_LOAD:
-		if (lkmexists(lkmtp))
-			return EEXIST;
+	dev->irqr = bus_alloc_resource_any(dev->device, SYS_RES_IRQ,
+	    &dev->irqrid, RF_SHAREABLE);
+	if (!dev->irqr) {
+		return ENOENT;
+	}
 
-		if(drm_modprobe())
-			return 0;
+	dev->irq = (int) rman_get_start(dev->irqr);
 
-		return 1;
+	DRM_SPININIT(&dev->dev_lock, "drmdev");
+	lwkt_serialize_init(&dev->irq_lock);
+	DRM_SPININIT(&dev->vbl_lock, "drmvbl");
+	DRM_SPININIT(&dev->drw_lock, "drmdrw");
 
-	case LKM_E_UNLOAD:
-		if (drm_refcnt > 0)
-			return (EBUSY);
-		break;
-	case LKM_E_STAT:
-		break;
+	id_entry = drm_find_description(dev->pci_vendor,
+	    dev->pci_device, idlist);
+	dev->id_entry = id_entry;
 
-	default:
-		error = EIO;
-		break;
-	}
-	
-	return error;
+	return drm_load(dev);
 }
 
-int drm_modprobe(void)
+int drm_detach(device_t kdev)
 {
-	struct pci_attach_args pa;
-	int error;
+	struct drm_device *dev;
 
-	error = pci_find_device(&pa, drm_probe, idlist);
-	if (error != 0)
-		drm_attach(&pa, 0);
+	dev = device_get_softc(kdev);
 
-	return error;
-}
+	drm_unload(dev);
 
-int drm_probe(struct pci_attach_args *pa, drm_pci_id_list_t idlist)
-{
-	const char *desc;
-	drm_pci_id_list_t *id_entry;
+	bus_release_resource(dev->device, SYS_RES_IRQ, dev->irqrid, dev->irqr);
 
-	id_entry = drm_find_description(PCI_VENDOR(pa->pa_id),
-	    PCI_PRODUCT(pa->pa_id), idlist);
-	if (id_entry != NULL) {
-		return 1;
+#if 0
+	if (dev->msi_enabled) {
+		pci_release_msi(dev->device);
+		DRM_INFO("MSI released\n");
 	}
+#endif
 
 	return 0;
 }
 
-void drm_attach(struct pci_attach_args *pa, dev_t kdev, 
-    drm_pci_id_list_t *idlist)
-{
-	int i;
-	drm_device_t *dev;
-	drm_pci_id_list_t *id_entry;
-
-	config_makeroom(kdev, &drm_cd);
-	drm_cd.cd_devs[(kdev)] = malloc(sizeof(drm_device_t), M_DRM, M_WAITOK);
-	dev = DRIVER_SOFTC(kdev);
-
-	memset(dev, 0, sizeof(drm_device_t));
-	memcpy(&dev->pa, pa, sizeof(dev->pa));
-
-	dev->irq = pa->pa_intrline;
-	dev->pci_domain = 0;
-	dev->pci_bus = pa->pa_bus;
-	dev->pci_slot = pa->pa_device;
-	dev->pci_func = pa->pa_function;
-	dev->dma_tag = pa->pa_dmat;
-
-	id_entry = drm_find_description(PCI_VENDOR(pa->pa_id),
-	    PCI_PRODUCT(pa->pa_id), idlist);
-	dev->driver.pci_id_entry = id_entry;
-
-	DRM_INFO("%s", id_entry->name);
-	drm_load(dev);
-}
-
-int drm_detach(struct device *self, int flags)
-{
-	drm_unload((drm_device_t *)self);
-	return 0;
-}
+#ifndef DRM_DEV_NAME
+#define DRM_DEV_NAME "drm"
+#endif
 
-int drm_activate(struct device *self, enum devact act)
-{
-	switch (act) {
-	case DVACT_ACTIVATE:
-		return (EOPNOTSUPP);
-		break;
-
-	case DVACT_DEACTIVATE:
-		/* FIXME */
-		break;
-	}
-	return (0);
-}
-#endif /* __NetBSD__ || __OpenBSD__ */
+devclass_t drm_devclass;
 
 drm_pci_id_list_t *drm_find_description(int vendor, int device,
     drm_pci_id_list_t *idlist)
@@ -394,14 +285,15 @@ drm_pci_id_list_t *drm_find_description(int vendor, int device,
 	
 	for (i = 0; idlist[i].vendor != 0; i++) {
 		if ((idlist[i].vendor == vendor) &&
-		    (idlist[i].device == device)) {
+		    ((idlist[i].device == device) ||
+		    (idlist[i].device == 0))) {
 			return &idlist[i];
 		}
 	}
 	return NULL;
 }
 
-static int drm_firstopen(drm_device_t *dev)
+static int drm_firstopen(struct drm_device *dev)
 {
 	drm_local_map_t *map;
 	int i;
@@ -410,22 +302,22 @@ static int drm_firstopen(drm_device_t *dev)
 
 	/* prebuild the SAREA */
 	i = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
-		       _DRM_CONTAINS_LOCK, &map);
+	    _DRM_CONTAINS_LOCK, &map);
 	if (i != 0)
 		return i;
 
-	if (dev->driver.firstopen)
-		dev->driver.firstopen(dev);
+	if (dev->driver->firstopen)
+		dev->driver->firstopen(dev);
 
 	dev->buf_use = 0;
 
-	if (dev->driver.use_dma) {
+	if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) {
 		i = drm_dma_setup(dev);
 		if (i != 0)
 			return i;
 	}
 
-	for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) {
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
 		dev->magiclist[i].head = NULL;
 		dev->magiclist[i].tail = NULL;
 	}
@@ -436,18 +328,14 @@ static int drm_firstopen(drm_device_t *dev)
 	dev->last_context = 0;
 	dev->if_version = 0;
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	dev->buf_sigio = NULL;
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	dev->buf_pgid = 0;
-#endif
 
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
 	return 0;
 }
 
-static int drm_lastclose(drm_device_t *dev)
+static int drm_lastclose(struct drm_device *dev)
 {
 	drm_magic_entry_t *pt, *next;
 	drm_local_map_t *map, *mapsave;
@@ -455,42 +343,46 @@ static int drm_lastclose(drm_device_t *dev)
 
 	DRM_SPINLOCK_ASSERT(&dev->dev_lock);
 
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-	if (dev->driver.lastclose != NULL)
-		dev->driver.lastclose(dev);
+	if (dev->driver->lastclose != NULL)
+		dev->driver->lastclose(dev);
 
 	if (dev->irq_enabled)
 		drm_irq_uninstall(dev);
 
-	if ( dev->unique ) {
-		free(dev->unique, M_DRM);
+	if (dev->unique) {
+		free(dev->unique, DRM_MEM_DRIVER);
 		dev->unique = NULL;
 		dev->unique_len = 0;
 	}
-				/* Clear pid list */
-	for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) {
-		for ( pt = dev->magiclist[i].head ; pt ; pt = next ) {
+	/* Clear pid list */
+	for (i = 0; i < DRM_HASH_SIZE; i++) {
+		for (pt = dev->magiclist[i].head; pt; pt = next) {
 			next = pt->next;
-			free(pt, M_DRM);
+			free(pt, DRM_MEM_MAGIC);
 		}
 		dev->magiclist[i].head = dev->magiclist[i].tail = NULL;
 	}
 
-				/* Clear AGP information */
-	if ( dev->agp ) {
+	DRM_UNLOCK();
+	drm_drawable_free_all(dev);
+	DRM_LOCK();
+
+	/* Clear AGP information */
+	if (dev->agp) {
 		drm_agp_mem_t *entry;
 		drm_agp_mem_t *nexte;
 
 		/* Remove AGP resources, but leave dev->agp intact until
 		 * drm_unload is called.
 		 */
-		for ( entry = dev->agp->memory ; entry ; entry = nexte ) {
+		for (entry = dev->agp->memory; entry; entry = nexte) {
 			nexte = entry->next;
-			if ( entry->bound )
+			if (entry->bound)
 				drm_agp_unbind_memory(entry->handle);
 			drm_agp_free_memory(entry->handle);
-			free(entry, M_DRM);
+			free(entry, DRM_MEM_AGPLISTS);
 		}
 		dev->agp->memory = NULL;
 
@@ -511,7 +403,7 @@ static int drm_lastclose(drm_device_t *dev)
 	}
 
 	drm_dma_takedown(dev);
-	if ( dev->lock.hw_lock ) {
+	if (dev->lock.hw_lock) {
 		dev->lock.hw_lock = NULL; /* SHM removed */
 		dev->lock.file_priv = NULL;
 		DRM_WAKEUP_INT((void *)&dev->lock.lock_queue);
@@ -520,31 +412,16 @@ static int drm_lastclose(drm_device_t *dev)
 	return 0;
 }
 
-static int drm_load(drm_device_t *dev)
+static int drm_load(struct drm_device *dev)
 {
 	int i, retcode;
 
-	DRM_DEBUG( "\n" );
-
-	dev->irq = pci_get_irq(dev->device);
-#if defined(__FreeBSD__) && __FreeBSD_version >= 700053
-	dev->pci_domain = pci_get_domain(dev->device);
-#else
-	dev->pci_domain = 0;
-#endif
-	dev->pci_bus = pci_get_bus(dev->device);
-	dev->pci_slot = pci_get_slot(dev->device);
-	dev->pci_func = pci_get_function(dev->device);
-
-	dev->pci_vendor = pci_get_vendor(dev->device);
-	dev->pci_device = pci_get_device(dev->device);
+	DRM_DEBUG("\n");
 
 	TAILQ_INIT(&dev->maplist);
 
 	drm_mem_init();
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	drm_sysctl_init(dev);
-#endif
 	TAILQ_INIT(&dev->files);
 
 	dev->counters  = 6;
@@ -555,23 +432,25 @@ static int drm_load(drm_device_t *dev)
 	dev->types[4]  = _DRM_STAT_LOCKS;
 	dev->types[5]  = _DRM_STAT_UNLOCKS;
 
-	for ( i = 0 ; i < DRM_ARRAY_SIZE(dev->counts) ; i++ )
-		atomic_set( &dev->counts[i], 0 );
+	for (i = 0; i < DRM_ARRAY_SIZE(dev->counts); i++)
+		atomic_set(&dev->counts[i], 0);
 
-	if (dev->driver.load != NULL) {
+	if (dev->driver->load != NULL) {
 		DRM_LOCK();
 		/* Shared code returns -errno. */
-		retcode = -dev->driver.load(dev,
+		retcode = -dev->driver->load(dev,
 		    dev->id_entry->driver_private);
+		pci_enable_busmaster(dev->device);
 		DRM_UNLOCK();
 		if (retcode != 0)
 			goto error;
 	}
 
-	if (dev->driver.use_agp) {
+	if (drm_core_has_AGP(dev)) {
 		if (drm_device_is_agp(dev))
 			dev->agp = drm_agp_init();
-		if (dev->driver.require_agp && dev->agp == NULL) {
+		if (drm_core_check_feature(dev, DRIVER_REQUIRE_AGP) &&
+		    dev->agp == NULL) {
 			DRM_ERROR("Card isn't AGP, or couldn't initialize "
 			    "AGP.\n");
 			retcode = ENOMEM;
@@ -590,51 +469,37 @@ static int drm_load(drm_device_t *dev)
 		goto error;
 	}
 
-#ifdef __FreeBSD__
-	dev->drw_unrhdr = new_unrhdr(1, INT_MAX, NULL);
-	if (dev->drw_unrhdr == NULL) {
-		DRM_ERROR("Couldn't allocate drawable number allocator\n");
-		goto error;
-	}
-#endif
-
 	DRM_INFO("Initialized %s %d.%d.%d %s\n",
-	  	dev->driver.name,
-	  	dev->driver.major,
-	  	dev->driver.minor,
-	  	dev->driver.patchlevel,
-	  	dev->driver.date);
+	    dev->driver->name,
+	    dev->driver->major,
+	    dev->driver->minor,
+	    dev->driver->patchlevel,
+	    dev->driver->date);
 
 	return 0;
 
 error:
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	drm_sysctl_cleanup(dev);
-#endif
 	DRM_LOCK();
 	drm_lastclose(dev);
 	DRM_UNLOCK();
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	destroy_dev(dev->devnode);
-#if __FreeBSD_version >= 500000
-	mtx_destroy(&dev->dev_lock);
-#elif defined(__DragonFly__)
+
+	DRM_SPINUNINIT(&dev->drw_lock);
+	DRM_SPINUNINIT(&dev->vbl_lock);
 	DRM_SPINUNINIT(&dev->dev_lock);
-#endif
-#endif
+
 	return retcode;
 }
 
-static void drm_unload(drm_device_t *dev)
+static void drm_unload(struct drm_device *dev)
 {
 	int i;
 
-	DRM_DEBUG( "\n" );
+	DRM_DEBUG("\n");
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	drm_sysctl_cleanup(dev);
 	destroy_dev(dev->devnode);
-#endif
 
 	drm_ctxbitmap_cleanup(dev);
 
@@ -646,6 +511,8 @@ static void drm_unload(drm_device_t *dev)
 		DRM_DEBUG("mtrr_del = %d", retcode);
 	}
 
+	drm_vblank_cleanup(dev);
+
 	DRM_LOCK();
 	drm_lastclose(dev);
 	DRM_UNLOCK();
@@ -663,30 +530,29 @@ static void drm_unload(drm_device_t *dev)
 		dev->pcir[i] = NULL;
 	}
 
-	if ( dev->agp ) {
-		free(dev->agp, M_DRM);
+	if (dev->agp) {
+		free(dev->agp, DRM_MEM_AGPLISTS);
 		dev->agp = NULL;
 	}
 
-	if (dev->driver.unload != NULL)
-		dev->driver.unload(dev);
-
-#ifdef __FreeBSD__
-	delete_unrhdr(dev->drw_unrhdr);
-#endif
+	if (dev->driver->unload != NULL) {
+		DRM_LOCK();
+		dev->driver->unload(dev);
+		DRM_UNLOCK();
+	}
 
 	drm_mem_uninit();
-#if defined(__FreeBSD__) &&  __FreeBSD_version >= 500000
-	mtx_destroy(&dev->dev_lock);
-#elif defined(__DragonFly__)
+
+	pci_disable_busmaster(dev->device);
+
+	DRM_SPINUNINIT(&dev->drw_lock);
+	DRM_SPINUNINIT(&dev->vbl_lock);
 	DRM_SPINUNINIT(&dev->dev_lock);
-#endif
 }
 
-
-int drm_version(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_version(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_version_t *version = data;
+	struct drm_version *version = data;
 	int len;
 
 #define DRM_COPY( name, value )						\
@@ -698,44 +564,37 @@ int drm_version(drm_device_t *dev, void *data, struct drm_file *file_priv)
 			return EFAULT;				\
 	}
 
-	version->version_major		= dev->driver.major;
-	version->version_minor		= dev->driver.minor;
-	version->version_patchlevel	= dev->driver.patchlevel;
+	version->version_major		= dev->driver->major;
+	version->version_minor		= dev->driver->minor;
+	version->version_patchlevel	= dev->driver->patchlevel;
 
-	DRM_COPY(version->name, dev->driver.name);
-	DRM_COPY(version->date, dev->driver.date);
-	DRM_COPY(version->desc, dev->driver.desc);
+	DRM_COPY(version->name, dev->driver->name);
+	DRM_COPY(version->date, dev->driver->date);
+	DRM_COPY(version->desc, dev->driver->desc);
 
 	return 0;
 }
 
-#ifndef __DragonFly__
-int drm_open(struct cdev *kdev, int flags, int fmt, DRM_STRUCTPROC *p)
-{
-#else
 int drm_open(struct dev_open_args *ap)
 {
 	struct cdev *kdev = ap->a_head.a_dev;
 	int flags = ap->a_oflags;
 	int fmt = 0;
 	struct thread *p = curthread;
-#endif
-	drm_device_t *dev = NULL;
+	struct drm_device *dev = NULL;
 	int retcode = 0;
 
 	dev = DRIVER_SOFTC(minor(kdev));
 
-	DRM_DEBUG( "open_count = %d\n", dev->open_count );
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
 
 	retcode = drm_open_helper(kdev, flags, fmt, p, dev);
 
-	if ( !retcode ) {
-		atomic_inc( &dev->counts[_DRM_STAT_OPENS] );
+	if (!retcode) {
+		atomic_inc(&dev->counts[_DRM_STAT_OPENS]);
 		DRM_LOCK();
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 		device_busy(dev->device);
-#endif
-		if ( !dev->open_count++ )
+		if (!dev->open_count++)
 			retcode = drm_firstopen(dev);
 		DRM_UNLOCK();
 	}
@@ -743,84 +602,60 @@ int drm_open(struct dev_open_args *ap)
 	return retcode;
 }
 
-#ifndef __DragonFly__
-int drm_close(struct cdev *kdev, int flags, int fmt, DRM_STRUCTPROC *p)
+void drm_close(void *data)
 {
-#else
-int drm_close(struct dev_close_args *ap)
-{
-	struct cdev *kdev = ap->a_head.a_dev;
-	struct thread *p = curthread;
-#endif
-	drm_device_t *dev = drm_get_device_from_kdev(kdev);
-	drm_file_t *file_priv;
+	struct drm_file *file_priv = data;
+	struct drm_device *dev = file_priv->dev;
 	int retcode = 0;
 
-	DRM_DEBUG( "open_count = %d\n", dev->open_count );
+	DRM_DEBUG("open_count = %d\n", dev->open_count);
 
 	DRM_LOCK();
 
-	file_priv = drm_find_file_by_proc(dev, p);
-	if (!file_priv) {
-		DRM_UNLOCK();
-		DRM_ERROR("can't find authenticator\n");
-		return EINVAL;
-	}
-
 	if (--file_priv->refs != 0)
 		goto done;
 
-	if (dev->driver.preclose != NULL)
-		dev->driver.preclose(dev, file_priv);
+	if (dev->driver->preclose != NULL)
+		dev->driver->preclose(dev, file_priv);
 
 	/* ========================================================
 	 * Begin inline drm_release
 	 */
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-	DRM_DEBUG( "pid = %d, device = 0x%lx, open_count = %d\n",
-		   DRM_CURRENTPID, (long)dev->device, dev->open_count );
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	DRM_DEBUG( "pid = %d, device = 0x%lx, open_count = %d\n",
-		   DRM_CURRENTPID, (long)&dev->device, dev->open_count);
-#endif
+	DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n",
+	    DRM_CURRENTPID, (long)dev->device, dev->open_count);
 
 	if (dev->lock.hw_lock && _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)
 	    && dev->lock.file_priv == file_priv) {
 		DRM_DEBUG("Process %d dead, freeing lock for context %d\n",
 			  DRM_CURRENTPID,
 			  _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
-		if (dev->driver.reclaim_buffers_locked != NULL)
-			dev->driver.reclaim_buffers_locked(dev, file_priv);
+		if (dev->driver->reclaim_buffers_locked != NULL)
+			dev->driver->reclaim_buffers_locked(dev, file_priv);
 
-		drm_lock_free(dev, &dev->lock.hw_lock->lock,
+		drm_lock_free(&dev->lock,
 		    _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock));
 		
 				/* FIXME: may require heavy-handed reset of
                                    hardware at this point, possibly
                                    processed via a callback to the X
                                    server. */
-	} else if (dev->driver.reclaim_buffers_locked != NULL &&
+	} else if (dev->driver->reclaim_buffers_locked != NULL &&
 	    dev->lock.hw_lock != NULL) {
 		/* The lock is required to reclaim buffers */
 		for (;;) {
-			if ( !dev->lock.hw_lock ) {
+			if (!dev->lock.hw_lock) {
 				/* Device has been unregistered */
 				retcode = EINTR;
 				break;
 			}
-			if (drm_lock_take(&dev->lock.hw_lock->lock,
-			    DRM_KERNEL_CONTEXT)) {
+			if (drm_lock_take(&dev->lock, DRM_KERNEL_CONTEXT)) {
 				dev->lock.file_priv = file_priv;
 				dev->lock.lock_time = jiffies;
-                                atomic_inc( &dev->counts[_DRM_STAT_LOCKS] );
+				atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
 				break;	/* Got lock */
 			}
-				/* Contention */
-#if defined(__FreeBSD__) && __FreeBSD_version > 500000
-			retcode = mtx_sleep((void *)&dev->lock.lock_queue,
-			    &dev->dev_lock, PZERO | PCATCH, "drmlk2", 0);
-#elif defined(__DragonFly__)
+			/* Contention */
 			crit_enter();
 			tsleep_interlock((void *)&dev->lock.lock_queue);
 			DRM_UNLOCK();
@@ -828,123 +663,79 @@ int drm_close(struct dev_close_args *ap)
 			    PCATCH, "drmlk2", 0);
 			crit_exit();
 			DRM_LOCK();
-#else
-			retcode = tsleep((void *)&dev->lock.lock_queue,
-			    PZERO | PCATCH, "drmlk2", 0);
-#endif
 			if (retcode)
 				break;
 		}
 		if (retcode == 0) {
-			dev->driver.reclaim_buffers_locked(dev, file_priv);
-			drm_lock_free(dev, &dev->lock.hw_lock->lock,
-			    DRM_KERNEL_CONTEXT);
+			dev->driver->reclaim_buffers_locked(dev, file_priv);
+			drm_lock_free(&dev->lock, DRM_KERNEL_CONTEXT);
 		}
 	}
 
-	if (dev->driver.use_dma && !dev->driver.reclaim_buffers_locked)
+	if (drm_core_check_feature(dev, DRIVER_HAVE_DMA) &&
+	    !dev->driver->reclaim_buffers_locked)
 		drm_reclaim_buffers(dev, file_priv);
 
-#if defined (__FreeBSD__) && (__FreeBSD_version >= 500000)
-	funsetown(&dev->buf_sigio);
-#elif defined(__FreeBSD__) || defined(__DragonFly__)
 	funsetown(dev->buf_sigio);
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	dev->buf_pgid = 0;
-#endif /* __NetBSD__  || __OpenBSD__ */
 
-	if (dev->driver.postclose != NULL)
-		dev->driver.postclose(dev, file_priv);
+	if (dev->driver->postclose != NULL)
+		dev->driver->postclose(dev, file_priv);
 	TAILQ_REMOVE(&dev->files, file_priv, link);
-	free(file_priv, M_DRM);
+	free(file_priv, DRM_MEM_FILES);
 
 	/* ========================================================
 	 * End inline drm_release
 	 */
-
 done:
-	atomic_inc( &dev->counts[_DRM_STAT_CLOSES] );
-#if defined(__FreeBSD__) || defined(__DragonFly__)
+	atomic_inc(&dev->counts[_DRM_STAT_CLOSES]);
 	device_unbusy(dev->device);
-#endif
 	if (--dev->open_count == 0) {
 		retcode = drm_lastclose(dev);
 	}
 
 	DRM_UNLOCK();
-	
-	return retcode;
 }
 
 /* drm_ioctl is called whenever a process performs an ioctl on /dev/drm.
  */
-#ifndef __DragonFly__
-int drm_ioctl(struct cdev *kdev, u_long cmd, caddr_t data, int flags, 
-    DRM_STRUCTPROC *p)
-{
-#else
 int drm_ioctl(struct dev_ioctl_args *ap)
 {
 	struct cdev *kdev = ap->a_head.a_dev;
 	u_long cmd = ap->a_cmd;
 	caddr_t data = ap->a_data;
 	struct thread *p = curthread;
-#endif
-	drm_device_t *dev = drm_get_device_from_kdev(kdev);
+	struct drm_device *dev = drm_get_device_from_kdev(kdev);
 	int retcode = 0;
 	drm_ioctl_desc_t *ioctl;
-	int (*func)(drm_device_t *dev, void *data, struct drm_file *file_priv);
+	int (*func)(struct drm_device *dev, void *data, struct drm_file *file_priv);
 	int nr = DRM_IOCTL_NR(cmd);
 	int is_driver_ioctl = 0;
-	drm_file_t *file_priv;
+	struct drm_file *file_priv;
 
-	DRM_LOCK();
 	file_priv = drm_find_file_by_proc(dev, p);
-	DRM_UNLOCK();
-	if (file_priv == NULL) {
+	if (!file_priv) {
 		DRM_ERROR("can't find authenticator\n");
 		return EINVAL;
 	}
 
-	atomic_inc( &dev->counts[_DRM_STAT_IOCTLS] );
+	atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]);
 	++file_priv->ioctl_count;
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-	DRM_DEBUG( "pid=%d, cmd=0x%02lx, nr=0x%02x, dev 0x%lx, auth=%d\n",
+	DRM_DEBUG("pid=%d, cmd=0x%02lx, nr=0x%02x, dev 0x%lx, auth=%d\n",
 	    DRM_CURRENTPID, cmd, nr, (long)dev->device,
-	    file_priv->authenticated );
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	DRM_DEBUG( "pid=%d, cmd=0x%02lx, nr=0x%02x, dev 0x%lx, auth=%d\n",
-	    DRM_CURRENTPID, cmd, nr, (long)&dev->device,
-	    file_priv->authenticated );
-#endif
+	    file_priv->authenticated);
 
 	switch (cmd) {
 	case FIONBIO:
 	case FIOASYNC:
 		return 0;
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	case FIOSETOWN:
 		return fsetown(*(int *)data, &dev->buf_sigio);
 
 	case FIOGETOWN:
-#if (__FreeBSD_version >= 500000)
-		*(int *) data = fgetown(&dev->buf_sigio);
-#else
 		*(int *) data = fgetown(dev->buf_sigio);
-#endif
-		return 0;
-#endif /* __FreeBSD__ || __DragonFly__ */
-#if defined(__NetBSD__) || defined(__OpenBSD__)
-	case TIOCSPGRP:
-		dev->buf_pgid = *(int *)data;
-		return 0;
-
-	case TIOCGPGRP:
-		*(int *)data = dev->buf_pgid;
 		return 0;
-#endif /* __NetBSD__ */
 	}
 
 	if (IOCGROUP(cmd) != DRM_IOCTL_BASE) {
@@ -957,18 +748,18 @@ int drm_ioctl(struct dev_ioctl_args *ap)
 	if (ioctl->func == NULL && nr >= DRM_COMMAND_BASE) {
 		/* The array entries begin at DRM_COMMAND_BASE ioctl nr */
 		nr -= DRM_COMMAND_BASE;
-		if (nr > dev->driver.max_ioctl) {
+		if (nr > dev->driver->max_ioctl) {
 			DRM_DEBUG("Bad driver ioctl number, 0x%x (of 0x%x)\n",
-			    nr, dev->driver.max_ioctl);
+			    nr, dev->driver->max_ioctl);
 			return EINVAL;
 		}
-		ioctl = &dev->driver.ioctls[nr];
+		ioctl = &dev->driver->ioctls[nr];
 		is_driver_ioctl = 1;
 	}
 	func = ioctl->func;
 
 	if (func == NULL) {
-		DRM_DEBUG( "no function\n" );
+		DRM_DEBUG("no function\n");
 		return EINVAL;
 	}
 
@@ -992,7 +783,7 @@ int drm_ioctl(struct dev_ioctl_args *ap)
 	return retcode;
 }
 
-drm_local_map_t *drm_getsarea(drm_device_t *dev)
+drm_local_map_t *drm_getsarea(struct drm_device *dev)
 {
 	drm_local_map_t *map;
 
diff --git a/sys/dev/drm/drm_fops.c b/sys/dev/drm/drm_fops.c
index a0948398ea..a6a4cd5ebf 100644
--- a/sys/dev/drm/drm_fops.c
+++ b/sys/dev/drm/drm_fops.c
@@ -27,7 +27,6 @@
  *    Daryll Strauss <daryll@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_fops.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_fops.c
@@ -35,23 +34,13 @@
  * open of the DRM device.
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
-drm_file_t *drm_find_file_by_proc(drm_device_t *dev, DRM_STRUCTPROC *p)
+struct drm_file *drm_find_file_by_proc(struct drm_device *dev, DRM_STRUCTPROC *p)
 {
-#if __FreeBSD_version >= 500021
-	uid_t uid = p->td_ucred->cr_svuid;
-	pid_t pid = p->td_proc->p_pid;
-#elif defined(__DragonFly__)
 	uid_t uid = p->td_proc->p_ucred->cr_svuid;
 	pid_t pid = p->td_proc->p_pid;
-#else
-	uid_t uid = p->p_cred->p_svuid;
-	pid_t pid = p->p_pid;
-#endif
-	drm_file_t *priv;
-
-	DRM_SPINLOCK_ASSERT(&dev->dev_lock);
+	struct drm_file *priv;
 
 	TAILQ_FOREACH(priv, &dev->files, link)
 		if (priv->pid == pid && priv->uid == uid)
@@ -61,10 +50,10 @@ drm_file_t *drm_find_file_by_proc(drm_device_t *dev, DRM_STRUCTPROC *p)
 
 /* drm_open_helper is called whenever a process opens /dev/drm. */
 int drm_open_helper(struct cdev *kdev, int flags, int fmt, DRM_STRUCTPROC *p,
-		    drm_device_t *dev)
+		    struct drm_device *dev)
 {
-	int	     m = minor(kdev);
-	drm_file_t   *priv;
+	struct drm_file *priv;
+	int m = minor(kdev);
 	int retcode;
 
 	if (flags & O_EXCL)
@@ -72,79 +61,55 @@ int drm_open_helper(struct cdev *kdev, int flags, int fmt, DRM_STRUCTPROC *p,
 	dev->flags = flags;
 
 	DRM_DEBUG("pid = %d, minor = %d\n", DRM_CURRENTPID, m);
-
-	DRM_LOCK();
-	priv = drm_find_file_by_proc(dev, p);
-	if (priv) {
-		priv->refs++;
-	} else {
-		priv = malloc(sizeof(*priv), M_DRM, M_NOWAIT | M_ZERO);
-		if (priv == NULL) {
-			DRM_UNLOCK();
-			return ENOMEM;
-		}
-#if __FreeBSD_version >= 500000
-		priv->uid		= p->td_ucred->cr_svuid;
-		priv->pid		= p->td_proc->p_pid;
-#elif defined(__DragonFly__)
-		priv->uid		= p->td_proc->p_ucred->cr_svuid;
-		priv->pid		= p->td_proc->p_pid;
-#else
-		priv->uid		= p->p_cred->p_svuid;
-		priv->pid		= p->p_pid;
-#endif
-
-		priv->refs		= 1;
-		priv->minor		= m;
-		priv->ioctl_count 	= 0;
-
-		/* for compatibility root is always authenticated */
-		priv->authenticated	= DRM_SUSER(p);
-
-		if (dev->driver.open) {
-			/* shared code returns -errno */
-			retcode = -dev->driver.open(dev, priv);
-			if (retcode != 0) {
-				free(priv, M_DRM);
-				DRM_UNLOCK();
-				return retcode;
-			}
-		}
-
-		/* first opener automatically becomes master */
-		priv->master = TAILQ_EMPTY(&dev->files);
-
-		TAILQ_INSERT_TAIL(&dev->files, priv, link);
+        DRM_LOCK();
+        priv = drm_find_file_by_proc(dev, p);
+        if (priv) {
+                priv->refs++;
+        } else {
+                priv = malloc(sizeof(*priv), DRM_MEM_FILES, M_NOWAIT | M_ZERO);
+                if (priv == NULL) {
+                        DRM_UNLOCK();
+                        return ENOMEM;
+                }
+                priv->uid               = p->td_proc->p_ucred->cr_svuid;
+                priv->pid               = p->td_proc->p_pid;
+                priv->refs              = 1;
+                priv->minor             = m;
+                priv->ioctl_count       = 0;
+
+                /* for compatibility root is always authenticated */
+                priv->authenticated     = DRM_SUSER(p);
+
+                if (dev->driver->open) {
+                        /* shared code returns -errno */
+                        retcode = -dev->driver->open(dev, priv);
+                        if (retcode != 0) {
+                                free(priv, DRM_MEM_FILES);
+                                DRM_UNLOCK();
+                                return retcode;
+                        }
+                }
+
+                /* first opener automatically becomes master */
+                priv->master = TAILQ_EMPTY(&dev->files);
+
+                TAILQ_INSERT_TAIL(&dev->files, priv, link);
 	}
+
 	DRM_UNLOCK();
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	kdev->si_drv1 = dev;
-#endif
 	return 0;
 }
 
 
 /* The drm_read and drm_poll are stubs to prevent spurious errors
  * on older X Servers (4.3.0 and earlier) */
-
-#ifdef __DragonFly__
 int drm_read(struct dev_read_args *ap)
-{
-	return (0);
-}
-
-int drm_poll(struct dev_poll_args *ap)
-{
-	return (0);
-}
-#else
-int drm_read(struct cdev *kdev, struct uio *uio, int ioflag)
 {
 	return 0;
 }
 
-int drm_poll(struct cdev *kdev, int events, DRM_STRUCTPROC *p)
+int drm_poll(struct dev_poll_args *ap)
 {
 	return 0;
 }
-#endif
diff --git a/sys/dev/drm/drm_internal.h b/sys/dev/drm/drm_internal.h
index 4d35e164c7..cd72ecdd2e 100644
--- a/sys/dev/drm/drm_internal.h
+++ b/sys/dev/drm/drm_internal.h
@@ -1,4 +1,4 @@
-/*
+/*-
  * Copyright 2007 Red Hat, Inc
  * All rights reserved.
  *
@@ -20,8 +20,6 @@
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/drm_internal.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /* This header file holds function prototypes and data types that are
diff --git a/sys/dev/drm/drm_ioctl.c b/sys/dev/drm/drm_ioctl.c
index daf5fe06c7..86760402ac 100644
--- a/sys/dev/drm/drm_ioctl.c
+++ b/sys/dev/drm/drm_ioctl.c
@@ -26,7 +26,6 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_ioctl.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_ioctl.c
@@ -34,7 +33,7 @@
  * information and reporting DRM information to userland.
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
 /*
  * Beginning in revision 1.1 of the DRM interface, getunique will return
@@ -42,9 +41,10 @@
  * before setunique has been called.  The format for the bus-specific part of
  * the unique is not defined for any other bus.
  */
-int drm_getunique(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_getunique(struct drm_device *dev, void *data,
+		  struct drm_file *file_priv)
 {
-	drm_unique_t	 *u = data;
+	struct drm_unique *u = data;
 
 	if (u->unique_len >= dev->unique_len) {
 		if (DRM_COPY_TO_USER(u->unique, dev->unique, dev->unique_len))
@@ -58,9 +58,10 @@ int drm_getunique(drm_device_t *dev, void *data, struct drm_file *file_priv)
 /* Deprecated in DRM version 1.1, and will return EBUSY when setversion has
  * requested version 1.1 or greater.
  */
-int drm_setunique(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_setunique(struct drm_device *dev, void *data,
+		  struct drm_file *file_priv)
 {
-	drm_unique_t *u = data;
+	struct drm_unique *u = data;
 	int domain, bus, slot, func, ret;
 	char *busid;
 
@@ -68,12 +69,12 @@ int drm_setunique(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	if (!u->unique_len || u->unique_len > 1024)
 		return EINVAL;
 
-	busid = malloc(u->unique_len + 1, M_DRM, M_WAITOK);
+	busid = malloc(u->unique_len + 1, DRM_MEM_DRIVER, M_WAITOK);
 	if (busid == NULL)
 		return ENOMEM;
 
 	if (DRM_COPY_FROM_USER(busid, u->unique, u->unique_len)) {
-		free(busid, M_DRM);
+		free(busid, DRM_MEM_DRIVER);
 		return EFAULT;
 	}
 	busid[u->unique_len] = '\0';
@@ -83,7 +84,7 @@ int drm_setunique(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	 */
 	ret = sscanf(busid, "PCI:%d:%d:%d", &bus, &slot, &func);
 	if (ret != 3) {
-		free(busid, M_DRM);
+		free(busid, DRM_MEM_DRIVER);
 		return EINVAL;
 	}
 	domain = bus >> 8;
@@ -93,7 +94,7 @@ int drm_setunique(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	    (bus != dev->pci_bus) ||
 	    (slot != dev->pci_slot) ||
 	    (func != dev->pci_func)) {
-		free(busid, M_DRM);
+		free(busid, DRM_MEM_DRIVER);
 		return EINVAL;
 	}
 
@@ -113,7 +114,7 @@ int drm_setunique(drm_device_t *dev, void *data, struct drm_file *file_priv)
 
 
 static int
-drm_set_busid(drm_device_t *dev)
+drm_set_busid(struct drm_device *dev)
 {
 
 	DRM_LOCK();
@@ -124,7 +125,7 @@ drm_set_busid(drm_device_t *dev)
 	}
 
 	dev->unique_len = 20;
-	dev->unique = malloc(dev->unique_len + 1, M_DRM, M_NOWAIT);
+	dev->unique = malloc(dev->unique_len + 1, DRM_MEM_DRIVER, M_NOWAIT);
 	if (dev->unique == NULL) {
 		DRM_UNLOCK();
 		return ENOMEM;
@@ -138,9 +139,9 @@ drm_set_busid(drm_device_t *dev)
 	return 0;
 }
 
-int drm_getmap(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_getmap(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_map_t    *map = data;
+	struct drm_map     *map = data;
 	drm_local_map_t    *mapinlist;
 	int          idx;
 	int	     i = 0;
@@ -154,7 +155,7 @@ int drm_getmap(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	}
 
 	TAILQ_FOREACH(mapinlist, &dev->maplist, link) {
-		if (i==idx) {
+		if (i == idx) {
 			map->offset = mapinlist->offset;
 			map->size   = mapinlist->size;
 			map->type   = mapinlist->type;
@@ -174,18 +175,18 @@ int drm_getmap(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return 0;
 }
 
-int drm_getclient(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_getclient(struct drm_device *dev, void *data,
+		  struct drm_file *file_priv)
 {
-	drm_client_t *client = data;
-	drm_file_t   *pt;
-	int          idx;
-	int          i = 0;
+	struct drm_client *client = data;
+	struct drm_file *pt;
+	int idx;
+	int i = 0;
 
 	idx = client->idx;
 	DRM_LOCK();
 	TAILQ_FOREACH(pt, &dev->files, link) {
-		if (i==idx)
-		{
+		if (i == idx) {
 			client->auth  = pt->authenticated;
 			client->pid   = pt->pid;
 			client->uid   = pt->uid;
@@ -201,23 +202,22 @@ int drm_getclient(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	return EINVAL;
 }
 
-int drm_getstats(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_getstats(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_stats_t  *stats = data;
+	struct drm_stats *stats = data;
 	int          i;
 
-	memset(stats, 0, sizeof(drm_stats_t));
+	memset(stats, 0, sizeof(struct drm_stats));
 	
 	DRM_LOCK();
 
 	for (i = 0; i < dev->counters; i++) {
 		if (dev->types[i] == _DRM_STAT_LOCK)
-			stats->data[i].value
-				= (dev->lock.hw_lock
-				   ? dev->lock.hw_lock->lock : 0);
+			stats->data[i].value =
+			    (dev->lock.hw_lock ? dev->lock.hw_lock->lock : 0);
 		else 
 			stats->data[i].value = atomic_read(&dev->counts[i]);
-		stats->data[i].type  = dev->types[i];
+		stats->data[i].type = dev->types[i];
 	}
 	
 	stats->count = dev->counters;
@@ -230,10 +230,11 @@ int drm_getstats(drm_device_t *dev, void *data, struct drm_file *file_priv)
 #define DRM_IF_MAJOR	1
 #define DRM_IF_MINOR	2
 
-int drm_setversion(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_setversion(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv)
 {
-	drm_set_version_t *sv = data;
-	drm_set_version_t ver;
+	struct drm_set_version *sv = data;
+	struct drm_set_version ver;
 	int if_version;
 
 	/* Save the incoming data, and set the response before continuing
@@ -242,8 +243,8 @@ int drm_setversion(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	ver = *sv;
 	sv->drm_di_major = DRM_IF_MAJOR;
 	sv->drm_di_minor = DRM_IF_MINOR;
-	sv->drm_dd_major = dev->driver.major;
-	sv->drm_dd_minor = dev->driver.minor;
+	sv->drm_dd_major = dev->driver->major;
+	sv->drm_dd_minor = dev->driver->minor;
 
 	if (ver.drm_di_major != -1) {
 		if (ver.drm_di_major != DRM_IF_MAJOR ||
@@ -262,9 +263,9 @@ int drm_setversion(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	}
 
 	if (ver.drm_dd_major != -1) {
-		if (ver.drm_dd_major != dev->driver.major ||
+		if (ver.drm_dd_major != dev->driver->major ||
 		    ver.drm_dd_minor < 0 ||
-		    ver.drm_dd_minor > dev->driver.minor)
+		    ver.drm_dd_minor > dev->driver->minor)
 		{
 			return EINVAL;
 		}
@@ -274,7 +275,7 @@ int drm_setversion(drm_device_t *dev, void *data, struct drm_file *file_priv)
 }
 
 
-int drm_noop(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_noop(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
 	DRM_DEBUG("\n");
 	return 0;
diff --git a/sys/dev/drm/drm_irq.c b/sys/dev/drm/drm_irq.c
index e75daacdf2..2681b26c15 100644
--- a/sys/dev/drm/drm_irq.c
+++ b/sys/dev/drm/drm_irq.c
@@ -23,7 +23,6 @@
  * Authors:
  *    Eric Anholt <anholt@FreeBSD.org>
  *
- * $DragonFly: src/sys/dev/drm/drm_irq.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_irq.c
@@ -31,14 +30,13 @@
  * handing interrupt handlers off to the drivers.
  */
 
-#include "drmP.h"
-#include "drm.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
 
-static void drm_locked_task(void *context, int pending __unused);
-
-int drm_irq_by_busid(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_irq_by_busid(struct drm_device *dev, void *data,
+		     struct drm_file *file_priv)
 {
-	drm_irq_busid_t *irq = data;
+	struct drm_irq_busid *irq = data;
 
 	if ((irq->busnum >> 8) != dev->pci_domain ||
 	    (irq->busnum & 0xff) != dev->pci_bus ||
@@ -49,34 +47,100 @@ int drm_irq_by_busid(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	irq->irq = dev->irq;
 
 	DRM_DEBUG("%d:%d:%d => IRQ %d\n",
-		  irq->busnum, irq->devnum, irq->funcnum, irq->irq);
+	    irq->busnum, irq->devnum, irq->funcnum, irq->irq);
 
 	return 0;
 }
 
-#if defined(__FreeBSD__) && __FreeBSD_version >= 500000
-static irqreturn_t
-drm_irq_handler_wrap(DRM_IRQ_ARGS)
+static void vblank_disable_fn(void *arg)
 {
-	drm_device_t *dev = (drm_device_t *)arg;
+	struct drm_device *dev = (struct drm_device *)arg;
+	int i;
 
-	DRM_SPINLOCK(&dev->irq_lock);
-	dev->driver.irq_handler(arg);
-	DRM_SPINUNLOCK(&dev->irq_lock);
+	if (callout_pending(&dev->vblank_disable_timer)) {
+		/* callout was reset */
+		return;
+	}
+	if (!callout_active(&dev->vblank_disable_timer)) {
+		/* callout was stopped */
+		return;
+	}
+	callout_deactivate(&dev->vblank_disable_timer);
+
+	DRM_DEBUG("vblank_disable: %s\n", dev->vblank_disable_allowed ?
+		"allowed" : "denied");
+	if (!dev->vblank_disable_allowed)
+		return;
+
+	for (i = 0; i < dev->num_crtcs; i++) {
+		if (atomic_read(&dev->vblank[i].refcount) == 0 &&
+		    dev->vblank[i].enabled && !dev->vblank[i].inmodeset) {
+			DRM_DEBUG("disabling vblank on crtc %d\n", i);
+			dev->vblank[i].last =
+			    dev->driver->get_vblank_counter(dev, i);
+			dev->driver->disable_vblank(dev, i);
+			dev->vblank[i].enabled = 0;
+		}
+	}
 }
-#endif
 
-int drm_irq_install(drm_device_t *dev)
+void drm_vblank_cleanup(struct drm_device *dev)
 {
-	int retcode;
-#ifdef __NetBSD__
-	pci_intr_handle_t ih;
-#endif
+	/* Bail if the driver didn't call drm_vblank_init() */
+	if (dev->num_crtcs == 0)
+		return;
+
+	DRM_SPINLOCK(&dev->vbl_lock);
+	callout_stop(&dev->vblank_disable_timer);
+	DRM_SPINUNLOCK(&dev->vbl_lock);
+
+	vblank_disable_fn((void *)dev);
+
+	free(dev->vblank, DRM_MEM_DRIVER);
+
+	dev->num_crtcs = 0;
+}
+
+int drm_vblank_init(struct drm_device *dev, int num_crtcs)
+{
+	int i, ret = ENOMEM;
+
+	callout_init(&dev->vblank_disable_timer);
+	atomic_set(&dev->vbl_signal_pending, 0);
+	dev->num_crtcs = num_crtcs;
+
+	dev->vblank = malloc(sizeof(struct drm_vblank_info) * num_crtcs,
+	    DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
+	if (!dev->vblank)
+	    goto err;
+
+	DRM_DEBUG("\n");
+
+	/* Zero per-crtc vblank stuff */
+	for (i = 0; i < num_crtcs; i++) {
+		DRM_INIT_WAITQUEUE(&dev->vblank[i].queue);
+		TAILQ_INIT(&dev->vblank[i].sigs);
+		atomic_set(&dev->vblank[i].count, 0);
+		atomic_set(&dev->vblank[i].refcount, 0);
+	}
+
+	dev->vblank_disable_allowed = 0;
+
+	return 0;
+
+err:
+	drm_vblank_cleanup(dev);
+	return ret;
+}
+
+int drm_irq_install(struct drm_device *dev)
+{
+	int crtc, retcode;
 
 	if (dev->irq == 0 || dev->dev_private == NULL)
 		return EINVAL;
 
-	DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq );
+	DRM_DEBUG("irq=%d\n", dev->irq);
 
 	DRM_LOCK();
 	if (dev->irq_enabled) {
@@ -87,130 +151,94 @@ int drm_irq_install(drm_device_t *dev)
 
 	dev->context_flag = 0;
 
-#ifndef __DragonFly__
-	DRM_SPININIT(&dev->irq_lock, "DRM IRQ lock");
-#else
-	lwkt_serialize_init(&dev->irq_lock);
-#endif
-
-				/* Before installing handler */
-	dev->driver.irq_preinstall(dev);
+	/* Before installing handler */
+	dev->driver->irq_preinstall(dev);
 	DRM_UNLOCK();
 
-				/* Install handler */
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-	dev->irqrid = 0;
-	dev->irqr = bus_alloc_resource_any(dev->device, SYS_RES_IRQ, 
-				      &dev->irqrid, RF_SHAREABLE);
-	if (!dev->irqr) {
-		retcode = ENOENT;
-		goto err;
-	}
-#if __FreeBSD_version >= 700031
-	retcode = bus_setup_intr(dev->device, dev->irqr,
-				 INTR_TYPE_TTY | INTR_MPSAFE,
-				 NULL, drm_irq_handler_wrap, dev, &dev->irqh);
-#elif defined(__DragonFly__)
-	retcode = bus_setup_intr(dev->device, dev->irqr,
-				 INTR_MPSAFE,
-				 dev->driver.irq_handler, dev, &dev->irqh,
+	/* Install handler */
+	retcode = bus_setup_intr(dev->device, dev->irqr, INTR_MPSAFE,
+				 dev->driver->irq_handler, dev, &dev->irqh,
 				 &dev->irq_lock);
-#else
-	retcode = bus_setup_intr(dev->device, dev->irqr,
-				 INTR_TYPE_TTY | INTR_MPSAFE,
-				 drm_irq_handler_wrap, dev, &dev->irqh);
-#endif
 	if (retcode != 0)
 		goto err;
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	if (pci_intr_map(&dev->pa, &ih) != 0) {
-		retcode = ENOENT;
-		goto err;
-	}
-	dev->irqh = pci_intr_establish(&dev->pa.pa_pc, ih, IPL_TTY,
-	    (irqreturn_t (*)(void *))dev->irq_handler, dev);
-	if (!dev->irqh) {
-		retcode = ENOENT;
-		goto err;
-	}
-#endif
 
-				/* After installing handler */
+	/* After installing handler */
 	DRM_LOCK();
-	dev->driver.irq_postinstall(dev);
+	dev->driver->irq_postinstall(dev);
 	DRM_UNLOCK();
+	if (dev->driver->enable_vblank) {
+		DRM_SPINLOCK(&dev->vbl_lock);
+		for( crtc = 0 ; crtc < dev->num_crtcs ; crtc++) {
+			if (dev->driver->enable_vblank(dev, crtc) == 0) {
+				dev->vblank[crtc].enabled = 1;
+			}
+		}
+		callout_reset(&dev->vblank_disable_timer, 5 * DRM_HZ,
+		    (timeout_t *)vblank_disable_fn, (void *)dev);
+		DRM_SPINUNLOCK(&dev->vbl_lock);
+	}
 
-	TASK_INIT(&dev->locked_task, 0, drm_locked_task, dev);
 	return 0;
 err:
 	DRM_LOCK();
 	dev->irq_enabled = 0;
-#if defined(___FreeBSD__) || defined(__DragonFly__)
-	if (dev->irqrid != 0) {
-		bus_release_resource(dev->device, SYS_RES_IRQ, dev->irqrid,
-		    dev->irqr);
-		dev->irqrid = 0;
-	}
-#endif
-#ifndef __DragonFly__
-	DRM_SPINUNINIT(&dev->irq_lock);
-#endif
 	DRM_UNLOCK();
+
 	return retcode;
 }
 
-int drm_irq_uninstall(drm_device_t *dev)
+int drm_irq_uninstall(struct drm_device *dev)
 {
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-	int irqrid;
-#endif
+	int crtc;
 
 	if (!dev->irq_enabled)
 		return EINVAL;
 
 	dev->irq_enabled = 0;
-#if defined(__FreeBSD__) || defined(__DragonFly__)
-	irqrid = dev->irqrid;
-	dev->irqrid = 0;
-#endif
 
-	DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq );
+	/*
+	* Wake up any waiters so they don't hang.
+	*/
+	DRM_SPINLOCK(&dev->vbl_lock);
+	for (crtc = 0; crtc < dev->num_crtcs; crtc++) {
+		if (dev->vblank[crtc].enabled) {
+			DRM_WAKEUP(&dev->vblank[crtc].queue);
+			dev->vblank[crtc].last =
+			    dev->driver->get_vblank_counter(dev, crtc);
+			dev->vblank[crtc].enabled = 0;
+		}
+	}
+	DRM_SPINUNLOCK(&dev->vbl_lock);
 
-	dev->driver.irq_uninstall(dev);
+	DRM_DEBUG("irq=%d\n", dev->irq);
+
+	dev->driver->irq_uninstall(dev);
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	DRM_UNLOCK();
 	bus_teardown_intr(dev->device, dev->irqr, dev->irqh);
-	bus_release_resource(dev->device, SYS_RES_IRQ, irqrid, dev->irqr);
 	DRM_LOCK();
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	pci_intr_disestablish(&dev->pa.pa_pc, dev->irqh);
-#endif
-#ifndef __DragonFly__
-	DRM_SPINUNINIT(&dev->irq_lock);
-#endif
 
 	return 0;
 }
 
-int drm_control(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_control(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_control_t *ctl = data;
+	struct drm_control *ctl = data;
 	int err;
 
-	switch ( ctl->func ) {
+	switch (ctl->func) {
 	case DRM_INST_HANDLER:
 		/* Handle drivers whose DRM used to require IRQ setup but the
 		 * no longer does.
 		 */
-		if (!dev->driver.use_irq)
+		if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
 			return 0;
 		if (dev->if_version < DRM_IF_VERSION(1, 2) &&
 		    ctl->irq != dev->irq)
 			return EINVAL;
 		return drm_irq_install(dev);
 	case DRM_UNINST_HANDLER:
-		if (!dev->driver.use_irq)
+		if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ))
 			return 0;
 		DRM_LOCK();
 		err = drm_irq_uninstall(dev);
@@ -221,12 +249,136 @@ int drm_control(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	}
 }
 
-int drm_wait_vblank(drm_device_t *dev, void *data, struct drm_file *file_priv)
+u32 drm_vblank_count(struct drm_device *dev, int crtc)
+{
+	return atomic_read(&dev->vblank[crtc].count);
+}
+
+static void drm_update_vblank_count(struct drm_device *dev, int crtc)
+{
+	u32 cur_vblank, diff;
+
+	/*
+	 * Interrupts were disabled prior to this call, so deal with counter
+	 * wrap if needed.
+	 * NOTE!  It's possible we lost a full dev->max_vblank_count events
+	 * here if the register is small or we had vblank interrupts off for
+	 * a long time.
+	 */
+	cur_vblank = dev->driver->get_vblank_counter(dev, crtc);
+	diff = cur_vblank - dev->vblank[crtc].last;
+	if (cur_vblank < dev->vblank[crtc].last) {
+		diff += dev->max_vblank_count;
+
+		DRM_DEBUG("vblank[%d].last=0x%x, cur_vblank=0x%x => diff=0x%x\n",
+		    crtc, dev->vblank[crtc].last, cur_vblank, diff);
+	}
+
+	DRM_DEBUG("enabling vblank interrupts on crtc %d, missed %d\n",
+	    crtc, diff);
+
+	atomic_add(diff, &dev->vblank[crtc].count);
+}
+
+int drm_vblank_get(struct drm_device *dev, int crtc)
+{
+	int ret = 0;
+
+	DRM_SPINLOCK(&dev->vbl_lock);
+	/* Going from 0->1 means we have to enable interrupts again */
+	atomic_add_acq_int(&dev->vblank[crtc].refcount, 1);
+	if (dev->vblank[crtc].refcount == 1 &&
+	    !dev->vblank[crtc].enabled) {
+		ret = dev->driver->enable_vblank(dev, crtc);
+		DRM_DEBUG("enabling vblank on crtc %d, ret: %d\n", crtc, ret);
+		if (ret)
+			atomic_dec(&dev->vblank[crtc].refcount);
+		else {
+			dev->vblank[crtc].enabled = 1;
+			drm_update_vblank_count(dev, crtc);
+		}
+	}
+	DRM_SPINUNLOCK(&dev->vbl_lock);
+
+	return ret;
+}
+
+void drm_vblank_put(struct drm_device *dev, int crtc)
+{
+	KASSERT(atomic_read(&dev->vblank[crtc].refcount) > 0,
+	    ("invalid refcount"));
+
+	/* Last user schedules interrupt disable */
+	atomic_subtract_acq_int(&dev->vblank[crtc].refcount, 1);
+
+	DRM_SPINLOCK(&dev->vbl_lock);
+	if (dev->vblank[crtc].refcount == 0)
+	    callout_reset(&dev->vblank_disable_timer, 5 * DRM_HZ,
+		(timeout_t *)vblank_disable_fn, (void *)dev);
+	DRM_SPINUNLOCK(&dev->vbl_lock);
+}
+
+int drm_modeset_ctl(struct drm_device *dev, void *data,
+		    struct drm_file *file_priv)
+{
+	struct drm_modeset_ctl *modeset = data;
+	int crtc, ret = 0;
+
+	DRM_DEBUG("num_crtcs=%d\n", dev->num_crtcs);
+	/* If drm_vblank_init() hasn't been called yet, just no-op */
+	if (!dev->num_crtcs)
+		goto out;
+
+	crtc = modeset->crtc;
+	DRM_DEBUG("crtc=%d\n", crtc);
+	if (crtc >= dev->num_crtcs) {
+		ret = EINVAL;
+		goto out;
+	}
+
+	/*
+	 * To avoid all the problems that might happen if interrupts
+	 * were enabled/disabled around or between these calls, we just
+	 * have the kernel take a reference on the CRTC (just once though
+	 * to avoid corrupting the count if multiple, mismatch calls occur),
+	 * so that interrupts remain enabled in the interim.
+	 */
+	switch (modeset->cmd) {
+	case _DRM_PRE_MODESET:
+		DRM_DEBUG("pre-modeset\n");
+		if (!dev->vblank[crtc].inmodeset) {
+			dev->vblank[crtc].inmodeset = 0x1;
+			if (drm_vblank_get(dev, crtc) == 0)
+				dev->vblank[crtc].inmodeset |= 0x2;
+		}
+		break;
+	case _DRM_POST_MODESET:
+		DRM_DEBUG("post-modeset\n");
+		if (dev->vblank[crtc].inmodeset) {
+			DRM_SPINLOCK(&dev->vbl_lock);
+			dev->vblank_disable_allowed = 1;
+			DRM_SPINUNLOCK(&dev->vbl_lock);
+
+			if (dev->vblank[crtc].inmodeset & 0x2)
+				drm_vblank_put(dev, crtc);
+
+			dev->vblank[crtc].inmodeset = 0;
+		}
+		break;
+	default:
+		ret = EINVAL;
+		break;
+	}
+
+out:
+	return ret;
+}
+
+int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_wait_vblank_t *vblwait = data;
-	struct timeval now;
+	union drm_wait_vblank *vblwait = data;
+	unsigned int flags, seq, crtc;
 	int ret = 0;
-	int flags, seq;
 
 	if (!dev->irq_enabled)
 		return EINVAL;
@@ -240,12 +392,17 @@ int drm_wait_vblank(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	}
 
 	flags = vblwait->request.type & _DRM_VBLANK_FLAGS_MASK;
+	crtc = flags & _DRM_VBLANK_SECONDARY ? 1 : 0;
 
-	if ((flags & _DRM_VBLANK_SECONDARY) && !dev->driver.use_vbl_irq2)
+	if (crtc >= dev->num_crtcs)
 		return EINVAL;
-	
-	seq = atomic_read((flags & _DRM_VBLANK_SECONDARY) ?
-	    &dev->vbl_received2 : &dev->vbl_received);
+
+	ret = drm_vblank_get(dev, crtc);
+	if (ret) {
+		DRM_ERROR("failed to acquire vblank counter, %d\n", ret);
+		return ret;
+	}
+	seq = drm_vblank_count(dev, crtc);
 
 	switch (vblwait->request.type & _DRM_VBLANK_TYPES_MASK) {
 	case _DRM_VBLANK_RELATIVE:
@@ -254,7 +411,8 @@ int drm_wait_vblank(drm_device_t *dev, void *data, struct drm_file *file_priv)
 	case _DRM_VBLANK_ABSOLUTE:
 		break;
 	default:
-		return EINVAL;
+		ret = EINVAL;
+		goto done;
 	}
 
 	if ((flags & _DRM_VBLANK_NEXTONMISS) &&
@@ -264,8 +422,8 @@ int drm_wait_vblank(drm_device_t *dev, void *data, struct drm_file *file_priv)
 
 	if (flags & _DRM_VBLANK_SIGNAL) {
 #if 0 /* disabled */
-		drm_vbl_sig_t *vbl_sig = malloc(sizeof(drm_vbl_sig_t), M_DRM,
-		    M_NOWAIT | M_ZERO);
+		drm_vbl_sig_t *vbl_sig = malloc(sizeof(drm_vbl_sig_t),
+		    DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
 		if (vbl_sig == NULL)
 			return ENOMEM;
 
@@ -275,39 +433,54 @@ int drm_wait_vblank(drm_device_t *dev, void *data, struct drm_file *file_priv)
 
 		vblwait->reply.sequence = atomic_read(&dev->vbl_received);
 		
-		DRM_SPINLOCK(&dev->irq_lock);
+		DRM_SPINLOCK(&dev->vbl_lock);
 		TAILQ_INSERT_HEAD(&dev->vbl_sig_list, vbl_sig, link);
-		DRM_SPINUNLOCK(&dev->irq_lock);
+		DRM_SPINUNLOCK(&dev->vbl_lock);
 		ret = 0;
 #endif
 		ret = EINVAL;
 	} else {
-		DRM_LOCK();
-		/* shared code returns -errno */
-		if (flags & _DRM_VBLANK_SECONDARY) {
-			if (dev->driver.vblank_wait2)
-				ret = -dev->driver.vblank_wait2(dev,
-				    &vblwait->request.sequence);
-		} else if (dev->driver.vblank_wait)
-			ret = -dev->driver.vblank_wait(dev,
-			    &vblwait->request.sequence);
-
-		DRM_UNLOCK();
+		DRM_DEBUG("waiting on vblank count %d, crtc %d\n",
+		    vblwait->request.sequence, crtc);
+		dev->vblank[crtc].last = vblwait->request.sequence;
+		for ( ret = 0 ; !ret && !(((drm_vblank_count(dev, crtc) -
+		    vblwait->request.sequence) <= (1 << 23)) ||
+		    !dev->irq_enabled) ; ) {
+			lwkt_serialize_enter(&dev->irq_lock);
+			if (!(((drm_vblank_count(dev, crtc) -
+			    vblwait->request.sequence) <= (1 << 23)) ||
+			    !dev->irq_enabled))
+				ret = serialize_sleep(&dev->vblank[crtc].queue,
+				    &dev->irq_lock, PCATCH, "vblwtq",
+				    3 * DRM_HZ);
+			lwkt_serialize_exit(&dev->irq_lock);
+		}
 
-		microtime(&now);
-		vblwait->reply.tval_sec = now.tv_sec;
-		vblwait->reply.tval_usec = now.tv_usec;
+		if (ret != EINTR && ret != ERESTART) {
+			struct timeval now;
+
+			microtime(&now);
+			vblwait->reply.tval_sec = now.tv_sec;
+			vblwait->reply.tval_usec = now.tv_usec;
+			vblwait->reply.sequence = drm_vblank_count(dev, crtc);
+			DRM_DEBUG("returning %d to client, irq_enabled %d\n",
+			    vblwait->reply.sequence, dev->irq_enabled);
+		} else {
+			DRM_DEBUG("vblank wait interrupted by signal\n");
+		}
 	}
 
+done:
+	drm_vblank_put(dev, crtc);
 	return ret;
 }
 
-void drm_vbl_send_signals(drm_device_t *dev)
+void drm_vbl_send_signals(struct drm_device *dev, int crtc)
 {
 }
 
 #if 0 /* disabled */
-void drm_vbl_send_signals( drm_device_t *dev )
+void drm_vbl_send_signals(struct drm_device *dev, int crtc )
 {
 	drm_vbl_sig_t *vbl_sig;
 	unsigned int vbl_seq = atomic_read( &dev->vbl_received );
@@ -317,7 +490,7 @@ void drm_vbl_send_signals( drm_device_t *dev )
 	while (vbl_sig != NULL) {
 		drm_vbl_sig_t *next = TAILQ_NEXT(vbl_sig, link);
 
-		if ( ( vbl_seq - vbl_sig->sequence ) <= (1<<23) ) {
+		if ((vbl_seq - vbl_sig->sequence) <= (1 << 23)) {
 			p = pfind(vbl_sig->pid);
 			if (p != NULL)
 				psignal(p, vbl_sig->signo);
@@ -330,52 +503,10 @@ void drm_vbl_send_signals( drm_device_t *dev )
 }
 #endif
 
-static void drm_locked_task(void *context, int pending __unused)
+void drm_handle_vblank(struct drm_device *dev, int crtc)
 {
-	drm_device_t *dev = context;
-
-	DRM_LOCK();
-	for (;;) {
-		int ret;
-
-		if (drm_lock_take(&dev->lock.hw_lock->lock,
-		    DRM_KERNEL_CONTEXT))
-		{
-			dev->lock.file_priv = NULL; /* kernel owned */
-			dev->lock.lock_time = jiffies;
-			atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
-			break;  /* Got lock */
-		}
-
-		/* Contention */
-#if defined(__FreeBSD__) && __FreeBSD_version > 500000
-		ret = mtx_sleep((void *)&dev->lock.lock_queue, &dev->dev_lock,
-		    PZERO | PCATCH, "drmlk2", 0);
-#elif defined(__DragonFly__)
-		crit_enter();
-		tsleep_interlock((void *)&dev->lock.lock_queue);
-		DRM_UNLOCK();
-		ret = tsleep((void *)&dev->lock.lock_queue, PCATCH,
-		    "drmlk2", 0);
-		crit_exit();
-		DRM_LOCK();
-#else
-		ret = tsleep((void *)&dev->lock.lock_queue, PZERO | PCATCH,
-		    "drmlk2", 0);
-#endif
-		if (ret != 0)
-			return;
-	}
-	DRM_UNLOCK();
-
-	dev->locked_task_call(dev);
-
-	drm_lock_free(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
+	atomic_inc(&dev->vblank[crtc].count);
+	DRM_WAKEUP(&dev->vblank[crtc].queue);
+	drm_vbl_send_signals(dev, crtc);
 }
 
-void
-drm_locked_tasklet(drm_device_t *dev, void (*tasklet)(drm_device_t *dev))
-{
-	dev->locked_task_call = tasklet;
-	taskqueue_enqueue(taskqueue_swi, &dev->locked_task);
-}
diff --git a/sys/dev/drm/drm_linux_list.h b/sys/dev/drm/drm_linux_list.h
index 686dce5b88..15c1b6ee07 100644
--- a/sys/dev/drm/drm_linux_list.h
+++ b/sys/dev/drm/drm_linux_list.h
@@ -27,7 +27,6 @@
  * Authors:
  *    Eric Anholt <anholt@FreeBSD.org>
  *
- * $DragonFly: src/sys/dev/drm/drm_linux_list.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 struct list_head {
@@ -65,8 +64,12 @@ list_del(struct list_head *entry) {
 #define list_for_each(entry, head)				\
     for (entry = (head)->next; entry != head; entry = (entry)->next)
 
+#define list_for_each_prev(entry, head) \
+        for (entry = (head)->prev; entry != (head); \
+                entry = entry->prev)
+
 #define list_for_each_safe(entry, temp, head)			\
     for (entry = (head)->next, temp = (entry)->next;		\
-	temp != head; 						\
-	entry = temp, temp = temp->next)
+	entry != head; 						\
+	entry = temp, temp = entry->next)
 
diff --git a/sys/dev/drm/drm_lock.c b/sys/dev/drm/drm_lock.c
index dfd3d1bb96..32c8419795 100644
--- a/sys/dev/drm/drm_lock.c
+++ b/sys/dev/drm/drm_lock.c
@@ -26,7 +26,6 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_lock.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_lock.c
@@ -48,91 +47,30 @@
  * contending client may be woken up.
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
-int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context)
+int drm_lock(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	unsigned int old, new;
-
-	do {
-		old = *lock;
-		if (old & _DRM_LOCK_HELD) new = old | _DRM_LOCK_CONT;
-		else			  new = context | _DRM_LOCK_HELD;
-	} while (!atomic_cmpset_int(lock, old, new));
-
-	if (_DRM_LOCKING_CONTEXT(old) == context) {
-		if (old & _DRM_LOCK_HELD) {
-			if (context != DRM_KERNEL_CONTEXT) {
-				DRM_ERROR("%d holds heavyweight lock\n",
-					  context);
-			}
-			return 0;
-		}
-	}
-	if (new == (context | _DRM_LOCK_HELD)) {
-				/* Have lock */
-		return 1;
-	}
-	return 0;
-}
-
-/* This takes a lock forcibly and hands it to context.	Should ONLY be used
-   inside *_unlock to give lock to kernel before calling *_dma_schedule. */
-int drm_lock_transfer(drm_device_t *dev,
-		       __volatile__ unsigned int *lock, unsigned int context)
-{
-	unsigned int old, new;
-
-	dev->lock.file_priv = NULL;
-	do {
-		old  = *lock;
-		new  = context | _DRM_LOCK_HELD;
-	} while (!atomic_cmpset_int(lock, old, new));
-
-	return 1;
-}
-
-int drm_lock_free(drm_device_t *dev,
-		   __volatile__ unsigned int *lock, unsigned int context)
-{
-	unsigned int old, new;
-
-	dev->lock.file_priv = NULL;
-	do {
-		old  = *lock;
-		new  = 0;
-	} while (!atomic_cmpset_int(lock, old, new));
-
-	if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) {
-		DRM_ERROR("%d freed heavyweight lock held by %d\n",
-			  context, _DRM_LOCKING_CONTEXT(old));
-		return 1;
-	}
-	DRM_WAKEUP_INT((void *)&dev->lock.lock_queue);
-	return 0;
-}
+	struct drm_lock *lock = data;
+	int ret = 0;
 
-int drm_lock(drm_device_t *dev, void *data, struct drm_file *file_priv)
-{
-        drm_lock_t *lock = data;
-        int ret = 0;
-
-        if (lock->context == DRM_KERNEL_CONTEXT) {
-                DRM_ERROR("Process %d using kernel context %d\n",
+	if (lock->context == DRM_KERNEL_CONTEXT) {
+		DRM_ERROR("Process %d using kernel context %d\n",
 		    DRM_CURRENTPID, lock->context);
-                return EINVAL;
-        }
+		return EINVAL;
+	}
 
-        DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
+	DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n",
 	    lock->context, DRM_CURRENTPID, dev->lock.hw_lock->lock,
 	    lock->flags);
 
-        if (dev->driver.use_dma_queue && lock->context < 0)
-                return EINVAL;
+	if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) &&
+	    lock->context < 0)
+		return EINVAL;
 
 	DRM_LOCK();
 	for (;;) {
-		if (drm_lock_take(&dev->lock.hw_lock->lock, lock->context)) {
+		if (drm_lock_take(&dev->lock, lock->context)) {
 			dev->lock.file_priv = file_priv;
 			dev->lock.lock_time = jiffies;
 			atomic_inc(&dev->counts[_DRM_STAT_LOCKS]);
@@ -140,10 +78,6 @@ int drm_lock(drm_device_t *dev, void *data, struct drm_file *file_priv)
 		}
 
 		/* Contention */
-#if defined(__FreeBSD__) && __FreeBSD_version > 500000
-		ret = mtx_sleep((void *)&dev->lock.lock_queue, &dev->dev_lock,
-		    PZERO | PCATCH, "drmlk2", 0);
-#elif defined(__DragonFly__)
 		crit_enter();
 		tsleep_interlock((void *)&dev->lock.lock_queue);
 		DRM_UNLOCK();
@@ -151,53 +85,117 @@ int drm_lock(drm_device_t *dev, void *data, struct drm_file *file_priv)
 		    "drmlk2", 0);
 		crit_exit();
 		DRM_LOCK();
-#else
-		ret = tsleep((void *)&dev->lock.lock_queue, PZERO | PCATCH,
-		    "drmlk2", 0);
-#endif
 		if (ret != 0)
 			break;
 	}
 	DRM_UNLOCK();
-	DRM_DEBUG("%d %s\n", lock->context, ret ? "interrupted" : "has lock");
+
+	if (ret == ERESTART)
+		DRM_DEBUG("restarting syscall\n");
+	else
+		DRM_DEBUG("%d %s\n", lock->context,
+		    ret ? "interrupted" : "has lock");
 
 	if (ret != 0)
 		return ret;
 
 	/* XXX: Add signal blocking here */
 
-	if (dev->driver.dma_quiescent != NULL &&
+	if (dev->driver->dma_quiescent != NULL &&
 	    (lock->flags & _DRM_LOCK_QUIESCENT))
-		dev->driver.dma_quiescent(dev);
+		dev->driver->dma_quiescent(dev);
 
 	return 0;
 }
 
-int drm_unlock(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int drm_unlock(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_lock_t *lock = data;
+	struct drm_lock *lock = data;
+
+	DRM_DEBUG("%d (pid %d) requests unlock (0x%08x), flags = 0x%08x\n",
+	    lock->context, DRM_CURRENTPID, dev->lock.hw_lock->lock,
+	    lock->flags);
 
 	if (lock->context == DRM_KERNEL_CONTEXT) {
 		DRM_ERROR("Process %d using kernel context %d\n",
 		    DRM_CURRENTPID, lock->context);
 		return EINVAL;
 	}
-	/* Check that the context unlock being requested actually matches
-	 * who currently holds the lock.
-	 */
-	if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) ||
-	    _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) != lock->context)
-		return EINVAL;
 
 	atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]);
 
 	DRM_LOCK();
-	drm_lock_transfer(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT);
+	drm_lock_transfer(&dev->lock, DRM_KERNEL_CONTEXT);
 
-	if (drm_lock_free(dev, &dev->lock.hw_lock->lock, DRM_KERNEL_CONTEXT)) {
+	if (drm_lock_free(&dev->lock, DRM_KERNEL_CONTEXT)) {
 		DRM_ERROR("\n");
 	}
 	DRM_UNLOCK();
 
 	return 0;
 }
+
+int drm_lock_take(struct drm_lock_data *lock_data, unsigned int context)
+{
+	volatile unsigned int *lock = &lock_data->hw_lock->lock;
+	unsigned int old, new;
+
+	do {
+		old = *lock;
+		if (old & _DRM_LOCK_HELD)
+			new = old | _DRM_LOCK_CONT;
+		else
+			new = context | _DRM_LOCK_HELD;
+	} while (!atomic_cmpset_int(lock, old, new));
+
+	if (_DRM_LOCKING_CONTEXT(old) == context) {
+		if (old & _DRM_LOCK_HELD) {
+			if (context != DRM_KERNEL_CONTEXT) {
+				DRM_ERROR("%d holds heavyweight lock\n",
+				    context);
+			}
+			return 0;
+		}
+	}
+	if (new == (context | _DRM_LOCK_HELD)) {
+		/* Have lock */
+		return 1;
+	}
+	return 0;
+}
+
+/* This takes a lock forcibly and hands it to context.	Should ONLY be used
+   inside *_unlock to give lock to kernel before calling *_dma_schedule. */
+int drm_lock_transfer(struct drm_lock_data *lock_data, unsigned int context)
+{
+	volatile unsigned int *lock = &lock_data->hw_lock->lock;
+	unsigned int old, new;
+
+	lock_data->file_priv = NULL;
+	do {
+		old = *lock;
+		new = context | _DRM_LOCK_HELD;
+	} while (!atomic_cmpset_int(lock, old, new));
+
+	return 1;
+}
+
+int drm_lock_free(struct drm_lock_data *lock_data, unsigned int context)
+{
+	volatile unsigned int *lock = &lock_data->hw_lock->lock;
+	unsigned int old, new;
+
+	lock_data->file_priv = NULL;
+	do {
+		old = *lock;
+		new = 0;
+	} while (!atomic_cmpset_int(lock, old, new));
+
+	if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) {
+		DRM_ERROR("%d freed heavyweight lock held by %d\n",
+		    context, _DRM_LOCKING_CONTEXT(old));
+		return 1;
+	}
+	DRM_WAKEUP_INT((void *)&lock_data->lock_queue);
+	return 0;
+}
diff --git a/sys/dev/drm/drm_memory.c b/sys/dev/drm/drm_memory.c
index d4c7adc971..85c054597c 100644
--- a/sys/dev/drm/drm_memory.c
+++ b/sys/dev/drm/drm_memory.c
@@ -26,7 +26,6 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/drm_memory.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_memory.c
@@ -37,73 +36,54 @@
  * has been stripped out for now.
  */
 
-#include "drmP.h"
-
-MALLOC_DEFINE(M_DRM, "drm", "DRM Data Structures");
+#include "dev/drm/drmP.h"
+
+MALLOC_DEFINE(DRM_MEM_DMA, "drm_dma", "DRM DMA Data Structures");
+MALLOC_DEFINE(DRM_MEM_SAREA, "drm_sarea", "DRM SAREA Data Structures");
+MALLOC_DEFINE(DRM_MEM_DRIVER, "drm_driver", "DRM DRIVER Data Structures");
+MALLOC_DEFINE(DRM_MEM_MAGIC, "drm_magic", "DRM MAGIC Data Structures");
+MALLOC_DEFINE(DRM_MEM_IOCTLS, "drm_ioctls", "DRM IOCTL Data Structures");
+MALLOC_DEFINE(DRM_MEM_MAPS, "drm_maps", "DRM MAP Data Structures");
+MALLOC_DEFINE(DRM_MEM_BUFS, "drm_bufs", "DRM BUFFER Data Structures");
+MALLOC_DEFINE(DRM_MEM_SEGS, "drm_segs", "DRM SEGMENTS Data Structures");
+MALLOC_DEFINE(DRM_MEM_PAGES, "drm_pages", "DRM PAGES Data Structures");
+MALLOC_DEFINE(DRM_MEM_FILES, "drm_files", "DRM FILE Data Structures");
+MALLOC_DEFINE(DRM_MEM_QUEUES, "drm_queues", "DRM QUEUE Data Structures");
+MALLOC_DEFINE(DRM_MEM_CMDS, "drm_cmds", "DRM COMMAND Data Structures");
+MALLOC_DEFINE(DRM_MEM_MAPPINGS, "drm_mapping", "DRM MAPPING Data Structures");
+MALLOC_DEFINE(DRM_MEM_BUFLISTS, "drm_buflists", "DRM BUFLISTS Data Structures");
+MALLOC_DEFINE(DRM_MEM_AGPLISTS, "drm_agplists", "DRM AGPLISTS Data Structures");
+MALLOC_DEFINE(DRM_MEM_CTXBITMAP, "drm_ctxbitmap",
+    "DRM CTXBITMAP Data Structures");
+MALLOC_DEFINE(DRM_MEM_SGLISTS, "drm_sglists", "DRM SGLISTS Data Structures");
+MALLOC_DEFINE(DRM_MEM_DRAWABLE, "drm_drawable", "DRM DRAWABLE Data Structures");
 
 void drm_mem_init(void)
 {
-#if defined(__NetBSD__) || defined(__OpenBSD__)
-	malloc_type_attach(M_DRM);
-#endif
 }
 
 void drm_mem_uninit(void)
 {
 }
 
-void *drm_alloc(size_t size, int area)
-{
-	return malloc(size, M_DRM, M_NOWAIT);
-}
-
-void *drm_calloc(size_t nmemb, size_t size, int area)
-{
-	return malloc(size * nmemb, M_DRM, M_NOWAIT | M_ZERO);
-}
-
-void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area)
+void *drm_ioremap_wc(struct drm_device *dev, drm_local_map_t *map)
 {
-	void *pt;
-
-	pt = malloc(size, M_DRM, M_NOWAIT);
-	if (pt == NULL)
-		return NULL;
-	if (oldpt && oldsize) {
-		memcpy(pt, oldpt, oldsize);
-		free(oldpt, M_DRM);
-	}
-	return pt;
-}
-
-void drm_free(void *pt, size_t size, int area)
-{
-	free(pt, M_DRM);
+#if 0 /* XXX */
+	return pmap_mapdev_attr(map->offset, map->size, PAT_WRITE_COMBINING);
+#endif
+	return pmap_mapdev(map->offset, map->size);
 }
 
-void *drm_ioremap(drm_device_t *dev, drm_local_map_t *map)
+void *drm_ioremap(struct drm_device *dev, drm_local_map_t *map)
 {
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	return pmap_mapdev(map->offset, map->size);
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	map->bst = dev->pa.pa_memt;
-	if (bus_space_map(map->bst, map->offset, map->size, 
-	    BUS_SPACE_MAP_LINEAR, &map->bsh))
-		return NULL;
-	return bus_space_vaddr(map->bst, map->bsh);
-#endif
 }
 
 void drm_ioremapfree(drm_local_map_t *map)
 {
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	pmap_unmapdev((vm_offset_t) map->handle, map->size);
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-	bus_space_unmap(map->bst, map->bsh, map->size);
-#endif
 }
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 int
 drm_mtrr_add(unsigned long offset, size_t size, int flags)
 {
@@ -131,30 +111,3 @@ drm_mtrr_del(int __unused handle, unsigned long offset, size_t size, int flags)
 	strlcpy(mrdesc.mr_owner, "drm", sizeof(mrdesc.mr_owner));
 	return mem_range_attr_set(&mrdesc, &act);
 }
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-int
-drm_mtrr_add(unsigned long offset, size_t size, int flags)
-{
-	struct mtrr mtrrmap;
-	int one = 1;
-
-	mtrrmap.base = offset;
-	mtrrmap.len = size;
-	mtrrmap.type = flags;
-	mtrrmap.flags = MTRR_VALID;
-	return mtrr_set(&mtrrmap, &one, NULL, MTRR_GETSET_KERNEL);
-}
-
-int
-drm_mtrr_del(unsigned long offset, size_t size, int flags)
-{
-	struct mtrr mtrrmap;
-	int one = 1;
-
-	mtrrmap.base = offset;
-	mtrrmap.len = size;
-	mtrrmap.type = flags;
-	mtrrmap.flags = 0;
-	return mtrr_set(&mtrrmap, &one, NULL, MTRR_GETSET_KERNEL);
-}
-#endif
diff --git a/sys/dev/drm/drm_pci.c b/sys/dev/drm/drm_pci.c
index 35facada67..ce7ed369b7 100644
--- a/sys/dev/drm/drm_pci.c
+++ b/sys/dev/drm/drm_pci.c
@@ -19,8 +19,6 @@
  * AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/drm_pci.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /**
@@ -30,13 +28,12 @@
  * \author Eric Anholt <anholt@FreeBSD.org>
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
 /**********************************************************************/
 /** \name PCI memory */
 /*@{*/
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 static void
 drm_pci_busdma_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 {
@@ -48,14 +45,14 @@ drm_pci_busdma_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error
 	KASSERT(nsegs == 1, ("drm_pci_busdma_callback: bad dma segment count"));
 	dmah->busaddr = segs[0].ds_addr;
 }
-#endif
 
 /**
  * \brief Allocate a physically contiguous DMA-accessible consistent 
  * memory block.
  */
 drm_dma_handle_t *
-drm_pci_alloc(drm_device_t *dev, size_t size, size_t align, dma_addr_t maxaddr)
+drm_pci_alloc(struct drm_device *dev, size_t size,
+	      size_t align, dma_addr_t maxaddr)
 {
 	drm_dma_handle_t *dmah;
 	int ret;
@@ -67,60 +64,48 @@ drm_pci_alloc(drm_device_t *dev, size_t size, size_t align, dma_addr_t maxaddr)
 		return NULL;
 	}
 
-	dmah = malloc(sizeof(drm_dma_handle_t), M_DRM, M_ZERO | M_NOWAIT);
+	dmah = malloc(sizeof(drm_dma_handle_t), DRM_MEM_DMA, M_ZERO | M_NOWAIT);
 	if (dmah == NULL)
 		return NULL;
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
+#if 0 /* HT XXX XXX XXX */
+	/* Make sure we aren't holding locks here */
+	mtx_assert(&dev->dev_lock, MA_NOTOWNED);
+	if (mtx_owned(&dev->dev_lock))
+	    DRM_ERROR("called while holding dev_lock\n");
+	mtx_assert(&dev->dma_lock, MA_NOTOWNED);
+	if (mtx_owned(&dev->dma_lock))
+	    DRM_ERROR("called while holding dma_lock\n");
+#endif
+
 	ret = bus_dma_tag_create(NULL, align, 0, /* tag, align, boundary */
 	    maxaddr, BUS_SPACE_MAXADDR, /* lowaddr, highaddr */
 	    NULL, NULL, /* filtfunc, filtfuncargs */
 	    size, 1, size, /* maxsize, nsegs, maxsegsize */
-	    BUS_DMA_ALLOCNOW, /* flags */
-#ifdef __FreeBSD__
-	    NULL, NULL, /* lockfunc, lockfuncargs */
-#endif
+	    0, /* flags */
 	    &dmah->tag);
 	if (ret != 0) {
-		free(dmah, M_DRM);
+		free(dmah, DRM_MEM_DMA);
 		return NULL;
 	}
 
-	ret = bus_dmamem_alloc(dmah->tag, &dmah->vaddr, BUS_DMA_NOWAIT,
-	    &dmah->map);
+	ret = bus_dmamem_alloc(dmah->tag, &dmah->vaddr,
+	    BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmah->map);
 	if (ret != 0) {
 		bus_dma_tag_destroy(dmah->tag);
-		free(dmah, M_DRM);
+		free(dmah, DRM_MEM_DMA);
 		return NULL;
 	}
 
 	ret = bus_dmamap_load(dmah->tag, dmah->map, dmah->vaddr, size,
-	    drm_pci_busdma_callback, dmah, 0);
+	    drm_pci_busdma_callback, dmah, BUS_DMA_NOWAIT);
 	if (ret != 0) {
 		bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
 		bus_dma_tag_destroy(dmah->tag);
-		free(dmah, M_DRM);
-		return NULL;
-	}
-#elif defined(__NetBSD__)
-	ret = bus_dmamem_alloc(dev->dma_tag, size, align, PAGE_SIZE,
-	    &dmah->seg, 1, &nsegs, BUS_DMA_NOWAIT);
-	if ((ret != 0) || (nsegs != 1)) {
-		free(dmah, M_DRM);
+		free(dmah, DRM_MEM_DMA);
 		return NULL;
 	}
 
-	ret = bus_dmamem_map(dev->dma_tag, &dmah->seg, 1, size, &dmah->addr,
-	    BUS_DMA_NOWAIT);
-	if (ret != 0) {
-		bus_dmamem_free(dev->dma_tag, &dmah->seg, 1);
-		free(dmah, M_DRM);
-		return NULL;
-	}
-
-	dmah->dmaaddr = h->seg.ds_addr;
-#endif
-
 	return dmah;
 }
 
@@ -128,19 +113,15 @@ drm_pci_alloc(drm_device_t *dev, size_t size, size_t align, dma_addr_t maxaddr)
  * \brief Free a DMA-accessible consistent memory block.
  */
 void
-drm_pci_free(drm_device_t *dev, drm_dma_handle_t *dmah)
+drm_pci_free(struct drm_device *dev, drm_dma_handle_t *dmah)
 {
 	if (dmah == NULL)
 		return;
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 	bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
 	bus_dma_tag_destroy(dmah->tag);
-#elif defined(__NetBSD__)
-	bus_dmamem_free(dev->dma_tag, &dmah->seg, 1);
-#endif
 
-	free(dmah, M_DRM);
+	free(dmah, DRM_MEM_DMA);
 }
 
 /*@}*/
diff --git a/sys/dev/drm/drm_pciids.h b/sys/dev/drm/drm_pciids.h
index 7daf2121f4..32ae901b73 100644
--- a/sys/dev/drm/drm_pciids.h
+++ b/sys/dev/drm/drm_pciids.h
@@ -1,4 +1,6 @@
-/* $DragonFly: src/sys/dev/drm/drm_pciids.h,v 1.1 2008/04/05 18:12:29 hasso Exp $ */
+/*
+ * $FreeBSD$
+ */
 /*
    This file is auto-generated from the drm_pciids.txt in the DRM CVS
    Please contact dri-devel@lists.sf.net to add new cards to this list
@@ -84,38 +86,39 @@
 	{0x1002, 0x5460, CHIP_RV380|RADEON_IS_MOBILITY, "ATI Radeon Mobility X300 M22"}, \
 	{0x1002, 0x5462, CHIP_RV380|RADEON_IS_MOBILITY, "ATI Radeon Mobility X600 SE M24C"}, \
 	{0x1002, 0x5464, CHIP_RV380|RADEON_IS_MOBILITY, "ATI FireGL M22 GL 5464"}, \
-	{0x1002, 0x5548, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800"}, \
-	{0x1002, 0x5549, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800 Pro"}, \
-	{0x1002, 0x554A, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800 XT PE"}, \
-	{0x1002, 0x554B, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800 SE"}, \
-	{0x1002, 0x554C, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R430 X800 XTP"}, \
-	{0x1002, 0x554D, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R430 X800 XL"}, \
-	{0x1002, 0x554E, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R430 X800 SE"}, \
-	{0x1002, 0x554F, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R430 X800"}, \
-	{0x1002, 0x5550, CHIP_R420|RADEON_NEW_MEMMAP, "ATI FireGL V7100 R423"}, \
-	{0x1002, 0x5551, CHIP_R420|RADEON_NEW_MEMMAP, "ATI FireGL V5100 R423 UQ"}, \
-	{0x1002, 0x5552, CHIP_R420|RADEON_NEW_MEMMAP, "ATI FireGL unknown R423 UR"}, \
-	{0x1002, 0x5554, CHIP_R420|RADEON_NEW_MEMMAP, "ATI FireGL unknown R423 UT"}, \
+	{0x1002, 0x5548, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800"}, \
+	{0x1002, 0x5549, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800 Pro"}, \
+	{0x1002, 0x554A, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800 XT PE"}, \
+	{0x1002, 0x554B, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800 SE"}, \
+	{0x1002, 0x554C, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R430 X800 XTP"}, \
+	{0x1002, 0x554D, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R430 X800 XL"}, \
+	{0x1002, 0x554E, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R430 X800 SE"}, \
+	{0x1002, 0x554F, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R430 X800"}, \
+	{0x1002, 0x5550, CHIP_R423|RADEON_NEW_MEMMAP, "ATI FireGL V7100 R423"}, \
+	{0x1002, 0x5551, CHIP_R423|RADEON_NEW_MEMMAP, "ATI FireGL V5100 R423 UQ"}, \
+	{0x1002, 0x5552, CHIP_R423|RADEON_NEW_MEMMAP, "ATI FireGL unknown R423 UR"}, \
+	{0x1002, 0x5554, CHIP_R423|RADEON_NEW_MEMMAP, "ATI FireGL unknown R423 UT"}, \
 	{0x1002, 0x564A, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL V5000 M26"}, \
 	{0x1002, 0x564B, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL V5000 M26"}, \
 	{0x1002, 0x564F, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Radeon Mobility X700 XL M26"}, \
 	{0x1002, 0x5652, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Radeon Mobility X700 M26"}, \
 	{0x1002, 0x5653, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Radeon Mobility X700 M26"}, \
+	{0x1002, 0x5657, CHIP_RV410|RADEON_NEW_MEMMAP, "ATI Radeon X550XTX"}, \
 	{0x1002, 0x5834, CHIP_RS300|RADEON_IS_IGP, "ATI Radeon RS300 9100 IGP"}, \
 	{0x1002, 0x5835, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY, "ATI Radeon RS300 Mobility IGP"}, \
-	{0x1002, 0x5954, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI RS480 XPRESS 200G"}, \
-	{0x1002, 0x5955, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon XPRESS 200M 5955"}, \
-	{0x1002, 0x5974, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon RS482 XPRESS 200"}, \
-	{0x1002, 0x5975, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon RS485 XPRESS 1100 IGP"}, \
+	{0x1002, 0x5954, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_IGPGART, "ATI RS480 XPRESS 200G"}, \
+	{0x1002, 0x5955, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon XPRESS 200M 5955"}, \
+	{0x1002, 0x5974, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon RS482 XPRESS 200"}, \
+	{0x1002, 0x5975, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon RS485 XPRESS 1100 IGP"}, \
 	{0x1002, 0x5960, CHIP_RV280, "ATI Radeon RV280 9250"}, \
 	{0x1002, 0x5961, CHIP_RV280, "ATI Radeon RV280 9200"}, \
 	{0x1002, 0x5962, CHIP_RV280, "ATI Radeon RV280 9200"}, \
 	{0x1002, 0x5964, CHIP_RV280, "ATI Radeon RV280 9200 SE"}, \
 	{0x1002, 0x5965, CHIP_RV280, "ATI FireMV 2200 PCI"}, \
 	{0x1002, 0x5969, CHIP_RV100, "ATI ES1000 RN50"}, \
-	{0x1002, 0x5a41, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon RS400 XPRESS 200"}, \
-	{0x1002, 0x5a42, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon RS400 XPRESS 200M"}, \
-	{0x1002, 0x5a61, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon RC410 XPRESS 200"}, \
+	{0x1002, 0x5a41, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART, "ATI Radeon XPRESS 200 5A41 (PCIE)"}, \
+	{0x1002, 0x5a42, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon XPRESS 200M 5A42 (PCIE)"}, \
+	{0x1002, 0x5a61, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART, "ATI Radeon RC410 XPRESS 200"}, \
 	{0x1002, 0x5a62, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART, "ATI Radeon RC410 XPRESS 200M"}, \
 	{0x1002, 0x5b60, CHIP_RV380|RADEON_NEW_MEMMAP, "ATI Radeon RV370 X300 SE"}, \
 	{0x1002, 0x5b62, CHIP_RV380|RADEON_NEW_MEMMAP, "ATI Radeon RV370 X600 Pro"}, \
@@ -124,16 +127,16 @@
 	{0x1002, 0x5b65, CHIP_RV380|RADEON_NEW_MEMMAP, "ATI FireMV 2200 PCIE (RV370) 5B65"}, \
 	{0x1002, 0x5c61, CHIP_RV280|RADEON_IS_MOBILITY, "ATI Radeon RV280 Mobility"}, \
 	{0x1002, 0x5c63, CHIP_RV280|RADEON_IS_MOBILITY, "ATI Radeon RV280 Mobility"}, \
-	{0x1002, 0x5d48, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon X800 XT M28"}, \
-	{0x1002, 0x5d49, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL V5100 M28"}, \
-	{0x1002, 0x5d4a, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon X800 M28"}, \
-	{0x1002, 0x5d4c, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850"}, \
-	{0x1002, 0x5d4d, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850 XT PE"}, \
-	{0x1002, 0x5d4e, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850 SE"}, \
-	{0x1002, 0x5d4f, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850 Pro"}, \
-	{0x1002, 0x5d50, CHIP_R420|RADEON_NEW_MEMMAP, "ATI unknown Radeon / FireGL R480"}, \
-	{0x1002, 0x5d52, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850 XT"}, \
-	{0x1002, 0x5d57, CHIP_R420|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800 XT"}, \
+	{0x1002, 0x5d48, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon X800 XT M28"}, \
+	{0x1002, 0x5d49, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL V5100 M28"}, \
+	{0x1002, 0x5d4a, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon X800 M28"}, \
+	{0x1002, 0x5d4c, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850"}, \
+	{0x1002, 0x5d4d, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850 XT PE"}, \
+	{0x1002, 0x5d4e, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850 SE"}, \
+	{0x1002, 0x5d4f, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850 Pro"}, \
+	{0x1002, 0x5d50, CHIP_R423|RADEON_NEW_MEMMAP, "ATI unknown Radeon / FireGL R480"}, \
+	{0x1002, 0x5d52, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R480 X850 XT"}, \
+	{0x1002, 0x5d57, CHIP_R423|RADEON_NEW_MEMMAP, "ATI Radeon R423 X800 XT"}, \
 	{0x1002, 0x5e48, CHIP_RV410|RADEON_NEW_MEMMAP, "ATI FireGL V5000 RV410"}, \
 	{0x1002, 0x5e4a, CHIP_RV410|RADEON_NEW_MEMMAP, "ATI Radeon RV410 X700 XT"}, \
 	{0x1002, 0x5e4b, CHIP_RV410|RADEON_NEW_MEMMAP, "ATI Radeon RV410 X700 Pro"}, \
@@ -205,9 +208,9 @@
 	{0x1002, 0x71D6, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon X1700 XT"}, \
 	{0x1002, 0x71DA, CHIP_RV530|RADEON_NEW_MEMMAP, "ATI FireGL V5200"}, \
 	{0x1002, 0x71DE, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon X1700"}, \
-	{0x1002, 0x7200, CHIP_RV530|RADEON_NEW_MEMMAP, "ATI  Radeon X2300HD"}, \
-	{0x1002, 0x7210, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2300"}, \
-	{0x1002, 0x7211, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2300"}, \
+	{0x1002, 0x7200, CHIP_RV515|RADEON_NEW_MEMMAP, "ATI  Radeon X2300HD"}, \
+	{0x1002, 0x7210, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2300"}, \
+	{0x1002, 0x7211, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2300"}, \
 	{0x1002, 0x7240, CHIP_R580|RADEON_NEW_MEMMAP, "ATI Radeon X1950"}, \
 	{0x1002, 0x7243, CHIP_R580|RADEON_NEW_MEMMAP, "ATI Radeon X1900"}, \
 	{0x1002, 0x7244, CHIP_R580|RADEON_NEW_MEMMAP, "ATI Radeon X1950"}, \
@@ -237,6 +240,125 @@
 	{0x1002, 0x7297, CHIP_RV560|RADEON_NEW_MEMMAP, "ATI RV560"}, \
 	{0x1002, 0x7834, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP, "ATI Radeon RS350 9000/9100 IGP"}, \
 	{0x1002, 0x7835, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Radeon RS350 Mobility IGP"}, \
+	{0x1002, 0x793f, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP, "ATI Radeon X1200"}, \
+	{0x1002, 0x7941, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP, "ATI Radeon X1200"}, \
+	{0x1002, 0x7942, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP, "ATI Radeon X1200"}, \
+	{0x1002, 0x791e, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS690 X1250 IGP"}, \
+	{0x1002, 0x791f, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS690 X1270 IGP"}, \
+	{0x1002, 0x796c, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS740 HD2100 IGP"}, \
+	{0x1002, 0x796d, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS740 HD2100 IGP"}, \
+	{0x1002, 0x796e, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS740 HD2100 IGP"}, \
+	{0x1002, 0x796f, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART, "ATI Radeon RS740 HD2100 IGP"}, \
+	{0x1002, 0x9400, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 XT"}, \
+	{0x1002, 0x9401, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 XT"}, \
+	{0x1002, 0x9402, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 XT"}, \
+	{0x1002, 0x9403, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 Pro"}, \
+	{0x1002, 0x9405, CHIP_R600|RADEON_NEW_MEMMAP, "ATI Radeon HD 2900 GT"}, \
+	{0x1002, 0x940A, CHIP_R600|RADEON_NEW_MEMMAP, "ATI FireGL V8650"}, \
+	{0x1002, 0x940B, CHIP_R600|RADEON_NEW_MEMMAP, "ATI FireGL V8600"}, \
+	{0x1002, 0x940F, CHIP_R600|RADEON_NEW_MEMMAP, "ATI FireGL V7600"}, \
+	{0x1002, 0x94C0, CHIP_RV610|RADEON_NEW_MEMMAP, "RV610"}, \
+	{0x1002, 0x94C1, CHIP_RV610|RADEON_NEW_MEMMAP, "Radeon HD 2400 XT"}, \
+	{0x1002, 0x94C3, CHIP_RV610|RADEON_NEW_MEMMAP, "Radeon HD 2400 Pro"}, \
+	{0x1002, 0x94C4, CHIP_RV610|RADEON_NEW_MEMMAP, "Radeon HD 2400 PRO AGP"}, \
+	{0x1002, 0x94C5, CHIP_RV610|RADEON_NEW_MEMMAP, "FireGL V4000"}, \
+	{0x1002, 0x94C6, CHIP_RV610|RADEON_NEW_MEMMAP, "RV610"}, \
+	{0x1002, 0x94C7, CHIP_RV610|RADEON_NEW_MEMMAP, "ATI Radeon HD 2350"}, \
+	{0x1002, 0x94C8, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2400 XT"}, \
+	{0x1002, 0x94C9, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2400"}, \
+	{0x1002, 0x94CB, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI RADEON E2400"}, \
+	{0x1002, 0x94CC, CHIP_RV610|RADEON_NEW_MEMMAP, "ATI RV610"}, \
+	{0x1002, 0x94CD, CHIP_RV610|RADEON_NEW_MEMMAP, "ATI FireMV 2260"}, \
+	{0x1002, 0x9500, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI RV670"}, \
+	{0x1002, 0x9501, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3870"}, \
+	{0x1002, 0x9504, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3850"}, \
+	{0x1002, 0x9505, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3850"}, \
+	{0x1002, 0x9506, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3850 X2"}, \
+	{0x1002, 0x9507, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI RV670"}, \
+	{0x1002, 0x9508, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3870"}, \
+	{0x1002, 0x9509, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3870 X2"}, \
+	{0x1002, 0x950F, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3870 X2"}, \
+	{0x1002, 0x9511, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI FireGL V7700"}, \
+	{0x1002, 0x9515, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3850"}, \
+	{0x1002, 0x9517, CHIP_RV670|RADEON_NEW_MEMMAP, "ATI Radeon HD3690"}, \
+	{0x1002, 0x9519, CHIP_RV670|RADEON_NEW_MEMMAP, "AMD Firestream 9170"}, \
+	{0x1002, 0x9580, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI RV630"}, \
+	{0x1002, 0x9581, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2600"}, \
+	{0x1002, 0x9583, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 2600 XT"}, \
+	{0x1002, 0x9586, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 XT AGP"}, \
+	{0x1002, 0x9587, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 Pro AGP"}, \
+	{0x1002, 0x9588, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 XT"}, \
+	{0x1002, 0x9589, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 Pro"}, \
+	{0x1002, 0x958A, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Gemini RV630"}, \
+	{0x1002, 0x958B, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Gemini Mobility Radeon HD 2600 XT"}, \
+	{0x1002, 0x958C, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI FireGL V5600"}, \
+	{0x1002, 0x958D, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI FireGL V3600"}, \
+	{0x1002, 0x958E, CHIP_RV630|RADEON_NEW_MEMMAP, "ATI Radeon HD 2600 LE"}, \
+	{0x1002, 0x958F, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL Graphics Processor"}, \
+	{0x1002, 0x95C0, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3470"}, \
+	{0x1002, 0x95C5, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3450"}, \
+	{0x1002, 0x95C6, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3450"}, \
+	{0x1002, 0x95C7, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3430"}, \
+	{0x1002, 0x95C9, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI Radeon HD 3450"}, \
+	{0x1002, 0x95C2, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3430"}, \
+	{0x1002, 0x95C4, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3400 Series"}, \
+	{0x1002, 0x95CC, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI FirePro V3700"}, \
+	{0x1002, 0x95CD, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI FireMV 2450"}, \
+	{0x1002, 0x95CE, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI FireMV 2260"}, \
+	{0x1002, 0x95CF, CHIP_RV620|RADEON_NEW_MEMMAP, "ATI FireMV 2260"}, \
+	{0x1002, 0x9590, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3600 Series"}, \
+	{0x1002, 0x9596, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3650 AGP"}, \
+	{0x1002, 0x9597, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3600 PRO"}, \
+	{0x1002, 0x9598, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3600 XT"}, \
+	{0x1002, 0x9599, CHIP_RV635|RADEON_NEW_MEMMAP, "ATI ATI Radeon HD 3600 PRO"}, \
+	{0x1002, 0x9591, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3650"}, \
+	{0x1002, 0x9593, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 3670"}, \
+	{0x1002, 0x9595, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL V5700"}, \
+	{0x1002, 0x959B, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility FireGL V5725"}, \
+	{0x1002, 0x9610, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon HD 3200 Graphics"}, \
+	{0x1002, 0x9611, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3100 Graphics"}, \
+	{0x1002, 0x9612, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon HD 3200 Graphics"}, \
+	{0x1002, 0x9613, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3100 Graphics"}, \
+	{0x1002, 0x9614, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3300 Graphics"}, \
+	{0x1002, 0x9615, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3200 Graphics"}, \
+	{0x1002, 0x9616, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP, "ATI Radeon 3000 Graphics"}, \
+	{0x1002, 0x9440, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4800 Series"}, \
+	{0x1002, 0x9441, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4870 X2"}, \
+	{0x1002, 0x9442, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4800 Series"}, \
+	{0x1002, 0x944C, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI Radeon 4800 Series"}, \
+	{0x1002, 0x9450, CHIP_RV770|RADEON_NEW_MEMMAP, "AMD FireStream 9270"}, \
+	{0x1002, 0x9452, CHIP_RV770|RADEON_NEW_MEMMAP, "AMD FireStream 9250"}, \
+	{0x1002, 0x9444, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI FirePro V8750 (FireGL)"}, \
+	{0x1002, 0x9446, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI FirePro V7760 (FireGL)"}, \
+	{0x1002, 0x9456, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI FirePro V8700 (FireGL)"}, \
+	{0x1002, 0x944E, CHIP_RV770|RADEON_NEW_MEMMAP, "ATI FirePro RV770"}, \
+	{0x1002, 0x944A, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4850"}, \
+	{0x1002, 0x944B, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4850 X2"}, \
+	{0x1002, 0x945A, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4870"}, \
+	{0x1002, 0x945B, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon M98"}, \
+	{0x1002, 0x946A, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI FirePro M7750"}, \
+	{0x1002, 0x946B, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI M98"}, \
+	{0x1002, 0x947A, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI M98"}, \
+	{0x1002, 0x947B, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI M98"}, \
+	{0x1002, 0x9487, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI Radeon RV730 (AGP)"}, \
+	{0x1002, 0x948F, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI Radeon RV730 (AGP)"}, \
+	{0x1002, 0x9490, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI Radeon HD 4670"}, \
+	{0x1002, 0x9498, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI Radeon HD 4650"}, \
+	{0x1002, 0x9480, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4650"}, \
+	{0x1002, 0x9488, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon HD 4670"}, \
+	{0x1002, 0x9489, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI FirePro M5750"}, \
+	{0x1002, 0x9491, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI RADEON E4600"}, \
+	{0x1002, 0x949C, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI FirePro V7750 (FireGL)"}, \
+	{0x1002, 0x949E, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI FirePro V5700 (FireGL)"}, \
+	{0x1002, 0x949F, CHIP_RV730|RADEON_NEW_MEMMAP, "ATI FirePro V3750 (FireGL)"}, \
+	{0x1002, 0x9540, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon HD 4550"}, \
+	{0x1002, 0x9541, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon RV710"}, \
+	{0x1002, 0x9542, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon RV710"}, \
+	{0x1002, 0x954E, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon RV710"}, \
+	{0x1002, 0x954F, CHIP_RV710|RADEON_NEW_MEMMAP, "ATI Radeon HD 4350"}, \
+	{0x1002, 0x9552, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon 4300 Series"}, \
+	{0x1002, 0x9553, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon 4500 Series"}, \
+	{0x1002, 0x9555, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP, "ATI Mobility Radeon 4500 Series"}, \
 	{0, 0, 0, NULL}
 
 #define r128_PCI_IDS \
@@ -394,6 +516,7 @@
 	{0x8086, 0x3582, CHIP_I8XX, "Intel i852GM/i855GM GMCH"}, \
 	{0x8086, 0x2572, CHIP_I8XX, "Intel i865G GMCH"}, \
 	{0x8086, 0x2582, CHIP_I9XX|CHIP_I915, "Intel i915G"}, \
+	{0x8086, 0x258a, CHIP_I9XX|CHIP_I915, "Intel E7221 (i915)"}, \
 	{0x8086, 0x2592, CHIP_I9XX|CHIP_I915, "Intel i915GM"}, \
 	{0x8086, 0x2772, CHIP_I9XX|CHIP_I915, "Intel i945G"}, \
 	{0x8086, 0x27A2, CHIP_I9XX|CHIP_I915, "Intel i945GM"}, \
@@ -407,6 +530,10 @@
 	{0x8086, 0x29C2, CHIP_I9XX|CHIP_I915, "Intel G33"}, \
 	{0x8086, 0x29B2, CHIP_I9XX|CHIP_I915, "Intel Q35"}, \
 	{0x8086, 0x29D2, CHIP_I9XX|CHIP_I915, "Intel Q33"}, \
+	{0x8086, 0x2A42, CHIP_I9XX|CHIP_I965, "Mobile Intel® GM45 Express Chipset"}, \
+	{0x8086, 0x2E02, CHIP_I9XX|CHIP_I965, "Intel Integrated Graphics Device"}, \
+	{0x8086, 0x2E12, CHIP_I9XX|CHIP_I965, "Intel Q45/Q43"}, \
+	{0x8086, 0x2E22, CHIP_I9XX|CHIP_I965, "Intel G45/G43"}, \
 	{0, 0, 0, NULL}
 
 #define imagine_PCI_IDS \
diff --git a/sys/dev/drm/drm_sarea.h b/sys/dev/drm/drm_sarea.h
index 254c0bd18e..b2ffc05f8b 100644
--- a/sys/dev/drm/drm_sarea.h
+++ b/sys/dev/drm/drm_sarea.h
@@ -5,7 +5,7 @@
  * \author Michel D�zer <michel@daenzer.net>
  */
 
-/*
+/*-
  * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
  *
@@ -27,14 +27,12 @@
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/drm_sarea.h,v 1.3 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef _DRM_SAREA_H_
 #define _DRM_SAREA_H_
 
-#include "drm.h"
+#include "dev/drm/drm.h"
 
 /* SAREA area needs to be at least a page */
 #if defined(__alpha__)
diff --git a/sys/dev/drm/drm_scatter.c b/sys/dev/drm/drm_scatter.c
index bc46a6c6e1..34a2bcc6b6 100644
--- a/sys/dev/drm/drm_scatter.c
+++ b/sys/dev/drm/drm_scatter.c
@@ -25,7 +25,6 @@
  *   Gareth Hughes <gareth@valinux.com>
  *   Eric Anholt <anholt@FreeBSD.org>
  *
- * $DragonFly: src/sys/dev/drm/drm_scatter.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_scatter.c
@@ -35,54 +34,85 @@
  * by drm_ati_pcigart_init().
  */
 
-#include "drmP.h"
+#include "dev/drm/drmP.h"
 
-#define DEBUG_SCATTER 0
+static void drm_sg_alloc_cb(void *arg, bus_dma_segment_t *segs,
+			    int nsegs, int error);
 
-void drm_sg_cleanup(drm_sg_mem_t *entry)
+int
+drm_sg_alloc(struct drm_device *dev, struct drm_scatter_gather *request)
 {
-	free((void *)entry->handle, M_DRM);
-	free(entry->busaddr, M_DRM);
-	free(entry, M_DRM);
-}
-
-int drm_sg_alloc(drm_device_t * dev, drm_scatter_gather_t * request)
-{
-	drm_sg_mem_t *entry;
+	struct drm_sg_mem *entry;
+	struct drm_dma_handle *dmah;
 	unsigned long pages;
-	int i;
+	int ret;
 
-	if ( dev->sg )
+	if (dev->sg)
 		return EINVAL;
 
-	entry = malloc(sizeof(*entry), M_DRM, M_WAITOK | M_ZERO);
-	if ( !entry )
+	entry = malloc(sizeof(*entry), DRM_MEM_SGLISTS, M_WAITOK | M_ZERO);
+	if (!entry)
 		return ENOMEM;
 
 	pages = round_page(request->size) / PAGE_SIZE;
-	DRM_DEBUG( "sg size=%ld pages=%ld\n", request->size, pages );
+	DRM_DEBUG("sg size=%ld pages=%ld\n", request->size, pages);
 
 	entry->pages = pages;
 
-	entry->busaddr = malloc(pages * sizeof(*entry->busaddr), M_DRM,
+	entry->busaddr = malloc(pages * sizeof(*entry->busaddr), DRM_MEM_PAGES,
 	    M_WAITOK | M_ZERO);
-	if ( !entry->busaddr ) {
-		drm_sg_cleanup(entry);
+	if (!entry->busaddr) {
+		free(entry, DRM_MEM_SGLISTS);
 		return ENOMEM;
 	}
 
-	entry->handle = (long)malloc(pages << PAGE_SHIFT, M_DRM,
-	    M_WAITOK | M_ZERO);
-	if (entry->handle == 0) {
-		drm_sg_cleanup(entry);
+	dmah = malloc(sizeof(struct drm_dma_handle), DRM_MEM_DMA,
+	    M_ZERO | M_NOWAIT);
+	if (dmah == NULL) {
+		free(entry->busaddr, DRM_MEM_PAGES);
+		free(entry, DRM_MEM_SGLISTS);
+		return ENOMEM;
+	}
+
+	ret = bus_dma_tag_create(NULL, PAGE_SIZE, 0, /* tag, align, boundary */
+	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, /* lowaddr, highaddr */
+	    NULL, NULL, /* filtfunc, filtfuncargs */
+	    request->size, pages, /* maxsize, nsegs */
+	    PAGE_SIZE, 0, /* maxsegsize, flags */
+	    &dmah->tag);
+	if (ret != 0) {
+		free(dmah, DRM_MEM_DMA);
+		free(entry->busaddr, DRM_MEM_PAGES);
+		free(entry, DRM_MEM_SGLISTS);
+		return ENOMEM;
+	}
+
+	/* XXX BUS_DMA_NOCACHE */
+	ret = bus_dmamem_alloc(dmah->tag, &dmah->vaddr,
+	    BUS_DMA_WAITOK | BUS_DMA_ZERO , &dmah->map);
+	if (ret != 0) {
+		bus_dma_tag_destroy(dmah->tag);
+		free(dmah, DRM_MEM_DMA);
+		free(entry->busaddr, DRM_MEM_PAGES);
+		free(entry, DRM_MEM_SGLISTS);
 		return ENOMEM;
 	}
 
-	for (i = 0; i < pages; i++) {
-		entry->busaddr[i] = vtophys(entry->handle + i * PAGE_SIZE);
+	ret = bus_dmamap_load(dmah->tag, dmah->map, dmah->vaddr,
+	    request->size, drm_sg_alloc_cb, entry, BUS_DMA_NOWAIT);
+	if (ret != 0) {
+		bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
+		bus_dma_tag_destroy(dmah->tag);
+		free(dmah, DRM_MEM_DMA);
+		free(entry->busaddr, DRM_MEM_PAGES);
+		free(entry, DRM_MEM_SGLISTS);
+		return ENOMEM;
 	}
 
-	DRM_DEBUG( "sg alloc handle  = %08lx\n", entry->handle );
+	entry->dmah = dmah;
+	entry->handle = (unsigned long)dmah->vaddr;
+	
+	DRM_DEBUG("sg alloc handle  = %08lx\n", entry->handle);
 
 	entry->virtual = (void *)entry->handle;
 	request->handle = entry->handle;
@@ -99,31 +129,59 @@ int drm_sg_alloc(drm_device_t * dev, drm_scatter_gather_t * request)
 	return 0;
 }
 
-int drm_sg_alloc_ioctl(drm_device_t *dev, void *data, struct drm_file *file_priv)
+static void
+drm_sg_alloc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 {
-	drm_scatter_gather_t *request = data;
-	int ret;
+	struct drm_sg_mem *entry = arg;
+	int i;
 
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
+	if (error != 0)
+	    return;
+
+	for(i = 0 ; i < nsegs ; i++) {
+		entry->busaddr[i] = segs[i].ds_addr;
+	}
+}
 
-	ret = drm_sg_alloc(dev, request);
-	return ret;
+int
+drm_sg_alloc_ioctl(struct drm_device *dev, void *data,
+		   struct drm_file *file_priv)
+{
+	struct drm_scatter_gather *request = data;
+
+	DRM_DEBUG("\n");
+
+	return drm_sg_alloc(dev, request);
+}
+
+void
+drm_sg_cleanup(struct drm_sg_mem *entry)
+{
+	struct drm_dma_handle *dmah = entry->dmah;
+
+	bus_dmamap_unload(dmah->tag, dmah->map);
+	bus_dmamem_free(dmah->tag, dmah->vaddr, dmah->map);
+	bus_dma_tag_destroy(dmah->tag);
+	free(dmah, DRM_MEM_DMA);
+	free(entry->busaddr, DRM_MEM_PAGES);
+	free(entry, DRM_MEM_SGLISTS);
 }
 
-int drm_sg_free(drm_device_t *dev, void *data, struct drm_file *file_priv)
+int
+drm_sg_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
-	drm_scatter_gather_t *request = data;
-	drm_sg_mem_t *entry;
+	struct drm_scatter_gather *request = data;
+	struct drm_sg_mem *entry;
 
 	DRM_LOCK();
 	entry = dev->sg;
 	dev->sg = NULL;
 	DRM_UNLOCK();
 
-	if ( !entry || entry->handle != request->handle )
+	if (!entry || entry->handle != request->handle)
 		return EINVAL;
 
-	DRM_DEBUG( "sg free virtual  = 0x%lx\n", entry->handle );
+	DRM_DEBUG("sg free virtual = 0x%lx\n", entry->handle);
 
 	drm_sg_cleanup(entry);
 
diff --git a/sys/dev/drm/drm_sysctl.c b/sys/dev/drm/drm_sysctl.c
index 76ec514b2f..4f4aeb1f1c 100644
--- a/sys/dev/drm/drm_sysctl.c
+++ b/sys/dev/drm/drm_sysctl.c
@@ -19,8 +19,6 @@
  * ERIC ANHOLT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/drm_sysctl.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_sysctl.c
@@ -28,8 +26,8 @@
  * debug information.
  */
 
-#include "drmP.h"
-#include "drm.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
 
 #include <sys/sysctl.h>
 
@@ -54,14 +52,14 @@ struct drm_sysctl_info {
 	char		       name[2];
 };
 
-int drm_sysctl_init(drm_device_t *dev)
+int drm_sysctl_init(struct drm_device *dev)
 {
 	struct drm_sysctl_info *info;
 	struct sysctl_oid *oid;
 	struct sysctl_oid *top, *drioid;
 	int		  i;
 
-	info = malloc(sizeof *info, M_DRM, M_WAITOK | M_ZERO);
+	info = malloc(sizeof *info, DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
 	if ( !info )
 		return 1;
 	dev->sysctl = info;
@@ -108,12 +106,12 @@ int drm_sysctl_init(drm_device_t *dev)
 	return 0;
 }
 
-int drm_sysctl_cleanup(drm_device_t *dev)
+int drm_sysctl_cleanup(struct drm_device *dev)
 {
 	int error;
 	error = sysctl_ctx_free( &dev->sysctl->ctx );
 
-	free(dev->sysctl, M_DRM);
+	free(dev->sysctl, DRM_MEM_DRIVER);
 	dev->sysctl = NULL;
 
 	return error;
@@ -129,12 +127,12 @@ do {								\
 
 static int drm_name_info DRM_SYSCTL_HANDLER_ARGS
 {
-	drm_device_t *dev = arg1;
+	struct drm_device *dev = arg1;
 	char buf[128];
 	int retcode;
 	int hasunique = 0;
 
-	DRM_SYSCTL_PRINT("%s 0x%x", dev->driver.name, dev2udev(dev->devnode));
+	DRM_SYSCTL_PRINT("%s 0x%x", dev->driver->name, dev2udev(dev->devnode));
 	
 	DRM_LOCK();
 	if (dev->unique) {
@@ -154,7 +152,7 @@ done:
 
 static int drm_vm_info DRM_SYSCTL_HANDLER_ARGS
 {
-	drm_device_t *dev = arg1;
+	struct drm_device *dev = arg1;
 	drm_local_map_t *map, *tempmaps;
 	const char   *types[] = { "FB", "REG", "SHM", "AGP", "SG" };
 	const char *type, *yesno;
@@ -171,7 +169,8 @@ static int drm_vm_info DRM_SYSCTL_HANDLER_ARGS
 	TAILQ_FOREACH(map, &dev->maplist, link)
 		mapcount++;
 
-	tempmaps = malloc(sizeof(drm_local_map_t) * mapcount, M_DRM, M_NOWAIT);
+	tempmaps = malloc(sizeof(drm_local_map_t) * mapcount, DRM_MEM_DRIVER,
+	    M_NOWAIT);
 	if (tempmaps == NULL) {
 		DRM_UNLOCK();
 		return ENOMEM;
@@ -183,8 +182,8 @@ static int drm_vm_info DRM_SYSCTL_HANDLER_ARGS
 
 	DRM_UNLOCK();
 
-	DRM_SYSCTL_PRINT("\nslot	 offset	      size type flags	 "
-			 "address mtrr\n");
+	DRM_SYSCTL_PRINT("\nslot offset	        size       "
+	    "type flags address            mtrr\n");
 
 	for (i = 0; i < mapcount; i++) {
 		map = &tempmaps[i];
@@ -200,20 +199,20 @@ static int drm_vm_info DRM_SYSCTL_HANDLER_ARGS
 			yesno = "yes";
 
 		DRM_SYSCTL_PRINT(
-		    "%4d 0x%08lx 0x%08lx %4.4s  0x%02x 0x%08lx %s\n", i,
+		    "%4d 0x%016lx 0x%08lx %4.4s  0x%02x 0x%016lx %s\n", i,
 		    map->offset, map->size, type, map->flags,
 		    (unsigned long)map->handle, yesno);
 	}
 	SYSCTL_OUT(req, "", 1);
 
 done:
-	free(tempmaps, M_DRM);
+	free(tempmaps, DRM_MEM_DRIVER);
 	return retcode;
 }
 
 static int drm_bufs_info DRM_SYSCTL_HANDLER_ARGS
 {
-	drm_device_t	 *dev = arg1;
+	struct drm_device	 *dev = arg1;
 	drm_device_dma_t *dma = dev->dma;
 	drm_device_dma_t tempdma;
 	int *templists;
@@ -231,7 +230,8 @@ static int drm_bufs_info DRM_SYSCTL_HANDLER_ARGS
 	}
 	DRM_SPINLOCK(&dev->dma_lock);
 	tempdma = *dma;
-	templists = malloc(sizeof(int) * dma->buf_count, M_DRM, M_NOWAIT);
+	templists = malloc(sizeof(int) * dma->buf_count, DRM_MEM_DRIVER,
+	    M_NOWAIT);
 	for (i = 0; i < dma->buf_count; i++)
 		templists[i] = dma->buflist[i]->list;
 	dma = &tempdma;
@@ -263,14 +263,14 @@ static int drm_bufs_info DRM_SYSCTL_HANDLER_ARGS
 
 	SYSCTL_OUT(req, "", 1);
 done:
-	free(templists, M_DRM);
+	free(templists, DRM_MEM_DRIVER);
 	return retcode;
 }
 
 static int drm_clients_info DRM_SYSCTL_HANDLER_ARGS
 {
-	drm_device_t *dev = arg1;
-	drm_file_t *priv, *tempprivs;
+	struct drm_device *dev = arg1;
+	struct drm_file *priv, *tempprivs;
 	char buf[128];
 	int retcode;
 	int privcount, i;
@@ -281,7 +281,8 @@ static int drm_clients_info DRM_SYSCTL_HANDLER_ARGS
 	TAILQ_FOREACH(priv, &dev->files, link)
 		privcount++;
 
-	tempprivs = malloc(sizeof(drm_file_t) * privcount, M_DRM, M_NOWAIT);
+	tempprivs = malloc(sizeof(struct drm_file) * privcount, DRM_MEM_DRIVER,
+	    M_NOWAIT);
 	if (tempprivs == NULL) {
 		DRM_UNLOCK();
 		return ENOMEM;
@@ -306,6 +307,6 @@ static int drm_clients_info DRM_SYSCTL_HANDLER_ARGS
 
 	SYSCTL_OUT(req, "", 1);
 done:
-	free(tempprivs, M_DRM);
+	free(tempprivs, DRM_MEM_DRIVER);
 	return retcode;
 }
diff --git a/sys/dev/drm/drm_vm.c b/sys/dev/drm/drm_vm.c
index fc581e19b7..1cbc313b62 100644
--- a/sys/dev/drm/drm_vm.c
+++ b/sys/dev/drm/drm_vm.c
@@ -19,55 +19,38 @@
  * ERIC ANHOLT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/drm_vm.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /** @file drm_vm.c
  * Support code for mmaping of DRM maps.
  */
 
-#include "drmP.h"
-#include "drm.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
 
-#if defined(__FreeBSD__) && __FreeBSD_version >= 500102
-int drm_mmap(struct cdev *kdev, vm_offset_t offset, vm_paddr_t *paddr,
-    int prot)
-#elif defined(__FreeBSD__)
-int drm_mmap(dev_t kdev, vm_offset_t offset, int prot)
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-paddr_t drm_mmap(dev_t kdev, off_t offset, int prot)
-#endif
-#ifdef __DragonFly__
 int drm_mmap(struct dev_mmap_args *ap)
 {
 	struct cdev *kdev = ap->a_head.a_dev;
 	vm_offset_t offset = ap->a_offset;
-#else
-{
-#endif
-	drm_device_t *dev = drm_get_device_from_kdev(kdev);
+	struct drm_device *dev = drm_get_device_from_kdev(kdev);
+	struct drm_file *file_priv = NULL;
 	drm_local_map_t *map;
-	drm_file_t *priv;
-	drm_map_type_t type;
-#if defined(__FreeBSD__) || defined(__DragonFly__)
+	enum drm_map_type type;
 	vm_paddr_t phys;
-#else
-	paddr_t phys;
-#endif
 
-	DRM_LOCK();
-	priv = drm_find_file_by_proc(dev, DRM_CURPROC);
-	DRM_UNLOCK();
-	if (priv == NULL) {
-		DRM_ERROR("can't find authenticator\n");
-		return EINVAL;
-	}
+        DRM_LOCK();
+        file_priv = drm_find_file_by_proc(dev, DRM_CURPROC);
+        DRM_UNLOCK();
+
+        if (file_priv == NULL) {
+                DRM_ERROR("can't find authenticator\n");
+                return EINVAL;
+        }
 
-	if (!priv->authenticated)
-		return EACCES;
+        if (!file_priv->authenticated)
+                return EACCES;
 
-	if (dev->dma && offset >= 0 && offset < ptoa(dev->dma->page_count)) {
+	if (dev->dma && offset < ptoa(dev->dma->page_count)) {
 		drm_device_dma_t *dma = dev->dma;
 
 		DRM_SPINLOCK(&dev->dma_lock);
@@ -75,23 +58,13 @@ int drm_mmap(struct dev_mmap_args *ap)
 		if (dma->pagelist != NULL) {
 			unsigned long page = offset >> PAGE_SHIFT;
 			unsigned long phys = dma->pagelist[page];
-
-#if defined(__FreeBSD__) && __FreeBSD_version >= 500102
-			*paddr = phys;
-			DRM_SPINUNLOCK(&dev->dma_lock);
-			return 0;
-#elif defined(__DragonFly__)
 			ap->a_result = atop(phys);
 			DRM_SPINUNLOCK(&dev->dma_lock);
-			return (0);
-#else
-			return atop(phys);
-#endif
+			return 0;
 		} else {
 			DRM_SPINUNLOCK(&dev->dma_lock);
 			return -1;
 		}
-		DRM_SPINUNLOCK(&dev->dma_lock);
 	}
 
 				/* A sequential search of a linked list is
@@ -108,8 +81,14 @@ int drm_mmap(struct dev_mmap_args *ap)
 	}
 
 	if (map == NULL) {
+		DRM_DEBUG("Can't find map, requested offset = %016lx\n",
+		    (unsigned long)offset);
+		TAILQ_FOREACH(map, &dev->maplist, link) {
+			DRM_DEBUG("map offset = %016lx, handle = %016lx\n",
+			    (unsigned long)map->offset,
+			    (unsigned long)map->handle);
+		}
 		DRM_UNLOCK();
-		DRM_DEBUG("can't find map\n");
 		return -1;
 	}
 	if (((map->flags&_DRM_RESTRICTED) && !DRM_SUSER(DRM_CURPROC))) {
@@ -138,14 +117,7 @@ int drm_mmap(struct dev_mmap_args *ap)
 		return -1;	/* This should never happen. */
 	}
 
-#if defined(__FreeBSD__) && __FreeBSD_version >= 500102
-	*paddr = phys;
-	return 0;
-#elif defined(__DragonFly__)
 	ap->a_result = atop(phys);
-	return (0);
-#else
-	return atop(phys);
-#endif
+	return 0;
 }
 
diff --git a/sys/dev/drm/i915/Makefile b/sys/dev/drm/i915/Makefile
index 36a2f5e314..6a25e1c0df 100644
--- a/sys/dev/drm/i915/Makefile
+++ b/sys/dev/drm/i915/Makefile
@@ -4,7 +4,7 @@
 KMOD	= i915
 KMODDEPS= drm
 NO_MAN	= YES
-SRCS    = i915_dma.c i915_drv.c i915_irq.c i915_mem.c
+SRCS    = i915_dma.c i915_drv.c i915_irq.c i915_mem.c i915_suspend.c
 SRCS   += device_if.h bus_if.h pci_if.h opt_drm.h
 CFLAGS += ${DEBUG_FLAGS} -I. -I..
 
diff --git a/sys/dev/drm/i915_dma.c b/sys/dev/drm/i915_dma.c
index bc82c1589b..667768d2f2 100644
--- a/sys/dev/drm/i915_dma.c
+++ b/sys/dev/drm/i915_dma.c
@@ -1,6 +1,6 @@
 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  */
-/*
+/*-
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
  *
@@ -24,13 +24,12 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * $DragonFly: src/sys/dev/drm/i915_dma.c,v 1.2 2008/10/27 03:42:33 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "i915_drm.h"
-#include "i915_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/i915_drm.h"
+#include "dev/drm/i915_drv.h"
 
 /* Really want an OS-independent resettable timer.  Would like to have
  * this loop run for (eg) 3 sec, but have the timer reset every time
@@ -41,37 +40,99 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
-	u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+	u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
+	u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
+	u32 last_acthd = I915_READ(acthd_reg);
+	u32 acthd;
 	int i;
 
-	for (i = 0; i < 10000; i++) {
-		ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
+	for (i = 0; i < 100000; i++) {
+		ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
+		acthd = I915_READ(acthd_reg);
 		ring->space = ring->head - (ring->tail + 8);
 		if (ring->space < 0)
 			ring->space += ring->Size;
 		if (ring->space >= n)
 			return 0;
 
+		if (dev_priv->sarea_priv)
+			dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
+
 		if (ring->head != last_head)
 			i = 0;
 
+		if (acthd != last_acthd)
+			i = 0;
+
 		last_head = ring->head;
-		DRM_UDELAY(1);
+		last_acthd = acthd;
+		DRM_UDELAY(10 * 1000);
 	}
 
 	return -EBUSY;
 }
 
+/**
+ * Sets up the hardware status page for devices that need a physical address
+ * in the register.
+ */
+static int i915_init_phys_hws(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+
+	/* Program Hardware Status Page */
+	DRM_UNLOCK();
+	dev_priv->status_page_dmah =
+		drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
+	DRM_LOCK();
+	if (!dev_priv->status_page_dmah) {
+		DRM_ERROR("Can not allocate hardware status page\n");
+		return -ENOMEM;
+	}
+	dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
+	dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
+
+	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+
+	I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
+	DRM_DEBUG("Enabled hardware status page\n");
+	return 0;
+}
+
+/**
+ * Frees the hardware status page, whether it's a physical address or a virtual
+ * address set up by the X Server.
+ */
+static void i915_free_hws(struct drm_device *dev)
+{
+	drm_i915_private_t *dev_priv = dev->dev_private;
+	if (dev_priv->status_page_dmah) {
+		drm_pci_free(dev, dev_priv->status_page_dmah);
+		dev_priv->status_page_dmah = NULL;
+	}
+
+	if (dev_priv->status_gfx_addr) {
+		dev_priv->status_gfx_addr = 0;
+		drm_core_ioremapfree(&dev_priv->hws_map, dev);
+	}
+
+	/* Need to rewrite hardware status page */
+	I915_WRITE(HWS_PGA, 0x1ffff000);
+}
+
 void i915_kernel_lost_context(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
 
-	ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-	ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
+	ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
+	ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 	ring->space = ring->head - (ring->tail + 8);
 	if (ring->space < 0)
 		ring->space += ring->Size;
+
+	if (ring->head == ring->tail && dev_priv->sarea_priv)
+		dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 }
 
 static int i915_dma_cleanup(struct drm_device * dev)
@@ -81,28 +142,19 @@ static int i915_dma_cleanup(struct drm_device * dev)
 	 * may not have been called from userspace and after dev_private
 	 * is freed, it's too late.
 	 */
-	if (dev->irq)
+	if (dev->irq_enabled)
 		drm_irq_uninstall(dev);
 
 	if (dev_priv->ring.virtual_start) {
 		drm_core_ioremapfree(&dev_priv->ring.map, dev);
-		dev_priv->ring.virtual_start = 0;
-		dev_priv->ring.map.handle = 0;
+		dev_priv->ring.virtual_start = NULL;
+		dev_priv->ring.map.handle = NULL;
 		dev_priv->ring.map.size = 0;
 	}
 
-	if (dev_priv->status_page_dmah) {
-		drm_pci_free(dev, dev_priv->status_page_dmah);
-		dev_priv->status_page_dmah = NULL;
-		/* Need to rewrite hardware status page */
-		I915_WRITE(0x02080, 0x1ffff000);
-	}
-
-	if (dev_priv->status_gfx_addr) {
-		dev_priv->status_gfx_addr = 0;
-		drm_core_ioremapfree(&dev_priv->hws_map, dev);
-		I915_WRITE(0x02080, 0x1ffff000);
-	}
+	/* Clear the HWS virtual address at teardown */
+	if (I915_NEED_GFX_HWS(dev))
+		i915_free_hws(dev);
 
 	return 0;
 }
@@ -118,81 +170,48 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 		return -EINVAL;
 	}
 
-	dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
-	if (!dev_priv->mmio_map) {
-		i915_dma_cleanup(dev);
-		DRM_ERROR("can not find mmio map!\n");
-		return -EINVAL;
-	}
-
-#ifdef I915_HAVE_BUFFER
-	dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
-#endif
-
 	dev_priv->sarea_priv = (drm_i915_sarea_t *)
 	    ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 
-	dev_priv->ring.Start = init->ring_start;
-	dev_priv->ring.End = init->ring_end;
-	dev_priv->ring.Size = init->ring_size;
-	dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
+	if (init->ring_size != 0) {
+		if (dev_priv->ring.ring_obj != NULL) {
+			i915_dma_cleanup(dev);
+			DRM_ERROR("Client tried to initialize ringbuffer in "
+				  "GEM mode\n");
+			return -EINVAL;
+		}
 
-	dev_priv->ring.map.offset = init->ring_start;
-	dev_priv->ring.map.size = init->ring_size;
-	dev_priv->ring.map.type = 0;
-	dev_priv->ring.map.flags = 0;
-	dev_priv->ring.map.mtrr = 0;
+		dev_priv->ring.Size = init->ring_size;
+		dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 
-	drm_core_ioremap(&dev_priv->ring.map, dev);
+		dev_priv->ring.map.offset = init->ring_start;
+		dev_priv->ring.map.size = init->ring_size;
+		dev_priv->ring.map.type = 0;
+		dev_priv->ring.map.flags = 0;
+		dev_priv->ring.map.mtrr = 0;
 
-	if (dev_priv->ring.map.handle == NULL) {
-		i915_dma_cleanup(dev);
-		DRM_ERROR("can not ioremap virtual address for"
-			  " ring buffer\n");
-		return -ENOMEM;
+		drm_core_ioremap_wc(&dev_priv->ring.map, dev);
+
+		if (dev_priv->ring.map.handle == NULL) {
+			i915_dma_cleanup(dev);
+			DRM_ERROR("can not ioremap virtual address for"
+				  " ring buffer\n");
+			return -ENOMEM;
+		}
 	}
 
 	dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 
 	dev_priv->cpp = init->cpp;
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->front_offset = init->front_offset;
+	dev_priv->current_page = 0;
 	dev_priv->sarea_priv->pf_current_page = 0;
 
-	/* We are using separate values as placeholders for mechanisms for
-	 * private backbuffer/depthbuffer usage.
-	 */
-	dev_priv->use_mi_batchbuffer_start = 0;
-	if (IS_I965G(dev)) /* 965 doesn't support older method */
-		dev_priv->use_mi_batchbuffer_start = 1;
-
 	/* Allow hardware batchbuffers unless told otherwise.
 	 */
 	dev_priv->allow_batchbuffer = 1;
 
-	/* Enable vblank on pipe A for older X servers
-	 */
-	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
-
-	/* Program Hardware Status Page */
-	if (!IS_G33(dev)) {
-		dev_priv->status_page_dmah =
-			drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
-
-		if (!dev_priv->status_page_dmah) {
-			i915_dma_cleanup(dev);
-			DRM_ERROR("Can not allocate hardware status page\n");
-			return -ENOMEM;
-		}
-		dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
-		dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
-
-		memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
-
-		I915_WRITE(0x02080, dev_priv->dma_status_page);
-	}
-	DRM_DEBUG("Enabled hardware status page\n");
-#ifdef I915_HAVE_BUFFER
-	mutex_init(&dev_priv->cmdbuf_mutex);
-#endif
 	return 0;
 }
 
@@ -207,11 +226,6 @@ static int i915_dma_resume(struct drm_device * dev)
 		return -EINVAL;
 	}
 
-	if (!dev_priv->mmio_map) {
-		DRM_ERROR("can not find mmio map!\n");
-		return -EINVAL;
-	}
-
 	if (dev_priv->ring.map.handle == NULL) {
 		DRM_ERROR("can not ioremap virtual address for"
 			  " ring buffer\n");
@@ -226,9 +240,9 @@ static int i915_dma_resume(struct drm_device * dev)
 	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 
 	if (dev_priv->status_gfx_addr != 0)
-		I915_WRITE(0x02080, dev_priv->status_gfx_addr);
+		I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 	else
-		I915_WRITE(0x02080, dev_priv->dma_status_page);
+		I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 	DRM_DEBUG("Enabled hardware status page\n");
 
 	return 0;
@@ -374,9 +388,9 @@ static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 	return 0;
 }
 
-static int i915_emit_box(struct drm_device * dev,
-			 struct drm_clip_rect __user * boxes,
-			 int i, int DR1, int DR4)
+int i915_emit_box(struct drm_device * dev,
+		  struct drm_clip_rect __user * boxes,
+		  int i, int DR1, int DR4)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	struct drm_clip_rect box;
@@ -417,54 +431,27 @@ static int i915_emit_box(struct drm_device * dev,
  * emit. For now, do it in both places:
  */
 
-void i915_emit_breadcrumb(struct drm_device *dev)
+static void i915_emit_breadcrumb(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;
 
-	if (++dev_priv->counter > BREADCRUMB_MASK) {
-		 dev_priv->counter = 1;
-		 DRM_DEBUG("Breadcrumb counter wrapped around\n");
-	}
-
-	dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
+	if (++dev_priv->counter > 0x7FFFFFFFUL)
+		dev_priv->counter = 0;
+	if (dev_priv->sarea_priv)
+		dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 
 	BEGIN_LP_RING(4);
-	OUT_RING(CMD_STORE_DWORD_IDX);
-	OUT_RING(20);
+	OUT_RING(MI_STORE_DWORD_INDEX);
+	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 	OUT_RING(dev_priv->counter);
 	OUT_RING(0);
 	ADVANCE_LP_RING();
 }
 
-
-int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
-{
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	uint32_t flush_cmd = CMD_MI_FLUSH;
-	RING_LOCALS;
-
-	flush_cmd |= flush;
-
-	i915_kernel_lost_context(dev);
-
-	BEGIN_LP_RING(4);
-	OUT_RING(flush_cmd);
-	OUT_RING(0);
-	OUT_RING(0);
-	OUT_RING(0);
-	ADVANCE_LP_RING();
-
-	return 0;
-}
-
-
 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 				   drm_i915_cmdbuffer_t * cmd)
 {
-#ifdef I915_HAVE_FENCE
-	drm_i915_private_t *dev_priv = dev->dev_private;
-#endif
 	int nbox = cmd->num_cliprects;
 	int i = 0, count, ret;
 
@@ -491,9 +478,6 @@ static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 	}
 
 	i915_emit_breadcrumb(dev);
-#ifdef I915_HAVE_FENCE
-	drm_fence_flush_old(dev, 0, dev_priv->counter);
-#endif
 	return 0;
 }
 
@@ -523,7 +507,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
 				return ret;
 		}
 
-		if (dev_priv->use_mi_batchbuffer_start) {
+		if (!IS_I830(dev) && !IS_845G(dev)) {
 			BEGIN_LP_RING(2);
 			if (IS_I965G(dev)) {
 				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
@@ -533,7 +517,6 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
 				OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 			}
 			ADVANCE_LP_RING();
-
 		} else {
 			BEGIN_LP_RING(4);
 			OUT_RING(MI_BATCH_BUFFER);
@@ -545,100 +528,82 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
 	}
 
 	i915_emit_breadcrumb(dev);
-#ifdef I915_HAVE_FENCE
-	drm_fence_flush_old(dev, 0, dev_priv->counter);
-#endif
+
 	return 0;
 }
 
-static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
+static int i915_dispatch_flip(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	u32 num_pages, current_page, next_page, dspbase;
-	int shift = 2 * plane, x, y;
 	RING_LOCALS;
 
-	/* Calculate display base offset */
-	num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
-	current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
-	next_page = (current_page + 1) % num_pages;
+	if (!dev_priv->sarea_priv)
+		return -EINVAL;
 
-	switch (next_page) {
-	default:
-	case 0:
-		dspbase = dev_priv->sarea_priv->front_offset;
-		break;
-	case 1:
-		dspbase = dev_priv->sarea_priv->back_offset;
-		break;
-	case 2:
-		dspbase = dev_priv->sarea_priv->third_offset;
-		break;
-	}
+	DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
+		  __func__,
+		  dev_priv->current_page,
+		  dev_priv->sarea_priv->pf_current_page);
+
+	i915_kernel_lost_context(dev);
 
-	if (plane == 0) {
-		x = dev_priv->sarea_priv->planeA_x;
-		y = dev_priv->sarea_priv->planeA_y;
+	BEGIN_LP_RING(2);
+	OUT_RING(MI_FLUSH | MI_READ_FLUSH);
+	OUT_RING(0);
+	ADVANCE_LP_RING();
+
+	BEGIN_LP_RING(6);
+	OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
+	OUT_RING(0);
+	if (dev_priv->current_page == 0) {
+		OUT_RING(dev_priv->back_offset);
+		dev_priv->current_page = 1;
 	} else {
-		x = dev_priv->sarea_priv->planeB_x;
-		y = dev_priv->sarea_priv->planeB_y;
+		OUT_RING(dev_priv->front_offset);
+		dev_priv->current_page = 0;
 	}
+	OUT_RING(0);
+	ADVANCE_LP_RING();
 
-	dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
+	BEGIN_LP_RING(2);
+	OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
+	OUT_RING(0);
+	ADVANCE_LP_RING();
 
-	DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
-		  dspbase);
+	if (++dev_priv->counter > 0x7FFFFFFFUL)
+		dev_priv->counter = 0;
+	if (dev_priv->sarea_priv)
+		dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 
 	BEGIN_LP_RING(4);
-	OUT_RING(sync ? 0 :
-		 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
-				       MI_WAIT_FOR_PLANE_A_FLIP)));
-	OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
-		 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
-	OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
-	OUT_RING(dspbase);
+	OUT_RING(MI_STORE_DWORD_INDEX);
+	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
+	OUT_RING(dev_priv->counter);
+	OUT_RING(0);
 	ADVANCE_LP_RING();
 
-	dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
-	dev_priv->sarea_priv->pf_current_page |= next_page << shift;
-}
-
-void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
-{
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	int i;
-
-	DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
-		  planes, dev_priv->sarea_priv->pf_current_page);
-
-	i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
-
-	for (i = 0; i < 2; i++)
-		if (planes & (1 << i))
-			i915_do_dispatch_flip(dev, i, sync);
-
-	i915_emit_breadcrumb(dev);
-#ifdef I915_HAVE_FENCE
-	if (!sync)
-		drm_fence_flush_old(dev, 0, dev_priv->counter);
-#endif
+	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
+	return 0;
 }
 
-static int i915_quiescent(struct drm_device *dev)
+static int i915_quiescent(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 
 	i915_kernel_lost_context(dev);
-	return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
+	return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
 }
 
 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 			    struct drm_file *file_priv)
 {
+	int ret;
+
+	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	LOCK_TEST_WITH_RETURN(dev, file_priv);
+	ret = i915_quiescent(dev);
 
-	return i915_quiescent(dev);
+	return ret;
 }
 
 static int i915_batchbuffer(struct drm_device *dev, void *data,
@@ -648,6 +613,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
 	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 	    dev_priv->sarea_priv;
 	drm_i915_batchbuffer_t *batch = data;
+	size_t cliplen;
 	int ret;
 
 	if (!dev_priv->allow_batchbuffer) {
@@ -658,16 +624,30 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
 	DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 		  batch->start, batch->used, batch->num_cliprects);
 
-	LOCK_TEST_WITH_RETURN(dev, file_priv);
+	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
+	DRM_UNLOCK();
+	cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 	if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
-							batch->num_cliprects *
-							sizeof(struct drm_clip_rect)))
+	    cliplen)) {
+		DRM_LOCK();
 		return -EFAULT;
+	}
+	if (batch->num_cliprects) {
+		vslock((caddr_t)batch->cliprects, cliplen);
+	}
+	DRM_LOCK();
 
 	ret = i915_dispatch_batchbuffer(dev, batch);
 
-	sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
+	if (sarea_priv)
+		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
+
+	DRM_UNLOCK();
+	if (batch->num_cliprects)
+		vsunlock((caddr_t)batch->cliprects, cliplen);
+	DRM_LOCK();
+
 	return ret;
 }
 
@@ -678,512 +658,58 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
 	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 	    dev_priv->sarea_priv;
 	drm_i915_cmdbuffer_t *cmdbuf = data;
+	size_t cliplen;
 	int ret;
 
 	DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 		  cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 
-	LOCK_TEST_WITH_RETURN(dev, file_priv);
+	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (cmdbuf->num_cliprects &&
-	    DRM_VERIFYAREA_READ(cmdbuf->cliprects,
-				cmdbuf->num_cliprects *
-				sizeof(struct drm_clip_rect))) {
+	DRM_UNLOCK();
+	cliplen = cmdbuf->num_cliprects * sizeof(struct drm_clip_rect);
+	if (cmdbuf->num_cliprects && DRM_VERIFYAREA_READ(cmdbuf->cliprects,
+	    cliplen)) {
 		DRM_ERROR("Fault accessing cliprects\n");
+		DRM_LOCK();
 		return -EFAULT;
 	}
+	if (cmdbuf->num_cliprects) {
+		vslock((caddr_t)cmdbuf->cliprects, cliplen);
+		vslock((caddr_t)cmdbuf->buf, cmdbuf->sz);
+	}
+	DRM_LOCK();
 
 	ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
+	DRM_UNLOCK();
+	if (cmdbuf->num_cliprects) {
+		vsunlock((caddr_t)cmdbuf->buf, cmdbuf->sz);
+		vsunlock((caddr_t)cmdbuf->cliprects, cliplen);
+	}
+	DRM_LOCK();
 	if (ret) {
 		DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 		return ret;
 	}
 
-	sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
-	return 0;
-}
-
-#if DRM_DEBUG_CODE
-#define DRM_DEBUG_RELOCATION	(drm_debug != 0)
-#else
-#define DRM_DEBUG_RELOCATION	0
-#endif
-
-#ifdef I915_HAVE_BUFFER
-
-struct i915_relocatee_info {
-	struct drm_buffer_object *buf;
-	unsigned long offset;
-	u32 *data_page;
-	unsigned page_offset;
-	struct drm_bo_kmap_obj kmap;
-	int is_iomem;
-};
-
-struct drm_i915_validate_buffer {
-	struct drm_buffer_object *buffer;
-	int presumed_offset_correct;
-};
-
-static void i915_dereference_buffers_locked(struct drm_i915_validate_buffer *buffers,
-					    unsigned num_buffers)
-{
-	while (num_buffers--)
-		drm_bo_usage_deref_locked(&buffers[num_buffers].buffer);
-}
-
-int i915_apply_reloc(struct drm_file *file_priv, int num_buffers,
-		     struct drm_i915_validate_buffer *buffers,
-		     struct i915_relocatee_info *relocatee,
-		     uint32_t *reloc)
-{
-	unsigned index;
-	unsigned long new_cmd_offset;
-	u32 val;
-	int ret;
-
-	if (reloc[2] >= num_buffers) {
-		DRM_ERROR("Illegal relocation buffer %08X\n", reloc[2]);
-		return -EINVAL;
-	}
-
-	/*
-	 * Short-circuit relocations that were correctly
-	 * guessed by the client
-	 */
-	if (buffers[reloc[2]].presumed_offset_correct && !DRM_DEBUG_RELOCATION)
-		return 0;
-
-	new_cmd_offset = reloc[0];
-	if (!relocatee->data_page ||
-	    !drm_bo_same_page(relocatee->offset, new_cmd_offset)) {
-		drm_bo_kunmap(&relocatee->kmap);
-		relocatee->offset = new_cmd_offset;
-		mutex_lock (&relocatee->buf->mutex);
-		ret = drm_bo_wait (relocatee->buf, 0, 0, FALSE);
-		mutex_unlock (&relocatee->buf->mutex);
-		if (ret) {
-			DRM_ERROR("Could not wait for buffer to apply relocs\n %08lx", new_cmd_offset);
-			return ret;
-		}
-		ret = drm_bo_kmap(relocatee->buf, new_cmd_offset >> PAGE_SHIFT,
-				  1, &relocatee->kmap);
-		if (ret) {
-			DRM_ERROR("Could not map command buffer to apply relocs\n %08lx", new_cmd_offset);
-			return ret;
-		}
-
-		relocatee->data_page = drm_bmo_virtual(&relocatee->kmap,
-						       &relocatee->is_iomem);
-		relocatee->page_offset = (relocatee->offset & PAGE_MASK);
-	}
-
-	val = buffers[reloc[2]].buffer->offset;
-	index = (reloc[0] - relocatee->page_offset) >> 2;
-
-	/* add in validate */
-	val = val + reloc[1];
-
-	if (DRM_DEBUG_RELOCATION) {
-		if (buffers[reloc[2]].presumed_offset_correct &&
-		    relocatee->data_page[index] != val) {
-			DRM_DEBUG ("Relocation mismatch source %d target %d buffer %d user %08x kernel %08x\n",
-				   reloc[0], reloc[1], reloc[2], relocatee->data_page[index], val);
-		}
-	}
-	relocatee->data_page[index] = val;
-	return 0;
-}
-
-int i915_process_relocs(struct drm_file *file_priv,
-			uint32_t buf_handle,
-			uint32_t *reloc_buf_handle,
-			struct i915_relocatee_info *relocatee,
-			struct drm_i915_validate_buffer *buffers,
-			uint32_t num_buffers)
-{
-	struct drm_device *dev = file_priv->head->dev;
-	struct drm_buffer_object *reloc_list_object;
-	uint32_t cur_handle = *reloc_buf_handle;
-	uint32_t *reloc_page;
-	int ret, reloc_is_iomem, reloc_stride;
-	uint32_t num_relocs, reloc_offset, reloc_end, reloc_page_offset, next_offset, cur_offset;
-	struct drm_bo_kmap_obj reloc_kmap;
-
-	memset(&reloc_kmap, 0, sizeof(reloc_kmap));
-
-	mutex_lock(&dev->struct_mutex);
-	reloc_list_object = drm_lookup_buffer_object(file_priv, cur_handle, 1);
-	mutex_unlock(&dev->struct_mutex);
-	if (!reloc_list_object)
-		return -EINVAL;
-
-	ret = drm_bo_kmap(reloc_list_object, 0, 1, &reloc_kmap);
-	if (ret) {
-		DRM_ERROR("Could not map relocation buffer.\n");
-		goto out;
-	}
-
-	reloc_page = drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem);
-	num_relocs = reloc_page[0] & 0xffff;
-
-	if ((reloc_page[0] >> 16) & 0xffff) {
-		DRM_ERROR("Unsupported relocation type requested\n");
-		goto out;
-	}
-
-	/* get next relocate buffer handle */
-	*reloc_buf_handle = reloc_page[1];
-	reloc_stride = I915_RELOC0_STRIDE * sizeof(uint32_t); /* may be different for other types of relocs */
-
-	DRM_DEBUG("num relocs is %d, next is %08X\n", num_relocs, reloc_page[1]);
-
-	reloc_page_offset = 0;
-	reloc_offset = I915_RELOC_HEADER * sizeof(uint32_t);
-	reloc_end = reloc_offset + (num_relocs * reloc_stride);
-
-	do {
-		next_offset = drm_bo_offset_end(reloc_offset, reloc_end);
-
-		do {
-			cur_offset = ((reloc_offset + reloc_page_offset) & ~PAGE_MASK) / sizeof(uint32_t);
-			ret = i915_apply_reloc(file_priv, num_buffers,
-					 buffers, relocatee, &reloc_page[cur_offset]);
-			if (ret)
-				goto out;
-
-			reloc_offset += reloc_stride;
-		} while (reloc_offset < next_offset);
-
-		drm_bo_kunmap(&reloc_kmap);
-
-		reloc_offset = next_offset;
-		if (reloc_offset != reloc_end) {
-			ret = drm_bo_kmap(reloc_list_object, reloc_offset >> PAGE_SHIFT, 1, &reloc_kmap);
-			if (ret) {
-				DRM_ERROR("Could not map relocation buffer.\n");
-				goto out;
-			}
-
-			reloc_page = drm_bmo_virtual(&reloc_kmap, &reloc_is_iomem);
-			reloc_page_offset = reloc_offset & ~PAGE_MASK;
-		}
-
-	} while (reloc_offset != reloc_end);
-out:
-	drm_bo_kunmap(&relocatee->kmap);
-	relocatee->data_page = NULL;
-
-	drm_bo_kunmap(&reloc_kmap);
-
-	mutex_lock(&dev->struct_mutex);
-	drm_bo_usage_deref_locked(&reloc_list_object);
-	mutex_unlock(&dev->struct_mutex);
-
-	return ret;
-}
-
-static int i915_exec_reloc(struct drm_file *file_priv, drm_handle_t buf_handle,
-			   drm_handle_t buf_reloc_handle,
-			   struct drm_i915_validate_buffer *buffers,
-			   uint32_t buf_count)
-{
-	struct drm_device *dev = file_priv->head->dev;
-	struct i915_relocatee_info relocatee;
-	int ret = 0;
-	int b;
-
-	/*
-	 * Short circuit relocations when all previous
-	 * buffers offsets were correctly guessed by
-	 * the client
-	 */
-	if (!DRM_DEBUG_RELOCATION) {
-		for (b = 0; b < buf_count; b++)
-			if (!buffers[b].presumed_offset_correct)
-				break;
-	
-		if (b == buf_count)
-			return 0;
-	}
-
-	memset(&relocatee, 0, sizeof(relocatee));
-
-	mutex_lock(&dev->struct_mutex);
-	relocatee.buf = drm_lookup_buffer_object(file_priv, buf_handle, 1);
-	mutex_unlock(&dev->struct_mutex);
-	if (!relocatee.buf) {
-		DRM_DEBUG("relocatee buffer invalid %08x\n", buf_handle);
-		ret = -EINVAL;
-		goto out_err;
-	}
-
-	while (buf_reloc_handle) {
-		ret = i915_process_relocs(file_priv, buf_handle, &buf_reloc_handle, &relocatee, buffers, buf_count);
-		if (ret) {
-			DRM_ERROR("process relocs failed\n");
-			break;
-		}
-	}
-
-	mutex_lock(&dev->struct_mutex);
-	drm_bo_usage_deref_locked(&relocatee.buf);
-	mutex_unlock(&dev->struct_mutex);
-
-out_err:
-	return ret;
-}
-
-/*
- * Validate, add fence and relocate a block of bos from a userspace list
- */
-int i915_validate_buffer_list(struct drm_file *file_priv,
-			      unsigned int fence_class, uint64_t data,
-			      struct drm_i915_validate_buffer *buffers,
-			      uint32_t *num_buffers)
-{
-	struct drm_i915_op_arg arg;
-	struct drm_bo_op_req *req = &arg.d.req;
-	struct drm_bo_arg_rep rep;
-	unsigned long next = 0;
-	int ret = 0;
-	unsigned buf_count = 0;
-	struct drm_device *dev = file_priv->head->dev;
-	uint32_t buf_reloc_handle, buf_handle;
-
-
-	do {
-		if (buf_count >= *num_buffers) {
-			DRM_ERROR("Buffer count exceeded %d\n.", *num_buffers);
-			ret = -EINVAL;
-			goto out_err;
-		}
-
-		buffers[buf_count].buffer = NULL;
-		buffers[buf_count].presumed_offset_correct = 0;
-
-		if (copy_from_user(&arg, (void __user *)(unsigned long)data, sizeof(arg))) {
-			ret = -EFAULT;
-			goto out_err;
-		}
-
-		if (arg.handled) {
-			data = arg.next;
-			mutex_lock(&dev->struct_mutex);
-			buffers[buf_count].buffer = drm_lookup_buffer_object(file_priv, req->arg_handle, 1);
-			mutex_unlock(&dev->struct_mutex);
-			buf_count++;
-			continue;
-		}
-
-		rep.ret = 0;
-		if (req->op != drm_bo_validate) {
-			DRM_ERROR
-			    ("Buffer object operation wasn't \"validate\".\n");
-			rep.ret = -EINVAL;
-			goto out_err;
-		}
-
-		buf_handle = req->bo_req.handle;
-		buf_reloc_handle = arg.reloc_handle;
-
-		if (buf_reloc_handle) {
-			ret = i915_exec_reloc(file_priv, buf_handle, buf_reloc_handle, buffers, buf_count);
-			if (ret)
-				goto out_err;
-			DRM_MEMORYBARRIER();
-		}
-
-		rep.ret = drm_bo_handle_validate(file_priv, req->bo_req.handle,
-						 req->bo_req.flags, req->bo_req.mask,
-						 req->bo_req.hint,
-						 req->bo_req.fence_class, 0,
-						 &rep.bo_info,
-						 &buffers[buf_count].buffer);
-
-		if (rep.ret) {
-			DRM_ERROR("error on handle validate %d\n", rep.ret);
-			goto out_err;
-		}
-		/*
-		 * If the user provided a presumed offset hint, check whether
-		 * the buffer is in the same place, if so, relocations relative to
-		 * this buffer need not be performed
-		 */
-		if ((req->bo_req.hint & DRM_BO_HINT_PRESUMED_OFFSET) &&
-		    buffers[buf_count].buffer->offset == req->bo_req.presumed_offset) {
-			buffers[buf_count].presumed_offset_correct = 1;
-		}
-
-		next = arg.next;
-		arg.handled = 1;
-		arg.d.rep = rep;
-
-		if (copy_to_user((void __user *)(unsigned long)data, &arg, sizeof(arg)))
-			return -EFAULT;
-
-		data = next;
-		buf_count++;
-
-	} while (next != 0);
-	*num_buffers = buf_count;
+	if (sarea_priv)
+		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 	return 0;
-out_err:
-	mutex_lock(&dev->struct_mutex);
-	i915_dereference_buffers_locked(buffers, buf_count);
-	mutex_unlock(&dev->struct_mutex);
-	*num_buffers = 0;
-	return (ret) ? ret : rep.ret;
 }
 
-static int i915_execbuffer(struct drm_device *dev, void *data,
-			   struct drm_file *file_priv)
+static int i915_flip_bufs(struct drm_device *dev, void *data,
+			  struct drm_file *file_priv)
 {
-	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
-		dev_priv->sarea_priv;
-	struct drm_i915_execbuffer *exec_buf = data;
-	struct _drm_i915_batchbuffer *batch = &exec_buf->batch;
-	struct drm_fence_arg *fence_arg = &exec_buf->fence_arg;
-	int num_buffers;
 	int ret;
-	struct drm_i915_validate_buffer *buffers;
-	struct drm_fence_object *fence;
-
-	if (!dev_priv->allow_batchbuffer) {
-		DRM_ERROR("Batchbuffer ioctl disabled\n");
-		return -EINVAL;
-	}
-
-
-	if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
-							batch->num_cliprects *
-							sizeof(struct drm_clip_rect)))
-		return -EFAULT;
-
-	if (exec_buf->num_buffers > dev_priv->max_validate_buffers)
-		return -EINVAL;
 
+	DRM_DEBUG("%s\n", __func__);
 
-	ret = drm_bo_read_lock(&dev->bm.bm_lock);
-	if (ret)
-		return ret;
+	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	/*
-	 * The cmdbuf_mutex makes sure the validate-submit-fence
-	 * operation is atomic.
-	 */
+	ret = i915_dispatch_flip(dev);
 
-	ret = mutex_lock_interruptible(&dev_priv->cmdbuf_mutex);
-	if (ret) {
-		drm_bo_read_unlock(&dev->bm.bm_lock);
-		return -EAGAIN;
-	}
-
-	num_buffers = exec_buf->num_buffers;
-
-	buffers = drm_calloc(num_buffers, sizeof(struct drm_i915_validate_buffer), DRM_MEM_DRIVER);
-	if (!buffers) {
-		drm_bo_read_unlock(&dev->bm.bm_lock);
-		mutex_unlock(&dev_priv->cmdbuf_mutex);
-		return -ENOMEM;
-	}
-
-	/* validate buffer list + fixup relocations */
-	ret = i915_validate_buffer_list(file_priv, 0, exec_buf->ops_list,
-					buffers, &num_buffers);
-	if (ret)
-		goto out_free;
-
-	/* make sure all previous memory operations have passed */
-	DRM_MEMORYBARRIER();
-	drm_agp_chipset_flush(dev);
-
-	/* submit buffer */
-	batch->start = buffers[num_buffers-1].buffer->offset;
-
-	DRM_DEBUG("i915 exec batchbuffer, start %x used %d cliprects %d\n",
-		  batch->start, batch->used, batch->num_cliprects);
-
-	ret = i915_dispatch_batchbuffer(dev, batch);
-	if (ret)
-		goto out_err0;
-
-	sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
-
-	/* fence */
-	ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence);
-	if (ret)
-		goto out_err0;
-
-	if (!(fence_arg->flags & DRM_FENCE_FLAG_NO_USER)) {
-		ret = drm_fence_add_user_object(file_priv, fence, fence_arg->flags & DRM_FENCE_FLAG_SHAREABLE);
-		if (!ret) {
-			fence_arg->handle = fence->base.hash.key;
-			fence_arg->fence_class = fence->fence_class;
-			fence_arg->type = fence->type;
-			fence_arg->signaled = fence->signaled;
-		}
-	}
-	drm_fence_usage_deref_unlocked(&fence);
-out_err0:
-
-	/* handle errors */
-	mutex_lock(&dev->struct_mutex);
-	i915_dereference_buffers_locked(buffers, num_buffers);
-	mutex_unlock(&dev->struct_mutex);
-
-out_free:
-	drm_free(buffers, (exec_buf->num_buffers * sizeof(struct drm_buffer_object *)), DRM_MEM_DRIVER);
-
-	mutex_unlock(&dev_priv->cmdbuf_mutex);
-	drm_bo_read_unlock(&dev->bm.bm_lock);
 	return ret;
 }
-#endif
-
-static int i915_do_cleanup_pageflip(struct drm_device * dev)
-{
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
-
-	DRM_DEBUG("\n");
-
-	for (i = 0, planes = 0; i < 2; i++)
-		if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
-			dev_priv->sarea_priv->pf_current_page =
-				(dev_priv->sarea_priv->pf_current_page &
-				 ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
-
-			planes |= 1 << i;
-		}
-
-	if (planes)
-		i915_dispatch_flip(dev, planes, 0);
-
-	return 0;
-}
-
-static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
-{
-	drm_i915_flip_t *param = data;
-
-	DRM_DEBUG("\n");
-
-	LOCK_TEST_WITH_RETURN(dev, file_priv);
-
-	/* This is really planes */
-	if (param->pipes & ~0x3) {
-		DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
-			  param->pipes);
-		return -EINVAL;
-	}
-
-	i915_dispatch_flip(dev, param->pipes, 0);
-
-	return 0;
-}
-
 
 static int i915_getparam(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
@@ -1199,7 +725,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
 
 	switch (param->param) {
 	case I915_PARAM_IRQ_ACTIVE:
-		value = dev->irq ? 1 : 0;
+		value = dev->irq_enabled ? 1 : 0;
 		break;
 	case I915_PARAM_ALLOW_BATCHBUFFER:
 		value = dev_priv->allow_batchbuffer ? 1 : 0;
@@ -1207,8 +733,15 @@ static int i915_getparam(struct drm_device *dev, void *data,
 	case I915_PARAM_LAST_DISPATCH:
 		value = READ_BREADCRUMB(dev_priv);
 		break;
+	case I915_PARAM_CHIPSET_ID:
+		value = dev->pci_device;
+		break;
+	case I915_PARAM_HAS_GEM:
+		/* We need to reset this to 1 once we have GEM */
+		value = 0;
+		break;
 	default:
-		DRM_ERROR("Unknown parameter %d\n", param->param);
+		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
 	}
 
@@ -1233,8 +766,6 @@ static int i915_setparam(struct drm_device *dev, void *data,
 
 	switch (param->param) {
 	case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
-		if (!IS_I965G(dev))
-			dev_priv->use_mi_batchbuffer_start = param->value;
 		break;
 	case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 		dev_priv->tex_lru_log_granularity = param->value;
@@ -1243,80 +774,27 @@ static int i915_setparam(struct drm_device *dev, void *data,
 		dev_priv->allow_batchbuffer = param->value;
 		break;
 	default:
-		DRM_ERROR("unknown parameter %d\n", param->param);
+		DRM_DEBUG("unknown parameter %d\n", param->param);
 		return -EINVAL;
 	}
 
 	return 0;
 }
 
-drm_i915_mmio_entry_t mmio_table[] = {
-	[MMIO_REGS_PS_DEPTH_COUNT] = {
-		I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
-		0x2350,
-		8
-	}
-};
-
-static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
-
-static int i915_mmio(struct drm_device *dev, void *data,
-		     struct drm_file *file_priv)
-{
-	uint32_t buf[8];
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	drm_i915_mmio_entry_t *e;
-	drm_i915_mmio_t *mmio = data;
-	void __iomem *base;
-	int i;
-
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
-
-	if (mmio->reg >= mmio_table_size)
-		return -EINVAL;
-
-	e = &mmio_table[mmio->reg];
-	base = (u8 *) dev_priv->mmio_map->handle + e->offset;
-
-	switch (mmio->read_write) {
-	case I915_MMIO_READ:
-		if (!(e->flag & I915_MMIO_MAY_READ))
-			return -EINVAL;
-		for (i = 0; i < e->size / 4; i++)
-			buf[i] = I915_READ(e->offset + i * 4);
-		if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
-			DRM_ERROR("DRM_COPY_TO_USER failed\n");
-			return -EFAULT;
-		}
-		break;
-		
-	case I915_MMIO_WRITE:
-		if (!(e->flag & I915_MMIO_MAY_WRITE))
-			return -EINVAL;
-		if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
-			DRM_ERROR("DRM_COPY_TO_USER failed\n");
-			return -EFAULT;
-		}
-		for (i = 0; i < e->size / 4; i++)
-			I915_WRITE(e->offset + i * 4, buf[i]);
-		break;
-	}
-	return 0;
-}
-
 static int i915_set_status_page(struct drm_device *dev, void *data,
 				struct drm_file *file_priv)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_hws_addr_t *hws = data;
 
+	if (!I915_NEED_GFX_HWS(dev))
+		return -EINVAL;
+
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
 	}
+
 	DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
 
 	dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
@@ -1327,7 +805,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
 	dev_priv->hws_map.flags = 0;
 	dev_priv->hws_map.mtrr = 0;
 
-	drm_core_ioremap(&dev_priv->hws_map, dev);
+	drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 	if (dev_priv->hws_map.handle == NULL) {
 		i915_dma_cleanup(dev);
 		dev_priv->status_gfx_addr = 0;
@@ -1338,8 +816,8 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
 	dev_priv->hw_status_page = dev_priv->hws_map.handle;
 
 	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
-	I915_WRITE(0x02080, dev_priv->status_gfx_addr);
-	DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
+	I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
+	DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
 			dev_priv->status_gfx_addr);
 	DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 	return 0;
@@ -1347,7 +825,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
 
 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 {
-	struct drm_i915_private *dev_priv;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned long base, size;
 	int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
 
@@ -1365,19 +843,59 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	memset(dev_priv, 0, sizeof(drm_i915_private_t));
 
 	dev->dev_private = (void *)dev_priv;
+	dev_priv->dev = dev;
 
 	/* Add register map (needed for suspend/resume) */
 	base = drm_get_resource_start(dev, mmio_bar);
 	size = drm_get_resource_len(dev, mmio_bar);
 
 	ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
-		_DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
+	    _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
 
-#ifdef __linux__
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
-	intel_init_chipset_flush_compat(dev);
+	if (IS_GM45(dev))
+		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
+	else
+		dev->driver->get_vblank_counter = i915_get_vblank_counter;
+
+#ifdef I915_HAVE_GEM
+	i915_gem_load(dev);
 #endif
+	/* Init HWS */
+	if (!I915_NEED_GFX_HWS(dev)) {
+		ret = i915_init_phys_hws(dev);
+		if (ret != 0) {
+			drm_rmmap(dev, dev_priv->mmio_map);
+			drm_free(dev_priv, sizeof(struct drm_i915_private),
+			    DRM_MEM_DRIVER);
+			return ret;
+		}
+	}
+#ifdef __linux__
+	/* On the 945G/GM, the chipset reports the MSI capability on the
+	 * integrated graphics even though the support isn't actually there
+	 * according to the published specs.  It doesn't appear to function
+	 * correctly in testing on 945G.
+	 * This may be a side effect of MSI having been made available for PEG
+	 * and the registers being closely associated.
+	 *
+	 * According to chipset errata, on the 965GM, MSI interrupts may
+	 * be lost or delayed
+	 */
+	if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev))
+		if (pci_enable_msi(dev->pdev))
+			DRM_ERROR("failed to enable MSI\n");
+
+	intel_opregion_init(dev);
 #endif
+	DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
+	dev_priv->user_irq_refcount = 0;
+
+	ret = drm_vblank_init(dev, I915_NUM_PIPE);
+
+	if (ret) {
+		(void) i915_driver_unload(dev);
+		return ret;
+	}
 
 	return ret;
 }
@@ -1386,16 +904,36 @@ int i915_driver_unload(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (dev_priv->mmio_map)
-		drm_rmmap(dev, dev_priv->mmio_map);
+	i915_free_hws(dev);
 
-	drm_free(dev->dev_private, sizeof(drm_i915_private_t),
-		 DRM_MEM_DRIVER);
+	drm_rmmap(dev, dev_priv->mmio_map);
 #ifdef __linux__
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
-	intel_fini_chipset_flush_compat(dev);
-#endif
+	intel_opregion_free(dev);
 #endif
+	DRM_SPINUNINIT(&dev_priv->user_irq_lock);
+
+	drm_free(dev->dev_private, sizeof(drm_i915_private_t),
+		 DRM_MEM_DRIVER);
+
+	return 0;
+}
+
+int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
+{
+	struct drm_i915_file_private *i915_file_priv;
+
+	DRM_DEBUG("\n");
+	i915_file_priv = (struct drm_i915_file_private *)
+	    drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
+
+	if (!i915_file_priv)
+		return -ENOMEM;
+
+	file_priv->driver_priv = i915_file_priv;
+
+	i915_file_priv->mm.last_gem_seqno = 0;
+	i915_file_priv->mm.last_gem_throttle_seqno = 0;
+
 	return 0;
 }
 
@@ -1403,8 +941,11 @@ void i915_driver_lastclose(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 
-	if (drm_getsarea(dev) && dev_priv->sarea_priv)
-		i915_do_cleanup_pageflip(dev);
+	if (!dev_priv)
+		return;
+#ifdef I915_HAVE_GEM
+	i915_gem_lastclose(dev);
+#endif
 	if (dev_priv->agp_heap)
 		i915_mem_takedown(&(dev_priv->agp_heap));
 
@@ -1417,6 +958,13 @@ void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
 	i915_mem_release(dev, file_priv, dev_priv->agp_heap);
 }
 
+void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
+{
+	struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
+
+	drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
+}
+
 struct drm_ioctl_desc i915_ioctls[] = {
 	DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
@@ -1434,10 +982,24 @@ struct drm_ioctl_desc i915_ioctls[] = {
 	DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
 	DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
 	DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
-	DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
-#ifdef I915_HAVE_BUFFER
-	DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
+#ifdef I915_HAVE_GEM
+	DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
+	DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
+	DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
+	DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
+	DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
+	DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
+	DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
+	DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
+	DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
+	DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
+	DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
 #endif
 };
 
@@ -1458,11 +1020,3 @@ int i915_driver_device_is_agp(struct drm_device * dev)
 {
 	return 1;
 }
-
-int i915_driver_firstopen(struct drm_device *dev)
-{
-#ifdef I915_HAVE_BUFFER
-	drm_bo_driver_init(dev);
-#endif
-	return 0;
-}
diff --git a/sys/dev/drm/i915_drm.h b/sys/dev/drm/i915_drm.h
index ddf6680668..769a96bab7 100644
--- a/sys/dev/drm/i915_drm.h
+++ b/sys/dev/drm/i915_drm.h
@@ -1,4 +1,4 @@
-/*
+/*-
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
  *
@@ -22,7 +22,6 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * $DragonFly: src/sys/dev/drm/i915_drm.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef _I915_DRM_H_
@@ -32,7 +31,7 @@
  * subject to backwards-compatibility constraints.
  */
 
-#include "drm.h"
+#include "dev/drm/drm.h"
 
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
@@ -44,7 +43,12 @@ typedef struct _drm_i915_init {
 	enum {
 		I915_INIT_DMA = 0x01,
 		I915_CLEANUP_DMA = 0x02,
-		I915_RESUME_DMA = 0x03
+		I915_RESUME_DMA = 0x03,
+
+		/* Since this struct isn't versioned, just used a new
+		 * 'func' code to indicate the presence of dri2 sarea
+		 * info. */
+		I915_INIT_DMA2 = 0x04
 	} func;
 	unsigned int mmio_offset;
 	int sarea_priv_offset;
@@ -62,9 +66,10 @@ typedef struct _drm_i915_init {
 	unsigned int depth_pitch;
 	unsigned int cpp;
 	unsigned int chipset;
+	unsigned int sarea_handle;
 } drm_i915_init_t;
 
-typedef struct _drm_i915_sarea {
+typedef struct drm_i915_sarea {
 	struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
 	int last_upload;	/* last time texture was uploaded */
 	int last_enqueue;	/* last time a buffer was enqueued */
@@ -120,6 +125,15 @@ typedef struct _drm_i915_sarea {
 	int third_offset;
 	int third_size;
 	unsigned int third_tiled;
+
+	/* buffer object handles for the static buffers.  May change
+	 * over the lifetime of the client, though it doesn't in our current
+	 * implementation.
+	 */
+	unsigned int front_bo_handle;
+	unsigned int back_bo_handle;
+	unsigned int third_bo_handle;
+	unsigned int depth_bo_handle;
 } drm_i915_sarea_t;
 
 /* Driver specific fence types and classes.
@@ -162,6 +176,22 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_MMIO		0x10
 #define DRM_I915_HWS_ADDR	0x11
 #define DRM_I915_EXECBUFFER	0x12
+#define DRM_I915_GEM_INIT	0x13
+#define DRM_I915_GEM_EXECBUFFER	0x14
+#define DRM_I915_GEM_PIN	0x15
+#define DRM_I915_GEM_UNPIN	0x16
+#define DRM_I915_GEM_BUSY	0x17
+#define DRM_I915_GEM_THROTTLE	0x18
+#define DRM_I915_GEM_ENTERVT	0x19
+#define DRM_I915_GEM_LEAVEVT	0x1a
+#define DRM_I915_GEM_CREATE	0x1b
+#define DRM_I915_GEM_PREAD	0x1c
+#define DRM_I915_GEM_PWRITE	0x1d
+#define DRM_I915_GEM_MMAP	0x1e
+#define DRM_I915_GEM_SET_DOMAIN	0x1f
+#define DRM_I915_GEM_SW_FINISH	0x20
+#define DRM_I915_GEM_SET_TILING	0x21
+#define DRM_I915_GEM_GET_TILING	0x22
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -181,6 +211,22 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_VBLANK_SWAP	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 #define DRM_IOCTL_I915_MMIO             DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
 #define DRM_IOCTL_I915_EXECBUFFER	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
+#define DRM_IOCTL_I915_GEM_INIT		DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
+#define DRM_IOCTL_I915_GEM_PIN		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
+#define DRM_IOCTL_I915_GEM_UNPIN	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
+#define DRM_IOCTL_I915_GEM_BUSY		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
+#define DRM_IOCTL_I915_GEM_THROTTLE	DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
+#define DRM_IOCTL_I915_GEM_ENTERVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
+#define DRM_IOCTL_I915_GEM_LEAVEVT	DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
+#define DRM_IOCTL_I915_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_PREAD	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
+#define DRM_IOCTL_I915_GEM_PWRITE	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
+#define DRM_IOCTL_I915_GEM_MMAP		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
+#define DRM_IOCTL_I915_GEM_SET_DOMAIN	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
+#define DRM_IOCTL_I915_GEM_SW_FINISH	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
+#define DRM_IOCTL_I915_GEM_SET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
+#define DRM_IOCTL_I915_GEM_GET_TILING	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 
 /* Asynchronous page flipping:
  */
@@ -197,7 +243,7 @@ typedef struct drm_i915_flip {
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
  */
-typedef struct _drm_i915_batchbuffer {
+typedef struct drm_i915_batchbuffer {
 	int start;		/* agp offset */
 	int used;		/* nr bytes in use */
 	int DR1;		/* hw flags for GFX_OP_DRAWRECT_INFO */
@@ -233,6 +279,8 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_IRQ_ACTIVE            1
 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 #define I915_PARAM_LAST_DISPATCH         3
+#define I915_PARAM_CHIPSET_ID            4
+#define I915_PARAM_HAS_GEM               5
 
 typedef struct drm_i915_getparam {
 	int param;
@@ -330,9 +378,9 @@ typedef struct drm_i915_hws_addr {
 
 /*
  * Relocation header is 4 uint32_ts
- * 0 - (16-bit relocation type << 16)| 16 bit reloc count
- * 1 - buffer handle for another list of relocs
- * 2-3 - spare.
+ * 0 - 32 bit reloc count
+ * 1 - 32-bit relocation type
+ * 2-3 - 64-bit user buffer handle ptr for another list of relocs.
  */
 #define I915_RELOC_HEADER 4
 
@@ -340,16 +388,31 @@ typedef struct drm_i915_hws_addr {
  * type 0 relocation has 4-uint32_t stride
  * 0 - offset into buffer
  * 1 - delta to add in
- * 2 - index into buffer list
+ * 2 - buffer handle
  * 3 - reserved (for optimisations later).
  */
+/*
+ * type 1 relocation has 4-uint32_t stride.
+ * Hangs off the first item in the op list.
+ * Performed after all valiations are done.
+ * Try to group relocs into the same relocatee together for
+ * performance reasons.
+ * 0 - offset into buffer
+ * 1 - delta to add in
+ * 2 - buffer index in op list.
+ * 3 - relocatee index in op list.
+ */
 #define I915_RELOC_TYPE_0 0
 #define I915_RELOC0_STRIDE 4
+#define I915_RELOC_TYPE_1 1
+#define I915_RELOC1_STRIDE 4
+
 
 struct drm_i915_op_arg {
 	uint64_t next;
-	uint32_t reloc_handle;
+	uint64_t reloc_ptr;
 	int handled;
+	unsigned int pad64;
 	union {
 		struct drm_bo_op_req req;
 		struct drm_bo_arg_rep rep;
@@ -360,9 +423,297 @@ struct drm_i915_op_arg {
 struct drm_i915_execbuffer {
 	uint64_t ops_list;
 	uint32_t num_buffers;
-	struct _drm_i915_batchbuffer batch;
+	struct drm_i915_batchbuffer batch;
 	drm_context_t context; /* for lockless use in the future */
 	struct drm_fence_arg fence_arg;
 };
 
+struct drm_i915_gem_init {
+	/**
+	 * Beginning offset in the GTT to be managed by the DRM memory
+	 * manager.
+	 */
+	uint64_t gtt_start;
+	/**
+	 * Ending offset in the GTT to be managed by the DRM memory
+	 * manager.
+	 */
+	uint64_t gtt_end;
+};
+
+struct drm_i915_gem_create {
+	/**
+	 * Requested size for the object.
+	 *
+	 * The (page-aligned) allocated size for the object will be returned.
+	 */
+	uint64_t size;
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	uint32_t handle;
+	uint32_t pad;
+};
+
+struct drm_i915_gem_pread {
+	/** Handle for the object being read. */
+	uint32_t handle;
+	uint32_t pad;
+	/** Offset into the object to read from */
+	uint64_t offset;
+	/** Length of data to read */
+	uint64_t size;
+	/** Pointer to write the data into. */
+	uint64_t data_ptr;	/* void *, but pointers are not 32/64 compatible */
+};
+
+struct drm_i915_gem_pwrite {
+	/** Handle for the object being written to. */
+	uint32_t handle;
+	uint32_t pad;
+	/** Offset into the object to write to */
+	uint64_t offset;
+	/** Length of data to write */
+	uint64_t size;
+	/** Pointer to read the data from. */
+	uint64_t data_ptr;	/* void *, but pointers are not 32/64 compatible */
+};
+
+struct drm_i915_gem_mmap {
+	/** Handle for the object being mapped. */
+	uint32_t handle;
+	uint32_t pad;
+	/** Offset in the object to map. */
+	uint64_t offset;
+	/**
+	 * Length of data to map.
+	 *
+	 * The value will be page-aligned.
+	 */
+	uint64_t size;
+	/** Returned pointer the data was mapped at */
+	uint64_t addr_ptr;	/* void *, but pointers are not 32/64 compatible */
+};
+
+struct drm_i915_gem_set_domain {
+	/** Handle for the object */
+	uint32_t handle;
+
+	/** New read domains */
+	uint32_t read_domains;
+
+	/** New write domain */
+	uint32_t write_domain;
+};
+
+struct drm_i915_gem_sw_finish {
+	/** Handle for the object */
+	uint32_t handle;
+};
+
+struct drm_i915_gem_relocation_entry {
+	/**
+	 * Handle of the buffer being pointed to by this relocation entry.
+	 *
+	 * It's appealing to make this be an index into the mm_validate_entry
+	 * list to refer to the buffer, but this allows the driver to create
+	 * a relocation list for state buffers and not re-write it per
+	 * exec using the buffer.
+	 */
+	uint32_t target_handle;
+
+	/**
+	 * Value to be added to the offset of the target buffer to make up
+	 * the relocation entry.
+	 */
+	uint32_t delta;
+
+	/** Offset in the buffer the relocation entry will be written into */
+	uint64_t offset;
+
+	/**
+	 * Offset value of the target buffer that the relocation entry was last
+	 * written as.
+	 *
+	 * If the buffer has the same offset as last time, we can skip syncing
+	 * and writing the relocation.  This value is written back out by
+	 * the execbuffer ioctl when the relocation is written.
+	 */
+	uint64_t presumed_offset;
+
+	/**
+	 * Target memory domains read by this operation.
+	 */
+	uint32_t read_domains;
+
+	/**
+	 * Target memory domains written by this operation.
+	 *
+	 * Note that only one domain may be written by the whole
+	 * execbuffer operation, so that where there are conflicts,
+	 * the application will get -EINVAL back.
+	 */
+	uint32_t write_domain;
+};
+
+/** @{
+ * Intel memory domains
+ *
+ * Most of these just align with the various caches in
+ * the system and are used to flush and invalidate as
+ * objects end up cached in different domains.
+ */
+/** CPU cache */
+#define I915_GEM_DOMAIN_CPU		0x00000001
+/** Render cache, used by 2D and 3D drawing */
+#define I915_GEM_DOMAIN_RENDER		0x00000002
+/** Sampler cache, used by texture engine */
+#define I915_GEM_DOMAIN_SAMPLER		0x00000004
+/** Command queue, used to load batch buffers */
+#define I915_GEM_DOMAIN_COMMAND		0x00000008
+/** Instruction cache, used by shader programs */
+#define I915_GEM_DOMAIN_INSTRUCTION	0x00000010
+/** Vertex address cache */
+#define I915_GEM_DOMAIN_VERTEX		0x00000020
+/** GTT domain - aperture and scanout */
+#define I915_GEM_DOMAIN_GTT		0x00000040
+/** @} */
+
+struct drm_i915_gem_exec_object {
+	/**
+	 * User's handle for a buffer to be bound into the GTT for this
+	 * operation.
+	 */
+	uint32_t handle;
+
+	/** Number of relocations to be performed on this buffer */
+	uint32_t relocation_count;
+	/**
+	 * Pointer to array of struct drm_i915_gem_relocation_entry containing
+	 * the relocations to be performed in this buffer.
+	 */
+	uint64_t relocs_ptr;
+
+	/** Required alignment in graphics aperture */
+	uint64_t alignment;
+
+	/**
+	 * Returned value of the updated offset of the object, for future
+	 * presumed_offset writes.
+	 */
+	uint64_t offset;
+};
+
+struct drm_i915_gem_execbuffer {
+	/**
+	 * List of buffers to be validated with their relocations to be
+	 * performend on them.
+	 *
+	 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
+	 *
+	 * These buffers must be listed in an order such that all relocations
+	 * a buffer is performing refer to buffers that have already appeared
+	 * in the validate list.
+	 */
+	uint64_t buffers_ptr;
+	uint32_t buffer_count;
+
+	/** Offset in the batchbuffer to start execution from. */
+	uint32_t batch_start_offset;
+	/** Bytes used in batchbuffer from batch_start_offset */
+	uint32_t batch_len;
+	uint32_t DR1;
+	uint32_t DR4;
+	uint32_t num_cliprects;
+	uint64_t cliprects_ptr;	/* struct drm_clip_rect *cliprects */
+};
+
+struct drm_i915_gem_pin {
+	/** Handle of the buffer to be pinned. */
+	uint32_t handle;
+	uint32_t pad;
+
+	/** alignment required within the aperture */
+	uint64_t alignment;
+
+	/** Returned GTT offset of the buffer. */
+	uint64_t offset;
+};
+
+struct drm_i915_gem_unpin {
+	/** Handle of the buffer to be unpinned. */
+	uint32_t handle;
+	uint32_t pad;
+};
+
+struct drm_i915_gem_busy {
+	/** Handle of the buffer to check for busy */
+	uint32_t handle;
+
+	/** Return busy status (1 if busy, 0 if idle) */
+	uint32_t busy;
+};
+
+#define I915_TILING_NONE	0
+#define I915_TILING_X		1
+#define I915_TILING_Y		2
+
+#define I915_BIT_6_SWIZZLE_NONE		0
+#define I915_BIT_6_SWIZZLE_9		1
+#define I915_BIT_6_SWIZZLE_9_10		2
+#define I915_BIT_6_SWIZZLE_9_11		3
+#define I915_BIT_6_SWIZZLE_9_10_11	4
+/* Not seen by userland */
+#define I915_BIT_6_SWIZZLE_UNKNOWN	5
+
+struct drm_i915_gem_set_tiling {
+	/** Handle of the buffer to have its tiling state updated */
+	uint32_t handle;
+
+	/**
+	 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+	 * I915_TILING_Y).
+	 *
+	 * This value is to be set on request, and will be updated by the
+	 * kernel on successful return with the actual chosen tiling layout.
+	 *
+	 * The tiling mode may be demoted to I915_TILING_NONE when the system
+	 * has bit 6 swizzling that can't be managed correctly by GEM.
+	 *
+	 * Buffer contents become undefined when changing tiling_mode.
+	 */
+	uint32_t tiling_mode;
+
+	/**
+	 * Stride in bytes for the object when in I915_TILING_X or
+	 * I915_TILING_Y.
+	 */
+	uint32_t stride;
+
+	/**
+	 * Returned address bit 6 swizzling required for CPU access through
+	 * mmap mapping.
+	 */
+	uint32_t swizzle_mode;
+};
+
+struct drm_i915_gem_get_tiling {
+	/** Handle of the buffer to get tiling state for. */
+	uint32_t handle;
+
+	/**
+	 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+	 * I915_TILING_Y).
+	 */
+	uint32_t tiling_mode;
+
+	/**
+	 * Returned address bit 6 swizzling required for CPU access through
+	 * mmap mapping.
+	 */
+	uint32_t swizzle_mode;
+};
+
 #endif				/* _I915_DRM_H_ */
diff --git a/sys/dev/drm/i915_drv.c b/sys/dev/drm/i915_drv.c
index 0ed569a215..11e25ede52 100644
--- a/sys/dev/drm/i915_drv.c
+++ b/sys/dev/drm/i915_drv.c
@@ -27,74 +27,111 @@
  * Authors:
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/i915_drv.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "i915_drm.h"
-#include "i915_drv.h"
-#include "drm_pciids.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/i915_drm.h"
+#include "dev/drm/i915_drv.h"
+#include "dev/drm/drm_pciids.h"
 
 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
 static drm_pci_id_list_t i915_pciidlist[] = {
 	i915_PCI_IDS
 };
 
-static void i915_configure(drm_device_t *dev)
+static int i915_suspend(device_t kdev)
 {
-	dev->driver.buf_priv_size	= 1;	/* No dev_priv */
-	dev->driver.load		= i915_driver_load;
-	dev->driver.preclose		= i915_driver_preclose;
-	dev->driver.lastclose		= i915_driver_lastclose;
-	dev->driver.device_is_agp	= i915_driver_device_is_agp;
-	dev->driver.vblank_wait		= i915_driver_vblank_wait;
-	dev->driver.vblank_wait2	= i915_driver_vblank_wait2;
-	dev->driver.irq_preinstall	= i915_driver_irq_preinstall;
-	dev->driver.irq_postinstall	= i915_driver_irq_postinstall;
-	dev->driver.irq_uninstall	= i915_driver_irq_uninstall;
-	dev->driver.irq_handler		= i915_driver_irq_handler;
-
-	dev->driver.ioctls		= i915_ioctls;
-	dev->driver.max_ioctl		= i915_max_ioctl;
-
-	dev->driver.name		= DRIVER_NAME;
-	dev->driver.desc		= DRIVER_DESC;
-	dev->driver.date		= DRIVER_DATE;
-	dev->driver.major		= DRIVER_MAJOR;
-	dev->driver.minor		= DRIVER_MINOR;
-	dev->driver.patchlevel		= DRIVER_PATCHLEVEL;
-
-	dev->driver.use_agp		= 1;
-	dev->driver.require_agp		= 1;
-	dev->driver.use_mtrr		= 1;
-	dev->driver.use_irq		= 1;
-	dev->driver.use_vbl_irq		= 1;
-	dev->driver.use_vbl_irq2	= 1;
+	struct drm_device *dev = device_get_softc(kdev);
+
+	if (!dev || !dev->dev_private) {
+		DRM_ERROR("DRM not initialized, aborting suspend.\n");
+		return -ENODEV;
+	}
+
+	i915_save_state(dev);
+
+	return (bus_generic_suspend(kdev));
+}
+
+static int i915_resume(device_t kdev)
+{
+	struct drm_device *dev = device_get_softc(kdev);
+
+	i915_restore_state(dev);
+
+	return (bus_generic_resume(kdev));
+}
+
+static void i915_configure(struct drm_device *dev)
+{
+	dev->driver->driver_features =
+	   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR |
+	   DRIVER_HAVE_IRQ;
+
+	dev->driver->buf_priv_size	= sizeof(drm_i915_private_t);
+	dev->driver->load		= i915_driver_load;
+	dev->driver->unload		= i915_driver_unload;
+	dev->driver->preclose		= i915_driver_preclose;
+	dev->driver->lastclose		= i915_driver_lastclose;
+	dev->driver->device_is_agp	= i915_driver_device_is_agp;
+	dev->driver->enable_vblank	= i915_enable_vblank;
+	dev->driver->disable_vblank	= i915_disable_vblank;
+	dev->driver->irq_preinstall	= i915_driver_irq_preinstall;
+	dev->driver->irq_postinstall	= i915_driver_irq_postinstall;
+	dev->driver->irq_uninstall	= i915_driver_irq_uninstall;
+	dev->driver->irq_handler	= i915_driver_irq_handler;
+
+	dev->driver->ioctls		= i915_ioctls;
+	dev->driver->max_ioctl		= i915_max_ioctl;
+
+	dev->driver->name		= DRIVER_NAME;
+	dev->driver->desc		= DRIVER_DESC;
+	dev->driver->date		= DRIVER_DATE;
+	dev->driver->major		= DRIVER_MAJOR;
+	dev->driver->minor		= DRIVER_MINOR;
+	dev->driver->patchlevel		= DRIVER_PATCHLEVEL;
 }
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 static int
-i915_probe(device_t dev)
+i915_probe(device_t kdev)
 {
-	return drm_probe(dev, i915_pciidlist);
+	return drm_probe(kdev, i915_pciidlist);
 }
 
 static int
-i915_attach(device_t nbdev)
+i915_attach(device_t kdev)
 {
-	drm_device_t *dev = device_get_softc(nbdev);
+	struct drm_device *dev = device_get_softc(kdev);
+
+	dev->driver = malloc(sizeof(struct drm_driver_info), DRM_MEM_DRIVER,
+	    M_WAITOK | M_ZERO);
 
-	bzero(dev, sizeof(drm_device_t));
 	i915_configure(dev);
-	return drm_attach(nbdev, i915_pciidlist);
+
+	return drm_attach(kdev, i915_pciidlist);
+}
+
+static int
+i915_detach(device_t kdev)
+{
+	struct drm_device *dev = device_get_softc(kdev);
+	int ret;
+
+	ret = drm_detach(kdev);
+
+	free(dev->driver, DRM_MEM_DRIVER);
+
+	return ret;
 }
 
 static device_method_t i915_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		i915_probe),
 	DEVMETHOD(device_attach,	i915_attach),
-	DEVMETHOD(device_detach,	drm_detach),
+	DEVMETHOD(device_suspend,	i915_suspend),
+	DEVMETHOD(device_resume,	i915_resume),
+	DEVMETHOD(device_detach,	i915_detach),
 
 	{ 0, 0 }
 };
@@ -106,7 +143,7 @@ static driver_t i915_driver = {
 	"drmsub",
 #endif
 	i915_methods,
-	sizeof(drm_device_t)
+	sizeof(struct drm_device)
 };
 
 extern devclass_t drm_devclass;
@@ -116,7 +153,3 @@ DRIVER_MODULE(i915, vgapci, i915_driver, drm_devclass, 0, 0);
 DRIVER_MODULE(i915, agp, i915_driver, drm_devclass, 0, 0);
 #endif
 MODULE_DEPEND(i915, drm, 1, 1, 1);
-
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-CFDRIVER_DECL(i915, DV_TTY, NULL);
-#endif
diff --git a/sys/dev/drm/i915_drv.h b/sys/dev/drm/i915_drv.h
index aea71d9421..d02b6383cc 100644
--- a/sys/dev/drm/i915_drv.h
+++ b/sys/dev/drm/i915_drv.h
@@ -25,12 +25,13 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * $DragonFly: src/sys/dev/drm/i915_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef _I915_DRV_H_
 #define _I915_DRV_H_
 
+#include "dev/drm/i915_reg.h"
+
 /* General customization:
  */
 
@@ -38,12 +39,14 @@
 
 #define DRIVER_NAME		"i915"
 #define DRIVER_DESC		"Intel Graphics"
-#define DRIVER_DATE		"20070209"
+#define DRIVER_DATE		"20080730"
 
-#if defined(__linux__)
-#define I915_HAVE_FENCE
-#define I915_HAVE_BUFFER
-#endif
+enum i915_pipe {
+	PIPE_A = 0,
+	PIPE_B,
+};
+
+#define I915_NUM_PIPE	2
 
 /* Interface history:
  *
@@ -54,34 +57,28 @@
  * 1.5: Add vblank pipe configuration
  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  *      - Support vertical blank on secondary display pipe
- * 1.8: New ioctl for ARB_Occlusion_Query
- * 1.9: Usable page flipping and triple buffering
- * 1.10: Plane/pipe disentangling
- * 1.11: TTM superioctl
- * 1.12: TTM relocation optimization
  */
 #define DRIVER_MAJOR		1
-#if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER)
-#define DRIVER_MINOR		12
-#else
 #define DRIVER_MINOR		6
-#endif
 #define DRIVER_PATCHLEVEL	0
 
-#ifdef I915_HAVE_BUFFER
-#define I915_MAX_VALIDATE_BUFFERS 4096
-#endif
+#define WATCH_COHERENCY	0
+#define WATCH_BUF	0
+#define WATCH_EXEC	0
+#define WATCH_LRU	0
+#define WATCH_RELOC	0
+#define WATCH_INACTIVE	0
+#define WATCH_PWRITE	0
 
 typedef struct _drm_i915_ring_buffer {
 	int tail_mask;
-	unsigned long Start;
-	unsigned long End;
 	unsigned long Size;
 	u8 *virtual_start;
 	int head;
 	int tail;
 	int space;
 	drm_local_map_t map;
+	struct drm_gem_object *ring_obj;
 } drm_i915_ring_buffer_t;
 
 struct mem_block {
@@ -92,15 +89,22 @@ struct mem_block {
 	struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 };
 
-typedef struct _drm_i915_vbl_swap {
-	struct list_head head;
-	drm_drawable_t drw_id;
-	unsigned int plane;
-	unsigned int sequence;
-	int flip;
-} drm_i915_vbl_swap_t;
+struct opregion_header;
+struct opregion_acpi;
+struct opregion_swsci;
+struct opregion_asle;
+
+struct intel_opregion {
+	struct opregion_header *header;
+	struct opregion_acpi *acpi;
+	struct opregion_swsci *swsci;
+	struct opregion_asle *asle;
+	int enabled;
+};
 
 typedef struct drm_i915_private {
+	struct drm_device *dev;
+
 	drm_local_map_t *sarea;
 	drm_local_map_t *mmio_map;
 
@@ -113,45 +117,39 @@ typedef struct drm_i915_private {
 	uint32_t counter;
 	unsigned int status_gfx_addr;
 	drm_local_map_t hws_map;
+	struct drm_gem_object *hws_obj;
 
 	unsigned int cpp;
-	int use_mi_batchbuffer_start;
+	int back_offset;
+	int front_offset;
+	int current_page;
+	int page_flipping;
 
 	wait_queue_head_t irq_queue;
 	atomic_t irq_received;
-	atomic_t irq_emitted;
+	/** Protects user_irq_refcount and irq_mask_reg */
+	DRM_SPINTYPE user_irq_lock;
+	/** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
+	int user_irq_refcount;
+	/** Cached value of IER to avoid reads in updating the bitfield */
+	u32 irq_mask_reg;
+	u32 pipestat[2];
 
 	int tex_lru_log_granularity;
 	int allow_batchbuffer;
 	struct mem_block *agp_heap;
 	unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 	int vblank_pipe;
-	DRM_SPINTYPE user_irq_lock;
-	int user_irq_refcount;
-	int fence_irq_on;
-	uint32_t irq_enable_reg;
-	int irq_enabled;
-
-#ifdef I915_HAVE_FENCE
-	uint32_t flush_sequence;
-	uint32_t flush_flags;
-	uint32_t flush_pending;
-	uint32_t saved_flush_status;
-#endif
-#ifdef I915_HAVE_BUFFER
-	void *agp_iomap;
-	unsigned int max_validate_buffers;
-	struct mutex cmdbuf_mutex;
-#endif
 
-	DRM_SPINTYPE swaps_lock;
-	drm_i915_vbl_swap_t vbl_swaps;
-	unsigned int swaps_pending;
+	struct intel_opregion opregion;
 
 	/* Register state */
 	u8 saveLBB;
 	u32 saveDSPACNTR;
 	u32 saveDSPBCNTR;
+	u32 saveDSPARB;
+	u32 saveRENDERSTANDBY;
+	u32 saveHWS;
 	u32 savePIPEACONF;
 	u32 savePIPEBCONF;
 	u32 savePIPEASRC;
@@ -167,10 +165,11 @@ typedef struct drm_i915_private {
 	u32 saveVBLANK_A;
 	u32 saveVSYNC_A;
 	u32 saveBCLRPAT_A;
+	u32 savePIPEASTAT;
 	u32 saveDSPASTRIDE;
 	u32 saveDSPASIZE;
 	u32 saveDSPAPOS;
-	u32 saveDSPABASE;
+	u32 saveDSPAADDR;
 	u32 saveDSPASURF;
 	u32 saveDSPATILEOFF;
 	u32 savePFIT_PGM_RATIOS;
@@ -187,27 +186,28 @@ typedef struct drm_i915_private {
 	u32 saveVBLANK_B;
 	u32 saveVSYNC_B;
 	u32 saveBCLRPAT_B;
+	u32 savePIPEBSTAT;
 	u32 saveDSPBSTRIDE;
 	u32 saveDSPBSIZE;
 	u32 saveDSPBPOS;
-	u32 saveDSPBBASE;
+	u32 saveDSPBADDR;
 	u32 saveDSPBSURF;
 	u32 saveDSPBTILEOFF;
-	u32 saveVCLK_DIVISOR_VGA0;
-	u32 saveVCLK_DIVISOR_VGA1;
-	u32 saveVCLK_POST_DIV;
+	u32 saveVGA0;
+	u32 saveVGA1;
+	u32 saveVGA_PD;
 	u32 saveVGACNTRL;
 	u32 saveADPA;
 	u32 saveLVDS;
-	u32 saveLVDSPP_ON;
-	u32 saveLVDSPP_OFF;
+	u32 savePP_ON_DELAYS;
+	u32 savePP_OFF_DELAYS;
 	u32 saveDVOA;
 	u32 saveDVOB;
 	u32 saveDVOC;
 	u32 savePP_ON;
 	u32 savePP_OFF;
 	u32 savePP_CONTROL;
-	u32 savePP_CYCLE;
+	u32 savePP_DIVISOR;
 	u32 savePFIT_CONTROL;
 	u32 save_palette_a[256];
 	u32 save_palette_b[256];
@@ -215,17 +215,106 @@ typedef struct drm_i915_private {
 	u32 saveFBC_LL_BASE;
 	u32 saveFBC_CONTROL;
 	u32 saveFBC_CONTROL2;
+	u32 saveIER;
+	u32 saveIIR;
+	u32 saveIMR;
+	u32 saveCACHE_MODE_0;
+	u32 saveD_STATE;
+	u32 saveCG_2D_DIS;
+	u32 saveMI_ARB_STATE;
 	u32 saveSWF0[16];
 	u32 saveSWF1[16];
 	u32 saveSWF2[3];
 	u8 saveMSR;
 	u8 saveSR[8];
-	u8 saveGR[24];
+	u8 saveGR[25];
 	u8 saveAR_INDEX;
-	u8 saveAR[20];
+	u8 saveAR[21];
 	u8 saveDACMASK;
-	u8 saveDACDATA[256*3]; /* 256 3-byte colors */
-	u8 saveCR[36];
+	u8 saveCR[37];
+
+	struct {
+#ifdef __linux__
+		struct drm_mm gtt_space;
+#endif
+		/**
+		 * List of objects currently involved in rendering from the
+		 * ringbuffer.
+		 *
+		 * A reference is held on the buffer while on this list.
+		 */
+		struct list_head active_list;
+
+		/**
+		 * List of objects which are not in the ringbuffer but which
+		 * still have a write_domain which needs to be flushed before
+		 * unbinding.
+		 *
+		 * A reference is held on the buffer while on this list.
+		 */
+		struct list_head flushing_list;
+
+		/**
+		 * LRU list of objects which are not in the ringbuffer and
+		 * are ready to unbind, but are still in the GTT.
+		 *
+		 * A reference is not held on the buffer while on this list,
+		 * as merely being GTT-bound shouldn't prevent its being
+		 * freed, and we'll pull it off the list in the free path.
+		 */
+		struct list_head inactive_list;
+
+		/**
+		 * List of breadcrumbs associated with GPU requests currently
+		 * outstanding.
+		 */
+		struct list_head request_list;
+#ifdef __linux__
+		/**
+		 * We leave the user IRQ off as much as possible,
+		 * but this means that requests will finish and never
+		 * be retired once the system goes idle. Set a timer to
+		 * fire periodically while the ring is running. When it
+		 * fires, go retire requests.
+		 */
+		struct delayed_work retire_work;
+#endif
+		uint32_t next_gem_seqno;
+
+		/**
+		 * Waiting sequence number, if any
+		 */
+		uint32_t waiting_gem_seqno;
+
+		/**
+		 * Last seq seen at irq time
+		 */
+		uint32_t irq_gem_seqno;
+
+		/**
+		 * Flag if the X Server, and thus DRM, is not currently in
+		 * control of the device.
+		 *
+		 * This is set between LeaveVT and EnterVT.  It needs to be
+		 * replaced with a semaphore.  It also needs to be
+		 * transitioned away from for kernel modesetting.
+		 */
+		int suspended;
+
+		/**
+		 * Flag if the hardware appears to be wedged.
+		 *
+		 * This is set when attempts to idle the device timeout.
+		 * It prevents command submission from occuring and makes
+		 * every pending request fail
+		 */
+		int wedged;
+
+		/** Bit 6 swizzling required for X tiling */
+		uint32_t bit_6_swizzle_x;
+		/** Bit 6 swizzling required for Y tiling */
+		uint32_t bit_6_swizzle_y;
+	} mm;
 } drm_i915_private_t;
 
 enum intel_chip_family {
@@ -235,6 +324,93 @@ enum intel_chip_family {
 	CHIP_I965 = 0x08,
 };
 
+/** driver private structure attached to each drm_gem_object */
+struct drm_i915_gem_object {
+	struct drm_gem_object *obj;
+
+	/** Current space allocated to this object in the GTT, if any. */
+	struct drm_mm_node *gtt_space;
+
+	/** This object's place on the active/flushing/inactive lists */
+	struct list_head list;
+
+	/**
+	 * This is set if the object is on the active or flushing lists
+	 * (has pending rendering), and is not set if it's on inactive (ready
+	 * to be unbound).
+	 */
+	int active;
+
+	/**
+	 * This is set if the object has been written to since last bound
+	 * to the GTT
+	 */
+	int dirty;
+
+	/** AGP memory structure for our GTT binding. */
+	DRM_AGP_MEM *agp_mem;
+
+	struct page **page_list;
+
+	/**
+	 * Current offset of the object in GTT space.
+	 *
+	 * This is the same as gtt_space->start
+	 */
+	uint32_t gtt_offset;
+
+	/** Boolean whether this object has a valid gtt offset. */
+	int gtt_bound;
+
+	/** How many users have pinned this object in GTT space */
+	int pin_count;
+
+	/** Breadcrumb of last rendering to the buffer. */
+	uint32_t last_rendering_seqno;
+
+	/** Current tiling mode for the object. */
+	uint32_t tiling_mode;
+
+	/** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
+	uint32_t agp_type;
+
+	/**
+	 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when
+	 * GEM_DOMAIN_CPU is not in the object's read domain.
+	 */
+	uint8_t *page_cpu_valid;
+};
+
+/**
+ * Request queue structure.
+ *
+ * The request queue allows us to note sequence numbers that have been emitted
+ * and may be associated with active buffers to be retired.
+ *
+ * By keeping this list, we can avoid having to do questionable
+ * sequence-number comparisons on buffer last_rendering_seqnos, and associate
+ * an emission time with seqnos for tracking how far ahead of the GPU we are.
+ */
+struct drm_i915_gem_request {
+	/** GEM sequence number associated with this request. */
+	uint32_t seqno;
+
+	/** Time at which this request was emitted, in jiffies. */
+	unsigned long emitted_jiffies;
+
+	/** Cache domains that were flushed at the start of the request. */
+	uint32_t flush_domains;
+
+	struct list_head list;
+};
+
+struct drm_i915_file_private {
+	struct {
+		uint32_t last_gem_seqno;
+		uint32_t last_gem_throttle_seqno;
+	} mm;
+};
+
 extern struct drm_ioctl_desc i915_ioctls[];
 extern int i915_max_ioctl;
 
@@ -242,39 +418,49 @@ extern int i915_max_ioctl;
 extern void i915_kernel_lost_context(struct drm_device * dev);
 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 extern int i915_driver_unload(struct drm_device *);
+extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 extern void i915_driver_lastclose(struct drm_device * dev);
 extern void i915_driver_preclose(struct drm_device *dev,
 				 struct drm_file *file_priv);
+extern void i915_driver_postclose(struct drm_device *dev,
+				  struct drm_file *file_priv);
 extern int i915_driver_device_is_agp(struct drm_device * dev);
 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 			      unsigned long arg);
-extern void i915_emit_breadcrumb(struct drm_device *dev);
-extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync);
-extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush);
-extern int i915_driver_firstopen(struct drm_device *dev);
+extern int i915_emit_box(struct drm_device *dev,
+			 struct drm_clip_rect __user *boxes,
+			 int i, int DR1, int DR4);
 
 /* i915_irq.c */
 extern int i915_irq_emit(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv);
 extern int i915_irq_wait(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv);
+void i915_user_irq_get(struct drm_device *dev);
+void i915_user_irq_put(struct drm_device *dev);
 
-extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
-extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 extern void i915_driver_irq_preinstall(struct drm_device * dev);
-extern void i915_driver_irq_postinstall(struct drm_device * dev);
+extern int i915_driver_irq_postinstall(struct drm_device *dev);
 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 				struct drm_file *file_priv);
-extern int i915_emit_irq(struct drm_device *dev);
-extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
-extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
+extern int i915_enable_vblank(struct drm_device *dev, int crtc);
+extern void i915_disable_vblank(struct drm_device *dev, int crtc);
+extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
+extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 			    struct drm_file *file_priv);
 
+void
+i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
+
+void
+i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
+
+
 /* i915_mem.c */
 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 			  struct drm_file *file_priv);
@@ -286,58 +472,113 @@ extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 				 struct drm_file *file_priv);
 extern void i915_mem_takedown(struct mem_block **heap);
 extern void i915_mem_release(struct drm_device * dev,
-			     struct drm_file *file_priv,
-			     struct mem_block *heap);
-#ifdef I915_HAVE_FENCE
-/* i915_fence.c */
-
-
-extern void i915_fence_handler(struct drm_device *dev);
-extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class,
-				    uint32_t flags,
-				    uint32_t *sequence,
-				    uint32_t *native_type);
-extern void i915_poke_flush(struct drm_device *dev, uint32_t class);
-extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
+			     struct drm_file *file_priv, struct mem_block *heap);
+#ifdef I915_HAVE_GEM
+/* i915_gem.c */
+int i915_gem_init_ioctl(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+int i915_gem_create_ioctl(struct drm_device *dev, void *data,
+			  struct drm_file *file_priv);
+int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
+			 struct drm_file *file_priv);
+int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
+			  struct drm_file *file_priv);
+int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
+			      struct drm_file *file_priv);
+int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
+			     struct drm_file *file_priv);
+int i915_gem_execbuffer(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
+		       struct drm_file *file_priv);
+int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
+			 struct drm_file *file_priv);
+int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
+			    struct drm_file *file_priv);
+int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
+			   struct drm_file *file_priv);
+int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
+			   struct drm_file *file_priv);
+int i915_gem_set_tiling(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+int i915_gem_get_tiling(struct drm_device *dev, void *data,
+			struct drm_file *file_priv);
+void i915_gem_load(struct drm_device *dev);
+int i915_gem_proc_init(struct drm_minor *minor);
+void i915_gem_proc_cleanup(struct drm_minor *minor);
+int i915_gem_init_object(struct drm_gem_object *obj);
+void i915_gem_free_object(struct drm_gem_object *obj);
+int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
+void i915_gem_object_unpin(struct drm_gem_object *obj);
+void i915_gem_lastclose(struct drm_device *dev);
+uint32_t i915_get_gem_seqno(struct drm_device *dev);
+void i915_gem_retire_requests(struct drm_device *dev);
+void i915_gem_retire_work_handler(struct work_struct *work);
+void i915_gem_clflush_object(struct drm_gem_object *obj);
+
+/* i915_gem_tiling.c */
+void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
+
+/* i915_gem_debug.c */
+void i915_gem_dump_object(struct drm_gem_object *obj, int len,
+			  const char *where, uint32_t mark);
+#if WATCH_INACTIVE
+void i915_verify_inactive(struct drm_device *dev, char *file, int line);
+#else
+#define i915_verify_inactive(dev, file, line)
 #endif
+void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
+void i915_gem_dump_object(struct drm_gem_object *obj, int len,
+			  const char *where, uint32_t mark);
+void i915_dump_lru(struct drm_device *dev, const char *where);
+#endif /* I915_HAVE_GEM */
+
+/* i915_suspend.c */
+extern int i915_save_state(struct drm_device *dev);
+extern int i915_restore_state(struct drm_device *dev);
+
+/* i915_opregion.c */
+extern int intel_opregion_init(struct drm_device *dev);
+extern void intel_opregion_free(struct drm_device *dev);
+extern void opregion_asle_intr(struct drm_device *dev);
+extern void opregion_enable_asle(struct drm_device *dev);
 
-#ifdef I915_HAVE_BUFFER
-/* i915_buffer.c */
-extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev);
-extern int i915_fence_type(struct drm_buffer_object *bo, uint32_t *fclass,
-			   uint32_t *type);
-extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
-extern int i915_init_mem_type(struct drm_device *dev, uint32_t type,
-			       struct drm_mem_type_manager *man);
-extern uint64_t i915_evict_flags(struct drm_buffer_object *bo);
-extern int i915_move(struct drm_buffer_object *bo, int evict,
-		int no_wait, struct drm_bo_mem_reg *new_mem);
-void i915_flush_ttm(struct drm_ttm *ttm);
-#endif
+/**
+ * Lock test for when it's just for synchronization of ring access.
+ *
+ * In that case, we don't need to do it when GEM is initialized as nobody else
+ * has access to the ring.
+ */
+#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {			\
+	if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
+		LOCK_TEST_WITH_RETURN(dev, file_priv);			\
+} while (0)
 
-#ifdef __linux__
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
-extern void intel_init_chipset_flush_compat(struct drm_device *dev);
-extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
-#endif
+#if defined(__FreeBSD__) || defined(__DragonFly__)
+typedef boolean_t bool;
 #endif
 
-#define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
-#define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
+#define I915_READ(reg)		DRM_READ32(dev_priv->mmio_map, (reg))
+#define I915_WRITE(reg,val)	DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
 #define I915_READ16(reg)	DRM_READ16(dev_priv->mmio_map, (reg))
 #define I915_WRITE16(reg,val)	DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
+#define I915_READ8(reg)		DRM_READ8(dev_priv->mmio_map, (reg))
+#define I915_WRITE8(reg,val)	DRM_WRITE8(dev_priv->mmio_map, (reg), (val))
 
 #define I915_VERBOSE 0
 
 #define RING_LOCALS	unsigned int outring, ringmask, outcount; \
-			volatile char *virt;
+                        volatile char *virt;
 
 #define BEGIN_LP_RING(n) do {				\
 	if (I915_VERBOSE)				\
-		DRM_DEBUG("BEGIN_LP_RING(%d)\n",	\
-	                         (n));		        \
-	if (dev_priv->ring.space < (n)*4)                      \
-		i915_wait_ring(dev, (n)*4, __FUNCTION__);      \
+		DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));	\
+	if (dev_priv->ring.space < (n)*4)		\
+		i915_wait_ring(dev, (n)*4, __func__);		\
 	outcount = 0;					\
 	outring = dev_priv->ring.tail;			\
 	ringmask = dev_priv->ring.tail_mask;		\
@@ -346,8 +587,8 @@ extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
 
 #define OUT_RING(n) do {					\
 	if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
-	*(volatile unsigned int *)(virt + outring) = (n);		\
-	outcount++;						\
+	*(volatile unsigned int *)(virt + outring) = (n);	\
+        outcount++;						\
 	outring += 4;						\
 	outring &= ringmask;					\
 } while (0)
@@ -356,801 +597,30 @@ extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
 	if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);	\
 	dev_priv->ring.tail = outring;					\
 	dev_priv->ring.space -= outcount * 4;				\
-	I915_WRITE(LP_RING + RING_TAIL, outring);			\
+	I915_WRITE(PRB0_TAIL, outring);			\
 } while(0)
 
-extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
-
-/* Extended config space */
-#define LBB 0xf4
-
-/* VGA stuff */
-
-#define VGA_ST01_MDA 0x3ba
-#define VGA_ST01_CGA 0x3da
-
-#define VGA_MSR_WRITE 0x3c2
-#define VGA_MSR_READ 0x3cc
-#define   VGA_MSR_MEM_EN (1<<1)
-#define   VGA_MSR_CGA_MODE (1<<0)
-
-#define VGA_SR_INDEX 0x3c4
-#define VGA_SR_DATA 0x3c5
-
-#define VGA_AR_INDEX 0x3c0
-#define   VGA_AR_VID_EN (1<<5)
-#define VGA_AR_DATA_WRITE 0x3c0
-#define VGA_AR_DATA_READ 0x3c1
-
-#define VGA_GR_INDEX 0x3ce
-#define VGA_GR_DATA 0x3cf
-/* GR05 */
-#define   VGA_GR_MEM_READ_MODE_SHIFT 3
-#define     VGA_GR_MEM_READ_MODE_PLANE 1
-/* GR06 */
-#define   VGA_GR_MEM_MODE_MASK 0xc
-#define   VGA_GR_MEM_MODE_SHIFT 2
-#define   VGA_GR_MEM_A0000_AFFFF 0
-#define   VGA_GR_MEM_A0000_BFFFF 1
-#define   VGA_GR_MEM_B0000_B7FFF 2
-#define   VGA_GR_MEM_B0000_BFFFF 3
-
-#define VGA_DACMASK 0x3c6
-#define VGA_DACRX 0x3c7
-#define VGA_DACWX 0x3c8
-#define VGA_DACDATA 0x3c9
-
-#define VGA_CR_INDEX_MDA 0x3b4
-#define VGA_CR_DATA_MDA 0x3b5
-#define VGA_CR_INDEX_CGA 0x3d4
-#define VGA_CR_DATA_CGA 0x3d5
-
-#define GFX_OP_USER_INTERRUPT		((0<<29)|(2<<23))
-#define GFX_OP_BREAKPOINT_INTERRUPT	((0<<29)|(1<<23))
-#define CMD_REPORT_HEAD			(7<<23)
-#define CMD_STORE_DWORD_IDX		((0x21<<23) | 0x1)
-#define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
-
-#define CMD_MI_FLUSH         (0x04 << 23)
-#define MI_NO_WRITE_FLUSH    (1 << 2)
-#define MI_READ_FLUSH        (1 << 0)
-#define MI_EXE_FLUSH         (1 << 1)
-#define MI_END_SCENE         (1 << 4) /* flush binner and incr scene count */
-#define MI_SCENE_COUNT       (1 << 3) /* just increment scene count */
-
-/* Packet to load a register value from the ring/batch command stream:
- */
-#define CMD_MI_LOAD_REGISTER_IMM	((0x22 << 23)|0x1)
-
-#define BB1_START_ADDR_MASK   (~0x7)
-#define BB1_PROTECTED         (1<<0)
-#define BB1_UNPROTECTED       (0<<0)
-#define BB2_END_ADDR_MASK     (~0x7)
-
-/* Framebuffer compression */
-#define FBC_CFB_BASE		0x03200 /* 4k page aligned */
-#define FBC_LL_BASE		0x03204 /* 4k page aligned */
-#define FBC_CONTROL		0x03208
-#define   FBC_CTL_EN		(1<<31)
-#define   FBC_CTL_PERIODIC	(1<<30)
-#define   FBC_CTL_INTERVAL_SHIFT (16)
-#define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
-#define   FBC_CTL_STRIDE_SHIFT	(5)
-#define   FBC_CTL_FENCENO	(1<<0)
-#define FBC_COMMAND		0x0320c
-#define   FBC_CMD_COMPRESS	(1<<0)
-#define FBC_STATUS		0x03210
-#define   FBC_STAT_COMPRESSING	(1<<31)
-#define   FBC_STAT_COMPRESSED	(1<<30)
-#define   FBC_STAT_MODIFIED	(1<<29)
-#define   FBC_STAT_CURRENT_LINE	(1<<0)
-#define FBC_CONTROL2		0x03214
-#define   FBC_CTL_FENCE_DBL	(0<<4)
-#define   FBC_CTL_IDLE_IMM	(0<<2)
-#define   FBC_CTL_IDLE_FULL	(1<<2)
-#define   FBC_CTL_IDLE_LINE	(2<<2)
-#define   FBC_CTL_IDLE_DEBUG	(3<<2)
-#define   FBC_CTL_CPU_FENCE	(1<<1)
-#define   FBC_CTL_PLANEA	(0<<0)
-#define   FBC_CTL_PLANEB	(1<<0)
-#define FBC_FENCE_OFF		0x0321b
-
-#define FBC_LL_SIZE		(1536)
-#define FBC_LL_PAD		(32)
-
-/* Interrupt bits:
- */
-#define USER_INT_FLAG    (1<<1)
-#define VSYNC_PIPEB_FLAG (1<<5)
-#define VSYNC_PIPEA_FLAG (1<<7)
-#define HWB_OOM_FLAG     (1<<13) /* binner out of memory */
-
-#define I915REG_HWSTAM		0x02098
-#define I915REG_INT_IDENTITY_R	0x020a4
-#define I915REG_INT_MASK_R	0x020a8
-#define I915REG_INT_ENABLE_R	0x020a0
-#define I915REG_INSTPM	        0x020c0
-
-#define I915REG_PIPEASTAT	0x70024
-#define I915REG_PIPEBSTAT	0x71024
-
-#define I915_VBLANK_INTERRUPT_ENABLE	(1UL<<17)
-#define I915_VBLANK_CLEAR		(1UL<<1)
-
-#define SRX_INDEX		0x3c4
-#define SRX_DATA		0x3c5
-#define SR01			1
-#define SR01_SCREEN_OFF		(1<<5)
-
-#define PPCR			0x61204
-#define PPCR_ON			(1<<0)
-
-#define DVOB			0x61140
-#define DVOB_ON			(1<<31)
-#define DVOC			0x61160
-#define DVOC_ON			(1<<31)
-#define LVDS			0x61180
-#define LVDS_ON			(1<<31)
-
-#define ADPA			0x61100
-#define ADPA_DPMS_MASK		(~(3<<10))
-#define ADPA_DPMS_ON		(0<<10)
-#define ADPA_DPMS_SUSPEND	(1<<10)
-#define ADPA_DPMS_STANDBY	(2<<10)
-#define ADPA_DPMS_OFF		(3<<10)
-
-#define NOPID                   0x2094
-#define LP_RING			0x2030
-#define HP_RING			0x2040
-/* The binner has its own ring buffer:
- */
-#define HWB_RING		0x2400
-
-#define RING_TAIL		0x00
-#define TAIL_ADDR		0x001FFFF8
-#define RING_HEAD		0x04
-#define HEAD_WRAP_COUNT		0xFFE00000
-#define HEAD_WRAP_ONE		0x00200000
-#define HEAD_ADDR		0x001FFFFC
-#define RING_START		0x08
-#define START_ADDR		0x0xFFFFF000
-#define RING_LEN		0x0C
-#define RING_NR_PAGES		0x001FF000
-#define RING_REPORT_MASK	0x00000006
-#define RING_REPORT_64K		0x00000002
-#define RING_REPORT_128K	0x00000004
-#define RING_NO_REPORT		0x00000000
-#define RING_VALID_MASK		0x00000001
-#define RING_VALID		0x00000001
-#define RING_INVALID		0x00000000
-
-/* Instruction parser error reg:
- */
-#define IPEIR			0x2088
-
-/* Scratch pad debug 0 reg:
- */
-#define SCPD0			0x209c
-
-/* Error status reg:
- */
-#define ESR			0x20b8
-
-/* Secondary DMA fetch address debug reg:
- */
-#define DMA_FADD_S		0x20d4
-
-/* Cache mode 0 reg.
- *  - Manipulating render cache behaviour is central
- *    to the concept of zone rendering, tuning this reg can help avoid
- *    unnecessary render cache reads and even writes (for z/stencil)
- *    at beginning and end of scene.
- *
- * - To change a bit, write to this reg with a mask bit set and the
- * bit of interest either set or cleared.  EG: (BIT<<16) | BIT to set.
- */
-#define Cache_Mode_0		0x2120
-#define CM0_MASK_SHIFT          16
-#define CM0_IZ_OPT_DISABLE      (1<<6)
-#define CM0_ZR_OPT_DISABLE      (1<<5)
-#define CM0_DEPTH_EVICT_DISABLE (1<<4)
-#define CM0_COLOR_EVICT_DISABLE (1<<3)
-#define CM0_DEPTH_WRITE_DISABLE (1<<1)
-#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
-
-
-/* Graphics flush control.  A CPU write flushes the GWB of all writes.
- * The data is discarded.
- */
-#define GFX_FLSH_CNTL		0x2170
-
-/* Binner control.  Defines the location of the bin pointer list:
- */
-#define BINCTL			0x2420
-#define BC_MASK			(1 << 9)
-
-/* Binned scene info.
- */
-#define BINSCENE		0x2428
-#define BS_OP_LOAD		(1 << 8)
-#define BS_MASK			(1 << 22)
-
-/* Bin command parser debug reg:
- */
-#define BCPD			0x2480
-
-/* Bin memory control debug reg:
- */
-#define BMCD			0x2484
-
-/* Bin data cache debug reg:
- */
-#define BDCD			0x2488
-
-/* Binner pointer cache debug reg:
- */
-#define BPCD			0x248c
-
-/* Binner scratch pad debug reg:
- */
-#define BINSKPD			0x24f0
-
-/* HWB scratch pad debug reg:
- */
-#define HWBSKPD			0x24f4
-
-/* Binner memory pool reg:
- */
-#define BMP_BUFFER		0x2430
-#define BMP_PAGE_SIZE_4K	(0 << 10)
-#define BMP_BUFFER_SIZE_SHIFT	1
-#define BMP_ENABLE		(1 << 0)
-
-/* Get/put memory from the binner memory pool:
- */
-#define BMP_GET			0x2438
-#define BMP_PUT			0x2440
-#define BMP_OFFSET_SHIFT	5
-
-/* 3D state packets:
- */
-#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
-
-#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
-#define SC_UPDATE_SCISSOR       (0x1<<1)
-#define SC_ENABLE_MASK          (0x1<<0)
-#define SC_ENABLE               (0x1<<0)
-
-#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
-
-#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
-#define SCI_YMIN_MASK      (0xffff<<16)
-#define SCI_XMIN_MASK      (0xffff<<0)
-#define SCI_YMAX_MASK      (0xffff<<16)
-#define SCI_XMAX_MASK      (0xffff<<0)
-
-#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
-#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
-#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
-#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
-#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
-#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
-#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
-
-#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
-
-#define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
-#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
-#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
-#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
-
-#define MI_BATCH_BUFFER		((0x30<<23)|1)
-#define MI_BATCH_BUFFER_START	(0x31<<23)
-#define MI_BATCH_BUFFER_END	(0xA<<23)
-#define MI_BATCH_NON_SECURE	(1)
-
-#define MI_BATCH_NON_SECURE_I965 (1<<8)
-
-#define MI_WAIT_FOR_EVENT       ((0x3<<23))
-#define MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
-#define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
-#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
-
-#define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
-
-#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
-#define ASYNC_FLIP                (1<<22)
-#define DISPLAY_PLANE_A           (0<<20)
-#define DISPLAY_PLANE_B           (1<<20)
-
-/* Display regs */
-#define DSPACNTR                0x70180
-#define DSPBCNTR                0x71180
-#define DISPPLANE_SEL_PIPE_MASK                 (1<<24)
-
-/* Define the region of interest for the binner:
- */
-#define CMD_OP_BIN_CONTROL	 ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
-
-#define CMD_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
-
-#define BREADCRUMB_BITS 31
-#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
-
-#define READ_BREADCRUMB(dev_priv)  (((volatile u32*)(dev_priv->hw_status_page))[5])
-#define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
-
-#define BLC_PWM_CTL		0x61254
-#define BACKLIGHT_MODULATION_FREQ_SHIFT		(17)
-
-#define BLC_PWM_CTL2		0x61250
-/**
- * This is the most significant 15 bits of the number of backlight cycles in a
- * complete cycle of the modulated backlight control.
- *
- * The actual value is this field multiplied by two.
- */
-#define BACKLIGHT_MODULATION_FREQ_MASK		(0x7fff << 17)
-#define BLM_LEGACY_MODE				(1 << 16)
-/**
- * This is the number of cycles out of the backlight modulation cycle for which
- * the backlight is on.
- *
- * This field must be no greater than the number of cycles in the complete
- * backlight modulation cycle.
- */
-#define BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
-#define BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
-
-#define I915_GCFGC			0xf0
-#define I915_LOW_FREQUENCY_ENABLE		(1 << 7)
-#define I915_DISPLAY_CLOCK_190_200_MHZ		(0 << 4)
-#define I915_DISPLAY_CLOCK_333_MHZ		(4 << 4)
-#define I915_DISPLAY_CLOCK_MASK			(7 << 4)
-
-#define I855_HPLLCC			0xc0
-#define I855_CLOCK_CONTROL_MASK			(3 << 0)
-#define I855_CLOCK_133_200			(0 << 0)
-#define I855_CLOCK_100_200			(1 << 0)
-#define I855_CLOCK_100_133			(2 << 0)
-#define I855_CLOCK_166_250			(3 << 0)
-
-/* p317, 319
- */
-#define VCLK2_VCO_M        0x6008 /* treat as 16 bit? (includes msbs) */
-#define VCLK2_VCO_N        0x600a
-#define VCLK2_VCO_DIV_SEL  0x6012
-
-#define VCLK_DIVISOR_VGA0   0x6000
-#define VCLK_DIVISOR_VGA1   0x6004
-#define VCLK_POST_DIV	    0x6010
-/** Selects a post divisor of 4 instead of 2. */
-# define VGA1_PD_P2_DIV_4	(1 << 15)
-/** Overrides the p2 post divisor field */
-# define VGA1_PD_P1_DIV_2	(1 << 13)
-# define VGA1_PD_P1_SHIFT	8
-/** P1 value is 2 greater than this field */
-# define VGA1_PD_P1_MASK	(0x1f << 8)
-/** Selects a post divisor of 4 instead of 2. */
-# define VGA0_PD_P2_DIV_4	(1 << 7)
-/** Overrides the p2 post divisor field */
-# define VGA0_PD_P1_DIV_2	(1 << 5)
-# define VGA0_PD_P1_SHIFT	0
-/** P1 value is 2 greater than this field */
-# define VGA0_PD_P1_MASK	(0x1f << 0)
-
-/* I830 CRTC registers */
-#define HTOTAL_A	0x60000
-#define HBLANK_A	0x60004
-#define HSYNC_A		0x60008
-#define VTOTAL_A	0x6000c
-#define VBLANK_A	0x60010
-#define VSYNC_A		0x60014
-#define PIPEASRC	0x6001c
-#define BCLRPAT_A	0x60020
-#define VSYNCSHIFT_A	0x60028
-
-#define HTOTAL_B	0x61000
-#define HBLANK_B	0x61004
-#define HSYNC_B		0x61008
-#define VTOTAL_B	0x6100c
-#define VBLANK_B	0x61010
-#define VSYNC_B		0x61014
-#define PIPEBSRC	0x6101c
-#define BCLRPAT_B	0x61020
-#define VSYNCSHIFT_B	0x61028
-
-#define PP_STATUS	0x61200
-# define PP_ON					(1 << 31)
-/**
- * Indicates that all dependencies of the panel are on:
- *
- * - PLL enabled
- * - pipe enabled
- * - LVDS/DVOB/DVOC on
- */
-# define PP_READY				(1 << 30)
-# define PP_SEQUENCE_NONE			(0 << 28)
-# define PP_SEQUENCE_ON				(1 << 28)
-# define PP_SEQUENCE_OFF			(2 << 28)
-# define PP_SEQUENCE_MASK			0x30000000
-#define PP_CONTROL	0x61204
-# define POWER_TARGET_ON			(1 << 0)
-
-#define LVDSPP_ON       0x61208
-#define LVDSPP_OFF      0x6120c
-#define PP_CYCLE        0x61210
-
-#define PFIT_CONTROL	0x61230
-# define PFIT_ENABLE				(1 << 31)
-# define PFIT_PIPE_MASK				(3 << 29)
-# define PFIT_PIPE_SHIFT			29
-# define VERT_INTERP_DISABLE			(0 << 10)
-# define VERT_INTERP_BILINEAR			(1 << 10)
-# define VERT_INTERP_MASK			(3 << 10)
-# define VERT_AUTO_SCALE			(1 << 9)
-# define HORIZ_INTERP_DISABLE			(0 << 6)
-# define HORIZ_INTERP_BILINEAR			(1 << 6)
-# define HORIZ_INTERP_MASK			(3 << 6)
-# define HORIZ_AUTO_SCALE			(1 << 5)
-# define PANEL_8TO6_DITHER_ENABLE		(1 << 3)
-
-#define PFIT_PGM_RATIOS	0x61234
-# define PFIT_VERT_SCALE_MASK			0xfff00000
-# define PFIT_HORIZ_SCALE_MASK			0x0000fff0
-
-#define PFIT_AUTO_RATIOS	0x61238
-
-
-#define DPLL_A		0x06014
-#define DPLL_B		0x06018
-# define DPLL_VCO_ENABLE			(1 << 31)
-# define DPLL_DVO_HIGH_SPEED			(1 << 30)
-# define DPLL_SYNCLOCK_ENABLE			(1 << 29)
-# define DPLL_VGA_MODE_DIS			(1 << 28)
-# define DPLLB_MODE_DAC_SERIAL			(1 << 26) /* i915 */
-# define DPLLB_MODE_LVDS			(2 << 26) /* i915 */
-# define DPLL_MODE_MASK				(3 << 26)
-# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10	(0 << 24) /* i915 */
-# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5		(1 << 24) /* i915 */
-# define DPLLB_LVDS_P2_CLOCK_DIV_14		(0 << 24) /* i915 */
-# define DPLLB_LVDS_P2_CLOCK_DIV_7		(1 << 24) /* i915 */
-# define DPLL_P2_CLOCK_DIV_MASK			0x03000000 /* i915 */
-# define DPLL_FPA01_P1_POST_DIV_MASK		0x00ff0000 /* i915 */
-/**
- *  The i830 generation, in DAC/serial mode, defines p1 as two plus this
- * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
- */
-# define DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
-/**
- * The i830 generation, in LVDS mode, defines P1 as the bit number set within
- * this field (only one bit may be set).
- */
-# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
-# define DPLL_FPA01_P1_POST_DIV_SHIFT		16
-# define PLL_P2_DIVIDE_BY_4			(1 << 23) /* i830, required in DVO non-gang */
-# define PLL_P1_DIVIDE_BY_TWO			(1 << 21) /* i830 */
-# define PLL_REF_INPUT_DREFCLK			(0 << 13)
-# define PLL_REF_INPUT_TVCLKINA			(1 << 13) /* i830 */
-# define PLL_REF_INPUT_TVCLKINBC		(2 << 13) /* SDVO TVCLKIN */
-# define PLLB_REF_INPUT_SPREADSPECTRUMIN	(3 << 13)
-# define PLL_REF_INPUT_MASK			(3 << 13)
-# define PLL_LOAD_PULSE_PHASE_SHIFT		9
-/*
- * Parallel to Serial Load Pulse phase selection.
- * Selects the phase for the 10X DPLL clock for the PCIe
- * digital display port. The range is 4 to 13; 10 or more
- * is just a flip delay. The default is 6
- */
-# define PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
-# define DISPLAY_RATE_SELECT_FPA1		(1 << 8)
-
-/**
- * SDVO multiplier for 945G/GM. Not used on 965.
- *
- * \sa DPLL_MD_UDI_MULTIPLIER_MASK
- */
-# define SDVO_MULTIPLIER_MASK			0x000000ff
-# define SDVO_MULTIPLIER_SHIFT_HIRES		4
-# define SDVO_MULTIPLIER_SHIFT_VGA		0
-
-/** @defgroup DPLL_MD
- * @{
- */
-/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
-#define DPLL_A_MD		0x0601c
-/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
-#define DPLL_B_MD		0x06020
-/**
- * UDI pixel divider, controlling how many pixels are stuffed into a packet.
- *
- * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
- */
-# define DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
-# define DPLL_MD_UDI_DIVIDER_SHIFT		24
-/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
-# define DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
-# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
-/**
- * SDVO/UDI pixel multiplier.
- *
- * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
- * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
- * modes, the bus rate would be below the limits, so SDVO allows for stuffing
- * dummy bytes in the datastream at an increased clock rate, with both sides of
- * the link knowing how many bytes are fill.
- *
- * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
- * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
- * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
- * through an SDVO command.
- *
- * This register field has values of multiplication factor minus 1, with
- * a maximum multiplier of 5 for SDVO.
- */
-# define DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
-# define DPLL_MD_UDI_MULTIPLIER_SHIFT		8
-/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
- * This best be set to the default value (3) or the CRT won't work. No,
- * I don't entirely understand what this does...
- */
-# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
-# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
-/** @} */
-
-#define DPLL_TEST		0x606c
-# define DPLLB_TEST_SDVO_DIV_1			(0 << 22)
-# define DPLLB_TEST_SDVO_DIV_2			(1 << 22)
-# define DPLLB_TEST_SDVO_DIV_4			(2 << 22)
-# define DPLLB_TEST_SDVO_DIV_MASK		(3 << 22)
-# define DPLLB_TEST_N_BYPASS			(1 << 19)
-# define DPLLB_TEST_M_BYPASS			(1 << 18)
-# define DPLLB_INPUT_BUFFER_ENABLE		(1 << 16)
-# define DPLLA_TEST_N_BYPASS			(1 << 3)
-# define DPLLA_TEST_M_BYPASS			(1 << 2)
-# define DPLLA_INPUT_BUFFER_ENABLE		(1 << 0)
-
-#define ADPA			0x61100
-#define ADPA_DAC_ENABLE		(1<<31)
-#define ADPA_DAC_DISABLE	0
-#define ADPA_PIPE_SELECT_MASK	(1<<30)
-#define ADPA_PIPE_A_SELECT	0
-#define ADPA_PIPE_B_SELECT	(1<<30)
-#define ADPA_USE_VGA_HVPOLARITY (1<<15)
-#define ADPA_SETS_HVPOLARITY	0
-#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
-#define ADPA_VSYNC_CNTL_ENABLE	0
-#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
-#define ADPA_HSYNC_CNTL_ENABLE	0
-#define ADPA_VSYNC_ACTIVE_HIGH	(1<<4)
-#define ADPA_VSYNC_ACTIVE_LOW	0
-#define ADPA_HSYNC_ACTIVE_HIGH	(1<<3)
-#define ADPA_HSYNC_ACTIVE_LOW	0
-
-#define FPA0		0x06040
-#define FPA1		0x06044
-#define FPB0		0x06048
-#define FPB1		0x0604c
-# define FP_N_DIV_MASK				0x003f0000
-# define FP_N_DIV_SHIFT				16
-# define FP_M1_DIV_MASK				0x00003f00
-# define FP_M1_DIV_SHIFT			8
-# define FP_M2_DIV_MASK				0x0000003f
-# define FP_M2_DIV_SHIFT			0
-
-
-#define PORT_HOTPLUG_EN		0x61110
-# define SDVOB_HOTPLUG_INT_EN			(1 << 26)
-# define SDVOC_HOTPLUG_INT_EN			(1 << 25)
-# define TV_HOTPLUG_INT_EN			(1 << 18)
-# define CRT_HOTPLUG_INT_EN			(1 << 9)
-# define CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
-
-#define PORT_HOTPLUG_STAT	0x61114
-# define CRT_HOTPLUG_INT_STATUS			(1 << 11)
-# define TV_HOTPLUG_INT_STATUS			(1 << 10)
-# define CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
-# define CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
-# define CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
-# define CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
-# define SDVOC_HOTPLUG_INT_STATUS		(1 << 7)
-# define SDVOB_HOTPLUG_INT_STATUS		(1 << 6)
-
-#define SDVOB			0x61140
-#define SDVOC			0x61160
-#define SDVO_ENABLE				(1 << 31)
-#define SDVO_PIPE_B_SELECT			(1 << 30)
-#define SDVO_STALL_SELECT			(1 << 29)
-#define SDVO_INTERRUPT_ENABLE			(1 << 26)
 /**
- * 915G/GM SDVO pixel multiplier.
- *
- * Programmed value is multiplier - 1, up to 5x.
+ * Reads a dword out of the status page, which is written to from the command
+ * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
+ * MI_STORE_DATA_IMM.
  *
- * \sa DPLL_MD_UDI_MULTIPLIER_MASK
- */
-#define SDVO_PORT_MULTIPLY_MASK			(7 << 23)
-#define SDVO_PORT_MULTIPLY_SHIFT		23
-#define SDVO_PHASE_SELECT_MASK			(15 << 19)
-#define SDVO_PHASE_SELECT_DEFAULT		(6 << 19)
-#define SDVO_CLOCK_OUTPUT_INVERT		(1 << 18)
-#define SDVOC_GANG_MODE				(1 << 16)
-#define SDVO_BORDER_ENABLE			(1 << 7)
-#define SDVOB_PCIE_CONCURRENCY			(1 << 3)
-#define SDVO_DETECTED				(1 << 2)
-/* Bits to be preserved when writing */
-#define SDVOB_PRESERVE_MASK			((1 << 17) | (1 << 16) | (1 << 14))
-#define SDVOC_PRESERVE_MASK			(1 << 17)
-
-/** @defgroup LVDS
- * @{
- */
-/**
- * This register controls the LVDS output enable, pipe selection, and data
- * format selection.
+ * The following dwords have a reserved meaning:
+ * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
+ * 0x04: ring 0 head pointer
+ * 0x05: ring 1 head pointer (915-class)
+ * 0x06: ring 2 head pointer (915-class)
+ * 0x10-0x1b: Context status DWords (GM45)
+ * 0x1f: Last written status offset. (GM45)
  *
- * All of the clock/data pairs are force powered down by power sequencing.
- */
-#define LVDS			0x61180
-/**
- * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
- * the DPLL semantics change when the LVDS is assigned to that pipe.
- */
-# define LVDS_PORT_EN			(1 << 31)
-/** Selects pipe B for LVDS data.  Must be set on pre-965. */
-# define LVDS_PIPEB_SELECT		(1 << 30)
-
-/**
- * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
- * pixel.
- */
-# define LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
-# define LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
-# define LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
-/**
- * Controls the A3 data pair, which contains the additional LSBs for 24 bit
- * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
- * on.
- */
-# define LVDS_A3_POWER_MASK		(3 << 6)
-# define LVDS_A3_POWER_DOWN		(0 << 6)
-# define LVDS_A3_POWER_UP		(3 << 6)
-/**
- * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
- * is set.
+ * The area from dword 0x20 to 0x3ff is available for driver usage.
  */
-# define LVDS_CLKB_POWER_MASK		(3 << 4)
-# define LVDS_CLKB_POWER_DOWN		(0 << 4)
-# define LVDS_CLKB_POWER_UP		(3 << 4)
-
-/**
- * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
- * setting for whether we are in dual-channel mode.  The B3 pair will
- * additionally only be powered up when LVDS_A3_POWER_UP is set.
- */
-# define LVDS_B0B3_POWER_MASK		(3 << 2)
-# define LVDS_B0B3_POWER_DOWN		(0 << 2)
-# define LVDS_B0B3_POWER_UP		(3 << 2)
-
-#define PIPEACONF 0x70008
-#define PIPEACONF_ENABLE	(1<<31)
-#define PIPEACONF_DISABLE	0
-#define PIPEACONF_DOUBLE_WIDE	(1<<30)
-#define I965_PIPECONF_ACTIVE	(1<<30)
-#define PIPEACONF_SINGLE_WIDE	0
-#define PIPEACONF_PIPE_UNLOCKED 0
-#define PIPEACONF_PIPE_LOCKED	(1<<25)
-#define PIPEACONF_PALETTE	0
-#define PIPEACONF_GAMMA		(1<<24)
-#define PIPECONF_FORCE_BORDER	(1<<25)
-#define PIPECONF_PROGRESSIVE	(0 << 21)
-#define PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
-#define PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
-
-#define PIPEBCONF 0x71008
-#define PIPEBCONF_ENABLE	(1<<31)
-#define PIPEBCONF_DISABLE	0
-#define PIPEBCONF_DOUBLE_WIDE	(1<<30)
-#define PIPEBCONF_DISABLE	0
-#define PIPEBCONF_GAMMA		(1<<24)
-#define PIPEBCONF_PALETTE	0
-
-#define PIPEBGCMAXRED		0x71010
-#define PIPEBGCMAXGREEN		0x71014
-#define PIPEBGCMAXBLUE		0x71018
-#define PIPEBSTAT		0x71024
-#define PIPEBFRAMEHIGH		0x71040
-#define PIPEBFRAMEPIXEL		0x71044
-
-#define DSPACNTR		0x70180
-#define DSPBCNTR		0x71180
-#define DISPLAY_PLANE_ENABLE			(1<<31)
-#define DISPLAY_PLANE_DISABLE			0
-#define DISPPLANE_GAMMA_ENABLE			(1<<30)
-#define DISPPLANE_GAMMA_DISABLE			0
-#define DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
-#define DISPPLANE_8BPP				(0x2<<26)
-#define DISPPLANE_15_16BPP			(0x4<<26)
-#define DISPPLANE_16BPP				(0x5<<26)
-#define DISPPLANE_32BPP_NO_ALPHA		(0x6<<26)
-#define DISPPLANE_32BPP				(0x7<<26)
-#define DISPPLANE_STEREO_ENABLE			(1<<25)
-#define DISPPLANE_STEREO_DISABLE		0
-#define DISPPLANE_SEL_PIPE_MASK			(1<<24)
-#define DISPPLANE_SEL_PIPE_A			0
-#define DISPPLANE_SEL_PIPE_B			(1<<24)
-#define DISPPLANE_SRC_KEY_ENABLE		(1<<22)
-#define DISPPLANE_SRC_KEY_DISABLE		0
-#define DISPPLANE_LINE_DOUBLE			(1<<20)
-#define DISPPLANE_NO_LINE_DOUBLE		0
-#define DISPPLANE_STEREO_POLARITY_FIRST		0
-#define DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
-/* plane B only */
-#define DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
-#define DISPPLANE_ALPHA_TRANS_DISABLE		0
-#define DISPPLANE_SPRITE_ABOVE_DISPLAYA		0
-#define DISPPLANE_SPRITE_ABOVE_OVERLAY		(1)
-
-#define DSPABASE		0x70184
-#define DSPASTRIDE		0x70188
-
-#define DSPBBASE		0x71184
-#define DSPBADDR		DSPBBASE
-#define DSPBSTRIDE		0x71188
-
-#define DSPAKEYVAL		0x70194
-#define DSPAKEYMASK		0x70198
-
-#define DSPAPOS			0x7018C /* reserved */
-#define DSPASIZE		0x70190
-#define DSPBPOS			0x7118C
-#define DSPBSIZE		0x71190
-
-#define DSPASURF		0x7019C
-#define DSPATILEOFF		0x701A4
-
-#define DSPBSURF		0x7119C
-#define DSPBTILEOFF		0x711A4
-
-#define VGACNTRL		0x71400
-# define VGA_DISP_DISABLE			(1 << 31)
-# define VGA_2X_MODE				(1 << 30)
-# define VGA_PIPE_B_SELECT			(1 << 29)
-
-/*
- * Some BIOS scratch area registers.  The 845 (and 830?) store the amount
- * of video memory available to the BIOS in SWF1.
- */
-
-#define SWF0			0x71410
-
-/*
- * 855 scratch registers.
- */
-#define SWF10			0x70410
-
-#define SWF30			0x72414
-
-/*
- * Overlay registers.  These are overlay registers accessed via MMIO.
- * Those loaded via the overlay register page are defined in i830_video.c.
- */
-#define OVADD			0x30000
-
-#define DOVSTA			0x30008
-#define OC_BUF			(0x3<<20)
+#define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
+#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
+#define I915_GEM_HWS_INDEX		0x20
+#define I915_BREADCRUMB_INDEX		0x21
 
-#define OGAMC5			0x30010
-#define OGAMC4			0x30014
-#define OGAMC3			0x30018
-#define OGAMC2			0x3001c
-#define OGAMC1			0x30020
-#define OGAMC0			0x30024
-/*
- * Palette registers
- */
-#define PALETTE_A		0x0a000
-#define PALETTE_B		0x0a800
+extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
@@ -1158,20 +628,31 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 
-#define IS_I915G(dev) (dev->pci_device == 0x2582)/* || dev->pci_device == PCI_DEVICE_ID_INTELPCI_CHIP_E7221_G)*/
+#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
-#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2)
-
+#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
+		        (dev)->pci_device == 0x27AE)
 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 		       (dev)->pci_device == 0x2982 || \
 		       (dev)->pci_device == 0x2992 || \
 		       (dev)->pci_device == 0x29A2 || \
 		       (dev)->pci_device == 0x2A02 || \
-		       (dev)->pci_device == 0x2A12)
+		       (dev)->pci_device == 0x2A12 || \
+		       (dev)->pci_device == 0x2A42 || \
+		       (dev)->pci_device == 0x2E02 || \
+		       (dev)->pci_device == 0x2E12 || \
+		       (dev)->pci_device == 0x2E22)
 
 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 
+#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
+
+#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
+		     (dev)->pci_device == 0x2E12 || \
+		     (dev)->pci_device == 0x2E22 || \
+		     IS_GM45(dev))
+
 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||	\
 			(dev)->pci_device == 0x29B2 ||	\
 			(dev)->pci_device == 0x29D2)
@@ -1180,7 +661,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 		      IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
 
 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
-			IS_I945GM(dev) || IS_I965GM(dev))
+			IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
+
+#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 
diff --git a/sys/dev/drm/i915_irq.c b/sys/dev/drm/i915_irq.c
index fd5b235a36..36dbfb3e36 100644
--- a/sys/dev/drm/i915_irq.c
+++ b/sys/dev/drm/i915_irq.c
@@ -1,6 +1,6 @@
 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
  */
-/*
+/*-
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
  *
@@ -24,461 +24,339 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * $DragonFly: src/sys/dev/drm/i915_irq.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "i915_drm.h"
-#include "i915_drv.h"
-
-#define USER_INT_FLAG (1<<1)
-#define VSYNC_PIPEB_FLAG (1<<5)
-#define VSYNC_PIPEA_FLAG (1<<7)
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/i915_drm.h"
+#include "dev/drm/i915_drv.h"
 
 #define MAX_NOPID ((u32)~0)
 
 /**
- * i915_get_pipe - return the the pipe associated with a given plane
- * @dev: DRM device
- * @plane: plane to look for
+ * Interrupts that are always left unmasked.
  *
- * We need to get the pipe associated with a given plane to correctly perform
- * vblank driven swapping, and they may not always be equal.  So look up the
- * pipe associated with @plane here.
+ * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
+ * we leave them always unmasked in IMR and then control enabling them through
+ * PIPESTAT alone.
  */
-static int
-i915_get_pipe(struct drm_device *dev, int plane)
+#define I915_INTERRUPT_ENABLE_FIX	(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
+				   	 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
+
+/** Interrupts that we mask and unmask at runtime. */
+#define I915_INTERRUPT_ENABLE_VAR	(I915_USER_INTERRUPT)
+
+/** These are all of the interrupts used by the driver */
+#define I915_INTERRUPT_ENABLE_MASK	(I915_INTERRUPT_ENABLE_FIX | \
+				    	 I915_INTERRUPT_ENABLE_VAR)
+
+#define I915_PIPE_VBLANK_STATUS		(PIPE_START_VBLANK_INTERRUPT_STATUS |\
+					 PIPE_VBLANK_INTERRUPT_STATUS)
+ 
+#define I915_PIPE_VBLANK_ENABLE		(PIPE_START_VBLANK_INTERRUPT_ENABLE |\
+					 PIPE_VBLANK_INTERRUPT_ENABLE)
+  
+#define DRM_I915_VBLANK_PIPE_ALL	(DRM_I915_VBLANK_PIPE_A | \
+					 DRM_I915_VBLANK_PIPE_B)
+
+static inline void
+i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 {
-	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	u32 dspcntr;
-
-	dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
+	mask &= I915_INTERRUPT_ENABLE_VAR;
+	if ((dev_priv->irq_mask_reg & mask) != 0) {
+		dev_priv->irq_mask_reg &= ~mask;
+		I915_WRITE(IMR, dev_priv->irq_mask_reg);
+		(void) I915_READ(IMR);
+	}
+}
 
-	return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
+static inline void
+i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
+{
+	mask &= I915_INTERRUPT_ENABLE_VAR;
+	if ((dev_priv->irq_mask_reg & mask) != mask) {
+		dev_priv->irq_mask_reg |= mask;
+		I915_WRITE(IMR, dev_priv->irq_mask_reg);
+		(void) I915_READ(IMR);
+	}
 }
 
-/**
- * Emit a synchronous flip.
- *
- * This function must be called with the drawable spinlock held.
- */
-static void
-i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
-			 int plane)
+static inline u32
+i915_pipestat(int pipe)
 {
-	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	u16 x1, y1, x2, y2;
-	int pf_planes = 1 << plane;
+	if (pipe == 0)
+	    return PIPEASTAT;
+	if (pipe == 1)
+	    return PIPEBSTAT;
+	return -EINVAL;
+}
 
-	DRM_SPINLOCK_ASSERT(&dev->drw_lock);
+void
+i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
+{
+	if ((dev_priv->pipestat[pipe] & mask) != mask) {
+		u32 reg = i915_pipestat(pipe);
 
-	/* If the window is visible on the other plane, we have to flip on that
-	 * plane as well.
-	 */
-	if (plane == 1) {
-		x1 = sarea_priv->planeA_x;
-		y1 = sarea_priv->planeA_y;
-		x2 = x1 + sarea_priv->planeA_w;
-		y2 = y1 + sarea_priv->planeA_h;
-	} else {
-		x1 = sarea_priv->planeB_x;
-		y1 = sarea_priv->planeB_y;
-		x2 = x1 + sarea_priv->planeB_w;
-		y2 = y1 + sarea_priv->planeB_h;
+		dev_priv->pipestat[pipe] |= mask;
+		/* Enable the interrupt, clear any pending status */
+		I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
+		(void) I915_READ(reg);
 	}
+}
 
-	if (x2 > 0 && y2 > 0) {
-		int i, num_rects = drw->num_rects;
-		struct drm_clip_rect *rect = drw->rects;
-
-		for (i = 0; i < num_rects; i++)
-			if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
-			      rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
-				pf_planes = 0x3;
+void
+i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
+{
+	if ((dev_priv->pipestat[pipe] & mask) != 0) {
+		u32 reg = i915_pipestat(pipe);
 
-				break;
-			}
+		dev_priv->pipestat[pipe] &= ~mask;
+		I915_WRITE(reg, dev_priv->pipestat[pipe]);
+		(void) I915_READ(reg);
 	}
-
-	i915_dispatch_flip(dev, pf_planes, 1);
 }
 
 /**
- * Emit blits for scheduled buffer swaps.
+ * i915_pipe_enabled - check if a pipe is enabled
+ * @dev: DRM device
+ * @pipe: pipe to check
  *
- * This function will be called with the HW lock held.
+ * Reading certain registers when the pipe is disabled can hang the chip.
+ * Use this routine to make sure the PLL is running and the pipe is active
+ * before reading such registers if unsure.
  */
-static void i915_vblank_tasklet(struct drm_device *dev)
+static int
+i915_pipe_enabled(struct drm_device *dev, int pipe)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	struct list_head *list, *tmp, hits, *hit;
-	int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
-	unsigned counter[2] = { atomic_read(&dev->vbl_received),
-				atomic_read(&dev->vbl_received2) };
-	struct drm_drawable_info *drw;
-	drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	u32 cpp = dev_priv->cpp,  offsets[3];
-	u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
-				XY_SRC_COPY_BLT_WRITE_ALPHA |
-				XY_SRC_COPY_BLT_WRITE_RGB)
-			     : XY_SRC_COPY_BLT_CMD;
-	u32 pitchropcpp = (sarea_priv->pitch * cpp) | (0xcc << 16) |
-			  (cpp << 23) | (1 << 24);
-	RING_LOCALS;
-
-	DRM_DEBUG("\n");
-
-	INIT_LIST_HEAD(&hits);
-
-	nhits = nrects = 0;
+	unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 
-	/* No irqsave/restore necessary.  This tasklet may be run in an
-	 * interrupt context or normal context, but we don't have to worry
-	 * about getting interrupted by something acquiring the lock, because
-	 * we are the interrupt context thing that acquires the lock.
-	 */
-	DRM_SPINLOCK(&dev_priv->swaps_lock);
-
-	/* Find buffer swaps scheduled for this vertical blank */
-	list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
-		drm_i915_vbl_swap_t *vbl_swap =
-			list_entry(list, drm_i915_vbl_swap_t, head);
-		int pipe = i915_get_pipe(dev, vbl_swap->plane);
-
-		if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
-			continue;
-
-		list_del(list);
-		dev_priv->swaps_pending--;
-
-		DRM_SPINUNLOCK(&dev_priv->swaps_lock);
-		DRM_SPINLOCK(&dev->drw_lock);
-
-		drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
-
-		if (!drw) {
-			DRM_SPINUNLOCK(&dev->drw_lock);
-			drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
-			DRM_SPINLOCK(&dev_priv->swaps_lock);
-			continue;
-		}
-
-		list_for_each(hit, &hits) {
-			drm_i915_vbl_swap_t *swap_cmp =
-				list_entry(hit, drm_i915_vbl_swap_t, head);
-			struct drm_drawable_info *drw_cmp =
-				drm_get_drawable_info(dev, swap_cmp->drw_id);
-
-			if (drw_cmp &&
-			    drw_cmp->rects[0].y1 > drw->rects[0].y1) {
-				list_add_tail(list, hit);
-				break;
-			}
-		}
-
-		DRM_SPINUNLOCK(&dev->drw_lock);
+	if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
+		return 1;
 
-		/* List of hits was empty, or we reached the end of it */
-		if (hit == &hits)
-			list_add_tail(list, hits.prev);
-
-		nhits++;
+	return 0;
+}
 
-		DRM_SPINLOCK(&dev_priv->swaps_lock);
-	}
+/* Called from drm generic code, passed a 'crtc', which
+ * we use as a pipe index
+ */
+u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	unsigned long high_frame;
+	unsigned long low_frame;
+	u32 high1, high2, low, count;
 
-	DRM_SPINUNLOCK(&dev_priv->swaps_lock);
+	high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
+	low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 
-	if (nhits == 0) {
-		return;
+	if (!i915_pipe_enabled(dev, pipe)) {
+		DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
+		return 0;
 	}
 
-	i915_kernel_lost_context(dev);
-
-	upper[0] = upper[1] = 0;
-	slice[0] = max(sarea_priv->planeA_h / nhits, 1);
-	slice[1] = max(sarea_priv->planeB_h / nhits, 1);
-	lower[0] = sarea_priv->planeA_y + slice[0];
-	lower[1] = sarea_priv->planeB_y + slice[0];
-
-	offsets[0] = sarea_priv->front_offset;
-	offsets[1] = sarea_priv->back_offset;
-	offsets[2] = sarea_priv->third_offset;
-	num_pages = sarea_priv->third_handle ? 3 : 2;
-
-	DRM_SPINLOCK(&dev->drw_lock);
-
-	/* Emit blits for buffer swaps, partitioning both outputs into as many
-	 * slices as there are buffer swaps scheduled in order to avoid tearing
-	 * (based on the assumption that a single buffer swap would always
-	 * complete before scanout starts).
+	/*
+	 * High & low register fields aren't synchronized, so make sure
+	 * we get a low value that's stable across two reads of the high
+	 * register.
 	 */
-	for (i = 0; i++ < nhits;
-	     upper[0] = lower[0], lower[0] += slice[0],
-	     upper[1] = lower[1], lower[1] += slice[1]) {
-		int init_drawrect = 1;
-
-		if (i == nhits)
-			lower[0] = lower[1] = sarea_priv->height;
-
-		list_for_each(hit, &hits) {
-			drm_i915_vbl_swap_t *swap_hit =
-				list_entry(hit, drm_i915_vbl_swap_t, head);
-			struct drm_clip_rect *rect;
-			int num_rects, plane, front, back;
-			unsigned short top, bottom;
-
-			drw = drm_get_drawable_info(dev, swap_hit->drw_id);
-
-			if (!drw)
-				continue;
-
-			plane = swap_hit->plane;
-
-			if (swap_hit->flip) {
-				i915_dispatch_vsync_flip(dev, drw, plane);
-				continue;
-			}
-
-			if (init_drawrect) {
-				BEGIN_LP_RING(6);
-
-				OUT_RING(GFX_OP_DRAWRECT_INFO);
-				OUT_RING(0);
-				OUT_RING(0);
-				OUT_RING(sarea_priv->width | sarea_priv->height << 16);
-				OUT_RING(sarea_priv->width | sarea_priv->height << 16);
-				OUT_RING(0);
-
-				ADVANCE_LP_RING();
-
-				sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
-
-				init_drawrect = 0;
-			}
-
-			rect = drw->rects;
-			top = upper[plane];
-			bottom = lower[plane];
-
-			front = (dev_priv->sarea_priv->pf_current_page >>
-				 (2 * plane)) & 0x3;
-			back = (front + 1) % num_pages;
-
-			for (num_rects = drw->num_rects; num_rects--; rect++) {
-				int y1 = max(rect->y1, top);
-				int y2 = min(rect->y2, bottom);
-
-				if (y1 >= y2)
-					continue;
-
-				BEGIN_LP_RING(8);
+	do {
+		high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
+			 PIPE_FRAME_HIGH_SHIFT);
+		low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
+			PIPE_FRAME_LOW_SHIFT);
+		high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
+			 PIPE_FRAME_HIGH_SHIFT);
+	} while (high1 != high2);
+
+	count = (high1 << 8) | low;
+
+	return count;
+}
 
-				OUT_RING(cmd);
-				OUT_RING(pitchropcpp);
-				OUT_RING((y1 << 16) | rect->x1);
-				OUT_RING((y2 << 16) | rect->x2);
-				OUT_RING(offsets[front]);
-				OUT_RING((y1 << 16) | rect->x1);
-				OUT_RING(pitchropcpp & 0xffff);
-				OUT_RING(offsets[back]);
+u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 
-				ADVANCE_LP_RING();
-			}
-		}
+	if (!i915_pipe_enabled(dev, pipe)) {
+		DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
+		return 0;
 	}
 
-	DRM_SPINUNLOCK(&dev->drw_lock);
-
-	list_for_each_safe(hit, tmp, &hits) {
-		drm_i915_vbl_swap_t *swap_hit =
-			list_entry(hit, drm_i915_vbl_swap_t, head);
-
-		list_del(hit);
-
-		drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
-	}
+	return I915_READ(reg);
 }
 
 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 {
 	struct drm_device *dev = (struct drm_device *) arg;
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	u16 temp;
+	u32 iir, new_iir;
 	u32 pipea_stats, pipeb_stats;
+	u32 vblank_status;
+	u32 vblank_enable;
+	int irq_received;
 
-	pipea_stats = I915_READ(I915REG_PIPEASTAT);
-	pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
+	atomic_inc(&dev_priv->irq_received);
 
-	temp = I915_READ16(I915REG_INT_IDENTITY_R);
-	temp &= (dev_priv->irq_enable_reg | USER_INT_FLAG);
+	iir = I915_READ(IIR);
 
-#if 0
-	DRM_DEBUG("flag=%08x\n", temp);
-#endif
-	if (temp == 0)
-		return IRQ_NONE;
+	if (IS_I965G(dev)) {
+		vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
+		vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
+	} else {
+		vblank_status = I915_VBLANK_INTERRUPT_STATUS;
+		vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
+	}
 
-	I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
-	(void) I915_READ16(I915REG_INT_IDENTITY_R);
-	DRM_READMEMORYBARRIER();
+	for (;;) {
+		irq_received = iir != 0;
 
-	dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
+		/* Can't rely on pipestat interrupt bit in iir as it might
+		 * have been cleared after the pipestat interrupt was received.
+		 * It doesn't set the bit in iir again, but it still produces
+		 * interrupts (for non-MSI).
+		 */
+		DRM_SPINLOCK(&dev_priv->user_irq_lock);
+		pipea_stats = I915_READ(PIPEASTAT);
+		pipeb_stats = I915_READ(PIPEBSTAT);
 
-	if (temp & USER_INT_FLAG) {
-		DRM_WAKEUP(&dev_priv->irq_queue);
-#ifdef I915_HAVE_FENCE
-		i915_fence_handler(dev);
-#endif
-	}
+		/*
+		 * Clear the PIPE(A|B)STAT regs before the IIR
+		 */
+		if (pipea_stats & 0x8000ffff) {
+			I915_WRITE(PIPEASTAT, pipea_stats);
+			irq_received = 1;
+		}
 
-	if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) {
-		int vblank_pipe = dev_priv->vblank_pipe;
-
-		if ((vblank_pipe &
-		     (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
-		    == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
-			if (temp & VSYNC_PIPEA_FLAG)
-				atomic_inc(&dev->vbl_received);
-			if (temp & VSYNC_PIPEB_FLAG)
-				atomic_inc(&dev->vbl_received2);
-		} else if (((temp & VSYNC_PIPEA_FLAG) &&
-			    (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
-			   ((temp & VSYNC_PIPEB_FLAG) &&
-			    (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
-			atomic_inc(&dev->vbl_received);
-
-		DRM_WAKEUP(&dev->vbl_queue);
-		drm_vbl_send_signals(dev);
-
-		if (dev_priv->swaps_pending > 0)
-			drm_locked_tasklet(dev, i915_vblank_tasklet);
-		I915_WRITE(I915REG_PIPEASTAT,
-			pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
-			I915_VBLANK_CLEAR);
-		I915_WRITE(I915REG_PIPEBSTAT,
-			pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
-			I915_VBLANK_CLEAR);
-	}
+		if (pipeb_stats & 0x8000ffff) {
+			I915_WRITE(PIPEBSTAT, pipeb_stats);
+			irq_received = 1;
+		}
+		DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
+
+		if (!irq_received)
+			break;
+
+		I915_WRITE(IIR, iir);
+		new_iir = I915_READ(IIR); /* Flush posted writes */
+
+		if (dev_priv->sarea_priv)
+			dev_priv->sarea_priv->last_dispatch =
+			    READ_BREADCRUMB(dev_priv);
+
+		if (iir & I915_USER_INTERRUPT) {
+			DRM_WAKEUP(&dev_priv->irq_queue);
+		}
 
-	return IRQ_HANDLED;
+		if (pipea_stats & vblank_status)
+			drm_handle_vblank(dev, 0);
+
+		if (pipeb_stats & vblank_status)
+			drm_handle_vblank(dev, 1);
+
+		/* With MSI, interrupts are only generated when iir
+		 * transitions from zero to nonzero.  If another bit got
+		 * set while we were handling the existing iir bits, then
+		 * we would never get another interrupt.
+		 *
+		 * This is fine on non-MSI as well, as if we hit this path
+		 * we avoid exiting the interrupt handler only to generate
+		 * another one.
+		 *
+		 * Note that for MSI this could cause a stray interrupt report
+		 * if an interrupt landed in the time between writing IIR and
+		 * the posting read.  This should be rare enough to never
+		 * trigger the 99% of 100,000 interrupts test for disabling
+		 * stray interrupts.
+		 */
+		iir = new_iir;
+	}
 }
 
-int i915_emit_irq(struct drm_device *dev)
+static int i915_emit_irq(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;
 
 	i915_kernel_lost_context(dev);
 
-	DRM_DEBUG("\n");
+	if (++dev_priv->counter > 0x7FFFFFFFUL)
+		dev_priv->counter = 0;
+	if (dev_priv->sarea_priv)
+		dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 
-	i915_emit_breadcrumb(dev);
+	DRM_DEBUG("emitting: %d\n", dev_priv->counter);
 
-	BEGIN_LP_RING(2);
-	OUT_RING(0);
-	OUT_RING(GFX_OP_USER_INTERRUPT);
+	BEGIN_LP_RING(4);
+	OUT_RING(MI_STORE_DWORD_INDEX);
+	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
+	OUT_RING(dev_priv->counter);
+	OUT_RING(MI_USER_INTERRUPT);
 	ADVANCE_LP_RING();
 
 	return dev_priv->counter;
 }
 
-void i915_user_irq_on(drm_i915_private_t *dev_priv)
+void i915_user_irq_get(struct drm_device *dev)
 {
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+	DRM_DEBUG("\n");
 	DRM_SPINLOCK(&dev_priv->user_irq_lock);
-	if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
-		dev_priv->irq_enable_reg |= USER_INT_FLAG;
-		I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
-	}
+	if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
+		i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 	DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
-
 }
 
-void i915_user_irq_off(drm_i915_private_t *dev_priv)
+void i915_user_irq_put(struct drm_device *dev)
 {
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
 	DRM_SPINLOCK(&dev_priv->user_irq_lock);
-	if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
-		/*
-		dev_priv->irq_enable_reg &= ~USER_INT_FLAG;
-		I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
-		*/
+	if (dev->irq_enabled) {
+		KASSERT(dev_priv->user_irq_refcount > 0, ("invalid refcount"));
+		if (--dev_priv->user_irq_refcount == 0)
+			i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 	}
 	DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 }
 
-
 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	int ret = 0;
 
+	if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
+		if (dev_priv->sarea_priv) {
+			dev_priv->sarea_priv->last_dispatch =
+				READ_BREADCRUMB(dev_priv);
+		}
+		return 0;
+	}
+
+	if (dev_priv->sarea_priv)
+		dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
+
 	DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 		  READ_BREADCRUMB(dev_priv));
 
-	if (READ_BREADCRUMB(dev_priv) >= irq_nr)
-		return 0;
-
-	i915_user_irq_on(dev_priv);
+	i915_user_irq_get(dev);
 	DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 		    READ_BREADCRUMB(dev_priv) >= irq_nr);
-	i915_user_irq_off(dev_priv);
+	i915_user_irq_put(dev);
+
+	if (ret == -ERESTART)
+		DRM_DEBUG("restarting syscall\n");
 
 	if (ret == -EBUSY) {
 		DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 			  READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 	}
 
-	dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 	return ret;
 }
 
-static int i915_driver_vblank_do_wait(struct drm_device *dev,
-				      unsigned int *sequence,
-				      atomic_t *counter)
-{
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	unsigned int cur_vblank;
-	int ret = 0;
-
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
-
-	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
-		    (((cur_vblank = atomic_read(counter))
-			- *sequence) <= (1<<23)));
-
-	*sequence = cur_vblank;
-
-	return ret;
-}
-
-int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
-{
-	atomic_t *counter;
-
-	if (i915_get_pipe(dev, 0) == 0)
-		counter = &dev->vbl_received;
-	else
-		counter = &dev->vbl_received2;
-	return i915_driver_vblank_do_wait(dev, sequence, counter);
-}
-
-int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
-{
-	atomic_t *counter;
-
-	if (i915_get_pipe(dev, 1) == 0)
-		counter = &dev->vbl_received;
-	else
-		counter = &dev->vbl_received2;
-
-	return i915_driver_vblank_do_wait(dev, sequence, counter);
-}
-
 /* Needs the lock as it touches the ring.
  */
 int i915_irq_emit(struct drm_device *dev, void *data,
@@ -488,13 +366,13 @@ int i915_irq_emit(struct drm_device *dev, void *data,
 	drm_i915_irq_emit_t *emit = data;
 	int result;
 
-	LOCK_TEST_WITH_RETURN(dev, file_priv);
-
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
 	}
 
+	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
+
 	result = i915_emit_irq(dev);
 
 	if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
@@ -508,7 +386,7 @@ int i915_irq_emit(struct drm_device *dev, void *data,
 /* Doesn't need the hardware lock.
  */
 int i915_irq_wait(struct drm_device *dev, void *data,
-		  struct drm_file *file_priv)
+			 struct drm_file *file_priv)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_irq_wait_t *irqwait = data;
@@ -521,18 +399,42 @@ int i915_irq_wait(struct drm_device *dev, void *data,
 	return i915_wait_irq(dev, irqwait->irq_seq);
 }
 
-static void i915_enable_interrupt (struct drm_device *dev)
+/* Called from drm generic code, passed 'crtc' which
+ * we use as a pipe index
+ */
+int i915_enable_vblank(struct drm_device *dev, int pipe)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+	int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
+	u32 pipeconf;
+
+	pipeconf = I915_READ(pipeconf_reg);
+	if (!(pipeconf & PIPEACONF_ENABLE))
+		return -EINVAL;
+
+	DRM_SPINLOCK(&dev_priv->user_irq_lock);
+	if (IS_I965G(dev))
+		i915_enable_pipestat(dev_priv, pipe,
+				     PIPE_START_VBLANK_INTERRUPT_ENABLE);
+	else
+		i915_enable_pipestat(dev_priv, pipe,
+				     PIPE_VBLANK_INTERRUPT_ENABLE);
+	DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
+	return 0;
+}
 
-	dev_priv->irq_enable_reg = USER_INT_FLAG;
-	if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
-		dev_priv->irq_enable_reg |= VSYNC_PIPEA_FLAG;
-	if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
-		dev_priv->irq_enable_reg |= VSYNC_PIPEB_FLAG;
+/* Called from drm generic code, passed 'crtc' which
+ * we use as a pipe index
+ */
+void i915_disable_vblank(struct drm_device *dev, int pipe)
+{
+	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
-	I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
-	dev_priv->irq_enabled = 1;
+	DRM_SPINLOCK(&dev_priv->user_irq_lock);
+	i915_disable_pipestat(dev_priv, pipe,
+			      PIPE_VBLANK_INTERRUPT_ENABLE |
+			      PIPE_START_VBLANK_INTERRUPT_ENABLE);
+	DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 }
 
 /* Set the vblank monitor pipe
@@ -541,22 +443,12 @@ int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 			 struct drm_file *file_priv)
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
-	drm_i915_vblank_pipe_t *pipe = data;
 
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
 	}
 
-	if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
-		DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);
-		return -EINVAL;
-	}
-
-	dev_priv->vblank_pipe = pipe->pipe;
-
-	i915_enable_interrupt (dev);
-
 	return 0;
 }
 
@@ -565,19 +457,13 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 {
 	drm_i915_private_t *dev_priv = dev->dev_private;
 	drm_i915_vblank_pipe_t *pipe = data;
-	u16 flag;
 
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
 	}
 
-	flag = I915_READ(I915REG_INT_ENABLE_R);
-	pipe->pipe = 0;
-	if (flag & VSYNC_PIPEA_FLAG)
-		pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
-	if (flag & VSYNC_PIPEB_FLAG)
-		pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
+	pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 
 	return 0;
 }
@@ -588,144 +474,21 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 int i915_vblank_swap(struct drm_device *dev, void *data,
 		     struct drm_file *file_priv)
 {
-	drm_i915_private_t *dev_priv = dev->dev_private;
-	drm_i915_vblank_swap_t *swap = data;
-	drm_i915_vbl_swap_t *vbl_swap;
-	unsigned int pipe, seqtype, curseq, plane;
-	unsigned long irqflags;
-	struct list_head *list;
-
-	if (!dev_priv) {
-		DRM_ERROR("%s called with no initialization\n", __func__);
-		return -EINVAL;
-	}
-
-	if (dev_priv->sarea_priv->rotation) {
-		DRM_DEBUG("Rotation not supported\n");
-		return -EINVAL;
-	}
-
-	if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
-			     _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
-			     _DRM_VBLANK_FLIP)) {
-		DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
-		return -EINVAL;
-	}
-
-	plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
-	pipe = i915_get_pipe(dev, plane);
-
-	seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
-
-	if (!(dev_priv->vblank_pipe & (1 << pipe))) {
-		DRM_ERROR("Invalid pipe %d\n", pipe);
-		return -EINVAL;
-	}
-
-	DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
-
-	/* It makes no sense to schedule a swap for a drawable that doesn't have
-	 * valid information at this point. E.g. this could mean that the X
-	 * server is too old to push drawable information to the DRM, in which
-	 * case all such swaps would become ineffective.
+	/* The delayed swap mechanism was fundamentally racy, and has been
+	 * removed.  The model was that the client requested a delayed flip/swap
+	 * from the kernel, then waited for vblank before continuing to perform
+	 * rendering.  The problem was that the kernel might wake the client
+	 * up before it dispatched the vblank swap (since the lock has to be
+	 * held while touching the ringbuffer), in which case the client would
+	 * clear and start the next frame before the swap occurred, and
+	 * flicker would occur in addition to likely missing the vblank.
+	 *
+	 * In the absence of this ioctl, userland falls back to a correct path
+	 * of waiting for a vblank, then dispatching the swap on its own.
+	 * Context switching to userland and back is plenty fast enough for
+	 * meeting the requirements of vblank swapping.
 	 */
-	if (!drm_get_drawable_info(dev, swap->drawable)) {
-		DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
-		DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
-		return -EINVAL;
-	}
-
-	DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
-
-	curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received);
-
-	if (seqtype == _DRM_VBLANK_RELATIVE)
-		swap->sequence += curseq;
-
-	if ((curseq - swap->sequence) <= (1<<23)) {
-		if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
-			swap->sequence = curseq + 1;
-		} else {
-			DRM_DEBUG("Missed target sequence\n");
-			return -EINVAL;
-		}
-	}
-
-	if (swap->seqtype & _DRM_VBLANK_FLIP) {
-		swap->sequence--;
-
-		if ((curseq - swap->sequence) <= (1<<23)) {
-			struct drm_drawable_info *drw;
-
-			LOCK_TEST_WITH_RETURN(dev, file_priv);
-
-			DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
-
-			drw = drm_get_drawable_info(dev, swap->drawable);
-
-			if (!drw) {
-				DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,
-				    irqflags);
-				DRM_DEBUG("Invalid drawable ID %d\n",
-					  swap->drawable);
-				return -EINVAL;
-			}
-
-			i915_dispatch_vsync_flip(dev, drw, plane);
-
-			DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
-
-			return 0;
-		}
-	}
-
-	DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
-
-	list_for_each(list, &dev_priv->vbl_swaps.head) {
-		vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
-
-		if (vbl_swap->drw_id == swap->drawable &&
-		    vbl_swap->plane == plane &&
-		    vbl_swap->sequence == swap->sequence) {
-			vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
-			DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
-			DRM_DEBUG("Already scheduled\n");
-			return 0;
-		}
-	}
-
-	DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
-
-	if (dev_priv->swaps_pending >= 100) {
-		DRM_DEBUG("Too many swaps queued\n");
-		return -EBUSY;
-	}
-
-	vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
-
-	if (!vbl_swap) {
-		DRM_ERROR("Failed to allocate memory to queue swap\n");
-		return -ENOMEM;
-	}
-
-	DRM_DEBUG("\n");
-
-	vbl_swap->drw_id = swap->drawable;
-	vbl_swap->plane = plane;
-	vbl_swap->sequence = swap->sequence;
-	vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
-
-	if (vbl_swap->flip)
-		swap->sequence++;
-
-	DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
-
-	list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
-	dev_priv->swaps_pending++;
-
-	DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
-
-	return 0;
+	return -EINVAL;
 }
 
 /* drm_dma.h hooks
@@ -734,45 +497,60 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
-	I915_WRITE16(I915REG_HWSTAM, 0xeffe);
-	I915_WRITE16(I915REG_INT_MASK_R, 0x0);
-	I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
+	atomic_set_int(&dev_priv->irq_received, 0);
+
+	I915_WRITE(HWSTAM, 0xeffe);
+	I915_WRITE(PIPEASTAT, 0);
+	I915_WRITE(PIPEBSTAT, 0);
+	I915_WRITE(IMR, 0xffffffff);
+	I915_WRITE(IER, 0x0);
+	(void) I915_READ(IER);
 }
 
-void i915_driver_irq_postinstall(struct drm_device * dev)
+int i915_driver_irq_postinstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 
-	DRM_SPININIT(&dev_priv->swaps_lock, "swap");
-	INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
-	dev_priv->swaps_pending = 0;
+	dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 
-	DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
-	dev_priv->user_irq_refcount = 0;
+	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 
-	i915_enable_interrupt(dev);
-	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
+	/* Unmask the interrupts that we always want on. */
+	dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
 
-	/*
-	 * Initialize the hardware status page IRQ location.
-	 */
+	dev_priv->pipestat[0] = 0;
+	dev_priv->pipestat[1] = 0;
+
+	/* Disable pipe interrupt enables, clear pending pipe status */
+	I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
+	I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
+
+	/* Clear pending interrupt status */
+	I915_WRITE(IIR, I915_READ(IIR));
 
-	I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
+	I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
+	I915_WRITE(IMR, dev_priv->irq_mask_reg);
+	(void) I915_READ(IER);
+
+	return 0;
 }
 
 void i915_driver_irq_uninstall(struct drm_device * dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	u16 temp;
 
 	if (!dev_priv)
 		return;
 
-	dev_priv->irq_enabled = 0;
-	I915_WRITE16(I915REG_HWSTAM, 0xffff);
-	I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
-	I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
+	dev_priv->vblank_pipe = 0;
+
+	I915_WRITE(HWSTAM, 0xffffffff);
+	I915_WRITE(PIPEASTAT, 0);
+	I915_WRITE(PIPEBSTAT, 0);
+	I915_WRITE(IMR, 0xffffffff);
+	I915_WRITE(IER, 0x0);
 
-	temp = I915_READ16(I915REG_INT_IDENTITY_R);
-	I915_WRITE16(I915REG_INT_IDENTITY_R, temp);
+	I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
+	I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
+	I915_WRITE(IIR, I915_READ(IIR));
 }
diff --git a/sys/dev/drm/i915_mem.c b/sys/dev/drm/i915_mem.c
index b964913b13..86111e32a1 100644
--- a/sys/dev/drm/i915_mem.c
+++ b/sys/dev/drm/i915_mem.c
@@ -1,6 +1,6 @@
 /* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*-
  */
-/*
+/*-
  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  * All Rights Reserved.
  *
@@ -24,13 +24,12 @@
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * $DragonFly: src/sys/dev/drm/i915_mem.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "i915_drm.h"
-#include "i915_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/i915_drm.h"
+#include "dev/drm/i915_drv.h"
 
 /* This memory manager is integrated into the global/local lru
  * mechanisms used by the clients.  Specifically, it operates by
diff --git a/sys/dev/drm/i915_reg.h b/sys/dev/drm/i915_reg.h
new file mode 100644
index 0000000000..90600d8994
--- /dev/null
+++ b/sys/dev/drm/i915_reg.h
@@ -0,0 +1,1469 @@
+/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _I915_REG_H_
+#define _I915_REG_H_
+
+/*
+ * The Bridge device's PCI config space has information about the
+ * fb aperture size and the amount of pre-reserved memory.
+ */
+#define INTEL_GMCH_CTRL		0x52
+#define INTEL_GMCH_ENABLED	0x4
+#define INTEL_GMCH_MEM_MASK	0x1
+#define INTEL_GMCH_MEM_64M	0x1
+#define INTEL_GMCH_MEM_128M	0
+
+#define INTEL_GMCH_GMS_MASK		(0xf << 4)
+#define INTEL_855_GMCH_GMS_DISABLED	(0x0 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_1M	(0x1 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_4M	(0x2 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_8M	(0x3 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_16M	(0x4 << 4)
+#define INTEL_855_GMCH_GMS_STOLEN_32M	(0x5 << 4)
+
+#define INTEL_915G_GMCH_GMS_STOLEN_48M	(0x6 << 4)
+#define INTEL_915G_GMCH_GMS_STOLEN_64M	(0x7 << 4)
+#define INTEL_GMCH_GMS_STOLEN_128M	(0x8 << 4)
+#define INTEL_GMCH_GMS_STOLEN_256M	(0x9 << 4)
+#define INTEL_GMCH_GMS_STOLEN_96M	(0xa << 4)
+#define INTEL_GMCH_GMS_STOLEN_160M	(0xb << 4)
+#define INTEL_GMCH_GMS_STOLEN_224M	(0xc << 4)
+#define INTEL_GMCH_GMS_STOLEN_352M	(0xd << 4)
+
+/* PCI config space */
+
+#define HPLLCC	0xc0 /* 855 only */
+#define   GC_CLOCK_CONTROL_MASK		(3 << 0)
+#define   GC_CLOCK_133_200		(0 << 0)
+#define   GC_CLOCK_100_200		(1 << 0)
+#define   GC_CLOCK_100_133		(2 << 0)
+#define   GC_CLOCK_166_250		(3 << 0)
+#define GCFGC	0xf0 /* 915+ only */
+#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
+#define   GC_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
+#define   GC_DISPLAY_CLOCK_333_MHZ	(4 << 4)
+#define   GC_DISPLAY_CLOCK_MASK		(7 << 4)
+#define LBB	0xf4
+
+/* VGA stuff */
+
+#define VGA_ST01_MDA 0x3ba
+#define VGA_ST01_CGA 0x3da
+
+#define VGA_MSR_WRITE 0x3c2
+#define VGA_MSR_READ 0x3cc
+#define   VGA_MSR_MEM_EN (1<<1)
+#define   VGA_MSR_CGA_MODE (1<<0)
+
+#define VGA_SR_INDEX 0x3c4
+#define VGA_SR_DATA 0x3c5
+
+#define VGA_AR_INDEX 0x3c0
+#define   VGA_AR_VID_EN (1<<5)
+#define VGA_AR_DATA_WRITE 0x3c0
+#define VGA_AR_DATA_READ 0x3c1
+
+#define VGA_GR_INDEX 0x3ce
+#define VGA_GR_DATA 0x3cf
+/* GR05 */
+#define   VGA_GR_MEM_READ_MODE_SHIFT 3
+#define     VGA_GR_MEM_READ_MODE_PLANE 1
+/* GR06 */
+#define   VGA_GR_MEM_MODE_MASK 0xc
+#define   VGA_GR_MEM_MODE_SHIFT 2
+#define   VGA_GR_MEM_A0000_AFFFF 0
+#define   VGA_GR_MEM_A0000_BFFFF 1
+#define   VGA_GR_MEM_B0000_B7FFF 2
+#define   VGA_GR_MEM_B0000_BFFFF 3
+
+#define VGA_DACMASK 0x3c6
+#define VGA_DACRX 0x3c7
+#define VGA_DACWX 0x3c8
+#define VGA_DACDATA 0x3c9
+
+#define VGA_CR_INDEX_MDA 0x3b4
+#define VGA_CR_DATA_MDA 0x3b5
+#define VGA_CR_INDEX_CGA 0x3d4
+#define VGA_CR_DATA_CGA 0x3d5
+
+/*
+ * Memory interface instructions used by the kernel
+ */
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+
+#define MI_NOOP			MI_INSTR(0, 0)
+#define MI_USER_INTERRUPT	MI_INSTR(0x02, 0)
+#define MI_WAIT_FOR_EVENT       MI_INSTR(0x03, 0)
+#define   MI_WAIT_FOR_PLANE_B_FLIP      (1<<6)
+#define   MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
+#define   MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
+#define MI_FLUSH		MI_INSTR(0x04, 0)
+#define   MI_READ_FLUSH		(1 << 0)
+#define   MI_EXE_FLUSH		(1 << 1)
+#define   MI_NO_WRITE_FLUSH	(1 << 2)
+#define   MI_SCENE_COUNT	(1 << 3) /* just increment scene count */
+#define   MI_END_SCENE		(1 << 4) /* flush binner and incr scene count */
+#define MI_BATCH_BUFFER_END	MI_INSTR(0x0a, 0)
+#define MI_REPORT_HEAD		MI_INSTR(0x07, 0)
+#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
+#define MI_STORE_DWORD_IMM	MI_INSTR(0x20, 1)
+#define   MI_MEM_VIRTUAL	(1 << 22) /* 965+ only */
+#define MI_STORE_DWORD_INDEX	MI_INSTR(0x21, 1)
+#define   MI_STORE_DWORD_INDEX_SHIFT 2
+#define MI_LOAD_REGISTER_IMM	MI_INSTR(0x22, 1)
+#define MI_BATCH_BUFFER		MI_INSTR(0x30, 1)
+#define   MI_BATCH_NON_SECURE	(1)
+#define   MI_BATCH_NON_SECURE_I965 (1<<8)
+#define MI_BATCH_BUFFER_START	MI_INSTR(0x31, 0)
+
+/*
+ * 3D instructions used by the kernel
+ */
+#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
+
+#define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
+#define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define   SC_UPDATE_SCISSOR       (0x1<<1)
+#define   SC_ENABLE_MASK          (0x1<<0)
+#define   SC_ENABLE               (0x1<<0)
+#define GFX_OP_LOAD_INDIRECT   ((0x3<<29)|(0x1d<<24)|(0x7<<16))
+#define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
+#define   SCI_YMIN_MASK      (0xffff<<16)
+#define   SCI_XMIN_MASK      (0xffff<<0)
+#define   SCI_YMAX_MASK      (0xffff<<16)
+#define   SCI_XMAX_MASK      (0xffff<<0)
+#define GFX_OP_SCISSOR_ENABLE	 ((0x3<<29)|(0x1c<<24)|(0x10<<19))
+#define GFX_OP_SCISSOR_RECT	 ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
+#define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
+#define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
+#define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
+#define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
+#define GFX_OP_DESTBUFFER_INFO	 ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
+#define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
+#define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
+#define SRC_COPY_BLT_CMD                ((2<<29)|(0x43<<22)|4)
+#define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
+#define XY_MONO_SRC_COPY_IMM_BLT	((2<<29)|(0x71<<22)|5)
+#define XY_SRC_COPY_BLT_WRITE_ALPHA	(1<<21)
+#define XY_SRC_COPY_BLT_WRITE_RGB	(1<<20)
+#define   BLT_DEPTH_8			(0<<24)
+#define   BLT_DEPTH_16_565		(1<<24)
+#define   BLT_DEPTH_16_1555		(2<<24)
+#define   BLT_DEPTH_32			(3<<24)
+#define   BLT_ROP_GXCOPY		(0xcc<<16)
+#define XY_SRC_COPY_BLT_SRC_TILED	(1<<15) /* 965+ only */
+#define XY_SRC_COPY_BLT_DST_TILED	(1<<11) /* 965+ only */
+#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
+#define   ASYNC_FLIP                (1<<22)
+#define   DISPLAY_PLANE_A           (0<<20)
+#define   DISPLAY_PLANE_B           (1<<20)
+
+/*
+ * Fence registers
+ */
+#define FENCE_REG_830_0			0x2000
+#define FENCE_REG_945_8			0x3000
+#define   I830_FENCE_START_MASK		0x07f80000
+#define   I830_FENCE_TILING_Y_SHIFT	12
+#define   I830_FENCE_SIZE_BITS(size)	((ffs((size) >> 19) - 1) << 8)
+#define   I830_FENCE_PITCH_SHIFT	4
+#define   I830_FENCE_REG_VALID		(1<<0)
+
+#define   I915_FENCE_START_MASK		0x0ff00000
+#define   I915_FENCE_SIZE_BITS(size)	((ffs((size) >> 20) - 1) << 8)
+
+#define FENCE_REG_965_0			0x03000
+#define   I965_FENCE_PITCH_SHIFT	2
+#define   I965_FENCE_TILING_Y_SHIFT	1
+#define   I965_FENCE_REG_VALID		(1<<0)
+
+/*
+ * Instruction and interrupt control regs
+ */
+#define PRB0_TAIL	0x02030
+#define PRB0_HEAD	0x02034
+#define PRB0_START	0x02038
+#define PRB0_CTL	0x0203c
+#define   TAIL_ADDR		0x001FFFF8
+#define   HEAD_WRAP_COUNT	0xFFE00000
+#define   HEAD_WRAP_ONE		0x00200000
+#define   HEAD_ADDR		0x001FFFFC
+#define   RING_NR_PAGES		0x001FF000
+#define   RING_REPORT_MASK	0x00000006
+#define   RING_REPORT_64K	0x00000002
+#define   RING_REPORT_128K	0x00000004
+#define   RING_NO_REPORT	0x00000000
+#define   RING_VALID_MASK	0x00000001
+#define   RING_VALID		0x00000001
+#define   RING_INVALID		0x00000000
+#define PRB1_TAIL	0x02040 /* 915+ only */
+#define PRB1_HEAD	0x02044 /* 915+ only */
+#define PRB1_START	0x02048 /* 915+ only */
+#define PRB1_CTL	0x0204c /* 915+ only */
+#define ACTHD_I965	0x02074
+#define HWS_PGA		0x02080
+#define HWS_ADDRESS_MASK	0xfffff000
+#define HWS_START_ADDRESS_SHIFT	4
+#define IPEIR		0x02088
+#define NOPID		0x02094
+#define HWSTAM		0x02098
+#define SCPD0		0x0209c /* 915+ only */
+#define IER		0x020a0
+#define IIR		0x020a4
+#define IMR		0x020a8
+#define ISR		0x020ac
+#define   I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1<<18)
+#define   I915_DISPLAY_PORT_INTERRUPT			(1<<17)
+#define   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT	(1<<15)
+#define   I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1<<14)
+#define   I915_HWB_OOM_INTERRUPT			(1<<13)
+#define   I915_SYNC_STATUS_INTERRUPT			(1<<12)
+#define   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1<<11)
+#define   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1<<10)
+#define   I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1<<9)
+#define   I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1<<8)
+#define   I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1<<7)
+#define   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1<<6)
+#define   I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1<<5)
+#define   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1<<4)
+#define   I915_DEBUG_INTERRUPT				(1<<2)
+#define   I915_USER_INTERRUPT				(1<<1)
+#define   I915_ASLE_INTERRUPT				(1<<0)
+#define EIR		0x020b0
+#define EMR		0x020b4
+#define ESR		0x020b8
+#define INSTPM	        0x020c0
+#define ACTHD	        0x020c8
+#define FW_BLC		0x020d8
+#define FW_BLC_SELF	0x020e0 /* 915+ only */
+#define MI_ARB_STATE	0x020e4 /* 915+ only */
+#define CACHE_MODE_0	0x02120 /* 915+ only */
+#define   CM0_MASK_SHIFT          16
+#define   CM0_IZ_OPT_DISABLE      (1<<6)
+#define   CM0_ZR_OPT_DISABLE      (1<<5)
+#define   CM0_DEPTH_EVICT_DISABLE (1<<4)
+#define   CM0_COLOR_EVICT_DISABLE (1<<3)
+#define   CM0_DEPTH_WRITE_DISABLE (1<<1)
+#define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
+#define GFX_FLSH_CNTL	0x02170 /* 915+ only */
+
+
+/*
+ * Framebuffer compression (915+ only)
+ */
+
+#define FBC_CFB_BASE		0x03200 /* 4k page aligned */
+#define FBC_LL_BASE		0x03204 /* 4k page aligned */
+#define FBC_CONTROL		0x03208
+#define   FBC_CTL_EN		(1<<31)
+#define   FBC_CTL_PERIODIC	(1<<30)
+#define   FBC_CTL_INTERVAL_SHIFT (16)
+#define   FBC_CTL_UNCOMPRESSIBLE (1<<14)
+#define   FBC_CTL_STRIDE_SHIFT	(5)
+#define   FBC_CTL_FENCENO	(1<<0)
+#define FBC_COMMAND		0x0320c
+#define   FBC_CMD_COMPRESS	(1<<0)
+#define FBC_STATUS		0x03210
+#define   FBC_STAT_COMPRESSING	(1<<31)
+#define   FBC_STAT_COMPRESSED	(1<<30)
+#define   FBC_STAT_MODIFIED	(1<<29)
+#define   FBC_STAT_CURRENT_LINE	(1<<0)
+#define FBC_CONTROL2		0x03214
+#define   FBC_CTL_FENCE_DBL	(0<<4)
+#define   FBC_CTL_IDLE_IMM	(0<<2)
+#define   FBC_CTL_IDLE_FULL	(1<<2)
+#define   FBC_CTL_IDLE_LINE	(2<<2)
+#define   FBC_CTL_IDLE_DEBUG	(3<<2)
+#define   FBC_CTL_CPU_FENCE	(1<<1)
+#define   FBC_CTL_PLANEA	(0<<0)
+#define   FBC_CTL_PLANEB	(1<<0)
+#define FBC_FENCE_OFF		0x0321b
+
+#define FBC_LL_SIZE		(1536)
+
+/*
+ * GPIO regs
+ */
+#define GPIOA			0x5010
+#define GPIOB			0x5014
+#define GPIOC			0x5018
+#define GPIOD			0x501c
+#define GPIOE			0x5020
+#define GPIOF			0x5024
+#define GPIOG			0x5028
+#define GPIOH			0x502c
+# define GPIO_CLOCK_DIR_MASK		(1 << 0)
+# define GPIO_CLOCK_DIR_IN		(0 << 1)
+# define GPIO_CLOCK_DIR_OUT		(1 << 1)
+# define GPIO_CLOCK_VAL_MASK		(1 << 2)
+# define GPIO_CLOCK_VAL_OUT		(1 << 3)
+# define GPIO_CLOCK_VAL_IN		(1 << 4)
+# define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
+# define GPIO_DATA_DIR_MASK		(1 << 8)
+# define GPIO_DATA_DIR_IN		(0 << 9)
+# define GPIO_DATA_DIR_OUT		(1 << 9)
+# define GPIO_DATA_VAL_MASK		(1 << 10)
+# define GPIO_DATA_VAL_OUT		(1 << 11)
+# define GPIO_DATA_VAL_IN		(1 << 12)
+# define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
+
+/*
+ * Clock control & power management
+ */
+
+#define VGA0	0x6000
+#define VGA1	0x6004
+#define VGA_PD	0x6010
+#define   VGA0_PD_P2_DIV_4	(1 << 7)
+#define   VGA0_PD_P1_DIV_2	(1 << 5)
+#define   VGA0_PD_P1_SHIFT	0
+#define   VGA0_PD_P1_MASK	(0x1f << 0)
+#define   VGA1_PD_P2_DIV_4	(1 << 15)
+#define   VGA1_PD_P1_DIV_2	(1 << 13)
+#define   VGA1_PD_P1_SHIFT	8
+#define   VGA1_PD_P1_MASK	(0x1f << 8)
+#define DPLL_A	0x06014
+#define DPLL_B	0x06018
+#define   DPLL_VCO_ENABLE		(1 << 31)
+#define   DPLL_DVO_HIGH_SPEED		(1 << 30)
+#define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
+#define   DPLL_VGA_MODE_DIS		(1 << 28)
+#define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
+#define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
+#define   DPLL_MODE_MASK		(3 << 26)
+#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
+#define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
+#define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
+#define   DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24) /* i915 */
+#define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
+#define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
+
+#define I915_FIFO_UNDERRUN_STATUS		(1UL<<31)
+#define I915_CRC_ERROR_ENABLE			(1UL<<29)
+#define I915_CRC_DONE_ENABLE			(1UL<<28)
+#define I915_GMBUS_EVENT_ENABLE			(1UL<<27)
+#define I915_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
+#define I915_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
+#define I915_DPST_EVENT_ENABLE			(1UL<<23)
+#define I915_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
+#define I915_ODD_FIELD_INTERRUPT_ENABLE		(1UL<<21)
+#define I915_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
+#define I915_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18)	/* 965 or later */
+#define I915_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
+#define I915_OVERLAY_UPDATED_ENABLE		(1UL<<16)
+#define I915_CRC_ERROR_INTERRUPT_STATUS		(1UL<<13)
+#define I915_CRC_DONE_INTERRUPT_STATUS		(1UL<<12)
+#define I915_GMBUS_INTERRUPT_STATUS		(1UL<<11)
+#define I915_VSYNC_INTERRUPT_STATUS		(1UL<<9)
+#define I915_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
+#define I915_DPST_EVENT_STATUS			(1UL<<7)
+#define I915_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
+#define I915_ODD_FIELD_INTERRUPT_STATUS		(1UL<<5)
+#define I915_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
+#define I915_START_VBLANK_INTERRUPT_STATUS	(1UL<<2)	/* 965 or later */
+#define I915_VBLANK_INTERRUPT_STATUS		(1UL<<1)
+#define I915_OVERLAY_UPDATED_STATUS		(1UL<<0)
+
+#define SRX_INDEX		0x3c4
+#define SRX_DATA		0x3c5
+#define SR01			1
+#define SR01_SCREEN_OFF		(1<<5)
+
+#define PPCR			0x61204
+#define PPCR_ON			(1<<0)
+
+#define DVOB			0x61140
+#define DVOB_ON			(1<<31)
+#define DVOC			0x61160
+#define DVOC_ON			(1<<31)
+#define LVDS			0x61180
+#define LVDS_ON			(1<<31)
+
+#define ADPA			0x61100
+#define ADPA_DPMS_MASK		(~(3<<10))
+#define ADPA_DPMS_ON		(0<<10)
+#define ADPA_DPMS_SUSPEND	(1<<10)
+#define ADPA_DPMS_STANDBY	(2<<10)
+#define ADPA_DPMS_OFF		(3<<10)
+
+#define RING_TAIL		0x00
+#define TAIL_ADDR		0x001FFFF8
+#define RING_HEAD		0x04
+#define HEAD_WRAP_COUNT		0xFFE00000
+#define HEAD_WRAP_ONE		0x00200000
+#define HEAD_ADDR		0x001FFFFC
+#define RING_START		0x08
+#define START_ADDR		0xFFFFF000
+#define RING_LEN		0x0C
+#define RING_NR_PAGES		0x001FF000
+#define RING_REPORT_MASK	0x00000006
+#define RING_REPORT_64K		0x00000002
+#define RING_REPORT_128K	0x00000004
+#define RING_NO_REPORT		0x00000000
+#define RING_VALID_MASK		0x00000001
+#define RING_VALID		0x00000001
+#define RING_INVALID		0x00000000
+
+/* Scratch pad debug 0 reg:
+ */
+#define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
+/*
+ * The i830 generation, in LVDS mode, defines P1 as the bit number set within
+ * this field (only one bit may be set).
+ */
+#define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
+#define   DPLL_FPA01_P1_POST_DIV_SHIFT	16
+/* i830, required in DVO non-gang */
+#define   PLL_P2_DIVIDE_BY_4		(1 << 23)
+#define   PLL_P1_DIVIDE_BY_TWO		(1 << 21) /* i830 */
+#define   PLL_REF_INPUT_DREFCLK		(0 << 13)
+#define   PLL_REF_INPUT_TVCLKINA	(1 << 13) /* i830 */
+#define   PLL_REF_INPUT_TVCLKINBC	(2 << 13) /* SDVO TVCLKIN */
+#define   PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
+#define   PLL_REF_INPUT_MASK		(3 << 13)
+#define   PLL_LOAD_PULSE_PHASE_SHIFT		9
+/*
+ * Parallel to Serial Load Pulse phase selection.
+ * Selects the phase for the 10X DPLL clock for the PCIe
+ * digital display port. The range is 4 to 13; 10 or more
+ * is just a flip delay. The default is 6
+ */
+#define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
+#define   DISPLAY_RATE_SELECT_FPA1		(1 << 8)
+/*
+ * SDVO multiplier for 945G/GM. Not used on 965.
+ */
+#define   SDVO_MULTIPLIER_MASK			0x000000ff
+#define   SDVO_MULTIPLIER_SHIFT_HIRES		4
+#define   SDVO_MULTIPLIER_SHIFT_VGA		0
+#define DPLL_A_MD 0x0601c /* 965+ only */
+/*
+ * UDI pixel divider, controlling how many pixels are stuffed into a packet.
+ *
+ * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
+ */
+#define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
+#define   DPLL_MD_UDI_DIVIDER_SHIFT		24
+/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
+#define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
+#define   DPLL_MD_VGA_UDI_DIVIDER_SHIFT		16
+/*
+ * SDVO/UDI pixel multiplier.
+ *
+ * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
+ * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
+ * modes, the bus rate would be below the limits, so SDVO allows for stuffing
+ * dummy bytes in the datastream at an increased clock rate, with both sides of
+ * the link knowing how many bytes are fill.
+ *
+ * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
+ * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
+ * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
+ * through an SDVO command.
+ *
+ * This register field has values of multiplication factor minus 1, with
+ * a maximum multiplier of 5 for SDVO.
+ */
+#define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
+#define   DPLL_MD_UDI_MULTIPLIER_SHIFT		8
+/*
+ * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
+ * This best be set to the default value (3) or the CRT won't work. No,
+ * I don't entirely understand what this does...
+ */
+#define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
+#define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
+#define DPLL_B_MD 0x06020 /* 965+ only */
+#define FPA0	0x06040
+#define FPA1	0x06044
+#define FPB0	0x06048
+#define FPB1	0x0604c
+#define   FP_N_DIV_MASK		0x003f0000
+#define   FP_N_DIV_SHIFT		16
+#define   FP_M1_DIV_MASK	0x00003f00
+#define   FP_M1_DIV_SHIFT		 8
+#define   FP_M2_DIV_MASK	0x0000003f
+#define   FP_M2_DIV_SHIFT		 0
+#define DPLL_TEST	0x606c
+#define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
+#define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
+#define   DPLLB_TEST_SDVO_DIV_4		(2 << 22)
+#define   DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
+#define   DPLLB_TEST_N_BYPASS		(1 << 19)
+#define   DPLLB_TEST_M_BYPASS		(1 << 18)
+#define   DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
+#define   DPLLA_TEST_N_BYPASS		(1 << 3)
+#define   DPLLA_TEST_M_BYPASS		(1 << 2)
+#define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
+#define D_STATE		0x6104
+#define CG_2D_DIS	0x6200
+#define CG_3D_DIS	0x6204
+
+/*
+ * Palette regs
+ */
+
+#define PALETTE_A		0x0a000
+#define PALETTE_B		0x0a800
+
+/* MCH MMIO space */
+
+/*
+ * MCHBAR mirror.
+ *
+ * This mirrors the MCHBAR MMIO space whose location is determined by
+ * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
+ * every way.  It is not accessible from the CP register read instructions.
+ *
+ */
+#define MCHBAR_MIRROR_BASE	0x10000
+
+/** 915-945 and GM965 MCH register controlling DRAM channel access */
+#define DCC			0x10200
+#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL		(0 << 0)
+#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
+#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
+#define DCC_ADDRESSING_MODE_MASK			(3 << 0)
+#define DCC_CHANNEL_XOR_DISABLE				(1 << 10)
+#define DCC_CHANNEL_XOR_BIT_17				(1 << 9)
+
+/** 965 MCH register controlling DRAM channel configuration */
+#define C0DRB3			0x10206
+#define C1DRB3			0x10606
+
+/** GM965 GM45 render standby register */
+#define MCHBAR_RENDER_STANDBY	0x111B8
+
+#define PEG_BAND_GAP_DATA	0x14d68
+
+/*
+ * Overlay regs
+ */
+
+#define OVADD			0x30000
+#define DOVSTA			0x30008
+#define OC_BUF			(0x3<<20)
+#define OGAMC5			0x30010
+#define OGAMC4			0x30014
+#define OGAMC3			0x30018
+#define OGAMC2			0x3001c
+#define OGAMC1			0x30020
+#define OGAMC0			0x30024
+
+/*
+ * Display engine regs
+ */
+
+/* Pipe A timing regs */
+#define HTOTAL_A	0x60000
+#define HBLANK_A	0x60004
+#define HSYNC_A		0x60008
+#define VTOTAL_A	0x6000c
+#define VBLANK_A	0x60010
+#define VSYNC_A		0x60014
+#define PIPEASRC	0x6001c
+#define BCLRPAT_A	0x60020
+
+/* Pipe B timing regs */
+#define HTOTAL_B	0x61000
+#define HBLANK_B	0x61004
+#define HSYNC_B		0x61008
+#define VTOTAL_B	0x6100c
+#define VBLANK_B	0x61010
+#define VSYNC_B		0x61014
+#define PIPEBSRC	0x6101c
+#define BCLRPAT_B	0x61020
+
+/* VGA port control */
+#define ADPA			0x61100
+#define   ADPA_DAC_ENABLE	(1<<31)
+#define   ADPA_DAC_DISABLE	0
+#define   ADPA_PIPE_SELECT_MASK	(1<<30)
+#define   ADPA_PIPE_A_SELECT	0
+#define   ADPA_PIPE_B_SELECT	(1<<30)
+#define   ADPA_USE_VGA_HVPOLARITY (1<<15)
+#define   ADPA_SETS_HVPOLARITY	0
+#define   ADPA_VSYNC_CNTL_DISABLE (1<<11)
+#define   ADPA_VSYNC_CNTL_ENABLE 0
+#define   ADPA_HSYNC_CNTL_DISABLE (1<<10)
+#define   ADPA_HSYNC_CNTL_ENABLE 0
+#define   ADPA_VSYNC_ACTIVE_HIGH (1<<4)
+#define   ADPA_VSYNC_ACTIVE_LOW	0
+#define   ADPA_HSYNC_ACTIVE_HIGH (1<<3)
+#define   ADPA_HSYNC_ACTIVE_LOW	0
+#define   ADPA_DPMS_MASK	(~(3<<10))
+#define   ADPA_DPMS_ON		(0<<10)
+#define   ADPA_DPMS_SUSPEND	(1<<10)
+#define   ADPA_DPMS_STANDBY	(2<<10)
+#define   ADPA_DPMS_OFF		(3<<10)
+
+/* Hotplug control (945+ only) */
+#define PORT_HOTPLUG_EN		0x61110
+#define   HDMIB_HOTPLUG_INT_EN			(1 << 29)
+#define   HDMIC_HOTPLUG_INT_EN			(1 << 28)
+#define   HDMID_HOTPLUG_INT_EN			(1 << 27)
+#define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
+#define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
+#define   TV_HOTPLUG_INT_EN			(1 << 18)
+#define   CRT_HOTPLUG_INT_EN			(1 << 9)
+#define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
+
+#define PORT_HOTPLUG_STAT	0x61114
+#define   HDMIB_HOTPLUG_INT_STATUS		(1 << 29)
+#define   HDMIC_HOTPLUG_INT_STATUS		(1 << 28)
+#define   HDMID_HOTPLUG_INT_STATUS		(1 << 27)
+#define   CRT_HOTPLUG_INT_STATUS		(1 << 11)
+#define   TV_HOTPLUG_INT_STATUS			(1 << 10)
+#define   CRT_HOTPLUG_MONITOR_MASK		(3 << 8)
+#define   CRT_HOTPLUG_MONITOR_COLOR		(3 << 8)
+#define   CRT_HOTPLUG_MONITOR_MONO		(2 << 8)
+#define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
+#define   SDVOC_HOTPLUG_INT_STATUS		(1 << 7)
+#define   SDVOB_HOTPLUG_INT_STATUS		(1 << 6)
+
+/* SDVO port control */
+#define SDVOB			0x61140
+#define SDVOC			0x61160
+#define   SDVO_ENABLE		(1 << 31)
+#define   SDVO_PIPE_B_SELECT	(1 << 30)
+#define   SDVO_STALL_SELECT	(1 << 29)
+#define   SDVO_INTERRUPT_ENABLE	(1 << 26)
+/**
+ * 915G/GM SDVO pixel multiplier.
+ *
+ * Programmed value is multiplier - 1, up to 5x.
+ *
+ * \sa DPLL_MD_UDI_MULTIPLIER_MASK
+ */
+#define   SDVO_PORT_MULTIPLY_MASK	(7 << 23)
+#define   SDVO_PORT_MULTIPLY_SHIFT		23
+#define   SDVO_PHASE_SELECT_MASK	(15 << 19)
+#define   SDVO_PHASE_SELECT_DEFAULT	(6 << 19)
+#define   SDVO_CLOCK_OUTPUT_INVERT	(1 << 18)
+#define   SDVOC_GANG_MODE		(1 << 16)
+#define   SDVO_ENCODING_SDVO		(0x0 << 10)
+#define   SDVO_ENCODING_HDMI		(0x2 << 10)
+/** Requird for HDMI operation */
+#define   SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
+#define   SDVO_BORDER_ENABLE		(1 << 7)
+#define   SDVO_AUDIO_ENABLE		(1 << 6)
+/** New with 965, default is to be set */
+#define   SDVO_VSYNC_ACTIVE_HIGH	(1 << 4)
+/** New with 965, default is to be set */
+#define   SDVO_HSYNC_ACTIVE_HIGH	(1 << 3)
+#define   SDVOB_PCIE_CONCURRENCY	(1 << 3)
+#define   SDVO_DETECTED			(1 << 2)
+/* Bits to be preserved when writing */
+#define   SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
+#define   SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
+
+/* DVO port control */
+#define DVOA			0x61120
+#define DVOB			0x61140
+#define DVOC			0x61160
+#define   DVO_ENABLE			(1 << 31)
+#define   DVO_PIPE_B_SELECT		(1 << 30)
+#define   DVO_PIPE_STALL_UNUSED		(0 << 28)
+#define   DVO_PIPE_STALL		(1 << 28)
+#define   DVO_PIPE_STALL_TV		(2 << 28)
+#define   DVO_PIPE_STALL_MASK		(3 << 28)
+#define   DVO_USE_VGA_SYNC		(1 << 15)
+#define   DVO_DATA_ORDER_I740		(0 << 14)
+#define   DVO_DATA_ORDER_FP		(1 << 14)
+#define   DVO_VSYNC_DISABLE		(1 << 11)
+#define   DVO_HSYNC_DISABLE		(1 << 10)
+#define   DVO_VSYNC_TRISTATE		(1 << 9)
+#define   DVO_HSYNC_TRISTATE		(1 << 8)
+#define   DVO_BORDER_ENABLE		(1 << 7)
+#define   DVO_DATA_ORDER_GBRG		(1 << 6)
+#define   DVO_DATA_ORDER_RGGB		(0 << 6)
+#define   DVO_DATA_ORDER_GBRG_ERRATA	(0 << 6)
+#define   DVO_DATA_ORDER_RGGB_ERRATA	(1 << 6)
+#define   DVO_VSYNC_ACTIVE_HIGH		(1 << 4)
+#define   DVO_HSYNC_ACTIVE_HIGH		(1 << 3)
+#define   DVO_BLANK_ACTIVE_HIGH		(1 << 2)
+#define   DVO_OUTPUT_CSTATE_PIXELS	(1 << 1)	/* SDG only */
+#define   DVO_OUTPUT_SOURCE_SIZE_PIXELS	(1 << 0)	/* SDG only */
+#define   DVO_PRESERVE_MASK		(0x7<<24)
+#define DVOA_SRCDIM		0x61124
+#define DVOB_SRCDIM		0x61144
+#define DVOC_SRCDIM		0x61164
+#define   DVO_SRCDIM_HORIZONTAL_SHIFT	12
+#define   DVO_SRCDIM_VERTICAL_SHIFT	0
+
+/* LVDS port control */
+#define LVDS			0x61180
+/*
+ * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
+ * the DPLL semantics change when the LVDS is assigned to that pipe.
+ */
+#define   LVDS_PORT_EN			(1 << 31)
+/* Selects pipe B for LVDS data.  Must be set on pre-965. */
+#define   LVDS_PIPEB_SELECT		(1 << 30)
+/*
+ * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
+ * pixel.
+ */
+#define   LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
+#define   LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
+#define   LVDS_A0A2_CLKA_POWER_UP	(3 << 8)
+/*
+ * Controls the A3 data pair, which contains the additional LSBs for 24 bit
+ * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
+ * on.
+ */
+#define   LVDS_A3_POWER_MASK		(3 << 6)
+#define   LVDS_A3_POWER_DOWN		(0 << 6)
+#define   LVDS_A3_POWER_UP		(3 << 6)
+/*
+ * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
+ * is set.
+ */
+#define   LVDS_CLKB_POWER_MASK		(3 << 4)
+#define   LVDS_CLKB_POWER_DOWN		(0 << 4)
+#define   LVDS_CLKB_POWER_UP		(3 << 4)
+/*
+ * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
+ * setting for whether we are in dual-channel mode.  The B3 pair will
+ * additionally only be powered up when LVDS_A3_POWER_UP is set.
+ */
+#define   LVDS_B0B3_POWER_MASK		(3 << 2)
+#define   LVDS_B0B3_POWER_DOWN		(0 << 2)
+#define   LVDS_B0B3_POWER_UP		(3 << 2)
+
+/* Panel power sequencing */
+#define PP_STATUS	0x61200
+#define   PP_ON		(1 << 31)
+/*
+ * Indicates that all dependencies of the panel are on:
+ *
+ * - PLL enabled
+ * - pipe enabled
+ * - LVDS/DVOB/DVOC on
+ */
+#define   PP_READY		(1 << 30)
+#define   PP_SEQUENCE_NONE	(0 << 28)
+#define   PP_SEQUENCE_ON	(1 << 28)
+#define   PP_SEQUENCE_OFF	(2 << 28)
+#define   PP_SEQUENCE_MASK	0x30000000
+#define PP_CONTROL	0x61204
+#define   POWER_TARGET_ON	(1 << 0)
+#define PP_ON_DELAYS	0x61208
+#define PP_OFF_DELAYS	0x6120c
+#define PP_DIVISOR	0x61210
+
+/* Panel fitting */
+#define PFIT_CONTROL	0x61230
+#define   PFIT_ENABLE		(1 << 31)
+#define   PFIT_PIPE_MASK	(3 << 29)
+#define   PFIT_PIPE_SHIFT	29
+#define   VERT_INTERP_DISABLE	(0 << 10)
+#define   VERT_INTERP_BILINEAR	(1 << 10)
+#define   VERT_INTERP_MASK	(3 << 10)
+#define   VERT_AUTO_SCALE	(1 << 9)
+#define   HORIZ_INTERP_DISABLE	(0 << 6)
+#define   HORIZ_INTERP_BILINEAR	(1 << 6)
+#define   HORIZ_INTERP_MASK	(3 << 6)
+#define   HORIZ_AUTO_SCALE	(1 << 5)
+#define   PANEL_8TO6_DITHER_ENABLE (1 << 3)
+#define PFIT_PGM_RATIOS	0x61234
+#define   PFIT_VERT_SCALE_MASK			0xfff00000
+#define   PFIT_HORIZ_SCALE_MASK			0x0000fff0
+#define PFIT_AUTO_RATIOS 0x61238
+
+/* Backlight control */
+#define BLC_PWM_CTL		0x61254
+#define   BACKLIGHT_MODULATION_FREQ_SHIFT		(17)
+#define BLC_PWM_CTL2		0x61250 /* 965+ only */
+#define   BLM_COMBINATION_MODE (1 << 30)
+/*
+ * This is the most significant 15 bits of the number of backlight cycles in a
+ * complete cycle of the modulated backlight control.
+ *
+ * The actual value is this field multiplied by two.
+ */
+#define   BACKLIGHT_MODULATION_FREQ_MASK		(0x7fff << 17)
+#define   BLM_LEGACY_MODE				(1 << 16)
+/*
+ * This is the number of cycles out of the backlight modulation cycle for which
+ * the backlight is on.
+ *
+ * This field must be no greater than the number of cycles in the complete
+ * backlight modulation cycle.
+ */
+#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
+#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
+
+/* TV port control */
+#define TV_CTL			0x68000
+/** Enables the TV encoder */
+# define TV_ENC_ENABLE			(1 << 31)
+/** Sources the TV encoder input from pipe B instead of A. */
+# define TV_ENC_PIPEB_SELECT		(1 << 30)
+/** Outputs composite video (DAC A only) */
+# define TV_ENC_OUTPUT_COMPOSITE	(0 << 28)
+/** Outputs SVideo video (DAC B/C) */
+# define TV_ENC_OUTPUT_SVIDEO		(1 << 28)
+/** Outputs Component video (DAC A/B/C) */
+# define TV_ENC_OUTPUT_COMPONENT	(2 << 28)
+/** Outputs Composite and SVideo (DAC A/B/C) */
+# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE	(3 << 28)
+# define TV_TRILEVEL_SYNC		(1 << 21)
+/** Enables slow sync generation (945GM only) */
+# define TV_SLOW_SYNC			(1 << 20)
+/** Selects 4x oversampling for 480i and 576p */
+# define TV_OVERSAMPLE_4X		(0 << 18)
+/** Selects 2x oversampling for 720p and 1080i */
+# define TV_OVERSAMPLE_2X		(1 << 18)
+/** Selects no oversampling for 1080p */
+# define TV_OVERSAMPLE_NONE		(2 << 18)
+/** Selects 8x oversampling */
+# define TV_OVERSAMPLE_8X		(3 << 18)
+/** Selects progressive mode rather than interlaced */
+# define TV_PROGRESSIVE			(1 << 17)
+/** Sets the colorburst to PAL mode.  Required for non-M PAL modes. */
+# define TV_PAL_BURST			(1 << 16)
+/** Field for setting delay of Y compared to C */
+# define TV_YC_SKEW_MASK		(7 << 12)
+/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
+# define TV_ENC_SDP_FIX			(1 << 11)
+/**
+ * Enables a fix for the 915GM only.
+ *
+ * Not sure what it does.
+ */
+# define TV_ENC_C0_FIX			(1 << 10)
+/** Bits that must be preserved by software */
+# define TV_CTL_SAVE			((3 << 8) | (3 << 6))
+# define TV_FUSE_STATE_MASK		(3 << 4)
+/** Read-only state that reports all features enabled */
+# define TV_FUSE_STATE_ENABLED		(0 << 4)
+/** Read-only state that reports that Macrovision is disabled in hardware*/
+# define TV_FUSE_STATE_NO_MACROVISION	(1 << 4)
+/** Read-only state that reports that TV-out is disabled in hardware. */
+# define TV_FUSE_STATE_DISABLED		(2 << 4)
+/** Normal operation */
+# define TV_TEST_MODE_NORMAL		(0 << 0)
+/** Encoder test pattern 1 - combo pattern */
+# define TV_TEST_MODE_PATTERN_1		(1 << 0)
+/** Encoder test pattern 2 - full screen vertical 75% color bars */
+# define TV_TEST_MODE_PATTERN_2		(2 << 0)
+/** Encoder test pattern 3 - full screen horizontal 75% color bars */
+# define TV_TEST_MODE_PATTERN_3		(3 << 0)
+/** Encoder test pattern 4 - random noise */
+# define TV_TEST_MODE_PATTERN_4		(4 << 0)
+/** Encoder test pattern 5 - linear color ramps */
+# define TV_TEST_MODE_PATTERN_5		(5 << 0)
+/**
+ * This test mode forces the DACs to 50% of full output.
+ *
+ * This is used for load detection in combination with TVDAC_SENSE_MASK
+ */
+# define TV_TEST_MODE_MONITOR_DETECT	(7 << 0)
+# define TV_TEST_MODE_MASK		(7 << 0)
+
+#define TV_DAC			0x68004
+/**
+ * Reports that DAC state change logic has reported change (RO).
+ *
+ * This gets cleared when TV_DAC_STATE_EN is cleared
+*/
+# define TVDAC_STATE_CHG		(1 << 31)
+# define TVDAC_SENSE_MASK		(7 << 28)
+/** Reports that DAC A voltage is above the detect threshold */
+# define TVDAC_A_SENSE			(1 << 30)
+/** Reports that DAC B voltage is above the detect threshold */
+# define TVDAC_B_SENSE			(1 << 29)
+/** Reports that DAC C voltage is above the detect threshold */
+# define TVDAC_C_SENSE			(1 << 28)
+/**
+ * Enables DAC state detection logic, for load-based TV detection.
+ *
+ * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
+ * to off, for load detection to work.
+ */
+# define TVDAC_STATE_CHG_EN		(1 << 27)
+/** Sets the DAC A sense value to high */
+# define TVDAC_A_SENSE_CTL		(1 << 26)
+/** Sets the DAC B sense value to high */
+# define TVDAC_B_SENSE_CTL		(1 << 25)
+/** Sets the DAC C sense value to high */
+# define TVDAC_C_SENSE_CTL		(1 << 24)
+/** Overrides the ENC_ENABLE and DAC voltage levels */
+# define DAC_CTL_OVERRIDE		(1 << 7)
+/** Sets the slew rate.  Must be preserved in software */
+# define ENC_TVDAC_SLEW_FAST		(1 << 6)
+# define DAC_A_1_3_V			(0 << 4)
+# define DAC_A_1_1_V			(1 << 4)
+# define DAC_A_0_7_V			(2 << 4)
+# define DAC_A_OFF			(3 << 4)
+# define DAC_B_1_3_V			(0 << 2)
+# define DAC_B_1_1_V			(1 << 2)
+# define DAC_B_0_7_V			(2 << 2)
+# define DAC_B_OFF			(3 << 2)
+# define DAC_C_1_3_V			(0 << 0)
+# define DAC_C_1_1_V			(1 << 0)
+# define DAC_C_0_7_V			(2 << 0)
+# define DAC_C_OFF			(3 << 0)
+
+/**
+ * CSC coefficients are stored in a floating point format with 9 bits of
+ * mantissa and 2 or 3 bits of exponent.  The exponent is represented as 2**-n,
+ * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
+ * -1 (0x3) being the only legal negative value.
+ */
+#define TV_CSC_Y		0x68010
+# define TV_RY_MASK			0x07ff0000
+# define TV_RY_SHIFT			16
+# define TV_GY_MASK			0x00000fff
+# define TV_GY_SHIFT			0
+
+#define TV_CSC_Y2		0x68014
+# define TV_BY_MASK			0x07ff0000
+# define TV_BY_SHIFT			16
+/**
+ * Y attenuation for component video.
+ *
+ * Stored in 1.9 fixed point.
+ */
+# define TV_AY_MASK			0x000003ff
+# define TV_AY_SHIFT			0
+
+#define TV_CSC_U		0x68018
+# define TV_RU_MASK			0x07ff0000
+# define TV_RU_SHIFT			16
+# define TV_GU_MASK			0x000007ff
+# define TV_GU_SHIFT			0
+
+#define TV_CSC_U2		0x6801c
+# define TV_BU_MASK			0x07ff0000
+# define TV_BU_SHIFT			16
+/**
+ * U attenuation for component video.
+ *
+ * Stored in 1.9 fixed point.
+ */
+# define TV_AU_MASK			0x000003ff
+# define TV_AU_SHIFT			0
+
+#define TV_CSC_V		0x68020
+# define TV_RV_MASK			0x0fff0000
+# define TV_RV_SHIFT			16
+# define TV_GV_MASK			0x000007ff
+# define TV_GV_SHIFT			0
+
+#define TV_CSC_V2		0x68024
+# define TV_BV_MASK			0x07ff0000
+# define TV_BV_SHIFT			16
+/**
+ * V attenuation for component video.
+ *
+ * Stored in 1.9 fixed point.
+ */
+# define TV_AV_MASK			0x000007ff
+# define TV_AV_SHIFT			0
+
+#define TV_CLR_KNOBS		0x68028
+/** 2s-complement brightness adjustment */
+# define TV_BRIGHTNESS_MASK		0xff000000
+# define TV_BRIGHTNESS_SHIFT		24
+/** Contrast adjustment, as a 2.6 unsigned floating point number */
+# define TV_CONTRAST_MASK		0x00ff0000
+# define TV_CONTRAST_SHIFT		16
+/** Saturation adjustment, as a 2.6 unsigned floating point number */
+# define TV_SATURATION_MASK		0x0000ff00
+# define TV_SATURATION_SHIFT		8
+/** Hue adjustment, as an integer phase angle in degrees */
+# define TV_HUE_MASK			0x000000ff
+# define TV_HUE_SHIFT			0
+
+#define TV_CLR_LEVEL		0x6802c
+/** Controls the DAC level for black */
+# define TV_BLACK_LEVEL_MASK		0x01ff0000
+# define TV_BLACK_LEVEL_SHIFT		16
+/** Controls the DAC level for blanking */
+# define TV_BLANK_LEVEL_MASK		0x000001ff
+# define TV_BLANK_LEVEL_SHIFT		0
+
+#define TV_H_CTL_1		0x68030
+/** Number of pixels in the hsync. */
+# define TV_HSYNC_END_MASK		0x1fff0000
+# define TV_HSYNC_END_SHIFT		16
+/** Total number of pixels minus one in the line (display and blanking). */
+# define TV_HTOTAL_MASK			0x00001fff
+# define TV_HTOTAL_SHIFT		0
+
+#define TV_H_CTL_2		0x68034
+/** Enables the colorburst (needed for non-component color) */
+# define TV_BURST_ENA			(1 << 31)
+/** Offset of the colorburst from the start of hsync, in pixels minus one. */
+# define TV_HBURST_START_SHIFT		16
+# define TV_HBURST_START_MASK		0x1fff0000
+/** Length of the colorburst */
+# define TV_HBURST_LEN_SHIFT		0
+# define TV_HBURST_LEN_MASK		0x0001fff
+
+#define TV_H_CTL_3		0x68038
+/** End of hblank, measured in pixels minus one from start of hsync */
+# define TV_HBLANK_END_SHIFT		16
+# define TV_HBLANK_END_MASK		0x1fff0000
+/** Start of hblank, measured in pixels minus one from start of hsync */
+# define TV_HBLANK_START_SHIFT		0
+# define TV_HBLANK_START_MASK		0x0001fff
+
+#define TV_V_CTL_1		0x6803c
+/** XXX */
+# define TV_NBR_END_SHIFT		16
+# define TV_NBR_END_MASK		0x07ff0000
+/** XXX */
+# define TV_VI_END_F1_SHIFT		8
+# define TV_VI_END_F1_MASK		0x00003f00
+/** XXX */
+# define TV_VI_END_F2_SHIFT		0
+# define TV_VI_END_F2_MASK		0x0000003f
+
+#define TV_V_CTL_2		0x68040
+/** Length of vsync, in half lines */
+# define TV_VSYNC_LEN_MASK		0x07ff0000
+# define TV_VSYNC_LEN_SHIFT		16
+/** Offset of the start of vsync in field 1, measured in one less than the
+ * number of half lines.
+ */
+# define TV_VSYNC_START_F1_MASK		0x00007f00
+# define TV_VSYNC_START_F1_SHIFT	8
+/**
+ * Offset of the start of vsync in field 2, measured in one less than the
+ * number of half lines.
+ */
+# define TV_VSYNC_START_F2_MASK		0x0000007f
+# define TV_VSYNC_START_F2_SHIFT	0
+
+#define TV_V_CTL_3		0x68044
+/** Enables generation of the equalization signal */
+# define TV_EQUAL_ENA			(1 << 31)
+/** Length of vsync, in half lines */
+# define TV_VEQ_LEN_MASK		0x007f0000
+# define TV_VEQ_LEN_SHIFT		16
+/** Offset of the start of equalization in field 1, measured in one less than
+ * the number of half lines.
+ */
+# define TV_VEQ_START_F1_MASK		0x0007f00
+# define TV_VEQ_START_F1_SHIFT		8
+/**
+ * Offset of the start of equalization in field 2, measured in one less than
+ * the number of half lines.
+ */
+# define TV_VEQ_START_F2_MASK		0x000007f
+# define TV_VEQ_START_F2_SHIFT		0
+
+#define TV_V_CTL_4		0x68048
+/**
+ * Offset to start of vertical colorburst, measured in one less than the
+ * number of lines from vertical start.
+ */
+# define TV_VBURST_START_F1_MASK	0x003f0000
+# define TV_VBURST_START_F1_SHIFT	16
+/**
+ * Offset to the end of vertical colorburst, measured in one less than the
+ * number of lines from the start of NBR.
+ */
+# define TV_VBURST_END_F1_MASK		0x000000ff
+# define TV_VBURST_END_F1_SHIFT		0
+
+#define TV_V_CTL_5		0x6804c
+/**
+ * Offset to start of vertical colorburst, measured in one less than the
+ * number of lines from vertical start.
+ */
+# define TV_VBURST_START_F2_MASK	0x003f0000
+# define TV_VBURST_START_F2_SHIFT	16
+/**
+ * Offset to the end of vertical colorburst, measured in one less than the
+ * number of lines from the start of NBR.
+ */
+# define TV_VBURST_END_F2_MASK		0x000000ff
+# define TV_VBURST_END_F2_SHIFT		0
+
+#define TV_V_CTL_6		0x68050
+/**
+ * Offset to start of vertical colorburst, measured in one less than the
+ * number of lines from vertical start.
+ */
+# define TV_VBURST_START_F3_MASK	0x003f0000
+# define TV_VBURST_START_F3_SHIFT	16
+/**
+ * Offset to the end of vertical colorburst, measured in one less than the
+ * number of lines from the start of NBR.
+ */
+# define TV_VBURST_END_F3_MASK		0x000000ff
+# define TV_VBURST_END_F3_SHIFT		0
+
+#define TV_V_CTL_7		0x68054
+/**
+ * Offset to start of vertical colorburst, measured in one less than the
+ * number of lines from vertical start.
+ */
+# define TV_VBURST_START_F4_MASK	0x003f0000
+# define TV_VBURST_START_F4_SHIFT	16
+/**
+ * Offset to the end of vertical colorburst, measured in one less than the
+ * number of lines from the start of NBR.
+ */
+# define TV_VBURST_END_F4_MASK		0x000000ff
+# define TV_VBURST_END_F4_SHIFT		0
+
+#define TV_SC_CTL_1		0x68060
+/** Turns on the first subcarrier phase generation DDA */
+# define TV_SC_DDA1_EN			(1 << 31)
+/** Turns on the first subcarrier phase generation DDA */
+# define TV_SC_DDA2_EN			(1 << 30)
+/** Turns on the first subcarrier phase generation DDA */
+# define TV_SC_DDA3_EN			(1 << 29)
+/** Sets the subcarrier DDA to reset frequency every other field */
+# define TV_SC_RESET_EVERY_2		(0 << 24)
+/** Sets the subcarrier DDA to reset frequency every fourth field */
+# define TV_SC_RESET_EVERY_4		(1 << 24)
+/** Sets the subcarrier DDA to reset frequency every eighth field */
+# define TV_SC_RESET_EVERY_8		(2 << 24)
+/** Sets the subcarrier DDA to never reset the frequency */
+# define TV_SC_RESET_NEVER		(3 << 24)
+/** Sets the peak amplitude of the colorburst.*/
+# define TV_BURST_LEVEL_MASK		0x00ff0000
+# define TV_BURST_LEVEL_SHIFT		16
+/** Sets the increment of the first subcarrier phase generation DDA */
+# define TV_SCDDA1_INC_MASK		0x00000fff
+# define TV_SCDDA1_INC_SHIFT		0
+
+#define TV_SC_CTL_2		0x68064
+/** Sets the rollover for the second subcarrier phase generation DDA */
+# define TV_SCDDA2_SIZE_MASK		0x7fff0000
+# define TV_SCDDA2_SIZE_SHIFT		16
+/** Sets the increent of the second subcarrier phase generation DDA */
+# define TV_SCDDA2_INC_MASK		0x00007fff
+# define TV_SCDDA2_INC_SHIFT		0
+
+#define TV_SC_CTL_3		0x68068
+/** Sets the rollover for the third subcarrier phase generation DDA */
+# define TV_SCDDA3_SIZE_MASK		0x7fff0000
+# define TV_SCDDA3_SIZE_SHIFT		16
+/** Sets the increent of the third subcarrier phase generation DDA */
+# define TV_SCDDA3_INC_MASK		0x00007fff
+# define TV_SCDDA3_INC_SHIFT		0
+
+#define TV_WIN_POS		0x68070
+/** X coordinate of the display from the start of horizontal active */
+# define TV_XPOS_MASK			0x1fff0000
+# define TV_XPOS_SHIFT			16
+/** Y coordinate of the display from the start of vertical active (NBR) */
+# define TV_YPOS_MASK			0x00000fff
+# define TV_YPOS_SHIFT			0
+
+#define TV_WIN_SIZE		0x68074
+/** Horizontal size of the display window, measured in pixels*/
+# define TV_XSIZE_MASK			0x1fff0000
+# define TV_XSIZE_SHIFT			16
+/**
+ * Vertical size of the display window, measured in pixels.
+ *
+ * Must be even for interlaced modes.
+ */
+# define TV_YSIZE_MASK			0x00000fff
+# define TV_YSIZE_SHIFT			0
+
+#define TV_FILTER_CTL_1		0x68080
+/**
+ * Enables automatic scaling calculation.
+ *
+ * If set, the rest of the registers are ignored, and the calculated values can
+ * be read back from the register.
+ */
+# define TV_AUTO_SCALE			(1 << 31)
+/**
+ * Disables the vertical filter.
+ *
+ * This is required on modes more than 1024 pixels wide */
+# define TV_V_FILTER_BYPASS		(1 << 29)
+/** Enables adaptive vertical filtering */
+# define TV_VADAPT			(1 << 28)
+# define TV_VADAPT_MODE_MASK		(3 << 26)
+/** Selects the least adaptive vertical filtering mode */
+# define TV_VADAPT_MODE_LEAST		(0 << 26)
+/** Selects the moderately adaptive vertical filtering mode */
+# define TV_VADAPT_MODE_MODERATE	(1 << 26)
+/** Selects the most adaptive vertical filtering mode */
+# define TV_VADAPT_MODE_MOST		(3 << 26)
+/**
+ * Sets the horizontal scaling factor.
+ *
+ * This should be the fractional part of the horizontal scaling factor divided
+ * by the oversampling rate.  TV_HSCALE should be less than 1, and set to:
+ *
+ * (src width - 1) / ((oversample * dest width) - 1)
+ */
+# define TV_HSCALE_FRAC_MASK		0x00003fff
+# define TV_HSCALE_FRAC_SHIFT		0
+
+#define TV_FILTER_CTL_2		0x68084
+/**
+ * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
+ *
+ * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
+ */
+# define TV_VSCALE_INT_MASK		0x00038000
+# define TV_VSCALE_INT_SHIFT		15
+/**
+ * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
+ *
+ * \sa TV_VSCALE_INT_MASK
+ */
+# define TV_VSCALE_FRAC_MASK		0x00007fff
+# define TV_VSCALE_FRAC_SHIFT		0
+
+#define TV_FILTER_CTL_3		0x68088
+/**
+ * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
+ *
+ * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
+ *
+ * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
+ */
+# define TV_VSCALE_IP_INT_MASK		0x00038000
+# define TV_VSCALE_IP_INT_SHIFT		15
+/**
+ * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
+ *
+ * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
+ *
+ * \sa TV_VSCALE_IP_INT_MASK
+ */
+# define TV_VSCALE_IP_FRAC_MASK		0x00007fff
+# define TV_VSCALE_IP_FRAC_SHIFT		0
+
+#define TV_CC_CONTROL		0x68090
+# define TV_CC_ENABLE			(1 << 31)
+/**
+ * Specifies which field to send the CC data in.
+ *
+ * CC data is usually sent in field 0.
+ */
+# define TV_CC_FID_MASK			(1 << 27)
+# define TV_CC_FID_SHIFT		27
+/** Sets the horizontal position of the CC data.  Usually 135. */
+# define TV_CC_HOFF_MASK		0x03ff0000
+# define TV_CC_HOFF_SHIFT		16
+/** Sets the vertical position of the CC data.  Usually 21 */
+# define TV_CC_LINE_MASK		0x0000003f
+# define TV_CC_LINE_SHIFT		0
+
+#define TV_CC_DATA		0x68094
+# define TV_CC_RDY			(1 << 31)
+/** Second word of CC data to be transmitted. */
+# define TV_CC_DATA_2_MASK		0x007f0000
+# define TV_CC_DATA_2_SHIFT		16
+/** First word of CC data to be transmitted. */
+# define TV_CC_DATA_1_MASK		0x0000007f
+# define TV_CC_DATA_1_SHIFT		0
+
+#define TV_H_LUMA_0		0x68100
+#define TV_H_LUMA_59		0x681ec
+#define TV_H_CHROMA_0		0x68200
+#define TV_H_CHROMA_59		0x682ec
+#define TV_V_LUMA_0		0x68300
+#define TV_V_LUMA_42		0x683a8
+#define TV_V_CHROMA_0		0x68400
+#define TV_V_CHROMA_42		0x684a8
+
+/* Display & cursor control */
+
+/* Pipe A */
+#define PIPEADSL		0x70000
+#define PIPEACONF		0x70008
+#define   PIPEACONF_ENABLE	(1<<31)
+#define   PIPEACONF_DISABLE	0
+#define   PIPEACONF_DOUBLE_WIDE	(1<<30)
+#define   I965_PIPECONF_ACTIVE	(1<<30)
+#define   PIPEACONF_SINGLE_WIDE	0
+#define   PIPEACONF_PIPE_UNLOCKED 0
+#define   PIPEACONF_PIPE_LOCKED	(1<<25)
+#define   PIPEACONF_PALETTE	0
+#define   PIPEACONF_GAMMA		(1<<24)
+#define   PIPECONF_FORCE_BORDER	(1<<25)
+#define   PIPECONF_PROGRESSIVE	(0 << 21)
+#define   PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
+#define   PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
+#define PIPEASTAT		0x70024
+#define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
+#define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
+#define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
+#define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
+#define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
+#define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
+#define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
+#define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
+#define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
+#define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
+#define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
+#define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
+#define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
+#define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
+#define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
+#define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
+#define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
+#define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
+#define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
+#define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
+#define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
+#define   PIPE_DPST_EVENT_STATUS		(1UL<<7)
+#define   PIPE_LEGACY_BLC_EVENT_STATUS		(1UL<<6)
+#define   PIPE_ODD_FIELD_INTERRUPT_STATUS	(1UL<<5)
+#define   PIPE_EVEN_FIELD_INTERRUPT_STATUS	(1UL<<4)
+#define   PIPE_HOTPLUG_TV_INTERRUPT_STATUS	(1UL<<2) /* pre-965 */
+#define   PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL<<2) /* 965 or later */
+#define   PIPE_VBLANK_INTERRUPT_STATUS		(1UL<<1)
+#define   PIPE_OVERLAY_UPDATED_STATUS		(1UL<<0)
+
+#define DSPARB			0x70030
+#define   DSPARB_CSTART_MASK	(0x7f << 7)
+#define   DSPARB_CSTART_SHIFT	7
+#define   DSPARB_BSTART_MASK	(0x7f)
+#define   DSPARB_BSTART_SHIFT	0
+/*
+ * The two pipe frame counter registers are not synchronized, so
+ * reading a stable value is somewhat tricky. The following code
+ * should work:
+ *
+ *  do {
+ *    high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
+ *             PIPE_FRAME_HIGH_SHIFT;
+ *    low1 =  ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
+ *             PIPE_FRAME_LOW_SHIFT);
+ *    high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
+ *             PIPE_FRAME_HIGH_SHIFT);
+ *  } while (high1 != high2);
+ *  frame = (high1 << 8) | low1;
+ */
+#define PIPEAFRAMEHIGH          0x70040
+#define   PIPE_FRAME_HIGH_MASK    0x0000ffff
+#define   PIPE_FRAME_HIGH_SHIFT   0
+#define PIPEAFRAMEPIXEL         0x70044
+#define   PIPE_FRAME_LOW_MASK     0xff000000
+#define   PIPE_FRAME_LOW_SHIFT    24
+#define   PIPE_PIXEL_MASK         0x00ffffff
+#define   PIPE_PIXEL_SHIFT        0
+/* GM45+ just has to be different */
+#define PIPEA_FRMCOUNT_GM45	0x70040
+#define PIPEA_FLIPCOUNT_GM45	0x70044
+
+/* Cursor A & B regs */
+#define CURACNTR		0x70080
+#define   CURSOR_MODE_DISABLE   0x00
+#define   CURSOR_MODE_64_32B_AX 0x07
+#define   CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
+#define   MCURSOR_GAMMA_ENABLE  (1 << 26)
+#define CURABASE		0x70084
+#define CURAPOS			0x70088
+#define   CURSOR_POS_MASK       0x007FF
+#define   CURSOR_POS_SIGN       0x8000
+#define   CURSOR_X_SHIFT        0
+#define   CURSOR_Y_SHIFT        16
+#define CURBCNTR		0x700c0
+#define CURBBASE		0x700c4
+#define CURBPOS			0x700c8
+
+/* Display A control */
+#define DSPACNTR                0x70180
+#define   DISPLAY_PLANE_ENABLE			(1<<31)
+#define   DISPLAY_PLANE_DISABLE			0
+#define   DISPPLANE_GAMMA_ENABLE		(1<<30)
+#define   DISPPLANE_GAMMA_DISABLE		0
+#define   DISPPLANE_PIXFORMAT_MASK		(0xf<<26)
+#define   DISPPLANE_8BPP			(0x2<<26)
+#define   DISPPLANE_15_16BPP			(0x4<<26)
+#define   DISPPLANE_16BPP			(0x5<<26)
+#define   DISPPLANE_32BPP_NO_ALPHA		(0x6<<26)
+#define   DISPPLANE_32BPP			(0x7<<26)
+#define   DISPPLANE_STEREO_ENABLE		(1<<25)
+#define   DISPPLANE_STEREO_DISABLE		0
+#define   DISPPLANE_SEL_PIPE_MASK		(1<<24)
+#define   DISPPLANE_SEL_PIPE_A			0
+#define   DISPPLANE_SEL_PIPE_B			(1<<24)
+#define   DISPPLANE_SRC_KEY_ENABLE		(1<<22)
+#define   DISPPLANE_SRC_KEY_DISABLE		0
+#define   DISPPLANE_LINE_DOUBLE			(1<<20)
+#define   DISPPLANE_NO_LINE_DOUBLE		0
+#define   DISPPLANE_STEREO_POLARITY_FIRST	0
+#define   DISPPLANE_STEREO_POLARITY_SECOND	(1<<18)
+#define DSPAADDR		0x70184
+#define DSPASTRIDE		0x70188
+#define DSPAPOS			0x7018C /* reserved */
+#define DSPASIZE		0x70190
+#define DSPASURF		0x7019C /* 965+ only */
+#define DSPATILEOFF		0x701A4 /* 965+ only */
+
+/* VBIOS flags */
+#define SWF00			0x71410
+#define SWF01			0x71414
+#define SWF02			0x71418
+#define SWF03			0x7141c
+#define SWF04			0x71420
+#define SWF05			0x71424
+#define SWF06			0x71428
+#define SWF10			0x70410
+#define SWF11			0x70414
+#define SWF14			0x71420
+#define SWF30			0x72414
+#define SWF31			0x72418
+#define SWF32			0x7241c
+
+/* Pipe B */
+#define PIPEBDSL		0x71000
+#define PIPEBCONF		0x71008
+#define PIPEBSTAT		0x71024
+#define PIPEBFRAMEHIGH		0x71040
+#define PIPEBFRAMEPIXEL		0x71044
+#define PIPEB_FRMCOUNT_GM45	0x71040
+#define PIPEB_FLIPCOUNT_GM45	0x71044
+
+
+/* Display B control */
+#define DSPBCNTR		0x71180
+#define   DISPPLANE_ALPHA_TRANS_ENABLE		(1<<15)
+#define   DISPPLANE_ALPHA_TRANS_DISABLE		0
+#define   DISPPLANE_SPRITE_ABOVE_DISPLAY	0
+#define   DISPPLANE_SPRITE_ABOVE_OVERLAY	(1)
+#define DSPBADDR		0x71184
+#define DSPBSTRIDE		0x71188
+#define DSPBPOS			0x7118C
+#define DSPBSIZE		0x71190
+#define DSPBSURF		0x7119C
+#define DSPBTILEOFF		0x711A4
+
+/* VBIOS regs */
+#define VGACNTRL		0x71400
+# define VGA_DISP_DISABLE			(1 << 31)
+# define VGA_2X_MODE				(1 << 30)
+# define VGA_PIPE_B_SELECT			(1 << 29)
+
+#endif /* _I915_REG_H_ */
diff --git a/sys/dev/drm/i915_suspend.c b/sys/dev/drm/i915_suspend.c
new file mode 100644
index 0000000000..afac3b3736
--- /dev/null
+++ b/sys/dev/drm/i915_suspend.c
@@ -0,0 +1,524 @@
+/* i915_suspend.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
+ */
+/*
+ *
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/i915_drm.h"
+#include "dev/drm/i915_drv.h"
+
+static bool i915_pipe_enabled(struct drm_device *dev, enum i915_pipe pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	if (pipe == PIPE_A)
+		return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
+	else
+		return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
+}
+
+static void i915_save_palette(struct drm_device *dev, enum i915_pipe pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
+	u32 *array;
+	int i;
+
+	if (!i915_pipe_enabled(dev, pipe))
+		return;
+
+	if (pipe == PIPE_A)
+		array = dev_priv->save_palette_a;
+	else
+		array = dev_priv->save_palette_b;
+
+	for(i = 0; i < 256; i++)
+		array[i] = I915_READ(reg + (i << 2));
+}
+
+static void i915_restore_palette(struct drm_device *dev, enum i915_pipe pipe)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
+	u32 *array;
+	int i;
+
+	if (!i915_pipe_enabled(dev, pipe))
+		return;
+
+	if (pipe == PIPE_A)
+		array = dev_priv->save_palette_a;
+	else
+		array = dev_priv->save_palette_b;
+
+	for(i = 0; i < 256; i++)
+		I915_WRITE(reg + (i << 2), array[i]);
+}
+
+static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE8(index_port, reg);
+	return I915_READ8(data_port);
+}
+
+static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_READ8(st01);
+	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
+	return I915_READ8(VGA_AR_DATA_READ);
+}
+
+static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_READ8(st01);
+	I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
+	I915_WRITE8(VGA_AR_DATA_WRITE, val);
+}
+
+static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE8(index_port, reg);
+	I915_WRITE8(data_port, val);
+}
+
+static void i915_save_vga(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int i;
+	u16 cr_index, cr_data, st01;
+
+	/* VGA color palette registers */
+	dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
+
+	/* MSR bits */
+	dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
+	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
+		cr_index = VGA_CR_INDEX_CGA;
+		cr_data = VGA_CR_DATA_CGA;
+		st01 = VGA_ST01_CGA;
+	} else {
+		cr_index = VGA_CR_INDEX_MDA;
+		cr_data = VGA_CR_DATA_MDA;
+		st01 = VGA_ST01_MDA;
+	}
+
+	/* CRT controller regs */
+	i915_write_indexed(dev, cr_index, cr_data, 0x11,
+			   i915_read_indexed(dev, cr_index, cr_data, 0x11) &
+			   (~0x80));
+	for (i = 0; i <= 0x24; i++)
+		dev_priv->saveCR[i] =
+			i915_read_indexed(dev, cr_index, cr_data, i);
+	/* Make sure we don't turn off CR group 0 writes */
+	dev_priv->saveCR[0x11] &= ~0x80;
+
+	/* Attribute controller registers */
+	I915_READ8(st01);
+	dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
+	for (i = 0; i <= 0x14; i++)
+		dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
+	I915_READ8(st01);
+	I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
+	I915_READ8(st01);
+
+	/* Graphics controller registers */
+	for (i = 0; i < 9; i++)
+		dev_priv->saveGR[i] =
+			i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
+
+	dev_priv->saveGR[0x10] =
+		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
+	dev_priv->saveGR[0x11] =
+		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
+	dev_priv->saveGR[0x18] =
+		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
+
+	/* Sequencer registers */
+	for (i = 0; i < 8; i++)
+		dev_priv->saveSR[i] =
+			i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
+}
+
+static void i915_restore_vga(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int i;
+	u16 cr_index, cr_data, st01;
+
+	/* MSR bits */
+	I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
+	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
+		cr_index = VGA_CR_INDEX_CGA;
+		cr_data = VGA_CR_DATA_CGA;
+		st01 = VGA_ST01_CGA;
+	} else {
+		cr_index = VGA_CR_INDEX_MDA;
+		cr_data = VGA_CR_DATA_MDA;
+		st01 = VGA_ST01_MDA;
+	}
+
+	/* Sequencer registers, don't write SR07 */
+	for (i = 0; i < 7; i++)
+		i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
+				   dev_priv->saveSR[i]);
+
+	/* CRT controller regs */
+	/* Enable CR group 0 writes */
+	i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
+	for (i = 0; i <= 0x24; i++)
+		i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
+
+	/* Graphics controller regs */
+	for (i = 0; i < 9; i++)
+		i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
+				   dev_priv->saveGR[i]);
+
+	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
+			   dev_priv->saveGR[0x10]);
+	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
+			   dev_priv->saveGR[0x11]);
+	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
+			   dev_priv->saveGR[0x18]);
+
+	/* Attribute controller registers */
+	I915_READ8(st01); /* switch back to index mode */
+	for (i = 0; i <= 0x14; i++)
+		i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
+	I915_READ8(st01); /* switch back to index mode */
+	I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
+	I915_READ8(st01);
+
+	/* VGA color palette registers */
+	I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
+}
+
+int i915_save_state(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int i;
+
+#if defined(__FreeBSD__) || defined(__DragonFly__)
+	dev_priv->saveLBB = (u8) pci_read_config(dev->device, LBB, 1);
+#else
+	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
+#endif
+
+	/* Render Standby */
+	if (IS_I965G(dev) && IS_MOBILE(dev))
+		dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
+
+	/* Hardware status page */
+	dev_priv->saveHWS = I915_READ(HWS_PGA);
+
+	/* Display arbitration control */
+	dev_priv->saveDSPARB = I915_READ(DSPARB);
+
+	/* Pipe & plane A info */
+	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
+	dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
+	dev_priv->saveFPA0 = I915_READ(FPA0);
+	dev_priv->saveFPA1 = I915_READ(FPA1);
+	dev_priv->saveDPLL_A = I915_READ(DPLL_A);
+	if (IS_I965G(dev))
+		dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
+	dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
+	dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
+	dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
+	dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
+	dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
+	dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
+	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
+
+	dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
+	dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
+	dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
+	dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
+	dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
+	if (IS_I965G(dev)) {
+		dev_priv->saveDSPASURF = I915_READ(DSPASURF);
+		dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
+	}
+	i915_save_palette(dev, PIPE_A);
+	dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
+
+	/* Pipe & plane B info */
+	dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
+	dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
+	dev_priv->saveFPB0 = I915_READ(FPB0);
+	dev_priv->saveFPB1 = I915_READ(FPB1);
+	dev_priv->saveDPLL_B = I915_READ(DPLL_B);
+	if (IS_I965G(dev))
+		dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
+	dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
+	dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
+	dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
+	dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
+	dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
+	dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
+	dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
+
+	dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
+	dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
+	dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
+	dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
+	dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
+	if (IS_I965GM(dev) || IS_GM45(dev)) {
+		dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
+		dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
+	}
+	i915_save_palette(dev, PIPE_B);
+	dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
+
+	/* CRT state */
+	dev_priv->saveADPA = I915_READ(ADPA);
+
+	/* LVDS state */
+	dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
+	dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
+	dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
+	if (IS_I965G(dev))
+		dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
+	if (IS_MOBILE(dev) && !IS_I830(dev))
+		dev_priv->saveLVDS = I915_READ(LVDS);
+	if (!IS_I830(dev) && !IS_845G(dev))
+		dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
+	dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
+	dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
+	dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
+
+	/* FIXME: save TV & SDVO state */
+
+	/* FBC state */
+	dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
+	dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
+	dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
+	dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
+
+	/* Interrupt state */
+	dev_priv->saveIIR = I915_READ(IIR);
+	dev_priv->saveIER = I915_READ(IER);
+	dev_priv->saveIMR = I915_READ(IMR);
+
+	/* VGA state */
+	dev_priv->saveVGA0 = I915_READ(VGA0);
+	dev_priv->saveVGA1 = I915_READ(VGA1);
+	dev_priv->saveVGA_PD = I915_READ(VGA_PD);
+	dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
+
+	/* Clock gating state */
+	dev_priv->saveD_STATE = I915_READ(D_STATE);
+	dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
+
+	/* Cache mode state */
+	dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
+
+	/* Memory Arbitration state */
+	dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
+
+	/* Scratch space */
+	for (i = 0; i < 16; i++) {
+		dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
+		dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
+	}
+	for (i = 0; i < 3; i++)
+		dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
+
+	i915_save_vga(dev);
+
+	return 0;
+}
+
+int i915_restore_state(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int i;
+
+#if defined(__FreeBSD__) || defined(__DragonFly__)
+	pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1);
+#else
+	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
+#endif
+
+	/* Render Standby */
+	if (IS_I965G(dev) && IS_MOBILE(dev))
+		I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
+
+	/* Hardware status page */
+	I915_WRITE(HWS_PGA, dev_priv->saveHWS);
+
+	/* Display arbitration */
+	I915_WRITE(DSPARB, dev_priv->saveDSPARB);
+
+	/* Pipe & plane A info */
+	/* Prime the clock */
+	if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
+		I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
+			   ~DPLL_VCO_ENABLE);
+		DRM_UDELAY(150);
+	}
+	I915_WRITE(FPA0, dev_priv->saveFPA0);
+	I915_WRITE(FPA1, dev_priv->saveFPA1);
+	/* Actually enable it */
+	I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
+	DRM_UDELAY(150);
+	if (IS_I965G(dev))
+		I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
+	DRM_UDELAY(150);
+
+	/* Restore mode */
+	I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
+	I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
+	I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
+	I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
+	I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
+	I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
+	I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
+
+	/* Restore plane info */
+	I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
+	I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
+	I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
+	I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
+	I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
+	if (IS_I965G(dev)) {
+		I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
+		I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
+	}
+
+	I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
+
+	i915_restore_palette(dev, PIPE_A);
+	/* Enable the plane */
+	I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
+	I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
+
+	/* Pipe & plane B info */
+	if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
+		I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
+			   ~DPLL_VCO_ENABLE);
+		DRM_UDELAY(150);
+	}
+	I915_WRITE(FPB0, dev_priv->saveFPB0);
+	I915_WRITE(FPB1, dev_priv->saveFPB1);
+	/* Actually enable it */
+	I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
+	DRM_UDELAY(150);
+	if (IS_I965G(dev))
+		I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
+	DRM_UDELAY(150);
+
+	/* Restore mode */
+	I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
+	I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
+	I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
+	I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
+	I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
+	I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
+	I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
+
+	/* Restore plane info */
+	I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
+	I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
+	I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
+	I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
+	I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
+	if (IS_I965G(dev)) {
+		I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
+		I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
+	}
+
+	I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
+
+	i915_restore_palette(dev, PIPE_B);
+	/* Enable the plane */
+	I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
+	I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
+
+	/* CRT state */
+	I915_WRITE(ADPA, dev_priv->saveADPA);
+
+	/* LVDS state */
+	if (IS_I965G(dev))
+		I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
+	if (IS_MOBILE(dev) && !IS_I830(dev))
+		I915_WRITE(LVDS, dev_priv->saveLVDS);
+	if (!IS_I830(dev) && !IS_845G(dev))
+		I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
+
+	I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
+	I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
+	I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
+	I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
+	I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
+	I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
+
+	/* FIXME: restore TV & SDVO state */
+
+	/* FBC info */
+	I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
+	I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
+	I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
+	I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
+
+	/* VGA state */
+	I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
+	I915_WRITE(VGA0, dev_priv->saveVGA0);
+	I915_WRITE(VGA1, dev_priv->saveVGA1);
+	I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
+	DRM_UDELAY(150);
+
+	/* Clock gating state */
+	I915_WRITE (D_STATE, dev_priv->saveD_STATE);
+	I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
+
+	/* Cache mode state */
+	I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
+
+	/* Memory arbitration state */
+	I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
+
+	for (i = 0; i < 16; i++) {
+		I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
+		I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
+	}
+	for (i = 0; i < 3; i++)
+		I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
+
+	i915_restore_vga(dev);
+
+	return 0;
+}
+
diff --git a/sys/dev/drm/mach64_dma.c b/sys/dev/drm/mach64_dma.c
index 51a82508f6..c7236d47f8 100644
--- a/sys/dev/drm/mach64_dma.c
+++ b/sys/dev/drm/mach64_dma.c
@@ -9,7 +9,7 @@
  * \author José Fonseca <j_r_fonseca@yahoo.co.uk>
  */
 
-/*
+/*-
  * Copyright 2000 Gareth Hughes
  * Copyright 2002 Frank C. Earl
  * Copyright 2002-2003 Leif Delgass
@@ -32,14 +32,12 @@
  * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/mach64_dma.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "mach64_drm.h"
-#include "mach64_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/mach64_drm.h"
+#include "dev/drm/mach64_drv.h"
 
 /*******************************************************************/
 /** \name Engine, FIFO control */
@@ -836,8 +834,14 @@ static int mach64_bm_dma_test(struct drm_device * dev)
 
 	/* FIXME: get a dma buffer from the freelist here */
 	DRM_DEBUG("Allocating data memory ...\n");
+#if defined(__FreeBSD__) || defined(__DragonFly__)
+	DRM_UNLOCK();
+#endif
 	cpu_addr_dmah =
 	    drm_pci_alloc(dev, 0x1000, 0x1000, 0xfffffffful);
+#if defined(__FreeBSD__) || defined(__DragonFly__)
+	DRM_LOCK();
+#endif
 	if (!cpu_addr_dmah) {
 		DRM_INFO("data-memory allocation failed!\n");
 		return -ENOMEM;
diff --git a/sys/dev/drm/mach64_drm.h b/sys/dev/drm/mach64_drm.h
index f5cb20e00d..6189ef138f 100644
--- a/sys/dev/drm/mach64_drm.h
+++ b/sys/dev/drm/mach64_drm.h
@@ -1,7 +1,7 @@
 /* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
  * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com
  */
-/*
+/*-
  * Copyright 2000 Gareth Hughes
  * Copyright 2002 Frank C. Earl
  * Copyright 2002-2003 Leif Delgass
@@ -29,8 +29,6 @@
  *    Gareth Hughes <gareth@valinux.com>
  *    Frank C. Earl <fearl@airmail.net>
  *    Leif Delgass <ldelgass@retinalburn.net>
- *
- * $DragonFly: src/sys/dev/drm/mach64_drm.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __MACH64_DRM_H__
diff --git a/sys/dev/drm/mach64_drv.c b/sys/dev/drm/mach64_drv.c
index c92275e577..e3af15bd82 100644
--- a/sys/dev/drm/mach64_drv.c
+++ b/sys/dev/drm/mach64_drv.c
@@ -28,75 +28,93 @@
  * Authors:
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/mach64_drv.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-
 #include <sys/types.h>
 
-#include "drmP.h"
-#include "drm.h"
-#include "mach64_drm.h"
-#include "mach64_drv.h"
-#include "drm_pciids.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/mach64_drm.h"
+#include "dev/drm/mach64_drv.h"
+#include "dev/drm/drm_pciids.h"
 
 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
 static drm_pci_id_list_t mach64_pciidlist[] = {
 	mach64_PCI_IDS
 };
 
-static void mach64_configure(drm_device_t *dev)
+static void mach64_configure(struct drm_device *dev)
 {
-	dev->driver.buf_priv_size	= 1; /* No dev_priv */
-	dev->driver.lastclose		= mach64_driver_lastclose;
-	dev->driver.vblank_wait		= mach64_driver_vblank_wait;
-	dev->driver.irq_preinstall	= mach64_driver_irq_preinstall;
-	dev->driver.irq_postinstall	= mach64_driver_irq_postinstall;
-	dev->driver.irq_uninstall	= mach64_driver_irq_uninstall;
-	dev->driver.irq_handler		= mach64_driver_irq_handler;
-	dev->driver.dma_ioctl		= mach64_dma_buffers;
-
-	dev->driver.ioctls		= mach64_ioctls;
-	dev->driver.max_ioctl		= mach64_max_ioctl;
-
-	dev->driver.name		= DRIVER_NAME;
-	dev->driver.desc		= DRIVER_DESC;
-	dev->driver.date		= DRIVER_DATE;
-	dev->driver.major		= DRIVER_MAJOR;
-	dev->driver.minor		= DRIVER_MINOR;
-	dev->driver.patchlevel		= DRIVER_PATCHLEVEL;
-
-	dev->driver.use_agp		= 1;
-	dev->driver.use_mtrr		= 1;
-	dev->driver.use_pci_dma		= 1;
-	dev->driver.use_dma		= 1;
-	dev->driver.use_irq		= 1;
-	dev->driver.use_vbl_irq		= 1;
+	dev->driver->driver_features =
+	    DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA |
+	    DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ;
+
+	dev->driver->buf_priv_size	= 1; /* No dev_priv */
+	dev->driver->load		= mach64_driver_load;
+	dev->driver->lastclose		= mach64_driver_lastclose;
+	dev->driver->get_vblank_counter	= mach64_get_vblank_counter;
+	dev->driver->enable_vblank	= mach64_enable_vblank;
+	dev->driver->disable_vblank	= mach64_disable_vblank;
+	dev->driver->irq_preinstall	= mach64_driver_irq_preinstall;
+	dev->driver->irq_postinstall	= mach64_driver_irq_postinstall;
+	dev->driver->irq_uninstall	= mach64_driver_irq_uninstall;
+	dev->driver->irq_handler	= mach64_driver_irq_handler;
+	dev->driver->dma_ioctl		= mach64_dma_buffers;
+
+	dev->driver->ioctls		= mach64_ioctls;
+	dev->driver->max_ioctl		= mach64_max_ioctl;
+
+	dev->driver->name		= DRIVER_NAME;
+	dev->driver->desc		= DRIVER_DESC;
+	dev->driver->date		= DRIVER_DATE;
+	dev->driver->major		= DRIVER_MAJOR;
+	dev->driver->minor		= DRIVER_MINOR;
+	dev->driver->patchlevel		= DRIVER_PATCHLEVEL;
 }
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 static int
-mach64_probe(device_t dev)
+mach64_probe(device_t kdev)
 {
-	return drm_probe(dev, mach64_pciidlist);
+	return drm_probe(kdev, mach64_pciidlist);
 }
 
 static int
-mach64_attach(device_t nbdev)
+mach64_attach(device_t kdev)
 {
-	drm_device_t *dev = device_get_softc(nbdev);
+	struct drm_device *dev = device_get_softc(kdev);
+
+	dev->driver = malloc(sizeof(struct drm_driver_info), DRM_MEM_DRIVER,
+	    M_WAITOK | M_ZERO);
 
-	bzero(dev, sizeof(drm_device_t));
 	mach64_configure(dev);
-	return drm_attach(nbdev, mach64_pciidlist);
+
+	return drm_attach(kdev, mach64_pciidlist);
+}
+
+int
+mach64_driver_load(struct drm_device * dev, unsigned long flags)
+{
+        return drm_vblank_init(dev, 1);
+}
+
+static int
+mach64_detach(device_t kdev)
+{
+	struct drm_device *dev = device_get_softc(kdev);
+	int ret;
+
+	ret = drm_detach(kdev);
+
+	free(dev->driver, DRM_MEM_DRIVER);
+
+	return ret;
 }
 
 static device_method_t mach64_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		mach64_probe),
 	DEVMETHOD(device_attach,	mach64_attach),
-	DEVMETHOD(device_detach,	drm_detach),
+	DEVMETHOD(device_detach,	mach64_detach),
 
 	{ 0, 0 }
 };
@@ -104,7 +122,7 @@ static device_method_t mach64_methods[] = {
 static driver_t mach64_driver = {
 	"drm",
 	mach64_methods,
-	sizeof(drm_device_t)
+	sizeof(struct drm_device)
 };
 
 extern devclass_t drm_devclass;
@@ -114,7 +132,3 @@ DRIVER_MODULE(mach64, vgapci, mach64_driver, drm_devclass, 0, 0);
 DRIVER_MODULE(mach64, pci, mach64_driver, drm_devclass, 0, 0);
 #endif
 MODULE_DEPEND(mach64, drm, 1, 1, 1);
-
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-CFDRIVER_DECL(mach64, DV_TTY, NULL);
-#endif
diff --git a/sys/dev/drm/mach64_drv.h b/sys/dev/drm/mach64_drv.h
index 60e4716d8c..e3d9cf000a 100644
--- a/sys/dev/drm/mach64_drv.h
+++ b/sys/dev/drm/mach64_drv.h
@@ -1,7 +1,7 @@
 /* mach64_drv.h -- Private header for mach64 driver -*- linux-c -*-
  * Created: Fri Nov 24 22:07:58 2000 by gareth@valinux.com
  */
-/*
+/*-
  * Copyright 2000 Gareth Hughes
  * Copyright 2002 Frank C. Earl
  * Copyright 2002-2003 Leif Delgass
@@ -30,8 +30,6 @@
  *    Frank C. Earl <fearl@airmail.net>
  *    Leif Delgass <ldelgass@retinalburn.net>
  *    José Fonseca <j_r_fonseca@yahoo.co.uk>
- *
- * $DragonFly: src/sys/dev/drm/mach64_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __MACH64_DRV_H__
@@ -98,6 +96,8 @@ typedef struct drm_mach64_private {
 	unsigned int depth_bpp;
 	unsigned int depth_offset, depth_pitch;
 
+	atomic_t vbl_received;          /**< Number of vblanks received. */
+
 	u32 front_offset_pitch;
 	u32 back_offset_pitch;
 	u32 depth_offset_pitch;
@@ -162,13 +162,15 @@ extern int mach64_dma_blit(struct drm_device *dev, void *data,
 			   struct drm_file *file_priv);
 extern int mach64_get_param(struct drm_device *dev, void *data,
 			    struct drm_file *file_priv);
-extern int mach64_driver_vblank_wait(struct drm_device * dev,
-				     unsigned int *sequence);
 
+extern int mach64_driver_load(struct drm_device * dev, unsigned long flags);
+extern u32 mach64_get_vblank_counter(struct drm_device *dev, int crtc);
+extern int mach64_enable_vblank(struct drm_device *dev, int crtc);
+extern void mach64_disable_vblank(struct drm_device *dev, int crtc);
 extern irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS);
-extern void mach64_driver_irq_preinstall(struct drm_device * dev);
-extern void mach64_driver_irq_postinstall(struct drm_device * dev);
-extern void mach64_driver_irq_uninstall(struct drm_device * dev);
+extern void mach64_driver_irq_preinstall(struct drm_device *dev);
+extern int mach64_driver_irq_postinstall(struct drm_device *dev);
+extern void mach64_driver_irq_uninstall(struct drm_device *dev);
 
 /* ================================================================
  * Registers
diff --git a/sys/dev/drm/mach64_irq.c b/sys/dev/drm/mach64_irq.c
index 2b5e3f47d2..fae8897303 100644
--- a/sys/dev/drm/mach64_irq.c
+++ b/sys/dev/drm/mach64_irq.c
@@ -33,20 +33,17 @@
  *    Keith Whitwell <keith@tungstengraphics.com>
  *    Eric Anholt <anholt@FreeBSD.org>
  *    Leif Delgass <ldelgass@retinalburn.net>
- *
- * $DragonFly: src/sys/dev/drm/mach64_irq.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "mach64_drm.h"
-#include "mach64_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/mach64_drm.h"
+#include "dev/drm/mach64_drv.h"
 
 irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS)
 {
-	struct drm_device *dev = (struct drm_device *) arg;
-	drm_mach64_private_t *dev_priv =
-	    (drm_mach64_private_t *) dev->dev_private;
+	struct drm_device *dev = arg;
+	drm_mach64_private_t *dev_priv = dev->dev_private;
 	int status;
 
 	status = MACH64_READ(MACH64_CRTC_INT_CNTL);
@@ -64,74 +61,98 @@ irqreturn_t mach64_driver_irq_handler(DRM_IRQ_ARGS)
 			     (status & ~MACH64_CRTC_INT_ACKS)
 			     | MACH64_CRTC_VBLANK_INT);
 
-		atomic_inc(&dev->vbl_received);
-		DRM_WAKEUP(&dev->vbl_queue);
-		drm_vbl_send_signals(dev);
+		atomic_inc(&dev_priv->vbl_received);
+		drm_handle_vblank(dev, 0);
 		return IRQ_HANDLED;
 	}
 	return IRQ_NONE;
 }
 
-int mach64_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
+u32 mach64_get_vblank_counter(struct drm_device * dev, int crtc)
 {
-	unsigned int cur_vblank;
-	int ret = 0;
+	const drm_mach64_private_t *const dev_priv = dev->dev_private;
 
-	/* Assume that the user has missed the current sequence number
-	 * by about a day rather than she wants to wait for years
-	 * using vertical blanks...
-	 */
-	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
-		    (((cur_vblank = atomic_read(&dev->vbl_received))
-		      - *sequence) <= (1 << 23)));
+	if (crtc != 0)
+		return 0;
+
+	return atomic_read(&dev_priv->vbl_received);
+}
+
+int mach64_enable_vblank(struct drm_device * dev, int crtc)
+{
+	drm_mach64_private_t *dev_priv = dev->dev_private;
+	u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL);
+
+	if (crtc != 0) {
+		DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
+			  crtc);
+		return -EINVAL;
+	}
 
-	*sequence = cur_vblank;
+	DRM_DEBUG("before enable vblank CRTC_INT_CTNL: 0x%08x\n", status);
 
-	return ret;
+	/* Turn on VBLANK interrupt */
+	MACH64_WRITE(MACH64_CRTC_INT_CNTL, MACH64_READ(MACH64_CRTC_INT_CNTL)
+		     | MACH64_CRTC_VBLANK_INT_EN);
+
+	return 0;
 }
 
-/* drm_dma.h hooks
-*/
-void mach64_driver_irq_preinstall(struct drm_device * dev)
+void mach64_disable_vblank(struct drm_device * dev, int crtc)
 {
-	drm_mach64_private_t *dev_priv =
-	    (drm_mach64_private_t *) dev->dev_private;
+	if (crtc != 0) {
+		DRM_ERROR("tried to disable vblank on non-existent crtc %d\n",
+			  crtc);
+		return;
+	}
+
+	/*
+	 * FIXME: implement proper interrupt disable by using the vblank
+	 * counter register (if available).
+	 */
+}
 
+static void mach64_disable_vblank_local(struct drm_device * dev, int crtc)
+{
+	drm_mach64_private_t *dev_priv = dev->dev_private;
 	u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL);
 
-	DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status);
+	if (crtc != 0) {
+		DRM_ERROR("tried to disable vblank on non-existent crtc %d\n",
+			  crtc);
+		return;
+	}
+
+	DRM_DEBUG("before disable vblank CRTC_INT_CTNL: 0x%08x\n", status);
 
 	/* Disable and clear VBLANK interrupt */
 	MACH64_WRITE(MACH64_CRTC_INT_CNTL, (status & ~MACH64_CRTC_VBLANK_INT_EN)
 		     | MACH64_CRTC_VBLANK_INT);
 }
 
-void mach64_driver_irq_postinstall(struct drm_device * dev)
+void mach64_driver_irq_preinstall(struct drm_device * dev)
 {
-	drm_mach64_private_t *dev_priv =
-	    (drm_mach64_private_t *) dev->dev_private;
+	drm_mach64_private_t *dev_priv = dev->dev_private;
 
-	/* Turn on VBLANK interrupt */
-	MACH64_WRITE(MACH64_CRTC_INT_CNTL, MACH64_READ(MACH64_CRTC_INT_CNTL)
-		     | MACH64_CRTC_VBLANK_INT_EN);
+	u32 status = MACH64_READ(MACH64_CRTC_INT_CNTL);
 
-	DRM_DEBUG("after install CRTC_INT_CTNL: 0x%08x\n",
-		  MACH64_READ(MACH64_CRTC_INT_CNTL));
+	DRM_DEBUG("before install CRTC_INT_CTNL: 0x%08x\n", status);
 
+	mach64_disable_vblank_local(dev, 0);
+}
+
+int mach64_driver_irq_postinstall(struct drm_device * dev)
+{
+	return 0;
 }
 
 void mach64_driver_irq_uninstall(struct drm_device * dev)
 {
-	drm_mach64_private_t *dev_priv =
-	    (drm_mach64_private_t *) dev->dev_private;
+	drm_mach64_private_t *dev_priv = dev->dev_private;
 	if (!dev_priv)
 		return;
 
-	/* Disable and clear VBLANK interrupt */
-	MACH64_WRITE(MACH64_CRTC_INT_CNTL,
-		     (MACH64_READ(MACH64_CRTC_INT_CNTL) &
-		      ~MACH64_CRTC_VBLANK_INT_EN)
-		     | MACH64_CRTC_VBLANK_INT);
+	mach64_disable_vblank_local(dev, 0);
 
 	DRM_DEBUG("after uninstall CRTC_INT_CTNL: 0x%08x\n",
 		  MACH64_READ(MACH64_CRTC_INT_CNTL));
diff --git a/sys/dev/drm/mach64_state.c b/sys/dev/drm/mach64_state.c
index 8248f36eae..ec96709018 100644
--- a/sys/dev/drm/mach64_state.c
+++ b/sys/dev/drm/mach64_state.c
@@ -1,7 +1,7 @@
 /* mach64_state.c -- State support for mach64 (Rage Pro) driver -*- linux-c -*-
  * Created: Sun Dec 03 19:20:26 2000 by gareth@valinux.com
  */
-/*
+/*-
  * Copyright 2000 Gareth Hughes
  * Copyright 2002-2003 Leif Delgass
  * All Rights Reserved.
@@ -28,14 +28,12 @@
  *    Gareth Hughes <gareth@valinux.com>
  *    Leif Delgass <ldelgass@retinalburn.net>
  *    José Fonseca <j_r_fonseca@yahoo.co.uk>
- *
- * $DragonFly: src/sys/dev/drm/mach64_state.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "mach64_drm.h"
-#include "mach64_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/mach64_drm.h"
+#include "dev/drm/mach64_drv.h"
 
 /* Interface history:
  *
diff --git a/sys/dev/drm/mga_dma.c b/sys/dev/drm/mga_dma.c
index 49ea3747cb..bec9cb5ba6 100644
--- a/sys/dev/drm/mga_dma.c
+++ b/sys/dev/drm/mga_dma.c
@@ -23,8 +23,6 @@
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/mga_dma.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /**
@@ -37,11 +35,11 @@
  * \author Gareth Hughes <gareth@valinux.com>
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "drm_sarea.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/drm_sarea.h"
+#include "dev/drm/mga_drm.h"
+#include "dev/drm/mga_drv.h"
 
 #define MGA_DEFAULT_USEC_TIMEOUT	10000
 #define MGA_FREELIST_DEBUG		0
@@ -398,6 +396,7 @@ int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf)
 int mga_driver_load(struct drm_device *dev, unsigned long flags)
 {
 	drm_mga_private_t *dev_priv;
+	int ret;
 
 	dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
 	if (!dev_priv)
@@ -417,6 +416,13 @@ int mga_driver_load(struct drm_device *dev, unsigned long flags)
 	dev->types[7] = _DRM_STAT_PRIMARY;
 	dev->types[8] = _DRM_STAT_SECONDARY;
 
+	ret = drm_vblank_init(dev, 1);
+
+	if (ret) {
+		(void) mga_driver_unload(dev);
+		return ret;
+	}
+
 	return 0;
 }
 
diff --git a/sys/dev/drm/mga_drm.h b/sys/dev/drm/mga_drm.h
index 93fda4ff14..c03d322044 100644
--- a/sys/dev/drm/mga_drm.h
+++ b/sys/dev/drm/mga_drm.h
@@ -30,8 +30,6 @@
  *
  * Rewritten by:
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/mga_drm.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __MGA_DRM_H__
diff --git a/sys/dev/drm/mga_drv.c b/sys/dev/drm/mga_drv.c
index 7db6490145..89d9d3e6eb 100644
--- a/sys/dev/drm/mga_drv.c
+++ b/sys/dev/drm/mga_drv.c
@@ -29,14 +29,13 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/mga_drv.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
-#include "drm_pciids.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/mga_drm.h"
+#include "dev/drm/mga_drv.h"
+#include "dev/drm/drm_pciids.h"
 
 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
 static drm_pci_id_list_t mga_pciidlist[] = {
@@ -60,7 +59,7 @@ static drm_pci_id_list_t mga_pciidlist[] = {
  * This function needs to be filled in!  The implementation in
  * linux-core/mga_drv.c shows what needs to be done.
  */
-static int mga_driver_device_is_agp(drm_device_t * dev)
+static int mga_driver_device_is_agp(struct drm_device * dev)
 {
 	device_t bus;
 
@@ -85,63 +84,75 @@ static int mga_driver_device_is_agp(drm_device_t * dev)
 		return DRM_MIGHT_BE_AGP;
 }
 
-static void mga_configure(drm_device_t *dev)
+static void mga_configure(struct drm_device *dev)
 {
-	dev->driver.buf_priv_size	= sizeof(drm_mga_buf_priv_t);
-	dev->driver.load		= mga_driver_load;
-	dev->driver.unload		= mga_driver_unload;
-	dev->driver.lastclose		= mga_driver_lastclose;
-	dev->driver.vblank_wait		= mga_driver_vblank_wait;
-	dev->driver.irq_preinstall	= mga_driver_irq_preinstall;
-	dev->driver.irq_postinstall	= mga_driver_irq_postinstall;
-	dev->driver.irq_uninstall	= mga_driver_irq_uninstall;
-	dev->driver.irq_handler		= mga_driver_irq_handler;
-	dev->driver.dma_ioctl		= mga_dma_buffers;
-	dev->driver.dma_quiescent	= mga_driver_dma_quiescent;
-	dev->driver.device_is_agp	= mga_driver_device_is_agp;
-
-	dev->driver.ioctls		= mga_ioctls;
-	dev->driver.max_ioctl		= mga_max_ioctl;
-
-	dev->driver.name		= DRIVER_NAME;
-	dev->driver.desc		= DRIVER_DESC;
-	dev->driver.date		= DRIVER_DATE;
-	dev->driver.major		= DRIVER_MAJOR;
-	dev->driver.minor		= DRIVER_MINOR;
-	dev->driver.patchlevel		= DRIVER_PATCHLEVEL;
-
-	dev->driver.use_agp		= 1;
-	dev->driver.require_agp		= 1;
-	dev->driver.use_mtrr		= 1;
-	dev->driver.use_dma		= 1;
-	dev->driver.use_irq		= 1;
-	dev->driver.use_vbl_irq		= 1;
+	dev->driver->driver_features =
+	    DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR |
+	    DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ;
+
+	dev->driver->buf_priv_size	= sizeof(drm_mga_buf_priv_t);
+	dev->driver->load		= mga_driver_load;
+	dev->driver->unload		= mga_driver_unload;
+	dev->driver->lastclose		= mga_driver_lastclose;
+	dev->driver->get_vblank_counter	= mga_get_vblank_counter;
+	dev->driver->enable_vblank	= mga_enable_vblank;
+	dev->driver->disable_vblank	= mga_disable_vblank;
+	dev->driver->irq_preinstall	= mga_driver_irq_preinstall;
+	dev->driver->irq_postinstall	= mga_driver_irq_postinstall;
+	dev->driver->irq_uninstall	= mga_driver_irq_uninstall;
+	dev->driver->irq_handler	= mga_driver_irq_handler;
+	dev->driver->dma_ioctl		= mga_dma_buffers;
+	dev->driver->dma_quiescent	= mga_driver_dma_quiescent;
+	dev->driver->device_is_agp	= mga_driver_device_is_agp;
+
+	dev->driver->ioctls		= mga_ioctls;
+	dev->driver->max_ioctl		= mga_max_ioctl;
+
+	dev->driver->name		= DRIVER_NAME;
+	dev->driver->desc		= DRIVER_DESC;
+	dev->driver->date		= DRIVER_DATE;
+	dev->driver->major		= DRIVER_MAJOR;
+	dev->driver->minor		= DRIVER_MINOR;
+	dev->driver->patchlevel		= DRIVER_PATCHLEVEL;
 }
 
-
-
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 static int
-mga_probe(device_t dev)
+mga_probe(device_t kdev)
 {
-	return drm_probe(dev, mga_pciidlist);
+	return drm_probe(kdev, mga_pciidlist);
 }
 
 static int
-mga_attach(device_t nbdev)
+mga_attach(device_t kdev)
 {
-	drm_device_t *dev = device_get_softc(nbdev);
+	struct drm_device *dev = device_get_softc(kdev);
+
+	dev->driver = malloc(sizeof(struct drm_driver_info), DRM_MEM_DRIVER,
+	    M_WAITOK | M_ZERO);
 
-	bzero(dev, sizeof(drm_device_t));
 	mga_configure(dev);
-	return drm_attach(nbdev, mga_pciidlist);
+
+	return drm_attach(kdev, mga_pciidlist);
+}
+
+static int
+mga_detach(device_t kdev)
+{
+	struct drm_device *dev = device_get_softc(kdev);
+	int ret;
+
+	ret = drm_detach(kdev);
+
+	free(dev->driver, DRM_MEM_DRIVER);
+
+	return ret;
 }
 
 static device_method_t mga_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		mga_probe),
 	DEVMETHOD(device_attach,	mga_attach),
-	DEVMETHOD(device_detach,	drm_detach),
+	DEVMETHOD(device_detach,	mga_detach),
 
 	{ 0, 0 }
 };
@@ -149,7 +160,7 @@ static device_method_t mga_methods[] = {
 static driver_t mga_driver = {
 	"drm",
 	mga_methods,
-	sizeof(drm_device_t)
+	sizeof(struct drm_device)
 };
 
 extern devclass_t drm_devclass;
@@ -159,12 +170,3 @@ DRIVER_MODULE(mga, vgapci, mga_driver, drm_devclass, 0, 0);
 DRIVER_MODULE(mga, pci, mga_driver, drm_devclass, 0, 0);
 #endif
 MODULE_DEPEND(mga, drm, 1, 1, 1);
-
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-#ifdef _LKM
-CFDRIVER_DECL(mga, DV_TTY, NULL);
-#else
-CFATTACH_DECL(mga, sizeof(drm_device_t), drm_probe, drm_attach, drm_detach,
-    drm_activate);
-#endif
-#endif
diff --git a/sys/dev/drm/mga_drv.h b/sys/dev/drm/mga_drv.h
index 47127afc37..bf3be80829 100644
--- a/sys/dev/drm/mga_drv.h
+++ b/sys/dev/drm/mga_drv.h
@@ -26,8 +26,6 @@
  *
  * Authors:
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/mga_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __MGA_DRV_H__
@@ -115,13 +113,14 @@ typedef struct drm_mga_private {
 	 * \sa drm_mga_private_t::mmio
 	 */
 	/*@{*/
-	u32 mmio_base;             /**< Bus address of base of MMIO. */
-	u32 mmio_size;             /**< Size of the MMIO region. */
+	u32 mmio_base;			/**< Bus address of base of MMIO. */
+	u32 mmio_size;			/**< Size of the MMIO region. */
 	/*@}*/
 
 	u32 clear_cmd;
 	u32 maccess;
 
+	atomic_t vbl_received;		/**< Number of vblanks received. */
 	wait_queue_head_t fence_queue;
 	atomic_t last_fence_retired;
 	u32 next_fence_to_post;
@@ -183,11 +182,14 @@ extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
 extern int mga_warp_init(drm_mga_private_t * dev_priv);
 
 				/* mga_irq.c */
+extern int mga_enable_vblank(struct drm_device *dev, int crtc);
+extern void mga_disable_vblank(struct drm_device *dev, int crtc);
+extern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc);
 extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence);
 extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
 extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
 extern void mga_driver_irq_preinstall(struct drm_device * dev);
-extern void mga_driver_irq_postinstall(struct drm_device * dev);
+extern int mga_driver_irq_postinstall(struct drm_device * dev);
 extern void mga_driver_irq_uninstall(struct drm_device * dev);
 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
 			     unsigned long arg);
diff --git a/sys/dev/drm/mga_irq.c b/sys/dev/drm/mga_irq.c
index 8197cd95af..3014d86468 100644
--- a/sys/dev/drm/mga_irq.c
+++ b/sys/dev/drm/mga_irq.c
@@ -1,6 +1,6 @@
 /* mga_irq.c -- IRQ handling for radeon -*- linux-c -*-
  */
-/*
+/*-
  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
  *
  * The Weather Channel (TM) funded Tungsten Graphics to develop the
@@ -29,14 +29,26 @@
  * Authors:
  *    Keith Whitwell <keith@tungstengraphics.com>
  *    Eric Anholt <anholt@FreeBSD.org>
- *
- * $DragonFly: src/sys/dev/drm/mga_irq.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/mga_drm.h"
+#include "dev/drm/mga_drv.h"
+
+u32 mga_get_vblank_counter(struct drm_device *dev, int crtc)
+{
+	const drm_mga_private_t *const dev_priv = 
+		(drm_mga_private_t *) dev->dev_private;
+
+	if (crtc != 0) {
+		return 0;
+	}
+
+
+	return atomic_read(&dev_priv->vbl_received);
+}
+
 
 irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
 {
@@ -50,9 +62,8 @@ irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
 	/* VBLANK interrupt */
 	if (status & MGA_VLINEPEN) {
 		MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR);
-		atomic_inc(&dev->vbl_received);
-		DRM_WAKEUP(&dev->vbl_queue);
-		drm_vbl_send_signals(dev);
+		atomic_inc(&dev_priv->vbl_received);
+		drm_handle_vblank(dev, 0);
 		handled = 1;
 	}
 
@@ -81,22 +92,34 @@ irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS)
 	return IRQ_NONE;
 }
 
-int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
+int mga_enable_vblank(struct drm_device *dev, int crtc)
 {
-	unsigned int cur_vblank;
-	int ret = 0;
+	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
 
-	/* Assume that the user has missed the current sequence number
-	 * by about a day rather than she wants to wait for years
-	 * using vertical blanks...
-	 */
-	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
-		    (((cur_vblank = atomic_read(&dev->vbl_received))
-		      - *sequence) <= (1 << 23)));
+	if (crtc != 0) {
+		DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
+			  crtc);
+		return 0;
+	}
 
-	*sequence = cur_vblank;
+	MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
+	return 0;
+}
 
-	return ret;
+
+void mga_disable_vblank(struct drm_device *dev, int crtc)
+{
+	if (crtc != 0) {
+		DRM_ERROR("tried to disable vblank on non-existent crtc %d\n",
+			  crtc);
+	}
+
+	/* Do *NOT* disable the vertical refresh interrupt.  MGA doesn't have
+	 * a nice hardware counter that tracks the number of refreshes when
+	 * the interrupt is disabled, and the kernel doesn't know the refresh
+	 * rate to calculate an estimate.
+	 */
+	/* MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); */
 }
 
 int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence)
@@ -113,6 +136,9 @@ int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence)
 		    (((cur_fence = atomic_read(&dev_priv->last_fence_retired))
 		      - *sequence) <= (1 << 23)));
 
+	if (ret == -ERESTART)
+		DRM_DEBUG("restarting syscall\n");
+
 	*sequence = cur_fence;
 
 	return ret;
@@ -128,14 +154,17 @@ void mga_driver_irq_preinstall(struct drm_device * dev)
 	MGA_WRITE(MGA_ICLEAR, ~0);
 }
 
-void mga_driver_irq_postinstall(struct drm_device * dev)
+int mga_driver_irq_postinstall(struct drm_device * dev)
 {
 	drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
 
 	DRM_INIT_WAITQUEUE(&dev_priv->fence_queue);
 
-	/* Turn on vertical blank interrupt and soft trap interrupt. */
-	MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
+	/* Turn on soft trap interrupt.  Vertical blank interrupts are enabled
+	 * in mga_enable_vblank.
+	 */
+	MGA_WRITE(MGA_IEN, MGA_SOFTRAPEN);
+	return 0;
 }
 
 void mga_driver_irq_uninstall(struct drm_device * dev)
diff --git a/sys/dev/drm/mga_state.c b/sys/dev/drm/mga_state.c
index 35508c57ae..9d9857178a 100644
--- a/sys/dev/drm/mga_state.c
+++ b/sys/dev/drm/mga_state.c
@@ -1,7 +1,7 @@
 /* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
  * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
  */
-/*
+/*-
  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
@@ -31,14 +31,12 @@
  *
  * Rewritten by:
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/mga_state.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/mga_drm.h"
+#include "dev/drm/mga_drv.h"
 
 /* ================================================================
  * DMA hardware state programming functions
diff --git a/sys/dev/drm/mga_ucode.h b/sys/dev/drm/mga_ucode.h
index e4694e5349..b611e27470 100644
--- a/sys/dev/drm/mga_ucode.h
+++ b/sys/dev/drm/mga_ucode.h
@@ -24,8 +24,6 @@
  *
  * Kernel-based WARP engine management:
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/mga_ucode.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 /*
diff --git a/sys/dev/drm/mga_warp.c b/sys/dev/drm/mga_warp.c
index 42332be2cf..f7bb011a18 100644
--- a/sys/dev/drm/mga_warp.c
+++ b/sys/dev/drm/mga_warp.c
@@ -1,7 +1,7 @@
 /* mga_warp.c -- Matrox G200/G400 WARP engine management -*- linux-c -*-
  * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com
  */
-/*
+/*-
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
  *
@@ -26,15 +26,13 @@
  *
  * Authors:
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/mga_warp.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
-#include "mga_ucode.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/mga_drm.h"
+#include "dev/drm/mga_drv.h"
+#include "dev/drm/mga_ucode.h"
 
 #define MGA_WARP_CODE_ALIGN		256	/* in bytes */
 
diff --git a/sys/dev/drm/r128_cce.c b/sys/dev/drm/r128_cce.c
index 73708e2f9c..c8a2b31f04 100644
--- a/sys/dev/drm/r128_cce.c
+++ b/sys/dev/drm/r128_cce.c
@@ -1,7 +1,7 @@
 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
  * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
  */
-/*
+/*-
  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
@@ -27,14 +27,12 @@
  *
  * Authors:
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/r128_cce.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
-#include "r128_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/r128_drm.h"
+#include "dev/drm/r128_drv.h"
 
 #define R128_FIFO_DEBUG		0
 
@@ -560,6 +558,7 @@ static int r128_do_init_cce(struct drm_device * dev, drm_r128_init_t * init)
 #if __OS_HAS_AGP
 	if (dev_priv->is_pci) {
 #endif
+		dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
 		dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
 		dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
 		dev_priv->gart_info.addr = NULL;
diff --git a/sys/dev/drm/r128_drm.h b/sys/dev/drm/r128_drm.h
index b2c1f6c030..32c6f1f1dc 100644
--- a/sys/dev/drm/r128_drm.h
+++ b/sys/dev/drm/r128_drm.h
@@ -1,7 +1,7 @@
 /* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
  * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
  */
-/*
+/*-
  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All rights reserved.
@@ -28,8 +28,6 @@
  * Authors:
  *    Gareth Hughes <gareth@valinux.com>
  *    Kevin E. Martin <martin@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/r128_drm.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __R128_DRM_H__
diff --git a/sys/dev/drm/r128_drv.c b/sys/dev/drm/r128_drv.c
index 962be16d34..4d719dce7b 100644
--- a/sys/dev/drm/r128_drv.c
+++ b/sys/dev/drm/r128_drv.c
@@ -29,73 +29,91 @@
  *    Rickard E. (Rik) Faith <faith@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/r128_drv.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
-#include "r128_drv.h"
-#include "drm_pciids.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/r128_drm.h"
+#include "dev/drm/r128_drv.h"
+#include "dev/drm/drm_pciids.h"
 
 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
 static drm_pci_id_list_t r128_pciidlist[] = {
 	r128_PCI_IDS
 };
 
-static void r128_configure(drm_device_t *dev)
+static void r128_configure(struct drm_device *dev)
 {
-	dev->driver.buf_priv_size	= sizeof(drm_r128_buf_priv_t);
-	dev->driver.preclose		= r128_driver_preclose;
-	dev->driver.lastclose		= r128_driver_lastclose;
-	dev->driver.vblank_wait		= r128_driver_vblank_wait;
-	dev->driver.irq_preinstall	= r128_driver_irq_preinstall;
-	dev->driver.irq_postinstall	= r128_driver_irq_postinstall;
-	dev->driver.irq_uninstall	= r128_driver_irq_uninstall;
-	dev->driver.irq_handler		= r128_driver_irq_handler;
-	dev->driver.dma_ioctl		= r128_cce_buffers;
-
-	dev->driver.ioctls		= r128_ioctls;
-	dev->driver.max_ioctl		= r128_max_ioctl;
-
-	dev->driver.name		= DRIVER_NAME;
-	dev->driver.desc		= DRIVER_DESC;
-	dev->driver.date		= DRIVER_DATE;
-	dev->driver.major		= DRIVER_MAJOR;
-	dev->driver.minor		= DRIVER_MINOR;
-	dev->driver.patchlevel		= DRIVER_PATCHLEVEL;
-
-	dev->driver.use_agp		= 1;
-	dev->driver.use_mtrr		= 1;
-	dev->driver.use_pci_dma		= 1;
-	dev->driver.use_sg		= 1;
-	dev->driver.use_dma		= 1;
-	dev->driver.use_irq		= 1;
-	dev->driver.use_vbl_irq		= 1;
+	dev->driver->driver_features =
+	    DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA |
+	    DRIVER_SG | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ;
+
+	dev->driver->buf_priv_size	= sizeof(drm_r128_buf_priv_t);
+	dev->driver->load		= r128_driver_load;
+	dev->driver->preclose		= r128_driver_preclose;
+	dev->driver->lastclose		= r128_driver_lastclose;
+	dev->driver->get_vblank_counter	= r128_get_vblank_counter;
+	dev->driver->enable_vblank	= r128_enable_vblank;
+	dev->driver->disable_vblank	= r128_disable_vblank;
+	dev->driver->irq_preinstall	= r128_driver_irq_preinstall;
+	dev->driver->irq_postinstall	= r128_driver_irq_postinstall;
+	dev->driver->irq_uninstall	= r128_driver_irq_uninstall;
+	dev->driver->irq_handler	= r128_driver_irq_handler;
+	dev->driver->dma_ioctl		= r128_cce_buffers;
+
+	dev->driver->ioctls		= r128_ioctls;
+	dev->driver->max_ioctl		= r128_max_ioctl;
+
+	dev->driver->name		= DRIVER_NAME;
+	dev->driver->desc		= DRIVER_DESC;
+	dev->driver->date		= DRIVER_DATE;
+	dev->driver->major		= DRIVER_MAJOR;
+	dev->driver->minor		= DRIVER_MINOR;
+	dev->driver->patchlevel		= DRIVER_PATCHLEVEL;
 }
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 static int
-r128_probe(device_t dev)
+r128_probe(device_t kdev)
 {
-	return drm_probe(dev, r128_pciidlist);
+	return drm_probe(kdev, r128_pciidlist);
 }
 
 static int
-r128_attach(device_t nbdev)
+r128_attach(device_t kdev)
 {
-	drm_device_t *dev = device_get_softc(nbdev);
+	struct drm_device *dev = device_get_softc(kdev);
+
+	dev->driver = malloc(sizeof(struct drm_driver_info), DRM_MEM_DRIVER,
+	    M_WAITOK | M_ZERO);
 
-	bzero(dev, sizeof(drm_device_t));
 	r128_configure(dev);
-	return drm_attach(nbdev, r128_pciidlist);
+
+	return drm_attach(kdev, r128_pciidlist);
+}
+
+int r128_driver_load(struct drm_device * dev, unsigned long flags)
+{
+	return drm_vblank_init(dev, 1);
+}
+
+static int
+r128_detach(device_t kdev)
+{
+	struct drm_device *dev = device_get_softc(kdev);
+	int ret;
+
+	ret = drm_detach(kdev);
+
+	free(dev->driver, DRM_MEM_DRIVER);
+
+	return ret;
 }
 
 static device_method_t r128_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		r128_probe),
 	DEVMETHOD(device_attach,	r128_attach),
-	DEVMETHOD(device_detach,	drm_detach),
+	DEVMETHOD(device_detach,	r128_detach),
 
 	{ 0, 0 }
 };
@@ -103,7 +121,7 @@ static device_method_t r128_methods[] = {
 static driver_t r128_driver = {
 	"drm",
 	r128_methods,
-	sizeof(drm_device_t)
+	sizeof(struct drm_device)
 };
 
 extern devclass_t drm_devclass;
@@ -113,12 +131,3 @@ DRIVER_MODULE(r128, vgapci, r128_driver, drm_devclass, 0, 0);
 DRIVER_MODULE(r128, pci, r128_driver, drm_devclass, 0, 0);
 #endif
 MODULE_DEPEND(r128, drm, 1, 1, 1);
-
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-#ifdef _LKM
-CFDRIVER_DECL(r128, DV_TTY, NULL);
-#else
-CFATTACH_DECL(r128, sizeof(drm_device_t), drm_probe, drm_attach, drm_detach,
-    drm_activate);
-#endif
-#endif
diff --git a/sys/dev/drm/r128_drv.h b/sys/dev/drm/r128_drv.h
index 5a19c1ae34..e1fef3acc8 100644
--- a/sys/dev/drm/r128_drv.h
+++ b/sys/dev/drm/r128_drv.h
@@ -1,7 +1,7 @@
 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
  * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
  */
-/*
+/*-
  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All rights reserved.
@@ -30,8 +30,6 @@
  *    Kevin E. Martin <martin@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *    Michel D�zer <daenzerm@student.ethz.ch>
- *
- * $DragonFly: src/sys/dev/drm/r128_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __R128_DRV_H__
@@ -99,6 +97,8 @@ typedef struct drm_r128_private {
 	u32 crtc_offset;
 	u32 crtc_offset_cntl;
 
+	atomic_t vbl_received;
+
 	u32 color_fmt;
 	unsigned int front_offset;
 	unsigned int front_pitch;
@@ -151,13 +151,15 @@ extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n);
 extern int r128_do_cce_idle(drm_r128_private_t * dev_priv);
 extern int r128_do_cleanup_cce(struct drm_device * dev);
 
-extern int r128_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
-
+extern int r128_enable_vblank(struct drm_device *dev, int crtc);
+extern void r128_disable_vblank(struct drm_device *dev, int crtc);
+extern u32 r128_get_vblank_counter(struct drm_device *dev, int crtc);
 extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS);
 extern void r128_driver_irq_preinstall(struct drm_device * dev);
-extern void r128_driver_irq_postinstall(struct drm_device * dev);
+extern int r128_driver_irq_postinstall(struct drm_device * dev);
 extern void r128_driver_irq_uninstall(struct drm_device * dev);
 extern void r128_driver_lastclose(struct drm_device * dev);
+extern int r128_driver_load(struct drm_device * dev, unsigned long flags);
 extern void r128_driver_preclose(struct drm_device * dev,
 				 struct drm_file *file_priv);
 
diff --git a/sys/dev/drm/r128_irq.c b/sys/dev/drm/r128_irq.c
index 853b1133d8..a4fd946644 100644
--- a/sys/dev/drm/r128_irq.c
+++ b/sys/dev/drm/r128_irq.c
@@ -1,5 +1,5 @@
 /* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- */
-/*
+/*-
  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
  *
  * The Weather Channel (TM) funded Tungsten Graphics to develop the
@@ -28,14 +28,22 @@
  * Authors:
  *    Keith Whitwell <keith@tungstengraphics.com>
  *    Eric Anholt <anholt@FreeBSD.org>
- *
- * $DragonFly: src/sys/dev/drm/r128_irq.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
-#include "r128_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/r128_drm.h"
+#include "dev/drm/r128_drv.h"
+
+u32 r128_get_vblank_counter(struct drm_device *dev, int crtc)
+{
+	const drm_r128_private_t *dev_priv = dev->dev_private;
+
+	if (crtc != 0)
+		return 0;
+
+	return atomic_read(&dev_priv->vbl_received);
+}
 
 irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS)
 {
@@ -48,30 +56,38 @@ irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS)
 	/* VBLANK interrupt */
 	if (status & R128_CRTC_VBLANK_INT) {
 		R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
-		atomic_inc(&dev->vbl_received);
-		DRM_WAKEUP(&dev->vbl_queue);
-		drm_vbl_send_signals(dev);
+		atomic_inc(&dev_priv->vbl_received);
+		drm_handle_vblank(dev, 0);
 		return IRQ_HANDLED;
 	}
 	return IRQ_NONE;
 }
 
-int r128_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence)
+int r128_enable_vblank(struct drm_device *dev, int crtc)
 {
-	unsigned int cur_vblank;
-	int ret = 0;
+	drm_r128_private_t *dev_priv = dev->dev_private;
 
-	/* Assume that the user has missed the current sequence number
-	 * by about a day rather than she wants to wait for years
-	 * using vertical blanks...
-	 */
-	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
-		    (((cur_vblank = atomic_read(&dev->vbl_received))
-		      - *sequence) <= (1 << 23)));
+	if (crtc != 0) {
+		DRM_ERROR("%s:  bad crtc %d\n", __FUNCTION__, crtc);
+		return -EINVAL;
+	}
 
-	*sequence = cur_vblank;
+	R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN);
+	return 0;
+}
+
+void r128_disable_vblank(struct drm_device *dev, int crtc)
+{
+	if (crtc != 0)
+		DRM_ERROR("%s:  bad crtc %d\n", __FUNCTION__, crtc);
 
-	return ret;
+	/*
+	 * FIXME: implement proper interrupt disable by using the vblank
+	 * counter register (if available)
+	 *
+	 * R128_WRITE(R128_GEN_INT_CNTL,
+	 *            R128_READ(R128_GEN_INT_CNTL) & ~R128_CRTC_VBLANK_INT_EN);
+	 */
 }
 
 void r128_driver_irq_preinstall(struct drm_device * dev)
@@ -84,12 +100,9 @@ void r128_driver_irq_preinstall(struct drm_device * dev)
 	R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK);
 }
 
-void r128_driver_irq_postinstall(struct drm_device * dev)
+int r128_driver_irq_postinstall(struct drm_device * dev)
 {
-	drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private;
-
-	/* Turn on VBL interrupt */
-	R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN);
+	return 0;
 }
 
 void r128_driver_irq_uninstall(struct drm_device * dev)
diff --git a/sys/dev/drm/r128_state.c b/sys/dev/drm/r128_state.c
index a8bbf8845a..0eee4aa309 100644
--- a/sys/dev/drm/r128_state.c
+++ b/sys/dev/drm/r128_state.c
@@ -1,7 +1,7 @@
 /* r128_state.c -- State support for r128 -*- linux-c -*-
  * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
  */
-/*
+/*-
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
  *
@@ -26,14 +26,12 @@
  *
  * Authors:
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/r128_state.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
-#include "r128_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/r128_drm.h"
+#include "dev/drm/r128_drv.h"
 
 /* ================================================================
  * CCE hardware state programming functions
diff --git a/sys/dev/drm/r300_cmdbuf.c b/sys/dev/drm/r300_cmdbuf.c
index e97b84bac6..1efe1f7d61 100644
--- a/sys/dev/drm/r300_cmdbuf.c
+++ b/sys/dev/drm/r300_cmdbuf.c
@@ -29,15 +29,13 @@
  *
  * Authors:
  *    Nicolai Haehnle <prefect_@gmx.net>
- *
- * $DragonFly: src/sys/dev/drm/r300_cmdbuf.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
-#include "r300_reg.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/radeon_drm.h"
+#include "dev/drm/radeon_drv.h"
+#include "dev/drm/r300_reg.h"
 
 #define R300_SIMULTANEOUS_CLIPRECTS		4
 
@@ -79,6 +77,9 @@ static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
 				return -EFAULT;
 			}
 
+			box.x2--; /* Hardware expects inclusive bottom-right corner */
+			box.y2--;
+
 			if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 				box.x1 = (box.x1) &
 					R300_CLIPRECT_MASK;
@@ -97,8 +98,8 @@ static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
 					R300_CLIPRECT_MASK;
 				box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) &
 					R300_CLIPRECT_MASK;
-
 			}
+
 			OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
 				 (box.y1 << R300_CLIPRECT_Y_SHIFT));
 			OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
@@ -138,6 +139,18 @@ static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
 		ADVANCE_RING();
 	}
 
+	/* flus cache and wait idle clean after cliprect change */
+	BEGIN_RING(2);
+	OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+	OUT_RING(R300_RB3D_DC_FLUSH);
+	ADVANCE_RING();
+	BEGIN_RING(2);
+	OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
+	OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
+	ADVANCE_RING();
+	/* set flush flag */
+	dev_priv->track_flush |= RADEON_FLUSH_EMITED;
+
 	return 0;
 }
 
@@ -168,13 +181,13 @@ void r300_init_reg_flags(struct drm_device *dev)
 	ADD_RANGE(0x21DC, 1);
 	ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
 	ADD_RANGE(R300_VAP_CLIP_X_0, 4);
-	ADD_RANGE(R300_VAP_PVS_WAITIDLE, 1);
+	ADD_RANGE(R300_VAP_PVS_STATE_FLUSH_REG, 1);
 	ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
 	ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 	ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
 	ADD_RANGE(R300_GB_ENABLE, 1);
 	ADD_RANGE(R300_GB_MSPOS0, 5);
-	ADD_RANGE(R300_TX_CNTL, 1);
+	ADD_RANGE(R300_TX_INVALTAGS, 1);
 	ADD_RANGE(R300_TX_ENABLE, 1);
 	ADD_RANGE(0x4200, 4);
 	ADD_RANGE(0x4214, 1);
@@ -191,18 +204,12 @@ void r300_init_reg_flags(struct drm_device *dev)
 	ADD_RANGE(R300_RE_CULL_CNTL, 1);
 	ADD_RANGE(0x42C0, 2);
 	ADD_RANGE(R300_RS_CNTL_0, 2);
-	ADD_RANGE(R300_RS_INTERP_0, 8);
-	ADD_RANGE(R300_RS_ROUTE_0, 8);
-	ADD_RANGE(0x43A4, 2);
+
+	ADD_RANGE(R300_SC_HYPERZ, 2);
 	ADD_RANGE(0x43E8, 1);
-	ADD_RANGE(R300_PFS_CNTL_0, 3);
-	ADD_RANGE(R300_PFS_NODE_0, 4);
-	ADD_RANGE(R300_PFS_TEXI_0, 64);
+
 	ADD_RANGE(0x46A4, 5);
-	ADD_RANGE(R300_PFS_INSTR0_0, 64);
-	ADD_RANGE(R300_PFS_INSTR1_0, 64);
-	ADD_RANGE(R300_PFS_INSTR2_0, 64);
-	ADD_RANGE(R300_PFS_INSTR3_0, 64);
+
 	ADD_RANGE(R300_RE_FOG_STATE, 1);
 	ADD_RANGE(R300_FOG_COLOR_R, 3);
 	ADD_RANGE(R300_PP_ALPHA_TEST, 2);
@@ -217,14 +224,12 @@ void r300_init_reg_flags(struct drm_device *dev)
 	ADD_RANGE(0x4E50, 9);
 	ADD_RANGE(0x4E88, 1);
 	ADD_RANGE(0x4EA0, 2);
-	ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
-	ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
-	ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);	/* check offset */
-	ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
-	ADD_RANGE(0x4F28, 1);
-	ADD_RANGE(0x4F30, 2);
-	ADD_RANGE(0x4F44, 1);
-	ADD_RANGE(0x4F54, 1);
+	ADD_RANGE(R300_ZB_CNTL, 3);
+	ADD_RANGE(R300_ZB_FORMAT, 4);
+	ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);	/* check offset */
+	ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
+	ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
+	ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
 
 	ADD_RANGE(R300_TX_FILTER_0, 16);
 	ADD_RANGE(R300_TX_FILTER1_0, 16);
@@ -237,13 +242,32 @@ void r300_init_reg_flags(struct drm_device *dev)
 	ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
 
 	/* Sporadic registers used as primitives are emitted */
-	ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
+	ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
 	ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
 	ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
 	ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
 
 	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
-		ADD_RANGE(0x4074, 16);
+		ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
+		ADD_RANGE(R500_US_CONFIG, 2);
+		ADD_RANGE(R500_US_CODE_ADDR, 3);
+		ADD_RANGE(R500_US_FC_CTRL, 1);
+		ADD_RANGE(R500_RS_IP_0, 16);
+		ADD_RANGE(R500_RS_INST_0, 16);
+		ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
+		ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
+		ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
+	} else {
+		ADD_RANGE(R300_PFS_CNTL_0, 3);
+		ADD_RANGE(R300_PFS_NODE_0, 4);
+		ADD_RANGE(R300_PFS_TEXI_0, 64);
+		ADD_RANGE(R300_PFS_INSTR0_0, 64);
+		ADD_RANGE(R300_PFS_INSTR1_0, 64);
+		ADD_RANGE(R300_PFS_INSTR2_0, 64);
+		ADD_RANGE(R300_PFS_INSTR3_0, 64);
+		ADD_RANGE(R300_RS_INTERP_0, 8);
+		ADD_RANGE(R300_RS_ROUTE_0, 8);
+
 	}
 }
 
@@ -328,6 +352,7 @@ static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
 	sz = header.packet0.count;
 	reg = (header.packet0.reghi << 8) | header.packet0.reglo;
 
+	DRM_DEBUG("R300_CMD_PACKET0: reg %04x, sz %d\n", reg, sz);
 	if (!sz)
 		return 0;
 
@@ -379,15 +404,28 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
 	if (sz * 16 > cmdbuf->bufsz)
 		return -EINVAL;
 
-	BEGIN_RING(5 + sz * 4);
-	/* Wait for VAP to come to senses.. */
-	/* there is no need to emit it multiple times, (only once before VAP is programmed,
-	   but this optimization is for later */
-	OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0);
+	/* VAP is very sensitive so we purge cache before we program it
+	 * and we also flush its state before & after */
+	BEGIN_RING(6);
+	OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+	OUT_RING(R300_RB3D_DC_FLUSH);
+	OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
+	OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
+	OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
+	OUT_RING(0);
+	ADVANCE_RING();
+	/* set flush flag */
+	dev_priv->track_flush |= RADEON_FLUSH_EMITED;
+
+	BEGIN_RING(3 + sz * 4);
 	OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
 	OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
 	OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
+	ADVANCE_RING();
 
+	BEGIN_RING(2);
+	OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
+	OUT_RING(0);
 	ADVANCE_RING();
 
 	cmdbuf->buf += sz * 16;
@@ -415,6 +453,15 @@ static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
 	OUT_RING_TABLE((int *)cmdbuf->buf, 8);
 	ADVANCE_RING();
 
+	BEGIN_RING(4);
+	OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+	OUT_RING(R300_RB3D_DC_FLUSH);
+	OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
+	OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
+	ADVANCE_RING();
+	/* set flush flag */
+	dev_priv->track_flush |= RADEON_FLUSH_EMITED;
+
 	cmdbuf->buf += 8 * 4;
 	cmdbuf->bufsz -= 8 * 4;
 
@@ -534,22 +581,23 @@ static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
 	return 0;
 }
 
-static __inline__ int r300_emit_indx_buffer(drm_radeon_private_t *dev_priv,
-					     drm_radeon_kcmd_buffer_t *cmdbuf)
+static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv,
+					    drm_radeon_kcmd_buffer_t *cmdbuf)
 {
-	u32 *cmd = (u32 *) cmdbuf->buf;
-	int count, ret;
+	u32 *cmd;
+	int count;
+	int expected_count;
 	RING_LOCALS;
 
-	count=(cmd[0]>>16) & 0x3fff;
+	cmd = (u32 *) cmdbuf->buf;
+	count = (cmd[0]>>16) & 0x3fff;
+	expected_count = cmd[1] >> 16;
+	if (!(cmd[1] & R300_VAP_VF_CNTL__INDEX_SIZE_32bit))
+		expected_count = (expected_count+1)/2;
 
-	if ((cmd[1] & 0x8000ffff) != 0x80000810) {
-		DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
-		return -EINVAL;
-	}
-	ret = !radeon_check_offset(dev_priv, cmd[2]);
-	if (ret) {
-		DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
+	if (count && count != expected_count) {
+		DRM_ERROR("3D_DRAW_INDX_2: packet size %i, expected %i\n",
+			count, expected_count);
 		return -EINVAL;
 	}
 
@@ -561,6 +609,50 @@ static __inline__ int r300_emit_indx_buffer(drm_radeon_private_t *dev_priv,
 	cmdbuf->buf += (count+2)*4;
 	cmdbuf->bufsz -= (count+2)*4;
 
+	if (!count) {
+		drm_r300_cmd_header_t header;
+
+		if (cmdbuf->bufsz < 4*4 + sizeof(header)) {
+			DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER, but stream is too short.\n");
+			return -EINVAL;
+		}
+
+		header.u = *(unsigned int *)cmdbuf->buf;
+
+		cmdbuf->buf += sizeof(header);
+		cmdbuf->bufsz -= sizeof(header);
+		cmd = (u32 *) cmdbuf->buf;
+
+		if (header.header.cmd_type != R300_CMD_PACKET3 ||
+		    header.packet3.packet != R300_CMD_PACKET3_RAW ||
+		    cmd[0] != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) {
+			DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER.\n");
+			return -EINVAL;
+		}
+
+		if ((cmd[1] & 0x8000ffff) != 0x80000810) {
+			DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
+			return -EINVAL;
+		}
+		if (!radeon_check_offset(dev_priv, cmd[2])) {
+			DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
+			return -EINVAL;
+		}
+		if (cmd[3] != expected_count) {
+			DRM_ERROR("INDX_BUFFER: buffer size %i, expected %i\n",
+				cmd[3], expected_count);
+			return -EINVAL;
+		}
+
+		BEGIN_RING(4);
+		OUT_RING(cmd[0]);
+		OUT_RING_TABLE((int *)(cmdbuf->buf + 4), 3);
+		ADVANCE_RING();
+
+		cmdbuf->buf += 4*4;
+		cmdbuf->bufsz -= 4*4;
+	}
+
 	return 0;
 }
 
@@ -604,11 +696,22 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
 	case RADEON_CNTL_BITBLT_MULTI:
 		return r300_emit_bitblt_multi(dev_priv, cmdbuf);
 
-	case RADEON_CP_INDX_BUFFER:	/* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
-		return r300_emit_indx_buffer(dev_priv, cmdbuf);
-	case RADEON_CP_3D_DRAW_IMMD_2:	/* triggers drawing using in-packet vertex data */
-	case RADEON_CP_3D_DRAW_VBUF_2:	/* triggers drawing of vertex buffers setup elsewhere */
-	case RADEON_CP_3D_DRAW_INDX_2:	/* triggers drawing using indices to vertex buffer */
+	case RADEON_CP_INDX_BUFFER:
+		DRM_ERROR("packet3 INDX_BUFFER without preceding 3D_DRAW_INDX_2 is illegal.\n");
+		return -EINVAL;
+	case RADEON_CP_3D_DRAW_IMMD_2:
+		/* triggers drawing using in-packet vertex data */
+	case RADEON_CP_3D_DRAW_VBUF_2:
+		/* triggers drawing of vertex buffers setup elsewhere */
+		dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
+					   RADEON_PURGE_EMITED);
+		break;
+	case RADEON_CP_3D_DRAW_INDX_2:
+		/* triggers drawing using indices to vertex buffer */
+		/* whenever we send vertex we clear flush & purge */
+		dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
+					   RADEON_PURGE_EMITED);
+		return r300_emit_draw_indx_2(dev_priv, cmdbuf);
 	case RADEON_WAIT_FOR_IDLE:
 	case RADEON_CP_NOP:
 		/* these packets are safe */
@@ -704,16 +807,53 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
  */
 static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
 {
+	uint32_t cache_z, cache_3d, cache_2d;
 	RING_LOCALS;
 
-	BEGIN_RING(6);
+	cache_z = R300_ZC_FLUSH;
+	cache_2d = R300_RB2D_DC_FLUSH;
+	cache_3d = R300_RB3D_DC_FLUSH;
+	if (!(dev_priv->track_flush & RADEON_PURGE_EMITED)) {
+		/* we can purge, primitive where draw since last purge */
+		cache_z |= R300_ZC_FREE;
+		cache_2d |= R300_RB2D_DC_FREE;
+		cache_3d |= R300_RB3D_DC_FREE;
+	}
+
+	/* flush & purge zbuffer */
+	BEGIN_RING(2);
+	OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
+	OUT_RING(cache_z);
+	ADVANCE_RING();
+	/* flush & purge 3d */
+	BEGIN_RING(2);
 	OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
-	OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
-	OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
-	OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
-	OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
-	OUT_RING(0x0);
+	OUT_RING(cache_3d);
 	ADVANCE_RING();
+	/* flush & purge texture */
+	BEGIN_RING(2);
+	OUT_RING(CP_PACKET0(R300_TX_INVALTAGS, 0));
+	OUT_RING(0);
+	ADVANCE_RING();
+	/* FIXME: is this one really needed ? */
+	BEGIN_RING(2);
+	OUT_RING(CP_PACKET0(R300_RB3D_AARESOLVE_CTL, 0));
+	OUT_RING(0);
+	ADVANCE_RING();
+	BEGIN_RING(2);
+	OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
+	OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
+	ADVANCE_RING();
+	/* flush & purge 2d through E2 as RB2D will trigger lockup */
+	BEGIN_RING(4);
+	OUT_RING(CP_PACKET0(R300_DSTCACHE_CTLSTAT, 0));
+	OUT_RING(cache_2d);
+	OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
+	OUT_RING(RADEON_WAIT_2D_IDLECLEAN |
+		 RADEON_WAIT_HOST_IDLECLEAN);
+	ADVANCE_RING();
+	/* set flush & purge flags */
+	dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 }
 
 /**
@@ -731,6 +871,47 @@ static void r300_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
 	buf->used = 0;
 }
 
+static void r300_cmd_wait(drm_radeon_private_t * dev_priv,
+			  drm_r300_cmd_header_t header)
+{
+	u32 wait_until;
+	RING_LOCALS;
+
+	if (!header.wait.flags)
+		return;
+
+	wait_until = 0;
+
+	switch(header.wait.flags) {
+	case R300_WAIT_2D:
+		wait_until = RADEON_WAIT_2D_IDLE;
+		break;
+	case R300_WAIT_3D:
+		wait_until = RADEON_WAIT_3D_IDLE;
+		break;
+	case R300_NEW_WAIT_2D_3D:
+		wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_3D_IDLE;
+		break;
+	case R300_NEW_WAIT_2D_2D_CLEAN:
+		wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
+		break;
+	case R300_NEW_WAIT_3D_3D_CLEAN:
+		wait_until = RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
+		break;
+	case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
+		wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
+		wait_until |= RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
+		break;
+	default:
+		return;
+	}
+
+	BEGIN_RING(2);
+	OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
+	OUT_RING(wait_until);
+	ADVANCE_RING();
+}
+
 static int r300_scratch(drm_radeon_private_t *dev_priv,
 			drm_radeon_kcmd_buffer_t *cmdbuf,
 			drm_r300_cmd_header_t header)
@@ -788,6 +969,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv,
 	return 0;
 }
 
+/**
+ * Uploads user-supplied vertex program instructions or parameters onto
+ * the graphics card.
+ * Called by r300_do_cp_cmdbuf.
+ */
+static __inline__ int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
+				       drm_radeon_kcmd_buffer_t *cmdbuf,
+				       drm_r300_cmd_header_t header)
+{
+	int sz;
+	int addr;
+	int type;
+	int clamp;
+	int stride;
+	RING_LOCALS;
+
+	sz = header.r500fp.count;
+	/* address is 9 bits 0 - 8, bit 1 of flags is part of address */
+	addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
+
+	type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
+	clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
+
+	addr |= (type << 16);
+	addr |= (clamp << 17);
+
+	stride = type ? 4 : 6;
+
+	DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
+	if (!sz)
+		return 0;
+	if (sz * stride * 4 > cmdbuf->bufsz)
+		return -EINVAL;
+
+	BEGIN_RING(3 + sz * stride);
+	OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
+	OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
+	OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
+
+	ADVANCE_RING();
+
+	cmdbuf->buf += sz * stride * 4;
+	cmdbuf->bufsz -= sz * stride * 4;
+
+	return 0;
+}
+
+
 /**
  * Parses and validates a user-supplied command buffer and emits appropriate
  * commands on the DMA ring buffer.
@@ -805,8 +1034,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 	DRM_DEBUG("\n");
 
-	/* See the comment above r300_emit_begin3d for why this call must be here,
-	 * and what the cleanup gotos are for. */
+	/* pacify */
 	r300_pacify(dev_priv);
 
 	if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
@@ -826,7 +1054,6 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 		switch (header.header.cmd_type) {
 		case R300_CMD_PACKET0:
-			DRM_DEBUG("R300_CMD_PACKET0\n");
 			ret = r300_emit_packet0(dev_priv, cmdbuf, header);
 			if (ret) {
 				DRM_ERROR("r300_emit_packet0 failed\n");
@@ -910,19 +1137,8 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
 			break;
 
 		case R300_CMD_WAIT:
-			/* simple enough, we can do it here */
 			DRM_DEBUG("R300_CMD_WAIT\n");
-			if (header.wait.flags == 0)
-				break;	/* nothing to do */
-
-			{
-				RING_LOCALS;
-
-				BEGIN_RING(2);
-				OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
-				OUT_RING((header.wait.flags & 0xf) << 14);
-				ADVANCE_RING();
-			}
+			r300_cmd_wait(dev_priv, header);
 			break;
 
 		case R300_CMD_SCRATCH:
@@ -934,6 +1150,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
 			}
 			break;
 
+		case R300_CMD_R500FP:
+			if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
+				DRM_ERROR("Calling r500 command on r300 card\n");
+				ret = -EINVAL;
+				goto cleanup;
+			}
+			DRM_DEBUG("R300_CMD_R500FP\n");
+			ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
+			if (ret) {
+				DRM_ERROR("r300_emit_r500fp failed\n");
+				goto cleanup;
+			}
+			break;
 		default:
 			DRM_ERROR("bad cmd_type %i at %p\n",
 				  header.header.cmd_type,
diff --git a/sys/dev/drm/r300_reg.h b/sys/dev/drm/r300_reg.h
index a9dc629661..d35dd39df7 100644
--- a/sys/dev/drm/r300_reg.h
+++ b/sys/dev/drm/r300_reg.h
@@ -1,5 +1,3 @@
-/* $DragonFly: src/sys/dev/drm/r300_reg.h,v 1.1 2008/04/05 18:12:29 hasso Exp $ */
-
 /**************************************************************************
 
 Copyright (C) 2004-2005 Nicolai Haehnle et al.
@@ -322,7 +320,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and
  * avoids bugs caused by still running shaders reading bad data from memory.
  */
-#define R300_VAP_PVS_WAITIDLE               0x2284 /* GUESS */
+#define R300_VAP_PVS_STATE_FLUSH_REG        0x2284
 
 /* Absolutely no clue what this register is about. */
 #define R300_VAP_UNKNOWN_2288               0x2288
@@ -518,7 +516,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* gap */
 
 /* Zero to flush caches. */
-#define R300_TX_CNTL                        0x4100
+#define R300_TX_INVALTAGS                   0x4100
 #define R300_TX_FLUSH                       0x0
 
 /* The upper enable bits are guessed, based on fglrx reported limits. */
@@ -707,6 +705,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #		define R300_RS_ROUTE_1_UNKNOWN11         (1 << 11)
 /* END: Rasterization / Interpolators - many guesses */
 
+/* Hierarchical Z Enable */
+#define R300_SC_HYPERZ                   0x43a4
+#	define R300_SC_HYPERZ_DISABLE     (0 << 0)
+#	define R300_SC_HYPERZ_ENABLE      (1 << 0)
+#	define R300_SC_HYPERZ_MIN         (0 << 1)
+#	define R300_SC_HYPERZ_MAX         (1 << 1)
+#	define R300_SC_HYPERZ_ADJ_256     (0 << 2)
+#	define R300_SC_HYPERZ_ADJ_128     (1 << 2)
+#	define R300_SC_HYPERZ_ADJ_64      (2 << 2)
+#	define R300_SC_HYPERZ_ADJ_32      (3 << 2)
+#	define R300_SC_HYPERZ_ADJ_16      (4 << 2)
+#	define R300_SC_HYPERZ_ADJ_8       (5 << 2)
+#	define R300_SC_HYPERZ_ADJ_4       (6 << 2)
+#	define R300_SC_HYPERZ_ADJ_2       (7 << 2)
+#	define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
+#	define R300_SC_HYPERZ_HZ_Z0MIN    (1 << 5)
+#	define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
+#	define R300_SC_HYPERZ_HZ_Z0MAX    (1 << 6)
+
+#define R300_SC_EDGERULE                 0x43a8
+
 /* BEGIN: Scissors and cliprects */
 
 /* There are four clipping rectangles. Their corner coordinates are inclusive.
@@ -1346,12 +1365,13 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R300_RB3D_COLORPITCH2               0x4E40 /* GUESS */
 #define R300_RB3D_COLORPITCH3               0x4E44 /* GUESS */
 
+#define R300_RB3D_AARESOLVE_CTL             0x4E88
 /* gap */
 
 /* Guess by Vladimir.
  * Set to 0A before 3D operations, set to 02 afterwards.
  */
-#define R300_RB3D_DSTCACHE_CTLSTAT          0x4E4C
+/*#define R300_RB3D_DSTCACHE_CTLSTAT          0x4E4C*/
 #       define R300_RB3D_DSTCACHE_UNKNOWN_02             0x00000002
 #       define R300_RB3D_DSTCACHE_UNKNOWN_0A             0x0000000A
 
@@ -1360,19 +1380,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  * for this.
  * Bit (1<<8) is the "test" bit. so plain write is 6  - vd
  */
-#define R300_RB3D_ZSTENCIL_CNTL_0                   0x4F00
-#       define R300_RB3D_Z_DISABLED_1            0x00000010
-#       define R300_RB3D_Z_DISABLED_2            0x00000014
-#       define R300_RB3D_Z_TEST                  0x00000012
-#       define R300_RB3D_Z_TEST_AND_WRITE        0x00000016
-#       define R300_RB3D_Z_WRITE_ONLY		 0x00000006
-
-#       define R300_RB3D_Z_TEST                  0x00000012
-#       define R300_RB3D_Z_TEST_AND_WRITE        0x00000016
-#       define R300_RB3D_Z_WRITE_ONLY		 0x00000006
-#	define R300_RB3D_STENCIL_ENABLE		 0x00000001
-
-#define R300_RB3D_ZSTENCIL_CNTL_1                   0x4F04
+#define R300_ZB_CNTL                             0x4F00
+#	define R300_STENCIL_ENABLE		 (1 << 0)
+#	define R300_Z_ENABLE		         (1 << 1)
+#	define R300_Z_WRITE_ENABLE		 (1 << 2)
+#	define R300_Z_SIGNED_COMPARE		 (1 << 3)
+#	define R300_STENCIL_FRONT_BACK		 (1 << 4)
+
+#define R300_ZB_ZSTENCILCNTL                   0x4f04
 	/* functions */
 #	define R300_ZS_NEVER			0
 #	define R300_ZS_LESS			1
@@ -1392,52 +1407,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #	define R300_ZS_INVERT			5
 #	define R300_ZS_INCR_WRAP		6
 #	define R300_ZS_DECR_WRAP		7
+#	define R300_Z_FUNC_SHIFT		0
 	/* front and back refer to operations done for front
 	   and back faces, i.e. separate stencil function support */
-#	define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT		0
-#	define R300_RB3D_ZS1_FRONT_FUNC_SHIFT		3
-#	define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT	6
-#	define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT	9
-#	define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT      12
-#	define R300_RB3D_ZS1_BACK_FUNC_SHIFT           15
-#	define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT        18
-#	define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT       21
-#	define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT       24
-
-#define R300_RB3D_ZSTENCIL_CNTL_2                   0x4F08
-#	define R300_RB3D_ZS2_STENCIL_REF_SHIFT		0
-#	define R300_RB3D_ZS2_STENCIL_MASK		0xFF
-#	define R300_RB3D_ZS2_STENCIL_MASK_SHIFT	        8
-#	define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT	16
+#	define R300_S_FRONT_FUNC_SHIFT	        3
+#	define R300_S_FRONT_SFAIL_OP_SHIFT	6
+#	define R300_S_FRONT_ZPASS_OP_SHIFT	9
+#	define R300_S_FRONT_ZFAIL_OP_SHIFT      12
+#	define R300_S_BACK_FUNC_SHIFT           15
+#	define R300_S_BACK_SFAIL_OP_SHIFT       18
+#	define R300_S_BACK_ZPASS_OP_SHIFT       21
+#	define R300_S_BACK_ZFAIL_OP_SHIFT       24
+
+#define R300_ZB_STENCILREFMASK                        0x4f08
+#	define R300_STENCILREF_SHIFT       0
+#	define R300_STENCILREF_MASK        0x000000ff
+#	define R300_STENCILMASK_SHIFT      8
+#	define R300_STENCILMASK_MASK       0x0000ff00
+#	define R300_STENCILWRITEMASK_SHIFT 16
+#	define R300_STENCILWRITEMASK_MASK  0x00ff0000
 
 /* gap */
 
-#define R300_RB3D_ZSTENCIL_FORMAT                   0x4F10
-#	define R300_DEPTH_FORMAT_16BIT_INT_Z     (0 << 0)
-#	define R300_DEPTH_FORMAT_24BIT_INT_Z     (2 << 0)
-	/* 16 bit format or some aditional bit ? */
-#	define R300_DEPTH_FORMAT_UNK32          (32 << 0)
+#define R300_ZB_FORMAT                             0x4f10
+#	define R300_DEPTHFORMAT_16BIT_INT_Z   (0 << 0)
+#	define R300_DEPTHFORMAT_16BIT_13E3    (1 << 0)
+#	define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL   (2 << 0)
+/* reserved up to (15 << 0) */
+#	define R300_INVERT_13E3_LEADING_ONES  (0 << 4)
+#	define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
 
-#define R300_RB3D_EARLY_Z                           0x4F14
-#	define R300_EARLY_Z_DISABLE              (0 << 0)
-#	define R300_EARLY_Z_ENABLE               (1 << 0)
+#define R300_ZB_ZTOP                             0x4F14
+#	define R300_ZTOP_DISABLE                 (0 << 0)
+#	define R300_ZTOP_ENABLE                  (1 << 0)
 
 /* gap */
 
-#define R300_RB3D_ZCACHE_CTLSTAT            0x4F18 /* GUESS */
-#       define R300_RB3D_ZCACHE_UNKNOWN_01  0x1
-#       define R300_RB3D_ZCACHE_UNKNOWN_03  0x3
+#define R300_ZB_ZCACHE_CTLSTAT            0x4f18
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT      (0 << 0)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT       (0 << 1)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE            (1 << 1)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE            (0 << 31)
+#       define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY            (1 << 31)
+
+#define R300_ZB_BW_CNTL                     0x4f1c
+#	define R300_HIZ_DISABLE                              (0 << 0)
+#	define R300_HIZ_ENABLE                               (1 << 0)
+#	define R300_HIZ_MIN                                  (0 << 1)
+#	define R300_HIZ_MAX                                  (1 << 1)
+#	define R300_FAST_FILL_DISABLE                        (0 << 2)
+#	define R300_FAST_FILL_ENABLE                         (1 << 2)
+#	define R300_RD_COMP_DISABLE                          (0 << 3)
+#	define R300_RD_COMP_ENABLE                           (1 << 3)
+#	define R300_WR_COMP_DISABLE                          (0 << 4)
+#	define R300_WR_COMP_ENABLE                           (1 << 4)
+#	define R300_ZB_CB_CLEAR_RMW                          (0 << 5)
+#	define R300_ZB_CB_CLEAR_CACHE_LINEAR                 (1 << 5)
+#	define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE   (0 << 6)
+#	define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE    (1 << 6)
+
+#	define R500_ZEQUAL_OPTIMIZE_ENABLE                   (0 << 7)
+#	define R500_ZEQUAL_OPTIMIZE_DISABLE                  (1 << 7)
+#	define R500_SEQUAL_OPTIMIZE_ENABLE                   (0 << 8)
+#	define R500_SEQUAL_OPTIMIZE_DISABLE                  (1 << 8)
+
+#	define R500_BMASK_ENABLE                             (0 << 10)
+#	define R500_BMASK_DISABLE                            (1 << 10)
+#	define R500_HIZ_EQUAL_REJECT_DISABLE                 (0 << 11)
+#	define R500_HIZ_EQUAL_REJECT_ENABLE                  (1 << 11)
+#	define R500_HIZ_FP_EXP_BITS_DISABLE                  (0 << 12)
+#	define R500_HIZ_FP_EXP_BITS_1                        (1 << 12)
+#	define R500_HIZ_FP_EXP_BITS_2                        (2 << 12)
+#	define R500_HIZ_FP_EXP_BITS_3                        (3 << 12)
+#	define R500_HIZ_FP_EXP_BITS_4                        (4 << 12)
+#	define R500_HIZ_FP_EXP_BITS_5                        (5 << 12)
+#	define R500_HIZ_FP_INVERT_LEADING_ONES               (0 << 15)
+#	define R500_HIZ_FP_INVERT_LEADING_ZEROS              (1 << 15)
+#	define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE      (0 << 16)
+#	define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE     (1 << 16)
+#	define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE           (0 << 17)
+#	define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE          (1 << 17)
+#	define R500_PEQ_PACKING_DISABLE                      (0 << 18)
+#	define R500_PEQ_PACKING_ENABLE                       (1 << 18)
+#	define R500_COVERED_PTR_MASKING_DISABLE              (0 << 18)
+#	define R500_COVERED_PTR_MASKING_ENABLE               (1 << 18)
+
 
 /* gap */
 
-#define R300_RB3D_DEPTHOFFSET               0x4F20
-#define R300_RB3D_DEPTHPITCH                0x4F24
-#       define R300_DEPTHPITCH_MASK              0x00001FF8 /* GUESS */
-#       define R300_DEPTH_TILE_ENABLE            (1 << 16) /* GUESS */
-#       define R300_DEPTH_MICROTILE_ENABLE       (1 << 17) /* GUESS */
-#       define R300_DEPTH_ENDIAN_NO_SWAP         (0 << 18) /* GUESS */
-#       define R300_DEPTH_ENDIAN_WORD_SWAP       (1 << 18) /* GUESS */
-#       define R300_DEPTH_ENDIAN_DWORD_SWAP      (2 << 18) /* GUESS */
+/* Z Buffer Address Offset.
+ * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
+ */
+#define R300_ZB_DEPTHOFFSET               0x4f20
+
+/* Z Buffer Pitch and Endian Control */
+#define R300_ZB_DEPTHPITCH                0x4f24
+#       define R300_DEPTHPITCH_MASK              0x00003FFC
+#       define R300_DEPTHMACROTILE_DISABLE      (0 << 16)
+#       define R300_DEPTHMACROTILE_ENABLE       (1 << 16)
+#       define R300_DEPTHMICROTILE_LINEAR       (0 << 17)
+#       define R300_DEPTHMICROTILE_TILED        (1 << 17)
+#       define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
+#       define R300_DEPTHENDIAN_NO_SWAP         (0 << 18)
+#       define R300_DEPTHENDIAN_WORD_SWAP       (1 << 18)
+#       define R300_DEPTHENDIAN_DWORD_SWAP      (2 << 18)
+#       define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
+
+/* Z Buffer Clear Value */
+#define R300_ZB_DEPTHCLEARVALUE                  0x4f28
+
+#define R300_ZB_ZMASK_OFFSET			 0x4f30
+#define R300_ZB_ZMASK_PITCH			 0x4f34
+#define R300_ZB_ZMASK_WRINDEX			 0x4f38
+#define R300_ZB_ZMASK_DWORD			 0x4f3c
+#define R300_ZB_ZMASK_RDINDEX			 0x4f40
+
+/* Hierarchical Z Memory Offset */
+#define R300_ZB_HIZ_OFFSET                       0x4f44
+
+/* Hierarchical Z Write Index */
+#define R300_ZB_HIZ_WRINDEX                      0x4f48
+
+/* Hierarchical Z Data */
+#define R300_ZB_HIZ_DWORD                        0x4f4c
+
+/* Hierarchical Z Read Index */
+#define R300_ZB_HIZ_RDINDEX                      0x4f50
+
+/* Hierarchical Z Pitch */
+#define R300_ZB_HIZ_PITCH                        0x4f54
+
+/* Z Buffer Z Pass Counter Data */
+#define R300_ZB_ZPASS_DATA                       0x4f58
+
+/* Z Buffer Z Pass Counter Address */
+#define R300_ZB_ZPASS_ADDR                       0x4f5c
+
+/* Depth buffer X and Y coordinate offset */
+#define R300_ZB_DEPTHXY_OFFSET                   0x4f60
+#	define R300_DEPTHX_OFFSET_SHIFT  1
+#	define R300_DEPTHX_OFFSET_MASK   0x000007FE
+#	define R300_DEPTHY_OFFSET_SHIFT  17
+#	define R300_DEPTHY_OFFSET_MASK   0x07FE0000
+
+/* Sets the fifo sizes */
+#define R500_ZB_FIFO_SIZE                        0x4fd0
+#	define R500_OP_FIFO_SIZE_FULL   (0 << 0)
+#	define R500_OP_FIFO_SIZE_HALF   (1 << 0)
+#	define R500_OP_FIFO_SIZE_QUATER (2 << 0)
+#	define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
+
+/* Stencil Reference Value and Mask for backfacing quads */
+/* R300_ZB_STENCILREFMASK handles front face */
+#define R500_ZB_STENCILREFMASK_BF                0x4fd4
+#	define R500_STENCILREF_SHIFT       0
+#	define R500_STENCILREF_MASK        0x000000ff
+#	define R500_STENCILMASK_SHIFT      8
+#	define R500_STENCILMASK_MASK       0x0000ff00
+#	define R500_STENCILWRITEMASK_SHIFT 16
+#	define R500_STENCILWRITEMASK_MASK  0x00ff0000
 
 /* BEGIN: Vertex program instruction set */
 
@@ -1628,6 +1757,22 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 #define R300_CP_CMD_BITBLT_MULTI	0xC0009B00
 
+#define R500_VAP_INDEX_OFFSET		0x208c
+
+#define R500_GA_US_VECTOR_INDEX         0x4250
+#define R500_GA_US_VECTOR_DATA          0x4254
+
+#define R500_RS_IP_0                    0x4074
+#define R500_RS_INST_0                  0x4320
+
+#define R500_US_CONFIG                  0x4600
+
+#define R500_US_FC_CTRL			0x4624
+#define R500_US_CODE_ADDR		0x4630
+
+#define R500_RB3D_COLOR_CLEAR_VALUE_AR  0x46c0
+#define R500_RB3D_CONSTANT_COLOR_AR     0x4ef8
+
 #endif /* _R300_REG_H */
 
 /* *INDENT-ON* */
diff --git a/sys/dev/drm/r600_cp.c b/sys/dev/drm/r600_cp.c
new file mode 100644
index 0000000000..08f6bdc4de
--- /dev/null
+++ b/sys/dev/drm/r600_cp.c
@@ -0,0 +1,2255 @@
+/*-
+ * Copyright 2008-2009 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *     Dave Airlie <airlied@redhat.com>
+ *     Alex Deucher <alexander.deucher@amd.com>
+ */
+
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/radeon_drm.h"
+#include "dev/drm/radeon_drv.h"
+
+#include "dev/drm/r600_microcode.h"
+
+# define ATI_PCIGART_PAGE_SIZE		4096	/**< PCI GART page size */
+# define ATI_PCIGART_PAGE_MASK		(~(ATI_PCIGART_PAGE_SIZE-1))
+
+#define R600_PTE_VALID     (1 << 0)
+#define R600_PTE_SYSTEM    (1 << 1)
+#define R600_PTE_SNOOPED   (1 << 2)
+#define R600_PTE_READABLE  (1 << 5)
+#define R600_PTE_WRITEABLE (1 << 6)
+
+/* MAX values used for gfx init */
+#define R6XX_MAX_SH_GPRS           256
+#define R6XX_MAX_TEMP_GPRS         16
+#define R6XX_MAX_SH_THREADS        256
+#define R6XX_MAX_SH_STACK_ENTRIES  4096
+#define R6XX_MAX_BACKENDS          8
+#define R6XX_MAX_BACKENDS_MASK     0xff
+#define R6XX_MAX_SIMDS             8
+#define R6XX_MAX_SIMDS_MASK        0xff
+#define R6XX_MAX_PIPES             8
+#define R6XX_MAX_PIPES_MASK        0xff
+
+#define R7XX_MAX_SH_GPRS           256
+#define R7XX_MAX_TEMP_GPRS         16
+#define R7XX_MAX_SH_THREADS        256
+#define R7XX_MAX_SH_STACK_ENTRIES  4096
+#define R7XX_MAX_BACKENDS          8
+#define R7XX_MAX_BACKENDS_MASK     0xff
+#define R7XX_MAX_SIMDS             16
+#define R7XX_MAX_SIMDS_MASK        0xffff
+#define R7XX_MAX_PIPES             8
+#define R7XX_MAX_PIPES_MASK        0xff
+
+static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
+{
+	int i;
+
+	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
+
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		int slots;
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
+			slots = (RADEON_READ(R600_GRBM_STATUS)
+				 & R700_CMDFIFO_AVAIL_MASK);
+		else
+			slots = (RADEON_READ(R600_GRBM_STATUS)
+				 & R600_CMDFIFO_AVAIL_MASK);
+		if (slots >= entries)
+			return 0;
+		DRM_UDELAY(1);
+	}
+	DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
+		 RADEON_READ(R600_GRBM_STATUS),
+		 RADEON_READ(R600_GRBM_STATUS2));
+
+	return -EBUSY;
+}
+
+static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
+{
+	int i, ret;
+
+	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
+		ret = r600_do_wait_for_fifo(dev_priv, 8);
+	else
+		ret = r600_do_wait_for_fifo(dev_priv, 16);
+	if (ret)
+		return ret;
+	for (i = 0; i < dev_priv->usec_timeout; i++) {
+		if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
+			return 0;
+		DRM_UDELAY(1);
+	}
+	DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
+		 RADEON_READ(R600_GRBM_STATUS),
+		 RADEON_READ(R600_GRBM_STATUS2));
+
+	return -EBUSY;
+}
+
+void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
+{
+#ifdef __linux__
+	struct drm_sg_mem *entry = dev->sg;
+	int max_pages;
+	int pages;
+	int i;
+#endif
+	if (gart_info->bus_addr) {
+#ifdef __linux__
+		max_pages = (gart_info->table_size / sizeof(u32));
+		pages = (entry->pages <= max_pages)
+		  ? entry->pages : max_pages;
+
+		for (i = 0; i < pages; i++) {
+			if (!entry->busaddr[i])
+				break;
+			pci_unmap_single(dev->pdev, entry->busaddr[i],
+					 PAGE_SIZE, PCI_DMA_TODEVICE);
+		}
+#endif
+		if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
+			gart_info->bus_addr = 0;
+	}
+}
+
+/* R600 has page table setup */
+int r600_page_table_init(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
+	struct drm_sg_mem *entry = dev->sg;
+	int ret = 0;
+	int i, j;
+	int max_pages, pages;
+	u64 *pci_gart, page_base;
+	dma_addr_t entry_addr;
+
+	/* okay page table is available - lets rock */
+
+	/* PTEs are 64-bits */
+	pci_gart = (u64 *)gart_info->addr;
+
+	max_pages = (gart_info->table_size / sizeof(u64));
+	pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
+
+	memset(pci_gart, 0, max_pages * sizeof(u64));
+
+	for (i = 0; i < pages; i++) {
+#ifdef __linux__
+		entry->busaddr[i] = pci_map_single(dev->pdev,
+						   page_address(entry->
+								pagelist[i]),
+						   PAGE_SIZE, PCI_DMA_TODEVICE);
+		if (entry->busaddr[i] == 0) {
+			DRM_ERROR("unable to map PCIGART pages!\n");
+			r600_page_table_cleanup(dev, gart_info);
+			goto done;
+		}
+#endif
+		entry_addr = entry->busaddr[i];
+		for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
+			page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
+			page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
+			page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
+
+			*pci_gart = page_base;
+
+			if ((i % 128) == 0)
+				DRM_DEBUG("page entry %d: 0x%016llx\n",
+				    i, (unsigned long long)page_base);
+			pci_gart++;
+			entry_addr += ATI_PCIGART_PAGE_SIZE;
+		}
+	}
+	ret = 1;
+#ifdef __linux__
+done:
+#endif
+	return ret;
+}
+
+static void r600_vm_flush_gart_range(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	u32 resp, countdown = 1000;
+	RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
+	RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
+	RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
+
+	do {
+		resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
+		countdown--;
+		DRM_UDELAY(1);
+	} while (((resp & 0xf0) == 0) && countdown);
+}
+
+static void r600_vm_init(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	/* initialise the VM to use the page table we constructed up there */
+	u32 vm_c0, i;
+	u32 mc_rd_a;
+	u32 vm_l2_cntl, vm_l2_cntl3;
+	/* okay set up the PCIE aperture type thingo */
+	RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
+	RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
+	RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+
+	/* setup MC RD a */
+	mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
+		R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
+		R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
+
+	RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
+	RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
+
+	RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
+	RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
+
+	RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
+	RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
+
+	RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
+	RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
+
+	RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
+	RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
+
+	RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
+	RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
+
+	RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
+	RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
+
+	vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
+	vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
+	RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
+
+	RADEON_WRITE(R600_VM_L2_CNTL2, 0);
+	vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
+		       R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
+		       R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
+	RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
+
+	vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
+
+	RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
+
+	vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
+
+	/* disable all other contexts */
+	for (i = 1; i < 8; i++)
+		RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
+
+	RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
+	RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
+	RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
+
+	r600_vm_flush_gart_range(dev);
+}
+
+/* load r600 microcode */
+static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
+{
+	int i;
+
+	r600_do_cp_stop(dev_priv);
+
+	RADEON_WRITE(R600_CP_RB_CNTL,
+		     R600_RB_NO_UPDATE |
+		     R600_RB_BLKSZ(15) |
+		     R600_RB_BUFSZ(3));
+
+	RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
+	RADEON_READ(R600_GRBM_SOFT_RESET);
+	DRM_UDELAY(15000);
+	RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
+
+	RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) {
+		DRM_INFO("Loading R600 CP Microcode\n");
+		for (i = 0; i < PM4_UCODE_SIZE; i++) {
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     R600_cp_microcode[i][0]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     R600_cp_microcode[i][1]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     R600_cp_microcode[i][2]);
+		}
+
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading R600 PFP Microcode\n");
+		for (i = 0; i < PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]);
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) {
+		DRM_INFO("Loading RV610 CP Microcode\n");
+		for (i = 0; i < PM4_UCODE_SIZE; i++) {
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV610_cp_microcode[i][0]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV610_cp_microcode[i][1]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV610_cp_microcode[i][2]);
+		}
+
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading RV610 PFP Microcode\n");
+		for (i = 0; i < PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]);
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
+		DRM_INFO("Loading RV630 CP Microcode\n");
+		for (i = 0; i < PM4_UCODE_SIZE; i++) {
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV630_cp_microcode[i][0]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV630_cp_microcode[i][1]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV630_cp_microcode[i][2]);
+		}
+
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading RV630 PFP Microcode\n");
+		for (i = 0; i < PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]);
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) {
+		DRM_INFO("Loading RV620 CP Microcode\n");
+		for (i = 0; i < PM4_UCODE_SIZE; i++) {
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV620_cp_microcode[i][0]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV620_cp_microcode[i][1]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV620_cp_microcode[i][2]);
+		}
+
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading RV620 PFP Microcode\n");
+		for (i = 0; i < PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]);
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
+		DRM_INFO("Loading RV635 CP Microcode\n");
+		for (i = 0; i < PM4_UCODE_SIZE; i++) {
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV635_cp_microcode[i][0]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV635_cp_microcode[i][1]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV635_cp_microcode[i][2]);
+		}
+
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading RV635 PFP Microcode\n");
+		for (i = 0; i < PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]);
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) {
+		DRM_INFO("Loading RV670 CP Microcode\n");
+		for (i = 0; i < PM4_UCODE_SIZE; i++) {
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV670_cp_microcode[i][0]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV670_cp_microcode[i][1]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV670_cp_microcode[i][2]);
+		}
+
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading RV670 PFP Microcode\n");
+		for (i = 0; i < PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
+		DRM_INFO("Loading RS780 CP Microcode\n");
+		for (i = 0; i < PM4_UCODE_SIZE; i++) {
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV670_cp_microcode[i][0]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV670_cp_microcode[i][1]);
+			RADEON_WRITE(R600_CP_ME_RAM_DATA,
+				     RV670_cp_microcode[i][2]);
+		}
+
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading RS780 PFP Microcode\n");
+		for (i = 0; i < PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
+	}
+	RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+	RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+	RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
+
+}
+
+static void r700_vm_init(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	/* initialise the VM to use the page table we constructed up there */
+	u32 vm_c0, i;
+	u32 mc_vm_md_l1;
+	u32 vm_l2_cntl, vm_l2_cntl3;
+	/* okay set up the PCIE aperture type thingo */
+	RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
+	RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
+	RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+
+	mc_vm_md_l1 = R700_ENABLE_L1_TLB |
+	    R700_ENABLE_L1_FRAGMENT_PROCESSING |
+	    R700_SYSTEM_ACCESS_MODE_IN_SYS |
+	    R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
+	    R700_EFFECTIVE_L1_TLB_SIZE(5) |
+	    R700_EFFECTIVE_L1_QUEUE_SIZE(5);
+
+	RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
+	RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
+	RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
+	RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
+	RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
+	RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
+	RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
+
+	vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
+	vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
+	RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
+
+	RADEON_WRITE(R600_VM_L2_CNTL2, 0);
+	vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
+	RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
+
+	vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
+
+	RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
+
+	vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
+
+	/* disable all other contexts */
+	for (i = 1; i < 8; i++)
+		RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
+
+	RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
+	RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
+	RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
+
+	r600_vm_flush_gart_range(dev);
+}
+
+/* load r600 microcode */
+static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
+{
+	int i;
+
+	r600_do_cp_stop(dev_priv);
+
+	RADEON_WRITE(R600_CP_RB_CNTL,
+		     R600_RB_NO_UPDATE |
+		     (15 << 8) |
+		     (3 << 0));
+
+	RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
+	RADEON_READ(R600_GRBM_SOFT_RESET);
+	DRM_UDELAY(15000);
+	RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
+
+
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) {
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading RV770 PFP Microcode\n");
+		for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]);
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+
+		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+		DRM_INFO("Loading RV770 CP Microcode\n");
+		for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
+		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) {
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading RV730 PFP Microcode\n");
+		for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+
+		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+		DRM_INFO("Loading RV730 CP Microcode\n");
+		for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
+		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) {
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+		DRM_INFO("Loading RV710 PFP Microcode\n");
+		for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]);
+		RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+
+		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+		DRM_INFO("Loading RV710 CP Microcode\n");
+		for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
+			RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]);
+		RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+
+	}
+	RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
+	RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
+	RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
+
+}
+
+static void r600_test_writeback(drm_radeon_private_t *dev_priv)
+{
+	u32 tmp;
+
+	/* Start with assuming that writeback doesn't work */
+	dev_priv->writeback_works = 0;
+
+	/* Writeback doesn't seem to work everywhere, test it here and possibly
+	 * enable it if it appears to work
+	 */
+	radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
+
+	RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
+
+	for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
+		u32 val;
+
+		val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
+		if (val == 0xdeadbeef)
+			break;
+		DRM_UDELAY(1);
+	}
+
+	if (tmp < dev_priv->usec_timeout) {
+		dev_priv->writeback_works = 1;
+		DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
+	} else {
+		dev_priv->writeback_works = 0;
+		DRM_INFO("writeback test failed\n");
+	}
+	if (radeon_no_wb == 1) {
+		dev_priv->writeback_works = 0;
+		DRM_INFO("writeback forced off\n");
+	}
+
+	if (!dev_priv->writeback_works) {
+		/* Disable writeback to avoid unnecessary bus master transfer */
+		RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
+			     RADEON_RB_NO_UPDATE);
+		RADEON_WRITE(R600_SCRATCH_UMSK, 0);
+	}
+}
+
+int r600_do_engine_reset(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
+
+	DRM_INFO("Resetting GPU\n");
+
+	cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
+	cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
+	RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
+
+	RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
+	RADEON_READ(R600_GRBM_SOFT_RESET);
+	DRM_UDELAY(50);
+	RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
+	RADEON_READ(R600_GRBM_SOFT_RESET);
+
+	RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
+	cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
+	RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
+
+	RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
+	RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
+	RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
+	RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
+
+	/* Reset the CP ring */
+	r600_do_cp_reset(dev_priv);
+
+	/* The CP is no longer running after an engine reset */
+	dev_priv->cp_running = 0;
+
+	/* Reset any pending vertex, indirect buffers */
+	radeon_freelist_reset(dev);
+
+	return 0;
+
+}
+
+static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
+					     u32 num_backends,
+					     u32 backend_disable_mask)
+{
+	u32 backend_map = 0;
+	u32 enabled_backends_mask;
+	u32 enabled_backends_count;
+	u32 cur_pipe;
+	u32 swizzle_pipe[R6XX_MAX_PIPES];
+	u32 cur_backend;
+	u32 i;
+
+	if (num_tile_pipes > R6XX_MAX_PIPES)
+		num_tile_pipes = R6XX_MAX_PIPES;
+	if (num_tile_pipes < 1)
+		num_tile_pipes = 1;
+	if (num_backends > R6XX_MAX_BACKENDS)
+		num_backends = R6XX_MAX_BACKENDS;
+	if (num_backends < 1)
+		num_backends = 1;
+
+	enabled_backends_mask = 0;
+	enabled_backends_count = 0;
+	for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
+		if (((backend_disable_mask >> i) & 1) == 0) {
+			enabled_backends_mask |= (1 << i);
+			++enabled_backends_count;
+		}
+		if (enabled_backends_count == num_backends)
+			break;
+	}
+
+	if (enabled_backends_count == 0) {
+		enabled_backends_mask = 1;
+		enabled_backends_count = 1;
+	}
+
+	if (enabled_backends_count != num_backends)
+		num_backends = enabled_backends_count;
+
+	memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
+	switch (num_tile_pipes) {
+	case 1:
+		swizzle_pipe[0] = 0;
+		break;
+	case 2:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		break;
+	case 3:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		swizzle_pipe[2] = 2;
+		break;
+	case 4:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		swizzle_pipe[2] = 2;
+		swizzle_pipe[3] = 3;
+		break;
+	case 5:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		swizzle_pipe[2] = 2;
+		swizzle_pipe[3] = 3;
+		swizzle_pipe[4] = 4;
+		break;
+	case 6:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 5;
+		swizzle_pipe[4] = 1;
+		swizzle_pipe[5] = 3;
+		break;
+	case 7:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 6;
+		swizzle_pipe[4] = 1;
+		swizzle_pipe[5] = 3;
+		swizzle_pipe[6] = 5;
+		break;
+	case 8:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 6;
+		swizzle_pipe[4] = 1;
+		swizzle_pipe[5] = 3;
+		swizzle_pipe[6] = 5;
+		swizzle_pipe[7] = 7;
+		break;
+	}
+
+	cur_backend = 0;
+	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
+		while (((1 << cur_backend) & enabled_backends_mask) == 0)
+			cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
+
+		backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
+
+		cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
+	}
+
+	return backend_map;
+}
+
+static int r600_count_pipe_bits(uint32_t val)
+{
+	int i, ret = 0;
+	for (i = 0; i < 32; i++) {
+		ret += val & 1;
+		val >>= 1;
+	}
+	return ret;
+}
+
+static void r600_gfx_init(struct drm_device *dev,
+			  drm_radeon_private_t *dev_priv)
+{
+	int i, j, num_qd_pipes;
+	u32 sx_debug_1;
+	u32 tc_cntl;
+	u32 arb_pop;
+	u32 num_gs_verts_per_thread;
+	u32 vgt_gs_per_es;
+	u32 gs_prim_buffer_depth = 0;
+	u32 sq_ms_fifo_sizes;
+	u32 sq_config;
+	u32 sq_gpr_resource_mgmt_1 = 0;
+	u32 sq_gpr_resource_mgmt_2 = 0;
+	u32 sq_thread_resource_mgmt = 0;
+	u32 sq_stack_resource_mgmt_1 = 0;
+	u32 sq_stack_resource_mgmt_2 = 0;
+	u32 hdp_host_path_cntl;
+	u32 backend_map;
+	u32 gb_tiling_config = 0;
+	u32 cc_rb_backend_disable = 0;
+	u32 cc_gc_shader_pipe_config = 0;
+	u32 ramcfg;
+
+	/* setup chip specs */
+	switch (dev_priv->flags & RADEON_FAMILY_MASK) {
+	case CHIP_R600:
+		dev_priv->r600_max_pipes = 4;
+		dev_priv->r600_max_tile_pipes = 8;
+		dev_priv->r600_max_simds = 4;
+		dev_priv->r600_max_backends = 4;
+		dev_priv->r600_max_gprs = 256;
+		dev_priv->r600_max_threads = 192;
+		dev_priv->r600_max_stack_entries = 256;
+		dev_priv->r600_max_hw_contexts = 8;
+		dev_priv->r600_max_gs_threads = 16;
+		dev_priv->r600_sx_max_export_size = 128;
+		dev_priv->r600_sx_max_export_pos_size = 16;
+		dev_priv->r600_sx_max_export_smx_size = 128;
+		dev_priv->r600_sq_num_cf_insts = 2;
+		break;
+	case CHIP_RV630:
+	case CHIP_RV635:
+		dev_priv->r600_max_pipes = 2;
+		dev_priv->r600_max_tile_pipes = 2;
+		dev_priv->r600_max_simds = 3;
+		dev_priv->r600_max_backends = 1;
+		dev_priv->r600_max_gprs = 128;
+		dev_priv->r600_max_threads = 192;
+		dev_priv->r600_max_stack_entries = 128;
+		dev_priv->r600_max_hw_contexts = 8;
+		dev_priv->r600_max_gs_threads = 4;
+		dev_priv->r600_sx_max_export_size = 128;
+		dev_priv->r600_sx_max_export_pos_size = 16;
+		dev_priv->r600_sx_max_export_smx_size = 128;
+		dev_priv->r600_sq_num_cf_insts = 2;
+		break;
+	case CHIP_RV610:
+	case CHIP_RS780:
+	case CHIP_RV620:
+		dev_priv->r600_max_pipes = 1;
+		dev_priv->r600_max_tile_pipes = 1;
+		dev_priv->r600_max_simds = 2;
+		dev_priv->r600_max_backends = 1;
+		dev_priv->r600_max_gprs = 128;
+		dev_priv->r600_max_threads = 192;
+		dev_priv->r600_max_stack_entries = 128;
+		dev_priv->r600_max_hw_contexts = 4;
+		dev_priv->r600_max_gs_threads = 4;
+		dev_priv->r600_sx_max_export_size = 128;
+		dev_priv->r600_sx_max_export_pos_size = 16;
+		dev_priv->r600_sx_max_export_smx_size = 128;
+		dev_priv->r600_sq_num_cf_insts = 1;
+		break;
+	case CHIP_RV670:
+		dev_priv->r600_max_pipes = 4;
+		dev_priv->r600_max_tile_pipes = 4;
+		dev_priv->r600_max_simds = 4;
+		dev_priv->r600_max_backends = 4;
+		dev_priv->r600_max_gprs = 192;
+		dev_priv->r600_max_threads = 192;
+		dev_priv->r600_max_stack_entries = 256;
+		dev_priv->r600_max_hw_contexts = 8;
+		dev_priv->r600_max_gs_threads = 16;
+		dev_priv->r600_sx_max_export_size = 128;
+		dev_priv->r600_sx_max_export_pos_size = 16;
+		dev_priv->r600_sx_max_export_smx_size = 128;
+		dev_priv->r600_sq_num_cf_insts = 2;
+		break;
+	default:
+		break;
+	}
+
+	/* Initialize HDP */
+	j = 0;
+	for (i = 0; i < 32; i++) {
+		RADEON_WRITE((0x2c14 + j), 0x00000000);
+		RADEON_WRITE((0x2c18 + j), 0x00000000);
+		RADEON_WRITE((0x2c1c + j), 0x00000000);
+		RADEON_WRITE((0x2c20 + j), 0x00000000);
+		RADEON_WRITE((0x2c24 + j), 0x00000000);
+		j += 0x18;
+	}
+
+	RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
+
+	/* setup tiling, simd, pipe config */
+	ramcfg = RADEON_READ(R600_RAMCFG);
+
+	switch (dev_priv->r600_max_tile_pipes) {
+	case 1:
+		gb_tiling_config |= R600_PIPE_TILING(0);
+		break;
+	case 2:
+		gb_tiling_config |= R600_PIPE_TILING(1);
+		break;
+	case 4:
+		gb_tiling_config |= R600_PIPE_TILING(2);
+		break;
+	case 8:
+		gb_tiling_config |= R600_PIPE_TILING(3);
+		break;
+	default:
+		break;
+	}
+
+	gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
+
+	gb_tiling_config |= R600_GROUP_SIZE(0);
+
+	if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
+		gb_tiling_config |= R600_ROW_TILING(3);
+		gb_tiling_config |= R600_SAMPLE_SPLIT(3);
+	} else {
+		gb_tiling_config |=
+			R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
+		gb_tiling_config |=
+			R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
+	}
+
+	gb_tiling_config |= R600_BANK_SWAPS(1);
+
+	backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
+							dev_priv->r600_max_backends,
+							(0xff << dev_priv->r600_max_backends) & 0xff);
+	gb_tiling_config |= R600_BACKEND_MAP(backend_map);
+
+	cc_gc_shader_pipe_config =
+		R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
+	cc_gc_shader_pipe_config |=
+		R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
+
+	cc_rb_backend_disable =
+		R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
+
+	RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
+	RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
+	RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
+
+	RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
+	RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
+	RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
+
+	num_qd_pipes =
+		R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
+	RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
+	RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
+
+	/* set HW defaults for 3D engine */
+	RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
+						R600_ROQ_IB2_START(0x2b)));
+
+	RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
+					      R600_ROQ_END(0x40)));
+
+	RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
+					R600_SYNC_GRADIENT |
+					R600_SYNC_WALKER |
+					R600_SYNC_ALIGNER));
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
+		RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
+
+	sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
+	sx_debug_1 |= R600_SMX_EVENT_RELEASE;
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
+		sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
+	RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
+
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
+		RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
+	else
+		RADEON_WRITE(R600_DB_DEBUG, 0);
+
+	RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
+					  R600_DEPTH_FLUSH(16) |
+					  R600_DEPTH_PENDING_FREE(4) |
+					  R600_DEPTH_CACHELINE_FREE(16)));
+	RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
+	RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
+
+	RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
+	RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
+
+	sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
+		sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
+				    R600_FETCH_FIFO_HIWATER(0xa) |
+				    R600_DONE_FIFO_HIWATER(0xe0) |
+				    R600_ALU_UPDATE_FIFO_HIWATER(0x8));
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
+		sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
+		sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
+	}
+	RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
+
+	/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
+	 * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
+	 */
+	sq_config = RADEON_READ(R600_SQ_CONFIG);
+	sq_config &= ~(R600_PS_PRIO(3) |
+		       R600_VS_PRIO(3) |
+		       R600_GS_PRIO(3) |
+		       R600_ES_PRIO(3));
+	sq_config |= (R600_DX9_CONSTS |
+		      R600_VC_ENABLE |
+		      R600_PS_PRIO(0) |
+		      R600_VS_PRIO(1) |
+		      R600_GS_PRIO(2) |
+		      R600_ES_PRIO(3));
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
+		sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
+					  R600_NUM_VS_GPRS(124) |
+					  R600_NUM_CLAUSE_TEMP_GPRS(4));
+		sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
+					  R600_NUM_ES_GPRS(0));
+		sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
+					   R600_NUM_VS_THREADS(48) |
+					   R600_NUM_GS_THREADS(4) |
+					   R600_NUM_ES_THREADS(4));
+		sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
+					    R600_NUM_VS_STACK_ENTRIES(128));
+		sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
+					    R600_NUM_ES_STACK_ENTRIES(0));
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
+		/* no vertex cache */
+		sq_config &= ~R600_VC_ENABLE;
+
+		sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
+					  R600_NUM_VS_GPRS(44) |
+					  R600_NUM_CLAUSE_TEMP_GPRS(2));
+		sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
+					  R600_NUM_ES_GPRS(17));
+		sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
+					   R600_NUM_VS_THREADS(78) |
+					   R600_NUM_GS_THREADS(4) |
+					   R600_NUM_ES_THREADS(31));
+		sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
+					    R600_NUM_VS_STACK_ENTRIES(40));
+		sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
+					    R600_NUM_ES_STACK_ENTRIES(16));
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
+		sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
+					  R600_NUM_VS_GPRS(44) |
+					  R600_NUM_CLAUSE_TEMP_GPRS(2));
+		sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
+					  R600_NUM_ES_GPRS(18));
+		sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
+					   R600_NUM_VS_THREADS(78) |
+					   R600_NUM_GS_THREADS(4) |
+					   R600_NUM_ES_THREADS(31));
+		sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
+					    R600_NUM_VS_STACK_ENTRIES(40));
+		sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
+					    R600_NUM_ES_STACK_ENTRIES(16));
+	} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
+		sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
+					  R600_NUM_VS_GPRS(44) |
+					  R600_NUM_CLAUSE_TEMP_GPRS(2));
+		sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
+					  R600_NUM_ES_GPRS(17));
+		sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
+					   R600_NUM_VS_THREADS(78) |
+					   R600_NUM_GS_THREADS(4) |
+					   R600_NUM_ES_THREADS(31));
+		sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
+					    R600_NUM_VS_STACK_ENTRIES(64));
+		sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
+					    R600_NUM_ES_STACK_ENTRIES(64));
+	}
+
+	RADEON_WRITE(R600_SQ_CONFIG, sq_config);
+	RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
+	RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
+	RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
+	RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
+	RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
+
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780))
+		RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
+	else
+		RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
+
+	RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
+						    R600_S0_Y(0x4) |
+						    R600_S1_X(0x4) |
+						    R600_S1_Y(0xc)));
+	RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
+						    R600_S0_Y(0xe) |
+						    R600_S1_X(0x2) |
+						    R600_S1_Y(0x2) |
+						    R600_S2_X(0xa) |
+						    R600_S2_Y(0x6) |
+						    R600_S3_X(0x6) |
+						    R600_S3_Y(0xa)));
+	RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
+							R600_S0_Y(0xb) |
+							R600_S1_X(0x4) |
+							R600_S1_Y(0xc) |
+							R600_S2_X(0x1) |
+							R600_S2_Y(0x6) |
+							R600_S3_X(0xa) |
+							R600_S3_Y(0xe)));
+	RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
+							R600_S4_Y(0x1) |
+							R600_S5_X(0x0) |
+							R600_S5_Y(0x0) |
+							R600_S6_X(0xb) |
+							R600_S6_Y(0x4) |
+							R600_S7_X(0x7) |
+							R600_S7_Y(0x8)));
+
+
+	switch (dev_priv->flags & RADEON_FAMILY_MASK) {
+	case CHIP_R600:
+	case CHIP_RV630:
+	case CHIP_RV635:
+		gs_prim_buffer_depth = 0;
+		break;
+	case CHIP_RV610:
+	case CHIP_RS780:
+	case CHIP_RV620:
+		gs_prim_buffer_depth = 32;
+		break;
+	case CHIP_RV670:
+		gs_prim_buffer_depth = 128;
+		break;
+	default:
+		break;
+	}
+
+	num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
+	vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
+	/* Max value for this is 256 */
+	if (vgt_gs_per_es > 256)
+		vgt_gs_per_es = 256;
+
+	RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
+	RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
+	RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
+	RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
+
+	/* more default values. 2D/3D driver should adjust as needed */
+	RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
+	RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
+	RADEON_WRITE(R600_SX_MISC, 0);
+	RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
+	RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
+	RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
+	RADEON_WRITE(R600_SPI_INPUT_Z, 0);
+	RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
+	RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
+
+	/* clear render buffer base addresses */
+	RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
+
+	switch (dev_priv->flags & RADEON_FAMILY_MASK) {
+	case CHIP_RV610:
+	case CHIP_RS780:
+	case CHIP_RV620:
+		tc_cntl = R600_TC_L2_SIZE(8);
+		break;
+	case CHIP_RV630:
+	case CHIP_RV635:
+		tc_cntl = R600_TC_L2_SIZE(4);
+		break;
+	case CHIP_R600:
+		tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
+		break;
+	default:
+		tc_cntl = R600_TC_L2_SIZE(0);
+		break;
+	}
+
+	RADEON_WRITE(R600_TC_CNTL, tc_cntl);
+
+	hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
+	RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
+
+	arb_pop = RADEON_READ(R600_ARB_POP);
+	arb_pop |= R600_ENABLE_TC128;
+	RADEON_WRITE(R600_ARB_POP, arb_pop);
+
+	RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
+	RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
+					  R600_NUM_CLIP_SEQ(3)));
+	RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
+
+}
+
+static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
+					     u32 num_backends,
+					     u32 backend_disable_mask)
+{
+	u32 backend_map = 0;
+	u32 enabled_backends_mask;
+	u32 enabled_backends_count;
+	u32 cur_pipe;
+	u32 swizzle_pipe[R7XX_MAX_PIPES];
+	u32 cur_backend;
+	u32 i;
+
+	if (num_tile_pipes > R7XX_MAX_PIPES)
+		num_tile_pipes = R7XX_MAX_PIPES;
+	if (num_tile_pipes < 1)
+		num_tile_pipes = 1;
+	if (num_backends > R7XX_MAX_BACKENDS)
+		num_backends = R7XX_MAX_BACKENDS;
+	if (num_backends < 1)
+		num_backends = 1;
+
+	enabled_backends_mask = 0;
+	enabled_backends_count = 0;
+	for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
+		if (((backend_disable_mask >> i) & 1) == 0) {
+			enabled_backends_mask |= (1 << i);
+			++enabled_backends_count;
+		}
+		if (enabled_backends_count == num_backends)
+			break;
+	}
+
+	if (enabled_backends_count == 0) {
+		enabled_backends_mask = 1;
+		enabled_backends_count = 1;
+	}
+
+	if (enabled_backends_count != num_backends)
+		num_backends = enabled_backends_count;
+
+	memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
+	switch (num_tile_pipes) {
+	case 1:
+		swizzle_pipe[0] = 0;
+		break;
+	case 2:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 1;
+		break;
+	case 3:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 1;
+		break;
+	case 4:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 3;
+		swizzle_pipe[3] = 1;
+		break;
+	case 5:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 1;
+		swizzle_pipe[4] = 3;
+		break;
+	case 6:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 5;
+		swizzle_pipe[4] = 3;
+		swizzle_pipe[5] = 1;
+		break;
+	case 7:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 6;
+		swizzle_pipe[4] = 3;
+		swizzle_pipe[5] = 1;
+		swizzle_pipe[6] = 5;
+		break;
+	case 8:
+		swizzle_pipe[0] = 0;
+		swizzle_pipe[1] = 2;
+		swizzle_pipe[2] = 4;
+		swizzle_pipe[3] = 6;
+		swizzle_pipe[4] = 3;
+		swizzle_pipe[5] = 1;
+		swizzle_pipe[6] = 7;
+		swizzle_pipe[7] = 5;
+		break;
+	}
+
+	cur_backend = 0;
+	for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
+		while (((1 << cur_backend) & enabled_backends_mask) == 0)
+			cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
+
+		backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
+
+		cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
+	}
+
+	return backend_map;
+}
+
+static void r700_gfx_init(struct drm_device *dev,
+			  drm_radeon_private_t *dev_priv)
+{
+	int i, j, num_qd_pipes;
+	u32 sx_debug_1;
+	u32 smx_dc_ctl0;
+	u32 num_gs_verts_per_thread;
+	u32 vgt_gs_per_es;
+	u32 gs_prim_buffer_depth = 0;
+	u32 sq_ms_fifo_sizes;
+	u32 sq_config;
+	u32 sq_thread_resource_mgmt;
+	u32 hdp_host_path_cntl;
+	u32 sq_dyn_gpr_size_simd_ab_0;
+	u32 backend_map;
+	u32 gb_tiling_config = 0;
+	u32 cc_rb_backend_disable = 0;
+	u32 cc_gc_shader_pipe_config = 0;
+	u32 mc_arb_ramcfg;
+	u32 db_debug4;
+
+	/* setup chip specs */
+	switch (dev_priv->flags & RADEON_FAMILY_MASK) {
+	case CHIP_RV770:
+		dev_priv->r600_max_pipes = 4;
+		dev_priv->r600_max_tile_pipes = 8;
+		dev_priv->r600_max_simds = 10;
+		dev_priv->r600_max_backends = 4;
+		dev_priv->r600_max_gprs = 256;
+		dev_priv->r600_max_threads = 248;
+		dev_priv->r600_max_stack_entries = 512;
+		dev_priv->r600_max_hw_contexts = 8;
+		dev_priv->r600_max_gs_threads = 16 * 2;
+		dev_priv->r600_sx_max_export_size = 128;
+		dev_priv->r600_sx_max_export_pos_size = 16;
+		dev_priv->r600_sx_max_export_smx_size = 112;
+		dev_priv->r600_sq_num_cf_insts = 2;
+
+		dev_priv->r700_sx_num_of_sets = 7;
+		dev_priv->r700_sc_prim_fifo_size = 0xF9;
+		dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
+		dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
+		break;
+	case CHIP_RV730:
+		dev_priv->r600_max_pipes = 2;
+		dev_priv->r600_max_tile_pipes = 4;
+		dev_priv->r600_max_simds = 8;
+		dev_priv->r600_max_backends = 2;
+		dev_priv->r600_max_gprs = 128;
+		dev_priv->r600_max_threads = 248;
+		dev_priv->r600_max_stack_entries = 256;
+		dev_priv->r600_max_hw_contexts = 8;
+		dev_priv->r600_max_gs_threads = 16 * 2;
+		dev_priv->r600_sx_max_export_size = 256;
+		dev_priv->r600_sx_max_export_pos_size = 32;
+		dev_priv->r600_sx_max_export_smx_size = 224;
+		dev_priv->r600_sq_num_cf_insts = 2;
+
+		dev_priv->r700_sx_num_of_sets = 7;
+		dev_priv->r700_sc_prim_fifo_size = 0xf9;
+		dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
+		dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
+		break;
+	case CHIP_RV710:
+		dev_priv->r600_max_pipes = 2;
+		dev_priv->r600_max_tile_pipes = 2;
+		dev_priv->r600_max_simds = 2;
+		dev_priv->r600_max_backends = 1;
+		dev_priv->r600_max_gprs = 256;
+		dev_priv->r600_max_threads = 192;
+		dev_priv->r600_max_stack_entries = 256;
+		dev_priv->r600_max_hw_contexts = 4;
+		dev_priv->r600_max_gs_threads = 8 * 2;
+		dev_priv->r600_sx_max_export_size = 128;
+		dev_priv->r600_sx_max_export_pos_size = 16;
+		dev_priv->r600_sx_max_export_smx_size = 112;
+		dev_priv->r600_sq_num_cf_insts = 1;
+
+		dev_priv->r700_sx_num_of_sets = 7;
+		dev_priv->r700_sc_prim_fifo_size = 0x40;
+		dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
+		dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
+		break;
+	default:
+		break;
+	}
+
+	/* Initialize HDP */
+	j = 0;
+	for (i = 0; i < 32; i++) {
+		RADEON_WRITE((0x2c14 + j), 0x00000000);
+		RADEON_WRITE((0x2c18 + j), 0x00000000);
+		RADEON_WRITE((0x2c1c + j), 0x00000000);
+		RADEON_WRITE((0x2c20 + j), 0x00000000);
+		RADEON_WRITE((0x2c24 + j), 0x00000000);
+		j += 0x18;
+	}
+
+	RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
+
+	/* setup tiling, simd, pipe config */
+	mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
+
+	switch (dev_priv->r600_max_tile_pipes) {
+	case 1:
+		gb_tiling_config |= R600_PIPE_TILING(0);
+		break;
+	case 2:
+		gb_tiling_config |= R600_PIPE_TILING(1);
+		break;
+	case 4:
+		gb_tiling_config |= R600_PIPE_TILING(2);
+		break;
+	case 8:
+		gb_tiling_config |= R600_PIPE_TILING(3);
+		break;
+	default:
+		break;
+	}
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
+		gb_tiling_config |= R600_BANK_TILING(1);
+	else
+		gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
+
+	gb_tiling_config |= R600_GROUP_SIZE(0);
+
+	if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
+		gb_tiling_config |= R600_ROW_TILING(3);
+		gb_tiling_config |= R600_SAMPLE_SPLIT(3);
+	} else {
+		gb_tiling_config |=
+			R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
+		gb_tiling_config |=
+			R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
+	}
+
+	gb_tiling_config |= R600_BANK_SWAPS(1);
+
+	backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
+							dev_priv->r600_max_backends,
+							(0xff << dev_priv->r600_max_backends) & 0xff);
+	gb_tiling_config |= R600_BACKEND_MAP(backend_map);
+
+	cc_gc_shader_pipe_config =
+		R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
+	cc_gc_shader_pipe_config |=
+		R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
+
+	cc_rb_backend_disable =
+		R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
+
+	RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
+	RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
+	RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
+
+	RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
+	RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
+	RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
+
+	RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
+	RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
+	RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
+	RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
+	RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
+
+	num_qd_pipes =
+		R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
+	RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
+	RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
+
+	/* set HW defaults for 3D engine */
+	RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
+						R600_ROQ_IB2_START(0x2b)));
+
+	RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
+
+	RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
+					R600_SYNC_GRADIENT |
+					R600_SYNC_WALKER |
+					R600_SYNC_ALIGNER));
+
+	sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
+	sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
+	RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
+
+	smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
+	smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
+	smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
+	RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
+
+	RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
+					  R700_GS_FLUSH_CTL(4) |
+					  R700_ACK_FLUSH_CTL(3) |
+					  R700_SYNC_FLUSH_CTL));
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
+		RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
+	else {
+		db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
+		db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
+		RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
+	}
+
+	RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
+						   R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
+						   R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
+
+	RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
+						 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
+						 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
+
+	RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
+
+	RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
+
+	RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
+
+	RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
+
+	RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
+
+	sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
+			    R600_DONE_FIFO_HIWATER(0xe0) |
+			    R600_ALU_UPDATE_FIFO_HIWATER(0x8));
+	switch (dev_priv->flags & RADEON_FAMILY_MASK) {
+	case CHIP_RV770:
+		sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
+		break;
+	case CHIP_RV730:
+	case CHIP_RV710:
+	default:
+		sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
+		break;
+	}
+	RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
+
+	/* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
+	 * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
+	 */
+	sq_config = RADEON_READ(R600_SQ_CONFIG);
+	sq_config &= ~(R600_PS_PRIO(3) |
+		       R600_VS_PRIO(3) |
+		       R600_GS_PRIO(3) |
+		       R600_ES_PRIO(3));
+	sq_config |= (R600_DX9_CONSTS |
+		      R600_VC_ENABLE |
+		      R600_EXPORT_SRC_C |
+		      R600_PS_PRIO(0) |
+		      R600_VS_PRIO(1) |
+		      R600_GS_PRIO(2) |
+		      R600_ES_PRIO(3));
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
+		/* no vertex cache */
+		sq_config &= ~R600_VC_ENABLE;
+
+	RADEON_WRITE(R600_SQ_CONFIG, sq_config);
+
+	RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
+						    R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
+						    R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
+
+	RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
+						    R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
+
+	sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
+				   R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
+				   R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
+	if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
+		sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
+	else
+		sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
+	RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
+
+	RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
+						     R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
+
+	RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
+						     R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
+
+	sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
+				     R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
+				     R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
+				     R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
+
+	RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
+	RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
+	RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
+	RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
+	RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
+	RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
+	RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
+	RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
+
+	RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
+						     R700_FORCE_EOV_MAX_REZ_CNT(255)));
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
+		RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
+							   R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
+	else
+		RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
+							   R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
+
+	switch (dev_priv->flags & RADEON_FAMILY_MASK) {
+	case CHIP_RV770:
+	case CHIP_RV730:
+		gs_prim_buffer_depth = 384;
+		break;
+	case CHIP_RV710:
+		gs_prim_buffer_depth = 128;
+		break;
+	default:
+		break;
+	}
+
+	num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
+	vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
+	/* Max value for this is 256 */
+	if (vgt_gs_per_es > 256)
+		vgt_gs_per_es = 256;
+
+	RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
+	RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
+	RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
+
+	/* more default values. 2D/3D driver should adjust as needed */
+	RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
+	RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
+	RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
+	RADEON_WRITE(R600_SX_MISC, 0);
+	RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
+	RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
+	RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
+	RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
+	RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
+	RADEON_WRITE(R600_SPI_INPUT_Z, 0);
+	RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
+	RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
+
+	/* clear render buffer base addresses */
+	RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
+	RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
+
+	RADEON_WRITE(R700_TCP_CNTL, 0);
+
+	hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
+	RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
+
+	RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
+
+	RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
+					  R600_NUM_CLIP_SEQ(3)));
+
+}
+
+static void r600_cp_init_ring_buffer(struct drm_device *dev,
+				       drm_radeon_private_t *dev_priv,
+				       struct drm_file *file_priv)
+{
+	u32 ring_start;
+	u64 rptr_addr;
+
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
+		r700_gfx_init(dev, dev_priv);
+	else
+		r600_gfx_init(dev, dev_priv);
+
+	RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
+	RADEON_READ(R600_GRBM_SOFT_RESET);
+	DRM_UDELAY(15000);
+	RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
+
+
+	/* Set ring buffer size */
+#ifdef __BIG_ENDIAN
+	RADEON_WRITE(R600_CP_RB_CNTL,
+		     RADEON_BUF_SWAP_32BIT |
+		     RADEON_RB_NO_UPDATE |
+		     (dev_priv->ring.rptr_update_l2qw << 8) |
+		     dev_priv->ring.size_l2qw);
+#else
+	RADEON_WRITE(R600_CP_RB_CNTL,
+		     RADEON_RB_NO_UPDATE |
+		     (dev_priv->ring.rptr_update_l2qw << 8) |
+		     dev_priv->ring.size_l2qw);
+#endif
+
+	RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
+
+	/* Set the write pointer delay */
+	RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
+
+#ifdef __BIG_ENDIAN
+	RADEON_WRITE(R600_CP_RB_CNTL,
+		     RADEON_BUF_SWAP_32BIT |
+		     RADEON_RB_NO_UPDATE |
+		     RADEON_RB_RPTR_WR_ENA |
+		     (dev_priv->ring.rptr_update_l2qw << 8) |
+		     dev_priv->ring.size_l2qw);
+#else
+	RADEON_WRITE(R600_CP_RB_CNTL,
+		     RADEON_RB_NO_UPDATE |
+		     RADEON_RB_RPTR_WR_ENA |
+		     (dev_priv->ring.rptr_update_l2qw << 8) |
+		     dev_priv->ring.size_l2qw);
+#endif
+
+	/* Initialize the ring buffer's read and write pointers */
+	RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
+	RADEON_WRITE(R600_CP_RB_WPTR, 0);
+	SET_RING_HEAD(dev_priv, 0);
+	dev_priv->ring.tail = 0;
+
+#if __OS_HAS_AGP
+	if (dev_priv->flags & RADEON_IS_AGP) {
+		rptr_addr = dev_priv->ring_rptr->offset
+			- dev->agp->base +
+			dev_priv->gart_vm_start;
+	} else
+#endif
+	{
+		rptr_addr = dev_priv->ring_rptr->offset
+			- ((unsigned long) dev->sg->virtual)
+			+ dev_priv->gart_vm_start;
+	}
+	RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
+		     rptr_addr & 0xffffffff);
+	RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
+		     upper_32_bits(rptr_addr));
+
+#ifdef __BIG_ENDIAN
+	RADEON_WRITE(R600_CP_RB_CNTL,
+		     RADEON_BUF_SWAP_32BIT |
+		     (dev_priv->ring.rptr_update_l2qw << 8) |
+		     dev_priv->ring.size_l2qw);
+#else
+	RADEON_WRITE(R600_CP_RB_CNTL,
+		     (dev_priv->ring.rptr_update_l2qw << 8) |
+		     dev_priv->ring.size_l2qw);
+#endif
+
+#if __OS_HAS_AGP
+	if (dev_priv->flags & RADEON_IS_AGP) {
+		/* XXX */
+		radeon_write_agp_base(dev_priv, dev->agp->base);
+
+		/* XXX */
+		radeon_write_agp_location(dev_priv,
+			     (((dev_priv->gart_vm_start - 1 +
+				dev_priv->gart_size) & 0xffff0000) |
+			      (dev_priv->gart_vm_start >> 16)));
+
+		ring_start = (dev_priv->cp_ring->offset
+			      - dev->agp->base
+			      + dev_priv->gart_vm_start);
+	} else
+#endif
+		ring_start = (dev_priv->cp_ring->offset
+			      - (unsigned long)dev->sg->virtual
+			      + dev_priv->gart_vm_start);
+
+	RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
+
+	RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
+
+	RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
+
+	/* Initialize the scratch register pointer.  This will cause
+	 * the scratch register values to be written out to memory
+	 * whenever they are updated.
+	 *
+	 * We simply put this behind the ring read pointer, this works
+	 * with PCI GART as well as (whatever kind of) AGP GART
+	 */
+	{
+		u64 scratch_addr;
+
+		scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
+		scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
+		scratch_addr += R600_SCRATCH_REG_OFFSET;
+		scratch_addr >>= 8;
+		scratch_addr &= 0xffffffff;
+
+		RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
+	}
+
+	RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
+
+	/* Turn on bus mastering */
+	radeon_enable_bm(dev_priv);
+
+	radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
+	RADEON_WRITE(R600_LAST_FRAME_REG, 0);
+
+	radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
+	RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
+
+	radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
+	RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
+
+	/* reset sarea copies of these */
+	if (dev_priv->sarea_priv) {
+		dev_priv->sarea_priv->last_frame = 0;
+		dev_priv->sarea_priv->last_dispatch = 0;
+		dev_priv->sarea_priv->last_clear = 0;
+	}
+
+	r600_do_wait_for_idle(dev_priv);
+
+}
+
+int r600_do_cleanup_cp(struct drm_device *dev)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG("\n");
+
+	/* Make sure interrupts are disabled here because the uninstall ioctl
+	 * may not have been called from userspace and after dev_private
+	 * is freed, it's too late.
+	 */
+	if (dev->irq_enabled)
+		drm_irq_uninstall(dev);
+
+#if __OS_HAS_AGP
+	if (dev_priv->flags & RADEON_IS_AGP) {
+		if (dev_priv->cp_ring != NULL) {
+			drm_core_ioremapfree(dev_priv->cp_ring, dev);
+			dev_priv->cp_ring = NULL;
+		}
+		if (dev_priv->ring_rptr != NULL) {
+			drm_core_ioremapfree(dev_priv->ring_rptr, dev);
+			dev_priv->ring_rptr = NULL;
+		}
+		if (dev->agp_buffer_map != NULL) {
+			drm_core_ioremapfree(dev->agp_buffer_map, dev);
+			dev->agp_buffer_map = NULL;
+		}
+	} else
+#endif
+	{
+
+		if (dev_priv->gart_info.bus_addr)
+			r600_page_table_cleanup(dev, &dev_priv->gart_info);
+
+		if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
+			drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
+			dev_priv->gart_info.addr = 0;
+		}
+	}
+	/* only clear to the start of flags */
+	memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
+
+	return 0;
+}
+
+int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
+		    struct drm_file *file_priv)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	DRM_DEBUG("\n");
+
+	/* if we require new memory map but we don't have it fail */
+	if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
+		DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
+		r600_do_cleanup_cp(dev);
+		return -EINVAL;
+	}
+
+	if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
+		DRM_DEBUG("Forcing AGP card to PCI mode\n");
+		dev_priv->flags &= ~RADEON_IS_AGP;
+		/* The writeback test succeeds, but when writeback is enabled,
+		 * the ring buffer read ptr update fails after first 128 bytes.
+		 */
+		radeon_no_wb = 1;
+	} else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
+		 && !init->is_pci) {
+		DRM_DEBUG("Restoring AGP flag\n");
+		dev_priv->flags |= RADEON_IS_AGP;
+	}
+
+	dev_priv->usec_timeout = init->usec_timeout;
+	if (dev_priv->usec_timeout < 1 ||
+	    dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
+		DRM_DEBUG("TIMEOUT problem!\n");
+		r600_do_cleanup_cp(dev);
+		return -EINVAL;
+	}
+
+	/* Enable vblank on CRTC1 for older X servers
+	 */
+	dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
+
+	dev_priv->cp_mode = init->cp_mode;
+
+	/* We don't support anything other than bus-mastering ring mode,
+	 * but the ring can be in either AGP or PCI space for the ring
+	 * read pointer.
+	 */
+	if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
+	    (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
+		DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
+		r600_do_cleanup_cp(dev);
+		return -EINVAL;
+	}
+
+	switch (init->fb_bpp) {
+	case 16:
+		dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
+		break;
+	case 32:
+	default:
+		dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
+		break;
+	}
+	dev_priv->front_offset = init->front_offset;
+	dev_priv->front_pitch = init->front_pitch;
+	dev_priv->back_offset = init->back_offset;
+	dev_priv->back_pitch = init->back_pitch;
+
+	dev_priv->ring_offset = init->ring_offset;
+	dev_priv->ring_rptr_offset = init->ring_rptr_offset;
+	dev_priv->buffers_offset = init->buffers_offset;
+	dev_priv->gart_textures_offset = init->gart_textures_offset;
+
+	dev_priv->sarea = drm_getsarea(dev);
+	if (!dev_priv->sarea) {
+		DRM_ERROR("could not find sarea!\n");
+		r600_do_cleanup_cp(dev);
+		return -EINVAL;
+	}
+
+	dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
+	if (!dev_priv->cp_ring) {
+		DRM_ERROR("could not find cp ring region!\n");
+		r600_do_cleanup_cp(dev);
+		return -EINVAL;
+	}
+	dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
+	if (!dev_priv->ring_rptr) {
+		DRM_ERROR("could not find ring read pointer!\n");
+		r600_do_cleanup_cp(dev);
+		return -EINVAL;
+	}
+	dev->agp_buffer_token = init->buffers_offset;
+	dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
+	if (!dev->agp_buffer_map) {
+		DRM_ERROR("could not find dma buffer region!\n");
+		r600_do_cleanup_cp(dev);
+		return -EINVAL;
+	}
+
+	if (init->gart_textures_offset) {
+		dev_priv->gart_textures =
+		    drm_core_findmap(dev, init->gart_textures_offset);
+		if (!dev_priv->gart_textures) {
+			DRM_ERROR("could not find GART texture region!\n");
+			r600_do_cleanup_cp(dev);
+			return -EINVAL;
+		}
+	}
+
+	dev_priv->sarea_priv =
+	    (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
+				    init->sarea_priv_offset);
+
+#if __OS_HAS_AGP
+	/* XXX */
+	if (dev_priv->flags & RADEON_IS_AGP) {
+		drm_core_ioremap_wc(dev_priv->cp_ring, dev);
+		drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
+		drm_core_ioremap_wc(dev->agp_buffer_map, dev);
+		if (!dev_priv->cp_ring->handle ||
+		    !dev_priv->ring_rptr->handle ||
+		    !dev->agp_buffer_map->handle) {
+			DRM_ERROR("could not find ioremap agp regions!\n");
+			r600_do_cleanup_cp(dev);
+			return -EINVAL;
+		}
+	} else
+#endif
+	{
+		dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
+		dev_priv->ring_rptr->handle =
+		    (void *)dev_priv->ring_rptr->offset;
+		dev->agp_buffer_map->handle =
+		    (void *)dev->agp_buffer_map->offset;
+
+		DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
+			  dev_priv->cp_ring->handle);
+		DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
+			  dev_priv->ring_rptr->handle);
+		DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
+			  dev->agp_buffer_map->handle);
+	}
+
+	dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
+	dev_priv->fb_size =
+		(((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
+		- dev_priv->fb_location;
+
+	dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
+					((dev_priv->front_offset
+					  + dev_priv->fb_location) >> 10));
+
+	dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
+				       ((dev_priv->back_offset
+					 + dev_priv->fb_location) >> 10));
+
+	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
+					((dev_priv->depth_offset
+					  + dev_priv->fb_location) >> 10));
+
+	dev_priv->gart_size = init->gart_size;
+
+	/* New let's set the memory map ... */
+	if (dev_priv->new_memmap) {
+		u32 base = 0;
+
+		DRM_INFO("Setting GART location based on new memory map\n");
+
+		/* If using AGP, try to locate the AGP aperture at the same
+		 * location in the card and on the bus, though we have to
+		 * align it down.
+		 */
+#if __OS_HAS_AGP
+		/* XXX */
+		if (dev_priv->flags & RADEON_IS_AGP) {
+			base = dev->agp->base;
+			/* Check if valid */
+			if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
+			    base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
+				DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
+					 dev->agp->base);
+				base = 0;
+			}
+		}
+#endif
+		/* If not or if AGP is at 0 (Macs), try to put it elsewhere */
+		if (base == 0) {
+			base = dev_priv->fb_location + dev_priv->fb_size;
+			if (base < dev_priv->fb_location ||
+			    ((base + dev_priv->gart_size) & 0xfffffffful) < base)
+				base = dev_priv->fb_location
+					- dev_priv->gart_size;
+		}
+		dev_priv->gart_vm_start = base & 0xffc00000u;
+		if (dev_priv->gart_vm_start != base)
+			DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
+				 base, dev_priv->gart_vm_start);
+	}
+
+#if __OS_HAS_AGP
+	/* XXX */
+	if (dev_priv->flags & RADEON_IS_AGP)
+		dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
+						 - dev->agp->base
+						 + dev_priv->gart_vm_start);
+	else
+#endif
+		dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
+						 - (unsigned long)dev->sg->virtual
+						 + dev_priv->gart_vm_start);
+
+	DRM_DEBUG("fb 0x%08x size %d\n",
+		  (unsigned int) dev_priv->fb_location,
+		  (unsigned int) dev_priv->fb_size);
+	DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
+	DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
+		  (unsigned int) dev_priv->gart_vm_start);
+	DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
+		  dev_priv->gart_buffers_offset);
+
+	dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
+	dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
+			      + init->ring_size / sizeof(u32));
+	dev_priv->ring.size = init->ring_size;
+	dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
+
+	dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
+	dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
+
+	dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
+	dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
+
+	dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
+
+	dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
+
+#if __OS_HAS_AGP
+	if (dev_priv->flags & RADEON_IS_AGP) {
+		/* XXX turn off pcie gart */
+	} else
+#endif
+	{
+		dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
+		/* if we have an offset set from userspace */
+		if (!dev_priv->pcigart_offset_set) {
+			DRM_ERROR("Need gart offset from userspace\n");
+			r600_do_cleanup_cp(dev);
+			return -EINVAL;
+		}
+
+		DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
+
+		dev_priv->gart_info.bus_addr =
+			dev_priv->pcigart_offset + dev_priv->fb_location;
+		dev_priv->gart_info.mapping.offset =
+			dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
+		dev_priv->gart_info.mapping.size =
+			dev_priv->gart_info.table_size;
+
+		drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
+		if (!dev_priv->gart_info.mapping.handle) {
+			DRM_ERROR("ioremap failed.\n");
+			r600_do_cleanup_cp(dev);
+			return -EINVAL;
+		}
+
+		dev_priv->gart_info.addr =
+			dev_priv->gart_info.mapping.handle;
+
+		DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
+			  dev_priv->gart_info.addr,
+			  dev_priv->pcigart_offset);
+
+		if (!r600_page_table_init(dev)) {
+			DRM_ERROR("Failed to init GART table\n");
+			r600_do_cleanup_cp(dev);
+			return -EINVAL;
+		}
+
+		if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
+			r700_vm_init(dev);
+		else
+			r600_vm_init(dev);
+	}
+
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
+		r700_cp_load_microcode(dev_priv);
+	else
+		r600_cp_load_microcode(dev_priv);
+
+	r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
+
+	dev_priv->last_buf = 0;
+
+	r600_do_engine_reset(dev);
+	r600_test_writeback(dev_priv);
+
+	return 0;
+}
+
+int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	DRM_DEBUG("\n");
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
+		r700_vm_init(dev);
+		r700_cp_load_microcode(dev_priv);
+	} else {
+		r600_vm_init(dev);
+		r600_cp_load_microcode(dev_priv);
+	}
+	r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
+	r600_do_engine_reset(dev);
+
+	return 0;
+}
+
+/* Wait for the CP to go idle.
+ */
+int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
+{
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	BEGIN_RING(5);
+	OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
+	OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
+	/* wait for 3D idle clean */
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+	OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
+	OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
+
+	ADVANCE_RING();
+	COMMIT_RING();
+
+	return r600_do_wait_for_idle(dev_priv);
+}
+
+/* Start the Command Processor.
+ */
+void r600_do_cp_start(drm_radeon_private_t *dev_priv)
+{
+	u32 cp_me;
+	RING_LOCALS;
+	DRM_DEBUG("\n");
+
+	BEGIN_RING(7);
+	OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
+	OUT_RING(0x00000001);
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
+		OUT_RING(0x00000003);
+	else
+		OUT_RING(0x00000000);
+	OUT_RING((dev_priv->r600_max_hw_contexts - 1));
+	OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
+	OUT_RING(0x00000000);
+	OUT_RING(0x00000000);
+	ADVANCE_RING();
+	COMMIT_RING();
+
+	/* set the mux and reset the halt bit */
+	cp_me = 0xff;
+	RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
+
+	dev_priv->cp_running = 1;
+
+}
+
+void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
+{
+	u32 cur_read_ptr;
+	DRM_DEBUG("\n");
+
+	cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
+	RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
+	SET_RING_HEAD(dev_priv, cur_read_ptr);
+	dev_priv->ring.tail = cur_read_ptr;
+}
+
+void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
+{
+	uint32_t cp_me;
+
+	DRM_DEBUG("\n");
+
+	cp_me = 0xff | R600_CP_ME_HALT;
+
+	RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
+
+	dev_priv->cp_running = 0;
+}
+
+int r600_cp_dispatch_indirect(struct drm_device *dev,
+			      struct drm_buf *buf, int start, int end)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	RING_LOCALS;
+
+	if (start != end) {
+		unsigned long offset = (dev_priv->gart_buffers_offset
+					+ buf->offset + start);
+		int dwords = (end - start + 3) / sizeof(u32);
+
+		DRM_DEBUG("dwords:%d\n", dwords);
+		DRM_DEBUG("offset 0x%lx\n", offset);
+
+
+		/* Indirect buffer data must be a multiple of 16 dwords.
+		 * pad the data with a Type-2 CP packet.
+		 */
+		while (dwords & 0xf) {
+			u32 *data = (u32 *)
+			    ((char *)dev->agp_buffer_map->handle
+			     + buf->offset + start);
+			data[dwords++] = RADEON_CP_PACKET2;
+		}
+
+		/* Fire off the indirect buffer */
+		BEGIN_RING(4);
+		OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
+		OUT_RING((offset & 0xfffffffc));
+		OUT_RING((upper_32_bits(offset) & 0xff));
+		OUT_RING(dwords);
+		ADVANCE_RING();
+	}
+
+	return 0;
+}
diff --git a/sys/dev/drm/r600_microcode.h b/sys/dev/drm/r600_microcode.h
new file mode 100644
index 0000000000..5f223e5c0c
--- /dev/null
+++ b/sys/dev/drm/r600_microcode.h
@@ -0,0 +1,23292 @@
+/*-
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+static const int ME_JUMP_TABLE_START = 1764;
+static const int ME_JUMP_TABLE_END   = 1792;
+
+#define PFP_UCODE_SIZE 576
+#define PM4_UCODE_SIZE 1792
+#define R700_PFP_UCODE_SIZE 848
+#define R700_PM4_UCODE_SIZE 1360
+
+static const u32 R600_cp_microcode[][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00000000, 0x00e00000, 0x000 },
+    { 0x00010000, 0xc0294620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x614 },
+    { 0x00000000, 0x00600000, 0x5b2 },
+    { 0x00000000, 0x00600000, 0x5c5 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000f00, 0x00281622, 0x000 },
+    { 0x00000008, 0x00211625, 0x000 },
+    { 0x00000020, 0x00203625, 0x000 },
+    { 0x8d000000, 0x00204411, 0x000 },
+    { 0x00000004, 0x002f0225, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x018 },
+    { 0x00412000, 0x00404811, 0x019 },
+    { 0x00422000, 0x00204811, 0x000 },
+    { 0x8e000000, 0x00204411, 0x000 },
+    { 0x00000031, 0x00204a2d, 0x000 },
+    { 0x90000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x0000000c, 0x00211622, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000019, 0x00211a22, 0x000 },
+    { 0x00000004, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002914c5, 0x000 },
+    { 0x00000021, 0x00203625, 0x000 },
+    { 0x00000000, 0x003a1402, 0x000 },
+    { 0x00000016, 0x00211625, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x0000001d, 0x00200e2d, 0x000 },
+    { 0xfffffffc, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002914a3, 0x000 },
+    { 0x0000001d, 0x00203625, 0x000 },
+    { 0x00008000, 0x00280e22, 0x000 },
+    { 0x00000007, 0x00220e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x20000000, 0x00280e22, 0x000 },
+    { 0x00000006, 0x00210e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00220222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x038 },
+    { 0x00000000, 0x2ee00000, 0x035 },
+    { 0x00000000, 0x2ce00000, 0x037 },
+    { 0x00000000, 0x00400e2d, 0x039 },
+    { 0x00000008, 0x00200e2d, 0x000 },
+    { 0x00000009, 0x0040122d, 0x046 },
+    { 0x00000001, 0x00400e2d, 0x039 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x03e },
+    { 0x00000008, 0x00401c11, 0x041 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x0000000f, 0x00281e27, 0x000 },
+    { 0x00000003, 0x00221e27, 0x000 },
+    { 0x7fc00000, 0x00281a23, 0x000 },
+    { 0x00000014, 0x00211a26, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000008, 0x00221a26, 0x000 },
+    { 0x00000000, 0x00290cc7, 0x000 },
+    { 0x00000030, 0x00203624, 0x000 },
+    { 0x00007f00, 0x00281221, 0x000 },
+    { 0x00001400, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04b },
+    { 0x00000001, 0x00290e23, 0x000 },
+    { 0x00000010, 0x00203623, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfff80000, 0x00294a23, 0x000 },
+    { 0x00000000, 0x003a2c02, 0x000 },
+    { 0x00000002, 0x00220e2b, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x00001fff, 0x00294a23, 0x000 },
+    { 0x00000030, 0x00204a2d, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000032, 0x00200e2d, 0x000 },
+    { 0x060a0200, 0x00294a23, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x061 },
+    { 0x00000000, 0x2ee00000, 0x05f },
+    { 0x00000000, 0x2ce00000, 0x05e },
+    { 0x00000000, 0x00400e2d, 0x062 },
+    { 0x00000001, 0x00400e2d, 0x062 },
+    { 0x0000000a, 0x00200e2d, 0x000 },
+    { 0x0000000b, 0x0040122d, 0x06a },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x7fc00000, 0x00281623, 0x000 },
+    { 0x00000014, 0x00211625, 0x000 },
+    { 0x00000001, 0x00331625, 0x000 },
+    { 0x80000000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00290ca3, 0x000 },
+    { 0x3ffffc00, 0x00290e23, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x06d },
+    { 0x00000100, 0x00401c11, 0x070 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x000000f0, 0x00281e27, 0x000 },
+    { 0x00000004, 0x00221e27, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0xfffff0ff, 0x00281a30, 0x000 },
+    { 0x0000a028, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e6, 0x000 },
+    { 0x0000a018, 0x00204411, 0x000 },
+    { 0x3fffffff, 0x00284a23, 0x000 },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x0000002d, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a3, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x080 },
+    { 0x0000002e, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a4, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x081 },
+    { 0x00000000, 0x00400000, 0x087 },
+    { 0x0000002d, 0x00203623, 0x000 },
+    { 0x0000002e, 0x00203624, 0x000 },
+    { 0x0000001d, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x087 },
+    { 0x00000000, 0x00600000, 0x5ed },
+    { 0x00000000, 0x00600000, 0x5e1 },
+    { 0x00000002, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x08a },
+    { 0x00000018, 0xc0403620, 0x090 },
+    { 0x00000000, 0x2ee00000, 0x08e },
+    { 0x00000000, 0x2ce00000, 0x08d },
+    { 0x00000002, 0x00400e2d, 0x08f },
+    { 0x00000003, 0x00400e2d, 0x08f },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000018, 0x00203623, 0x000 },
+    { 0x00000003, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x095 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x09d },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x2ee00000, 0x09b },
+    { 0x00000000, 0x2ce00000, 0x09a },
+    { 0x00000002, 0x00400e2d, 0x09c },
+    { 0x00000003, 0x00400e2d, 0x09c },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x003f0000, 0x00280e23, 0x000 },
+    { 0x00000010, 0x00210e23, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x0000001e, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0a4 },
+    { 0x0000001c, 0xc0203620, 0x000 },
+    { 0x0000001f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0a7 },
+    { 0x0000001b, 0xc0203620, 0x000 },
+    { 0x00000008, 0x00210e2b, 0x000 },
+    { 0x0000007f, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0db },
+    { 0x00000000, 0x27000000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00221e30, 0x000 },
+    { 0x99800000, 0x00204411, 0x000 },
+    { 0x00000004, 0x0020122d, 0x000 },
+    { 0x00000008, 0x00221224, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00291ce4, 0x000 },
+    { 0x00000000, 0x00604807, 0x128 },
+    { 0x9b000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x9c000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x0033146f, 0x000 },
+    { 0x00000001, 0x00333e23, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00203c05, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e007, 0x00204411, 0x000 },
+    { 0x0000000f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0c5 },
+    { 0x00f8ff08, 0x00204811, 0x000 },
+    { 0x98000000, 0x00404811, 0x0d6 },
+    { 0x000000f0, 0x00280e22, 0x000 },
+    { 0x000000a0, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x0d4 },
+    { 0x00000013, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0cf },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0ce },
+    { 0x00003f00, 0x00400c11, 0x0d0 },
+    { 0x00001f00, 0x00400c11, 0x0d0 },
+    { 0x00000f00, 0x00200c11, 0x000 },
+    { 0x00380009, 0x00294a23, 0x000 },
+    { 0x3f000000, 0x00280e2b, 0x000 },
+    { 0x00000002, 0x00220e23, 0x000 },
+    { 0x00000007, 0x00494a23, 0x0d6 },
+    { 0x00380f09, 0x00204811, 0x000 },
+    { 0x68000007, 0x00204811, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000a202, 0x00204411, 0x000 },
+    { 0x00ff0000, 0x00284a22, 0x000 },
+    { 0x00000030, 0x00200e2d, 0x000 },
+    { 0x0000002e, 0x0020122d, 0x000 },
+    { 0x00000000, 0x002f0083, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0e3 },
+    { 0x00000000, 0x00600000, 0x5e7 },
+    { 0x00000000, 0x00400000, 0x0e4 },
+    { 0x00000000, 0x00600000, 0x5ea },
+    { 0x00000007, 0x0020222d, 0x000 },
+    { 0x00000005, 0x00220e22, 0x000 },
+    { 0x00100000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x000000ef, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x0000001d, 0x00200e2d, 0x000 },
+    { 0x00000003, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x0f1 },
+    { 0x0000000b, 0x00210228, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0f1 },
+    { 0x00000400, 0x00292228, 0x000 },
+    { 0x0000001a, 0x00203628, 0x000 },
+    { 0x0000001c, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0f6 },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000001e, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x104 },
+    { 0x0000a30f, 0x00204411, 0x000 },
+    { 0x00000013, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x0fd },
+    { 0xffffffff, 0x00404811, 0x104 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x100 },
+    { 0x0000ffff, 0x00404811, 0x104 },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x103 },
+    { 0x000000ff, 0x00404811, 0x104 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0002c400, 0x00204411, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x10b },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x00000019, 0x00203623, 0x000 },
+    { 0x00000018, 0x40224a20, 0x000 },
+    { 0x00000010, 0xc0424a20, 0x10d },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000019, 0x00203623, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000000a, 0x00201011, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x114 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00531224, 0x110 },
+    { 0xffbfffff, 0x00283a2e, 0x000 },
+    { 0x0000001b, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x127 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0x00000018, 0x00220e30, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e00e, 0x00204411, 0x000 },
+    { 0x07f8ff08, 0x00204811, 0x000 },
+    { 0x00000000, 0x00294a23, 0x000 },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x00800000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x614 },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x613 },
+    { 0x00000004, 0x00404c11, 0x12e },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x2fe },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x19f },
+    { 0x00000000, 0x00600000, 0x151 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40280620, 0x000 },
+    { 0x00000010, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x00341461, 0x000 },
+    { 0x00000000, 0x00741882, 0x2a4 },
+    { 0x0001a1fd, 0x00604411, 0x2c9 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x138 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x2fe },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x19f },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x151 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0681a20, 0x2a4 },
+    { 0x0001a1fd, 0x00604411, 0x2c9 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x149 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000001, 0x00300a2f, 0x000 },
+    { 0x00000001, 0x00210a22, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600000, 0x17c },
+    { 0x00000000, 0x00600000, 0x18d },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00202c08, 0x000 },
+    { 0x00000000, 0x00202411, 0x000 },
+    { 0x00000000, 0x00202811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000002, 0x00221e29, 0x000 },
+    { 0x00000000, 0x007048eb, 0x189 },
+    { 0x00000000, 0x00600000, 0x2a4 },
+    { 0x00000001, 0x40330620, 0x000 },
+    { 0x00000000, 0xc0302409, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x173 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000001, 0x00530621, 0x16f },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0604800, 0x184 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000013, 0x0020062d, 0x000 },
+    { 0x00000000, 0x0078042a, 0x2e4 },
+    { 0x00000000, 0x00202809, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x165 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000210, 0x00600411, 0x2fe },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x181 },
+    { 0x0000001b, 0xc0203620, 0x000 },
+    { 0x0000001c, 0xc0203620, 0x000 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x46000000, 0x00600811, 0x19f },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x188 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00804811, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40281620, 0x000 },
+    { 0x00000010, 0xc0811a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000008, 0x00221e30, 0x000 },
+    { 0x00000032, 0x00201a2d, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfffbff09, 0x00204811, 0x000 },
+    { 0x00000011, 0x0020222d, 0x000 },
+    { 0x00001fff, 0x00294a28, 0x000 },
+    { 0x00000006, 0x0020222d, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000100, 0x00201811, 0x000 },
+    { 0x00000008, 0x00621e28, 0x128 },
+    { 0x00000008, 0x00822228, 0x000 },
+    { 0x0002c000, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00600e2d, 0x1aa },
+    { 0x0000001c, 0x00600e2d, 0x1aa },
+    { 0x0000c008, 0x00204411, 0x000 },
+    { 0x0000001d, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1a6 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x39000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00804802, 0x000 },
+    { 0x00000020, 0x00202e2d, 0x000 },
+    { 0x00000000, 0x003b0d63, 0x000 },
+    { 0x00000008, 0x00224a23, 0x000 },
+    { 0x00000010, 0x00224a23, 0x000 },
+    { 0x00000018, 0x00224a23, 0x000 },
+    { 0x00000000, 0x00804803, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x2fe },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x19f },
+    { 0x00000007, 0x0021062f, 0x000 },
+    { 0x00000019, 0x00200a2d, 0x000 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000ffff, 0x40282220, 0x000 },
+    { 0x0000000f, 0x00262228, 0x000 },
+    { 0x00000010, 0x40212620, 0x000 },
+    { 0x0000000f, 0x00262629, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1cd },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000081, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000080, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1c9 },
+    { 0x00000000, 0x00600000, 0x1d6 },
+    { 0x00000001, 0x00531e27, 0x1c5 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000001f, 0x00280a22, 0x000 },
+    { 0x0000001f, 0x00282a2a, 0x000 },
+    { 0x00000001, 0x00530621, 0x1be },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000002, 0x00304a2f, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x00301e2f, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x1d6 },
+    { 0x00000001, 0x00531e27, 0x1d2 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x0000000f, 0x00260e23, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000000f, 0x00261224, 0x000 },
+    { 0x00000000, 0x00201411, 0x000 },
+    { 0x00000000, 0x00601811, 0x2a4 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022b, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1e5 },
+    { 0x00000010, 0x00221628, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a29, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000010, 0x00221623, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a24, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x00731503, 0x1f2 },
+    { 0x00000000, 0x00201805, 0x000 },
+    { 0x00000000, 0x00731524, 0x1f2 },
+    { 0x00000000, 0x002d14c5, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00000000, 0x00202003, 0x000 },
+    { 0x00000000, 0x00802404, 0x000 },
+    { 0x0000000f, 0x00210225, 0x000 },
+    { 0x00000000, 0x14c00000, 0x613 },
+    { 0x00000000, 0x002b1405, 0x000 },
+    { 0x00000001, 0x00901625, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x2fe },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x19f },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00294a22, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a21, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000ffff, 0x40281220, 0x000 },
+    { 0x00000010, 0xc0211a20, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211620, 0x000 },
+    { 0x00000000, 0x00741465, 0x2a4 },
+    { 0x0001a1fd, 0x00604411, 0x2c9 },
+    { 0x00000001, 0x00330621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x206 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x1ff },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x5c5 },
+    { 0x00000000, 0x0040040f, 0x200 },
+    { 0x00000000, 0x00600000, 0x5b2 },
+    { 0x00000000, 0x00600000, 0x5c5 },
+    { 0x00000210, 0x00600411, 0x2fe },
+    { 0x00000000, 0x00600000, 0x18d },
+    { 0x00000000, 0x00600000, 0x189 },
+    { 0x00000000, 0x00600000, 0x2a4 },
+    { 0x00000000, 0x00600000, 0x28c },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x21f },
+    { 0x00000000, 0xc0404800, 0x21c },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x00600411, 0x2e4 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x5b2 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000018, 0x40210a20, 0x000 },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x235 },
+    { 0x0000001a, 0x0020222d, 0x000 },
+    { 0x00080101, 0x00292228, 0x000 },
+    { 0x0000001a, 0x00203628, 0x000 },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x23a },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000010, 0x00600411, 0x2fe },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x19f },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00000000, 0x00600000, 0x265 },
+    { 0x0000001d, 0x00201e2d, 0x000 },
+    { 0x00000001, 0x00211e27, 0x000 },
+    { 0x00000000, 0x14e00000, 0x253 },
+    { 0x00000018, 0x00201e2d, 0x000 },
+    { 0x0000ffff, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00341c27, 0x000 },
+    { 0x00000000, 0x12c00000, 0x248 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e5, 0x000 },
+    { 0x00000000, 0x08c00000, 0x24b },
+    { 0x00000000, 0x00201407, 0x000 },
+    { 0x00000018, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00211e27, 0x000 },
+    { 0x00000000, 0x00341c47, 0x000 },
+    { 0x00000000, 0x12c00000, 0x250 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x08c00000, 0x253 },
+    { 0x00000000, 0x00201807, 0x000 },
+    { 0x00000000, 0x00600000, 0x2aa },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000000, 0x00342023, 0x000 },
+    { 0x00000000, 0x12c00000, 0x25b },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x25a },
+    { 0x00000016, 0x00404811, 0x25f },
+    { 0x00000018, 0x00404811, 0x25f },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x25e },
+    { 0x00000017, 0x00404811, 0x25f },
+    { 0x00000019, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00604411, 0x2d2 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x23f },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000010, 0x40210620, 0x000 },
+    { 0x0000ffff, 0xc0280a20, 0x000 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0881a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x614 },
+    { 0x00000000, 0x00600000, 0x5b2 },
+    { 0x00000000, 0xc0600000, 0x28c },
+    { 0x00000005, 0x00200a2d, 0x000 },
+    { 0x00000008, 0x00220a22, 0x000 },
+    { 0x00000034, 0x00201a2d, 0x000 },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00007000, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00311ce6, 0x000 },
+    { 0x00000033, 0x00201a2d, 0x000 },
+    { 0x0000000c, 0x00221a26, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x06e00000, 0x27b },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000034, 0x00203623, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00691ce2, 0x128 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x286 },
+    { 0x00000001, 0x00333e2f, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000024, 0x00403627, 0x000 },
+    { 0x0000000c, 0xc0220a20, 0x000 },
+    { 0x00000032, 0x00203622, 0x000 },
+    { 0x00000031, 0xc0403620, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000009, 0x00204811, 0x000 },
+    { 0xa1000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000029, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce3, 0x000 },
+    { 0x00000029, 0x00203627, 0x000 },
+    { 0x0000002a, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce4, 0x000 },
+    { 0x0000002a, 0x00203627, 0x000 },
+    { 0x0000002b, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120a3, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x0000002b, 0x00203627, 0x000 },
+    { 0x0000002c, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x0000002c, 0x00803627, 0x000 },
+    { 0x00000029, 0x00203623, 0x000 },
+    { 0x0000002a, 0x00203624, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x0000002b, 0x00203627, 0x000 },
+    { 0x00000000, 0x00311cc4, 0x000 },
+    { 0x0000002c, 0x00803627, 0x000 },
+    { 0x00000022, 0x00203627, 0x000 },
+    { 0x00000023, 0x00203628, 0x000 },
+    { 0x0000001d, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14c00000, 0x2c5 },
+    { 0x00000000, 0x00400000, 0x2c2 },
+    { 0x00000022, 0x00203627, 0x000 },
+    { 0x00000023, 0x00203628, 0x000 },
+    { 0x0000001d, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2c2 },
+    { 0x00000003, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2c5 },
+    { 0x0000002b, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e1, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2c5 },
+    { 0x00000029, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120a1, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2c5 },
+    { 0x0000002c, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e2, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2c5 },
+    { 0x0000002a, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2c5 },
+    { 0x00000000, 0x00600000, 0x5ed },
+    { 0x00000000, 0x00600000, 0x29e },
+    { 0x00000000, 0x00400000, 0x2c7 },
+    { 0x00000000, 0x00600000, 0x29e },
+    { 0x00000000, 0x00600000, 0x5e4 },
+    { 0x00000000, 0x00400000, 0x2c7 },
+    { 0x00000000, 0x00600000, 0x290 },
+    { 0x00000000, 0x00400000, 0x2c7 },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000023, 0x0080222d, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca1, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x003808c5, 0x000 },
+    { 0x00000000, 0x00300841, 0x000 },
+    { 0x00000001, 0x00220a22, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x0000001d, 0x0020222d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x301 },
+    { 0xffffffef, 0x00280621, 0x000 },
+    { 0x0000001a, 0x0020222d, 0x000 },
+    { 0x0000f8e0, 0x00204411, 0x000 },
+    { 0x00000000, 0x00294901, 0x000 },
+    { 0x00000000, 0x00894901, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x97000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00002257, 0x00204411, 0x000 },
+    { 0x00000003, 0xc0484a20, 0x000 },
+    { 0x0000225d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x5c5 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x00000001, 0x40304a20, 0x000 },
+    { 0x00000002, 0xc0304a20, 0x000 },
+    { 0x00000001, 0x00530a22, 0x334 },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000017, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x614 },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x33d },
+    { 0x00000014, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x351 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000016, 0x00604811, 0x35e },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x355 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00404811, 0x349 },
+    { 0x00000028, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x349 },
+    { 0x00002104, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x00000035, 0x00203626, 0x000 },
+    { 0x00000049, 0x00201811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x360 },
+    { 0x00000035, 0x00801a2d, 0x000 },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x00000015, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x376 },
+    { 0x0000001e, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x380 },
+    { 0x00000020, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x38c },
+    { 0x0000000f, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x398 },
+    { 0x00000010, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x398 },
+    { 0x00000006, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x39a },
+    { 0x00000016, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x39f },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x08000000, 0x00290a22, 0x000 },
+    { 0x00000003, 0x40210e20, 0x000 },
+    { 0x0000000c, 0xc0211220, 0x000 },
+    { 0x00080000, 0x00281224, 0x000 },
+    { 0x00000014, 0xc0221620, 0x000 },
+    { 0x00000000, 0x002914a4, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948a2, 0x000 },
+    { 0x0000a1fe, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000015, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x614 },
+    { 0x00000015, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x382 },
+    { 0x0000210e, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x614 },
+    { 0x00000003, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x38e },
+    { 0x00002108, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00404811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000006, 0x00404811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000016, 0x00604811, 0x35e },
+    { 0x00000016, 0x00404811, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x0000001d, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x3b9 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000017, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x614 },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x3ab },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0xbabecafe, 0x00204811, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000004, 0x00404811, 0x000 },
+    { 0x00002170, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000a, 0x00204811, 0x000 },
+    { 0x00000000, 0x00200010, 0x000 },
+    { 0x00000000, 0x14c00000, 0x3be },
+    { 0x8c000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00404811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00003fff, 0x40280a20, 0x000 },
+    { 0x80000000, 0x40280e20, 0x000 },
+    { 0x40000000, 0xc0281220, 0x000 },
+    { 0x00040000, 0x00694622, 0x614 },
+    { 0x00000000, 0x00201410, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x3cc },
+    { 0x00000000, 0xc0401800, 0x3cf },
+    { 0x00003fff, 0xc0281a20, 0x000 },
+    { 0x00040000, 0x00694626, 0x614 },
+    { 0x00000000, 0x00201810, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x3d2 },
+    { 0x00000000, 0xc0401c00, 0x3d5 },
+    { 0x00003fff, 0xc0281e20, 0x000 },
+    { 0x00040000, 0x00694627, 0x614 },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0x002820c5, 0x000 },
+    { 0x00000000, 0x004948e8, 0x000 },
+    { 0xa5800000, 0x00200811, 0x000 },
+    { 0x00002000, 0x00200c11, 0x000 },
+    { 0x83000000, 0x00604411, 0x3fd },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x0000001f, 0xc0210220, 0x000 },
+    { 0x00000000, 0x14c00000, 0x3e2 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0000ffff, 0xc0481220, 0x3ea },
+    { 0xa7800000, 0x00200811, 0x000 },
+    { 0x0000a000, 0x00200c11, 0x000 },
+    { 0x83000000, 0x00604411, 0x3fd },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x83000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00304883, 0x000 },
+    { 0x84000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x1d000000, 0x000 },
+    { 0x83000000, 0x00604411, 0x3fd },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0xa9800000, 0x00200811, 0x000 },
+    { 0x0000c000, 0x00400c11, 0x3e5 },
+    { 0xab800000, 0x00200811, 0x000 },
+    { 0x0000f8e0, 0x00400c11, 0x3e5 },
+    { 0xad800000, 0x00200811, 0x000 },
+    { 0x0000f880, 0x00400c11, 0x3e5 },
+    { 0xb3800000, 0x00200811, 0x000 },
+    { 0x0000f3fc, 0x00400c11, 0x3e5 },
+    { 0xaf800000, 0x00200811, 0x000 },
+    { 0x0000e000, 0x00400c11, 0x3e5 },
+    { 0xb1800000, 0x00200811, 0x000 },
+    { 0x0000f000, 0x00400c11, 0x3e5 },
+    { 0x83000000, 0x00204411, 0x000 },
+    { 0x00002148, 0x00204811, 0x000 },
+    { 0x84000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x1d000000, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00182000, 0xc0304620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0018a000, 0xc0304620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0018c000, 0xc0304620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0018f8e0, 0xc0304620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0018f880, 0xc0304620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0018e000, 0xc0304620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0018f000, 0xc0304620, 0x000 },
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+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
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+    { 0x00000000, 0x0ce00000, 0x444 },
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+    { 0x00000001, 0x00204811, 0x000 },
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+    { 0x00000000, 0x1ac00000, 0x4a9 },
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+    { 0x00000000, 0x00400000, 0x4b2 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0xc0294620, 0x000 },
+    { 0x00000000, 0xc0600000, 0x614 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x4b9 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
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+    { 0x00000000, 0xc0204400, 0x000 },
+    { 0x00000000, 0xc0404810, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x614 },
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+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000003, 0x00333e2f, 0x000 },
+    { 0x00000001, 0x00210221, 0x000 },
+    { 0x00000000, 0x14e00000, 0x4eb },
+    { 0x00000035, 0x00200a2d, 0x000 },
+    { 0x00040000, 0x18e00c11, 0x4da },
+    { 0x00000001, 0x00333e2f, 0x000 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
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+    { 0x0000001c, 0x00203623, 0x000 },
+    { 0xffffe000, 0x00200c11, 0x000 },
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+    { 0x0000002b, 0x00203623, 0x000 },
+    { 0x0000002c, 0x00203623, 0x000 },
+    { 0xf1ffffff, 0x00283a2e, 0x000 },
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+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
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+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x9d000000, 0x00204411, 0x000 },
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+    { 0x96000000, 0x00204411, 0x000 },
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+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x0000001f, 0x00211624, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x00000025, 0x00203623, 0x000 },
+    { 0x00000003, 0x00281e23, 0x000 },
+    { 0x00000008, 0x00222223, 0x000 },
+    { 0xfffff000, 0x00282228, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x00000027, 0x00203628, 0x000 },
+    { 0x00000018, 0x00211e23, 0x000 },
+    { 0x00000028, 0x00203627, 0x000 },
+    { 0x00000002, 0x00221624, 0x000 },
+    { 0x00000000, 0x003014a8, 0x000 },
+    { 0x00000026, 0x00203625, 0x000 },
+    { 0x00000003, 0x00211a24, 0x000 },
+    { 0x10000000, 0x00281a26, 0x000 },
+    { 0xefffffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x004938ce, 0x602 },
+    { 0x00000001, 0x40280a20, 0x000 },
+    { 0x00000006, 0x40280e20, 0x000 },
+    { 0x00000300, 0xc0281220, 0x000 },
+    { 0x00000008, 0x00211224, 0x000 },
+    { 0x00000000, 0xc0201620, 0x000 },
+    { 0x00000000, 0xc0201a20, 0x000 },
+    { 0x00000000, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x541 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00002258, 0x00300a24, 0x000 },
+    { 0x00040000, 0x00694622, 0x614 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00020000, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x549 },
+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x55b },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x549 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00002258, 0x00300a24, 0x000 },
+    { 0x00040000, 0x00694622, 0x614 },
+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x55b },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x54d },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0xc0400000, 0x55b },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x559 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000216d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x554 },
+    { 0x9e000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x557 },
+    { 0x00000000, 0x00401c10, 0x55b },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x55d },
+    { 0x00000000, 0x00600000, 0x5a4 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x56d },
+    { 0x0000a2b7, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x614 },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x0000a2c4, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x56b },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x57d },
+    { 0x0000a2bb, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x614 },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x0000a2c5, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x57b },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x58d },
+    { 0x0000a2bf, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x614 },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x0000a2c6, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x58b },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x0000a2c3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x614 },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x0000a2c7, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x599 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x85000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x0000304a, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x59f },
+    { 0xa4000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0xc0600000, 0x5a4 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x88000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0xff000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000002, 0x00804811, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x5b7 },
+    { 0x00001000, 0x00200811, 0x000 },
+    { 0x00000034, 0x00203622, 0x000 },
+    { 0x00000000, 0x00600000, 0x5bb },
+    { 0x00000000, 0x00600000, 0x5a4 },
+    { 0x98000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0600000, 0x5bb },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000022, 0x00204811, 0x000 },
+    { 0x89000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0xff000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000002, 0x00804811, 0x000 },
+    { 0x0000217a, 0xc0204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0xff000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000002, 0x00804811, 0x000 },
+    { 0x00000000, 0x00600000, 0x5e1 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0xc0204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000016, 0x00604811, 0x35e },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x09800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x614 },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x00000004, 0x00404c11, 0x5dc },
+    { 0x0000001d, 0x00201e2d, 0x000 },
+    { 0x00000004, 0x00291e27, 0x000 },
+    { 0x0000001d, 0x00803627, 0x000 },
+    { 0x0000001d, 0x00201e2d, 0x000 },
+    { 0xfffffffb, 0x00281e27, 0x000 },
+    { 0x0000001d, 0x00803627, 0x000 },
+    { 0x0000001d, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00291e27, 0x000 },
+    { 0x0000001d, 0x00803627, 0x000 },
+    { 0x0000001d, 0x00201e2d, 0x000 },
+    { 0xfffffff7, 0x00281e27, 0x000 },
+    { 0x0000001d, 0x00803627, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000016, 0x00604811, 0x35e },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x01800000, 0x00204811, 0x000 },
+    { 0x00ffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004217f, 0x00604411, 0x614 },
+    { 0x00000000, 0x00200010, 0x000 },
+    { 0x00000000, 0x14c00000, 0x613 },
+    { 0x00000010, 0x00404c11, 0x5f9 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x38c00000, 0x000 },
+    { 0x00000025, 0x00200a2d, 0x000 },
+    { 0x00000026, 0x00200e2d, 0x000 },
+    { 0x00000027, 0x0020122d, 0x000 },
+    { 0x00000028, 0x0020162d, 0x000 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x002f0064, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x612 },
+    { 0x00000003, 0x00281a22, 0x000 },
+    { 0x00000008, 0x00221222, 0x000 },
+    { 0xfffff000, 0x00281224, 0x000 },
+    { 0x00000000, 0x002910c4, 0x000 },
+    { 0x00000027, 0x00403624, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x614 },
+    { 0x9f000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x617 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x2fe },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x19f },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0xc0204411, 0x000 },
+    { 0x00000029, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x0000002c, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000002a, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000002b, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x013304ef, 0x059b0239, 0x000 },
+    { 0x01b00159, 0x0425059b, 0x000 },
+    { 0x021201f6, 0x02390142, 0x000 },
+    { 0x0210022e, 0x0289022a, 0x000 },
+    { 0x03c2059b, 0x059b059b, 0x000 },
+    { 0x05cd05ce, 0x0308059b, 0x000 },
+    { 0x059b05a0, 0x03090329, 0x000 },
+    { 0x0313026b, 0x032b031d, 0x000 },
+    { 0x059b059b, 0x059b059b, 0x000 },
+    { 0x059b052c, 0x059b059b, 0x000 },
+    { 0x03a5059b, 0x04a2032d, 0x000 },
+    { 0x04810433, 0x0423059b, 0x000 },
+    { 0x04bb04ed, 0x042704c8, 0x000 },
+    { 0x043304f4, 0x033a0365, 0x000 },
+    { 0x059b059b, 0x059b059b, 0x000 },
+    { 0x059b059b, 0x059b059b, 0x000 },
+    { 0x059b059b, 0x05b905a2, 0x000 },
+    { 0x059b059b, 0x0007059b, 0x000 },
+    { 0x059b059b, 0x059b059b, 0x000 },
+    { 0x059b059b, 0x059b059b, 0x000 },
+    { 0x03e303d8, 0x03f303f1, 0x000 },
+    { 0x03f903f5, 0x03f703fb, 0x000 },
+    { 0x04070403, 0x040f040b, 0x000 },
+    { 0x04170413, 0x041f041b, 0x000 },
+    { 0x059b059b, 0x059b059b, 0x000 },
+    { 0x059b059b, 0x059b059b, 0x000 },
+    { 0x059b059b, 0x059b059b, 0x000 },
+    { 0x00020600, 0x06190006, 0x000 },
+};
+
+static const u32 R600_pfp_microcode[]={
+0xd40071,
+0xd40072,
+0xca0400,
+0xa00000,
+0x7e828b,
+0x800003,
+0xca0400,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xc41838,
+0xca2400,
+0xca2800,
+0x9581a8,
+0xc41c3a,
+0xc3c000,
+0xca0800,
+0xca0c00,
+0x7c744b,
+0xc20005,
+0x99c000,
+0xc41c3a,
+0x7c744c,
+0xc0fff0,
+0x042c04,
+0x309002,
+0x7d2500,
+0x351402,
+0x7d350b,
+0x255403,
+0x7cd580,
+0x259c03,
+0x95c004,
+0xd5001b,
+0x7eddc1,
+0x7d9d80,
+0xd6801b,
+0xd5801b,
+0xd4401e,
+0xd5401e,
+0xd6401e,
+0xd6801e,
+0xd4801e,
+0xd4c01e,
+0x9783d4,
+0xd5c01e,
+0xca0800,
+0x80001b,
+0xca0c00,
+0xe4011e,
+0xd4001e,
+0x80000d,
+0xc41838,
+0xe4013e,
+0xd4001e,
+0x80000d,
+0xc41838,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca1800,
+0xd4401e,
+0xd5801e,
+0x800054,
+0xd40073,
+0xd4401e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd48019,
+0xd4c018,
+0xd50017,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xe2001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0xd48060,
+0xd4401e,
+0x800002,
+0xd4801e,
+0xca0800,
+0xd48061,
+0xd4401e,
+0x800002,
+0xd4801e,
+0xca0800,
+0xca0c00,
+0xd4401e,
+0xd48016,
+0xd4c016,
+0xd4801e,
+0x8001b9,
+0xd4c01e,
+0xc6083e,
+0xca0c00,
+0xca1000,
+0x948004,
+0xca1400,
+0xe420f3,
+0xd42013,
+0xd56065,
+0xd4e01c,
+0xd5201c,
+0xd5601c,
+0x800002,
+0x062001,
+0xc6083e,
+0xca0c00,
+0xca1000,
+0x9483f7,
+0xca1400,
+0xe420f3,
+0x80007a,
+0xd42013,
+0xc6083e,
+0xca0c00,
+0xca1000,
+0x9883ef,
+0xca1400,
+0xd40064,
+0x80008e,
+0x000000,
+0xc41432,
+0xc6183e,
+0xc4082f,
+0x954005,
+0xc40c30,
+0xd4401e,
+0x800002,
+0xee001e,
+0x9583f5,
+0xc41031,
+0xd44033,
+0xd52065,
+0xd4a01c,
+0xd4e01c,
+0xd5201c,
+0xd40073,
+0xe4015e,
+0xd4001e,
+0x8001b9,
+0x062001,
+0x0a2001,
+0xd60074,
+0xc40836,
+0xc61040,
+0x988007,
+0xcc3835,
+0x95010f,
+0xd4001f,
+0xd46062,
+0x800002,
+0xd42062,
+0xcc1433,
+0x8401bc,
+0xd40070,
+0xd5401e,
+0x800002,
+0xee001e,
+0xca0c00,
+0xca1000,
+0xd4c01a,
+0x8401bc,
+0xd5001a,
+0xcc0443,
+0x35101f,
+0x2c9401,
+0x7d098b,
+0x984005,
+0x7d15cb,
+0xd4001a,
+0x8001b9,
+0xd4006d,
+0x344401,
+0xcc0c44,
+0x98403a,
+0xcc2c46,
+0x958004,
+0xcc0445,
+0x8001b9,
+0xd4001a,
+0xd4c01a,
+0x282801,
+0x8400f3,
+0xcc1003,
+0x98801b,
+0x04380c,
+0x8400f3,
+0xcc1003,
+0x988017,
+0x043808,
+0x8400f3,
+0xcc1003,
+0x988013,
+0x043804,
+0x8400f3,
+0xcc1003,
+0x988014,
+0xcc1047,
+0x9a8009,
+0xcc1448,
+0x9840da,
+0xd4006d,
+0xcc1844,
+0xd5001a,
+0xd5401a,
+0x8000cc,
+0xd5801a,
+0x96c0d3,
+0xd4006d,
+0x8001b9,
+0xd4006e,
+0x9ac003,
+0xd4006d,
+0xd4006e,
+0x800002,
+0xec007f,
+0x9ac0ca,
+0xd4006d,
+0x8001b9,
+0xd4006e,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0x7d9103,
+0x7dd583,
+0x7d190c,
+0x35cc1f,
+0x35701f,
+0x7cf0cb,
+0x7cd08b,
+0x880000,
+0x7e8e8b,
+0x95c004,
+0xd4006e,
+0x8001b9,
+0xd4001a,
+0xd4c01a,
+0xcc0803,
+0xcc0c03,
+0xcc1003,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0xcc2403,
+0xcc2803,
+0x35c41f,
+0x36b01f,
+0x7c704b,
+0x34f01f,
+0x7c704b,
+0x35701f,
+0x7c704b,
+0x7d8881,
+0x7dccc1,
+0x7e5101,
+0x7e9541,
+0x7c9082,
+0x7cd4c2,
+0x7c848b,
+0x9ac003,
+0x7c8c8b,
+0x2c8801,
+0x98809c,
+0xd4006d,
+0x98409a,
+0xd4006e,
+0xcc0847,
+0xcc0c48,
+0xcc1044,
+0xd4801a,
+0xd4c01a,
+0x800104,
+0xd5001a,
+0xcc0832,
+0xd40032,
+0x9482d8,
+0xca0c00,
+0xd4401e,
+0x800002,
+0xd4001e,
+0xe4011e,
+0xd4001e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd4401e,
+0xca1400,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xd5401e,
+0xd54034,
+0x800002,
+0xee001e,
+0x280404,
+0xe2001a,
+0xe2001a,
+0xd4401a,
+0xca3800,
+0xcc0803,
+0xcc0c03,
+0xcc0c03,
+0xcc0c03,
+0x9882bc,
+0x000000,
+0x8401bc,
+0xd7806f,
+0x800002,
+0xee001f,
+0xca0400,
+0xc2ff00,
+0xcc0834,
+0xc13fff,
+0x7c74cb,
+0x7cc90b,
+0x7d010f,
+0x9902af,
+0x7c738b,
+0x8401bc,
+0xd7806f,
+0x800002,
+0xee001f,
+0xca0800,
+0x281900,
+0x7d898b,
+0x958014,
+0x281404,
+0xca0c00,
+0xca1000,
+0xca1c00,
+0xca2400,
+0xe2001f,
+0xd4c01a,
+0xd5001a,
+0xd5401a,
+0xcc1803,
+0xcc2c03,
+0xcc2c03,
+0xcc2c03,
+0x7da58b,
+0x7d9c47,
+0x984296,
+0x000000,
+0x800164,
+0xd4c01a,
+0xd4401e,
+0xd4801e,
+0x800002,
+0xee001e,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0x248c06,
+0x0ccc06,
+0x98c006,
+0xcc1049,
+0x990004,
+0xd40071,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xd4801e,
+0x800002,
+0xee001e,
+0xca0800,
+0xca0c00,
+0x34d018,
+0x251001,
+0x95001f,
+0xc17fff,
+0xca1000,
+0xca1400,
+0xca1800,
+0xd4801d,
+0xd4c01d,
+0x7db18b,
+0xc14202,
+0xc2c001,
+0xd5801d,
+0x34dc0e,
+0x7d5d4c,
+0x7f734c,
+0xd7401e,
+0xd5001e,
+0xd5401e,
+0xc14200,
+0xc2c000,
+0x099c01,
+0x31dc10,
+0x7f5f4c,
+0x7f734c,
+0x7d8380,
+0xd5806f,
+0xd58066,
+0xd7401e,
+0xec005e,
+0xc82402,
+0x8001b9,
+0xd60074,
+0xd4401e,
+0xd4801e,
+0xd4c01e,
+0x800002,
+0xee001e,
+0x800002,
+0xee001f,
+0xd4001f,
+0x800002,
+0xd4001f,
+0xd4001f,
+0x880000,
+0xd4001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x010174,
+0x02017b,
+0x030090,
+0x040080,
+0x050005,
+0x060040,
+0x070033,
+0x08012f,
+0x090047,
+0x0a0037,
+0x1001b7,
+0x1700a4,
+0x22013d,
+0x23014c,
+0x2000b5,
+0x240128,
+0x27004e,
+0x28006b,
+0x2a0061,
+0x2b0053,
+0x2f0066,
+0x320088,
+0x340182,
+0x3c0159,
+0x3f0073,
+0x41018f,
+0x440131,
+0x550176,
+0x56017d,
+0x60000c,
+0x610035,
+0x620039,
+0x630039,
+0x640039,
+0x650039,
+0x660039,
+0x670039,
+0x68003b,
+0x690042,
+0x6a0049,
+0x6b0049,
+0x6c0049,
+0x6d0049,
+0x6e0049,
+0x6f0049,
+0x7301b7,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+0x000007,
+};
+
+static const u32 RV610_cp_microcode[][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00000000, 0x00e00000, 0x000 },
+    { 0x00010000, 0xc0294620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x00000000, 0x00600000, 0x631 },
+    { 0x00000000, 0x00600000, 0x645 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000f00, 0x00281622, 0x000 },
+    { 0x00000008, 0x00211625, 0x000 },
+    { 0x00000018, 0x00203625, 0x000 },
+    { 0x8d000000, 0x00204411, 0x000 },
+    { 0x00000004, 0x002f0225, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x018 },
+    { 0x00412000, 0x00404811, 0x019 },
+    { 0x00422000, 0x00204811, 0x000 },
+    { 0x8e000000, 0x00204411, 0x000 },
+    { 0x00000028, 0x00204a2d, 0x000 },
+    { 0x90000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x0000000c, 0x00211622, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000019, 0x00211a22, 0x000 },
+    { 0x00000004, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002914c5, 0x000 },
+    { 0x00000019, 0x00203625, 0x000 },
+    { 0x00000000, 0x003a1402, 0x000 },
+    { 0x00000016, 0x00211625, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0xfffffffc, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002914a3, 0x000 },
+    { 0x00000017, 0x00203625, 0x000 },
+    { 0x00008000, 0x00280e22, 0x000 },
+    { 0x00000007, 0x00220e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x20000000, 0x00280e22, 0x000 },
+    { 0x00000006, 0x00210e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00220222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x038 },
+    { 0x00000000, 0x2ee00000, 0x035 },
+    { 0x00000000, 0x2ce00000, 0x037 },
+    { 0x00000000, 0x00400e2d, 0x039 },
+    { 0x00000008, 0x00200e2d, 0x000 },
+    { 0x00000009, 0x0040122d, 0x046 },
+    { 0x00000001, 0x00400e2d, 0x039 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x03e },
+    { 0x00000008, 0x00401c11, 0x041 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x0000000f, 0x00281e27, 0x000 },
+    { 0x00000003, 0x00221e27, 0x000 },
+    { 0x7fc00000, 0x00281a23, 0x000 },
+    { 0x00000014, 0x00211a26, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000008, 0x00221a26, 0x000 },
+    { 0x00000000, 0x00290cc7, 0x000 },
+    { 0x00000027, 0x00203624, 0x000 },
+    { 0x00007f00, 0x00281221, 0x000 },
+    { 0x00001400, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04b },
+    { 0x00000001, 0x00290e23, 0x000 },
+    { 0x0000000e, 0x00203623, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfff80000, 0x00294a23, 0x000 },
+    { 0x00000000, 0x003a2c02, 0x000 },
+    { 0x00000002, 0x00220e2b, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x0000000f, 0x00203623, 0x000 },
+    { 0x00001fff, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00204a2d, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000029, 0x00200e2d, 0x000 },
+    { 0x060a0200, 0x00294a23, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x061 },
+    { 0x00000000, 0x2ee00000, 0x05f },
+    { 0x00000000, 0x2ce00000, 0x05e },
+    { 0x00000000, 0x00400e2d, 0x062 },
+    { 0x00000001, 0x00400e2d, 0x062 },
+    { 0x0000000a, 0x00200e2d, 0x000 },
+    { 0x0000000b, 0x0040122d, 0x06a },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x7fc00000, 0x00281623, 0x000 },
+    { 0x00000014, 0x00211625, 0x000 },
+    { 0x00000001, 0x00331625, 0x000 },
+    { 0x80000000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00290ca3, 0x000 },
+    { 0x3ffffc00, 0x00290e23, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x06d },
+    { 0x00000100, 0x00401c11, 0x070 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x000000f0, 0x00281e27, 0x000 },
+    { 0x00000004, 0x00221e27, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0xfffff0ff, 0x00281a30, 0x000 },
+    { 0x0000a028, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e6, 0x000 },
+    { 0x0000a018, 0x00204411, 0x000 },
+    { 0x3fffffff, 0x00284a23, 0x000 },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000030, 0x0020162d, 0x000 },
+    { 0x00000002, 0x00291625, 0x000 },
+    { 0x00000030, 0x00203625, 0x000 },
+    { 0x00000025, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a3, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x083 },
+    { 0x00000026, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a4, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x084 },
+    { 0x00000000, 0x00400000, 0x08a },
+    { 0x00000025, 0x00203623, 0x000 },
+    { 0x00000026, 0x00203624, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x08a },
+    { 0x00000000, 0x00600000, 0x668 },
+    { 0x00000000, 0x00600000, 0x65c },
+    { 0x00000002, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x08d },
+    { 0x00000012, 0xc0403620, 0x093 },
+    { 0x00000000, 0x2ee00000, 0x091 },
+    { 0x00000000, 0x2ce00000, 0x090 },
+    { 0x00000002, 0x00400e2d, 0x092 },
+    { 0x00000003, 0x00400e2d, 0x092 },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000012, 0x00203623, 0x000 },
+    { 0x00000003, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x098 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x0a0 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x2ee00000, 0x09e },
+    { 0x00000000, 0x2ce00000, 0x09d },
+    { 0x00000002, 0x00400e2d, 0x09f },
+    { 0x00000003, 0x00400e2d, 0x09f },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x003f0000, 0x00280e23, 0x000 },
+    { 0x00000010, 0x00210e23, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x0000001e, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0a7 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x0000001f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0aa },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000008, 0x00210e2b, 0x000 },
+    { 0x0000007f, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0e1 },
+    { 0x00000000, 0x27000000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b3 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00221e30, 0x000 },
+    { 0x99800000, 0x00204411, 0x000 },
+    { 0x00000004, 0x0020122d, 0x000 },
+    { 0x00000008, 0x00221224, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00291ce4, 0x000 },
+    { 0x00000000, 0x00604807, 0x12f },
+    { 0x9b000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x9c000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x0033146f, 0x000 },
+    { 0x00000001, 0x00333e23, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00203c05, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e007, 0x00204411, 0x000 },
+    { 0x0000000f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0cb },
+    { 0x00f8ff08, 0x00204811, 0x000 },
+    { 0x98000000, 0x00404811, 0x0dc },
+    { 0x000000f0, 0x00280e22, 0x000 },
+    { 0x000000a0, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x0da },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d5 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d4 },
+    { 0x00003f00, 0x00400c11, 0x0d6 },
+    { 0x00001f00, 0x00400c11, 0x0d6 },
+    { 0x00000f00, 0x00200c11, 0x000 },
+    { 0x00380009, 0x00294a23, 0x000 },
+    { 0x3f000000, 0x00280e2b, 0x000 },
+    { 0x00000002, 0x00220e23, 0x000 },
+    { 0x00000007, 0x00494a23, 0x0dc },
+    { 0x00380f09, 0x00204811, 0x000 },
+    { 0x68000007, 0x00204811, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000a202, 0x00204411, 0x000 },
+    { 0x00ff0000, 0x00280e22, 0x000 },
+    { 0x00000080, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00200e2d, 0x000 },
+    { 0x00000026, 0x0020122d, 0x000 },
+    { 0x00000000, 0x002f0083, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0ea },
+    { 0x00000000, 0x00600000, 0x662 },
+    { 0x00000000, 0x00400000, 0x0eb },
+    { 0x00000000, 0x00600000, 0x665 },
+    { 0x00000007, 0x0020222d, 0x000 },
+    { 0x00000005, 0x00220e22, 0x000 },
+    { 0x00100000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x000000ef, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000003, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x0f8 },
+    { 0x0000000b, 0x00210228, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0f8 },
+    { 0x00000400, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000001c, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0fd },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000001e, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x10b },
+    { 0x0000a30f, 0x00204411, 0x000 },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x104 },
+    { 0xffffffff, 0x00404811, 0x10b },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x107 },
+    { 0x0000ffff, 0x00404811, 0x10b },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x10a },
+    { 0x000000ff, 0x00404811, 0x10b },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0002c400, 0x00204411, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x112 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000018, 0x40224a20, 0x000 },
+    { 0x00000010, 0xc0424a20, 0x114 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000000a, 0x00201011, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x11b },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00531224, 0x117 },
+    { 0xffbfffff, 0x00283a2e, 0x000 },
+    { 0x0000001b, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x12e },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0x00000018, 0x00220e30, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e00e, 0x00204411, 0x000 },
+    { 0x07f8ff08, 0x00204811, 0x000 },
+    { 0x00000000, 0x00294a23, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x00800000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68d },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x68c },
+    { 0x00000004, 0x00404c11, 0x135 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x0000001c, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x13c },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40280620, 0x000 },
+    { 0x00000010, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x00341461, 0x000 },
+    { 0x00000000, 0x00741882, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x147 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0681a20, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x158 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000001, 0x00300a2f, 0x000 },
+    { 0x00000001, 0x00210a22, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600000, 0x18f },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00202c08, 0x000 },
+    { 0x00000000, 0x00202411, 0x000 },
+    { 0x00000000, 0x00202811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000002, 0x00221e29, 0x000 },
+    { 0x00000000, 0x007048eb, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000001, 0x40330620, 0x000 },
+    { 0x00000000, 0xc0302409, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x181 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x186 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x186 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000001, 0x00530621, 0x182 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0604800, 0x197 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000011, 0x0020062d, 0x000 },
+    { 0x00000000, 0x0078042a, 0x2fb },
+    { 0x00000000, 0x00202809, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x174 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x194 },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x46000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x19b },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00804811, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40281620, 0x000 },
+    { 0x00000010, 0xc0811a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000008, 0x00221e30, 0x000 },
+    { 0x00000029, 0x00201a2d, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfffbff09, 0x00204811, 0x000 },
+    { 0x0000000f, 0x0020222d, 0x000 },
+    { 0x00001fff, 0x00294a28, 0x000 },
+    { 0x00000006, 0x0020222d, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000100, 0x00201811, 0x000 },
+    { 0x00000008, 0x00621e28, 0x12f },
+    { 0x00000008, 0x00822228, 0x000 },
+    { 0x0002c000, 0x00204411, 0x000 },
+    { 0x00000015, 0x00600e2d, 0x1bd },
+    { 0x00000016, 0x00600e2d, 0x1bd },
+    { 0x0000c008, 0x00204411, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1b9 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x39000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00804802, 0x000 },
+    { 0x00000018, 0x00202e2d, 0x000 },
+    { 0x00000000, 0x003b0d63, 0x000 },
+    { 0x00000008, 0x00224a23, 0x000 },
+    { 0x00000010, 0x00224a23, 0x000 },
+    { 0x00000018, 0x00224a23, 0x000 },
+    { 0x00000000, 0x00804803, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000007, 0x0021062f, 0x000 },
+    { 0x00000013, 0x00200a2d, 0x000 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000ffff, 0x40282220, 0x000 },
+    { 0x0000000f, 0x00262228, 0x000 },
+    { 0x00000010, 0x40212620, 0x000 },
+    { 0x0000000f, 0x00262629, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1e0 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000081, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000080, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1dc },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1d8 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000001f, 0x00280a22, 0x000 },
+    { 0x0000001f, 0x00282a2a, 0x000 },
+    { 0x00000001, 0x00530621, 0x1d1 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000002, 0x00304a2f, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x00301e2f, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1e5 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x0000000f, 0x00260e23, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000000f, 0x00261224, 0x000 },
+    { 0x00000000, 0x00201411, 0x000 },
+    { 0x00000000, 0x00601811, 0x2bb },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022b, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1f8 },
+    { 0x00000010, 0x00221628, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a29, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000010, 0x00221623, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a24, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x00731503, 0x205 },
+    { 0x00000000, 0x00201805, 0x000 },
+    { 0x00000000, 0x00731524, 0x205 },
+    { 0x00000000, 0x002d14c5, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00000000, 0x00202003, 0x000 },
+    { 0x00000000, 0x00802404, 0x000 },
+    { 0x0000000f, 0x00210225, 0x000 },
+    { 0x00000000, 0x14c00000, 0x68c },
+    { 0x00000000, 0x002b1405, 0x000 },
+    { 0x00000001, 0x00901625, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00294a22, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a21, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000ffff, 0x40281220, 0x000 },
+    { 0x00000010, 0xc0211a20, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211620, 0x000 },
+    { 0x00000000, 0x00741465, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00000001, 0x00330621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x219 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x212 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x645 },
+    { 0x00000000, 0x0040040f, 0x213 },
+    { 0x00000000, 0x00600000, 0x631 },
+    { 0x00000000, 0x00600000, 0x645 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00000000, 0x00600000, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x232 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x236 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x236 },
+    { 0x00000000, 0xc0404800, 0x233 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x00600411, 0x2fb },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x631 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000018, 0x40210a20, 0x000 },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x24c },
+    { 0x00000014, 0x0020222d, 0x000 },
+    { 0x00080101, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x251 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000010, 0x00600411, 0x315 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00000000, 0x00600000, 0x27c },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000001, 0x00211e27, 0x000 },
+    { 0x00000000, 0x14e00000, 0x26a },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x0000ffff, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00341c27, 0x000 },
+    { 0x00000000, 0x12c00000, 0x25f },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e5, 0x000 },
+    { 0x00000000, 0x08c00000, 0x262 },
+    { 0x00000000, 0x00201407, 0x000 },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00211e27, 0x000 },
+    { 0x00000000, 0x00341c47, 0x000 },
+    { 0x00000000, 0x12c00000, 0x267 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x08c00000, 0x26a },
+    { 0x00000000, 0x00201807, 0x000 },
+    { 0x00000000, 0x00600000, 0x2c1 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000000, 0x00342023, 0x000 },
+    { 0x00000000, 0x12c00000, 0x272 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x271 },
+    { 0x00000016, 0x00404811, 0x276 },
+    { 0x00000018, 0x00404811, 0x276 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x275 },
+    { 0x00000017, 0x00404811, 0x276 },
+    { 0x00000019, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00604411, 0x2e9 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x256 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000010, 0x40210620, 0x000 },
+    { 0x0000ffff, 0xc0280a20, 0x000 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0881a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x00000000, 0x00600000, 0x631 },
+    { 0x00000000, 0xc0600000, 0x2a3 },
+    { 0x00000005, 0x00200a2d, 0x000 },
+    { 0x00000008, 0x00220a22, 0x000 },
+    { 0x0000002b, 0x00201a2d, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00007000, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00311ce6, 0x000 },
+    { 0x0000002a, 0x00201a2d, 0x000 },
+    { 0x0000000c, 0x00221a26, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x06e00000, 0x292 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x0000002b, 0x00203623, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00691ce2, 0x12f },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x29d },
+    { 0x00000001, 0x00333e2f, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000001c, 0x00403627, 0x000 },
+    { 0x0000000c, 0xc0220a20, 0x000 },
+    { 0x00000029, 0x00203622, 0x000 },
+    { 0x00000028, 0xc0403620, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000009, 0x00204811, 0x000 },
+    { 0xa1000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce3, 0x000 },
+    { 0x00000021, 0x00203627, 0x000 },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce4, 0x000 },
+    { 0x00000022, 0x00203627, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120a3, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x00000023, 0x00203627, 0x000 },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x00000024, 0x00803627, 0x000 },
+    { 0x00000021, 0x00203623, 0x000 },
+    { 0x00000022, 0x00203624, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000023, 0x00203627, 0x000 },
+    { 0x00000000, 0x00311cc4, 0x000 },
+    { 0x00000024, 0x00803627, 0x000 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14c00000, 0x2dc },
+    { 0x00000000, 0x00400000, 0x2d9 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2d9 },
+    { 0x00000003, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2dc },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e1, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120a1, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e2, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000000, 0x00600000, 0x668 },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00600000, 0x65f },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2a7 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x0000001a, 0x00201e2d, 0x000 },
+    { 0x0000001b, 0x0080222d, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca1, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x003808c5, 0x000 },
+    { 0x00000000, 0x00300841, 0x000 },
+    { 0x00000001, 0x00220a22, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000017, 0x0020222d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x318 },
+    { 0xffffffef, 0x00280621, 0x000 },
+    { 0x00000014, 0x0020222d, 0x000 },
+    { 0x0000f8e0, 0x00204411, 0x000 },
+    { 0x00000000, 0x00294901, 0x000 },
+    { 0x00000000, 0x00894901, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x97000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00002257, 0x00204411, 0x000 },
+    { 0x00000003, 0xc0484a20, 0x000 },
+    { 0x0000225d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x645 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x00000001, 0x40304a20, 0x000 },
+    { 0x00000002, 0xc0304a20, 0x000 },
+    { 0x00000001, 0x00530a22, 0x34b },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x354 },
+    { 0x00000014, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x364 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00604802, 0x36e },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x36a },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35f },
+    { 0x00000028, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5c0 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35f },
+    { 0x0000002c, 0x00203626, 0x000 },
+    { 0x00000049, 0x00201811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x370 },
+    { 0x0000002c, 0x00801a2d, 0x000 },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x00000015, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x386 },
+    { 0x00000006, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3b1 },
+    { 0x00000016, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3b5 },
+    { 0x00000020, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x39c },
+    { 0x0000000f, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a8 },
+    { 0x00000010, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a8 },
+    { 0x0000001e, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x390 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x08000000, 0x00290a22, 0x000 },
+    { 0x00000003, 0x40210e20, 0x000 },
+    { 0x0000000c, 0xc0211220, 0x000 },
+    { 0x00080000, 0x00281224, 0x000 },
+    { 0x00000014, 0xc0221620, 0x000 },
+    { 0x00000000, 0x002914a4, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948a2, 0x000 },
+    { 0x0000a1fe, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000015, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x392 },
+    { 0x0000210e, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000017, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000003, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x39e },
+    { 0x00002108, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x80000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000010, 0x00204811, 0x000 },
+    { 0x00000000, 0x00200010, 0x000 },
+    { 0x00000000, 0x14c00000, 0x3ae },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000006, 0x00404811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x0000001d, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x3ce },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x3c0 },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0xbabecafe, 0x00204811, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000004, 0x00404811, 0x000 },
+    { 0x00002170, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000a, 0x00204811, 0x000 },
+    { 0x00000000, 0x00200010, 0x000 },
+    { 0x00000000, 0x14c00000, 0x3d3 },
+    { 0x8c000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00404811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00003fff, 0x40280a20, 0x000 },
+    { 0x80000000, 0x40280e20, 0x000 },
+    { 0x40000000, 0xc0281220, 0x000 },
+    { 0x00040000, 0x00694622, 0x68d },
+    { 0x00000000, 0x00201410, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x3e1 },
+    { 0x00000000, 0xc0401800, 0x3e4 },
+    { 0x00003fff, 0xc0281a20, 0x000 },
+    { 0x00040000, 0x00694626, 0x68d },
+    { 0x00000000, 0x00201810, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x3e7 },
+    { 0x00000000, 0xc0401c00, 0x3ea },
+    { 0x00003fff, 0xc0281e20, 0x000 },
+    { 0x00040000, 0x00694627, 0x68d },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0x002820c5, 0x000 },
+    { 0x00000000, 0x004948e8, 0x000 },
+    { 0xa5800000, 0x00200811, 0x000 },
+    { 0x00002000, 0x00200c11, 0x000 },
+    { 0x83000000, 0x00604411, 0x412 },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x0000001f, 0xc0210220, 0x000 },
+    { 0x00000000, 0x14c00000, 0x3f7 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0000ffff, 0xc0481220, 0x3ff },
+    { 0xa7800000, 0x00200811, 0x000 },
+    { 0x0000a000, 0x00200c11, 0x000 },
+    { 0x83000000, 0x00604411, 0x412 },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x83000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00304883, 0x000 },
+    { 0x84000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0x1d000000, 0x000 },
+    { 0x83000000, 0x00604411, 0x412 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0xa9800000, 0x00200811, 0x000 },
+    { 0x0000c000, 0x00400c11, 0x3fa },
+    { 0xab800000, 0x00200811, 0x000 },
+    { 0x0000f8e0, 0x00400c11, 0x3fa },
+    { 0xad800000, 0x00200811, 0x000 },
+    { 0x0000f880, 0x00400c11, 0x3fa },
+    { 0xb3800000, 0x00200811, 0x000 },
+    { 0x0000f3fc, 0x00400c11, 0x3fa },
+    { 0xaf800000, 0x00200811, 0x000 },
+    { 0x0000e000, 0x00400c11, 0x3fa },
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+    { 0x0000f000, 0x00400c11, 0x3fa },
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+    { 0xefffffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x004938ce, 0x67b },
+    { 0x00000001, 0x40280a20, 0x000 },
+    { 0x00000006, 0x40280e20, 0x000 },
+    { 0x00000300, 0xc0281220, 0x000 },
+    { 0x00000008, 0x00211224, 0x000 },
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+    { 0x00000000, 0x14c00000, 0x566 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
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+    { 0x00040000, 0x00694622, 0x68d },
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+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x57c },
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+    { 0x00000000, 0x0cc00000, 0x56e },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
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+    { 0x00040000, 0x00694622, 0x68d },
+    { 0x00000000, 0xc0201c10, 0x000 },
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+    { 0x00000000, 0x00401c10, 0x57c },
+    { 0x00000000, 0xc0200000, 0x000 },
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+    { 0x00000000, 0x00600000, 0x5c9 },
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+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x68d },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
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+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5a0 },
+    { 0x0000a2bb, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x68d },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
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+    { 0x00000000, 0x00e00000, 0x59e },
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+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5b1 },
+    { 0x0000a2bf, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x68d },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0000a2c6, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5af },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x0000a2c3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x68d },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0000a2c7, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5be },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x85000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x0000304a, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x5c4 },
+    { 0xa4000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0xc0600000, 0x5c9 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000002c, 0x00203621, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5d0 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000030, 0x00403621, 0x5e3 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x5e3 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a092, 0x00604411, 0x68d },
+    { 0x00000031, 0x00203630, 0x000 },
+    { 0x0004a093, 0x00604411, 0x68d },
+    { 0x00000032, 0x00203630, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x68d },
+    { 0x00000033, 0x00203630, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x68d },
+    { 0x00000034, 0x00203630, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x68d },
+    { 0x00000035, 0x00203630, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x68d },
+    { 0x00000036, 0x00203630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x88000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000001, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x62c },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x62c },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x605 },
+    { 0x0000a092, 0x00204411, 0x000 },
+    { 0x00000031, 0x00204a2d, 0x000 },
+    { 0x0000a093, 0x00204411, 0x000 },
+    { 0x00000032, 0x00204a2d, 0x000 },
+    { 0x0000a2b6, 0x00204411, 0x000 },
+    { 0x00000033, 0x00204a2d, 0x000 },
+    { 0x0000a2ba, 0x00204411, 0x000 },
+    { 0x00000034, 0x00204a2d, 0x000 },
+    { 0x0000a2be, 0x00204411, 0x000 },
+    { 0x00000035, 0x00204a2d, 0x000 },
+    { 0x0000a2c2, 0x00204411, 0x000 },
+    { 0x00000036, 0x00204a2d, 0x000 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x000001ff, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x62b },
+    { 0x00000000, 0x00210221, 0x000 },
+    { 0x00000000, 0x14c00000, 0x60e },
+    { 0x0004a003, 0x00604411, 0x68d },
+    { 0x0000a003, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x14c00000, 0x613 },
+    { 0x0004a010, 0x00604411, 0x68d },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x62b },
+    { 0x0004a011, 0x00604411, 0x68d },
+    { 0x0000a011, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a012, 0x00604411, 0x68d },
+    { 0x0000a012, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a013, 0x00604411, 0x68d },
+    { 0x0000a013, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a014, 0x00604411, 0x68d },
+    { 0x0000a014, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a015, 0x00604411, 0x68d },
+    { 0x0000a015, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a016, 0x00604411, 0x68d },
+    { 0x0000a016, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a017, 0x00604411, 0x68d },
+    { 0x0000a017, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0000002c, 0x0080062d, 0x000 },
+    { 0xff000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000002, 0x00804811, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x63d },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000002, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x63b },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x00001000, 0x00200811, 0x000 },
+    { 0x0000002b, 0x00203622, 0x000 },
+    { 0x00000000, 0x00600000, 0x641 },
+    { 0x00000000, 0x00600000, 0x5c9 },
+    { 0x98000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0600000, 0x641 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000022, 0x00204811, 0x000 },
+    { 0x89000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00404811, 0x62d },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x62d },
+    { 0x00000000, 0x00600000, 0x65c },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0xc0204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x09800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68d },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x00000004, 0x00404c11, 0x656 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000004, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffffb, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffff7, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x01800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68d },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x68c },
+    { 0x00000010, 0x00404c11, 0x672 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x38c00000, 0x000 },
+    { 0x0000001d, 0x00200a2d, 0x000 },
+    { 0x0000001e, 0x00200e2d, 0x000 },
+    { 0x0000001f, 0x0020122d, 0x000 },
+    { 0x00000020, 0x0020162d, 0x000 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x002f0064, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x68b },
+    { 0x00000003, 0x00281a22, 0x000 },
+    { 0x00000008, 0x00221222, 0x000 },
+    { 0xfffff000, 0x00281224, 0x000 },
+    { 0x00000000, 0x002910c4, 0x000 },
+    { 0x0000001f, 0x00403624, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x68d },
+    { 0x9f000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x690 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x692 },
+    { 0x9e000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x695 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0xc0204411, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000024, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000022, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x01420502, 0x05c00250, 0x000 },
+    { 0x01c30168, 0x043f05c0, 0x000 },
+    { 0x02250209, 0x02500151, 0x000 },
+    { 0x02230245, 0x02a00241, 0x000 },
+    { 0x03d705c0, 0x05c005c0, 0x000 },
+    { 0x0649064a, 0x031f05c0, 0x000 },
+    { 0x05c005c5, 0x03200340, 0x000 },
+    { 0x032a0282, 0x03420334, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c00551, 0x05c005c0, 0x000 },
+    { 0x03ba05c0, 0x04bb0344, 0x000 },
+    { 0x049a0450, 0x043d05c0, 0x000 },
+    { 0x04d005c0, 0x044104dd, 0x000 },
+    { 0x04500507, 0x03510375, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c005c0, 0x063f05c7, 0x000 },
+    { 0x05c005c0, 0x000705c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x03f803ed, 0x04080406, 0x000 },
+    { 0x040e040a, 0x040c0410, 0x000 },
+    { 0x041c0418, 0x04240420, 0x000 },
+    { 0x042c0428, 0x04340430, 0x000 },
+    { 0x05c005c0, 0x043805c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x00020679, 0x06970006, 0x000 },
+};
+
+static const u32 RV610_pfp_microcode[]={
+0xca0400,
+0xa00000,
+0x7e828b,
+0x7c038b,
+0x8001b8,
+0x7c038b,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xc41838,
+0xca2400,
+0xca2800,
+0x9581a8,
+0xc41c3a,
+0xc3c000,
+0xca0800,
+0xca0c00,
+0x7c744b,
+0xc20005,
+0x99c000,
+0xc41c3a,
+0x7c744c,
+0xc0fff0,
+0x042c04,
+0x309002,
+0x7d2500,
+0x351402,
+0x7d350b,
+0x255403,
+0x7cd580,
+0x259c03,
+0x95c004,
+0xd5001b,
+0x7eddc1,
+0x7d9d80,
+0xd6801b,
+0xd5801b,
+0xd4401e,
+0xd5401e,
+0xd6401e,
+0xd6801e,
+0xd4801e,
+0xd4c01e,
+0x9783d3,
+0xd5c01e,
+0xca0800,
+0x80001a,
+0xca0c00,
+0xe4011e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xe4013e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca1800,
+0xd4401e,
+0xd5801e,
+0x800053,
+0xd40075,
+0xd4401e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd48019,
+0xd4c018,
+0xd50017,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xe2001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0xd48060,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xd48061,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xca0c00,
+0xd4401e,
+0xd48016,
+0xd4c016,
+0xd4801e,
+0x8001b8,
+0xd4c01e,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x948004,
+0xca1400,
+0xe420f3,
+0xd42013,
+0xd56065,
+0xd4e01c,
+0xd5201c,
+0xd5601c,
+0x800000,
+0x062001,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9483f7,
+0xca1400,
+0xe420f3,
+0x800079,
+0xd42013,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9883ef,
+0xca1400,
+0xd40064,
+0x80008d,
+0x000000,
+0xc41432,
+0xc61843,
+0xc4082f,
+0x954005,
+0xc40c30,
+0xd4401e,
+0x800000,
+0xee001e,
+0x9583f5,
+0xc41031,
+0xd44033,
+0xd52065,
+0xd4a01c,
+0xd4e01c,
+0xd5201c,
+0xe4015e,
+0xd4001e,
+0x800000,
+0x062001,
+0xca1800,
+0x0a2001,
+0xd60076,
+0xc40836,
+0x988007,
+0xc61045,
+0x950110,
+0xd4001f,
+0xd46062,
+0x800000,
+0xd42062,
+0xcc3835,
+0xcc1433,
+0x8401bb,
+0xd40072,
+0xd5401e,
+0x800000,
+0xee001e,
+0xe2001a,
+0x8401bb,
+0xe2001a,
+0xcc104b,
+0xcc0447,
+0x2c9401,
+0x7d098b,
+0x984005,
+0x7d15cb,
+0xd4001a,
+0x8001b8,
+0xd4006d,
+0x344401,
+0xcc0c48,
+0x98403a,
+0xcc2c4a,
+0x958004,
+0xcc0449,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0x282801,
+0x8400f0,
+0xcc1003,
+0x98801b,
+0x04380c,
+0x8400f0,
+0xcc1003,
+0x988017,
+0x043808,
+0x8400f0,
+0xcc1003,
+0x988013,
+0x043804,
+0x8400f0,
+0xcc1003,
+0x988014,
+0xcc104c,
+0x9a8009,
+0xcc144d,
+0x9840dc,
+0xd4006d,
+0xcc1848,
+0xd5001a,
+0xd5401a,
+0x8000c9,
+0xd5801a,
+0x96c0d5,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0x9ac003,
+0xd4006d,
+0xd4006e,
+0x800000,
+0xec007f,
+0x9ac0cc,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0x7d9103,
+0x7dd583,
+0x7d190c,
+0x35cc1f,
+0x35701f,
+0x7cf0cb,
+0x7cd08b,
+0x880000,
+0x7e8e8b,
+0x95c004,
+0xd4006e,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0xcc0803,
+0xcc0c03,
+0xcc1003,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0xcc2403,
+0xcc2803,
+0x35c41f,
+0x36b01f,
+0x7c704b,
+0x34f01f,
+0x7c704b,
+0x35701f,
+0x7c704b,
+0x7d8881,
+0x7dccc1,
+0x7e5101,
+0x7e9541,
+0x7c9082,
+0x7cd4c2,
+0x7c848b,
+0x9ac003,
+0x7c8c8b,
+0x2c8801,
+0x98809e,
+0xd4006d,
+0x98409c,
+0xd4006e,
+0xcc084c,
+0xcc0c4d,
+0xcc1048,
+0xd4801a,
+0xd4c01a,
+0x800101,
+0xd5001a,
+0xcc0832,
+0xd40032,
+0x9482d9,
+0xca0c00,
+0xd4401e,
+0x800000,
+0xd4001e,
+0xe4011e,
+0xd4001e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd4401e,
+0xca1400,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xd5401e,
+0xd54034,
+0x800000,
+0xee001e,
+0x280404,
+0xe2001a,
+0xe2001a,
+0xd4401a,
+0xca3800,
+0xcc0803,
+0xcc0c03,
+0xcc0c03,
+0xcc0c03,
+0x9882bd,
+0x000000,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0400,
+0xc2ff00,
+0xcc0834,
+0xc13fff,
+0x7c74cb,
+0x7cc90b,
+0x7d010f,
+0x9902b0,
+0x7c738b,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0800,
+0x281900,
+0x7d898b,
+0x958014,
+0x281404,
+0xca0c00,
+0xca1000,
+0xca1c00,
+0xca2400,
+0xe2001f,
+0xd4c01a,
+0xd5001a,
+0xd5401a,
+0xcc1803,
+0xcc2c03,
+0xcc2c03,
+0xcc2c03,
+0x7da58b,
+0x7d9c47,
+0x984297,
+0x000000,
+0x800161,
+0xd4c01a,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0x248c06,
+0x0ccc06,
+0x98c006,
+0xcc104e,
+0x990004,
+0xd40073,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xca0800,
+0xca0c00,
+0x34d018,
+0x251001,
+0x950021,
+0xc17fff,
+0xca1000,
+0xca1400,
+0xca1800,
+0xd4801d,
+0xd4c01d,
+0x7db18b,
+0xc14202,
+0xc2c001,
+0xd5801d,
+0x34dc0e,
+0x7d5d4c,
+0x7f734c,
+0xd7401e,
+0xd5001e,
+0xd5401e,
+0xc14200,
+0xc2c000,
+0x099c01,
+0x31dc10,
+0x7f5f4c,
+0x7f734c,
+0x042802,
+0x7d8380,
+0xd5a86f,
+0xd58066,
+0xd7401e,
+0xec005e,
+0xc82402,
+0xc82402,
+0x8001b8,
+0xd60076,
+0xd4401e,
+0xd4801e,
+0xd4c01e,
+0x800000,
+0xee001e,
+0x800000,
+0xee001f,
+0xd4001f,
+0x800000,
+0xd4001f,
+0xd4001f,
+0x880000,
+0xd4001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x010171,
+0x020178,
+0x03008f,
+0x04007f,
+0x050003,
+0x06003f,
+0x070032,
+0x08012c,
+0x090046,
+0x0a0036,
+0x1001b6,
+0x1700a2,
+0x22013a,
+0x230149,
+0x2000b4,
+0x240125,
+0x27004d,
+0x28006a,
+0x2a0060,
+0x2b0052,
+0x2f0065,
+0x320087,
+0x34017f,
+0x3c0156,
+0x3f0072,
+0x41018c,
+0x44012e,
+0x550173,
+0x56017a,
+0x60000b,
+0x610034,
+0x620038,
+0x630038,
+0x640038,
+0x650038,
+0x660038,
+0x670038,
+0x68003a,
+0x690041,
+0x6a0048,
+0x6b0048,
+0x6c0048,
+0x6d0048,
+0x6e0048,
+0x6f0048,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+};
+
+static const u32 RV620_cp_microcode[][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00000000, 0x00e00000, 0x000 },
+    { 0x00010000, 0xc0294620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x00000000, 0x00600000, 0x631 },
+    { 0x00000000, 0x00600000, 0x645 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000f00, 0x00281622, 0x000 },
+    { 0x00000008, 0x00211625, 0x000 },
+    { 0x00000018, 0x00203625, 0x000 },
+    { 0x8d000000, 0x00204411, 0x000 },
+    { 0x00000004, 0x002f0225, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x018 },
+    { 0x00412000, 0x00404811, 0x019 },
+    { 0x00422000, 0x00204811, 0x000 },
+    { 0x8e000000, 0x00204411, 0x000 },
+    { 0x00000028, 0x00204a2d, 0x000 },
+    { 0x90000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x0000000c, 0x00211622, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000019, 0x00211a22, 0x000 },
+    { 0x00000004, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002914c5, 0x000 },
+    { 0x00000019, 0x00203625, 0x000 },
+    { 0x00000000, 0x003a1402, 0x000 },
+    { 0x00000016, 0x00211625, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0xfffffffc, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002914a3, 0x000 },
+    { 0x00000017, 0x00203625, 0x000 },
+    { 0x00008000, 0x00280e22, 0x000 },
+    { 0x00000007, 0x00220e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x20000000, 0x00280e22, 0x000 },
+    { 0x00000006, 0x00210e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00220222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x038 },
+    { 0x00000000, 0x2ee00000, 0x035 },
+    { 0x00000000, 0x2ce00000, 0x037 },
+    { 0x00000000, 0x00400e2d, 0x039 },
+    { 0x00000008, 0x00200e2d, 0x000 },
+    { 0x00000009, 0x0040122d, 0x046 },
+    { 0x00000001, 0x00400e2d, 0x039 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x03e },
+    { 0x00000008, 0x00401c11, 0x041 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x0000000f, 0x00281e27, 0x000 },
+    { 0x00000003, 0x00221e27, 0x000 },
+    { 0x7fc00000, 0x00281a23, 0x000 },
+    { 0x00000014, 0x00211a26, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000008, 0x00221a26, 0x000 },
+    { 0x00000000, 0x00290cc7, 0x000 },
+    { 0x00000027, 0x00203624, 0x000 },
+    { 0x00007f00, 0x00281221, 0x000 },
+    { 0x00001400, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04b },
+    { 0x00000001, 0x00290e23, 0x000 },
+    { 0x0000000e, 0x00203623, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfff80000, 0x00294a23, 0x000 },
+    { 0x00000000, 0x003a2c02, 0x000 },
+    { 0x00000002, 0x00220e2b, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x0000000f, 0x00203623, 0x000 },
+    { 0x00001fff, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00204a2d, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000029, 0x00200e2d, 0x000 },
+    { 0x060a0200, 0x00294a23, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x061 },
+    { 0x00000000, 0x2ee00000, 0x05f },
+    { 0x00000000, 0x2ce00000, 0x05e },
+    { 0x00000000, 0x00400e2d, 0x062 },
+    { 0x00000001, 0x00400e2d, 0x062 },
+    { 0x0000000a, 0x00200e2d, 0x000 },
+    { 0x0000000b, 0x0040122d, 0x06a },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x7fc00000, 0x00281623, 0x000 },
+    { 0x00000014, 0x00211625, 0x000 },
+    { 0x00000001, 0x00331625, 0x000 },
+    { 0x80000000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00290ca3, 0x000 },
+    { 0x3ffffc00, 0x00290e23, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x06d },
+    { 0x00000100, 0x00401c11, 0x070 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x000000f0, 0x00281e27, 0x000 },
+    { 0x00000004, 0x00221e27, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0xfffff0ff, 0x00281a30, 0x000 },
+    { 0x0000a028, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e6, 0x000 },
+    { 0x0000a018, 0x00204411, 0x000 },
+    { 0x3fffffff, 0x00284a23, 0x000 },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000030, 0x0020162d, 0x000 },
+    { 0x00000002, 0x00291625, 0x000 },
+    { 0x00000030, 0x00203625, 0x000 },
+    { 0x00000025, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a3, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x083 },
+    { 0x00000026, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a4, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x084 },
+    { 0x00000000, 0x00400000, 0x08a },
+    { 0x00000025, 0x00203623, 0x000 },
+    { 0x00000026, 0x00203624, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x08a },
+    { 0x00000000, 0x00600000, 0x668 },
+    { 0x00000000, 0x00600000, 0x65c },
+    { 0x00000002, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x08d },
+    { 0x00000012, 0xc0403620, 0x093 },
+    { 0x00000000, 0x2ee00000, 0x091 },
+    { 0x00000000, 0x2ce00000, 0x090 },
+    { 0x00000002, 0x00400e2d, 0x092 },
+    { 0x00000003, 0x00400e2d, 0x092 },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000012, 0x00203623, 0x000 },
+    { 0x00000003, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x098 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x0a0 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x2ee00000, 0x09e },
+    { 0x00000000, 0x2ce00000, 0x09d },
+    { 0x00000002, 0x00400e2d, 0x09f },
+    { 0x00000003, 0x00400e2d, 0x09f },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x003f0000, 0x00280e23, 0x000 },
+    { 0x00000010, 0x00210e23, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x0000001e, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0a7 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x0000001f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0aa },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000008, 0x00210e2b, 0x000 },
+    { 0x0000007f, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0e1 },
+    { 0x00000000, 0x27000000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b3 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00221e30, 0x000 },
+    { 0x99800000, 0x00204411, 0x000 },
+    { 0x00000004, 0x0020122d, 0x000 },
+    { 0x00000008, 0x00221224, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00291ce4, 0x000 },
+    { 0x00000000, 0x00604807, 0x12f },
+    { 0x9b000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x9c000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x0033146f, 0x000 },
+    { 0x00000001, 0x00333e23, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00203c05, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e007, 0x00204411, 0x000 },
+    { 0x0000000f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0cb },
+    { 0x00f8ff08, 0x00204811, 0x000 },
+    { 0x98000000, 0x00404811, 0x0dc },
+    { 0x000000f0, 0x00280e22, 0x000 },
+    { 0x000000a0, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x0da },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d5 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d4 },
+    { 0x00003f00, 0x00400c11, 0x0d6 },
+    { 0x00001f00, 0x00400c11, 0x0d6 },
+    { 0x00000f00, 0x00200c11, 0x000 },
+    { 0x00380009, 0x00294a23, 0x000 },
+    { 0x3f000000, 0x00280e2b, 0x000 },
+    { 0x00000002, 0x00220e23, 0x000 },
+    { 0x00000007, 0x00494a23, 0x0dc },
+    { 0x00380f09, 0x00204811, 0x000 },
+    { 0x68000007, 0x00204811, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000a202, 0x00204411, 0x000 },
+    { 0x00ff0000, 0x00280e22, 0x000 },
+    { 0x00000080, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00200e2d, 0x000 },
+    { 0x00000026, 0x0020122d, 0x000 },
+    { 0x00000000, 0x002f0083, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0ea },
+    { 0x00000000, 0x00600000, 0x662 },
+    { 0x00000000, 0x00400000, 0x0eb },
+    { 0x00000000, 0x00600000, 0x665 },
+    { 0x00000007, 0x0020222d, 0x000 },
+    { 0x00000005, 0x00220e22, 0x000 },
+    { 0x00100000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x000000ef, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000003, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x0f8 },
+    { 0x0000000b, 0x00210228, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0f8 },
+    { 0x00000400, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000001c, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0fd },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000001e, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x10b },
+    { 0x0000a30f, 0x00204411, 0x000 },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x104 },
+    { 0xffffffff, 0x00404811, 0x10b },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x107 },
+    { 0x0000ffff, 0x00404811, 0x10b },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x10a },
+    { 0x000000ff, 0x00404811, 0x10b },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0002c400, 0x00204411, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x112 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000018, 0x40224a20, 0x000 },
+    { 0x00000010, 0xc0424a20, 0x114 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000000a, 0x00201011, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x11b },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00531224, 0x117 },
+    { 0xffbfffff, 0x00283a2e, 0x000 },
+    { 0x0000001b, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x12e },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0x00000018, 0x00220e30, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e00e, 0x00204411, 0x000 },
+    { 0x07f8ff08, 0x00204811, 0x000 },
+    { 0x00000000, 0x00294a23, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x00800000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68d },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x68c },
+    { 0x00000004, 0x00404c11, 0x135 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x0000001c, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x13c },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40280620, 0x000 },
+    { 0x00000010, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x00341461, 0x000 },
+    { 0x00000000, 0x00741882, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x147 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0681a20, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x158 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000001, 0x00300a2f, 0x000 },
+    { 0x00000001, 0x00210a22, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600000, 0x18f },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00202c08, 0x000 },
+    { 0x00000000, 0x00202411, 0x000 },
+    { 0x00000000, 0x00202811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000002, 0x00221e29, 0x000 },
+    { 0x00000000, 0x007048eb, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000001, 0x40330620, 0x000 },
+    { 0x00000000, 0xc0302409, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x181 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x186 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x186 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000001, 0x00530621, 0x182 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0604800, 0x197 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000011, 0x0020062d, 0x000 },
+    { 0x00000000, 0x0078042a, 0x2fb },
+    { 0x00000000, 0x00202809, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x174 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x194 },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x46000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x19b },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00804811, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40281620, 0x000 },
+    { 0x00000010, 0xc0811a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000008, 0x00221e30, 0x000 },
+    { 0x00000029, 0x00201a2d, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfffbff09, 0x00204811, 0x000 },
+    { 0x0000000f, 0x0020222d, 0x000 },
+    { 0x00001fff, 0x00294a28, 0x000 },
+    { 0x00000006, 0x0020222d, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000100, 0x00201811, 0x000 },
+    { 0x00000008, 0x00621e28, 0x12f },
+    { 0x00000008, 0x00822228, 0x000 },
+    { 0x0002c000, 0x00204411, 0x000 },
+    { 0x00000015, 0x00600e2d, 0x1bd },
+    { 0x00000016, 0x00600e2d, 0x1bd },
+    { 0x0000c008, 0x00204411, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1b9 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x39000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00804802, 0x000 },
+    { 0x00000018, 0x00202e2d, 0x000 },
+    { 0x00000000, 0x003b0d63, 0x000 },
+    { 0x00000008, 0x00224a23, 0x000 },
+    { 0x00000010, 0x00224a23, 0x000 },
+    { 0x00000018, 0x00224a23, 0x000 },
+    { 0x00000000, 0x00804803, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000007, 0x0021062f, 0x000 },
+    { 0x00000013, 0x00200a2d, 0x000 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000ffff, 0x40282220, 0x000 },
+    { 0x0000000f, 0x00262228, 0x000 },
+    { 0x00000010, 0x40212620, 0x000 },
+    { 0x0000000f, 0x00262629, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1e0 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000081, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000080, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1dc },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1d8 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000001f, 0x00280a22, 0x000 },
+    { 0x0000001f, 0x00282a2a, 0x000 },
+    { 0x00000001, 0x00530621, 0x1d1 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000002, 0x00304a2f, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x00301e2f, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1e5 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x0000000f, 0x00260e23, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000000f, 0x00261224, 0x000 },
+    { 0x00000000, 0x00201411, 0x000 },
+    { 0x00000000, 0x00601811, 0x2bb },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022b, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1f8 },
+    { 0x00000010, 0x00221628, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a29, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000010, 0x00221623, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a24, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x00731503, 0x205 },
+    { 0x00000000, 0x00201805, 0x000 },
+    { 0x00000000, 0x00731524, 0x205 },
+    { 0x00000000, 0x002d14c5, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00000000, 0x00202003, 0x000 },
+    { 0x00000000, 0x00802404, 0x000 },
+    { 0x0000000f, 0x00210225, 0x000 },
+    { 0x00000000, 0x14c00000, 0x68c },
+    { 0x00000000, 0x002b1405, 0x000 },
+    { 0x00000001, 0x00901625, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00294a22, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a21, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000ffff, 0x40281220, 0x000 },
+    { 0x00000010, 0xc0211a20, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211620, 0x000 },
+    { 0x00000000, 0x00741465, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00000001, 0x00330621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x219 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x212 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x645 },
+    { 0x00000000, 0x0040040f, 0x213 },
+    { 0x00000000, 0x00600000, 0x631 },
+    { 0x00000000, 0x00600000, 0x645 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00000000, 0x00600000, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x232 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x236 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x236 },
+    { 0x00000000, 0xc0404800, 0x233 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x00600411, 0x2fb },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x631 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000018, 0x40210a20, 0x000 },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x24c },
+    { 0x00000014, 0x0020222d, 0x000 },
+    { 0x00080101, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x251 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000010, 0x00600411, 0x315 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00000000, 0x00600000, 0x27c },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000001, 0x00211e27, 0x000 },
+    { 0x00000000, 0x14e00000, 0x26a },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x0000ffff, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00341c27, 0x000 },
+    { 0x00000000, 0x12c00000, 0x25f },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e5, 0x000 },
+    { 0x00000000, 0x08c00000, 0x262 },
+    { 0x00000000, 0x00201407, 0x000 },
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+    { 0x00000010, 0x00211e27, 0x000 },
+    { 0x00000000, 0x00341c47, 0x000 },
+    { 0x00000000, 0x12c00000, 0x267 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x08c00000, 0x26a },
+    { 0x00000000, 0x00201807, 0x000 },
+    { 0x00000000, 0x00600000, 0x2c1 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000000, 0x00342023, 0x000 },
+    { 0x00000000, 0x12c00000, 0x272 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x271 },
+    { 0x00000016, 0x00404811, 0x276 },
+    { 0x00000018, 0x00404811, 0x276 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x275 },
+    { 0x00000017, 0x00404811, 0x276 },
+    { 0x00000019, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00604411, 0x2e9 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x256 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000010, 0x40210620, 0x000 },
+    { 0x0000ffff, 0xc0280a20, 0x000 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0881a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x00000000, 0x00600000, 0x631 },
+    { 0x00000000, 0xc0600000, 0x2a3 },
+    { 0x00000005, 0x00200a2d, 0x000 },
+    { 0x00000008, 0x00220a22, 0x000 },
+    { 0x0000002b, 0x00201a2d, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00007000, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00311ce6, 0x000 },
+    { 0x0000002a, 0x00201a2d, 0x000 },
+    { 0x0000000c, 0x00221a26, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
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+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x0000002b, 0x00203623, 0x000 },
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+    { 0x00000000, 0x00691ce2, 0x12f },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x29d },
+    { 0x00000001, 0x00333e2f, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
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+    { 0x00000009, 0x00204811, 0x000 },
+    { 0xa1000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce3, 0x000 },
+    { 0x00000021, 0x00203627, 0x000 },
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+    { 0x00000000, 0x002c1ce4, 0x000 },
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+    { 0x00000000, 0x003120a3, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
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+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
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+    { 0x00000022, 0x00203624, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000023, 0x00203627, 0x000 },
+    { 0x00000000, 0x00311cc4, 0x000 },
+    { 0x00000024, 0x00803627, 0x000 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14c00000, 0x2dc },
+    { 0x00000000, 0x00400000, 0x2d9 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2d9 },
+    { 0x00000003, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2dc },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e1, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
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+    { 0x00000000, 0x003120a1, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
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+    { 0x00000000, 0x002e00e2, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000000, 0x00600000, 0x668 },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00600000, 0x65f },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2a7 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x0000001a, 0x00201e2d, 0x000 },
+    { 0x0000001b, 0x0080222d, 0x000 },
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+    { 0x00000000, 0x00311ca3, 0x000 },
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+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca1, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x003808c5, 0x000 },
+    { 0x00000000, 0x00300841, 0x000 },
+    { 0x00000001, 0x00220a22, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
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+    { 0x00000000, 0x14c00000, 0x318 },
+    { 0xffffffef, 0x00280621, 0x000 },
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+    { 0x00000000, 0x00294901, 0x000 },
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+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x97000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
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+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
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+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00002257, 0x00204411, 0x000 },
+    { 0x00000003, 0xc0484a20, 0x000 },
+    { 0x0000225d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x645 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x00000001, 0x40304a20, 0x000 },
+    { 0x00000002, 0xc0304a20, 0x000 },
+    { 0x00000001, 0x00530a22, 0x34b },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x354 },
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+    { 0x00000000, 0x0cc00000, 0x364 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00604802, 0x36e },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x36a },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35f },
+    { 0x00000028, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5c0 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35f },
+    { 0x0000002c, 0x00203626, 0x000 },
+    { 0x00000049, 0x00201811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x370 },
+    { 0x0000002c, 0x00801a2d, 0x000 },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x00000015, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x386 },
+    { 0x00000006, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3b1 },
+    { 0x00000016, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3b5 },
+    { 0x00000020, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x39c },
+    { 0x0000000f, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a8 },
+    { 0x00000010, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a8 },
+    { 0x0000001e, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x390 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x08000000, 0x00290a22, 0x000 },
+    { 0x00000003, 0x40210e20, 0x000 },
+    { 0x0000000c, 0xc0211220, 0x000 },
+    { 0x00080000, 0x00281224, 0x000 },
+    { 0x00000014, 0xc0221620, 0x000 },
+    { 0x00000000, 0x002914a4, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948a2, 0x000 },
+    { 0x0000a1fe, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000015, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x392 },
+    { 0x0000210e, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000017, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000003, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x39e },
+    { 0x00002108, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x80000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000010, 0x00204811, 0x000 },
+    { 0x00000000, 0x00200010, 0x000 },
+    { 0x00000000, 0x14c00000, 0x3ae },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000006, 0x00404811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x0000001d, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x3ce },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68d },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x3c0 },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0xbabecafe, 0x00204811, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000004, 0x00404811, 0x000 },
+    { 0x00002170, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000a, 0x00204811, 0x000 },
+    { 0x00000000, 0x00200010, 0x000 },
+    { 0x00000000, 0x14c00000, 0x3d3 },
+    { 0x8c000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00404811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00003fff, 0x40280a20, 0x000 },
+    { 0x80000000, 0x40280e20, 0x000 },
+    { 0x40000000, 0xc0281220, 0x000 },
+    { 0x00040000, 0x00694622, 0x68d },
+    { 0x00000000, 0x00201410, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x3e1 },
+    { 0x00000000, 0xc0401800, 0x3e4 },
+    { 0x00003fff, 0xc0281a20, 0x000 },
+    { 0x00040000, 0x00694626, 0x68d },
+    { 0x00000000, 0x00201810, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x3e7 },
+    { 0x00000000, 0xc0401c00, 0x3ea },
+    { 0x00003fff, 0xc0281e20, 0x000 },
+    { 0x00040000, 0x00694627, 0x68d },
+    { 0x00000000, 0x00201c10, 0x000 },
+    { 0x00000000, 0x00204402, 0x000 },
+    { 0x00000000, 0x002820c5, 0x000 },
+    { 0x00000000, 0x004948e8, 0x000 },
+    { 0xa5800000, 0x00200811, 0x000 },
+    { 0x00002000, 0x00200c11, 0x000 },
+    { 0x83000000, 0x00604411, 0x412 },
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+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0000a2c4, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x58d },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5a0 },
+    { 0x0000a2bb, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x68d },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0000a2c5, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x59e },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5b1 },
+    { 0x0000a2bf, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x68d },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0000a2c6, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5af },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x0000a2c3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x68d },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0000a2c7, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5be },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x85000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x0000304a, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x5c4 },
+    { 0xa4000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0xc0600000, 0x5c9 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000002c, 0x00203621, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5d0 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000030, 0x00403621, 0x5e3 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x5e3 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a092, 0x00604411, 0x68d },
+    { 0x00000031, 0x00203630, 0x000 },
+    { 0x0004a093, 0x00604411, 0x68d },
+    { 0x00000032, 0x00203630, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x68d },
+    { 0x00000033, 0x00203630, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x68d },
+    { 0x00000034, 0x00203630, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x68d },
+    { 0x00000035, 0x00203630, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x68d },
+    { 0x00000036, 0x00203630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x88000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000001, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x62c },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x62c },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x605 },
+    { 0x0000a092, 0x00204411, 0x000 },
+    { 0x00000031, 0x00204a2d, 0x000 },
+    { 0x0000a093, 0x00204411, 0x000 },
+    { 0x00000032, 0x00204a2d, 0x000 },
+    { 0x0000a2b6, 0x00204411, 0x000 },
+    { 0x00000033, 0x00204a2d, 0x000 },
+    { 0x0000a2ba, 0x00204411, 0x000 },
+    { 0x00000034, 0x00204a2d, 0x000 },
+    { 0x0000a2be, 0x00204411, 0x000 },
+    { 0x00000035, 0x00204a2d, 0x000 },
+    { 0x0000a2c2, 0x00204411, 0x000 },
+    { 0x00000036, 0x00204a2d, 0x000 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x000001ff, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x62b },
+    { 0x00000000, 0x00210221, 0x000 },
+    { 0x00000000, 0x14c00000, 0x60e },
+    { 0x0004a003, 0x00604411, 0x68d },
+    { 0x0000a003, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x14c00000, 0x613 },
+    { 0x0004a010, 0x00604411, 0x68d },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x62b },
+    { 0x0004a011, 0x00604411, 0x68d },
+    { 0x0000a011, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a012, 0x00604411, 0x68d },
+    { 0x0000a012, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a013, 0x00604411, 0x68d },
+    { 0x0000a013, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a014, 0x00604411, 0x68d },
+    { 0x0000a014, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a015, 0x00604411, 0x68d },
+    { 0x0000a015, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a016, 0x00604411, 0x68d },
+    { 0x0000a016, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a017, 0x00604411, 0x68d },
+    { 0x0000a017, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x0000002c, 0x0080062d, 0x000 },
+    { 0xff000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000002, 0x00804811, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x63d },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000002, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x63b },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68d },
+    { 0x00001000, 0x00200811, 0x000 },
+    { 0x0000002b, 0x00203622, 0x000 },
+    { 0x00000000, 0x00600000, 0x641 },
+    { 0x00000000, 0x00600000, 0x5c9 },
+    { 0x98000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0600000, 0x641 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000022, 0x00204811, 0x000 },
+    { 0x89000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00404811, 0x62d },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x62d },
+    { 0x00000000, 0x00600000, 0x65c },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0xc0204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x09800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68d },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x00000004, 0x00404c11, 0x656 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000004, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffffb, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffff7, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x01800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68d },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x68c },
+    { 0x00000010, 0x00404c11, 0x672 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x38c00000, 0x000 },
+    { 0x0000001d, 0x00200a2d, 0x000 },
+    { 0x0000001e, 0x00200e2d, 0x000 },
+    { 0x0000001f, 0x0020122d, 0x000 },
+    { 0x00000020, 0x0020162d, 0x000 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x002f0064, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x68b },
+    { 0x00000003, 0x00281a22, 0x000 },
+    { 0x00000008, 0x00221222, 0x000 },
+    { 0xfffff000, 0x00281224, 0x000 },
+    { 0x00000000, 0x002910c4, 0x000 },
+    { 0x0000001f, 0x00403624, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x68d },
+    { 0x9f000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x690 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x692 },
+    { 0x9e000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x695 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0xc0204411, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000024, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000022, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x01420502, 0x05c00250, 0x000 },
+    { 0x01c30168, 0x043f05c0, 0x000 },
+    { 0x02250209, 0x02500151, 0x000 },
+    { 0x02230245, 0x02a00241, 0x000 },
+    { 0x03d705c0, 0x05c005c0, 0x000 },
+    { 0x0649064a, 0x031f05c0, 0x000 },
+    { 0x05c005c5, 0x03200340, 0x000 },
+    { 0x032a0282, 0x03420334, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c00551, 0x05c005c0, 0x000 },
+    { 0x03ba05c0, 0x04bb0344, 0x000 },
+    { 0x049a0450, 0x043d05c0, 0x000 },
+    { 0x04d005c0, 0x044104dd, 0x000 },
+    { 0x04500507, 0x03510375, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c005c0, 0x063f05c7, 0x000 },
+    { 0x05c005c0, 0x000705c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x03f803ed, 0x04080406, 0x000 },
+    { 0x040e040a, 0x040c0410, 0x000 },
+    { 0x041c0418, 0x04240420, 0x000 },
+    { 0x042c0428, 0x04340430, 0x000 },
+    { 0x05c005c0, 0x043805c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x05c005c0, 0x05c005c0, 0x000 },
+    { 0x00020679, 0x06970006, 0x000 },
+};
+
+static const u32 RV620_pfp_microcode[]={
+0xca0400,
+0xa00000,
+0x7e828b,
+0x7c038b,
+0x8001b8,
+0x7c038b,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xc41838,
+0xca2400,
+0xca2800,
+0x9581a8,
+0xc41c3a,
+0xc3c000,
+0xca0800,
+0xca0c00,
+0x7c744b,
+0xc20005,
+0x99c000,
+0xc41c3a,
+0x7c744c,
+0xc0fff0,
+0x042c04,
+0x309002,
+0x7d2500,
+0x351402,
+0x7d350b,
+0x255403,
+0x7cd580,
+0x259c03,
+0x95c004,
+0xd5001b,
+0x7eddc1,
+0x7d9d80,
+0xd6801b,
+0xd5801b,
+0xd4401e,
+0xd5401e,
+0xd6401e,
+0xd6801e,
+0xd4801e,
+0xd4c01e,
+0x9783d3,
+0xd5c01e,
+0xca0800,
+0x80001a,
+0xca0c00,
+0xe4011e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xe4013e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca1800,
+0xd4401e,
+0xd5801e,
+0x800053,
+0xd40075,
+0xd4401e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd48019,
+0xd4c018,
+0xd50017,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xe2001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0xd48060,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xd48061,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xca0c00,
+0xd4401e,
+0xd48016,
+0xd4c016,
+0xd4801e,
+0x8001b8,
+0xd4c01e,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x948004,
+0xca1400,
+0xe420f3,
+0xd42013,
+0xd56065,
+0xd4e01c,
+0xd5201c,
+0xd5601c,
+0x800000,
+0x062001,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9483f7,
+0xca1400,
+0xe420f3,
+0x800079,
+0xd42013,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9883ef,
+0xca1400,
+0xd40064,
+0x80008d,
+0x000000,
+0xc41432,
+0xc61843,
+0xc4082f,
+0x954005,
+0xc40c30,
+0xd4401e,
+0x800000,
+0xee001e,
+0x9583f5,
+0xc41031,
+0xd44033,
+0xd52065,
+0xd4a01c,
+0xd4e01c,
+0xd5201c,
+0xe4015e,
+0xd4001e,
+0x800000,
+0x062001,
+0xca1800,
+0x0a2001,
+0xd60076,
+0xc40836,
+0x988007,
+0xc61045,
+0x950110,
+0xd4001f,
+0xd46062,
+0x800000,
+0xd42062,
+0xcc3835,
+0xcc1433,
+0x8401bb,
+0xd40072,
+0xd5401e,
+0x800000,
+0xee001e,
+0xe2001a,
+0x8401bb,
+0xe2001a,
+0xcc104b,
+0xcc0447,
+0x2c9401,
+0x7d098b,
+0x984005,
+0x7d15cb,
+0xd4001a,
+0x8001b8,
+0xd4006d,
+0x344401,
+0xcc0c48,
+0x98403a,
+0xcc2c4a,
+0x958004,
+0xcc0449,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0x282801,
+0x8400f0,
+0xcc1003,
+0x98801b,
+0x04380c,
+0x8400f0,
+0xcc1003,
+0x988017,
+0x043808,
+0x8400f0,
+0xcc1003,
+0x988013,
+0x043804,
+0x8400f0,
+0xcc1003,
+0x988014,
+0xcc104c,
+0x9a8009,
+0xcc144d,
+0x9840dc,
+0xd4006d,
+0xcc1848,
+0xd5001a,
+0xd5401a,
+0x8000c9,
+0xd5801a,
+0x96c0d5,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0x9ac003,
+0xd4006d,
+0xd4006e,
+0x800000,
+0xec007f,
+0x9ac0cc,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0x7d9103,
+0x7dd583,
+0x7d190c,
+0x35cc1f,
+0x35701f,
+0x7cf0cb,
+0x7cd08b,
+0x880000,
+0x7e8e8b,
+0x95c004,
+0xd4006e,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0xcc0803,
+0xcc0c03,
+0xcc1003,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0xcc2403,
+0xcc2803,
+0x35c41f,
+0x36b01f,
+0x7c704b,
+0x34f01f,
+0x7c704b,
+0x35701f,
+0x7c704b,
+0x7d8881,
+0x7dccc1,
+0x7e5101,
+0x7e9541,
+0x7c9082,
+0x7cd4c2,
+0x7c848b,
+0x9ac003,
+0x7c8c8b,
+0x2c8801,
+0x98809e,
+0xd4006d,
+0x98409c,
+0xd4006e,
+0xcc084c,
+0xcc0c4d,
+0xcc1048,
+0xd4801a,
+0xd4c01a,
+0x800101,
+0xd5001a,
+0xcc0832,
+0xd40032,
+0x9482d9,
+0xca0c00,
+0xd4401e,
+0x800000,
+0xd4001e,
+0xe4011e,
+0xd4001e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd4401e,
+0xca1400,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xd5401e,
+0xd54034,
+0x800000,
+0xee001e,
+0x280404,
+0xe2001a,
+0xe2001a,
+0xd4401a,
+0xca3800,
+0xcc0803,
+0xcc0c03,
+0xcc0c03,
+0xcc0c03,
+0x9882bd,
+0x000000,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0400,
+0xc2ff00,
+0xcc0834,
+0xc13fff,
+0x7c74cb,
+0x7cc90b,
+0x7d010f,
+0x9902b0,
+0x7c738b,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0800,
+0x281900,
+0x7d898b,
+0x958014,
+0x281404,
+0xca0c00,
+0xca1000,
+0xca1c00,
+0xca2400,
+0xe2001f,
+0xd4c01a,
+0xd5001a,
+0xd5401a,
+0xcc1803,
+0xcc2c03,
+0xcc2c03,
+0xcc2c03,
+0x7da58b,
+0x7d9c47,
+0x984297,
+0x000000,
+0x800161,
+0xd4c01a,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0x248c06,
+0x0ccc06,
+0x98c006,
+0xcc104e,
+0x990004,
+0xd40073,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xca0800,
+0xca0c00,
+0x34d018,
+0x251001,
+0x950021,
+0xc17fff,
+0xca1000,
+0xca1400,
+0xca1800,
+0xd4801d,
+0xd4c01d,
+0x7db18b,
+0xc14202,
+0xc2c001,
+0xd5801d,
+0x34dc0e,
+0x7d5d4c,
+0x7f734c,
+0xd7401e,
+0xd5001e,
+0xd5401e,
+0xc14200,
+0xc2c000,
+0x099c01,
+0x31dc10,
+0x7f5f4c,
+0x7f734c,
+0x042802,
+0x7d8380,
+0xd5a86f,
+0xd58066,
+0xd7401e,
+0xec005e,
+0xc82402,
+0xc82402,
+0x8001b8,
+0xd60076,
+0xd4401e,
+0xd4801e,
+0xd4c01e,
+0x800000,
+0xee001e,
+0x800000,
+0xee001f,
+0xd4001f,
+0x800000,
+0xd4001f,
+0xd4001f,
+0x880000,
+0xd4001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x010171,
+0x020178,
+0x03008f,
+0x04007f,
+0x050003,
+0x06003f,
+0x070032,
+0x08012c,
+0x090046,
+0x0a0036,
+0x1001b6,
+0x1700a2,
+0x22013a,
+0x230149,
+0x2000b4,
+0x240125,
+0x27004d,
+0x28006a,
+0x2a0060,
+0x2b0052,
+0x2f0065,
+0x320087,
+0x34017f,
+0x3c0156,
+0x3f0072,
+0x41018c,
+0x44012e,
+0x550173,
+0x56017a,
+0x60000b,
+0x610034,
+0x620038,
+0x630038,
+0x640038,
+0x650038,
+0x660038,
+0x670038,
+0x68003a,
+0x690041,
+0x6a0048,
+0x6b0048,
+0x6c0048,
+0x6d0048,
+0x6e0048,
+0x6f0048,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+};
+
+static const u32 RV630_cp_microcode[][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00000000, 0x00e00000, 0x000 },
+    { 0x00010000, 0xc0294620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x00000000, 0x00600000, 0x62e },
+    { 0x00000000, 0x00600000, 0x642 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000f00, 0x00281622, 0x000 },
+    { 0x00000008, 0x00211625, 0x000 },
+    { 0x00000018, 0x00203625, 0x000 },
+    { 0x8d000000, 0x00204411, 0x000 },
+    { 0x00000004, 0x002f0225, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x018 },
+    { 0x00412000, 0x00404811, 0x019 },
+    { 0x00422000, 0x00204811, 0x000 },
+    { 0x8e000000, 0x00204411, 0x000 },
+    { 0x00000028, 0x00204a2d, 0x000 },
+    { 0x90000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x0000000c, 0x00211622, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000019, 0x00211a22, 0x000 },
+    { 0x00000004, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002914c5, 0x000 },
+    { 0x00000019, 0x00203625, 0x000 },
+    { 0x00000000, 0x003a1402, 0x000 },
+    { 0x00000016, 0x00211625, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0xfffffffc, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002914a3, 0x000 },
+    { 0x00000017, 0x00203625, 0x000 },
+    { 0x00008000, 0x00280e22, 0x000 },
+    { 0x00000007, 0x00220e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x20000000, 0x00280e22, 0x000 },
+    { 0x00000006, 0x00210e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00220222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x038 },
+    { 0x00000000, 0x2ee00000, 0x035 },
+    { 0x00000000, 0x2ce00000, 0x037 },
+    { 0x00000000, 0x00400e2d, 0x039 },
+    { 0x00000008, 0x00200e2d, 0x000 },
+    { 0x00000009, 0x0040122d, 0x046 },
+    { 0x00000001, 0x00400e2d, 0x039 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x03e },
+    { 0x00000008, 0x00401c11, 0x041 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x0000000f, 0x00281e27, 0x000 },
+    { 0x00000003, 0x00221e27, 0x000 },
+    { 0x7fc00000, 0x00281a23, 0x000 },
+    { 0x00000014, 0x00211a26, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000008, 0x00221a26, 0x000 },
+    { 0x00000000, 0x00290cc7, 0x000 },
+    { 0x00000027, 0x00203624, 0x000 },
+    { 0x00007f00, 0x00281221, 0x000 },
+    { 0x00001400, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04b },
+    { 0x00000001, 0x00290e23, 0x000 },
+    { 0x0000000e, 0x00203623, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfff80000, 0x00294a23, 0x000 },
+    { 0x00000000, 0x003a2c02, 0x000 },
+    { 0x00000002, 0x00220e2b, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x0000000f, 0x00203623, 0x000 },
+    { 0x00001fff, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00204a2d, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000029, 0x00200e2d, 0x000 },
+    { 0x060a0200, 0x00294a23, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x061 },
+    { 0x00000000, 0x2ee00000, 0x05f },
+    { 0x00000000, 0x2ce00000, 0x05e },
+    { 0x00000000, 0x00400e2d, 0x062 },
+    { 0x00000001, 0x00400e2d, 0x062 },
+    { 0x0000000a, 0x00200e2d, 0x000 },
+    { 0x0000000b, 0x0040122d, 0x06a },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x7fc00000, 0x00281623, 0x000 },
+    { 0x00000014, 0x00211625, 0x000 },
+    { 0x00000001, 0x00331625, 0x000 },
+    { 0x80000000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00290ca3, 0x000 },
+    { 0x3ffffc00, 0x00290e23, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x06d },
+    { 0x00000100, 0x00401c11, 0x070 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x000000f0, 0x00281e27, 0x000 },
+    { 0x00000004, 0x00221e27, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0xfffff0ff, 0x00281a30, 0x000 },
+    { 0x0000a028, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e6, 0x000 },
+    { 0x0000a018, 0x00204411, 0x000 },
+    { 0x3fffffff, 0x00284a23, 0x000 },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000030, 0x0020162d, 0x000 },
+    { 0x00000002, 0x00291625, 0x000 },
+    { 0x00000030, 0x00203625, 0x000 },
+    { 0x00000025, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a3, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x083 },
+    { 0x00000026, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a4, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x084 },
+    { 0x00000000, 0x00400000, 0x08a },
+    { 0x00000025, 0x00203623, 0x000 },
+    { 0x00000026, 0x00203624, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x08a },
+    { 0x00000000, 0x00600000, 0x665 },
+    { 0x00000000, 0x00600000, 0x659 },
+    { 0x00000002, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x08d },
+    { 0x00000012, 0xc0403620, 0x093 },
+    { 0x00000000, 0x2ee00000, 0x091 },
+    { 0x00000000, 0x2ce00000, 0x090 },
+    { 0x00000002, 0x00400e2d, 0x092 },
+    { 0x00000003, 0x00400e2d, 0x092 },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000012, 0x00203623, 0x000 },
+    { 0x00000003, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x098 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x0a0 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x2ee00000, 0x09e },
+    { 0x00000000, 0x2ce00000, 0x09d },
+    { 0x00000002, 0x00400e2d, 0x09f },
+    { 0x00000003, 0x00400e2d, 0x09f },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x003f0000, 0x00280e23, 0x000 },
+    { 0x00000010, 0x00210e23, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x0000001e, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0a7 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x0000001f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0aa },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000008, 0x00210e2b, 0x000 },
+    { 0x0000007f, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0e1 },
+    { 0x00000000, 0x27000000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b3 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00221e30, 0x000 },
+    { 0x99800000, 0x00204411, 0x000 },
+    { 0x00000004, 0x0020122d, 0x000 },
+    { 0x00000008, 0x00221224, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00291ce4, 0x000 },
+    { 0x00000000, 0x00604807, 0x12f },
+    { 0x9b000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x9c000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x0033146f, 0x000 },
+    { 0x00000001, 0x00333e23, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00203c05, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e007, 0x00204411, 0x000 },
+    { 0x0000000f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0cb },
+    { 0x00f8ff08, 0x00204811, 0x000 },
+    { 0x98000000, 0x00404811, 0x0dc },
+    { 0x000000f0, 0x00280e22, 0x000 },
+    { 0x000000a0, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x0da },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d5 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d4 },
+    { 0x00003f00, 0x00400c11, 0x0d6 },
+    { 0x00001f00, 0x00400c11, 0x0d6 },
+    { 0x00000f00, 0x00200c11, 0x000 },
+    { 0x00380009, 0x00294a23, 0x000 },
+    { 0x3f000000, 0x00280e2b, 0x000 },
+    { 0x00000002, 0x00220e23, 0x000 },
+    { 0x00000007, 0x00494a23, 0x0dc },
+    { 0x00380f09, 0x00204811, 0x000 },
+    { 0x68000007, 0x00204811, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000a202, 0x00204411, 0x000 },
+    { 0x00ff0000, 0x00280e22, 0x000 },
+    { 0x00000080, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00200e2d, 0x000 },
+    { 0x00000026, 0x0020122d, 0x000 },
+    { 0x00000000, 0x002f0083, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0ea },
+    { 0x00000000, 0x00600000, 0x65f },
+    { 0x00000000, 0x00400000, 0x0eb },
+    { 0x00000000, 0x00600000, 0x662 },
+    { 0x00000007, 0x0020222d, 0x000 },
+    { 0x00000005, 0x00220e22, 0x000 },
+    { 0x00100000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x000000ef, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000003, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x0f8 },
+    { 0x0000000b, 0x00210228, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0f8 },
+    { 0x00000400, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000001c, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0fd },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000001e, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x10b },
+    { 0x0000a30f, 0x00204411, 0x000 },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x104 },
+    { 0xffffffff, 0x00404811, 0x10b },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x107 },
+    { 0x0000ffff, 0x00404811, 0x10b },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x10a },
+    { 0x000000ff, 0x00404811, 0x10b },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0002c400, 0x00204411, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x112 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000018, 0x40224a20, 0x000 },
+    { 0x00000010, 0xc0424a20, 0x114 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000000a, 0x00201011, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x11b },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00531224, 0x117 },
+    { 0xffbfffff, 0x00283a2e, 0x000 },
+    { 0x0000001b, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x12e },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0x00000018, 0x00220e30, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e00e, 0x00204411, 0x000 },
+    { 0x07f8ff08, 0x00204811, 0x000 },
+    { 0x00000000, 0x00294a23, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x00800000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68a },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x689 },
+    { 0x00000004, 0x00404c11, 0x135 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x0000001c, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68a },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x13c },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40280620, 0x000 },
+    { 0x00000010, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x00341461, 0x000 },
+    { 0x00000000, 0x00741882, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x147 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0681a20, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x158 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000001, 0x00300a2f, 0x000 },
+    { 0x00000001, 0x00210a22, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600000, 0x18f },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00202c08, 0x000 },
+    { 0x00000000, 0x00202411, 0x000 },
+    { 0x00000000, 0x00202811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000002, 0x00221e29, 0x000 },
+    { 0x00000000, 0x007048eb, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000001, 0x40330620, 0x000 },
+    { 0x00000000, 0xc0302409, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x181 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x186 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x186 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000001, 0x00530621, 0x182 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0604800, 0x197 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000011, 0x0020062d, 0x000 },
+    { 0x00000000, 0x0078042a, 0x2fb },
+    { 0x00000000, 0x00202809, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x174 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x194 },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x46000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x19b },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00804811, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40281620, 0x000 },
+    { 0x00000010, 0xc0811a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000008, 0x00221e30, 0x000 },
+    { 0x00000029, 0x00201a2d, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfffbff09, 0x00204811, 0x000 },
+    { 0x0000000f, 0x0020222d, 0x000 },
+    { 0x00001fff, 0x00294a28, 0x000 },
+    { 0x00000006, 0x0020222d, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000100, 0x00201811, 0x000 },
+    { 0x00000008, 0x00621e28, 0x12f },
+    { 0x00000008, 0x00822228, 0x000 },
+    { 0x0002c000, 0x00204411, 0x000 },
+    { 0x00000015, 0x00600e2d, 0x1bd },
+    { 0x00000016, 0x00600e2d, 0x1bd },
+    { 0x0000c008, 0x00204411, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1b9 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x39000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00804802, 0x000 },
+    { 0x00000018, 0x00202e2d, 0x000 },
+    { 0x00000000, 0x003b0d63, 0x000 },
+    { 0x00000008, 0x00224a23, 0x000 },
+    { 0x00000010, 0x00224a23, 0x000 },
+    { 0x00000018, 0x00224a23, 0x000 },
+    { 0x00000000, 0x00804803, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000007, 0x0021062f, 0x000 },
+    { 0x00000013, 0x00200a2d, 0x000 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000ffff, 0x40282220, 0x000 },
+    { 0x0000000f, 0x00262228, 0x000 },
+    { 0x00000010, 0x40212620, 0x000 },
+    { 0x0000000f, 0x00262629, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1e0 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000081, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000080, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1dc },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1d8 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000001f, 0x00280a22, 0x000 },
+    { 0x0000001f, 0x00282a2a, 0x000 },
+    { 0x00000001, 0x00530621, 0x1d1 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000002, 0x00304a2f, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x00301e2f, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1e5 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x0000000f, 0x00260e23, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000000f, 0x00261224, 0x000 },
+    { 0x00000000, 0x00201411, 0x000 },
+    { 0x00000000, 0x00601811, 0x2bb },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022b, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1f8 },
+    { 0x00000010, 0x00221628, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a29, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000010, 0x00221623, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a24, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x00731503, 0x205 },
+    { 0x00000000, 0x00201805, 0x000 },
+    { 0x00000000, 0x00731524, 0x205 },
+    { 0x00000000, 0x002d14c5, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00000000, 0x00202003, 0x000 },
+    { 0x00000000, 0x00802404, 0x000 },
+    { 0x0000000f, 0x00210225, 0x000 },
+    { 0x00000000, 0x14c00000, 0x689 },
+    { 0x00000000, 0x002b1405, 0x000 },
+    { 0x00000001, 0x00901625, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00294a22, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a21, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000ffff, 0x40281220, 0x000 },
+    { 0x00000010, 0xc0211a20, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211620, 0x000 },
+    { 0x00000000, 0x00741465, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00000001, 0x00330621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x219 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x212 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x642 },
+    { 0x00000000, 0x0040040f, 0x213 },
+    { 0x00000000, 0x00600000, 0x62e },
+    { 0x00000000, 0x00600000, 0x642 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00000000, 0x00600000, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x232 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x236 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x236 },
+    { 0x00000000, 0xc0404800, 0x233 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x00600411, 0x2fb },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x62e },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000018, 0x40210a20, 0x000 },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x24c },
+    { 0x00000014, 0x0020222d, 0x000 },
+    { 0x00080101, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x251 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000010, 0x00600411, 0x315 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00000000, 0x00600000, 0x27c },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000001, 0x00211e27, 0x000 },
+    { 0x00000000, 0x14e00000, 0x26a },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x0000ffff, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00341c27, 0x000 },
+    { 0x00000000, 0x12c00000, 0x25f },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e5, 0x000 },
+    { 0x00000000, 0x08c00000, 0x262 },
+    { 0x00000000, 0x00201407, 0x000 },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00211e27, 0x000 },
+    { 0x00000000, 0x00341c47, 0x000 },
+    { 0x00000000, 0x12c00000, 0x267 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x08c00000, 0x26a },
+    { 0x00000000, 0x00201807, 0x000 },
+    { 0x00000000, 0x00600000, 0x2c1 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000000, 0x00342023, 0x000 },
+    { 0x00000000, 0x12c00000, 0x272 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x271 },
+    { 0x00000016, 0x00404811, 0x276 },
+    { 0x00000018, 0x00404811, 0x276 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x275 },
+    { 0x00000017, 0x00404811, 0x276 },
+    { 0x00000019, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00604411, 0x2e9 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x256 },
+    { 0x00000000, 0xc0400400, 0x001 },
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+    { 0x0000ffff, 0xc0280a20, 0x000 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0881a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x00000000, 0x00600000, 0x62e },
+    { 0x00000000, 0xc0600000, 0x2a3 },
+    { 0x00000005, 0x00200a2d, 0x000 },
+    { 0x00000008, 0x00220a22, 0x000 },
+    { 0x0000002b, 0x00201a2d, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00007000, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00311ce6, 0x000 },
+    { 0x0000002a, 0x00201a2d, 0x000 },
+    { 0x0000000c, 0x00221a26, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x06e00000, 0x292 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x0000002b, 0x00203623, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00691ce2, 0x12f },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x29d },
+    { 0x00000001, 0x00333e2f, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000001c, 0x00403627, 0x000 },
+    { 0x0000000c, 0xc0220a20, 0x000 },
+    { 0x00000029, 0x00203622, 0x000 },
+    { 0x00000028, 0xc0403620, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000009, 0x00204811, 0x000 },
+    { 0xa1000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce3, 0x000 },
+    { 0x00000021, 0x00203627, 0x000 },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce4, 0x000 },
+    { 0x00000022, 0x00203627, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120a3, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x00000023, 0x00203627, 0x000 },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x00000024, 0x00803627, 0x000 },
+    { 0x00000021, 0x00203623, 0x000 },
+    { 0x00000022, 0x00203624, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000023, 0x00203627, 0x000 },
+    { 0x00000000, 0x00311cc4, 0x000 },
+    { 0x00000024, 0x00803627, 0x000 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14c00000, 0x2dc },
+    { 0x00000000, 0x00400000, 0x2d9 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2d9 },
+    { 0x00000003, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2dc },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e1, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
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+    { 0x00000000, 0x003120a1, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e2, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000000, 0x00600000, 0x665 },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00600000, 0x65c },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2a7 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x0000001a, 0x00201e2d, 0x000 },
+    { 0x0000001b, 0x0080222d, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca1, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x003808c5, 0x000 },
+    { 0x00000000, 0x00300841, 0x000 },
+    { 0x00000001, 0x00220a22, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000017, 0x0020222d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x318 },
+    { 0xffffffef, 0x00280621, 0x000 },
+    { 0x00000014, 0x0020222d, 0x000 },
+    { 0x0000f8e0, 0x00204411, 0x000 },
+    { 0x00000000, 0x00294901, 0x000 },
+    { 0x00000000, 0x00894901, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x97000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00002257, 0x00204411, 0x000 },
+    { 0x00000003, 0xc0484a20, 0x000 },
+    { 0x0000225d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x642 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x00000001, 0x40304a20, 0x000 },
+    { 0x00000002, 0xc0304a20, 0x000 },
+    { 0x00000001, 0x00530a22, 0x34b },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68a },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x354 },
+    { 0x00000014, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x364 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00604802, 0x36e },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x36a },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35f },
+    { 0x00000028, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5bd },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35f },
+    { 0x0000002c, 0x00203626, 0x000 },
+    { 0x00000049, 0x00201811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x370 },
+    { 0x0000002c, 0x00801a2d, 0x000 },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x00000015, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x386 },
+    { 0x00000006, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3b1 },
+    { 0x00000016, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3b5 },
+    { 0x00000020, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x39c },
+    { 0x0000000f, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a8 },
+    { 0x00000010, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a8 },
+    { 0x0000001e, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x390 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x08000000, 0x00290a22, 0x000 },
+    { 0x00000003, 0x40210e20, 0x000 },
+    { 0x0000000c, 0xc0211220, 0x000 },
+    { 0x00080000, 0x00281224, 0x000 },
+    { 0x00000014, 0xc0221620, 0x000 },
+    { 0x00000000, 0x002914a4, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948a2, 0x000 },
+    { 0x0000a1fe, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68a },
+    { 0x00000015, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x392 },
+    { 0x0000210e, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000017, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68a },
+    { 0x00000003, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x39e },
+    { 0x00002108, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x80000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000010, 0x00204811, 0x000 },
+    { 0x00000000, 0x00200010, 0x000 },
+    { 0x00000000, 0x14c00000, 0x3ae },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000006, 0x00404811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x0000001d, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x3ce },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68a },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x3c0 },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0xbabecafe, 0x00204811, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000004, 0x00404811, 0x000 },
+    { 0x00002170, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000a, 0x00204811, 0x000 },
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+    { 0x80000000, 0x40280e20, 0x000 },
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+    { 0x00000001, 0x00204811, 0x000 },
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+    { 0x00000001, 0x00210222, 0x000 },
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+    { 0x00040000, 0x18e00c11, 0x4ec },
+    { 0x00000001, 0x00333e2f, 0x000 },
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+    { 0xefffffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x004938ce, 0x678 },
+    { 0x00000001, 0x40280a20, 0x000 },
+    { 0x00000006, 0x40280e20, 0x000 },
+    { 0x00000300, 0xc0281220, 0x000 },
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+    { 0x00000000, 0x14c00000, 0x563 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
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+    { 0x00040000, 0x00694622, 0x68a },
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+    { 0x00000000, 0x0cc00000, 0x56b },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00002258, 0x00300a24, 0x000 },
+    { 0x00040000, 0x00694622, 0x68a },
+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x579 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x56f },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0xc0400000, 0x579 },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x577 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000216d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0604800, 0x68f },
+    { 0x00000000, 0x00401c10, 0x579 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x57b },
+    { 0x00000000, 0x00600000, 0x5c6 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x58c },
+    { 0x0000a2b7, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x68a },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000a2c4, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x58a },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x59d },
+    { 0x0000a2bb, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x68a },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000a2c5, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x59b },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5ae },
+    { 0x0000a2bf, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x68a },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000a2c6, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5ac },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x0000a2c3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x68a },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000a2c7, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5bb },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x85000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x0000304a, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x5c1 },
+    { 0xa4000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0xc0600000, 0x5c6 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000002c, 0x00203621, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5cd },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000030, 0x00403621, 0x5e0 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x5e0 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a092, 0x00604411, 0x68a },
+    { 0x00000031, 0x00203630, 0x000 },
+    { 0x0004a093, 0x00604411, 0x68a },
+    { 0x00000032, 0x00203630, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x68a },
+    { 0x00000033, 0x00203630, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x68a },
+    { 0x00000034, 0x00203630, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x68a },
+    { 0x00000035, 0x00203630, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x68a },
+    { 0x00000036, 0x00203630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x88000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000001, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x629 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x629 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x602 },
+    { 0x0000a092, 0x00204411, 0x000 },
+    { 0x00000031, 0x00204a2d, 0x000 },
+    { 0x0000a093, 0x00204411, 0x000 },
+    { 0x00000032, 0x00204a2d, 0x000 },
+    { 0x0000a2b6, 0x00204411, 0x000 },
+    { 0x00000033, 0x00204a2d, 0x000 },
+    { 0x0000a2ba, 0x00204411, 0x000 },
+    { 0x00000034, 0x00204a2d, 0x000 },
+    { 0x0000a2be, 0x00204411, 0x000 },
+    { 0x00000035, 0x00204a2d, 0x000 },
+    { 0x0000a2c2, 0x00204411, 0x000 },
+    { 0x00000036, 0x00204a2d, 0x000 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x000001ff, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x628 },
+    { 0x00000000, 0x00210221, 0x000 },
+    { 0x00000000, 0x14c00000, 0x60b },
+    { 0x0004a003, 0x00604411, 0x68a },
+    { 0x0000a003, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x14c00000, 0x610 },
+    { 0x0004a010, 0x00604411, 0x68a },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x628 },
+    { 0x0004a011, 0x00604411, 0x68a },
+    { 0x0000a011, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a012, 0x00604411, 0x68a },
+    { 0x0000a012, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a013, 0x00604411, 0x68a },
+    { 0x0000a013, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a014, 0x00604411, 0x68a },
+    { 0x0000a014, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a015, 0x00604411, 0x68a },
+    { 0x0000a015, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a016, 0x00604411, 0x68a },
+    { 0x0000a016, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a017, 0x00604411, 0x68a },
+    { 0x0000a017, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000002c, 0x0080062d, 0x000 },
+    { 0xff000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000002, 0x00804811, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x63a },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000002, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x638 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x00001000, 0x00200811, 0x000 },
+    { 0x0000002b, 0x00203622, 0x000 },
+    { 0x00000000, 0x00600000, 0x63e },
+    { 0x00000000, 0x00600000, 0x5c6 },
+    { 0x98000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0600000, 0x63e },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000022, 0x00204811, 0x000 },
+    { 0x89000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00404811, 0x62a },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x62a },
+    { 0x00000000, 0x00600000, 0x659 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0xc0204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x09800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68a },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x00000004, 0x00404c11, 0x653 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000004, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffffb, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffff7, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x01800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68a },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x689 },
+    { 0x00000010, 0x00404c11, 0x66f },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x38c00000, 0x000 },
+    { 0x0000001d, 0x00200a2d, 0x000 },
+    { 0x0000001e, 0x00200e2d, 0x000 },
+    { 0x0000001f, 0x0020122d, 0x000 },
+    { 0x00000020, 0x0020162d, 0x000 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x002f0064, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x688 },
+    { 0x00000003, 0x00281a22, 0x000 },
+    { 0x00000008, 0x00221222, 0x000 },
+    { 0xfffff000, 0x00281224, 0x000 },
+    { 0x00000000, 0x002910c4, 0x000 },
+    { 0x0000001f, 0x00403624, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x68a },
+    { 0x9f000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x68d },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x68f },
+    { 0x9e000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x692 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0xc0204411, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000024, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000022, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x014204ff, 0x05bd0250, 0x000 },
+    { 0x01c30168, 0x043f05bd, 0x000 },
+    { 0x02250209, 0x02500151, 0x000 },
+    { 0x02230245, 0x02a00241, 0x000 },
+    { 0x03d705bd, 0x05bd05bd, 0x000 },
+    { 0x06460647, 0x031f05bd, 0x000 },
+    { 0x05bd05c2, 0x03200340, 0x000 },
+    { 0x032a0282, 0x03420334, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd054e, 0x05bd05bd, 0x000 },
+    { 0x03ba05bd, 0x04b80344, 0x000 },
+    { 0x0497044d, 0x043d05bd, 0x000 },
+    { 0x04cd05bd, 0x044104da, 0x000 },
+    { 0x044d0504, 0x03510375, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd05bd, 0x063c05c4, 0x000 },
+    { 0x05bd05bd, 0x000705bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x03f803ed, 0x04080406, 0x000 },
+    { 0x040e040a, 0x040c0410, 0x000 },
+    { 0x041c0418, 0x04240420, 0x000 },
+    { 0x042c0428, 0x04340430, 0x000 },
+    { 0x05bd05bd, 0x043805bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x00020676, 0x06940006, 0x000 },
+};
+
+static const u32 RV630_pfp_microcode[]={
+0xca0400,
+0xa00000,
+0x7e828b,
+0x7c038b,
+0x8001b8,
+0x7c038b,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xc41838,
+0xca2400,
+0xca2800,
+0x9581a8,
+0xc41c3a,
+0xc3c000,
+0xca0800,
+0xca0c00,
+0x7c744b,
+0xc20005,
+0x99c000,
+0xc41c3a,
+0x7c744c,
+0xc0fff0,
+0x042c04,
+0x309002,
+0x7d2500,
+0x351402,
+0x7d350b,
+0x255403,
+0x7cd580,
+0x259c03,
+0x95c004,
+0xd5001b,
+0x7eddc1,
+0x7d9d80,
+0xd6801b,
+0xd5801b,
+0xd4401e,
+0xd5401e,
+0xd6401e,
+0xd6801e,
+0xd4801e,
+0xd4c01e,
+0x9783d3,
+0xd5c01e,
+0xca0800,
+0x80001a,
+0xca0c00,
+0xe4011e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xe4013e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca1800,
+0xd4401e,
+0xd5801e,
+0x800053,
+0xd40075,
+0xd4401e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd48019,
+0xd4c018,
+0xd50017,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xe2001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0xd48060,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xd48061,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xca0c00,
+0xd4401e,
+0xd48016,
+0xd4c016,
+0xd4801e,
+0x8001b8,
+0xd4c01e,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x948004,
+0xca1400,
+0xe420f3,
+0xd42013,
+0xd56065,
+0xd4e01c,
+0xd5201c,
+0xd5601c,
+0x800000,
+0x062001,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9483f7,
+0xca1400,
+0xe420f3,
+0x800079,
+0xd42013,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9883ef,
+0xca1400,
+0xd40064,
+0x80008d,
+0x000000,
+0xc41432,
+0xc61843,
+0xc4082f,
+0x954005,
+0xc40c30,
+0xd4401e,
+0x800000,
+0xee001e,
+0x9583f5,
+0xc41031,
+0xd44033,
+0xd52065,
+0xd4a01c,
+0xd4e01c,
+0xd5201c,
+0xe4015e,
+0xd4001e,
+0x800000,
+0x062001,
+0xca1800,
+0x0a2001,
+0xd60076,
+0xc40836,
+0x988007,
+0xc61045,
+0x950110,
+0xd4001f,
+0xd46062,
+0x800000,
+0xd42062,
+0xcc3835,
+0xcc1433,
+0x8401bb,
+0xd40072,
+0xd5401e,
+0x800000,
+0xee001e,
+0xe2001a,
+0x8401bb,
+0xe2001a,
+0xcc104b,
+0xcc0447,
+0x2c9401,
+0x7d098b,
+0x984005,
+0x7d15cb,
+0xd4001a,
+0x8001b8,
+0xd4006d,
+0x344401,
+0xcc0c48,
+0x98403a,
+0xcc2c4a,
+0x958004,
+0xcc0449,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0x282801,
+0x8400f0,
+0xcc1003,
+0x98801b,
+0x04380c,
+0x8400f0,
+0xcc1003,
+0x988017,
+0x043808,
+0x8400f0,
+0xcc1003,
+0x988013,
+0x043804,
+0x8400f0,
+0xcc1003,
+0x988014,
+0xcc104c,
+0x9a8009,
+0xcc144d,
+0x9840dc,
+0xd4006d,
+0xcc1848,
+0xd5001a,
+0xd5401a,
+0x8000c9,
+0xd5801a,
+0x96c0d5,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0x9ac003,
+0xd4006d,
+0xd4006e,
+0x800000,
+0xec007f,
+0x9ac0cc,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0x7d9103,
+0x7dd583,
+0x7d190c,
+0x35cc1f,
+0x35701f,
+0x7cf0cb,
+0x7cd08b,
+0x880000,
+0x7e8e8b,
+0x95c004,
+0xd4006e,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0xcc0803,
+0xcc0c03,
+0xcc1003,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0xcc2403,
+0xcc2803,
+0x35c41f,
+0x36b01f,
+0x7c704b,
+0x34f01f,
+0x7c704b,
+0x35701f,
+0x7c704b,
+0x7d8881,
+0x7dccc1,
+0x7e5101,
+0x7e9541,
+0x7c9082,
+0x7cd4c2,
+0x7c848b,
+0x9ac003,
+0x7c8c8b,
+0x2c8801,
+0x98809e,
+0xd4006d,
+0x98409c,
+0xd4006e,
+0xcc084c,
+0xcc0c4d,
+0xcc1048,
+0xd4801a,
+0xd4c01a,
+0x800101,
+0xd5001a,
+0xcc0832,
+0xd40032,
+0x9482d9,
+0xca0c00,
+0xd4401e,
+0x800000,
+0xd4001e,
+0xe4011e,
+0xd4001e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd4401e,
+0xca1400,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xd5401e,
+0xd54034,
+0x800000,
+0xee001e,
+0x280404,
+0xe2001a,
+0xe2001a,
+0xd4401a,
+0xca3800,
+0xcc0803,
+0xcc0c03,
+0xcc0c03,
+0xcc0c03,
+0x9882bd,
+0x000000,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0400,
+0xc2ff00,
+0xcc0834,
+0xc13fff,
+0x7c74cb,
+0x7cc90b,
+0x7d010f,
+0x9902b0,
+0x7c738b,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0800,
+0x281900,
+0x7d898b,
+0x958014,
+0x281404,
+0xca0c00,
+0xca1000,
+0xca1c00,
+0xca2400,
+0xe2001f,
+0xd4c01a,
+0xd5001a,
+0xd5401a,
+0xcc1803,
+0xcc2c03,
+0xcc2c03,
+0xcc2c03,
+0x7da58b,
+0x7d9c47,
+0x984297,
+0x000000,
+0x800161,
+0xd4c01a,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0x248c06,
+0x0ccc06,
+0x98c006,
+0xcc104e,
+0x990004,
+0xd40073,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xca0800,
+0xca0c00,
+0x34d018,
+0x251001,
+0x950021,
+0xc17fff,
+0xca1000,
+0xca1400,
+0xca1800,
+0xd4801d,
+0xd4c01d,
+0x7db18b,
+0xc14202,
+0xc2c001,
+0xd5801d,
+0x34dc0e,
+0x7d5d4c,
+0x7f734c,
+0xd7401e,
+0xd5001e,
+0xd5401e,
+0xc14200,
+0xc2c000,
+0x099c01,
+0x31dc10,
+0x7f5f4c,
+0x7f734c,
+0x042802,
+0x7d8380,
+0xd5a86f,
+0xd58066,
+0xd7401e,
+0xec005e,
+0xc82402,
+0xc82402,
+0x8001b8,
+0xd60076,
+0xd4401e,
+0xd4801e,
+0xd4c01e,
+0x800000,
+0xee001e,
+0x800000,
+0xee001f,
+0xd4001f,
+0x800000,
+0xd4001f,
+0xd4001f,
+0x880000,
+0xd4001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x010171,
+0x020178,
+0x03008f,
+0x04007f,
+0x050003,
+0x06003f,
+0x070032,
+0x08012c,
+0x090046,
+0x0a0036,
+0x1001b6,
+0x1700a2,
+0x22013a,
+0x230149,
+0x2000b4,
+0x240125,
+0x27004d,
+0x28006a,
+0x2a0060,
+0x2b0052,
+0x2f0065,
+0x320087,
+0x34017f,
+0x3c0156,
+0x3f0072,
+0x41018c,
+0x44012e,
+0x550173,
+0x56017a,
+0x60000b,
+0x610034,
+0x620038,
+0x630038,
+0x640038,
+0x650038,
+0x660038,
+0x670038,
+0x68003a,
+0x690041,
+0x6a0048,
+0x6b0048,
+0x6c0048,
+0x6d0048,
+0x6e0048,
+0x6f0048,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+};
+
+static const u32 RV635_cp_microcode[][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00000000, 0x00e00000, 0x000 },
+    { 0x00010000, 0xc0294620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x00000000, 0x00600000, 0x62e },
+    { 0x00000000, 0x00600000, 0x642 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000f00, 0x00281622, 0x000 },
+    { 0x00000008, 0x00211625, 0x000 },
+    { 0x00000018, 0x00203625, 0x000 },
+    { 0x8d000000, 0x00204411, 0x000 },
+    { 0x00000004, 0x002f0225, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x018 },
+    { 0x00412000, 0x00404811, 0x019 },
+    { 0x00422000, 0x00204811, 0x000 },
+    { 0x8e000000, 0x00204411, 0x000 },
+    { 0x00000028, 0x00204a2d, 0x000 },
+    { 0x90000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x0000000c, 0x00211622, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000019, 0x00211a22, 0x000 },
+    { 0x00000004, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002914c5, 0x000 },
+    { 0x00000019, 0x00203625, 0x000 },
+    { 0x00000000, 0x003a1402, 0x000 },
+    { 0x00000016, 0x00211625, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0xfffffffc, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002914a3, 0x000 },
+    { 0x00000017, 0x00203625, 0x000 },
+    { 0x00008000, 0x00280e22, 0x000 },
+    { 0x00000007, 0x00220e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x20000000, 0x00280e22, 0x000 },
+    { 0x00000006, 0x00210e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00220222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x038 },
+    { 0x00000000, 0x2ee00000, 0x035 },
+    { 0x00000000, 0x2ce00000, 0x037 },
+    { 0x00000000, 0x00400e2d, 0x039 },
+    { 0x00000008, 0x00200e2d, 0x000 },
+    { 0x00000009, 0x0040122d, 0x046 },
+    { 0x00000001, 0x00400e2d, 0x039 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x03e },
+    { 0x00000008, 0x00401c11, 0x041 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x0000000f, 0x00281e27, 0x000 },
+    { 0x00000003, 0x00221e27, 0x000 },
+    { 0x7fc00000, 0x00281a23, 0x000 },
+    { 0x00000014, 0x00211a26, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000008, 0x00221a26, 0x000 },
+    { 0x00000000, 0x00290cc7, 0x000 },
+    { 0x00000027, 0x00203624, 0x000 },
+    { 0x00007f00, 0x00281221, 0x000 },
+    { 0x00001400, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04b },
+    { 0x00000001, 0x00290e23, 0x000 },
+    { 0x0000000e, 0x00203623, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfff80000, 0x00294a23, 0x000 },
+    { 0x00000000, 0x003a2c02, 0x000 },
+    { 0x00000002, 0x00220e2b, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x0000000f, 0x00203623, 0x000 },
+    { 0x00001fff, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00204a2d, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000029, 0x00200e2d, 0x000 },
+    { 0x060a0200, 0x00294a23, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x061 },
+    { 0x00000000, 0x2ee00000, 0x05f },
+    { 0x00000000, 0x2ce00000, 0x05e },
+    { 0x00000000, 0x00400e2d, 0x062 },
+    { 0x00000001, 0x00400e2d, 0x062 },
+    { 0x0000000a, 0x00200e2d, 0x000 },
+    { 0x0000000b, 0x0040122d, 0x06a },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x7fc00000, 0x00281623, 0x000 },
+    { 0x00000014, 0x00211625, 0x000 },
+    { 0x00000001, 0x00331625, 0x000 },
+    { 0x80000000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00290ca3, 0x000 },
+    { 0x3ffffc00, 0x00290e23, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x06d },
+    { 0x00000100, 0x00401c11, 0x070 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x000000f0, 0x00281e27, 0x000 },
+    { 0x00000004, 0x00221e27, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0xfffff0ff, 0x00281a30, 0x000 },
+    { 0x0000a028, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e6, 0x000 },
+    { 0x0000a018, 0x00204411, 0x000 },
+    { 0x3fffffff, 0x00284a23, 0x000 },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000030, 0x0020162d, 0x000 },
+    { 0x00000002, 0x00291625, 0x000 },
+    { 0x00000030, 0x00203625, 0x000 },
+    { 0x00000025, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a3, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x083 },
+    { 0x00000026, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a4, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x084 },
+    { 0x00000000, 0x00400000, 0x08a },
+    { 0x00000025, 0x00203623, 0x000 },
+    { 0x00000026, 0x00203624, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x08a },
+    { 0x00000000, 0x00600000, 0x665 },
+    { 0x00000000, 0x00600000, 0x659 },
+    { 0x00000002, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x08d },
+    { 0x00000012, 0xc0403620, 0x093 },
+    { 0x00000000, 0x2ee00000, 0x091 },
+    { 0x00000000, 0x2ce00000, 0x090 },
+    { 0x00000002, 0x00400e2d, 0x092 },
+    { 0x00000003, 0x00400e2d, 0x092 },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000012, 0x00203623, 0x000 },
+    { 0x00000003, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x098 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x0a0 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x2ee00000, 0x09e },
+    { 0x00000000, 0x2ce00000, 0x09d },
+    { 0x00000002, 0x00400e2d, 0x09f },
+    { 0x00000003, 0x00400e2d, 0x09f },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x003f0000, 0x00280e23, 0x000 },
+    { 0x00000010, 0x00210e23, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x0000001e, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0a7 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x0000001f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0aa },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000008, 0x00210e2b, 0x000 },
+    { 0x0000007f, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0e1 },
+    { 0x00000000, 0x27000000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b3 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00221e30, 0x000 },
+    { 0x99800000, 0x00204411, 0x000 },
+    { 0x00000004, 0x0020122d, 0x000 },
+    { 0x00000008, 0x00221224, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00291ce4, 0x000 },
+    { 0x00000000, 0x00604807, 0x12f },
+    { 0x9b000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x9c000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x0033146f, 0x000 },
+    { 0x00000001, 0x00333e23, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00203c05, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e007, 0x00204411, 0x000 },
+    { 0x0000000f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0cb },
+    { 0x00f8ff08, 0x00204811, 0x000 },
+    { 0x98000000, 0x00404811, 0x0dc },
+    { 0x000000f0, 0x00280e22, 0x000 },
+    { 0x000000a0, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x0da },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d5 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d4 },
+    { 0x00003f00, 0x00400c11, 0x0d6 },
+    { 0x00001f00, 0x00400c11, 0x0d6 },
+    { 0x00000f00, 0x00200c11, 0x000 },
+    { 0x00380009, 0x00294a23, 0x000 },
+    { 0x3f000000, 0x00280e2b, 0x000 },
+    { 0x00000002, 0x00220e23, 0x000 },
+    { 0x00000007, 0x00494a23, 0x0dc },
+    { 0x00380f09, 0x00204811, 0x000 },
+    { 0x68000007, 0x00204811, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000a202, 0x00204411, 0x000 },
+    { 0x00ff0000, 0x00280e22, 0x000 },
+    { 0x00000080, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00200e2d, 0x000 },
+    { 0x00000026, 0x0020122d, 0x000 },
+    { 0x00000000, 0x002f0083, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0ea },
+    { 0x00000000, 0x00600000, 0x65f },
+    { 0x00000000, 0x00400000, 0x0eb },
+    { 0x00000000, 0x00600000, 0x662 },
+    { 0x00000007, 0x0020222d, 0x000 },
+    { 0x00000005, 0x00220e22, 0x000 },
+    { 0x00100000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x000000ef, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000003, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x0f8 },
+    { 0x0000000b, 0x00210228, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0f8 },
+    { 0x00000400, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000001c, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0fd },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000001e, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x10b },
+    { 0x0000a30f, 0x00204411, 0x000 },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x104 },
+    { 0xffffffff, 0x00404811, 0x10b },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x107 },
+    { 0x0000ffff, 0x00404811, 0x10b },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x10a },
+    { 0x000000ff, 0x00404811, 0x10b },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0002c400, 0x00204411, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x112 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000018, 0x40224a20, 0x000 },
+    { 0x00000010, 0xc0424a20, 0x114 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000000a, 0x00201011, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x11b },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00531224, 0x117 },
+    { 0xffbfffff, 0x00283a2e, 0x000 },
+    { 0x0000001b, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x12e },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0x00000018, 0x00220e30, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e00e, 0x00204411, 0x000 },
+    { 0x07f8ff08, 0x00204811, 0x000 },
+    { 0x00000000, 0x00294a23, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x00800000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68a },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x689 },
+    { 0x00000004, 0x00404c11, 0x135 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x0000001c, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68a },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x13c },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40280620, 0x000 },
+    { 0x00000010, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x00341461, 0x000 },
+    { 0x00000000, 0x00741882, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x147 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0681a20, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x158 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000001, 0x00300a2f, 0x000 },
+    { 0x00000001, 0x00210a22, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600000, 0x18f },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00202c08, 0x000 },
+    { 0x00000000, 0x00202411, 0x000 },
+    { 0x00000000, 0x00202811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000002, 0x00221e29, 0x000 },
+    { 0x00000000, 0x007048eb, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000001, 0x40330620, 0x000 },
+    { 0x00000000, 0xc0302409, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x181 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x186 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x186 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000001, 0x00530621, 0x182 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0604800, 0x197 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000011, 0x0020062d, 0x000 },
+    { 0x00000000, 0x0078042a, 0x2fb },
+    { 0x00000000, 0x00202809, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x174 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x194 },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x46000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x19b },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00804811, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40281620, 0x000 },
+    { 0x00000010, 0xc0811a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000008, 0x00221e30, 0x000 },
+    { 0x00000029, 0x00201a2d, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfffbff09, 0x00204811, 0x000 },
+    { 0x0000000f, 0x0020222d, 0x000 },
+    { 0x00001fff, 0x00294a28, 0x000 },
+    { 0x00000006, 0x0020222d, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000100, 0x00201811, 0x000 },
+    { 0x00000008, 0x00621e28, 0x12f },
+    { 0x00000008, 0x00822228, 0x000 },
+    { 0x0002c000, 0x00204411, 0x000 },
+    { 0x00000015, 0x00600e2d, 0x1bd },
+    { 0x00000016, 0x00600e2d, 0x1bd },
+    { 0x0000c008, 0x00204411, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1b9 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x39000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00804802, 0x000 },
+    { 0x00000018, 0x00202e2d, 0x000 },
+    { 0x00000000, 0x003b0d63, 0x000 },
+    { 0x00000008, 0x00224a23, 0x000 },
+    { 0x00000010, 0x00224a23, 0x000 },
+    { 0x00000018, 0x00224a23, 0x000 },
+    { 0x00000000, 0x00804803, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000007, 0x0021062f, 0x000 },
+    { 0x00000013, 0x00200a2d, 0x000 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000ffff, 0x40282220, 0x000 },
+    { 0x0000000f, 0x00262228, 0x000 },
+    { 0x00000010, 0x40212620, 0x000 },
+    { 0x0000000f, 0x00262629, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1e0 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000081, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000080, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1dc },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1d8 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000001f, 0x00280a22, 0x000 },
+    { 0x0000001f, 0x00282a2a, 0x000 },
+    { 0x00000001, 0x00530621, 0x1d1 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000002, 0x00304a2f, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x00301e2f, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1e5 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x0000000f, 0x00260e23, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000000f, 0x00261224, 0x000 },
+    { 0x00000000, 0x00201411, 0x000 },
+    { 0x00000000, 0x00601811, 0x2bb },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022b, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1f8 },
+    { 0x00000010, 0x00221628, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a29, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000010, 0x00221623, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a24, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x00731503, 0x205 },
+    { 0x00000000, 0x00201805, 0x000 },
+    { 0x00000000, 0x00731524, 0x205 },
+    { 0x00000000, 0x002d14c5, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00000000, 0x00202003, 0x000 },
+    { 0x00000000, 0x00802404, 0x000 },
+    { 0x0000000f, 0x00210225, 0x000 },
+    { 0x00000000, 0x14c00000, 0x689 },
+    { 0x00000000, 0x002b1405, 0x000 },
+    { 0x00000001, 0x00901625, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00294a22, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a21, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000ffff, 0x40281220, 0x000 },
+    { 0x00000010, 0xc0211a20, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211620, 0x000 },
+    { 0x00000000, 0x00741465, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00000001, 0x00330621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x219 },
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+    { 0x00000000, 0x0cc00000, 0x212 },
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+    { 0x00000000, 0x00600000, 0x62e },
+    { 0x00000000, 0x00600000, 0x642 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00000000, 0x00600000, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
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+    { 0x00000000, 0x0ae00000, 0x232 },
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+    { 0x00000000, 0x00400000, 0x236 },
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+    { 0x00000000, 0x0ce00000, 0x236 },
+    { 0x00000000, 0xc0404800, 0x233 },
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+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x00600411, 0x2fb },
+    { 0x00000000, 0xc0400400, 0x001 },
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+    { 0x0000a00c, 0x00204411, 0x000 },
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+    { 0x00000000, 0xc0404800, 0x000 },
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+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x24c },
+    { 0x00000014, 0x0020222d, 0x000 },
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+    { 0x00000000, 0xc0204800, 0x000 },
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+    { 0x00000000, 0x00600811, 0x1b2 },
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+    { 0x00000000, 0x00600000, 0x27c },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000001, 0x00211e27, 0x000 },
+    { 0x00000000, 0x14e00000, 0x26a },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x0000ffff, 0x00281e27, 0x000 },
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+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x08c00000, 0x26a },
+    { 0x00000000, 0x00201807, 0x000 },
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+    { 0x00000000, 0x00342023, 0x000 },
+    { 0x00000000, 0x12c00000, 0x272 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x271 },
+    { 0x00000016, 0x00404811, 0x276 },
+    { 0x00000018, 0x00404811, 0x276 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x275 },
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+    { 0x00000019, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00604411, 0x2e9 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x256 },
+    { 0x00000000, 0xc0400400, 0x001 },
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+    { 0x0000ffff, 0xc0281220, 0x000 },
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+    { 0x0000ffff, 0xc0881a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x00000000, 0x00600000, 0x62e },
+    { 0x00000000, 0xc0600000, 0x2a3 },
+    { 0x00000005, 0x00200a2d, 0x000 },
+    { 0x00000008, 0x00220a22, 0x000 },
+    { 0x0000002b, 0x00201a2d, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00007000, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00311ce6, 0x000 },
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+    { 0x00000000, 0x002f00e6, 0x000 },
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+    { 0x00000000, 0x00691ce2, 0x12f },
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+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x29d },
+    { 0x00000001, 0x00333e2f, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
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+    { 0x00000009, 0x00204811, 0x000 },
+    { 0xa1000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce3, 0x000 },
+    { 0x00000021, 0x00203627, 0x000 },
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+    { 0x00000000, 0x00311ca3, 0x000 },
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+    { 0x00000000, 0x00311cc4, 0x000 },
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+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14c00000, 0x2dc },
+    { 0x00000000, 0x00400000, 0x2d9 },
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+    { 0x0000001b, 0x00203628, 0x000 },
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+    { 0x00000000, 0x02c00000, 0x2dc },
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+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000000, 0x00600000, 0x665 },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00600000, 0x65c },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2a7 },
+    { 0x00000000, 0x00400000, 0x2de },
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+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
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+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca1, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
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+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
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+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
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+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
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+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x003808c5, 0x000 },
+    { 0x00000000, 0x00300841, 0x000 },
+    { 0x00000001, 0x00220a22, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
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+    { 0x00000000, 0x14c00000, 0x318 },
+    { 0xffffffef, 0x00280621, 0x000 },
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+    { 0x00000000, 0x00294901, 0x000 },
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+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x97000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
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+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00002257, 0x00204411, 0x000 },
+    { 0x00000003, 0xc0484a20, 0x000 },
+    { 0x0000225d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x642 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x00000001, 0x40304a20, 0x000 },
+    { 0x00000002, 0xc0304a20, 0x000 },
+    { 0x00000001, 0x00530a22, 0x34b },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68a },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x354 },
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+    { 0x00000000, 0x0cc00000, 0x364 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00604802, 0x36e },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x36a },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35f },
+    { 0x00000028, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5bd },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35f },
+    { 0x0000002c, 0x00203626, 0x000 },
+    { 0x00000049, 0x00201811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x370 },
+    { 0x0000002c, 0x00801a2d, 0x000 },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x00000015, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x386 },
+    { 0x00000006, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3b1 },
+    { 0x00000016, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3b5 },
+    { 0x00000020, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x39c },
+    { 0x0000000f, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a8 },
+    { 0x00000010, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a8 },
+    { 0x0000001e, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x390 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x08000000, 0x00290a22, 0x000 },
+    { 0x00000003, 0x40210e20, 0x000 },
+    { 0x0000000c, 0xc0211220, 0x000 },
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+    { 0x00000014, 0xc0221620, 0x000 },
+    { 0x00000000, 0x002914a4, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948a2, 0x000 },
+    { 0x0000a1fe, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68a },
+    { 0x00000015, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x392 },
+    { 0x0000210e, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000017, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x68a },
+    { 0x00000003, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x39e },
+    { 0x00002108, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x80000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000010, 0x00204811, 0x000 },
+    { 0x00000000, 0x00200010, 0x000 },
+    { 0x00000000, 0x14c00000, 0x3ae },
+    { 0x00000000, 0x00400000, 0x000 },
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+    { 0x00000020, 0x00203627, 0x000 },
+    { 0x00000002, 0x00221624, 0x000 },
+    { 0x00000000, 0x003014a8, 0x000 },
+    { 0x0000001e, 0x00203625, 0x000 },
+    { 0x00000003, 0x00211a24, 0x000 },
+    { 0x10000000, 0x00281a26, 0x000 },
+    { 0xefffffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x004938ce, 0x678 },
+    { 0x00000001, 0x40280a20, 0x000 },
+    { 0x00000006, 0x40280e20, 0x000 },
+    { 0x00000300, 0xc0281220, 0x000 },
+    { 0x00000008, 0x00211224, 0x000 },
+    { 0x00000000, 0xc0201620, 0x000 },
+    { 0x00000000, 0xc0201a20, 0x000 },
+    { 0x00000000, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x563 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00002258, 0x00300a24, 0x000 },
+    { 0x00040000, 0x00694622, 0x68a },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00020000, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x56b },
+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x579 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x56b },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00002258, 0x00300a24, 0x000 },
+    { 0x00040000, 0x00694622, 0x68a },
+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x579 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x56f },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0xc0400000, 0x579 },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x577 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000216d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0604800, 0x68f },
+    { 0x00000000, 0x00401c10, 0x579 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x57b },
+    { 0x00000000, 0x00600000, 0x5c6 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x58c },
+    { 0x0000a2b7, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x68a },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000a2c4, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x58a },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x59d },
+    { 0x0000a2bb, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x68a },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000a2c5, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x59b },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5ae },
+    { 0x0000a2bf, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x68a },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000a2c6, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5ac },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x0000a2c3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x68a },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000a2c7, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5bb },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x85000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x0000304a, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x5c1 },
+    { 0xa4000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0xc0600000, 0x5c6 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000002c, 0x00203621, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5cd },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000030, 0x00403621, 0x5e0 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x5e0 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a092, 0x00604411, 0x68a },
+    { 0x00000031, 0x00203630, 0x000 },
+    { 0x0004a093, 0x00604411, 0x68a },
+    { 0x00000032, 0x00203630, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x68a },
+    { 0x00000033, 0x00203630, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x68a },
+    { 0x00000034, 0x00203630, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x68a },
+    { 0x00000035, 0x00203630, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x68a },
+    { 0x00000036, 0x00203630, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x88000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000001, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x629 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x629 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x602 },
+    { 0x0000a092, 0x00204411, 0x000 },
+    { 0x00000031, 0x00204a2d, 0x000 },
+    { 0x0000a093, 0x00204411, 0x000 },
+    { 0x00000032, 0x00204a2d, 0x000 },
+    { 0x0000a2b6, 0x00204411, 0x000 },
+    { 0x00000033, 0x00204a2d, 0x000 },
+    { 0x0000a2ba, 0x00204411, 0x000 },
+    { 0x00000034, 0x00204a2d, 0x000 },
+    { 0x0000a2be, 0x00204411, 0x000 },
+    { 0x00000035, 0x00204a2d, 0x000 },
+    { 0x0000a2c2, 0x00204411, 0x000 },
+    { 0x00000036, 0x00204a2d, 0x000 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x000001ff, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x628 },
+    { 0x00000000, 0x00210221, 0x000 },
+    { 0x00000000, 0x14c00000, 0x60b },
+    { 0x0004a003, 0x00604411, 0x68a },
+    { 0x0000a003, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x14c00000, 0x610 },
+    { 0x0004a010, 0x00604411, 0x68a },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x628 },
+    { 0x0004a011, 0x00604411, 0x68a },
+    { 0x0000a011, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a012, 0x00604411, 0x68a },
+    { 0x0000a012, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a013, 0x00604411, 0x68a },
+    { 0x0000a013, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a014, 0x00604411, 0x68a },
+    { 0x0000a014, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a015, 0x00604411, 0x68a },
+    { 0x0000a015, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a016, 0x00604411, 0x68a },
+    { 0x0000a016, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a017, 0x00604411, 0x68a },
+    { 0x0000a017, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x0000002c, 0x0080062d, 0x000 },
+    { 0xff000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000002, 0x00804811, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x63a },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000002, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x638 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x68a },
+    { 0x00001000, 0x00200811, 0x000 },
+    { 0x0000002b, 0x00203622, 0x000 },
+    { 0x00000000, 0x00600000, 0x63e },
+    { 0x00000000, 0x00600000, 0x5c6 },
+    { 0x98000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0600000, 0x63e },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000022, 0x00204811, 0x000 },
+    { 0x89000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00404811, 0x62a },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x62a },
+    { 0x00000000, 0x00600000, 0x659 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0xc0204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x09800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68a },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x00000004, 0x00404c11, 0x653 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000004, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffffb, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffff7, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00008000, 0x00204811, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36e },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x01800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004217f, 0x00604411, 0x68a },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x689 },
+    { 0x00000010, 0x00404c11, 0x66f },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x38c00000, 0x000 },
+    { 0x0000001d, 0x00200a2d, 0x000 },
+    { 0x0000001e, 0x00200e2d, 0x000 },
+    { 0x0000001f, 0x0020122d, 0x000 },
+    { 0x00000020, 0x0020162d, 0x000 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x002f0064, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x688 },
+    { 0x00000003, 0x00281a22, 0x000 },
+    { 0x00000008, 0x00221222, 0x000 },
+    { 0xfffff000, 0x00281224, 0x000 },
+    { 0x00000000, 0x002910c4, 0x000 },
+    { 0x0000001f, 0x00403624, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x68a },
+    { 0x9f000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x68d },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x68f },
+    { 0x9e000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x692 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0xc0204411, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000024, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000022, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x014204ff, 0x05bd0250, 0x000 },
+    { 0x01c30168, 0x043f05bd, 0x000 },
+    { 0x02250209, 0x02500151, 0x000 },
+    { 0x02230245, 0x02a00241, 0x000 },
+    { 0x03d705bd, 0x05bd05bd, 0x000 },
+    { 0x06460647, 0x031f05bd, 0x000 },
+    { 0x05bd05c2, 0x03200340, 0x000 },
+    { 0x032a0282, 0x03420334, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd054e, 0x05bd05bd, 0x000 },
+    { 0x03ba05bd, 0x04b80344, 0x000 },
+    { 0x0497044d, 0x043d05bd, 0x000 },
+    { 0x04cd05bd, 0x044104da, 0x000 },
+    { 0x044d0504, 0x03510375, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd05bd, 0x063c05c4, 0x000 },
+    { 0x05bd05bd, 0x000705bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x03f803ed, 0x04080406, 0x000 },
+    { 0x040e040a, 0x040c0410, 0x000 },
+    { 0x041c0418, 0x04240420, 0x000 },
+    { 0x042c0428, 0x04340430, 0x000 },
+    { 0x05bd05bd, 0x043805bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x05bd05bd, 0x05bd05bd, 0x000 },
+    { 0x00020676, 0x06940006, 0x000 },
+};
+
+static const u32 RV635_pfp_microcode[]={
+0xca0400,
+0xa00000,
+0x7e828b,
+0x7c038b,
+0x8001b8,
+0x7c038b,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xc41838,
+0xca2400,
+0xca2800,
+0x9581a8,
+0xc41c3a,
+0xc3c000,
+0xca0800,
+0xca0c00,
+0x7c744b,
+0xc20005,
+0x99c000,
+0xc41c3a,
+0x7c744c,
+0xc0fff0,
+0x042c04,
+0x309002,
+0x7d2500,
+0x351402,
+0x7d350b,
+0x255403,
+0x7cd580,
+0x259c03,
+0x95c004,
+0xd5001b,
+0x7eddc1,
+0x7d9d80,
+0xd6801b,
+0xd5801b,
+0xd4401e,
+0xd5401e,
+0xd6401e,
+0xd6801e,
+0xd4801e,
+0xd4c01e,
+0x9783d3,
+0xd5c01e,
+0xca0800,
+0x80001a,
+0xca0c00,
+0xe4011e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xe4013e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca1800,
+0xd4401e,
+0xd5801e,
+0x800053,
+0xd40075,
+0xd4401e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd48019,
+0xd4c018,
+0xd50017,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xe2001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0xd48060,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xd48061,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xca0c00,
+0xd4401e,
+0xd48016,
+0xd4c016,
+0xd4801e,
+0x8001b8,
+0xd4c01e,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x948004,
+0xca1400,
+0xe420f3,
+0xd42013,
+0xd56065,
+0xd4e01c,
+0xd5201c,
+0xd5601c,
+0x800000,
+0x062001,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9483f7,
+0xca1400,
+0xe420f3,
+0x800079,
+0xd42013,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9883ef,
+0xca1400,
+0xd40064,
+0x80008d,
+0x000000,
+0xc41432,
+0xc61843,
+0xc4082f,
+0x954005,
+0xc40c30,
+0xd4401e,
+0x800000,
+0xee001e,
+0x9583f5,
+0xc41031,
+0xd44033,
+0xd52065,
+0xd4a01c,
+0xd4e01c,
+0xd5201c,
+0xe4015e,
+0xd4001e,
+0x800000,
+0x062001,
+0xca1800,
+0x0a2001,
+0xd60076,
+0xc40836,
+0x988007,
+0xc61045,
+0x950110,
+0xd4001f,
+0xd46062,
+0x800000,
+0xd42062,
+0xcc3835,
+0xcc1433,
+0x8401bb,
+0xd40072,
+0xd5401e,
+0x800000,
+0xee001e,
+0xe2001a,
+0x8401bb,
+0xe2001a,
+0xcc104b,
+0xcc0447,
+0x2c9401,
+0x7d098b,
+0x984005,
+0x7d15cb,
+0xd4001a,
+0x8001b8,
+0xd4006d,
+0x344401,
+0xcc0c48,
+0x98403a,
+0xcc2c4a,
+0x958004,
+0xcc0449,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0x282801,
+0x8400f0,
+0xcc1003,
+0x98801b,
+0x04380c,
+0x8400f0,
+0xcc1003,
+0x988017,
+0x043808,
+0x8400f0,
+0xcc1003,
+0x988013,
+0x043804,
+0x8400f0,
+0xcc1003,
+0x988014,
+0xcc104c,
+0x9a8009,
+0xcc144d,
+0x9840dc,
+0xd4006d,
+0xcc1848,
+0xd5001a,
+0xd5401a,
+0x8000c9,
+0xd5801a,
+0x96c0d5,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0x9ac003,
+0xd4006d,
+0xd4006e,
+0x800000,
+0xec007f,
+0x9ac0cc,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0x7d9103,
+0x7dd583,
+0x7d190c,
+0x35cc1f,
+0x35701f,
+0x7cf0cb,
+0x7cd08b,
+0x880000,
+0x7e8e8b,
+0x95c004,
+0xd4006e,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0xcc0803,
+0xcc0c03,
+0xcc1003,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0xcc2403,
+0xcc2803,
+0x35c41f,
+0x36b01f,
+0x7c704b,
+0x34f01f,
+0x7c704b,
+0x35701f,
+0x7c704b,
+0x7d8881,
+0x7dccc1,
+0x7e5101,
+0x7e9541,
+0x7c9082,
+0x7cd4c2,
+0x7c848b,
+0x9ac003,
+0x7c8c8b,
+0x2c8801,
+0x98809e,
+0xd4006d,
+0x98409c,
+0xd4006e,
+0xcc084c,
+0xcc0c4d,
+0xcc1048,
+0xd4801a,
+0xd4c01a,
+0x800101,
+0xd5001a,
+0xcc0832,
+0xd40032,
+0x9482d9,
+0xca0c00,
+0xd4401e,
+0x800000,
+0xd4001e,
+0xe4011e,
+0xd4001e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd4401e,
+0xca1400,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xd5401e,
+0xd54034,
+0x800000,
+0xee001e,
+0x280404,
+0xe2001a,
+0xe2001a,
+0xd4401a,
+0xca3800,
+0xcc0803,
+0xcc0c03,
+0xcc0c03,
+0xcc0c03,
+0x9882bd,
+0x000000,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0400,
+0xc2ff00,
+0xcc0834,
+0xc13fff,
+0x7c74cb,
+0x7cc90b,
+0x7d010f,
+0x9902b0,
+0x7c738b,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0800,
+0x281900,
+0x7d898b,
+0x958014,
+0x281404,
+0xca0c00,
+0xca1000,
+0xca1c00,
+0xca2400,
+0xe2001f,
+0xd4c01a,
+0xd5001a,
+0xd5401a,
+0xcc1803,
+0xcc2c03,
+0xcc2c03,
+0xcc2c03,
+0x7da58b,
+0x7d9c47,
+0x984297,
+0x000000,
+0x800161,
+0xd4c01a,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0x248c06,
+0x0ccc06,
+0x98c006,
+0xcc104e,
+0x990004,
+0xd40073,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xca0800,
+0xca0c00,
+0x34d018,
+0x251001,
+0x950021,
+0xc17fff,
+0xca1000,
+0xca1400,
+0xca1800,
+0xd4801d,
+0xd4c01d,
+0x7db18b,
+0xc14202,
+0xc2c001,
+0xd5801d,
+0x34dc0e,
+0x7d5d4c,
+0x7f734c,
+0xd7401e,
+0xd5001e,
+0xd5401e,
+0xc14200,
+0xc2c000,
+0x099c01,
+0x31dc10,
+0x7f5f4c,
+0x7f734c,
+0x042802,
+0x7d8380,
+0xd5a86f,
+0xd58066,
+0xd7401e,
+0xec005e,
+0xc82402,
+0xc82402,
+0x8001b8,
+0xd60076,
+0xd4401e,
+0xd4801e,
+0xd4c01e,
+0x800000,
+0xee001e,
+0x800000,
+0xee001f,
+0xd4001f,
+0x800000,
+0xd4001f,
+0xd4001f,
+0x880000,
+0xd4001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x010171,
+0x020178,
+0x03008f,
+0x04007f,
+0x050003,
+0x06003f,
+0x070032,
+0x08012c,
+0x090046,
+0x0a0036,
+0x1001b6,
+0x1700a2,
+0x22013a,
+0x230149,
+0x2000b4,
+0x240125,
+0x27004d,
+0x28006a,
+0x2a0060,
+0x2b0052,
+0x2f0065,
+0x320087,
+0x34017f,
+0x3c0156,
+0x3f0072,
+0x41018c,
+0x44012e,
+0x550173,
+0x56017a,
+0x60000b,
+0x610034,
+0x620038,
+0x630038,
+0x640038,
+0x650038,
+0x660038,
+0x670038,
+0x68003a,
+0x690041,
+0x6a0048,
+0x6b0048,
+0x6c0048,
+0x6d0048,
+0x6e0048,
+0x6f0048,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+};
+
+static const u32 RV670_cp_microcode[][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00000000, 0x00e00000, 0x000 },
+    { 0x00010000, 0xc0294620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x67c },
+    { 0x00000000, 0x00600000, 0x624 },
+    { 0x00000000, 0x00600000, 0x638 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000f00, 0x00281622, 0x000 },
+    { 0x00000008, 0x00211625, 0x000 },
+    { 0x00000018, 0x00203625, 0x000 },
+    { 0x8d000000, 0x00204411, 0x000 },
+    { 0x00000004, 0x002f0225, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x018 },
+    { 0x00412000, 0x00404811, 0x019 },
+    { 0x00422000, 0x00204811, 0x000 },
+    { 0x8e000000, 0x00204411, 0x000 },
+    { 0x00000028, 0x00204a2d, 0x000 },
+    { 0x90000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x0000000c, 0x00211622, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000019, 0x00211a22, 0x000 },
+    { 0x00000004, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002914c5, 0x000 },
+    { 0x00000019, 0x00203625, 0x000 },
+    { 0x00000000, 0x003a1402, 0x000 },
+    { 0x00000016, 0x00211625, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0xfffffffc, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002914a3, 0x000 },
+    { 0x00000017, 0x00203625, 0x000 },
+    { 0x00008000, 0x00280e22, 0x000 },
+    { 0x00000007, 0x00220e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x20000000, 0x00280e22, 0x000 },
+    { 0x00000006, 0x00210e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00220222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x038 },
+    { 0x00000000, 0x2ee00000, 0x035 },
+    { 0x00000000, 0x2ce00000, 0x037 },
+    { 0x00000000, 0x00400e2d, 0x039 },
+    { 0x00000008, 0x00200e2d, 0x000 },
+    { 0x00000009, 0x0040122d, 0x046 },
+    { 0x00000001, 0x00400e2d, 0x039 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x03e },
+    { 0x00000008, 0x00401c11, 0x041 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x0000000f, 0x00281e27, 0x000 },
+    { 0x00000003, 0x00221e27, 0x000 },
+    { 0x7fc00000, 0x00281a23, 0x000 },
+    { 0x00000014, 0x00211a26, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000008, 0x00221a26, 0x000 },
+    { 0x00000000, 0x00290cc7, 0x000 },
+    { 0x00000027, 0x00203624, 0x000 },
+    { 0x00007f00, 0x00281221, 0x000 },
+    { 0x00001400, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04b },
+    { 0x00000001, 0x00290e23, 0x000 },
+    { 0x0000000e, 0x00203623, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfff80000, 0x00294a23, 0x000 },
+    { 0x00000000, 0x003a2c02, 0x000 },
+    { 0x00000002, 0x00220e2b, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x0000000f, 0x00203623, 0x000 },
+    { 0x00001fff, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00204a2d, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000029, 0x00200e2d, 0x000 },
+    { 0x060a0200, 0x00294a23, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x061 },
+    { 0x00000000, 0x2ee00000, 0x05f },
+    { 0x00000000, 0x2ce00000, 0x05e },
+    { 0x00000000, 0x00400e2d, 0x062 },
+    { 0x00000001, 0x00400e2d, 0x062 },
+    { 0x0000000a, 0x00200e2d, 0x000 },
+    { 0x0000000b, 0x0040122d, 0x06a },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x7fc00000, 0x00281623, 0x000 },
+    { 0x00000014, 0x00211625, 0x000 },
+    { 0x00000001, 0x00331625, 0x000 },
+    { 0x80000000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00290ca3, 0x000 },
+    { 0x3ffffc00, 0x00290e23, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x06d },
+    { 0x00000100, 0x00401c11, 0x070 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x000000f0, 0x00281e27, 0x000 },
+    { 0x00000004, 0x00221e27, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0xfffff0ff, 0x00281a30, 0x000 },
+    { 0x0000a028, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e6, 0x000 },
+    { 0x0000a018, 0x00204411, 0x000 },
+    { 0x3fffffff, 0x00284a23, 0x000 },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000030, 0x0020162d, 0x000 },
+    { 0x00000002, 0x00291625, 0x000 },
+    { 0x00000030, 0x00203625, 0x000 },
+    { 0x00000025, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a3, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x083 },
+    { 0x00000026, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a4, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x084 },
+    { 0x00000000, 0x00400000, 0x08a },
+    { 0x00000025, 0x00203623, 0x000 },
+    { 0x00000026, 0x00203624, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x08a },
+    { 0x00000000, 0x00600000, 0x659 },
+    { 0x00000000, 0x00600000, 0x64d },
+    { 0x00000002, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x08d },
+    { 0x00000012, 0xc0403620, 0x093 },
+    { 0x00000000, 0x2ee00000, 0x091 },
+    { 0x00000000, 0x2ce00000, 0x090 },
+    { 0x00000002, 0x00400e2d, 0x092 },
+    { 0x00000003, 0x00400e2d, 0x092 },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000012, 0x00203623, 0x000 },
+    { 0x00000003, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x098 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x0a0 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x2ee00000, 0x09e },
+    { 0x00000000, 0x2ce00000, 0x09d },
+    { 0x00000002, 0x00400e2d, 0x09f },
+    { 0x00000003, 0x00400e2d, 0x09f },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x003f0000, 0x00280e23, 0x000 },
+    { 0x00000010, 0x00210e23, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x0000001e, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0a7 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x0000001f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0aa },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000008, 0x00210e2b, 0x000 },
+    { 0x0000007f, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0e1 },
+    { 0x00000000, 0x27000000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b3 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00221e30, 0x000 },
+    { 0x99800000, 0x00204411, 0x000 },
+    { 0x00000004, 0x0020122d, 0x000 },
+    { 0x00000008, 0x00221224, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00291ce4, 0x000 },
+    { 0x00000000, 0x00604807, 0x12f },
+    { 0x9b000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x9c000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x0033146f, 0x000 },
+    { 0x00000001, 0x00333e23, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00203c05, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e007, 0x00204411, 0x000 },
+    { 0x0000000f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0cb },
+    { 0x00f8ff08, 0x00204811, 0x000 },
+    { 0x98000000, 0x00404811, 0x0dc },
+    { 0x000000f0, 0x00280e22, 0x000 },
+    { 0x000000a0, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x0da },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d5 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d4 },
+    { 0x00003f00, 0x00400c11, 0x0d6 },
+    { 0x00001f00, 0x00400c11, 0x0d6 },
+    { 0x00000f00, 0x00200c11, 0x000 },
+    { 0x00380009, 0x00294a23, 0x000 },
+    { 0x3f000000, 0x00280e2b, 0x000 },
+    { 0x00000002, 0x00220e23, 0x000 },
+    { 0x00000007, 0x00494a23, 0x0dc },
+    { 0x00380f09, 0x00204811, 0x000 },
+    { 0x68000007, 0x00204811, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000a202, 0x00204411, 0x000 },
+    { 0x00ff0000, 0x00280e22, 0x000 },
+    { 0x00000080, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00200e2d, 0x000 },
+    { 0x00000026, 0x0020122d, 0x000 },
+    { 0x00000000, 0x002f0083, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0ea },
+    { 0x00000000, 0x00600000, 0x653 },
+    { 0x00000000, 0x00400000, 0x0eb },
+    { 0x00000000, 0x00600000, 0x656 },
+    { 0x00000007, 0x0020222d, 0x000 },
+    { 0x00000005, 0x00220e22, 0x000 },
+    { 0x00100000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x000000ef, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000003, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x0f8 },
+    { 0x0000000b, 0x00210228, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0f8 },
+    { 0x00000400, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000001c, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0fd },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000001e, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x10b },
+    { 0x0000a30f, 0x00204411, 0x000 },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x104 },
+    { 0xffffffff, 0x00404811, 0x10b },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x107 },
+    { 0x0000ffff, 0x00404811, 0x10b },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x10a },
+    { 0x000000ff, 0x00404811, 0x10b },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0002c400, 0x00204411, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x112 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000018, 0x40224a20, 0x000 },
+    { 0x00000010, 0xc0424a20, 0x114 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000000a, 0x00201011, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x11b },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00531224, 0x117 },
+    { 0xffbfffff, 0x00283a2e, 0x000 },
+    { 0x0000001b, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x12e },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0x00000018, 0x00220e30, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e00e, 0x00204411, 0x000 },
+    { 0x07f8ff08, 0x00204811, 0x000 },
+    { 0x00000000, 0x00294a23, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x00800000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x67c },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x67b },
+    { 0x00000004, 0x00404c11, 0x135 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x0000001c, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x67c },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x13c },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40280620, 0x000 },
+    { 0x00000010, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x00341461, 0x000 },
+    { 0x00000000, 0x00741882, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x147 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0681a20, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x158 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000001, 0x00300a2f, 0x000 },
+    { 0x00000001, 0x00210a22, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600000, 0x18f },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00202c08, 0x000 },
+    { 0x00000000, 0x00202411, 0x000 },
+    { 0x00000000, 0x00202811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000002, 0x00221e29, 0x000 },
+    { 0x00000000, 0x007048eb, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000001, 0x40330620, 0x000 },
+    { 0x00000000, 0xc0302409, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x181 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x186 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x186 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000001, 0x00530621, 0x182 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0604800, 0x197 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000011, 0x0020062d, 0x000 },
+    { 0x00000000, 0x0078042a, 0x2fb },
+    { 0x00000000, 0x00202809, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x174 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x194 },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x46000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x19b },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00804811, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40281620, 0x000 },
+    { 0x00000010, 0xc0811a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000008, 0x00221e30, 0x000 },
+    { 0x00000029, 0x00201a2d, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfffbff09, 0x00204811, 0x000 },
+    { 0x0000000f, 0x0020222d, 0x000 },
+    { 0x00001fff, 0x00294a28, 0x000 },
+    { 0x00000006, 0x0020222d, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000100, 0x00201811, 0x000 },
+    { 0x00000008, 0x00621e28, 0x12f },
+    { 0x00000008, 0x00822228, 0x000 },
+    { 0x0002c000, 0x00204411, 0x000 },
+    { 0x00000015, 0x00600e2d, 0x1bd },
+    { 0x00000016, 0x00600e2d, 0x1bd },
+    { 0x0000c008, 0x00204411, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1b9 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x39000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00804802, 0x000 },
+    { 0x00000018, 0x00202e2d, 0x000 },
+    { 0x00000000, 0x003b0d63, 0x000 },
+    { 0x00000008, 0x00224a23, 0x000 },
+    { 0x00000010, 0x00224a23, 0x000 },
+    { 0x00000018, 0x00224a23, 0x000 },
+    { 0x00000000, 0x00804803, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000007, 0x0021062f, 0x000 },
+    { 0x00000013, 0x00200a2d, 0x000 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000ffff, 0x40282220, 0x000 },
+    { 0x0000000f, 0x00262228, 0x000 },
+    { 0x00000010, 0x40212620, 0x000 },
+    { 0x0000000f, 0x00262629, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1e0 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000081, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000080, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1dc },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1d8 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000001f, 0x00280a22, 0x000 },
+    { 0x0000001f, 0x00282a2a, 0x000 },
+    { 0x00000001, 0x00530621, 0x1d1 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000002, 0x00304a2f, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x00301e2f, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1e5 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x0000000f, 0x00260e23, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000000f, 0x00261224, 0x000 },
+    { 0x00000000, 0x00201411, 0x000 },
+    { 0x00000000, 0x00601811, 0x2bb },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022b, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1f8 },
+    { 0x00000010, 0x00221628, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a29, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000010, 0x00221623, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a24, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x00731503, 0x205 },
+    { 0x00000000, 0x00201805, 0x000 },
+    { 0x00000000, 0x00731524, 0x205 },
+    { 0x00000000, 0x002d14c5, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00000000, 0x00202003, 0x000 },
+    { 0x00000000, 0x00802404, 0x000 },
+    { 0x0000000f, 0x00210225, 0x000 },
+    { 0x00000000, 0x14c00000, 0x67b },
+    { 0x00000000, 0x002b1405, 0x000 },
+    { 0x00000001, 0x00901625, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00294a22, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a21, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000ffff, 0x40281220, 0x000 },
+    { 0x00000010, 0xc0211a20, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211620, 0x000 },
+    { 0x00000000, 0x00741465, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00000001, 0x00330621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x219 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x212 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x638 },
+    { 0x00000000, 0x0040040f, 0x213 },
+    { 0x00000000, 0x00600000, 0x624 },
+    { 0x00000000, 0x00600000, 0x638 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00000000, 0x00600000, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x232 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x236 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x236 },
+    { 0x00000000, 0xc0404800, 0x233 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x00600411, 0x2fb },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x624 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000018, 0x40210a20, 0x000 },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x24c },
+    { 0x00000014, 0x0020222d, 0x000 },
+    { 0x00080101, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x251 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000010, 0x00600411, 0x315 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00000000, 0x00600000, 0x27c },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000001, 0x00211e27, 0x000 },
+    { 0x00000000, 0x14e00000, 0x26a },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x0000ffff, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00341c27, 0x000 },
+    { 0x00000000, 0x12c00000, 0x25f },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e5, 0x000 },
+    { 0x00000000, 0x08c00000, 0x262 },
+    { 0x00000000, 0x00201407, 0x000 },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00211e27, 0x000 },
+    { 0x00000000, 0x00341c47, 0x000 },
+    { 0x00000000, 0x12c00000, 0x267 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x08c00000, 0x26a },
+    { 0x00000000, 0x00201807, 0x000 },
+    { 0x00000000, 0x00600000, 0x2c1 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000000, 0x00342023, 0x000 },
+    { 0x00000000, 0x12c00000, 0x272 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x271 },
+    { 0x00000016, 0x00404811, 0x276 },
+    { 0x00000018, 0x00404811, 0x276 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x275 },
+    { 0x00000017, 0x00404811, 0x276 },
+    { 0x00000019, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00604411, 0x2e9 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x256 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000010, 0x40210620, 0x000 },
+    { 0x0000ffff, 0xc0280a20, 0x000 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0881a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x67c },
+    { 0x00000000, 0x00600000, 0x624 },
+    { 0x00000000, 0xc0600000, 0x2a3 },
+    { 0x00000005, 0x00200a2d, 0x000 },
+    { 0x00000008, 0x00220a22, 0x000 },
+    { 0x0000002b, 0x00201a2d, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00007000, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00311ce6, 0x000 },
+    { 0x0000002a, 0x00201a2d, 0x000 },
+    { 0x0000000c, 0x00221a26, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x06e00000, 0x292 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x0000002b, 0x00203623, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00691ce2, 0x12f },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x29d },
+    { 0x00000001, 0x00333e2f, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000001c, 0x00403627, 0x000 },
+    { 0x0000000c, 0xc0220a20, 0x000 },
+    { 0x00000029, 0x00203622, 0x000 },
+    { 0x00000028, 0xc0403620, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000009, 0x00204811, 0x000 },
+    { 0xa1000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce3, 0x000 },
+    { 0x00000021, 0x00203627, 0x000 },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce4, 0x000 },
+    { 0x00000022, 0x00203627, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120a3, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x00000023, 0x00203627, 0x000 },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x00000024, 0x00803627, 0x000 },
+    { 0x00000021, 0x00203623, 0x000 },
+    { 0x00000022, 0x00203624, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000023, 0x00203627, 0x000 },
+    { 0x00000000, 0x00311cc4, 0x000 },
+    { 0x00000024, 0x00803627, 0x000 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14c00000, 0x2dc },
+    { 0x00000000, 0x00400000, 0x2d9 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2d9 },
+    { 0x00000003, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2dc },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e1, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120a1, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e2, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000000, 0x00600000, 0x659 },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00600000, 0x650 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2a7 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x0000001a, 0x00201e2d, 0x000 },
+    { 0x0000001b, 0x0080222d, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca1, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x003808c5, 0x000 },
+    { 0x00000000, 0x00300841, 0x000 },
+    { 0x00000001, 0x00220a22, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000017, 0x0020222d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x318 },
+    { 0xffffffef, 0x00280621, 0x000 },
+    { 0x00000014, 0x0020222d, 0x000 },
+    { 0x0000f8e0, 0x00204411, 0x000 },
+    { 0x00000000, 0x00294901, 0x000 },
+    { 0x00000000, 0x00894901, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x97000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00002257, 0x00204411, 0x000 },
+    { 0x00000003, 0xc0484a20, 0x000 },
+    { 0x0000225d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x638 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x00000001, 0x40304a20, 0x000 },
+    { 0x00000002, 0xc0304a20, 0x000 },
+    { 0x00000001, 0x00530a22, 0x34b },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x67c },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x354 },
+    { 0x00000014, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x362 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00604802, 0x36a },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x366 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35d },
+    { 0x00000028, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5b3 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x35d },
+    { 0x0000002c, 0x00203626, 0x000 },
+    { 0x00000049, 0x00201811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x36c },
+    { 0x0000002c, 0x00801a2d, 0x000 },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x00000015, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x382 },
+    { 0x00000006, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3ad },
+    { 0x00000016, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3af },
+    { 0x00000020, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x398 },
+    { 0x0000000f, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a4 },
+    { 0x00000010, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x3a4 },
+    { 0x0000001e, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x38c },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x08000000, 0x00290a22, 0x000 },
+    { 0x00000003, 0x40210e20, 0x000 },
+    { 0x0000000c, 0xc0211220, 0x000 },
+    { 0x00080000, 0x00281224, 0x000 },
+    { 0x00000014, 0xc0221620, 0x000 },
+    { 0x00000000, 0x002914a4, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948a2, 0x000 },
+    { 0x0000a1fe, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x67c },
+    { 0x00000015, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x38e },
+    { 0x0000210e, 0x00204411, 0x000 },
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+    { 0x00000017, 0x00204811, 0x000 },
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+    { 0x00000001, 0x00204811, 0x000 },
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+    { 0x00000001, 0x00210222, 0x000 },
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+    { 0x00040000, 0x18e00c11, 0x4e2 },
+    { 0x00000001, 0x00333e2f, 0x000 },
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+    { 0x87000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000030, 0x00203623, 0x000 },
+    { 0x9d000000, 0x00204411, 0x000 },
+    { 0x0000001f, 0x40214a20, 0x000 },
+    { 0x96000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x0000001f, 0x00211624, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x0000001d, 0x00203623, 0x000 },
+    { 0x00000003, 0x00281e23, 0x000 },
+    { 0x00000008, 0x00222223, 0x000 },
+    { 0xfffff000, 0x00282228, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x0000001f, 0x00203628, 0x000 },
+    { 0x00000018, 0x00211e23, 0x000 },
+    { 0x00000020, 0x00203627, 0x000 },
+    { 0x00000002, 0x00221624, 0x000 },
+    { 0x00000000, 0x003014a8, 0x000 },
+    { 0x0000001e, 0x00203625, 0x000 },
+    { 0x00000003, 0x00211a24, 0x000 },
+    { 0x10000000, 0x00281a26, 0x000 },
+    { 0xefffffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x004938ce, 0x66a },
+    { 0x00000001, 0x40280a20, 0x000 },
+    { 0x00000006, 0x40280e20, 0x000 },
+    { 0x00000300, 0xc0281220, 0x000 },
+    { 0x00000008, 0x00211224, 0x000 },
+    { 0x00000000, 0xc0201620, 0x000 },
+    { 0x00000000, 0xc0201a20, 0x000 },
+    { 0x00000000, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x559 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00002258, 0x00300a24, 0x000 },
+    { 0x00040000, 0x00694622, 0x67c },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00020000, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x561 },
+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x56f },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x561 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00002258, 0x00300a24, 0x000 },
+    { 0x00040000, 0x00694622, 0x67c },
+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x56f },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x565 },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0xc0400000, 0x56f },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x56d },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000216d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0604800, 0x681 },
+    { 0x00000000, 0x00401c10, 0x56f },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x571 },
+    { 0x00000000, 0x00600000, 0x5bc },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x582 },
+    { 0x0000a2b7, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x67c },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x67c },
+    { 0x0000a2c4, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x580 },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x593 },
+    { 0x0000a2bb, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x67c },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x67c },
+    { 0x0000a2c5, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x591 },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5a4 },
+    { 0x0000a2bf, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x67c },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x67c },
+    { 0x0000a2c6, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5a2 },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x0000a2c3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x67c },
+    { 0x0000001a, 0x00212230, 0x000 },
+    { 0x00000006, 0x00222630, 0x000 },
+    { 0x00042004, 0x00604411, 0x67c },
+    { 0x0000a2c7, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5b1 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x85000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x0000304a, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x5b7 },
+    { 0xa4000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0xc0600000, 0x5bc },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000002c, 0x00203621, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5c3 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000030, 0x00403621, 0x5d6 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x5d6 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004a092, 0x00604411, 0x67c },
+    { 0x00000031, 0x00203630, 0x000 },
+    { 0x0004a093, 0x00604411, 0x67c },
+    { 0x00000032, 0x00203630, 0x000 },
+    { 0x0004a2b6, 0x00604411, 0x67c },
+    { 0x00000033, 0x00203630, 0x000 },
+    { 0x0004a2ba, 0x00604411, 0x67c },
+    { 0x00000034, 0x00203630, 0x000 },
+    { 0x0004a2be, 0x00604411, 0x67c },
+    { 0x00000035, 0x00203630, 0x000 },
+    { 0x0004a2c2, 0x00604411, 0x67c },
+    { 0x00000036, 0x00203630, 0x000 },
+    { 0x00042004, 0x00604411, 0x67c },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x88000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000001, 0x002f0230, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x61f },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x61f },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00007e00, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x5f8 },
+    { 0x0000a092, 0x00204411, 0x000 },
+    { 0x00000031, 0x00204a2d, 0x000 },
+    { 0x0000a093, 0x00204411, 0x000 },
+    { 0x00000032, 0x00204a2d, 0x000 },
+    { 0x0000a2b6, 0x00204411, 0x000 },
+    { 0x00000033, 0x00204a2d, 0x000 },
+    { 0x0000a2ba, 0x00204411, 0x000 },
+    { 0x00000034, 0x00204a2d, 0x000 },
+    { 0x0000a2be, 0x00204411, 0x000 },
+    { 0x00000035, 0x00204a2d, 0x000 },
+    { 0x0000a2c2, 0x00204411, 0x000 },
+    { 0x00000036, 0x00204a2d, 0x000 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x000001ff, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x61e },
+    { 0x00000000, 0x00210221, 0x000 },
+    { 0x00000000, 0x14c00000, 0x601 },
+    { 0x0004a003, 0x00604411, 0x67c },
+    { 0x0000a003, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x14c00000, 0x606 },
+    { 0x0004a010, 0x00604411, 0x67c },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00000001, 0x00210621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x61e },
+    { 0x0004a011, 0x00604411, 0x67c },
+    { 0x0000a011, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a012, 0x00604411, 0x67c },
+    { 0x0000a012, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a013, 0x00604411, 0x67c },
+    { 0x0000a013, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a014, 0x00604411, 0x67c },
+    { 0x0000a014, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a015, 0x00604411, 0x67c },
+    { 0x0000a015, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a016, 0x00604411, 0x67c },
+    { 0x0000a016, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x0004a017, 0x00604411, 0x67c },
+    { 0x0000a017, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x00042004, 0x00604411, 0x67c },
+    { 0x0000002c, 0x0080062d, 0x000 },
+    { 0xff000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000002, 0x00804811, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x630 },
+    { 0x00000030, 0x0020062d, 0x000 },
+    { 0x00000002, 0x00280621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x62e },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x67c },
+    { 0x00001000, 0x00200811, 0x000 },
+    { 0x0000002b, 0x00203622, 0x000 },
+    { 0x00000000, 0x00600000, 0x634 },
+    { 0x00000000, 0x00600000, 0x5bc },
+    { 0x98000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0600000, 0x634 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000022, 0x00204811, 0x000 },
+    { 0x89000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00404811, 0x620 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x620 },
+    { 0x00000000, 0x00600000, 0x64d },
+    { 0x0001a2a4, 0xc0204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36a },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x09800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x67c },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x00000004, 0x00404c11, 0x647 },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000004, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffffb, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffff7, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x36a },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x01800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004217f, 0x00604411, 0x67c },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x67b },
+    { 0x00000010, 0x00404c11, 0x661 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x38c00000, 0x000 },
+    { 0x0000001d, 0x00200a2d, 0x000 },
+    { 0x0000001e, 0x00200e2d, 0x000 },
+    { 0x0000001f, 0x0020122d, 0x000 },
+    { 0x00000020, 0x0020162d, 0x000 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x002f0064, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x67a },
+    { 0x00000003, 0x00281a22, 0x000 },
+    { 0x00000008, 0x00221222, 0x000 },
+    { 0xfffff000, 0x00281224, 0x000 },
+    { 0x00000000, 0x002910c4, 0x000 },
+    { 0x0000001f, 0x00403624, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x67c },
+    { 0x9f000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x67f },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x681 },
+    { 0x9e000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x684 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0xc0204411, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000024, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000022, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x014204f5, 0x05b30250, 0x000 },
+    { 0x01c30168, 0x043505b3, 0x000 },
+    { 0x02250209, 0x02500151, 0x000 },
+    { 0x02230245, 0x02a00241, 0x000 },
+    { 0x03cd05b3, 0x05b305b3, 0x000 },
+    { 0x063c063d, 0x031f05b3, 0x000 },
+    { 0x05b305b8, 0x03200340, 0x000 },
+    { 0x032a0282, 0x03420334, 0x000 },
+    { 0x05b305b3, 0x05b305b3, 0x000 },
+    { 0x05b30544, 0x05b305b3, 0x000 },
+    { 0x03b205b3, 0x04ae0344, 0x000 },
+    { 0x048d0443, 0x043305b3, 0x000 },
+    { 0x04c305b3, 0x043704d0, 0x000 },
+    { 0x044304fa, 0x03510371, 0x000 },
+    { 0x05b305b3, 0x05b305b3, 0x000 },
+    { 0x05b305b3, 0x05b305b3, 0x000 },
+    { 0x05b305b3, 0x063205ba, 0x000 },
+    { 0x05b305b3, 0x000705b3, 0x000 },
+    { 0x05b305b3, 0x05b305b3, 0x000 },
+    { 0x05b305b3, 0x05b305b3, 0x000 },
+    { 0x03ee03e3, 0x03fe03fc, 0x000 },
+    { 0x04040400, 0x04020406, 0x000 },
+    { 0x0412040e, 0x041a0416, 0x000 },
+    { 0x0422041e, 0x042a0426, 0x000 },
+    { 0x05b305b3, 0x042e05b3, 0x000 },
+    { 0x05b305b3, 0x05b305b3, 0x000 },
+    { 0x05b305b3, 0x05b305b3, 0x000 },
+    { 0x00020668, 0x06860006, 0x000 },
+};
+
+static const u32 RV670_pfp_microcode[]={
+0xca0400,
+0xa00000,
+0x7e828b,
+0x7c038b,
+0x8001b8,
+0x7c038b,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xc41838,
+0xca2400,
+0xca2800,
+0x9581a8,
+0xc41c3a,
+0xc3c000,
+0xca0800,
+0xca0c00,
+0x7c744b,
+0xc20005,
+0x99c000,
+0xc41c3a,
+0x7c744c,
+0xc0fff0,
+0x042c04,
+0x309002,
+0x7d2500,
+0x351402,
+0x7d350b,
+0x255403,
+0x7cd580,
+0x259c03,
+0x95c004,
+0xd5001b,
+0x7eddc1,
+0x7d9d80,
+0xd6801b,
+0xd5801b,
+0xd4401e,
+0xd5401e,
+0xd6401e,
+0xd6801e,
+0xd4801e,
+0xd4c01e,
+0x9783d3,
+0xd5c01e,
+0xca0800,
+0x80001a,
+0xca0c00,
+0xe4011e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xe4013e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca1800,
+0xd4401e,
+0xd5801e,
+0x800053,
+0xd40075,
+0xd4401e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd48019,
+0xd4c018,
+0xd50017,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xe2001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0xd48060,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xd48061,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xca0c00,
+0xd4401e,
+0xd48016,
+0xd4c016,
+0xd4801e,
+0x8001b8,
+0xd4c01e,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x948004,
+0xca1400,
+0xe420f3,
+0xd42013,
+0xd56065,
+0xd4e01c,
+0xd5201c,
+0xd5601c,
+0x800000,
+0x062001,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9483f7,
+0xca1400,
+0xe420f3,
+0x800079,
+0xd42013,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9883ef,
+0xca1400,
+0xd40064,
+0x80008d,
+0x000000,
+0xc41432,
+0xc61843,
+0xc4082f,
+0x954005,
+0xc40c30,
+0xd4401e,
+0x800000,
+0xee001e,
+0x9583f5,
+0xc41031,
+0xd44033,
+0xd52065,
+0xd4a01c,
+0xd4e01c,
+0xd5201c,
+0xe4015e,
+0xd4001e,
+0x800000,
+0x062001,
+0xca1800,
+0x0a2001,
+0xd60076,
+0xc40836,
+0x988007,
+0xc61045,
+0x950110,
+0xd4001f,
+0xd46062,
+0x800000,
+0xd42062,
+0xcc3835,
+0xcc1433,
+0x8401bb,
+0xd40072,
+0xd5401e,
+0x800000,
+0xee001e,
+0xe2001a,
+0x8401bb,
+0xe2001a,
+0xcc104b,
+0xcc0447,
+0x2c9401,
+0x7d098b,
+0x984005,
+0x7d15cb,
+0xd4001a,
+0x8001b8,
+0xd4006d,
+0x344401,
+0xcc0c48,
+0x98403a,
+0xcc2c4a,
+0x958004,
+0xcc0449,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0x282801,
+0x8400f0,
+0xcc1003,
+0x98801b,
+0x04380c,
+0x8400f0,
+0xcc1003,
+0x988017,
+0x043808,
+0x8400f0,
+0xcc1003,
+0x988013,
+0x043804,
+0x8400f0,
+0xcc1003,
+0x988014,
+0xcc104c,
+0x9a8009,
+0xcc144d,
+0x9840dc,
+0xd4006d,
+0xcc1848,
+0xd5001a,
+0xd5401a,
+0x8000c9,
+0xd5801a,
+0x96c0d5,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0x9ac003,
+0xd4006d,
+0xd4006e,
+0x800000,
+0xec007f,
+0x9ac0cc,
+0xd4006d,
+0x8001b8,
+0xd4006e,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0x7d9103,
+0x7dd583,
+0x7d190c,
+0x35cc1f,
+0x35701f,
+0x7cf0cb,
+0x7cd08b,
+0x880000,
+0x7e8e8b,
+0x95c004,
+0xd4006e,
+0x8001b8,
+0xd4001a,
+0xd4c01a,
+0xcc0803,
+0xcc0c03,
+0xcc1003,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0xcc2403,
+0xcc2803,
+0x35c41f,
+0x36b01f,
+0x7c704b,
+0x34f01f,
+0x7c704b,
+0x35701f,
+0x7c704b,
+0x7d8881,
+0x7dccc1,
+0x7e5101,
+0x7e9541,
+0x7c9082,
+0x7cd4c2,
+0x7c848b,
+0x9ac003,
+0x7c8c8b,
+0x2c8801,
+0x98809e,
+0xd4006d,
+0x98409c,
+0xd4006e,
+0xcc084c,
+0xcc0c4d,
+0xcc1048,
+0xd4801a,
+0xd4c01a,
+0x800101,
+0xd5001a,
+0xcc0832,
+0xd40032,
+0x9482d9,
+0xca0c00,
+0xd4401e,
+0x800000,
+0xd4001e,
+0xe4011e,
+0xd4001e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd4401e,
+0xca1400,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xd5401e,
+0xd54034,
+0x800000,
+0xee001e,
+0x280404,
+0xe2001a,
+0xe2001a,
+0xd4401a,
+0xca3800,
+0xcc0803,
+0xcc0c03,
+0xcc0c03,
+0xcc0c03,
+0x9882bd,
+0x000000,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0400,
+0xc2ff00,
+0xcc0834,
+0xc13fff,
+0x7c74cb,
+0x7cc90b,
+0x7d010f,
+0x9902b0,
+0x7c738b,
+0x8401bb,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0800,
+0x281900,
+0x7d898b,
+0x958014,
+0x281404,
+0xca0c00,
+0xca1000,
+0xca1c00,
+0xca2400,
+0xe2001f,
+0xd4c01a,
+0xd5001a,
+0xd5401a,
+0xcc1803,
+0xcc2c03,
+0xcc2c03,
+0xcc2c03,
+0x7da58b,
+0x7d9c47,
+0x984297,
+0x000000,
+0x800161,
+0xd4c01a,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0x248c06,
+0x0ccc06,
+0x98c006,
+0xcc104e,
+0x990004,
+0xd40073,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xca0800,
+0xca0c00,
+0x34d018,
+0x251001,
+0x950021,
+0xc17fff,
+0xca1000,
+0xca1400,
+0xca1800,
+0xd4801d,
+0xd4c01d,
+0x7db18b,
+0xc14202,
+0xc2c001,
+0xd5801d,
+0x34dc0e,
+0x7d5d4c,
+0x7f734c,
+0xd7401e,
+0xd5001e,
+0xd5401e,
+0xc14200,
+0xc2c000,
+0x099c01,
+0x31dc10,
+0x7f5f4c,
+0x7f734c,
+0x042802,
+0x7d8380,
+0xd5a86f,
+0xd58066,
+0xd7401e,
+0xec005e,
+0xc82402,
+0xc82402,
+0x8001b8,
+0xd60076,
+0xd4401e,
+0xd4801e,
+0xd4c01e,
+0x800000,
+0xee001e,
+0x800000,
+0xee001f,
+0xd4001f,
+0x800000,
+0xd4001f,
+0xd4001f,
+0x880000,
+0xd4001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x010171,
+0x020178,
+0x03008f,
+0x04007f,
+0x050003,
+0x06003f,
+0x070032,
+0x08012c,
+0x090046,
+0x0a0036,
+0x1001b6,
+0x1700a2,
+0x22013a,
+0x230149,
+0x2000b4,
+0x240125,
+0x27004d,
+0x28006a,
+0x2a0060,
+0x2b0052,
+0x2f0065,
+0x320087,
+0x34017f,
+0x3c0156,
+0x3f0072,
+0x41018c,
+0x44012e,
+0x550173,
+0x56017a,
+0x60000b,
+0x610034,
+0x620038,
+0x630038,
+0x640038,
+0x650038,
+0x660038,
+0x670038,
+0x68003a,
+0x690041,
+0x6a0048,
+0x6b0048,
+0x6c0048,
+0x6d0048,
+0x6e0048,
+0x6f0048,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+};
+
+static const u32 RS780_cp_microcode[][3]={
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x0000ffff, 0x00284621, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00000000, 0x00e00000, 0x000 },
+    { 0x00010000, 0xc0294620, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x622 },
+    { 0x00000000, 0x00600000, 0x5d1 },
+    { 0x00000000, 0x00600000, 0x5de },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000f00, 0x00281622, 0x000 },
+    { 0x00000008, 0x00211625, 0x000 },
+    { 0x00000018, 0x00203625, 0x000 },
+    { 0x8d000000, 0x00204411, 0x000 },
+    { 0x00000004, 0x002f0225, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x018 },
+    { 0x00412000, 0x00404811, 0x019 },
+    { 0x00422000, 0x00204811, 0x000 },
+    { 0x8e000000, 0x00204411, 0x000 },
+    { 0x00000028, 0x00204a2d, 0x000 },
+    { 0x90000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x0000000c, 0x00211622, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000019, 0x00211a22, 0x000 },
+    { 0x00000004, 0x00281a26, 0x000 },
+    { 0x00000000, 0x002914c5, 0x000 },
+    { 0x00000019, 0x00203625, 0x000 },
+    { 0x00000000, 0x003a1402, 0x000 },
+    { 0x00000016, 0x00211625, 0x000 },
+    { 0x00000003, 0x00281625, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0xfffffffc, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002914a3, 0x000 },
+    { 0x00000017, 0x00203625, 0x000 },
+    { 0x00008000, 0x00280e22, 0x000 },
+    { 0x00000007, 0x00220e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x20000000, 0x00280e22, 0x000 },
+    { 0x00000006, 0x00210e23, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x00000000, 0x00220222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x038 },
+    { 0x00000000, 0x2ee00000, 0x035 },
+    { 0x00000000, 0x2ce00000, 0x037 },
+    { 0x00000000, 0x00400e2d, 0x039 },
+    { 0x00000008, 0x00200e2d, 0x000 },
+    { 0x00000009, 0x0040122d, 0x046 },
+    { 0x00000001, 0x00400e2d, 0x039 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x03e },
+    { 0x00000008, 0x00401c11, 0x041 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x0000000f, 0x00281e27, 0x000 },
+    { 0x00000003, 0x00221e27, 0x000 },
+    { 0x7fc00000, 0x00281a23, 0x000 },
+    { 0x00000014, 0x00211a26, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000008, 0x00221a26, 0x000 },
+    { 0x00000000, 0x00290cc7, 0x000 },
+    { 0x00000027, 0x00203624, 0x000 },
+    { 0x00007f00, 0x00281221, 0x000 },
+    { 0x00001400, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x04b },
+    { 0x00000001, 0x00290e23, 0x000 },
+    { 0x0000000e, 0x00203623, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfff80000, 0x00294a23, 0x000 },
+    { 0x00000000, 0x003a2c02, 0x000 },
+    { 0x00000002, 0x00220e2b, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x0000000f, 0x00203623, 0x000 },
+    { 0x00001fff, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00204a2d, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000029, 0x00200e2d, 0x000 },
+    { 0x060a0200, 0x00294a23, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14e00000, 0x061 },
+    { 0x00000000, 0x2ee00000, 0x05f },
+    { 0x00000000, 0x2ce00000, 0x05e },
+    { 0x00000000, 0x00400e2d, 0x062 },
+    { 0x00000001, 0x00400e2d, 0x062 },
+    { 0x0000000a, 0x00200e2d, 0x000 },
+    { 0x0000000b, 0x0040122d, 0x06a },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x003ffffc, 0x00281223, 0x000 },
+    { 0x00000002, 0x00221224, 0x000 },
+    { 0x7fc00000, 0x00281623, 0x000 },
+    { 0x00000014, 0x00211625, 0x000 },
+    { 0x00000001, 0x00331625, 0x000 },
+    { 0x80000000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00290ca3, 0x000 },
+    { 0x3ffffc00, 0x00290e23, 0x000 },
+    { 0x0000001f, 0x00211e23, 0x000 },
+    { 0x00000000, 0x14e00000, 0x06d },
+    { 0x00000100, 0x00401c11, 0x070 },
+    { 0x0000000d, 0x00201e2d, 0x000 },
+    { 0x000000f0, 0x00281e27, 0x000 },
+    { 0x00000004, 0x00221e27, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0xfffff0ff, 0x00281a30, 0x000 },
+    { 0x0000a028, 0x00204411, 0x000 },
+    { 0x00000000, 0x002948e6, 0x000 },
+    { 0x0000a018, 0x00204411, 0x000 },
+    { 0x3fffffff, 0x00284a23, 0x000 },
+    { 0x0000a010, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000030, 0x0020162d, 0x000 },
+    { 0x00000002, 0x00291625, 0x000 },
+    { 0x00000030, 0x00203625, 0x000 },
+    { 0x00000025, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a3, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x083 },
+    { 0x00000026, 0x0020162d, 0x000 },
+    { 0x00000000, 0x002f00a4, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x084 },
+    { 0x00000000, 0x00400000, 0x08a },
+    { 0x00000025, 0x00203623, 0x000 },
+    { 0x00000026, 0x00203624, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x08a },
+    { 0x00000000, 0x00600000, 0x5ff },
+    { 0x00000000, 0x00600000, 0x5f3 },
+    { 0x00000002, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x08d },
+    { 0x00000012, 0xc0403620, 0x093 },
+    { 0x00000000, 0x2ee00000, 0x091 },
+    { 0x00000000, 0x2ce00000, 0x090 },
+    { 0x00000002, 0x00400e2d, 0x092 },
+    { 0x00000003, 0x00400e2d, 0x092 },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000012, 0x00203623, 0x000 },
+    { 0x00000003, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x098 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x0a0 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x2ee00000, 0x09e },
+    { 0x00000000, 0x2ce00000, 0x09d },
+    { 0x00000002, 0x00400e2d, 0x09f },
+    { 0x00000003, 0x00400e2d, 0x09f },
+    { 0x0000000c, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x00204803, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x003f0000, 0x00280e23, 0x000 },
+    { 0x00000010, 0x00210e23, 0x000 },
+    { 0x00000011, 0x00203623, 0x000 },
+    { 0x0000001e, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0a7 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x0000001f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0aa },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000008, 0x00210e2b, 0x000 },
+    { 0x0000007f, 0x00280e23, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0e1 },
+    { 0x00000000, 0x27000000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x0b3 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x0000000c, 0x00221e30, 0x000 },
+    { 0x99800000, 0x00204411, 0x000 },
+    { 0x00000004, 0x0020122d, 0x000 },
+    { 0x00000008, 0x00221224, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00291ce4, 0x000 },
+    { 0x00000000, 0x00604807, 0x12f },
+    { 0x9b000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x9c000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x0033146f, 0x000 },
+    { 0x00000001, 0x00333e23, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0x00203c05, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e007, 0x00204411, 0x000 },
+    { 0x0000000f, 0x0021022b, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0cb },
+    { 0x00f8ff08, 0x00204811, 0x000 },
+    { 0x98000000, 0x00404811, 0x0dc },
+    { 0x000000f0, 0x00280e22, 0x000 },
+    { 0x000000a0, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x0da },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d5 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0d4 },
+    { 0x00003f00, 0x00400c11, 0x0d6 },
+    { 0x00001f00, 0x00400c11, 0x0d6 },
+    { 0x00000f00, 0x00200c11, 0x000 },
+    { 0x00380009, 0x00294a23, 0x000 },
+    { 0x3f000000, 0x00280e2b, 0x000 },
+    { 0x00000002, 0x00220e23, 0x000 },
+    { 0x00000007, 0x00494a23, 0x0dc },
+    { 0x00380f09, 0x00204811, 0x000 },
+    { 0x68000007, 0x00204811, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000a202, 0x00204411, 0x000 },
+    { 0x00ff0000, 0x00280e22, 0x000 },
+    { 0x00000080, 0x00294a23, 0x000 },
+    { 0x00000027, 0x00200e2d, 0x000 },
+    { 0x00000026, 0x0020122d, 0x000 },
+    { 0x00000000, 0x002f0083, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x0ea },
+    { 0x00000000, 0x00600000, 0x5f9 },
+    { 0x00000000, 0x00400000, 0x0eb },
+    { 0x00000000, 0x00600000, 0x5fc },
+    { 0x00000007, 0x0020222d, 0x000 },
+    { 0x00000005, 0x00220e22, 0x000 },
+    { 0x00100000, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000000, 0x003a0c02, 0x000 },
+    { 0x000000ef, 0x00280e23, 0x000 },
+    { 0x00000000, 0x00292068, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000003, 0x00210223, 0x000 },
+    { 0x00000000, 0x14e00000, 0x0f8 },
+    { 0x0000000b, 0x00210228, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0f8 },
+    { 0x00000400, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000001c, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x0fd },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000001e, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x10b },
+    { 0x0000a30f, 0x00204411, 0x000 },
+    { 0x00000011, 0x00200e2d, 0x000 },
+    { 0x00000001, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x104 },
+    { 0xffffffff, 0x00404811, 0x10b },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x107 },
+    { 0x0000ffff, 0x00404811, 0x10b },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x10a },
+    { 0x000000ff, 0x00404811, 0x10b },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0002c400, 0x00204411, 0x000 },
+    { 0x0000001f, 0x00210e22, 0x000 },
+    { 0x00000000, 0x14c00000, 0x112 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000018, 0x40224a20, 0x000 },
+    { 0x00000010, 0xc0424a20, 0x114 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x00000013, 0x00203623, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000000a, 0x00201011, 0x000 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x11b },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00531224, 0x117 },
+    { 0xffbfffff, 0x00283a2e, 0x000 },
+    { 0x0000001b, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x12e },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000d, 0x00204811, 0x000 },
+    { 0x00000018, 0x00220e30, 0x000 },
+    { 0xfc000000, 0x00280e23, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x00000000, 0x00201010, 0x000 },
+    { 0x0000e00e, 0x00204411, 0x000 },
+    { 0x07f8ff08, 0x00204811, 0x000 },
+    { 0x00000000, 0x00294a23, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a24, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x00800000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204806, 0x000 },
+    { 0x00000008, 0x00214a27, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x622 },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x621 },
+    { 0x00000004, 0x00404c11, 0x135 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x0000001c, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x622 },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x13c },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40280620, 0x000 },
+    { 0x00000010, 0xc0210a20, 0x000 },
+    { 0x00000000, 0x00341461, 0x000 },
+    { 0x00000000, 0x00741882, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x147 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x160 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0681a20, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x158 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000001, 0x00300a2f, 0x000 },
+    { 0x00000001, 0x00210a22, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600000, 0x18f },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00202c08, 0x000 },
+    { 0x00000000, 0x00202411, 0x000 },
+    { 0x00000000, 0x00202811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000002, 0x00221e29, 0x000 },
+    { 0x00000000, 0x007048eb, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000001, 0x40330620, 0x000 },
+    { 0x00000000, 0xc0302409, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x181 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x186 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x186 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000001, 0x00530621, 0x182 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0604800, 0x197 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000011, 0x0020062d, 0x000 },
+    { 0x00000000, 0x0078042a, 0x2fb },
+    { 0x00000000, 0x00202809, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x174 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x194 },
+    { 0x00000015, 0xc0203620, 0x000 },
+    { 0x00000016, 0xc0203620, 0x000 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x46000000, 0x00600811, 0x1b2 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x19b },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00804811, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000ffff, 0x40281620, 0x000 },
+    { 0x00000010, 0xc0811a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x00000008, 0x00221e30, 0x000 },
+    { 0x00000029, 0x00201a2d, 0x000 },
+    { 0x0000e000, 0x00204411, 0x000 },
+    { 0xfffbff09, 0x00204811, 0x000 },
+    { 0x0000000f, 0x0020222d, 0x000 },
+    { 0x00001fff, 0x00294a28, 0x000 },
+    { 0x00000006, 0x0020222d, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000100, 0x00201811, 0x000 },
+    { 0x00000008, 0x00621e28, 0x12f },
+    { 0x00000008, 0x00822228, 0x000 },
+    { 0x0002c000, 0x00204411, 0x000 },
+    { 0x00000015, 0x00600e2d, 0x1bd },
+    { 0x00000016, 0x00600e2d, 0x1bd },
+    { 0x0000c008, 0x00204411, 0x000 },
+    { 0x00000017, 0x00200e2d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x1b9 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x39000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00804802, 0x000 },
+    { 0x00000018, 0x00202e2d, 0x000 },
+    { 0x00000000, 0x003b0d63, 0x000 },
+    { 0x00000008, 0x00224a23, 0x000 },
+    { 0x00000010, 0x00224a23, 0x000 },
+    { 0x00000018, 0x00224a23, 0x000 },
+    { 0x00000000, 0x00804803, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00000007, 0x0021062f, 0x000 },
+    { 0x00000013, 0x00200a2d, 0x000 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000ffff, 0x40282220, 0x000 },
+    { 0x0000000f, 0x00262228, 0x000 },
+    { 0x00000010, 0x40212620, 0x000 },
+    { 0x0000000f, 0x00262629, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1e0 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000081, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000080, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1dc },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1d8 },
+    { 0x00000001, 0x00202c11, 0x000 },
+    { 0x0000001f, 0x00280a22, 0x000 },
+    { 0x0000001f, 0x00282a2a, 0x000 },
+    { 0x00000001, 0x00530621, 0x1d1 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000002, 0x00304a2f, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000001, 0x00301e2f, 0x000 },
+    { 0x00000000, 0x002f0227, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x00600000, 0x1e9 },
+    { 0x00000001, 0x00531e27, 0x1e5 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x0000000f, 0x00260e23, 0x000 },
+    { 0x00000010, 0xc0211220, 0x000 },
+    { 0x0000000f, 0x00261224, 0x000 },
+    { 0x00000000, 0x00201411, 0x000 },
+    { 0x00000000, 0x00601811, 0x2bb },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022b, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x1f8 },
+    { 0x00000010, 0x00221628, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a29, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x0020480a, 0x000 },
+    { 0x00000000, 0x00202c11, 0x000 },
+    { 0x00000010, 0x00221623, 0x000 },
+    { 0xffff0000, 0x00281625, 0x000 },
+    { 0x0000ffff, 0x00281a24, 0x000 },
+    { 0x00000000, 0x002948c5, 0x000 },
+    { 0x00000000, 0x00731503, 0x205 },
+    { 0x00000000, 0x00201805, 0x000 },
+    { 0x00000000, 0x00731524, 0x205 },
+    { 0x00000000, 0x002d14c5, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
+    { 0x00000000, 0x00202802, 0x000 },
+    { 0x00000000, 0x00202003, 0x000 },
+    { 0x00000000, 0x00802404, 0x000 },
+    { 0x0000000f, 0x00210225, 0x000 },
+    { 0x00000000, 0x14c00000, 0x621 },
+    { 0x00000000, 0x002b1405, 0x000 },
+    { 0x00000001, 0x00901625, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001a, 0x00294a22, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a21, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000ffff, 0x40281220, 0x000 },
+    { 0x00000010, 0xc0211a20, 0x000 },
+    { 0x0000ffff, 0x40280e20, 0x000 },
+    { 0x00000010, 0xc0211620, 0x000 },
+    { 0x00000000, 0x00741465, 0x2bb },
+    { 0x0001a1fd, 0x00604411, 0x2e0 },
+    { 0x00000001, 0x00330621, 0x000 },
+    { 0x00000000, 0x002f0221, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x219 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x212 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x5de },
+    { 0x00000000, 0x0040040f, 0x213 },
+    { 0x00000000, 0x00600000, 0x5d1 },
+    { 0x00000000, 0x00600000, 0x5de },
+    { 0x00000210, 0x00600411, 0x315 },
+    { 0x00000000, 0x00600000, 0x1a0 },
+    { 0x00000000, 0x00600000, 0x19c },
+    { 0x00000000, 0x00600000, 0x2bb },
+    { 0x00000000, 0x00600000, 0x2a3 },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204808, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x232 },
+    { 0x00000000, 0x00600000, 0x13a },
+    { 0x00000000, 0x00400000, 0x236 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x236 },
+    { 0x00000000, 0xc0404800, 0x233 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x00600411, 0x2fb },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000000, 0x00600000, 0x5d1 },
+    { 0x0000a00c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000018, 0x40210a20, 0x000 },
+    { 0x00000003, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ae00000, 0x24c },
+    { 0x00000014, 0x0020222d, 0x000 },
+    { 0x00080101, 0x00292228, 0x000 },
+    { 0x00000014, 0x00203628, 0x000 },
+    { 0x0000a30c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x251 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000010, 0x00600411, 0x315 },
+    { 0x3f800000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00000000, 0x00600000, 0x27c },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000001, 0x00211e27, 0x000 },
+    { 0x00000000, 0x14e00000, 0x26a },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x0000ffff, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00341c27, 0x000 },
+    { 0x00000000, 0x12c00000, 0x25f },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e5, 0x000 },
+    { 0x00000000, 0x08c00000, 0x262 },
+    { 0x00000000, 0x00201407, 0x000 },
+    { 0x00000012, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00211e27, 0x000 },
+    { 0x00000000, 0x00341c47, 0x000 },
+    { 0x00000000, 0x12c00000, 0x267 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x08c00000, 0x26a },
+    { 0x00000000, 0x00201807, 0x000 },
+    { 0x00000000, 0x00600000, 0x2c1 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x00000000, 0x00342023, 0x000 },
+    { 0x00000000, 0x12c00000, 0x272 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x271 },
+    { 0x00000016, 0x00404811, 0x276 },
+    { 0x00000018, 0x00404811, 0x276 },
+    { 0x00000000, 0x00342044, 0x000 },
+    { 0x00000000, 0x12c00000, 0x275 },
+    { 0x00000017, 0x00404811, 0x276 },
+    { 0x00000019, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0x00604411, 0x2e9 },
+    { 0x00003fff, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x256 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x00000010, 0x40210620, 0x000 },
+    { 0x0000ffff, 0xc0280a20, 0x000 },
+    { 0x00000010, 0x40210e20, 0x000 },
+    { 0x0000ffff, 0xc0281220, 0x000 },
+    { 0x00000010, 0x40211620, 0x000 },
+    { 0x0000ffff, 0xc0881a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00042004, 0x00604411, 0x622 },
+    { 0x00000000, 0x00600000, 0x5d1 },
+    { 0x00000000, 0xc0600000, 0x2a3 },
+    { 0x00000005, 0x00200a2d, 0x000 },
+    { 0x00000008, 0x00220a22, 0x000 },
+    { 0x0000002b, 0x00201a2d, 0x000 },
+    { 0x0000001c, 0x00201e2d, 0x000 },
+    { 0x00007000, 0x00281e27, 0x000 },
+    { 0x00000000, 0x00311ce6, 0x000 },
+    { 0x0000002a, 0x00201a2d, 0x000 },
+    { 0x0000000c, 0x00221a26, 0x000 },
+    { 0x00000000, 0x002f00e6, 0x000 },
+    { 0x00000000, 0x06e00000, 0x292 },
+    { 0x00000000, 0x00201c11, 0x000 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x0000002b, 0x00203623, 0x000 },
+    { 0x00000010, 0x00201811, 0x000 },
+    { 0x00000000, 0x00691ce2, 0x12f },
+    { 0x93800000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x95000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f022f, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x29d },
+    { 0x00000001, 0x00333e2f, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x92000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000001c, 0x00403627, 0x000 },
+    { 0x0000000c, 0xc0220a20, 0x000 },
+    { 0x00000029, 0x00203622, 0x000 },
+    { 0x00000028, 0xc0403620, 0x000 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000009, 0x00204811, 0x000 },
+    { 0xa1000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00804811, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce3, 0x000 },
+    { 0x00000021, 0x00203627, 0x000 },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002c1ce4, 0x000 },
+    { 0x00000022, 0x00203627, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120a3, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x00000023, 0x00203627, 0x000 },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x00000000, 0x002d1d07, 0x000 },
+    { 0x00000024, 0x00803627, 0x000 },
+    { 0x00000021, 0x00203623, 0x000 },
+    { 0x00000022, 0x00203624, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000023, 0x00203627, 0x000 },
+    { 0x00000000, 0x00311cc4, 0x000 },
+    { 0x00000024, 0x00803627, 0x000 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14c00000, 0x2dc },
+    { 0x00000000, 0x00400000, 0x2d9 },
+    { 0x0000001a, 0x00203627, 0x000 },
+    { 0x0000001b, 0x00203628, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000002, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2d9 },
+    { 0x00000003, 0x00210227, 0x000 },
+    { 0x00000000, 0x14e00000, 0x2dc },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e1, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120a1, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000024, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x002e00e2, 0x000 },
+    { 0x00000000, 0x02c00000, 0x2dc },
+    { 0x00000022, 0x00201e2d, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x00000000, 0x002e00e8, 0x000 },
+    { 0x00000000, 0x06c00000, 0x2dc },
+    { 0x00000000, 0x00600000, 0x5ff },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2b5 },
+    { 0x00000000, 0x00600000, 0x5f6 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x00000000, 0x00600000, 0x2a7 },
+    { 0x00000000, 0x00400000, 0x2de },
+    { 0x0000001a, 0x00201e2d, 0x000 },
+    { 0x0000001b, 0x0080222d, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000000, 0x00311ca1, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294847, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e21, 0x000 },
+    { 0x00000000, 0x003120c2, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00311ca3, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294887, 0x000 },
+    { 0x00000001, 0x00220a21, 0x000 },
+    { 0x00000000, 0x003008a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000010, 0x00221e23, 0x000 },
+    { 0x00000000, 0x003120c4, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x003808c5, 0x000 },
+    { 0x00000000, 0x00300841, 0x000 },
+    { 0x00000001, 0x00220a22, 0x000 },
+    { 0x00000000, 0x003308a2, 0x000 },
+    { 0x00000010, 0x00221e22, 0x000 },
+    { 0x00000010, 0x00212222, 0x000 },
+    { 0x00000000, 0x00894907, 0x000 },
+    { 0x00000017, 0x0020222d, 0x000 },
+    { 0x00000000, 0x14c00000, 0x318 },
+    { 0xffffffef, 0x00280621, 0x000 },
+    { 0x00000014, 0x0020222d, 0x000 },
+    { 0x0000f8e0, 0x00204411, 0x000 },
+    { 0x00000000, 0x00294901, 0x000 },
+    { 0x00000000, 0x00894901, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x060a0200, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x97000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0204811, 0x000 },
+    { 0x8a000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0xd9004800, 0x000 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x00a0000a, 0x000 },
+    { 0x00002257, 0x00204411, 0x000 },
+    { 0x00000003, 0xc0484a20, 0x000 },
+    { 0x0000225d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0x00600000, 0x5de },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00384a22, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0001a1fd, 0x00204411, 0x000 },
+    { 0x00000000, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0ce00000, 0x000 },
+    { 0x00000000, 0x40204800, 0x000 },
+    { 0x00000001, 0x40304a20, 0x000 },
+    { 0x00000002, 0xc0304a20, 0x000 },
+    { 0x00000001, 0x00530a22, 0x355 },
+    { 0x0000003f, 0xc0280a20, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x622 },
+    { 0x00000011, 0x00210230, 0x000 },
+    { 0x00000000, 0x14e00000, 0x35e },
+    { 0x00000014, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x36c },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00604802, 0x374 },
+    { 0x00002100, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000004, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x370 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x367 },
+    { 0x00000028, 0x002f0222, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5ba },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404802, 0x367 },
+    { 0x0000002c, 0x00203626, 0x000 },
+    { 0x00000049, 0x00201811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000001, 0x00331a26, 0x000 },
+    { 0x00000000, 0x002f0226, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x376 },
+    { 0x0000002c, 0x00801a2d, 0x000 },
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+    { 0x00000000, 0x002948a2, 0x000 },
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+    { 0x00000000, 0x00404803, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x00000016, 0x00204811, 0x000 },
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+    { 0x00000000, 0x00404802, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
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+    { 0x00000017, 0x00204811, 0x000 },
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+    { 0x00000000, 0x14e00000, 0x3ce },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
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+    { 0x00000018, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x622 },
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+    { 0xcafebabe, 0x00404811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00003fff, 0x40280a20, 0x000 },
+    { 0x80000000, 0x40280e20, 0x000 },
+    { 0x40000000, 0xc0281220, 0x000 },
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+    { 0x00000007, 0x00280a23, 0x000 },
+    { 0x00000001, 0x002f0222, 0x000 },
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+    { 0x00000000, 0x04e00000, 0x48e },
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+    { 0x00000000, 0xc0604800, 0x627 },
+    { 0x00000000, 0x00400000, 0x4cf },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00040000, 0xc0294620, 0x000 },
+    { 0x00000000, 0xc0600000, 0x622 },
+    { 0x00000001, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x4d6 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
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+    { 0x00000000, 0xc0204400, 0x000 },
+    { 0x00000000, 0xc0404810, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x000021f8, 0x00204411, 0x000 },
+    { 0x0000000e, 0x00204811, 0x000 },
+    { 0x000421f9, 0x00604411, 0x622 },
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+    { 0x00000000, 0x14c00000, 0x4d8 },
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+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000003, 0x00333e2f, 0x000 },
+    { 0x00000001, 0x00210221, 0x000 },
+    { 0x00000000, 0x14e00000, 0x508 },
+    { 0x0000002c, 0x00200a2d, 0x000 },
+    { 0x00040000, 0x18e00c11, 0x4f7 },
+    { 0x00000001, 0x00333e2f, 0x000 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204802, 0x000 },
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+    { 0x00000000, 0xd8c04800, 0x4eb },
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+    { 0x0000002d, 0x0020122d, 0x000 },
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+    { 0x00000000, 0x00400000, 0x4b2 },
+    { 0x0000002c, 0xc0203620, 0x000 },
+    { 0x0000002d, 0xc0403620, 0x000 },
+    { 0x0000000f, 0x00210221, 0x000 },
+    { 0x00000000, 0x14c00000, 0x50d },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00000000, 0xd9000000, 0x000 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0xb5000000, 0x00204411, 0x000 },
+    { 0x00002000, 0x00204811, 0x000 },
+    { 0xb6000000, 0x00204411, 0x000 },
+    { 0x0000a000, 0x00204811, 0x000 },
+    { 0xb7000000, 0x00204411, 0x000 },
+    { 0x0000c000, 0x00204811, 0x000 },
+    { 0xb8000000, 0x00204411, 0x000 },
+    { 0x0000f8e0, 0x00204811, 0x000 },
+    { 0xb9000000, 0x00204411, 0x000 },
+    { 0x0000f880, 0x00204811, 0x000 },
+    { 0xba000000, 0x00204411, 0x000 },
+    { 0x0000e000, 0x00204811, 0x000 },
+    { 0xbb000000, 0x00204411, 0x000 },
+    { 0x0000f000, 0x00204811, 0x000 },
+    { 0xbc000000, 0x00204411, 0x000 },
+    { 0x0000f3fc, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000002, 0x00204811, 0x000 },
+    { 0x000000ff, 0x00280e30, 0x000 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x521 },
+    { 0x00000000, 0xc0200800, 0x000 },
+    { 0x00000000, 0x14c00000, 0x536 },
+    { 0x00000000, 0x00200c11, 0x000 },
+    { 0x0000001c, 0x00203623, 0x000 },
+    { 0x0000002b, 0x00203623, 0x000 },
+    { 0x00000029, 0x00203623, 0x000 },
+    { 0x00000028, 0x00203623, 0x000 },
+    { 0x00000017, 0x00203623, 0x000 },
+    { 0x00000025, 0x00203623, 0x000 },
+    { 0x00000026, 0x00203623, 0x000 },
+    { 0x00000015, 0x00203623, 0x000 },
+    { 0x00000016, 0x00203623, 0x000 },
+    { 0xffffe000, 0x00200c11, 0x000 },
+    { 0x00000021, 0x00203623, 0x000 },
+    { 0x00000022, 0x00203623, 0x000 },
+    { 0x00001fff, 0x00200c11, 0x000 },
+    { 0x00000023, 0x00203623, 0x000 },
+    { 0x00000024, 0x00203623, 0x000 },
+    { 0xf1ffffff, 0x00283a2e, 0x000 },
+    { 0x0000001a, 0xc0220e20, 0x000 },
+    { 0x00000000, 0x0029386e, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000006, 0x00204811, 0x000 },
+    { 0x0000002a, 0x40203620, 0x000 },
+    { 0x87000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0x9d000000, 0x00204411, 0x000 },
+    { 0x0000001f, 0x40214a20, 0x000 },
+    { 0x96000000, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0200c00, 0x000 },
+    { 0x00000000, 0xc0201000, 0x000 },
+    { 0x0000001f, 0x00211624, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x0000001d, 0x00203623, 0x000 },
+    { 0x00000003, 0x00281e23, 0x000 },
+    { 0x00000008, 0x00222223, 0x000 },
+    { 0xfffff000, 0x00282228, 0x000 },
+    { 0x00000000, 0x002920e8, 0x000 },
+    { 0x0000001f, 0x00203628, 0x000 },
+    { 0x00000018, 0x00211e23, 0x000 },
+    { 0x00000020, 0x00203627, 0x000 },
+    { 0x00000002, 0x00221624, 0x000 },
+    { 0x00000000, 0x003014a8, 0x000 },
+    { 0x0000001e, 0x00203625, 0x000 },
+    { 0x00000003, 0x00211a24, 0x000 },
+    { 0x10000000, 0x00281a26, 0x000 },
+    { 0xefffffff, 0x00283a2e, 0x000 },
+    { 0x00000000, 0x004938ce, 0x610 },
+    { 0x00000001, 0x40280a20, 0x000 },
+    { 0x00000006, 0x40280e20, 0x000 },
+    { 0x00000300, 0xc0281220, 0x000 },
+    { 0x00000008, 0x00211224, 0x000 },
+    { 0x00000000, 0xc0201620, 0x000 },
+    { 0x00000000, 0xc0201a20, 0x000 },
+    { 0x00000000, 0x00210222, 0x000 },
+    { 0x00000000, 0x14c00000, 0x56c },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00002258, 0x00300a24, 0x000 },
+    { 0x00040000, 0x00694622, 0x622 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00020000, 0x00294a26, 0x000 },
+    { 0x00000000, 0x00204810, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x574 },
+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x582 },
+    { 0x00000002, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x574 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00002258, 0x00300a24, 0x000 },
+    { 0x00040000, 0x00694622, 0x622 },
+    { 0x00000000, 0xc0201c10, 0x000 },
+    { 0x00000000, 0xc0400000, 0x582 },
+    { 0x00000000, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x578 },
+    { 0x00000000, 0xc0201c00, 0x000 },
+    { 0x00000000, 0xc0400000, 0x582 },
+    { 0x00000004, 0x002f0223, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x580 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x0000216d, 0x00204411, 0x000 },
+    { 0x00000000, 0xc0204800, 0x000 },
+    { 0x00000000, 0xc0604800, 0x627 },
+    { 0x00000000, 0x00401c10, 0x582 },
+    { 0x00000000, 0xc0200000, 0x000 },
+    { 0x00000000, 0xc0400000, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x584 },
+    { 0x00000000, 0x00600000, 0x5c3 },
+    { 0x00000000, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x592 },
+    { 0x0000a2b7, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x00000033, 0x0020262d, 0x000 },
+    { 0x0000001a, 0x00212229, 0x000 },
+    { 0x00000006, 0x00222629, 0x000 },
+    { 0x0000a2c4, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x590 },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d1, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000001, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5a0 },
+    { 0x0000a2bb, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x00000034, 0x0020262d, 0x000 },
+    { 0x0000001a, 0x00212229, 0x000 },
+    { 0x00000006, 0x00222629, 0x000 },
+    { 0x0000a2c5, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x59e },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d2, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x00000002, 0x002f0224, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x5ae },
+    { 0x0000a2bf, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x00000035, 0x0020262d, 0x000 },
+    { 0x0000001a, 0x00212229, 0x000 },
+    { 0x00000006, 0x00222629, 0x000 },
+    { 0x0000a2c6, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5ac },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d3, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x0000a2c3, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204807, 0x000 },
+    { 0x00000036, 0x0020262d, 0x000 },
+    { 0x0000001a, 0x00212229, 0x000 },
+    { 0x00000006, 0x00222629, 0x000 },
+    { 0x0000a2c7, 0x00204411, 0x000 },
+    { 0x00000000, 0x003048e9, 0x000 },
+    { 0x00000000, 0x00e00000, 0x5b8 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404808, 0x000 },
+    { 0x0000a2d4, 0x00204411, 0x000 },
+    { 0x00000001, 0x00504a28, 0x000 },
+    { 0x85000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0x0000304a, 0x00204411, 0x000 },
+    { 0x01000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x00400000, 0x5be },
+    { 0xa4000000, 0xc0204411, 0x000 },
+    { 0x00000000, 0xc0404800, 0x000 },
+    { 0x00000000, 0xc0600000, 0x5c3 },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x0000003f, 0x00204811, 0x000 },
+    { 0x00000005, 0x00204811, 0x000 },
+    { 0x0000a1f4, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x88000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0xff000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x00000002, 0x00804811, 0x000 },
+    { 0x00000000, 0x0ee00000, 0x5d6 },
+    { 0x00001000, 0x00200811, 0x000 },
+    { 0x0000002b, 0x00203622, 0x000 },
+    { 0x00000000, 0x00600000, 0x5da },
+    { 0x00000000, 0x00600000, 0x5c3 },
+    { 0x98000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00804811, 0x000 },
+    { 0x00000000, 0xc0600000, 0x5da },
+    { 0x00000000, 0xc0400400, 0x001 },
+    { 0x0000a2a4, 0x00204411, 0x000 },
+    { 0x00000022, 0x00204811, 0x000 },
+    { 0x89000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00404811, 0x5cd },
+    { 0x97000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x8a000000, 0x00204411, 0x000 },
+    { 0x00000000, 0x00404811, 0x5cd },
+    { 0x00000000, 0x00600000, 0x5f3 },
+    { 0x0001a2a4, 0xc0204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x374 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x09800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x0004217f, 0x00604411, 0x622 },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x000 },
+    { 0x00000004, 0x00404c11, 0x5ed },
+    { 0x00000000, 0x00400000, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000004, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffffb, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0x00000008, 0x00291e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x00000017, 0x00201e2d, 0x000 },
+    { 0xfffffff7, 0x00281e27, 0x000 },
+    { 0x00000017, 0x00803627, 0x000 },
+    { 0x0001a2a4, 0x00204411, 0x000 },
+    { 0x00000016, 0x00604811, 0x374 },
+    { 0x00002010, 0x00204411, 0x000 },
+    { 0x00010000, 0x00204811, 0x000 },
+    { 0x0000217c, 0x00204411, 0x000 },
+    { 0x01800000, 0x00204811, 0x000 },
+    { 0xffffffff, 0x00204811, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000000, 0x17000000, 0x000 },
+    { 0x81000000, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0004217f, 0x00604411, 0x622 },
+    { 0x0000001f, 0x00210230, 0x000 },
+    { 0x00000000, 0x14c00000, 0x621 },
+    { 0x00000010, 0x00404c11, 0x607 },
+    { 0x00000000, 0xc0200400, 0x000 },
+    { 0x00000000, 0x38c00000, 0x000 },
+    { 0x0000001d, 0x00200a2d, 0x000 },
+    { 0x0000001e, 0x00200e2d, 0x000 },
+    { 0x0000001f, 0x0020122d, 0x000 },
+    { 0x00000020, 0x0020162d, 0x000 },
+    { 0x00002169, 0x00204411, 0x000 },
+    { 0x00000000, 0x00204804, 0x000 },
+    { 0x00000000, 0x00204805, 0x000 },
+    { 0x00000000, 0x00204801, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000004, 0x00301224, 0x000 },
+    { 0x00000000, 0x002f0064, 0x000 },
+    { 0x00000000, 0x0cc00000, 0x620 },
+    { 0x00000003, 0x00281a22, 0x000 },
+    { 0x00000008, 0x00221222, 0x000 },
+    { 0xfffff000, 0x00281224, 0x000 },
+    { 0x00000000, 0x002910c4, 0x000 },
+    { 0x0000001f, 0x00403624, 0x000 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x622 },
+    { 0x9f000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x625 },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x1ac00000, 0x627 },
+    { 0x9e000000, 0x00204411, 0x000 },
+    { 0xcafebabe, 0x00204811, 0x000 },
+    { 0x00000000, 0x1ae00000, 0x62a },
+    { 0x00000000, 0x00800000, 0x000 },
+    { 0x00000000, 0x00600000, 0x00b },
+    { 0x00001000, 0x00600411, 0x315 },
+    { 0x00000000, 0x00200411, 0x000 },
+    { 0x00000000, 0x00600811, 0x1b2 },
+    { 0x0000225c, 0x00204411, 0x000 },
+    { 0x00000003, 0x00204811, 0x000 },
+    { 0x00002256, 0x00204411, 0x000 },
+    { 0x0000001b, 0x00204811, 0x000 },
+    { 0x0000a1fc, 0x00204411, 0x000 },
+    { 0x00000001, 0x00204811, 0x000 },
+    { 0x0001a1fd, 0xc0204411, 0x000 },
+    { 0x00000021, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000024, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000022, 0x0020222d, 0x000 },
+    { 0x0000ffff, 0x00282228, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00204811, 0x000 },
+    { 0x00000023, 0x00201e2d, 0x000 },
+    { 0x00000010, 0x00221e27, 0x000 },
+    { 0x00000000, 0x00294907, 0x000 },
+    { 0x00000000, 0x00404811, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
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+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x00000000, 0x00000000, 0x000 },
+    { 0x0142050a, 0x05ba0250, 0x000 },
+    { 0x01c30168, 0x044105ba, 0x000 },
+    { 0x02250209, 0x02500151, 0x000 },
+    { 0x02230245, 0x02a00241, 0x000 },
+    { 0x03d705ba, 0x05ba05ba, 0x000 },
+    { 0x05e205e3, 0x031f05ba, 0x000 },
+    { 0x032005bf, 0x0320034a, 0x000 },
+    { 0x03340282, 0x034c033e, 0x000 },
+    { 0x05ba05ba, 0x05ba05ba, 0x000 },
+    { 0x05ba0557, 0x05ba032a, 0x000 },
+    { 0x03bc05ba, 0x04c3034e, 0x000 },
+    { 0x04a20455, 0x043f05ba, 0x000 },
+    { 0x04d805ba, 0x044304e5, 0x000 },
+    { 0x0455050f, 0x035b037b, 0x000 },
+    { 0x05ba05ba, 0x05ba05ba, 0x000 },
+    { 0x05ba05ba, 0x05ba05ba, 0x000 },
+    { 0x05ba05ba, 0x05d805c1, 0x000 },
+    { 0x05ba05ba, 0x000705ba, 0x000 },
+    { 0x05ba05ba, 0x05ba05ba, 0x000 },
+    { 0x05ba05ba, 0x05ba05ba, 0x000 },
+    { 0x03f803ed, 0x04080406, 0x000 },
+    { 0x040e040a, 0x040c0410, 0x000 },
+    { 0x041c0418, 0x04240420, 0x000 },
+    { 0x042c0428, 0x04340430, 0x000 },
+    { 0x05ba05ba, 0x043a0438, 0x000 },
+    { 0x05ba05ba, 0x05ba05ba, 0x000 },
+    { 0x05ba05ba, 0x05ba05ba, 0x000 },
+    { 0x0002060e, 0x062c0006, 0x000 },
+};
+
+static const u32 RS780_pfp_microcode[]={
+0xca0400,
+0xa00000,
+0x7e828b,
+0x7c038b,
+0x8001db,
+0x7c038b,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xc41838,
+0xca2400,
+0xca2800,
+0x9581cb,
+0xc41c3a,
+0xc3c000,
+0xca0800,
+0xca0c00,
+0x7c744b,
+0xc20005,
+0x99c000,
+0xc41c3a,
+0x7c744c,
+0xc0ffe0,
+0x042c08,
+0x309002,
+0x7d2500,
+0x351402,
+0x7d350b,
+0x255407,
+0x7cd580,
+0x259c07,
+0x95c004,
+0xd5001b,
+0x7eddc1,
+0x7d9d80,
+0xd6801b,
+0xd5801b,
+0xd4401e,
+0xd5401e,
+0xd6401e,
+0xd6801e,
+0xd4801e,
+0xd4c01e,
+0x9783d3,
+0xd5c01e,
+0xca0800,
+0x80001a,
+0xca0c00,
+0xe4011e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xe4013e,
+0xd4001e,
+0x80000c,
+0xc41838,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0xca0c00,
+0x8001db,
+0xd48024,
+0xca0800,
+0x7c00c0,
+0xc81425,
+0xc81824,
+0x7c9488,
+0x7c9880,
+0xc20003,
+0xd40075,
+0x7c744c,
+0x800064,
+0xd4401e,
+0xca1800,
+0xd4401e,
+0xd5801e,
+0x800062,
+0xd40075,
+0xd4401e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd48019,
+0xd4c018,
+0xd50017,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xe2001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xd40075,
+0xd4401e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd48019,
+0xd4c018,
+0xd50017,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0x248c01,
+0xd48060,
+0x94c003,
+0x041001,
+0x041002,
+0xd50025,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xd48061,
+0xd4401e,
+0x800000,
+0xd4801e,
+0xca0800,
+0xca0c00,
+0xd4401e,
+0xd48016,
+0xd4c016,
+0xd4801e,
+0x8001db,
+0xd4c01e,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x948004,
+0xca1400,
+0xe420f3,
+0xd42013,
+0xd56065,
+0xd4e01c,
+0xd5201c,
+0xd5601c,
+0x800000,
+0x062001,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9483f7,
+0xca1400,
+0xe420f3,
+0x80009c,
+0xd42013,
+0xc60843,
+0xca0c00,
+0xca1000,
+0x9883ef,
+0xca1400,
+0xd40064,
+0x8000b0,
+0x000000,
+0xc41432,
+0xc61843,
+0xc4082f,
+0x954005,
+0xc40c30,
+0xd4401e,
+0x800000,
+0xee001e,
+0x9583f5,
+0xc41031,
+0xd44033,
+0xd52065,
+0xd4a01c,
+0xd4e01c,
+0xd5201c,
+0xe4015e,
+0xd4001e,
+0x800000,
+0x062001,
+0xca1800,
+0x0a2001,
+0xd60076,
+0xc40836,
+0x988007,
+0xc61045,
+0x950110,
+0xd4001f,
+0xd46062,
+0x800000,
+0xd42062,
+0xcc3835,
+0xcc1433,
+0x8401de,
+0xd40072,
+0xd5401e,
+0x800000,
+0xee001e,
+0xe2001a,
+0x8401de,
+0xe2001a,
+0xcc104b,
+0xcc0447,
+0x2c9401,
+0x7d098b,
+0x984005,
+0x7d15cb,
+0xd4001a,
+0x8001db,
+0xd4006d,
+0x344401,
+0xcc0c48,
+0x98403a,
+0xcc2c4a,
+0x958004,
+0xcc0449,
+0x8001db,
+0xd4001a,
+0xd4c01a,
+0x282801,
+0x840113,
+0xcc1003,
+0x98801b,
+0x04380c,
+0x840113,
+0xcc1003,
+0x988017,
+0x043808,
+0x840113,
+0xcc1003,
+0x988013,
+0x043804,
+0x840113,
+0xcc1003,
+0x988014,
+0xcc104c,
+0x9a8009,
+0xcc144d,
+0x9840dc,
+0xd4006d,
+0xcc1848,
+0xd5001a,
+0xd5401a,
+0x8000ec,
+0xd5801a,
+0x96c0d5,
+0xd4006d,
+0x8001db,
+0xd4006e,
+0x9ac003,
+0xd4006d,
+0xd4006e,
+0x800000,
+0xec007f,
+0x9ac0cc,
+0xd4006d,
+0x8001db,
+0xd4006e,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0x7d9103,
+0x7dd583,
+0x7d190c,
+0x35cc1f,
+0x35701f,
+0x7cf0cb,
+0x7cd08b,
+0x880000,
+0x7e8e8b,
+0x95c004,
+0xd4006e,
+0x8001db,
+0xd4001a,
+0xd4c01a,
+0xcc0803,
+0xcc0c03,
+0xcc1003,
+0xcc1403,
+0xcc1803,
+0xcc1c03,
+0xcc2403,
+0xcc2803,
+0x35c41f,
+0x36b01f,
+0x7c704b,
+0x34f01f,
+0x7c704b,
+0x35701f,
+0x7c704b,
+0x7d8881,
+0x7dccc1,
+0x7e5101,
+0x7e9541,
+0x7c9082,
+0x7cd4c2,
+0x7c848b,
+0x9ac003,
+0x7c8c8b,
+0x2c8801,
+0x98809e,
+0xd4006d,
+0x98409c,
+0xd4006e,
+0xcc084c,
+0xcc0c4d,
+0xcc1048,
+0xd4801a,
+0xd4c01a,
+0x800124,
+0xd5001a,
+0xcc0832,
+0xd40032,
+0x9482b6,
+0xca0c00,
+0xd4401e,
+0x800000,
+0xd4001e,
+0xe4011e,
+0xd4001e,
+0xca0800,
+0xca0c00,
+0xca1000,
+0xd4401e,
+0xca1400,
+0xd4801e,
+0xd4c01e,
+0xd5001e,
+0xd5401e,
+0xd54034,
+0x800000,
+0xee001e,
+0x280404,
+0xe2001a,
+0xe2001a,
+0xd4401a,
+0xca3800,
+0xcc0803,
+0xcc0c03,
+0xcc0c03,
+0xcc0c03,
+0x98829a,
+0x000000,
+0x8401de,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0400,
+0xc2ff00,
+0xcc0834,
+0xc13fff,
+0x7c74cb,
+0x7cc90b,
+0x7d010f,
+0x99028d,
+0x7c738b,
+0x8401de,
+0xd7a06f,
+0x800000,
+0xee001f,
+0xca0800,
+0x281900,
+0x7d898b,
+0x958014,
+0x281404,
+0xca0c00,
+0xca1000,
+0xca1c00,
+0xca2400,
+0xe2001f,
+0xd4c01a,
+0xd5001a,
+0xd5401a,
+0xcc1803,
+0xcc2c03,
+0xcc2c03,
+0xcc2c03,
+0x7da58b,
+0x7d9c47,
+0x984274,
+0x000000,
+0x800184,
+0xd4c01a,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xe4013e,
+0xd4001e,
+0xd4401e,
+0xee001e,
+0xca0400,
+0xa00000,
+0x7e828b,
+0xca0800,
+0x248c06,
+0x0ccc06,
+0x98c006,
+0xcc104e,
+0x990004,
+0xd40073,
+0xe4011e,
+0xd4001e,
+0xd4401e,
+0xd4801e,
+0x800000,
+0xee001e,
+0xca0800,
+0xca0c00,
+0x34d018,
+0x251001,
+0x950021,
+0xc17fff,
+0xca1000,
+0xca1400,
+0xca1800,
+0xd4801d,
+0xd4c01d,
+0x7db18b,
+0xc14202,
+0xc2c001,
+0xd5801d,
+0x34dc0e,
+0x7d5d4c,
+0x7f734c,
+0xd7401e,
+0xd5001e,
+0xd5401e,
+0xc14200,
+0xc2c000,
+0x099c01,
+0x31dc10,
+0x7f5f4c,
+0x7f734c,
+0x042802,
+0x7d8380,
+0xd5a86f,
+0xd58066,
+0xd7401e,
+0xec005e,
+0xc82402,
+0xc82402,
+0x8001db,
+0xd60076,
+0xd4401e,
+0xd4801e,
+0xd4c01e,
+0x800000,
+0xee001e,
+0x800000,
+0xee001f,
+0xd4001f,
+0x800000,
+0xd4001f,
+0xd4001f,
+0x880000,
+0xd4001f,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x000000,
+0x010194,
+0x02019b,
+0x0300b2,
+0x0400a2,
+0x050003,
+0x06003f,
+0x070032,
+0x08014f,
+0x090046,
+0x0a0036,
+0x1001d9,
+0x1700c5,
+0x22015d,
+0x23016c,
+0x2000d7,
+0x240148,
+0x26004d,
+0x27005c,
+0x28008d,
+0x290051,
+0x2a007e,
+0x2b0061,
+0x2f0088,
+0x3200aa,
+0x3401a2,
+0x36006f,
+0x3c0179,
+0x3f0095,
+0x4101af,
+0x440151,
+0x550196,
+0x56019d,
+0x60000b,
+0x610034,
+0x620038,
+0x630038,
+0x640038,
+0x650038,
+0x660038,
+0x670038,
+0x68003a,
+0x690041,
+0x6a0048,
+0x6b0048,
+0x6c0048,
+0x6d0048,
+0x6e0048,
+0x6f0048,
+0x7301d9,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+0x000006,
+};
+
+static const u32 RV770_cp_microcode[]={
+0xcc0003ea,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x80000001,
+0xd040007f,
+0x80000001,
+0xcc400041,
+0x7c40c000,
+0xc0160004,
+0x30d03fff,
+0x7d15000c,
+0xcc110000,
+0x28d8001e,
+0x31980001,
+0x28dc001f,
+0xc8200004,
+0x95c00006,
+0x7c424000,
+0xcc000062,
+0x7e56800c,
+0xcc290000,
+0xc8240004,
+0x7e26000b,
+0x95800006,
+0x7c42c000,
+0xcc000062,
+0x7ed7000c,
+0xcc310000,
+0xc82c0004,
+0x7e2e000c,
+0xcc000062,
+0x31103fff,
+0x80000001,
+0xce110000,
+0x7c40c000,
+0x80000001,
+0xcc400040,
+0x80000001,
+0xcc412257,
+0x7c418000,
+0xcc400045,
+0xcc400048,
+0xcc41225c,
+0xcc41a1fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xcc400045,
+0xcc400048,
+0x7c40c000,
+0xcc41225c,
+0xcc41a1fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xcc000045,
+0xcc000048,
+0xcc41225c,
+0xcc41a1fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x040ca1fd,
+0xc0120001,
+0xcc000045,
+0xcc000048,
+0x7cd0c00c,
+0xcc41225c,
+0xcc41a1fc,
+0xd04d0000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x80000001,
+0xcc41225d,
+0x7c408000,
+0x7c40c000,
+0xc02a0002,
+0x7c410000,
+0x7d29000c,
+0x30940001,
+0x30980006,
+0x309c0300,
+0x29dc0008,
+0x7c420000,
+0x7c424000,
+0x9540000f,
+0xc02e0004,
+0x05f02258,
+0x7f2f000c,
+0xcc310000,
+0xc8280004,
+0xccc12169,
+0xcd01216a,
+0xce81216b,
+0x0db40002,
+0xcc01216c,
+0x9740000e,
+0x0db40000,
+0x8000007b,
+0xc834000a,
+0x0db40002,
+0x97400009,
+0x0db40000,
+0xc02e0004,
+0x05f02258,
+0x7f2f000c,
+0xcc310000,
+0xc8280004,
+0x8000007b,
+0xc834000a,
+0x97400004,
+0x7e028000,
+0x8000007b,
+0xc834000a,
+0x0db40004,
+0x9740ff8c,
+0x00000000,
+0xce01216d,
+0xce41216e,
+0xc8280003,
+0xc834000a,
+0x9b400004,
+0x043c0005,
+0x8400026d,
+0xcc000062,
+0x0df40000,
+0x9740000b,
+0xc82c03e6,
+0xce81a2b7,
+0xc0300006,
+0x7ef34028,
+0xc0300020,
+0x7f6b8020,
+0x7fb3c029,
+0xcf81a2c4,
+0x80000001,
+0xcfc1a2d1,
+0x0df40001,
+0x9740000b,
+0xc82c03e7,
+0xce81a2bb,
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+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00010333,
+0x00100004,
+0x00170006,
+0x00210008,
+0x00270028,
+0x00280023,
+0x00290029,
+0x002a0026,
+0x002b0029,
+0x002d0038,
+0x002e003f,
+0x002f004a,
+0x0034004c,
+0x00360030,
+0x003900af,
+0x003a00d0,
+0x003b00e5,
+0x003c00fd,
+0x003d016c,
+0x003f00ad,
+0x00410338,
+0x0043036c,
+0x0044018f,
+0x004500fd,
+0x004601ad,
+0x004701ad,
+0x00480200,
+0x0049020e,
+0x004a0257,
+0x004b0284,
+0x00520261,
+0x00530273,
+0x00540289,
+0x0057029b,
+0x0060029f,
+0x006102ae,
+0x006202b8,
+0x006302c2,
+0x006402cc,
+0x006502d6,
+0x006602e0,
+0x006702ea,
+0x006802f4,
+0x006902f8,
+0x006a02fc,
+0x006b0300,
+0x006c0304,
+0x006d0308,
+0x006e030c,
+0x006f0310,
+0x00700314,
+0x00720386,
+0x0074038c,
+0x0079038a,
+0x007c031e,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+0x000f039b,
+};
+
+static const u32 RV770_pfp_microcode[]={
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0x80000000,
+0xdc030000,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xc818000e,
+0x31980001,
+0x7c424000,
+0x95800252,
+0x7c428000,
+0xc81c001c,
+0xc037c000,
+0x7c40c000,
+0x7c410000,
+0x7cb4800b,
+0xc0360003,
+0x99c00000,
+0xc81c001c,
+0x7cb4800c,
+0x24d40002,
+0x7d654000,
+0xcd400043,
+0xce800043,
+0xcd000043,
+0xcc800040,
+0xce400040,
+0xce800040,
+0xccc00040,
+0xdc3a0000,
+0x9780ffde,
+0xcd000040,
+0x7c40c000,
+0x80000018,
+0x7c410000,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xc818000e,
+0x8000000c,
+0x31980002,
+0xd40003c0,
+0xd4000fc0,
+0xd4000fa2,
+0xc818000e,
+0x288c0008,
+0x30cc000f,
+0x34100001,
+0x7d0d0008,
+0x8000000c,
+0x7d91800b,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xd40003c0,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xcc4003f9,
+0x80000261,
+0xcc4003f8,
+0xc82003f8,
+0xc81c03f9,
+0xc81803fb,
+0xc037ffff,
+0x7c414000,
+0xcf41a29e,
+0x66200020,
+0x7de1c02c,
+0x7d58c008,
+0x7cdcc020,
+0x68d00020,
+0xc0360003,
+0xcc000054,
+0x7cb4800c,
+0x8000006a,
+0xcc800040,
+0x7c418000,
+0xcd81a29e,
+0xcc800040,
+0xcd800040,
+0x80000068,
+0xcc000054,
+0xc019ffff,
+0xcc800040,
+0xcd81a29e,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0xccc1a1fa,
+0xcd01a1f9,
+0xcd41a29d,
+0xccc00040,
+0xcd000040,
+0xcd400040,
+0xcc400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xcc000054,
+0xcc800040,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0xccc1a1fa,
+0xcd01a1f9,
+0xcd41a29d,
+0xccc00040,
+0xcd000040,
+0xcd400040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0x7c40c000,
+0x30d00001,
+0xccc1a29f,
+0x95000003,
+0x04140001,
+0x04140002,
+0xcd4003fb,
+0xcc800040,
+0x80000000,
+0xccc00040,
+0x7c40c000,
+0xcc800040,
+0xccc1a2a2,
+0x80000000,
+0xccc00040,
+0x7c40c000,
+0x28d4001f,
+0xcc800040,
+0x95400003,
+0x7c410000,
+0xccc00057,
+0x2918001f,
+0xccc00040,
+0x95800003,
+0xcd000040,
+0xcd000058,
+0x80000261,
+0xcc00007f,
+0xc8200017,
+0xc8300022,
+0x9a000006,
+0x0e280001,
+0xc824001e,
+0x0a640001,
+0xd4001240,
+0xce400040,
+0xc036c000,
+0x96800007,
+0x37747900,
+0x041c0001,
+0xcf400040,
+0xcdc00040,
+0xcf0003fa,
+0x7c030000,
+0xca0c0010,
+0x7c410000,
+0x94c00004,
+0x7c414000,
+0xd42002c4,
+0xcde00044,
+0x9b00000b,
+0x7c418000,
+0xcc00004b,
+0xcda00049,
+0xcd200041,
+0xcd600041,
+0xcda00041,
+0x06200001,
+0xce000056,
+0x80000261,
+0xcc00007f,
+0xc8280020,
+0xc82c0021,
+0xcc000063,
+0x7eea4001,
+0x65740020,
+0x7f53402c,
+0x269c0002,
+0x7df5c020,
+0x69f80020,
+0xce80004b,
+0xce600049,
+0xcde00041,
+0xcfa00041,
+0xce600041,
+0x271c0002,
+0x7df5c020,
+0x69f80020,
+0x7db24001,
+0xcf00004b,
+0xce600049,
+0xcde00041,
+0xcfa00041,
+0x800000bd,
+0xce600041,
+0xc8200017,
+0xc8300022,
+0x9a000006,
+0x0e280001,
+0xc824001e,
+0x0a640001,
+0xd4001240,
+0xce400040,
+0xca0c0010,
+0x7c410000,
+0x94c0000b,
+0xc036c000,
+0x96800007,
+0x37747900,
+0x041c0001,
+0xcf400040,
+0xcdc00040,
+0xcf0003fa,
+0x7c030000,
+0x800000b6,
+0x7c414000,
+0xcc000048,
+0x800000ef,
+0x00000000,
+0xc8200017,
+0xc81c0023,
+0x0e240002,
+0x99c00015,
+0x7c418000,
+0x0a200001,
+0xce000056,
+0xd4000440,
+0xcc000040,
+0xc036c000,
+0xca140013,
+0x96400007,
+0x37747900,
+0xcf400040,
+0xcc000040,
+0xc83003fa,
+0x80000104,
+0xcf000022,
+0xcc000022,
+0x9540015d,
+0xcc00007f,
+0xcca00046,
+0x80000000,
+0xcc200046,
+0x80000261,
+0xcc000064,
+0xc8200017,
+0xc810001f,
+0x96000005,
+0x09100001,
+0xd4000440,
+0xcd000040,
+0xcd000022,
+0xcc800040,
+0xd0400040,
+0xc80c0025,
+0x94c0feeb,
+0xc8100008,
+0xcd000040,
+0xd4000fc0,
+0x80000000,
+0xd4000fa2,
+0x7c40c000,
+0x7c410000,
+0xccc003fd,
+0xcd0003fc,
+0xccc00042,
+0xcd000042,
+0x2914001f,
+0x29180010,
+0x31980007,
+0x3b5c0001,
+0x7d76000b,
+0x99800005,
+0x7d5e400b,
+0xcc000042,
+0x80000261,
+0xcc00004d,
+0x29980001,
+0x292c0008,
+0x9980003d,
+0x32ec0001,
+0x96000004,
+0x2930000c,
+0x80000261,
+0xcc000042,
+0x04140010,
+0xcd400042,
+0x33300001,
+0x34280001,
+0x8400015e,
+0xc8140003,
+0x9b40001b,
+0x0438000c,
+0x8400015e,
+0xc8140003,
+0x9b400017,
+0x04380008,
+0x8400015e,
+0xc8140003,
+0x9b400013,
+0x04380004,
+0x8400015e,
+0xc8140003,
+0x9b400015,
+0xc80c03fd,
+0x9a800009,
+0xc81003fc,
+0x9b000118,
+0xcc00004d,
+0x04140010,
+0xccc00042,
+0xcd000042,
+0x80000136,
+0xcd400042,
+0x96c00111,
+0xcc00004d,
+0x80000261,
+0xcc00004e,
+0x9ac00003,
+0xcc00004d,
+0xcc00004e,
+0xdf830000,
+0x80000000,
+0xd80301ff,
+0x9ac00107,
+0xcc00004d,
+0x80000261,
+0xcc00004e,
+0xc8180003,
+0xc81c0003,
+0xc8200003,
+0x7d5d4003,
+0x7da1c003,
+0x7d5d400c,
+0x2a10001f,
+0x299c001f,
+0x7d1d000b,
+0x7d17400b,
+0x88000000,
+0x7e92800b,
+0x96400004,
+0xcc00004e,
+0x80000261,
+0xcc000042,
+0x04380008,
+0xcf800042,
+0xc8080003,
+0xc80c0003,
+0xc8100003,
+0xc8140003,
+0xc8180003,
+0xc81c0003,
+0xc8240003,
+0xc8280003,
+0x29fc001f,
+0x2ab0001f,
+0x7ff3c00b,
+0x28f0001f,
+0x7ff3c00b,
+0x2970001f,
+0x7ff3c00b,
+0x7d888001,
+0x7dccc001,
+0x7e510001,
+0x7e954001,
+0x7c908002,
+0x7cd4c002,
+0x7cbc800b,
+0x9ac00003,
+0x7c8f400b,
+0x38b40001,
+0x9b4000d8,
+0xcc00004d,
+0x9bc000d6,
+0xcc00004e,
+0xc80c03fd,
+0xc81003fc,
+0xccc00042,
+0x8000016f,
+0xcd000042,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xcc400040,
+0xcc400040,
+0xcc400040,
+0x7c40c000,
+0xccc00040,
+0xccc0000d,
+0x80000000,
+0xd0400040,
+0x7c40c000,
+0x7c410000,
+0x65140020,
+0x7d4d402c,
+0x24580002,
+0x7d598020,
+0x7c41c000,
+0xcd800042,
+0x69980020,
+0xcd800042,
+0xcdc00042,
+0xc023c000,
+0x05e40002,
+0x7ca0800b,
+0x26640010,
+0x7ca4800c,
+0xcc800040,
+0xcdc00040,
+0xccc00040,
+0x95c0000e,
+0xcd000040,
+0x09dc0001,
+0xc8280003,
+0x96800008,
+0xce800040,
+0xc834001d,
+0x97400000,
+0xc834001d,
+0x26a80008,
+0x84000264,
+0xcc2b0000,
+0x99c0fff7,
+0x09dc0001,
+0xdc3a0000,
+0x97800004,
+0x7c418000,
+0x800001a3,
+0x25980002,
+0xa0000000,
+0x7d808000,
+0xc818001d,
+0x7c40c000,
+0x64d00008,
+0x95800000,
+0xc818001d,
+0xcc130000,
+0xcc800040,
+0xccc00040,
+0x80000000,
+0xcc400040,
+0xc810001f,
+0x7c40c000,
+0xcc800040,
+0x7cd1400c,
+0xcd400040,
+0x05180001,
+0x80000000,
+0xcd800022,
+0x7c40c000,
+0x64500020,
+0x84000264,
+0xcc000061,
+0x7cd0c02c,
+0xc8200017,
+0xc8d60000,
+0x99400008,
+0x7c438000,
+0xdf830000,
+0xcfa0004f,
+0x84000264,
+0xcc000062,
+0x80000000,
+0xd040007f,
+0x80000261,
+0xcc000062,
+0x84000264,
+0xcc000061,
+0xc8200017,
+0x7c40c000,
+0xc036ff00,
+0xc810000d,
+0xc0303fff,
+0x7cf5400b,
+0x7d51800b,
+0x7d81800f,
+0x99800008,
+0x7cf3800b,
+0xdf830000,
+0xcfa0004f,
+0x84000264,
+0xcc000062,
+0x80000000,
+0xd040007f,
+0x80000261,
+0xcc000062,
+0x84000264,
+0x7c40c000,
+0x28dc0008,
+0x95c00019,
+0x30dc0010,
+0x7c410000,
+0x99c00004,
+0x64540020,
+0x80000209,
+0xc91d0000,
+0x7d15002c,
+0xc91e0000,
+0x7c420000,
+0x7c424000,
+0x7c418000,
+0x7de5c00b,
+0x7de28007,
+0x9a80000e,
+0x41ac0005,
+0x9ac00000,
+0x0aec0001,
+0x30dc0010,
+0x99c00004,
+0x00000000,
+0x8000020c,
+0xc91d0000,
+0x8000020c,
+0xc91e0000,
+0xcc800040,
+0xccc00040,
+0xd0400040,
+0xc80c0025,
+0x94c0fde3,
+0xc8100008,
+0xcd000040,
+0xd4000fc0,
+0x80000000,
+0xd4000fa2,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xd40003c0,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0x7c40c000,
+0x30d00006,
+0x0d100006,
+0x99000007,
+0xc8140015,
+0x99400005,
+0xcc000052,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xccc00040,
+0x80000000,
+0xd0400040,
+0x7c40c000,
+0xcc4d0000,
+0xdc3a0000,
+0x9780fdbc,
+0x04cc0001,
+0x80000243,
+0xcc4d0000,
+0x7c40c000,
+0x7c410000,
+0x29240018,
+0x32640001,
+0x9640000f,
+0xcc800040,
+0x7c414000,
+0x7c418000,
+0x7c41c000,
+0xccc00043,
+0xcd000043,
+0x31dc7fff,
+0xcdc00043,
+0xccc00040,
+0xcd000040,
+0xcd400040,
+0xcd800040,
+0x80000000,
+0xcdc00040,
+0xccc00040,
+0xcd000040,
+0x80000000,
+0xd0400040,
+0x80000000,
+0xd040007f,
+0xcc00007f,
+0x80000000,
+0xcc00007f,
+0xcc00007f,
+0x88000000,
+0xcc00007f,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00030223,
+0x0004022b,
+0x000500a0,
+0x00020003,
+0x0006003c,
+0x00070027,
+0x00080192,
+0x00090044,
+0x000a002d,
+0x0010025f,
+0x001700f1,
+0x002201d8,
+0x002301e9,
+0x0026004c,
+0x0027005f,
+0x0020011b,
+0x00280093,
+0x0029004f,
+0x002a0084,
+0x002b0065,
+0x002f008e,
+0x003200d9,
+0x00340233,
+0x00360075,
+0x0039010b,
+0x003c01fd,
+0x003f00a0,
+0x00410248,
+0x00440195,
+0x0048019e,
+0x004901c6,
+0x004a01d0,
+0x00550226,
+0x0056022e,
+0x0060000a,
+0x0061002a,
+0x00620030,
+0x00630030,
+0x00640030,
+0x00650030,
+0x00660030,
+0x00670030,
+0x00680037,
+0x0069003f,
+0x006a0047,
+0x006b0047,
+0x006c0047,
+0x006d0047,
+0x006e0047,
+0x006f0047,
+0x00700047,
+0x0073025f,
+0x007b0241,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+};
+
+static const u32 RV730_pfp_microcode[]={
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0x80000000,
+0xdc030000,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xc818000e,
+0x31980001,
+0x7c424000,
+0x9580023a,
+0x7c428000,
+0xc81c001c,
+0xc037c000,
+0x7c40c000,
+0x7c410000,
+0x7cb4800b,
+0xc0360003,
+0x99c00000,
+0xc81c001c,
+0x7cb4800c,
+0x24d40002,
+0x7d654000,
+0xcd400043,
+0xce800043,
+0xcd000043,
+0xcc800040,
+0xce400040,
+0xce800040,
+0xccc00040,
+0xdc3a0000,
+0x9780ffde,
+0xcd000040,
+0x7c40c000,
+0x80000018,
+0x7c410000,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xc818000e,
+0x8000000c,
+0x31980002,
+0xd40003c0,
+0xd4000fc0,
+0xd4000fa2,
+0xc818000e,
+0x288c0008,
+0x30cc000f,
+0x34100001,
+0x7d0d0008,
+0x8000000c,
+0x7d91800b,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xd40003c0,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xcc4003f9,
+0x80000249,
+0xcc4003f8,
+0xc037ffff,
+0x7c414000,
+0xcf41a29e,
+0xc82003f8,
+0xc81c03f9,
+0x66200020,
+0xc81803fb,
+0x7de1c02c,
+0x7d58c008,
+0x7cdcc020,
+0x69100020,
+0xc0360003,
+0xcc000054,
+0x7cb4800c,
+0x80000069,
+0xcc800040,
+0x7c418000,
+0xcd81a29e,
+0xcc800040,
+0x80000067,
+0xcd800040,
+0xc019ffff,
+0xcc800040,
+0xcd81a29e,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0xccc1a1fa,
+0xcd01a1f9,
+0xcd41a29d,
+0xccc00040,
+0xcd000040,
+0xcd400040,
+0xcc400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xcc000054,
+0xcc800040,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0xccc1a1fa,
+0xcd01a1f9,
+0xcd41a29d,
+0xccc00040,
+0xcd000040,
+0xcd400040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0x7c40c000,
+0x30d00001,
+0xccc1a29f,
+0x95000003,
+0x04140001,
+0x04140002,
+0xcd4003fb,
+0xcc800040,
+0x80000000,
+0xccc00040,
+0x7c40c000,
+0xcc800040,
+0xccc1a2a2,
+0x80000000,
+0xccc00040,
+0x7c40c000,
+0x28d4001f,
+0xcc800040,
+0x95400003,
+0x7c410000,
+0xccc00057,
+0x2918001f,
+0xccc00040,
+0x95800003,
+0xcd000040,
+0xcd000058,
+0x80000249,
+0xcc00007f,
+0xc8200017,
+0xc8300022,
+0x9a000006,
+0x0e280001,
+0xc824001e,
+0x0a640001,
+0xd4001240,
+0xce400040,
+0xc036c000,
+0x96800007,
+0x37747900,
+0x041c0001,
+0xcf400040,
+0xcdc00040,
+0xcf0003fa,
+0x7c030000,
+0xca0c0010,
+0x7c410000,
+0x94c00004,
+0x7c414000,
+0xd42002c4,
+0xcde00044,
+0x9b00000b,
+0x7c418000,
+0xcc00004b,
+0xcda00049,
+0xcd200041,
+0xcd600041,
+0xcda00041,
+0x06200001,
+0xce000056,
+0x80000249,
+0xcc00007f,
+0xc8280020,
+0xc82c0021,
+0xcc000063,
+0x7eea4001,
+0x65740020,
+0x7f53402c,
+0x269c0002,
+0x7df5c020,
+0x69f80020,
+0xce80004b,
+0xce600049,
+0xcde00041,
+0xcfa00041,
+0xce600041,
+0x271c0002,
+0x7df5c020,
+0x69f80020,
+0x7db24001,
+0xcf00004b,
+0xce600049,
+0xcde00041,
+0xcfa00041,
+0x800000bc,
+0xce600041,
+0xc8200017,
+0xc8300022,
+0x9a000006,
+0x0e280001,
+0xc824001e,
+0x0a640001,
+0xd4001240,
+0xce400040,
+0xca0c0010,
+0x7c410000,
+0x94c0000b,
+0xc036c000,
+0x96800007,
+0x37747900,
+0x041c0001,
+0xcf400040,
+0xcdc00040,
+0xcf0003fa,
+0x7c030000,
+0x800000b5,
+0x7c414000,
+0xcc000048,
+0x800000ee,
+0x00000000,
+0xc8200017,
+0xc81c0023,
+0x0e240002,
+0x99c00015,
+0x7c418000,
+0x0a200001,
+0xce000056,
+0xd4000440,
+0xcc000040,
+0xc036c000,
+0xca140013,
+0x96400007,
+0x37747900,
+0xcf400040,
+0xcc000040,
+0xc83003fa,
+0x80000103,
+0xcf000022,
+0xcc000022,
+0x95400146,
+0xcc00007f,
+0xcca00046,
+0x80000000,
+0xcc200046,
+0x80000249,
+0xcc000064,
+0xc8200017,
+0xc810001f,
+0x96000005,
+0x09100001,
+0xd4000440,
+0xcd000040,
+0xcd000022,
+0xcc800040,
+0xd0400040,
+0xc80c0025,
+0x94c0feec,
+0xc8100008,
+0xcd000040,
+0xd4000fc0,
+0x80000000,
+0xd4000fa2,
+0x7c40c000,
+0x7c410000,
+0xccc003fd,
+0xcd0003fc,
+0xccc00042,
+0xcd000042,
+0x2914001f,
+0x29180010,
+0x31980007,
+0x3b5c0001,
+0x7d76000b,
+0x99800005,
+0x7d5e400b,
+0xcc000042,
+0x80000249,
+0xcc00004d,
+0x29980001,
+0x292c0008,
+0x9980003d,
+0x32ec0001,
+0x96000004,
+0x2930000c,
+0x80000249,
+0xcc000042,
+0x04140010,
+0xcd400042,
+0x33300001,
+0x34280001,
+0x8400015d,
+0xc8140003,
+0x9b40001b,
+0x0438000c,
+0x8400015d,
+0xc8140003,
+0x9b400017,
+0x04380008,
+0x8400015d,
+0xc8140003,
+0x9b400013,
+0x04380004,
+0x8400015d,
+0xc8140003,
+0x9b400015,
+0xc80c03fd,
+0x9a800009,
+0xc81003fc,
+0x9b000101,
+0xcc00004d,
+0x04140010,
+0xccc00042,
+0xcd000042,
+0x80000135,
+0xcd400042,
+0x96c000fa,
+0xcc00004d,
+0x80000249,
+0xcc00004e,
+0x9ac00003,
+0xcc00004d,
+0xcc00004e,
+0xdf830000,
+0x80000000,
+0xd80301ff,
+0x9ac000f0,
+0xcc00004d,
+0x80000249,
+0xcc00004e,
+0xc8180003,
+0xc81c0003,
+0xc8200003,
+0x7d5d4003,
+0x7da1c003,
+0x7d5d400c,
+0x2a10001f,
+0x299c001f,
+0x7d1d000b,
+0x7d17400b,
+0x88000000,
+0x7e92800b,
+0x96400004,
+0xcc00004e,
+0x80000249,
+0xcc000042,
+0x04380008,
+0xcf800042,
+0xc8080003,
+0xc80c0003,
+0xc8100003,
+0xc8140003,
+0xc8180003,
+0xc81c0003,
+0xc8240003,
+0xc8280003,
+0x29fc001f,
+0x2ab0001f,
+0x7ff3c00b,
+0x28f0001f,
+0x7ff3c00b,
+0x2970001f,
+0x7ff3c00b,
+0x7d888001,
+0x7dccc001,
+0x7e510001,
+0x7e954001,
+0x7c908002,
+0x7cd4c002,
+0x7cbc800b,
+0x9ac00003,
+0x7c8f400b,
+0x38b40001,
+0x9b4000c1,
+0xcc00004d,
+0x9bc000bf,
+0xcc00004e,
+0xc80c03fd,
+0xc81003fc,
+0xccc00042,
+0x8000016e,
+0xcd000042,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xcc400040,
+0xcc400040,
+0xcc400040,
+0x7c40c000,
+0xccc00040,
+0xccc0000d,
+0x80000000,
+0xd0400040,
+0x7c40c000,
+0x7c410000,
+0x65140020,
+0x7d4d402c,
+0x24580002,
+0x7d598020,
+0x7c41c000,
+0xcd800042,
+0x69980020,
+0xcd800042,
+0xcdc00042,
+0xc023c000,
+0x05e40002,
+0x7ca0800b,
+0x26640010,
+0x7ca4800c,
+0xcc800040,
+0xcdc00040,
+0xccc00040,
+0x95c0000e,
+0xcd000040,
+0x09dc0001,
+0xc8280003,
+0x96800008,
+0xce800040,
+0xc834001d,
+0x97400000,
+0xc834001d,
+0x26a80008,
+0x8400024c,
+0xcc2b0000,
+0x99c0fff7,
+0x09dc0001,
+0xdc3a0000,
+0x97800004,
+0x7c418000,
+0x800001a2,
+0x25980002,
+0xa0000000,
+0x7d808000,
+0xc818001d,
+0x7c40c000,
+0x64d00008,
+0x95800000,
+0xc818001d,
+0xcc130000,
+0xcc800040,
+0xccc00040,
+0x80000000,
+0xcc400040,
+0xc810001f,
+0x7c40c000,
+0xcc800040,
+0x7cd1400c,
+0xcd400040,
+0x05180001,
+0x80000000,
+0xcd800022,
+0x7c40c000,
+0x64500020,
+0x8400024c,
+0xcc000061,
+0x7cd0c02c,
+0xc8200017,
+0xc8d60000,
+0x99400008,
+0x7c438000,
+0xdf830000,
+0xcfa0004f,
+0x8400024c,
+0xcc000062,
+0x80000000,
+0xd040007f,
+0x80000249,
+0xcc000062,
+0x8400024c,
+0xcc000061,
+0xc8200017,
+0x7c40c000,
+0xc036ff00,
+0xc810000d,
+0xc0303fff,
+0x7cf5400b,
+0x7d51800b,
+0x7d81800f,
+0x99800008,
+0x7cf3800b,
+0xdf830000,
+0xcfa0004f,
+0x8400024c,
+0xcc000062,
+0x80000000,
+0xd040007f,
+0x80000249,
+0xcc000062,
+0x8400024c,
+0x7c40c000,
+0x28dc0008,
+0x95c00019,
+0x30dc0010,
+0x7c410000,
+0x99c00004,
+0x64540020,
+0x80000208,
+0xc91d0000,
+0x7d15002c,
+0xc91e0000,
+0x7c420000,
+0x7c424000,
+0x7c418000,
+0x7de5c00b,
+0x7de28007,
+0x9a80000e,
+0x41ac0005,
+0x9ac00000,
+0x0aec0001,
+0x30dc0010,
+0x99c00004,
+0x00000000,
+0x8000020b,
+0xc91d0000,
+0x8000020b,
+0xc91e0000,
+0xcc800040,
+0xccc00040,
+0xd0400040,
+0xc80c0025,
+0x94c0fde4,
+0xc8100008,
+0xcd000040,
+0xd4000fc0,
+0x80000000,
+0xd4000fa2,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xd40003c0,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0x7c40c000,
+0x30d00006,
+0x0d100006,
+0x99000007,
+0xc8140015,
+0x99400005,
+0xcc000052,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xccc00040,
+0x80000000,
+0xd0400040,
+0x7c40c000,
+0xcc4d0000,
+0xdc3a0000,
+0x9780fdbd,
+0x04cc0001,
+0x80000242,
+0xcc4d0000,
+0x80000000,
+0xd040007f,
+0xcc00007f,
+0x80000000,
+0xcc00007f,
+0xcc00007f,
+0x88000000,
+0xcc00007f,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00030222,
+0x0004022a,
+0x0005009f,
+0x00020003,
+0x0006003c,
+0x00070027,
+0x00080191,
+0x00090044,
+0x000a002d,
+0x00100247,
+0x001700f0,
+0x002201d7,
+0x002301e8,
+0x0026004c,
+0x0027005f,
+0x0020011a,
+0x00280092,
+0x0029004f,
+0x002a0083,
+0x002b0064,
+0x002f008d,
+0x003200d8,
+0x00340232,
+0x00360074,
+0x0039010a,
+0x003c01fc,
+0x003f009f,
+0x00410005,
+0x00440194,
+0x0048019d,
+0x004901c5,
+0x004a01cf,
+0x00550225,
+0x0056022d,
+0x0060000a,
+0x0061002a,
+0x00620030,
+0x00630030,
+0x00640030,
+0x00650030,
+0x00660030,
+0x00670030,
+0x00680037,
+0x0069003f,
+0x006a0047,
+0x006b0047,
+0x006c0047,
+0x006d0047,
+0x006e0047,
+0x006f0047,
+0x00700047,
+0x00730247,
+0x007b0240,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+};
+
+static const u32 RV730_cp_microcode[]={
+0xcc0003ea,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x80000001,
+0xd040007f,
+0x80000001,
+0xcc400041,
+0x7c40c000,
+0xc0160004,
+0x30d03fff,
+0x7d15000c,
+0xcc110000,
+0x28d8001e,
+0x31980001,
+0x28dc001f,
+0xc8200004,
+0x95c00006,
+0x7c424000,
+0xcc000062,
+0x7e56800c,
+0xcc290000,
+0xc8240004,
+0x7e26000b,
+0x95800006,
+0x7c42c000,
+0xcc000062,
+0x7ed7000c,
+0xcc310000,
+0xc82c0004,
+0x7e2e000c,
+0xcc000062,
+0x31103fff,
+0x80000001,
+0xce110000,
+0x7c40c000,
+0x80000001,
+0xcc400040,
+0x80000001,
+0xcc412257,
+0x7c418000,
+0xcc400045,
+0xcc400048,
+0xcc41225c,
+0xcc41a1fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xcc400045,
+0xcc400048,
+0x7c40c000,
+0xcc41225c,
+0xcc41a1fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xcc000045,
+0xcc000048,
+0xcc41225c,
+0xcc41a1fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x040ca1fd,
+0xc0120001,
+0xcc000045,
+0xcc000048,
+0x7cd0c00c,
+0xcc41225c,
+0xcc41a1fc,
+0xd04d0000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x80000001,
+0xcc41225d,
+0x7c408000,
+0x7c40c000,
+0xc02a0002,
+0x7c410000,
+0x7d29000c,
+0x30940001,
+0x30980006,
+0x309c0300,
+0x29dc0008,
+0x7c420000,
+0x7c424000,
+0x9540000f,
+0xc02e0004,
+0x05f02258,
+0x7f2f000c,
+0xcc310000,
+0xc8280004,
+0xccc12169,
+0xcd01216a,
+0xce81216b,
+0x0db40002,
+0xcc01216c,
+0x9740000e,
+0x0db40000,
+0x8000007b,
+0xc834000a,
+0x0db40002,
+0x97400009,
+0x0db40000,
+0xc02e0004,
+0x05f02258,
+0x7f2f000c,
+0xcc310000,
+0xc8280004,
+0x8000007b,
+0xc834000a,
+0x97400004,
+0x7e028000,
+0x8000007b,
+0xc834000a,
+0x0db40004,
+0x9740ff8c,
+0x00000000,
+0xce01216d,
+0xce41216e,
+0xc8280003,
+0xc834000a,
+0x9b400004,
+0x043c0005,
+0x8400026b,
+0xcc000062,
+0x0df40000,
+0x9740000b,
+0xc82c03e6,
+0xce81a2b7,
+0xc0300006,
+0x7ef34028,
+0xc0300020,
+0x7f6b8020,
+0x7fb3c029,
+0xcf81a2c4,
+0x80000001,
+0xcfc1a2d1,
+0x0df40001,
+0x9740000b,
+0xc82c03e7,
+0xce81a2bb,
+0xc0300006,
+0x7ef34028,
+0xc0300020,
+0x7f6b8020,
+0x7fb3c029,
+0xcf81a2c5,
+0x80000001,
+0xcfc1a2d2,
+0x0df40002,
+0x9740000b,
+0xc82c03e8,
+0xce81a2bf,
+0xc0300006,
+0x7ef34028,
+0xc0300020,
+0x7f6b8020,
+0x7fb3c029,
+0xcf81a2c6,
+0x80000001,
+0xcfc1a2d3,
+0xc82c03e9,
+0xce81a2c3,
+0xc0300006,
+0x7ef34028,
+0xc0300020,
+0x7f6b8020,
+0x7fb3c029,
+0xcf81a2c7,
+0x80000001,
+0xcfc1a2d4,
+0x80000001,
+0xcc400042,
+0x7c40c000,
+0x7c410000,
+0x2914001d,
+0x31540001,
+0x9940000c,
+0x31181000,
+0xc81c0011,
+0x95c00000,
+0xc81c0011,
+0xccc12100,
+0xcd012101,
+0xccc12102,
+0xcd012103,
+0x04180004,
+0x8000037c,
+0xcd81a2a4,
+0xc02a0004,
+0x95800008,
+0x36a821a3,
+0xcc290000,
+0xc8280004,
+0xc81c0011,
+0x0de40040,
+0x9640ffff,
+0xc81c0011,
+0xccc12170,
+0xcd012171,
+0xc8200012,
+0x96000000,
+0xc8200012,
+0x8000037c,
+0xcc000064,
+0x7c40c000,
+0x7c410000,
+0xcc000045,
+0xcc000048,
+0x40d40003,
+0xcd41225c,
+0xcd01a1fc,
+0xc01a0001,
+0x041ca1fd,
+0x7dd9c00c,
+0x7c420000,
+0x08cc0001,
+0x06240001,
+0x06280002,
+0xce1d0000,
+0xce5d0000,
+0x98c0fffa,
+0xce9d0000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x7c40c000,
+0x30d00001,
+0x28cc0001,
+0x7c414000,
+0x95000006,
+0x7c418000,
+0xcd41216d,
+0xcd81216e,
+0x800000f2,
+0xc81c0003,
+0xc0220004,
+0x7e16000c,
+0xcc210000,
+0xc81c0004,
+0x7c424000,
+0x98c00004,
+0x7c428000,
+0x80000001,
+0xcde50000,
+0xce412169,
+0xce81216a,
+0xcdc1216b,
+0x80000001,
+0xcc01216c,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0x7c41c000,
+0x28a40008,
+0x326400ff,
+0x0e68003c,
+0x9680000a,
+0x7c020000,
+0x7c420000,
+0x1e300003,
+0xcc00006a,
+0x9b000003,
+0x42200005,
+0x04200040,
+0x8000010f,
+0x7c024000,
+0x7e024000,
+0x9a400000,
+0x0a640001,
+0x30ec0010,
+0x9ac0000a,
+0xcc000062,
+0xc02a0004,
+0xc82c0021,
+0x7e92800c,
+0xcc000041,
+0xcc290000,
+0xcec00021,
+0x8000011f,
+0xc8300004,
+0xcd01216d,
+0xcd41216e,
+0xc8300003,
+0x7f1f000b,
+0x30f40007,
+0x27780001,
+0x9740002a,
+0x07b80124,
+0x9f800000,
+0x00000000,
+0x80000134,
+0x7f1b8004,
+0x80000138,
+0x7f1b8005,
+0x8000013c,
+0x7f1b8002,
+0x80000140,
+0x7f1b8003,
+0x80000144,
+0x7f1b8007,
+0x80000148,
+0x7f1b8006,
+0x8000014d,
+0x28a40008,
+0x9b800019,
+0x28a40008,
+0x8000015d,
+0x326400ff,
+0x9b800015,
+0x28a40008,
+0x8000015d,
+0x326400ff,
+0x9b800011,
+0x28a40008,
+0x8000015d,
+0x326400ff,
+0x9b80000d,
+0x28a40008,
+0x8000015d,
+0x326400ff,
+0x9b800009,
+0x28a40008,
+0x8000015d,
+0x326400ff,
+0x9b800005,
+0x28a40008,
+0x8000015d,
+0x326400ff,
+0x28a40008,
+0x326400ff,
+0x0e68003c,
+0x9a80feb2,
+0x28ec0008,
+0x7c434000,
+0x7c438000,
+0x7c43c000,
+0x96c00007,
+0xcc000062,
+0xcf412169,
+0xcf81216a,
+0xcfc1216b,
+0x80000001,
+0xcc01216c,
+0x80000001,
+0xcff50000,
+0xcc00006b,
+0x8400037f,
+0x0e68003c,
+0x9a800004,
+0xc8280015,
+0x80000001,
+0xd040007f,
+0x9680ffab,
+0x7e024000,
+0x84000239,
+0xc00e0002,
+0xcc000041,
+0x80000237,
+0xccc1304a,
+0x7c40c000,
+0x7c410000,
+0xc01e0001,
+0x29240012,
+0xc0220002,
+0x96400005,
+0xc0260004,
+0xc027fffb,
+0x7d25000b,
+0xc0260000,
+0x7dd2800b,
+0x7e12c00b,
+0x7d25000c,
+0x7c414000,
+0x7c418000,
+0xccc12169,
+0x9a80000a,
+0xcd01216a,
+0xcd41216b,
+0x96c0fe83,
+0xcd81216c,
+0xc8300018,
+0x97000000,
+0xc8300018,
+0x80000001,
+0xcc000018,
+0x8400037f,
+0xcc00007f,
+0xc8140013,
+0xc8180014,
+0xcd41216b,
+0x96c0fe77,
+0xcd81216c,
+0x80000181,
+0xc8300018,
+0xc80c0008,
+0x98c00000,
+0xc80c0008,
+0x7c410000,
+0x95000002,
+0x00000000,
+0x7c414000,
+0xc8200009,
+0xcc400043,
+0xce01a1f4,
+0xcc400044,
+0xc00e8000,
+0x7c424000,
+0x7c428000,
+0x2aac001f,
+0x96c0fe64,
+0xc035f000,
+0xce4003e2,
+0x32780003,
+0x267c0008,
+0x7ff7c00b,
+0x7ffbc00c,
+0x2a780018,
+0xcfc003e3,
+0xcf8003e4,
+0x26b00002,
+0x7f3f0000,
+0xcf0003e5,
+0x8000031d,
+0x7c80c000,
+0x7c40c000,
+0x28d00008,
+0x3110000f,
+0x9500000f,
+0x25280001,
+0x06a801b2,
+0x9e800000,
+0x00000000,
+0x800001d3,
+0xc0120800,
+0x800001e1,
+0xc814000f,
+0x800001e8,
+0xc8140010,
+0x800001ef,
+0xccc1a2a4,
+0x800001f8,
+0xc8140011,
+0x30d0003f,
+0x0d280015,
+0x9a800012,
+0x0d28001e,
+0x9a80001e,
+0x0d280020,
+0x9a800023,
+0x0d24000f,
+0x0d280010,
+0x7e6a800c,
+0x9a800026,
+0x0d200004,
+0x0d240014,
+0x0d280028,
+0x7e62400c,
+0x7ea6800c,
+0x9a80002a,
+0xc8140011,
+0x80000001,
+0xccc1a2a4,
+0xc0120800,
+0x7c414000,
+0x7d0cc00c,
+0xc0120008,
+0x29580003,
+0x295c000c,
+0x7c420000,
+0x7dd1c00b,
+0x26200014,
+0x7e1e400c,
+0x7e4e800c,
+0xce81a2a4,
+0x80000001,
+0xcd81a1fe,
+0xc814000f,
+0x0410210e,
+0x95400000,
+0xc814000f,
+0xd0510000,
+0x80000001,
+0xccc1a2a4,
+0xc8140010,
+0x04102108,
+0x95400000,
+0xc8140010,
+0xd0510000,
+0x80000001,
+0xccc1a2a4,
+0xccc1a2a4,
+0x04100001,
+0xcd000019,
+0x8400037f,
+0xcc00007f,
+0xc8100019,
+0x99000000,
+0xc8100019,
+0x80000002,
+0x7c408000,
+0x04102100,
+0x95400000,
+0xc8140011,
+0xd0510000,
+0x8000037c,
+0xccc1a2a4,
+0x7c40c000,
+0xcc40000d,
+0x94c0fe01,
+0xcc40000e,
+0x7c410000,
+0x95000005,
+0x08cc0001,
+0xc8140005,
+0x99400014,
+0x00000000,
+0x98c0fffb,
+0x7c410000,
+0x80000002,
+0x7d008000,
+0xc8140005,
+0x7c40c000,
+0x9940000c,
+0xc818000c,
+0x7c410000,
+0x9580fdf0,
+0xc820000e,
+0xc81c000d,
+0x66200020,
+0x7e1e002c,
+0x25240002,
+0x7e624020,
+0x80000001,
+0xcce60000,
+0x7c410000,
+0xcc00006c,
+0xcc00006d,
+0xc818001f,
+0xc81c001e,
+0x65980020,
+0x7dd9c02c,
+0x7cd4c00c,
+0xccde0000,
+0x45dc0004,
+0xc8280017,
+0x9680000f,
+0xc00e0001,
+0x28680008,
+0x2aac0016,
+0x32a800ff,
+0x0eb00049,
+0x7f2f000b,
+0x97000006,
+0x00000000,
+0xc8140005,
+0x7c40c000,
+0x80000221,
+0x7c410000,
+0x80000224,
+0xd040007f,
+0x84000239,
+0xcc000041,
+0xccc1304a,
+0x94000000,
+0xc83c001a,
+0x043c0005,
+0xcfc1a2a4,
+0xc0361f90,
+0xc0387fff,
+0x7c03c010,
+0x7f7b400c,
+0xcf41217c,
+0xcfc1217d,
+0xcc01217e,
+0xc03a0004,
+0x0434217f,
+0x7f7b400c,
+0xcc350000,
+0xc83c0004,
+0x2bfc001f,
+0x04380020,
+0x97c00005,
+0xcc000062,
+0x9b800000,
+0x0bb80001,
+0x80000245,
+0xcc000071,
+0xcc01a1f4,
+0x04380016,
+0xc0360002,
+0xcf81a2a4,
+0x88000000,
+0xcf412010,
+0x7c40c000,
+0x28d0001c,
+0x95000005,
+0x04d40001,
+0xcd400065,
+0x80000001,
+0xcd400068,
+0x09540002,
+0x80000001,
+0xcd400066,
+0x8400026a,
+0xc81803ea,
+0x7c40c000,
+0x9980fd9f,
+0xc8140016,
+0x08d00001,
+0x9940002b,
+0xcd000068,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x043c0005,
+0xcfc1a2a4,
+0xcc01a1f4,
+0x8400037f,
+0xcc000046,
+0x88000000,
+0xcc00007f,
+0x8400027c,
+0xc81803ea,
+0x7c40c000,
+0x9980fd8d,
+0xc8140016,
+0x08d00001,
+0x99400019,
+0xcd000068,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x043c0022,
+0xcfc1a2a4,
+0x8400037f,
+0xcc000047,
+0x88000000,
+0xcc00007f,
+0xc8100016,
+0x9900000d,
+0xcc400067,
+0x80000002,
+0x7c408000,
+0xc81803ea,
+0x9980fd79,
+0x7c40c000,
+0x94c00003,
+0xc8100016,
+0x99000004,
+0xccc00068,
+0x80000002,
+0x7c408000,
+0x84000239,
+0xc0148000,
+0xcc000041,
+0xcd41304a,
+0xc0148000,
+0x99000000,
+0xc8100016,
+0x80000002,
+0x7c408000,
+0xc0120001,
+0x7c51400c,
+0x80000001,
+0xd0550000,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0x291c001f,
+0xccc0004a,
+0xcd00004b,
+0x95c00003,
+0xc01c8000,
+0xcdc12010,
+0xdd830000,
+0x055c2000,
+0xcc000062,
+0x80000001,
+0xd81f4100,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0xccc0004c,
+0xcd00004d,
+0xdd830000,
+0x055ca000,
+0x80000001,
+0xd81f4100,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0xccc0004e,
+0xcd00004f,
+0xdd830000,
+0x055cc000,
+0x80000001,
+0xd81f4100,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0xccc00050,
+0xcd000051,
+0xdd830000,
+0x055cf8e0,
+0x80000001,
+0xd81f4100,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0xccc00052,
+0xcd000053,
+0xdd830000,
+0x055cf880,
+0x80000001,
+0xd81f4100,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0xccc00054,
+0xcd000055,
+0xdd830000,
+0x055ce000,
+0x80000001,
+0xd81f4100,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0xccc00056,
+0xcd000057,
+0xdd830000,
+0x055cf000,
+0x80000001,
+0xd81f4100,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0xccc00058,
+0xcd000059,
+0xdd830000,
+0x055cf3fc,
+0x80000001,
+0xd81f4100,
+0xd0432000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xd043a000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xd043c000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xd043f8e0,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xd043f880,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xd043e000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xd043f000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xd043f3fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xc81403e0,
+0xcc430000,
+0xcc430000,
+0xcc430000,
+0x7d45c000,
+0xcdc30000,
+0xd0430000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x7c40c000,
+0xc81003e2,
+0xc81403e5,
+0xc81803e3,
+0xc81c03e4,
+0xcd812169,
+0xcdc1216a,
+0xccc1216b,
+0xcc01216c,
+0x04200004,
+0x7da18000,
+0x7d964002,
+0x9640fcd9,
+0xcd8003e3,
+0x31280003,
+0xc02df000,
+0x25180008,
+0x7dad800b,
+0x7da9800c,
+0x80000001,
+0xcd8003e3,
+0x308cffff,
+0xd04d0000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xc8140020,
+0x15580002,
+0x9580ffff,
+0xc8140020,
+0xcc00006e,
+0xcc412180,
+0x7c40c000,
+0xccc1218d,
+0xcc412181,
+0x28d0001f,
+0x34588000,
+0xcd81218c,
+0x9500fcbf,
+0xcc412182,
+0xc8140020,
+0x9940ffff,
+0xc8140020,
+0x80000002,
+0x7c408000,
+0x7c40c000,
+0x28d00018,
+0x31100001,
+0xc0160080,
+0x95000003,
+0xc02a0004,
+0x7cd4c00c,
+0xccc1217c,
+0xcc41217d,
+0xcc41217e,
+0x7c418000,
+0x1db00003,
+0x36a0217f,
+0x9b000003,
+0x419c0005,
+0x041c0040,
+0x99c00000,
+0x09dc0001,
+0xcc210000,
+0xc8240004,
+0x2a6c001f,
+0x419c0005,
+0x9ac0fffa,
+0xcc800062,
+0x80000002,
+0x7c408000,
+0x7c40c000,
+0x04d403e6,
+0x80000001,
+0xcc540000,
+0x8000037c,
+0xcc4003ea,
+0xc01c8000,
+0x044ca000,
+0xcdc12010,
+0x7c410000,
+0xc8140009,
+0x04180000,
+0x041c0008,
+0xcd800071,
+0x09dc0001,
+0x05980001,
+0xcd0d0000,
+0x99c0fffc,
+0xcc800062,
+0x8000037c,
+0xcd400071,
+0xc00e0100,
+0xcc000041,
+0xccc1304a,
+0xc83c007f,
+0xcc00007f,
+0x80000001,
+0xcc00007f,
+0xcc00007f,
+0x88000000,
+0xcc00007f,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
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+0x00000000,
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+0x00000000,
+0x00000000,
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+0x00000000,
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+0x00000000,
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+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
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+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00010331,
+0x00100004,
+0x00170006,
+0x00210008,
+0x00270028,
+0x00280023,
+0x00290029,
+0x002a0026,
+0x002b0029,
+0x002d0038,
+0x002e003f,
+0x002f004a,
+0x0034004c,
+0x00360030,
+0x003900af,
+0x003a00cf,
+0x003b00e4,
+0x003c00fc,
+0x003d016b,
+0x003f00ad,
+0x00410336,
+0x00430349,
+0x0044018e,
+0x004500fc,
+0x004601ac,
+0x004701ac,
+0x004801fe,
+0x0049020c,
+0x004a0255,
+0x004b0282,
+0x0052025f,
+0x00530271,
+0x00540287,
+0x00570299,
+0x0060029d,
+0x006102ac,
+0x006202b6,
+0x006302c0,
+0x006402ca,
+0x006502d4,
+0x006602de,
+0x006702e8,
+0x006802f2,
+0x006902f6,
+0x006a02fa,
+0x006b02fe,
+0x006c0302,
+0x006d0306,
+0x006e030a,
+0x006f030e,
+0x00700312,
+0x00720363,
+0x00740369,
+0x00790367,
+0x007c031c,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+0x000f0378,
+};
+
+static const u32 RV710_pfp_microcode[]={
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0x80000000,
+0xdc030000,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xc818000e,
+0x31980001,
+0x7c424000,
+0x9580023a,
+0x7c428000,
+0xc81c001c,
+0xc037c000,
+0x7c40c000,
+0x7c410000,
+0x7cb4800b,
+0xc0360003,
+0x99c00000,
+0xc81c001c,
+0x7cb4800c,
+0x24d40002,
+0x7d654000,
+0xcd400043,
+0xce800043,
+0xcd000043,
+0xcc800040,
+0xce400040,
+0xce800040,
+0xccc00040,
+0xdc3a0000,
+0x9780ffde,
+0xcd000040,
+0x7c40c000,
+0x80000018,
+0x7c410000,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xc818000e,
+0x8000000c,
+0x31980002,
+0xd40003c0,
+0xd4000fc0,
+0xd4000fa2,
+0xc818000e,
+0x288c0008,
+0x30cc000f,
+0x34100001,
+0x7d0d0008,
+0x8000000c,
+0x7d91800b,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xd40003c0,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xcc4003f9,
+0x80000249,
+0xcc4003f8,
+0xc037ffff,
+0x7c414000,
+0xcf41a29e,
+0xc82003f8,
+0xc81c03f9,
+0x66200020,
+0xc81803fb,
+0x7de1c02c,
+0x7d58c008,
+0x7cdcc020,
+0x69100020,
+0xc0360003,
+0xcc000054,
+0x7cb4800c,
+0x80000069,
+0xcc800040,
+0x7c418000,
+0xcd81a29e,
+0xcc800040,
+0x80000067,
+0xcd800040,
+0xc019ffff,
+0xcc800040,
+0xcd81a29e,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0xccc1a1fa,
+0xcd01a1f9,
+0xcd41a29d,
+0xccc00040,
+0xcd000040,
+0xcd400040,
+0xcc400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xcc000054,
+0xcc800040,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0xccc1a1fa,
+0xcd01a1f9,
+0xcd41a29d,
+0xccc00040,
+0xcd000040,
+0xcd400040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0x7c40c000,
+0x30d00001,
+0xccc1a29f,
+0x95000003,
+0x04140001,
+0x04140002,
+0xcd4003fb,
+0xcc800040,
+0x80000000,
+0xccc00040,
+0x7c40c000,
+0xcc800040,
+0xccc1a2a2,
+0x80000000,
+0xccc00040,
+0x7c40c000,
+0x28d4001f,
+0xcc800040,
+0x95400003,
+0x7c410000,
+0xccc00057,
+0x2918001f,
+0xccc00040,
+0x95800003,
+0xcd000040,
+0xcd000058,
+0x80000249,
+0xcc00007f,
+0xc8200017,
+0xc8300022,
+0x9a000006,
+0x0e280001,
+0xc824001e,
+0x0a640001,
+0xd4001240,
+0xce400040,
+0xc036c000,
+0x96800007,
+0x37747900,
+0x041c0001,
+0xcf400040,
+0xcdc00040,
+0xcf0003fa,
+0x7c030000,
+0xca0c0010,
+0x7c410000,
+0x94c00004,
+0x7c414000,
+0xd42002c4,
+0xcde00044,
+0x9b00000b,
+0x7c418000,
+0xcc00004b,
+0xcda00049,
+0xcd200041,
+0xcd600041,
+0xcda00041,
+0x06200001,
+0xce000056,
+0x80000249,
+0xcc00007f,
+0xc8280020,
+0xc82c0021,
+0xcc000063,
+0x7eea4001,
+0x65740020,
+0x7f53402c,
+0x269c0002,
+0x7df5c020,
+0x69f80020,
+0xce80004b,
+0xce600049,
+0xcde00041,
+0xcfa00041,
+0xce600041,
+0x271c0002,
+0x7df5c020,
+0x69f80020,
+0x7db24001,
+0xcf00004b,
+0xce600049,
+0xcde00041,
+0xcfa00041,
+0x800000bc,
+0xce600041,
+0xc8200017,
+0xc8300022,
+0x9a000006,
+0x0e280001,
+0xc824001e,
+0x0a640001,
+0xd4001240,
+0xce400040,
+0xca0c0010,
+0x7c410000,
+0x94c0000b,
+0xc036c000,
+0x96800007,
+0x37747900,
+0x041c0001,
+0xcf400040,
+0xcdc00040,
+0xcf0003fa,
+0x7c030000,
+0x800000b5,
+0x7c414000,
+0xcc000048,
+0x800000ee,
+0x00000000,
+0xc8200017,
+0xc81c0023,
+0x0e240002,
+0x99c00015,
+0x7c418000,
+0x0a200001,
+0xce000056,
+0xd4000440,
+0xcc000040,
+0xc036c000,
+0xca140013,
+0x96400007,
+0x37747900,
+0xcf400040,
+0xcc000040,
+0xc83003fa,
+0x80000103,
+0xcf000022,
+0xcc000022,
+0x95400146,
+0xcc00007f,
+0xcca00046,
+0x80000000,
+0xcc200046,
+0x80000249,
+0xcc000064,
+0xc8200017,
+0xc810001f,
+0x96000005,
+0x09100001,
+0xd4000440,
+0xcd000040,
+0xcd000022,
+0xcc800040,
+0xd0400040,
+0xc80c0025,
+0x94c0feec,
+0xc8100008,
+0xcd000040,
+0xd4000fc0,
+0x80000000,
+0xd4000fa2,
+0x7c40c000,
+0x7c410000,
+0xccc003fd,
+0xcd0003fc,
+0xccc00042,
+0xcd000042,
+0x2914001f,
+0x29180010,
+0x31980007,
+0x3b5c0001,
+0x7d76000b,
+0x99800005,
+0x7d5e400b,
+0xcc000042,
+0x80000249,
+0xcc00004d,
+0x29980001,
+0x292c0008,
+0x9980003d,
+0x32ec0001,
+0x96000004,
+0x2930000c,
+0x80000249,
+0xcc000042,
+0x04140010,
+0xcd400042,
+0x33300001,
+0x34280001,
+0x8400015d,
+0xc8140003,
+0x9b40001b,
+0x0438000c,
+0x8400015d,
+0xc8140003,
+0x9b400017,
+0x04380008,
+0x8400015d,
+0xc8140003,
+0x9b400013,
+0x04380004,
+0x8400015d,
+0xc8140003,
+0x9b400015,
+0xc80c03fd,
+0x9a800009,
+0xc81003fc,
+0x9b000101,
+0xcc00004d,
+0x04140010,
+0xccc00042,
+0xcd000042,
+0x80000135,
+0xcd400042,
+0x96c000fa,
+0xcc00004d,
+0x80000249,
+0xcc00004e,
+0x9ac00003,
+0xcc00004d,
+0xcc00004e,
+0xdf830000,
+0x80000000,
+0xd80301ff,
+0x9ac000f0,
+0xcc00004d,
+0x80000249,
+0xcc00004e,
+0xc8180003,
+0xc81c0003,
+0xc8200003,
+0x7d5d4003,
+0x7da1c003,
+0x7d5d400c,
+0x2a10001f,
+0x299c001f,
+0x7d1d000b,
+0x7d17400b,
+0x88000000,
+0x7e92800b,
+0x96400004,
+0xcc00004e,
+0x80000249,
+0xcc000042,
+0x04380008,
+0xcf800042,
+0xc8080003,
+0xc80c0003,
+0xc8100003,
+0xc8140003,
+0xc8180003,
+0xc81c0003,
+0xc8240003,
+0xc8280003,
+0x29fc001f,
+0x2ab0001f,
+0x7ff3c00b,
+0x28f0001f,
+0x7ff3c00b,
+0x2970001f,
+0x7ff3c00b,
+0x7d888001,
+0x7dccc001,
+0x7e510001,
+0x7e954001,
+0x7c908002,
+0x7cd4c002,
+0x7cbc800b,
+0x9ac00003,
+0x7c8f400b,
+0x38b40001,
+0x9b4000c1,
+0xcc00004d,
+0x9bc000bf,
+0xcc00004e,
+0xc80c03fd,
+0xc81003fc,
+0xccc00042,
+0x8000016e,
+0xcd000042,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xcc400040,
+0xcc400040,
+0xcc400040,
+0x7c40c000,
+0xccc00040,
+0xccc0000d,
+0x80000000,
+0xd0400040,
+0x7c40c000,
+0x7c410000,
+0x65140020,
+0x7d4d402c,
+0x24580002,
+0x7d598020,
+0x7c41c000,
+0xcd800042,
+0x69980020,
+0xcd800042,
+0xcdc00042,
+0xc023c000,
+0x05e40002,
+0x7ca0800b,
+0x26640010,
+0x7ca4800c,
+0xcc800040,
+0xcdc00040,
+0xccc00040,
+0x95c0000e,
+0xcd000040,
+0x09dc0001,
+0xc8280003,
+0x96800008,
+0xce800040,
+0xc834001d,
+0x97400000,
+0xc834001d,
+0x26a80008,
+0x8400024c,
+0xcc2b0000,
+0x99c0fff7,
+0x09dc0001,
+0xdc3a0000,
+0x97800004,
+0x7c418000,
+0x800001a2,
+0x25980002,
+0xa0000000,
+0x7d808000,
+0xc818001d,
+0x7c40c000,
+0x64d00008,
+0x95800000,
+0xc818001d,
+0xcc130000,
+0xcc800040,
+0xccc00040,
+0x80000000,
+0xcc400040,
+0xc810001f,
+0x7c40c000,
+0xcc800040,
+0x7cd1400c,
+0xcd400040,
+0x05180001,
+0x80000000,
+0xcd800022,
+0x7c40c000,
+0x64500020,
+0x8400024c,
+0xcc000061,
+0x7cd0c02c,
+0xc8200017,
+0xc8d60000,
+0x99400008,
+0x7c438000,
+0xdf830000,
+0xcfa0004f,
+0x8400024c,
+0xcc000062,
+0x80000000,
+0xd040007f,
+0x80000249,
+0xcc000062,
+0x8400024c,
+0xcc000061,
+0xc8200017,
+0x7c40c000,
+0xc036ff00,
+0xc810000d,
+0xc0303fff,
+0x7cf5400b,
+0x7d51800b,
+0x7d81800f,
+0x99800008,
+0x7cf3800b,
+0xdf830000,
+0xcfa0004f,
+0x8400024c,
+0xcc000062,
+0x80000000,
+0xd040007f,
+0x80000249,
+0xcc000062,
+0x8400024c,
+0x7c40c000,
+0x28dc0008,
+0x95c00019,
+0x30dc0010,
+0x7c410000,
+0x99c00004,
+0x64540020,
+0x80000208,
+0xc91d0000,
+0x7d15002c,
+0xc91e0000,
+0x7c420000,
+0x7c424000,
+0x7c418000,
+0x7de5c00b,
+0x7de28007,
+0x9a80000e,
+0x41ac0005,
+0x9ac00000,
+0x0aec0001,
+0x30dc0010,
+0x99c00004,
+0x00000000,
+0x8000020b,
+0xc91d0000,
+0x8000020b,
+0xc91e0000,
+0xcc800040,
+0xccc00040,
+0xd0400040,
+0xc80c0025,
+0x94c0fde4,
+0xc8100008,
+0xcd000040,
+0xd4000fc0,
+0x80000000,
+0xd4000fa2,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0xd40003c0,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xd0400040,
+0x7c408000,
+0xa0000000,
+0x7e82800b,
+0x7c40c000,
+0x30d00006,
+0x0d100006,
+0x99000007,
+0xc8140015,
+0x99400005,
+0xcc000052,
+0xd4000340,
+0xd4000fc0,
+0xd4000fa2,
+0xcc800040,
+0xccc00040,
+0x80000000,
+0xd0400040,
+0x7c40c000,
+0xcc4d0000,
+0xdc3a0000,
+0x9780fdbd,
+0x04cc0001,
+0x80000242,
+0xcc4d0000,
+0x80000000,
+0xd040007f,
+0xcc00007f,
+0x80000000,
+0xcc00007f,
+0xcc00007f,
+0x88000000,
+0xcc00007f,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00030222,
+0x0004022a,
+0x0005009f,
+0x00020003,
+0x0006003c,
+0x00070027,
+0x00080191,
+0x00090044,
+0x000a002d,
+0x00100247,
+0x001700f0,
+0x002201d7,
+0x002301e8,
+0x0026004c,
+0x0027005f,
+0x0020011a,
+0x00280092,
+0x0029004f,
+0x002a0083,
+0x002b0064,
+0x002f008d,
+0x003200d8,
+0x00340232,
+0x00360074,
+0x0039010a,
+0x003c01fc,
+0x003f009f,
+0x00410005,
+0x00440194,
+0x0048019d,
+0x004901c5,
+0x004a01cf,
+0x00550225,
+0x0056022d,
+0x0060000a,
+0x0061002a,
+0x00620030,
+0x00630030,
+0x00640030,
+0x00650030,
+0x00660030,
+0x00670030,
+0x00680037,
+0x0069003f,
+0x006a0047,
+0x006b0047,
+0x006c0047,
+0x006d0047,
+0x006e0047,
+0x006f0047,
+0x00700047,
+0x00730247,
+0x007b0240,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+0x00000005,
+};
+
+static const u32 RV710_cp_microcode[]={
+0xcc0003ea,
+0x04080003,
+0xcc800043,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x80000003,
+0xd040007f,
+0x80000003,
+0xcc400041,
+0x7c40c000,
+0xc0160004,
+0x30d03fff,
+0x7d15000c,
+0xcc110000,
+0x28d8001e,
+0x31980001,
+0x28dc001f,
+0xc8200004,
+0x95c00006,
+0x7c424000,
+0xcc000062,
+0x7e56800c,
+0xcc290000,
+0xc8240004,
+0x7e26000b,
+0x95800006,
+0x7c42c000,
+0xcc000062,
+0x7ed7000c,
+0xcc310000,
+0xc82c0004,
+0x7e2e000c,
+0xcc000062,
+0x31103fff,
+0x80000003,
+0xce110000,
+0x7c40c000,
+0x80000003,
+0xcc400040,
+0x80000003,
+0xcc412257,
+0x7c418000,
+0xcc400045,
+0xcc400048,
+0xcc41225c,
+0xcc41a1fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xcc400045,
+0xcc400048,
+0x7c40c000,
+0xcc41225c,
+0xcc41a1fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0xcc000045,
+0xcc000048,
+0xcc41225c,
+0xcc41a1fc,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x040ca1fd,
+0xc0120001,
+0xcc000045,
+0xcc000048,
+0x7cd0c00c,
+0xcc41225c,
+0xcc41a1fc,
+0xd04d0000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x80000003,
+0xcc41225d,
+0x7c408000,
+0x7c40c000,
+0xc02a0002,
+0x7c410000,
+0x7d29000c,
+0x30940001,
+0x30980006,
+0x309c0300,
+0x29dc0008,
+0x7c420000,
+0x7c424000,
+0x9540000f,
+0xc02e0004,
+0x05f02258,
+0x7f2f000c,
+0xcc310000,
+0xc8280004,
+0xccc12169,
+0xcd01216a,
+0xce81216b,
+0x0db40002,
+0xcc01216c,
+0x9740000e,
+0x0db40000,
+0x8000007d,
+0xc834000a,
+0x0db40002,
+0x97400009,
+0x0db40000,
+0xc02e0004,
+0x05f02258,
+0x7f2f000c,
+0xcc310000,
+0xc8280004,
+0x8000007d,
+0xc834000a,
+0x97400004,
+0x7e028000,
+0x8000007d,
+0xc834000a,
+0x0db40004,
+0x9740ff8c,
+0x00000000,
+0xce01216d,
+0xce41216e,
+0xc8280003,
+0xc834000a,
+0x9b400004,
+0x043c0005,
+0x8400026d,
+0xcc000062,
+0x0df40000,
+0x9740000b,
+0xc82c03e6,
+0xce81a2b7,
+0xc0300006,
+0x7ef34028,
+0xc0300020,
+0x7f6b8020,
+0x7fb3c029,
+0xcf81a2c4,
+0x80000003,
+0xcfc1a2d1,
+0x0df40001,
+0x9740000b,
+0xc82c03e7,
+0xce81a2bb,
+0xc0300006,
+0x7ef34028,
+0xc0300020,
+0x7f6b8020,
+0x7fb3c029,
+0xcf81a2c5,
+0x80000003,
+0xcfc1a2d2,
+0x0df40002,
+0x9740000b,
+0xc82c03e8,
+0xce81a2bf,
+0xc0300006,
+0x7ef34028,
+0xc0300020,
+0x7f6b8020,
+0x7fb3c029,
+0xcf81a2c6,
+0x80000003,
+0xcfc1a2d3,
+0xc82c03e9,
+0xce81a2c3,
+0xc0300006,
+0x7ef34028,
+0xc0300020,
+0x7f6b8020,
+0x7fb3c029,
+0xcf81a2c7,
+0x80000003,
+0xcfc1a2d4,
+0x80000003,
+0xcc400042,
+0x7c40c000,
+0x7c410000,
+0x2914001d,
+0x31540001,
+0x9940000c,
+0x31181000,
+0xc81c0011,
+0x95c00000,
+0xc81c0011,
+0xccc12100,
+0xcd012101,
+0xccc12102,
+0xcd012103,
+0x04180004,
+0x8000037e,
+0xcd81a2a4,
+0xc02a0004,
+0x95800008,
+0x36a821a3,
+0xcc290000,
+0xc8280004,
+0xc81c0011,
+0x0de40040,
+0x9640ffff,
+0xc81c0011,
+0xccc12170,
+0xcd012171,
+0xc8200012,
+0x96000000,
+0xc8200012,
+0x8000037e,
+0xcc000064,
+0x7c40c000,
+0x7c410000,
+0xcc000045,
+0xcc000048,
+0x40d40003,
+0xcd41225c,
+0xcd01a1fc,
+0xc01a0001,
+0x041ca1fd,
+0x7dd9c00c,
+0x7c420000,
+0x08cc0001,
+0x06240001,
+0x06280002,
+0xce1d0000,
+0xce5d0000,
+0x98c0fffa,
+0xce9d0000,
+0x7c408000,
+0xa0000000,
+0xcc800062,
+0x7c40c000,
+0x30d00001,
+0x28cc0001,
+0x7c414000,
+0x95000006,
+0x7c418000,
+0xcd41216d,
+0xcd81216e,
+0x800000f4,
+0xc81c0003,
+0xc0220004,
+0x7e16000c,
+0xcc210000,
+0xc81c0004,
+0x7c424000,
+0x98c00004,
+0x7c428000,
+0x80000003,
+0xcde50000,
+0xce412169,
+0xce81216a,
+0xcdc1216b,
+0x80000003,
+0xcc01216c,
+0x7c40c000,
+0x7c410000,
+0x7c414000,
+0x7c418000,
+0x7c41c000,
+0x28a40008,
+0x326400ff,
+0x0e68003c,
+0x9680000a,
+0x7c020000,
+0x7c420000,
+0x1e300003,
+0xcc00006a,
+0x9b000003,
+0x42200005,
+0x04200040,
+0x80000111,
+0x7c024000,
+0x7e024000,
+0x9a400000,
+0x0a640001,
+0x30ec0010,
+0x9ac0000a,
+0xcc000062,
+0xc02a0004,
+0xc82c0021,
+0x7e92800c,
+0xcc000041,
+0xcc290000,
+0xcec00021,
+0x80000121,
+0xc8300004,
+0xcd01216d,
+0xcd41216e,
+0xc8300003,
+0x7f1f000b,
+0x30f40007,
+0x27780001,
+0x9740002a,
+0x07b80126,
+0x9f800000,
+0x00000000,
+0x80000136,
+0x7f1b8004,
+0x8000013a,
+0x7f1b8005,
+0x8000013e,
+0x7f1b8002,
+0x80000142,
+0x7f1b8003,
+0x80000146,
+0x7f1b8007,
+0x8000014a,
+0x7f1b8006,
+0x8000014f,
+0x28a40008,
+0x9b800019,
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+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00000000,
+0x00010333,
+0x00100006,
+0x00170008,
+0x0021000a,
+0x0027002a,
+0x00280025,
+0x0029002b,
+0x002a0028,
+0x002b002b,
+0x002d003a,
+0x002e0041,
+0x002f004c,
+0x0034004e,
+0x00360032,
+0x003900b1,
+0x003a00d1,
+0x003b00e6,
+0x003c00fe,
+0x003d016d,
+0x003f00af,
+0x00410338,
+0x0043034b,
+0x00440190,
+0x004500fe,
+0x004601ae,
+0x004701ae,
+0x00480200,
+0x0049020e,
+0x004a0257,
+0x004b0284,
+0x00520261,
+0x00530273,
+0x00540289,
+0x0057029b,
+0x0060029f,
+0x006102ae,
+0x006202b8,
+0x006302c2,
+0x006402cc,
+0x006502d6,
+0x006602e0,
+0x006702ea,
+0x006802f4,
+0x006902f8,
+0x006a02fc,
+0x006b0300,
+0x006c0304,
+0x006d0308,
+0x006e030c,
+0x006f0310,
+0x00700314,
+0x00720365,
+0x0074036b,
+0x00790369,
+0x007c031e,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+0x000f037a,
+};
diff --git a/sys/dev/drm/radeon/Makefile b/sys/dev/drm/radeon/Makefile
index 894686cabd..06aa137678 100644
--- a/sys/dev/drm/radeon/Makefile
+++ b/sys/dev/drm/radeon/Makefile
@@ -4,8 +4,8 @@
 KMOD	= radeon
 KMODDEPS= drm
 NO_MAN	= YES
-SRCS    = r300_cmdbuf.c radeon_cp.c radeon_drv.c radeon_state.c radeon_irq.c \
-	radeon_mem.c
+SRCS    = r300_cmdbuf.c r600_cp.c radeon_cp.c radeon_drv.c radeon_state.c \
+	  radeon_irq.c radeon_mem.c
 SRCS   += device_if.h bus_if.h pci_if.h opt_drm.h
 CFLAGS += ${DEBUG_FLAGS} -I. -I..
 
diff --git a/sys/dev/drm/radeon_cp.c b/sys/dev/drm/radeon_cp.c
index fceb73ccb8..b70eda914e 100644
--- a/sys/dev/drm/radeon_cp.c
+++ b/sys/dev/drm/radeon_cp.c
@@ -1,7 +1,7 @@
-/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
-/*
+/*-
  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
+ * Copyright 2007 Advanced Micro Devices, Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -26,799 +26,95 @@
  * Authors:
  *    Kevin E. Martin <martin@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/radeon_cp.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
-#include "r300_reg.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/drm_sarea.h"
+#include "dev/drm/radeon_drm.h"
+#include "dev/drm/radeon_drv.h"
+#include "dev/drm/r300_reg.h"
+
+#include "dev/drm/radeon_microcode.h"
 
 #define RADEON_FIFO_DEBUG	0
 
 static int radeon_do_cleanup_cp(struct drm_device * dev);
+static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
+
+u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
+{
+	u32 val;
+
+	if (dev_priv->flags & RADEON_IS_AGP) {
+		val = DRM_READ32(dev_priv->ring_rptr, off);
+	} else {
+		val = *(((volatile u32 *)
+			 dev_priv->ring_rptr->handle) +
+			(off / sizeof(u32)));
+		val = le32_to_cpu(val);
+	}
+	return val;
+}
+
+u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
+{
+	if (dev_priv->writeback_works)
+		return radeon_read_ring_rptr(dev_priv, 0);
+	else {
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+			return RADEON_READ(R600_CP_RB_RPTR);
+		else
+			return RADEON_READ(RADEON_CP_RB_RPTR);
+	}
+}
+
+void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
+{
+	if (dev_priv->flags & RADEON_IS_AGP)
+		DRM_WRITE32(dev_priv->ring_rptr, off, val);
+	else
+		*(((volatile u32 *) dev_priv->ring_rptr->handle) +
+		  (off / sizeof(u32))) = cpu_to_le32(val);
+}
+
+void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
+{
+	radeon_write_ring_rptr(dev_priv, 0, val);
+}
+
+u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
+{
+	if (dev_priv->writeback_works) {
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+			return radeon_read_ring_rptr(dev_priv,
+						     R600_SCRATCHOFF(index));
+		else
+			return radeon_read_ring_rptr(dev_priv,
+						     RADEON_SCRATCHOFF(index));
+	} else {
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+			return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
+		else
+			return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
+	}
+}
+
+u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
+{
+	u32 ret;
+
+	if (addr < 0x10000)
+		ret = DRM_READ32(dev_priv->mmio, addr);
+	else {
+		DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
+		ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
+	}
 
-/* CP microcode (from ATI) */
-static const u32 R200_cp_microcode[][2] = {
-	{0x21007000, 0000000000},
-	{0x20007000, 0000000000},
-	{0x000000ab, 0x00000004},
-	{0x000000af, 0x00000004},
-	{0x66544a49, 0000000000},
-	{0x49494174, 0000000000},
-	{0x54517d83, 0000000000},
-	{0x498d8b64, 0000000000},
-	{0x49494949, 0000000000},
-	{0x49da493c, 0000000000},
-	{0x49989898, 0000000000},
-	{0xd34949d5, 0000000000},
-	{0x9dc90e11, 0000000000},
-	{0xce9b9b9b, 0000000000},
-	{0x000f0000, 0x00000016},
-	{0x352e232c, 0000000000},
-	{0x00000013, 0x00000004},
-	{0x000f0000, 0x00000016},
-	{0x352e272c, 0000000000},
-	{0x000f0001, 0x00000016},
-	{0x3239362f, 0000000000},
-	{0x000077ef, 0x00000002},
-	{0x00061000, 0x00000002},
-	{0x00000020, 0x0000001a},
-	{0x00004000, 0x0000001e},
-	{0x00061000, 0x00000002},
-	{0x00000020, 0x0000001a},
-	{0x00004000, 0x0000001e},
-	{0x00061000, 0x00000002},
-	{0x00000020, 0x0000001a},
-	{0x00004000, 0x0000001e},
-	{0x00000016, 0x00000004},
-	{0x0003802a, 0x00000002},
-	{0x040067e0, 0x00000002},
-	{0x00000016, 0x00000004},
-	{0x000077e0, 0x00000002},
-	{0x00065000, 0x00000002},
-	{0x000037e1, 0x00000002},
-	{0x040067e1, 0x00000006},
-	{0x000077e0, 0x00000002},
-	{0x000077e1, 0x00000002},
-	{0x000077e1, 0x00000006},
-	{0xffffffff, 0000000000},
-	{0x10000000, 0000000000},
-	{0x0003802a, 0x00000002},
-	{0x040067e0, 0x00000006},
-	{0x00007675, 0x00000002},
-	{0x00007676, 0x00000002},
-	{0x00007677, 0x00000002},
-	{0x00007678, 0x00000006},
-	{0x0003802b, 0x00000002},
-	{0x04002676, 0x00000002},
-	{0x00007677, 0x00000002},
-	{0x00007678, 0x00000006},
-	{0x0000002e, 0x00000018},
-	{0x0000002e, 0x00000018},
-	{0000000000, 0x00000006},
-	{0x0000002f, 0x00000018},
-	{0x0000002f, 0x00000018},
-	{0000000000, 0x00000006},
-	{0x01605000, 0x00000002},
-	{0x00065000, 0x00000002},
-	{0x00098000, 0x00000002},
-	{0x00061000, 0x00000002},
-	{0x64c0603d, 0x00000004},
-	{0x00080000, 0x00000016},
-	{0000000000, 0000000000},
-	{0x0400251d, 0x00000002},
-	{0x00007580, 0x00000002},
-	{0x00067581, 0x00000002},
-	{0x04002580, 0x00000002},
-	{0x00067581, 0x00000002},
-	{0x00000046, 0x00000004},
-	{0x00005000, 0000000000},
-	{0x00061000, 0x00000002},
-	{0x0000750e, 0x00000002},
-	{0x00019000, 0x00000002},
-	{0x00011055, 0x00000014},
-	{0x00000055, 0x00000012},
-	{0x0400250f, 0x00000002},
-	{0x0000504a, 0x00000004},
-	{0x00007565, 0x00000002},
-	{0x00007566, 0x00000002},
-	{0x00000051, 0x00000004},
-	{0x01e655b4, 0x00000002},
-	{0x4401b0dc, 0x00000002},
-	{0x01c110dc, 0x00000002},
-	{0x2666705d, 0x00000018},
-	{0x040c2565, 0x00000002},
-	{0x0000005d, 0x00000018},
-	{0x04002564, 0x00000002},
-	{0x00007566, 0x00000002},
-	{0x00000054, 0x00000004},
-	{0x00401060, 0x00000008},
-	{0x00101000, 0x00000002},
-	{0x000d80ff, 0x00000002},
-	{0x00800063, 0x00000008},
-	{0x000f9000, 0x00000002},
-	{0x000e00ff, 0x00000002},
-	{0000000000, 0x00000006},
-	{0x00000080, 0x00000018},
-	{0x00000054, 0x00000004},
-	{0x00007576, 0x00000002},
-	{0x00065000, 0x00000002},
-	{0x00009000, 0x00000002},
-	{0x00041000, 0x00000002},
-	{0x0c00350e, 0x00000002},
-	{0x00049000, 0x00000002},
-	{0x00051000, 0x00000002},
-	{0x01e785f8, 0x00000002},
-	{0x00200000, 0x00000002},
-	{0x00600073, 0x0000000c},
-	{0x00007563, 0x00000002},
-	{0x006075f0, 0x00000021},
-	{0x20007068, 0x00000004},
-	{0x00005068, 0x00000004},
-	{0x00007576, 0x00000002},
-	{0x00007577, 0x00000002},
-	{0x0000750e, 0x00000002},
-	{0x0000750f, 0x00000002},
-	{0x00a05000, 0x00000002},
-	{0x00600076, 0x0000000c},
-	{0x006075f0, 0x00000021},
-	{0x000075f8, 0x00000002},
-	{0x00000076, 0x00000004},
-	{0x000a750e, 0x00000002},
-	{0x0020750f, 0x00000002},
-	{0x00600079, 0x00000004},
-	{0x00007570, 0x00000002},
-	{0x00007571, 0x00000002},
-	{0x00007572, 0x00000006},
-	{0x00005000, 0x00000002},
-	{0x00a05000, 0x00000002},
-	{0x00007568, 0x00000002},
-	{0x00061000, 0x00000002},
-	{0x00000084, 0x0000000c},
-	{0x00058000, 0x00000002},
-	{0x0c607562, 0x00000002},
-	{0x00000086, 0x00000004},
-	{0x00600085, 0x00000004},
-	{0x400070dd, 0000000000},
-	{0x000380dd, 0x00000002},
-	{0x00000093, 0x0000001c},
-	{0x00065095, 0x00000018},
-	{0x040025bb, 0x00000002},
-	{0x00061096, 0x00000018},
-	{0x040075bc, 0000000000},
-	{0x000075bb, 0x00000002},
-	{0x000075bc, 0000000000},
-	{0x00090000, 0x00000006},
-	{0x00090000, 0x00000002},
-	{0x000d8002, 0x00000006},
-	{0x00005000, 0x00000002},
-	{0x00007821, 0x00000002},
-	{0x00007800, 0000000000},
-	{0x00007821, 0x00000002},
-	{0x00007800, 0000000000},
-	{0x01665000, 0x00000002},
-	{0x000a0000, 0x00000002},
-	{0x000671cc, 0x00000002},
-	{0x0286f1cd, 0x00000002},
-	{0x000000a3, 0x00000010},
-	{0x21007000, 0000000000},
-	{0x000000aa, 0x0000001c},
-	{0x00065000, 0x00000002},
-	{0x000a0000, 0x00000002},
-	{0x00061000, 0x00000002},
-	{0x000b0000, 0x00000002},
-	{0x38067000, 0x00000002},
-	{0x000a00a6, 0x00000004},
-	{0x20007000, 0000000000},
-	{0x01200000, 0x00000002},
-	{0x20077000, 0x00000002},
-	{0x01200000, 0x00000002},
-	{0x20007000, 0000000000},
-	{0x00061000, 0x00000002},
-	{0x0120751b, 0x00000002},
-	{0x8040750a, 0x00000002},
-	{0x8040750b, 0x00000002},
-	{0x00110000, 0x00000002},
-	{0x000380dd, 0x00000002},
-	{0x000000bd, 0x0000001c},
-	{0x00061096, 0x00000018},
-	{0x844075bd, 0x00000002},
-	{0x00061095, 0x00000018},
-	{0x840075bb, 0x00000002},
-	{0x00061096, 0x00000018},
-	{0x844075bc, 0x00000002},
-	{0x000000c0, 0x00000004},
-	{0x804075bd, 0x00000002},
-	{0x800075bb, 0x00000002},
-	{0x804075bc, 0x00000002},
-	{0x00108000, 0x00000002},
-	{0x01400000, 0x00000002},
-	{0x006000c4, 0x0000000c},
-	{0x20c07000, 0x00000020},
-	{0x000000c6, 0x00000012},
-	{0x00800000, 0x00000006},
-	{0x0080751d, 0x00000006},
-	{0x000025bb, 0x00000002},
-	{0x000040c0, 0x00000004},
-	{0x0000775c, 0x00000002},
-	{0x00a05000, 0x00000002},
-	{0x00661000, 0x00000002},
-	{0x0460275d, 0x00000020},
-	{0x00004000, 0000000000},
-	{0x00007999, 0x00000002},
-	{0x00a05000, 0x00000002},
-	{0x00661000, 0x00000002},
-	{0x0460299b, 0x00000020},
-	{0x00004000, 0000000000},
-	{0x01e00830, 0x00000002},
-	{0x21007000, 0000000000},
-	{0x00005000, 0x00000002},
-	{0x00038042, 0x00000002},
-	{0x040025e0, 0x00000002},
-	{0x000075e1, 0000000000},
-	{0x00000001, 0000000000},
-	{0x000380d9, 0x00000002},
-	{0x04007394, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-};
-
-static const u32 radeon_cp_microcode[][2] = {
-	{0x21007000, 0000000000},
-	{0x20007000, 0000000000},
-	{0x000000b4, 0x00000004},
-	{0x000000b8, 0x00000004},
-	{0x6f5b4d4c, 0000000000},
-	{0x4c4c427f, 0000000000},
-	{0x5b568a92, 0000000000},
-	{0x4ca09c6d, 0000000000},
-	{0xad4c4c4c, 0000000000},
-	{0x4ce1af3d, 0000000000},
-	{0xd8afafaf, 0000000000},
-	{0xd64c4cdc, 0000000000},
-	{0x4cd10d10, 0000000000},
-	{0x000f0000, 0x00000016},
-	{0x362f242d, 0000000000},
-	{0x00000012, 0x00000004},
-	{0x000f0000, 0x00000016},
-	{0x362f282d, 0000000000},
-	{0x000380e7, 0x00000002},
-	{0x04002c97, 0x00000002},
-	{0x000f0001, 0x00000016},
-	{0x333a3730, 0000000000},
-	{0x000077ef, 0x00000002},
-	{0x00061000, 0x00000002},
-	{0x00000021, 0x0000001a},
-	{0x00004000, 0x0000001e},
-	{0x00061000, 0x00000002},
-	{0x00000021, 0x0000001a},
-	{0x00004000, 0x0000001e},
-	{0x00061000, 0x00000002},
-	{0x00000021, 0x0000001a},
-	{0x00004000, 0x0000001e},
-	{0x00000017, 0x00000004},
-	{0x0003802b, 0x00000002},
-	{0x040067e0, 0x00000002},
-	{0x00000017, 0x00000004},
-	{0x000077e0, 0x00000002},
-	{0x00065000, 0x00000002},
-	{0x000037e1, 0x00000002},
-	{0x040067e1, 0x00000006},
-	{0x000077e0, 0x00000002},
-	{0x000077e1, 0x00000002},
-	{0x000077e1, 0x00000006},
-	{0xffffffff, 0000000000},
-	{0x10000000, 0000000000},
-	{0x0003802b, 0x00000002},
-	{0x040067e0, 0x00000006},
-	{0x00007675, 0x00000002},
-	{0x00007676, 0x00000002},
-	{0x00007677, 0x00000002},
-	{0x00007678, 0x00000006},
-	{0x0003802c, 0x00000002},
-	{0x04002676, 0x00000002},
-	{0x00007677, 0x00000002},
-	{0x00007678, 0x00000006},
-	{0x0000002f, 0x00000018},
-	{0x0000002f, 0x00000018},
-	{0000000000, 0x00000006},
-	{0x00000030, 0x00000018},
-	{0x00000030, 0x00000018},
-	{0000000000, 0x00000006},
-	{0x01605000, 0x00000002},
-	{0x00065000, 0x00000002},
-	{0x00098000, 0x00000002},
-	{0x00061000, 0x00000002},
-	{0x64c0603e, 0x00000004},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x00080000, 0x00000016},
-	{0000000000, 0000000000},
-	{0x0400251d, 0x00000002},
-	{0x00007580, 0x00000002},
-	{0x00067581, 0x00000002},
-	{0x04002580, 0x00000002},
-	{0x00067581, 0x00000002},
-	{0x00000049, 0x00000004},
-	{0x00005000, 0000000000},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x00061000, 0x00000002},
-	{0x0000750e, 0x00000002},
-	{0x00019000, 0x00000002},
-	{0x00011055, 0x00000014},
-	{0x00000055, 0x00000012},
-	{0x0400250f, 0x00000002},
-	{0x0000504f, 0x00000004},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x00007565, 0x00000002},
-	{0x00007566, 0x00000002},
-	{0x00000058, 0x00000004},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x01e655b4, 0x00000002},
-	{0x4401b0e4, 0x00000002},
-	{0x01c110e4, 0x00000002},
-	{0x26667066, 0x00000018},
-	{0x040c2565, 0x00000002},
-	{0x00000066, 0x00000018},
-	{0x04002564, 0x00000002},
-	{0x00007566, 0x00000002},
-	{0x0000005d, 0x00000004},
-	{0x00401069, 0x00000008},
-	{0x00101000, 0x00000002},
-	{0x000d80ff, 0x00000002},
-	{0x0080006c, 0x00000008},
-	{0x000f9000, 0x00000002},
-	{0x000e00ff, 0x00000002},
-	{0000000000, 0x00000006},
-	{0x0000008f, 0x00000018},
-	{0x0000005b, 0x00000004},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x00007576, 0x00000002},
-	{0x00065000, 0x00000002},
-	{0x00009000, 0x00000002},
-	{0x00041000, 0x00000002},
-	{0x0c00350e, 0x00000002},
-	{0x00049000, 0x00000002},
-	{0x00051000, 0x00000002},
-	{0x01e785f8, 0x00000002},
-	{0x00200000, 0x00000002},
-	{0x0060007e, 0x0000000c},
-	{0x00007563, 0x00000002},
-	{0x006075f0, 0x00000021},
-	{0x20007073, 0x00000004},
-	{0x00005073, 0x00000004},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x00007576, 0x00000002},
-	{0x00007577, 0x00000002},
-	{0x0000750e, 0x00000002},
-	{0x0000750f, 0x00000002},
-	{0x00a05000, 0x00000002},
-	{0x00600083, 0x0000000c},
-	{0x006075f0, 0x00000021},
-	{0x000075f8, 0x00000002},
-	{0x00000083, 0x00000004},
-	{0x000a750e, 0x00000002},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x0020750f, 0x00000002},
-	{0x00600086, 0x00000004},
-	{0x00007570, 0x00000002},
-	{0x00007571, 0x00000002},
-	{0x00007572, 0x00000006},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x00005000, 0x00000002},
-	{0x00a05000, 0x00000002},
-	{0x00007568, 0x00000002},
-	{0x00061000, 0x00000002},
-	{0x00000095, 0x0000000c},
-	{0x00058000, 0x00000002},
-	{0x0c607562, 0x00000002},
-	{0x00000097, 0x00000004},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x00600096, 0x00000004},
-	{0x400070e5, 0000000000},
-	{0x000380e6, 0x00000002},
-	{0x040025c5, 0x00000002},
-	{0x000380e5, 0x00000002},
-	{0x000000a8, 0x0000001c},
-	{0x000650aa, 0x00000018},
-	{0x040025bb, 0x00000002},
-	{0x000610ab, 0x00000018},
-	{0x040075bc, 0000000000},
-	{0x000075bb, 0x00000002},
-	{0x000075bc, 0000000000},
-	{0x00090000, 0x00000006},
-	{0x00090000, 0x00000002},
-	{0x000d8002, 0x00000006},
-	{0x00007832, 0x00000002},
-	{0x00005000, 0x00000002},
-	{0x000380e7, 0x00000002},
-	{0x04002c97, 0x00000002},
-	{0x00007820, 0x00000002},
-	{0x00007821, 0x00000002},
-	{0x00007800, 0000000000},
-	{0x01200000, 0x00000002},
-	{0x20077000, 0x00000002},
-	{0x01200000, 0x00000002},
-	{0x20007000, 0x00000002},
-	{0x00061000, 0x00000002},
-	{0x0120751b, 0x00000002},
-	{0x8040750a, 0x00000002},
-	{0x8040750b, 0x00000002},
-	{0x00110000, 0x00000002},
-	{0x000380e5, 0x00000002},
-	{0x000000c6, 0x0000001c},
-	{0x000610ab, 0x00000018},
-	{0x844075bd, 0x00000002},
-	{0x000610aa, 0x00000018},
-	{0x840075bb, 0x00000002},
-	{0x000610ab, 0x00000018},
-	{0x844075bc, 0x00000002},
-	{0x000000c9, 0x00000004},
-	{0x804075bd, 0x00000002},
-	{0x800075bb, 0x00000002},
-	{0x804075bc, 0x00000002},
-	{0x00108000, 0x00000002},
-	{0x01400000, 0x00000002},
-	{0x006000cd, 0x0000000c},
-	{0x20c07000, 0x00000020},
-	{0x000000cf, 0x00000012},
-	{0x00800000, 0x00000006},
-	{0x0080751d, 0x00000006},
-	{0000000000, 0000000000},
-	{0x0000775c, 0x00000002},
-	{0x00a05000, 0x00000002},
-	{0x00661000, 0x00000002},
-	{0x0460275d, 0x00000020},
-	{0x00004000, 0000000000},
-	{0x01e00830, 0x00000002},
-	{0x21007000, 0000000000},
-	{0x6464614d, 0000000000},
-	{0x69687420, 0000000000},
-	{0x00000073, 0000000000},
-	{0000000000, 0000000000},
-	{0x00005000, 0x00000002},
-	{0x000380d0, 0x00000002},
-	{0x040025e0, 0x00000002},
-	{0x000075e1, 0000000000},
-	{0x00000001, 0000000000},
-	{0x000380e0, 0x00000002},
-	{0x04002394, 0x00000002},
-	{0x00005000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0x00000008, 0000000000},
-	{0x00000004, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-	{0000000000, 0000000000},
-};
-
-static const u32 R300_cp_microcode[][2] = {
-	{ 0x4200e000, 0000000000 },
-	{ 0x4000e000, 0000000000 },
-	{ 0x000000af, 0x00000008 },
-	{ 0x000000b3, 0x00000008 },
-	{ 0x6c5a504f, 0000000000 },
-	{ 0x4f4f497a, 0000000000 },
-	{ 0x5a578288, 0000000000 },
-	{ 0x4f91906a, 0000000000 },
-	{ 0x4f4f4f4f, 0000000000 },
-	{ 0x4fe24f44, 0000000000 },
-	{ 0x4f9c9c9c, 0000000000 },
-	{ 0xdc4f4fde, 0000000000 },
-	{ 0xa1cd4f4f, 0000000000 },
-	{ 0xd29d9d9d, 0000000000 },
-	{ 0x4f0f9fd7, 0000000000 },
-	{ 0x000ca000, 0x00000004 },
-	{ 0x000d0012, 0x00000038 },
-	{ 0x0000e8b4, 0x00000004 },
-	{ 0x000d0014, 0x00000038 },
-	{ 0x0000e8b6, 0x00000004 },
-	{ 0x000d0016, 0x00000038 },
-	{ 0x0000e854, 0x00000004 },
-	{ 0x000d0018, 0x00000038 },
-	{ 0x0000e855, 0x00000004 },
-	{ 0x000d001a, 0x00000038 },
-	{ 0x0000e856, 0x00000004 },
-	{ 0x000d001c, 0x00000038 },
-	{ 0x0000e857, 0x00000004 },
-	{ 0x000d001e, 0x00000038 },
-	{ 0x0000e824, 0x00000004 },
-	{ 0x000d0020, 0x00000038 },
-	{ 0x0000e825, 0x00000004 },
-	{ 0x000d0022, 0x00000038 },
-	{ 0x0000e830, 0x00000004 },
-	{ 0x000d0024, 0x00000038 },
-	{ 0x0000f0c0, 0x00000004 },
-	{ 0x000d0026, 0x00000038 },
-	{ 0x0000f0c1, 0x00000004 },
-	{ 0x000d0028, 0x00000038 },
-	{ 0x0000f041, 0x00000004 },
-	{ 0x000d002a, 0x00000038 },
-	{ 0x0000f184, 0x00000004 },
-	{ 0x000d002c, 0x00000038 },
-	{ 0x0000f185, 0x00000004 },
-	{ 0x000d002e, 0x00000038 },
-	{ 0x0000f186, 0x00000004 },
-	{ 0x000d0030, 0x00000038 },
-	{ 0x0000f187, 0x00000004 },
-	{ 0x000d0032, 0x00000038 },
-	{ 0x0000f180, 0x00000004 },
-	{ 0x000d0034, 0x00000038 },
-	{ 0x0000f393, 0x00000004 },
-	{ 0x000d0036, 0x00000038 },
-	{ 0x0000f38a, 0x00000004 },
-	{ 0x000d0038, 0x00000038 },
-	{ 0x0000f38e, 0x00000004 },
-	{ 0x0000e821, 0x00000004 },
-	{ 0x0140a000, 0x00000004 },
-	{ 0x00000043, 0x00000018 },
-	{ 0x00cce800, 0x00000004 },
-	{ 0x001b0001, 0x00000004 },
-	{ 0x08004800, 0x00000004 },
-	{ 0x001b0001, 0x00000004 },
-	{ 0x08004800, 0x00000004 },
-	{ 0x001b0001, 0x00000004 },
-	{ 0x08004800, 0x00000004 },
-	{ 0x0000003a, 0x00000008 },
-	{ 0x0000a000, 0000000000 },
-	{ 0x02c0a000, 0x00000004 },
-	{ 0x000ca000, 0x00000004 },
-	{ 0x00130000, 0x00000004 },
-	{ 0x000c2000, 0x00000004 },
-	{ 0xc980c045, 0x00000008 },
-	{ 0x2000451d, 0x00000004 },
-	{ 0x0000e580, 0x00000004 },
-	{ 0x000ce581, 0x00000004 },
-	{ 0x08004580, 0x00000004 },
-	{ 0x000ce581, 0x00000004 },
-	{ 0x0000004c, 0x00000008 },
-	{ 0x0000a000, 0000000000 },
-	{ 0x000c2000, 0x00000004 },
-	{ 0x0000e50e, 0x00000004 },
-	{ 0x00032000, 0x00000004 },
-	{ 0x00022056, 0x00000028 },
-	{ 0x00000056, 0x00000024 },
-	{ 0x0800450f, 0x00000004 },
-	{ 0x0000a050, 0x00000008 },
-	{ 0x0000e565, 0x00000004 },
-	{ 0x0000e566, 0x00000004 },
-	{ 0x00000057, 0x00000008 },
-	{ 0x03cca5b4, 0x00000004 },
-	{ 0x05432000, 0x00000004 },
-	{ 0x00022000, 0x00000004 },
-	{ 0x4ccce063, 0x00000030 },
-	{ 0x08274565, 0x00000004 },
-	{ 0x00000063, 0x00000030 },
-	{ 0x08004564, 0x00000004 },
-	{ 0x0000e566, 0x00000004 },
-	{ 0x0000005a, 0x00000008 },
-	{ 0x00802066, 0x00000010 },
-	{ 0x00202000, 0x00000004 },
-	{ 0x001b00ff, 0x00000004 },
-	{ 0x01000069, 0x00000010 },
-	{ 0x001f2000, 0x00000004 },
-	{ 0x001c00ff, 0x00000004 },
-	{ 0000000000, 0x0000000c },
-	{ 0x00000085, 0x00000030 },
-	{ 0x0000005a, 0x00000008 },
-	{ 0x0000e576, 0x00000004 },
-	{ 0x000ca000, 0x00000004 },
-	{ 0x00012000, 0x00000004 },
-	{ 0x00082000, 0x00000004 },
-	{ 0x1800650e, 0x00000004 },
-	{ 0x00092000, 0x00000004 },
-	{ 0x000a2000, 0x00000004 },
-	{ 0x000f0000, 0x00000004 },
-	{ 0x00400000, 0x00000004 },
-	{ 0x00000079, 0x00000018 },
-	{ 0x0000e563, 0x00000004 },
-	{ 0x00c0e5f9, 0x000000c2 },
-	{ 0x0000006e, 0x00000008 },
-	{ 0x0000a06e, 0x00000008 },
-	{ 0x0000e576, 0x00000004 },
-	{ 0x0000e577, 0x00000004 },
-	{ 0x0000e50e, 0x00000004 },
-	{ 0x0000e50f, 0x00000004 },
-	{ 0x0140a000, 0x00000004 },
-	{ 0x0000007c, 0x00000018 },
-	{ 0x00c0e5f9, 0x000000c2 },
-	{ 0x0000007c, 0x00000008 },
-	{ 0x0014e50e, 0x00000004 },
-	{ 0x0040e50f, 0x00000004 },
-	{ 0x00c0007f, 0x00000008 },
-	{ 0x0000e570, 0x00000004 },
-	{ 0x0000e571, 0x00000004 },
-	{ 0x0000e572, 0x0000000c },
-	{ 0x0000a000, 0x00000004 },
-	{ 0x0140a000, 0x00000004 },
-	{ 0x0000e568, 0x00000004 },
-	{ 0x000c2000, 0x00000004 },
-	{ 0x00000089, 0x00000018 },
-	{ 0x000b0000, 0x00000004 },
-	{ 0x18c0e562, 0x00000004 },
-	{ 0x0000008b, 0x00000008 },
-	{ 0x00c0008a, 0x00000008 },
-	{ 0x000700e4, 0x00000004 },
-	{ 0x00000097, 0x00000038 },
-	{ 0x000ca099, 0x00000030 },
-	{ 0x080045bb, 0x00000004 },
-	{ 0x000c209a, 0x00000030 },
-	{ 0x0800e5bc, 0000000000 },
-	{ 0x0000e5bb, 0x00000004 },
-	{ 0x0000e5bc, 0000000000 },
-	{ 0x00120000, 0x0000000c },
-	{ 0x00120000, 0x00000004 },
-	{ 0x001b0002, 0x0000000c },
-	{ 0x0000a000, 0x00000004 },
-	{ 0x0000e821, 0x00000004 },
-	{ 0x0000e800, 0000000000 },
-	{ 0x0000e821, 0x00000004 },
-	{ 0x0000e82e, 0000000000 },
-	{ 0x02cca000, 0x00000004 },
-	{ 0x00140000, 0x00000004 },
-	{ 0x000ce1cc, 0x00000004 },
-	{ 0x050de1cd, 0x00000004 },
-	{ 0x000000a7, 0x00000020 },
-	{ 0x4200e000, 0000000000 },
-	{ 0x000000ae, 0x00000038 },
-	{ 0x000ca000, 0x00000004 },
-	{ 0x00140000, 0x00000004 },
-	{ 0x000c2000, 0x00000004 },
-	{ 0x00160000, 0x00000004 },
-	{ 0x700ce000, 0x00000004 },
-	{ 0x001400aa, 0x00000008 },
-	{ 0x4000e000, 0000000000 },
-	{ 0x02400000, 0x00000004 },
-	{ 0x400ee000, 0x00000004 },
-	{ 0x02400000, 0x00000004 },
-	{ 0x4000e000, 0000000000 },
-	{ 0x000c2000, 0x00000004 },
-	{ 0x0240e51b, 0x00000004 },
-	{ 0x0080e50a, 0x00000005 },
-	{ 0x0080e50b, 0x00000005 },
-	{ 0x00220000, 0x00000004 },
-	{ 0x000700e4, 0x00000004 },
-	{ 0x000000c1, 0x00000038 },
-	{ 0x000c209a, 0x00000030 },
-	{ 0x0880e5bd, 0x00000005 },
-	{ 0x000c2099, 0x00000030 },
-	{ 0x0800e5bb, 0x00000005 },
-	{ 0x000c209a, 0x00000030 },
-	{ 0x0880e5bc, 0x00000005 },
-	{ 0x000000c4, 0x00000008 },
-	{ 0x0080e5bd, 0x00000005 },
-	{ 0x0000e5bb, 0x00000005 },
-	{ 0x0080e5bc, 0x00000005 },
-	{ 0x00210000, 0x00000004 },
-	{ 0x02800000, 0x00000004 },
-	{ 0x00c000c8, 0x00000018 },
-	{ 0x4180e000, 0x00000040 },
-	{ 0x000000ca, 0x00000024 },
-	{ 0x01000000, 0x0000000c },
-	{ 0x0100e51d, 0x0000000c },
-	{ 0x000045bb, 0x00000004 },
-	{ 0x000080c4, 0x00000008 },
-	{ 0x0000f3ce, 0x00000004 },
-	{ 0x0140a000, 0x00000004 },
-	{ 0x00cc2000, 0x00000004 },
-	{ 0x08c053cf, 0x00000040 },
-	{ 0x00008000, 0000000000 },
-	{ 0x0000f3d2, 0x00000004 },
-	{ 0x0140a000, 0x00000004 },
-	{ 0x00cc2000, 0x00000004 },
-	{ 0x08c053d3, 0x00000040 },
-	{ 0x00008000, 0000000000 },
-	{ 0x0000f39d, 0x00000004 },
-	{ 0x0140a000, 0x00000004 },
-	{ 0x00cc2000, 0x00000004 },
-	{ 0x08c0539e, 0x00000040 },
-	{ 0x00008000, 0000000000 },
-	{ 0x03c00830, 0x00000004 },
-	{ 0x4200e000, 0000000000 },
-	{ 0x0000a000, 0x00000004 },
-	{ 0x200045e0, 0x00000004 },
-	{ 0x0000e5e1, 0000000000 },
-	{ 0x00000001, 0000000000 },
-	{ 0x000700e1, 0x00000004 },
-	{ 0x0800e394, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-};
-
-static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+	return ret;
+}
+
+static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
 	u32 ret;
 	RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
@@ -827,37 +123,159 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 	return ret;
 }
 
+static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+	u32 ret;
+	RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
+	ret = RADEON_READ(RS480_NB_MC_DATA);
+	RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
+	return ret;
+}
+
+static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+	u32 ret;
+	RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
+	ret = RADEON_READ(RS690_MC_DATA);
+	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
+	return ret;
+}
+
+static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+	u32 ret;
+	RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
+				      RS600_MC_IND_CITF_ARB0));
+	ret = RADEON_READ(RS600_MC_DATA);
+	return ret;
+}
+
+static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+{
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+		return RS690_READ_MCIND(dev_priv, addr);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
+		return RS600_READ_MCIND(dev_priv, addr);
+	else
+		return RS480_READ_MCIND(dev_priv, addr);
+}
+
 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 {
-	
-	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
-		return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
+		return RADEON_READ(R700_MC_VM_FB_LOCATION);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return RADEON_READ(R600_MC_VM_FB_LOCATION);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+		return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
+	else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+		 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+		return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
+		return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 	else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
-		return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
+		return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 	else
 		return RADEON_READ(RADEON_MC_FB_LOCATION);
 }
 
 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 {
-	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
-		RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
+		RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+		R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
+	else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+		 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+		RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
+		RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 	else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
-		RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
+		R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 	else
 		RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 }
 
-static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
+void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 {
-	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
-		RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
+	/*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
+		RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
+		RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
+	} else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
+		RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
+		RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
+	} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+		R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
+	else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+		 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+		RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
+		RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 	else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
-		RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
+		R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 	else
 		RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 }
 
+void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+{
+	u32 agp_base_hi = upper_32_bits(agp_base);
+	u32 agp_base_lo = agp_base & 0xffffffff;
+	u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
+
+	/* R6xx/R7xx must be aligned to a 4MB boundry */
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
+		RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
+		R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
+		R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+		 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
+		RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
+		RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
+	} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
+		RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
+		RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
+	} else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
+		R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
+		R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
+		RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+		RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
+	} else {
+		RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
+			RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
+	}
+}
+
+void radeon_enable_bm(struct drm_radeon_private *dev_priv)
+{
+	u32 tmp;
+	/* Turn on bus mastering */
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
+		/* rs600/rs690/rs740 */
+		tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
+		RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
+		/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
+		tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+		RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+	} /* PCIE cards appears to not need this */
+}
+
 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -872,19 +290,10 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 	return RADEON_READ(RADEON_PCIE_DATA);
 }
 
-static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
-{
-	u32 ret;
-	RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
-	ret = RADEON_READ(RADEON_IGPGART_DATA);
-	RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
-	return ret;
-}
-
 #if RADEON_FIFO_DEBUG
 static void radeon_status(drm_radeon_private_t * dev_priv)
 {
-	printk("%s:\n", __FUNCTION__);
+	printk("%s:\n", __func__);
 	printk("RBBM_STATUS = 0x%08x\n",
 	       (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 	printk("CP_RB_RTPR = 0x%08x\n",
@@ -915,16 +324,21 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 
 	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 
-	tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
-	tmp |= RADEON_RB3D_DC_FLUSH_ALL;
-	RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
+		tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
+		tmp |= RADEON_RB3D_DC_FLUSH_ALL;
+		RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 
-	for (i = 0; i < dev_priv->usec_timeout; i++) {
-		if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
-		      & RADEON_RB3D_DC_BUSY)) {
-			return 0;
+		for (i = 0; i < dev_priv->usec_timeout; i++) {
+			if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
+			      & RADEON_RB3D_DC_BUSY)) {
+				return 0;
+			}
+			DRM_UDELAY(1);
 		}
-		DRM_UDELAY(1);
+	} else {
+		/* don't flush or purge cache here or lockup */
+		return 0;
 	}
 
 #if RADEON_FIFO_DEBUG
@@ -947,6 +361,9 @@ static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 			return 0;
 		DRM_UDELAY(1);
 	}
+	DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
+		 RADEON_READ(RADEON_RBBM_STATUS),
+		 RADEON_READ(R300_VAP_CNTL_STATUS));
 
 #if RADEON_FIFO_DEBUG
 	DRM_ERROR("failed!\n");
@@ -973,6 +390,9 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 		}
 		DRM_UDELAY(1);
 	}
+	DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
+		 RADEON_READ(RADEON_RBBM_STATUS),
+		 RADEON_READ(R300_VAP_CNTL_STATUS));
 
 #if RADEON_FIFO_DEBUG
 	DRM_ERROR("failed!\n");
@@ -981,6 +401,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 	return -EBUSY;
 }
 
+static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
+{
+	uint32_t gb_tile_config, gb_pipe_sel = 0;
+
+	/* RS4xx/RS6xx/R4xx/R5xx */
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
+		gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
+		dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
+	} else {
+		/* R3xx */
+		if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
+		    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
+			dev_priv->num_gb_pipes = 2;
+		} else {
+			/* R3Vxx */
+			dev_priv->num_gb_pipes = 1;
+		}
+	}
+	DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
+
+	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
+
+	switch (dev_priv->num_gb_pipes) {
+	case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
+	case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
+	case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
+	default:
+	case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
+	}
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
+		RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
+		RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
+	}
+	RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
+	radeon_do_wait_for_idle(dev_priv);
+	RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
+	RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
+					       R300_DC_AUTOFLUSH_ENABLE |
+					       R300_DC_DC_DISABLE_IGNORE_PE));
+
+
+}
+
 /* ================================================================
  * CP control, initialization
  */
@@ -994,8 +458,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 	radeon_do_wait_for_idle(dev_priv);
 
 	RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
-
-	if (dev_priv->microcode_version == UCODE_R200) {
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
+		DRM_INFO("Loading R100 Microcode\n");
+		for (i = 0; i < 256; i++) {
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+				     R100_cp_microcode[i][1]);
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+				     R100_cp_microcode[i][0]);
+		}
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 		DRM_INFO("Loading R200 Microcode\n");
 		for (i = 0; i < 256; i++) {
 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1003,7 +481,12 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 				     R200_cp_microcode[i][0]);
 		}
-	} else if (dev_priv->microcode_version == UCODE_R300) {
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 		DRM_INFO("Loading R300 Microcode\n");
 		for (i = 0; i < 256; i++) {
 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
@@ -1011,12 +494,45 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 				     R300_cp_microcode[i][0]);
 		}
-	} else {
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
+		DRM_INFO("Loading R400 Microcode\n");
+		for (i = 0; i < 256; i++) {
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+				     R420_cp_microcode[i][1]);
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+				     R420_cp_microcode[i][0]);
+		}
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
+		DRM_INFO("Loading RS690/RS740 Microcode\n");
+		for (i = 0; i < 256; i++) {
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+				     RS690_cp_microcode[i][1]);
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+				     RS690_cp_microcode[i][0]);
+		}
+	} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
+		DRM_INFO("Loading RS600 Microcode\n");
 		for (i = 0; i < 256; i++) {
 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
-				     radeon_cp_microcode[i][1]);
+				     RS600_cp_microcode[i][1]);
 			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
-				     radeon_cp_microcode[i][0]);
+				     RS600_cp_microcode[i][0]);
+		}
+	} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
+		   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
+		DRM_INFO("Loading R500 Microcode\n");
+		for (i = 0; i < 256; i++) {
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+				     R520_cp_microcode[i][1]);
+			RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+				     R520_cp_microcode[i][0]);
 		}
 	}
 }
@@ -1068,14 +584,20 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 
 	dev_priv->cp_running = 1;
 
-	BEGIN_RING(6);
-
+	BEGIN_RING(8);
+	/* isync can only be written through cp on r5xx write it here */
+	OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
+	OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
+		 RADEON_ISYNC_ANY3D_IDLE2D |
+		 RADEON_ISYNC_WAIT_IDLEGUI |
+		 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 	RADEON_PURGE_CACHE();
 	RADEON_PURGE_ZCACHE();
 	RADEON_WAIT_UNTIL_IDLE();
-
 	ADVANCE_RING();
 	COMMIT_RING();
+
+	dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 }
 
 /* Reset the Command Processor.  This will not flush any pending
@@ -1111,15 +633,16 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 static int radeon_do_engine_reset(struct drm_device * dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
+	u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 	DRM_DEBUG("\n");
 
 	radeon_do_pixcache_flush(dev_priv);
 
-	if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
+		/* may need something similar for newer chips */
 		clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 		mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
-		
+
 		RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 						    RADEON_FORCEON_MCLKA |
 						    RADEON_FORCEON_MCLKB |
@@ -1127,33 +650,39 @@ static int radeon_do_engine_reset(struct drm_device * dev)
 						    RADEON_FORCEON_YCLKB |
 						    RADEON_FORCEON_MC |
 						    RADEON_FORCEON_AIC));
-		
-		rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
-		
-		RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
-						      RADEON_SOFT_RESET_CP |
-						      RADEON_SOFT_RESET_HI |
-						      RADEON_SOFT_RESET_SE |
-						      RADEON_SOFT_RESET_RE |
-						      RADEON_SOFT_RESET_PP |
-						      RADEON_SOFT_RESET_E2 |
-						      RADEON_SOFT_RESET_RB));
-		RADEON_READ(RADEON_RBBM_SOFT_RESET);
-		RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
-						      ~(RADEON_SOFT_RESET_CP |
-							RADEON_SOFT_RESET_HI |
-							RADEON_SOFT_RESET_SE |
-							RADEON_SOFT_RESET_RE |
-							RADEON_SOFT_RESET_PP |
-							RADEON_SOFT_RESET_E2 |
-							RADEON_SOFT_RESET_RB)));
-		RADEON_READ(RADEON_RBBM_SOFT_RESET);
-		
+	}
+
+	rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
+					      RADEON_SOFT_RESET_CP |
+					      RADEON_SOFT_RESET_HI |
+					      RADEON_SOFT_RESET_SE |
+					      RADEON_SOFT_RESET_RE |
+					      RADEON_SOFT_RESET_PP |
+					      RADEON_SOFT_RESET_E2 |
+					      RADEON_SOFT_RESET_RB));
+	RADEON_READ(RADEON_RBBM_SOFT_RESET);
+	RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
+					      ~(RADEON_SOFT_RESET_CP |
+						RADEON_SOFT_RESET_HI |
+						RADEON_SOFT_RESET_SE |
+						RADEON_SOFT_RESET_RE |
+						RADEON_SOFT_RESET_PP |
+						RADEON_SOFT_RESET_E2 |
+						RADEON_SOFT_RESET_RB)));
+	RADEON_READ(RADEON_RBBM_SOFT_RESET);
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 		RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 		RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 		RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 	}
 
+	/* setup the raster pipes */
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
+	    radeon_init_pipes(dev_priv);
+
 	/* Reset the CP ring */
 	radeon_do_cp_reset(dev_priv);
 
@@ -1167,10 +696,10 @@ static int radeon_do_engine_reset(struct drm_device * dev)
 }
 
 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
-				       drm_radeon_private_t * dev_priv)
+				       drm_radeon_private_t *dev_priv,
+				       struct drm_file *file_priv)
 {
 	u32 ring_start, cur_read_ptr;
-	u32 tmp;
 
 	/* Initialize the memory controller. With new memory map, the fb location
 	 * is not changed, it should have been properly initialized already. Part
@@ -1184,7 +713,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 
 #if __OS_HAS_AGP
 	if (dev_priv->flags & RADEON_IS_AGP) {
-		RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
+		radeon_write_agp_base(dev_priv, dev->agp->base);
+
 		radeon_write_agp_location(dev_priv,
 			     (((dev_priv->gart_vm_start - 1 +
 				dev_priv->gart_size) & 0xffff0000) |
@@ -1218,17 +748,10 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 	} else
 #endif
 	{
-		struct drm_sg_mem *entry = dev->sg;
-		unsigned long tmp_ofs, page_ofs;
-
-		tmp_ofs = dev_priv->ring_rptr->offset -
-				(unsigned long)dev->sg->virtual;
-		page_ofs = tmp_ofs >> PAGE_SHIFT;
-
-		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
-		DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
-			  (unsigned long)entry->busaddr[page_ofs],
-			  entry->handle + tmp_ofs);
+		RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
+			     dev_priv->ring_rptr->offset
+			     - ((unsigned long) dev->sg->virtual)
+			     + dev_priv->gart_vm_start);
 	}
 
 	/* Set ring buffer size */
@@ -1245,8 +768,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 		     dev_priv->ring.size_l2qw);
 #endif
 
-	/* Start with assuming that writeback doesn't work */
-	dev_priv->writeback_works = 0;
 
 	/* Initialize the scratch register pointer.  This will cause
 	 * the scratch register values to be written out to memory
@@ -1258,25 +779,25 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 	RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 		     + RADEON_SCRATCH_REG_OFFSET);
 
-	dev_priv->scratch = ((__volatile__ u32 *)
-			     dev_priv->ring_rptr->handle +
-			     (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
-
 	RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 
-	/* Turn on bus mastering */
-	tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
-	RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+	radeon_enable_bm(dev_priv);
+
+	radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
+	RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 
-	dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
-	RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
+	radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
+	RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 
-	dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
-	RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
-		     dev_priv->sarea_priv->last_dispatch);
+	radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
+	RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 
-	dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
-	RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
+	/* reset sarea copies of these */
+	if (dev_priv->sarea_priv) {
+		dev_priv->sarea_priv->last_frame = 0;
+		dev_priv->sarea_priv->last_dispatch = 0;
+		dev_priv->sarea_priv->last_clear = 0;
+	}
 
 	radeon_do_wait_for_idle(dev_priv);
 
@@ -1293,15 +814,21 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 {
 	u32 tmp;
 
+	/* Start with assuming that writeback doesn't work */
+	dev_priv->writeback_works = 0;
+
 	/* Writeback doesn't seem to work everywhere, test it here and possibly
 	 * enable it if it appears to work
 	 */
-	DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
+	radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
+
 	RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 
 	for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
-		if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
-		    0xdeadbeef)
+		u32 val;
+
+		val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
+		if (val == 0xdeadbeef)
 			break;
 		DRM_UDELAY(1);
 	}
@@ -1319,8 +846,9 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 	}
 
 	if (!dev_priv->writeback_works) {
-		/* Disable writeback to avoid unnecessary bus master transfers */
-		RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
+		/* Disable writeback to avoid unnecessary bus master transfer */
+		RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
+			     RADEON_RB_NO_UPDATE);
 		RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 	}
 }
@@ -1328,40 +856,148 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 /* Enable or disable IGP GART on the chip */
 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 {
-	u32 temp, tmp;
+	u32 temp;
 
-	tmp = RADEON_READ(RADEON_AIC_CNTL);
-	DRM_DEBUG("setting igpgart AIC CNTL is %08X\n", tmp);
 	if (on) {
-		DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
-			 dev_priv->gart_vm_start,
-			 (long)dev_priv->gart_info.bus_addr,
-			 dev_priv->gart_size);
+		DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
+			  dev_priv->gart_vm_start,
+			  (long)dev_priv->gart_info.bus_addr,
+			  dev_priv->gart_size);
+
+		temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
+		if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+		    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+			IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
+							     RS690_BLOCK_GFX_D3_EN));
+		else
+			IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
-				     dev_priv->gart_info.bus_addr);
+		IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
+							       RS480_VA_SIZE_32MB));
 
-		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
+		temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
+		IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
+							RS480_TLB_ENABLE |
+							RS480_GTW_LAC_EN |
+							RS480_1LEVEL_GART));
+
+		temp = dev_priv->gart_info.bus_addr & 0xfffff000;
+		temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
+		IGP_WRITE_MCIND(RS480_GART_BASE, temp);
+
+		temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
+		IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
+						      RS480_REQ_TYPE_SNOOP_DIS));
+
+		radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 
-		RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
 		dev_priv->gart_size = 32*1024*1024;
-		radeon_write_agp_location(dev_priv,
-			     (((dev_priv->gart_vm_start - 1 +
-			       dev_priv->gart_size) & 0xffff0000) |
-			     (dev_priv->gart_vm_start >> 16)));
+		temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
+			 0xffff0000) | (dev_priv->gart_vm_start >> 16));
+
+		radeon_write_agp_location(dev_priv, temp);
+
+		temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
+		IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
+							       RS480_VA_SIZE_32MB));
+
+		do {
+			temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
+			if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
+				break;
+			DRM_UDELAY(1);
+		} while (1);
+
+		IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
+				RS480_GART_CACHE_INVALIDATE);
+
+		do {
+			temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
+			if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
+				break;
+			DRM_UDELAY(1);
+		} while (1);
+
+		IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
+	} else {
+		IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
+	}
+}
+
+/* Enable or disable IGP GART on the chip */
+static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
+{
+	u32 temp;
+	int i;
+
+	if (on) {
+		DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
+			 dev_priv->gart_vm_start,
+			 (long)dev_priv->gart_info.bus_addr,
+			 dev_priv->gart_size);
 
-		temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
+		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
+						    RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
+
+		for (i = 0; i < 19; i++)
+			IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
+					(RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
+					 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
+					 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
+					 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
+					 RS600_ENABLE_FRAGMENT_PROCESSING |
+					 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
+
+		IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
+							     RS600_PAGE_TABLE_TYPE_FLAT));
+
+		/* disable all other contexts */
+		for (i = 1; i < 8; i++)
+			IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
+
+		/* setup the page table aperture */
+		IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
+				dev_priv->gart_info.bus_addr);
+		IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
+				dev_priv->gart_vm_start);
+		IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
+				(dev_priv->gart_vm_start + dev_priv->gart_size - 1));
+		IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
+
+		/* setup the system aperture */
+		IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
+				dev_priv->gart_vm_start);
+		IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
+				(dev_priv->gart_vm_start + dev_priv->gart_size - 1));
+
+		/* enable page tables */
+		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
+		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
+
+		temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
+		IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
+
+		/* invalidate the cache */
+		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
+
+		temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
+		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
+		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
+
+		temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
+		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
+		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
+
+		temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
+		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
+		temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 
-		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
-		RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
-		RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
-       }
+	} else {
+		IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
+		temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
+		temp &= ~RS600_ENABLE_PAGE_TABLES;
+		IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
+	}
 }
 
 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
@@ -1398,11 +1034,18 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 {
 	u32 tmp;
 
-	if (dev_priv->flags & RADEON_IS_IGPGART) {
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
+	    (dev_priv->flags & RADEON_IS_IGPGART)) {
 		radeon_set_igpgart(dev_priv, on);
 		return;
 	}
 
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
+		rs600_set_igpgart(dev_priv, on);
+		return;
+	}
+
 	if (dev_priv->flags & RADEON_IS_PCIE) {
 		radeon_set_pciegart(dev_priv, on);
 		return;
@@ -1434,7 +1077,48 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 	}
 }
 
-static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
+{
+	struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
+	struct radeon_virt_surface *vp;
+	int i;
+
+	for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
+		if (!dev_priv->virt_surfaces[i].file_priv ||
+		    dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
+			break;
+	}
+	if (i >= 2 * RADEON_MAX_SURFACES)
+		return -ENOMEM;
+	vp = &dev_priv->virt_surfaces[i];
+
+	for (i = 0; i < RADEON_MAX_SURFACES; i++) {
+		struct radeon_surface *sp = &dev_priv->surfaces[i];
+		if (sp->refcount)
+			continue;
+
+		vp->surface_index = i;
+		vp->lower = gart_info->bus_addr;
+		vp->upper = vp->lower + gart_info->table_size;
+		vp->flags = 0;
+		vp->file_priv = PCIGART_FILE_PRIV;
+
+		sp->refcount = 1;
+		sp->lower = vp->lower;
+		sp->upper = vp->upper;
+		sp->flags = 0;
+
+		RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
+		RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
+		RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
+		return 0;
+	}
+
+	return -ENOMEM;
+}
+
+static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
+			     struct drm_file *file_priv)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
@@ -1447,14 +1131,11 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 		return -EINVAL;
 	}
 
-	if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
-	{
+	if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
 		DRM_DEBUG("Forcing AGP card to PCI mode\n");
 		dev_priv->flags &= ~RADEON_IS_AGP;
-	}
-	else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
-		 && !init->is_pci)
-	{
+	} else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
+		   && !init->is_pci) {
 		DRM_DEBUG("Restoring AGP flag\n");
 		dev_priv->flags |= RADEON_IS_AGP;
 	}
@@ -1607,9 +1288,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 
 #if __OS_HAS_AGP
 	if (dev_priv->flags & RADEON_IS_AGP) {
-		drm_core_ioremap(dev_priv->cp_ring, dev);
-		drm_core_ioremap(dev_priv->ring_rptr, dev);
-		drm_core_ioremap(dev->agp_buffer_map, dev);
+		drm_core_ioremap_wc(dev_priv->cp_ring, dev);
+		drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
+		drm_core_ioremap_wc(dev->agp_buffer_map, dev);
 		if (!dev_priv->cp_ring->handle ||
 		    !dev_priv->ring_rptr->handle ||
 		    !dev->agp_buffer_map->handle) {
@@ -1620,11 +1301,12 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 	} else
 #endif
 	{
-		dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
+		dev_priv->cp_ring->handle =
+			(void *)(unsigned long)dev_priv->cp_ring->offset;
 		dev_priv->ring_rptr->handle =
-		    (void *)dev_priv->ring_rptr->offset;
+			(void *)(unsigned long)dev_priv->ring_rptr->offset;
 		dev->agp_buffer_map->handle =
-		    (void *)dev->agp_buffer_map->offset;
+			(void *)(unsigned long)dev->agp_buffer_map->offset;
 
 		DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
 			  dev_priv->cp_ring->handle);
@@ -1720,7 +1402,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 
 	dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
 	dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
-
 	dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
 
 	dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
@@ -1732,6 +1413,10 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 	} else
 #endif
 	{
+		u32 sctrl;
+		int ret;
+
+		dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
 		/* if we have an offset set from userspace */
 		if (dev_priv->pcigart_offset_set) {
 			dev_priv->gart_info.bus_addr =
@@ -1741,7 +1426,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 			dev_priv->gart_info.mapping.size =
 			    dev_priv->gart_info.table_size;
 
-			drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
+			drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
 			dev_priv->gart_info.addr =
 			    dev_priv->gart_info.mapping.handle;
 
@@ -1772,18 +1457,37 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 			}
 		}
 
-		if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
+		sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
+		RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
+			ret = r600_page_table_init(dev);
+		else
+			ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
+		RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
+
+		if (!ret) {
 			DRM_ERROR("failed to init PCI GART!\n");
 			radeon_do_cleanup_cp(dev);
 			return -ENOMEM;
 		}
 
+		ret = radeon_setup_pcigart_surface(dev_priv);
+		if (ret) {
+			DRM_ERROR("failed to setup GART surface!\n");
+			if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
+				r600_page_table_cleanup(dev, &dev_priv->gart_info);
+			else
+				drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
+			radeon_do_cleanup_cp(dev);
+			return ret;
+		}
+
 		/* Turn on PCI GART */
 		radeon_set_pcigart(dev_priv, 1);
 	}
 
 	radeon_cp_load_microcode(dev_priv);
-	radeon_cp_init_ring_buffer(dev, dev_priv);
+	radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
 
 	dev_priv->last_buf = 0;
 
@@ -1826,8 +1530,12 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
 		if (dev_priv->gart_info.bus_addr) {
 			/* Turn off PCI GART */
 			radeon_set_pcigart(dev_priv, 0);
-			if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
-				DRM_ERROR("failed to cleanup PCI GART!\n");
+			if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
+				r600_page_table_cleanup(dev, &dev_priv->gart_info);
+			else {
+				if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
+					DRM_ERROR("failed to cleanup PCI GART!\n");
+			}
 		}
 
 		if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
@@ -1849,7 +1557,7 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
  *
  * Charl P. Botha <http://cpbotha.net>
  */
-static int radeon_do_resume_cp(struct drm_device * dev)
+static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
@@ -1872,9 +1580,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
 	}
 
 	radeon_cp_load_microcode(dev_priv);
-	radeon_cp_init_ring_buffer(dev, dev_priv);
+	radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
 
 	radeon_do_engine_reset(dev);
+	radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 
 	DRM_DEBUG("radeon_do_resume_cp() complete\n");
 
@@ -1883,6 +1592,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
 
 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
+	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_init_t *init = data;
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
@@ -1894,9 +1604,14 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
 	case RADEON_INIT_CP:
 	case RADEON_INIT_R200_CP:
 	case RADEON_INIT_R300_CP:
-		return radeon_do_init_cp(dev, init);
+		return radeon_do_init_cp(dev, init, file_priv);
+	case RADEON_INIT_R600_CP:
+		return r600_do_init_cp(dev, init, file_priv);
 	case RADEON_CLEANUP_CP:
-		return radeon_do_cleanup_cp(dev);
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+			return r600_do_cleanup_cp(dev);
+		else
+			return radeon_do_cleanup_cp(dev);
 	}
 
 	return -EINVAL;
@@ -1919,7 +1634,10 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
 		return 0;
 	}
 
-	radeon_do_cp_start(dev_priv);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		r600_do_cp_start(dev_priv);
+	else
+		radeon_do_cp_start(dev_priv);
 
 	return 0;
 }
@@ -1950,7 +1668,10 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
 	 * code so that the DRM ioctl wrapper can try again.
 	 */
 	if (stop->idle) {
-		ret = radeon_do_cp_idle(dev_priv);
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+			ret = r600_do_cp_idle(dev_priv);
+		else
+			ret = radeon_do_cp_idle(dev_priv);
 		if (ret)
 			return ret;
 	}
@@ -1959,10 +1680,16 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
 	 * we will get some dropped triangles as they won't be fully
 	 * rendered before the CP is shut down.
 	 */
-	radeon_do_cp_stop(dev_priv);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		r600_do_cp_stop(dev_priv);
+	else
+		radeon_do_cp_stop(dev_priv);
 
 	/* Reset the engine */
-	radeon_do_engine_reset(dev);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		r600_do_engine_reset(dev);
+	else
+		radeon_do_engine_reset(dev);
 
 	return 0;
 }
@@ -1975,41 +1702,51 @@ void radeon_do_release(struct drm_device * dev)
 	if (dev_priv) {
 		if (dev_priv->cp_running) {
 			/* Stop the cp */
-			while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
-				DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
-#ifdef __linux__
-				schedule();
-#else
-#if defined(__FreeBSD__) && __FreeBSD_version > 500000
-				mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
-				       1);
-#elif defined(__DragonFly__)
-				crit_enter();
-				tsleep_interlock(&ret);
-				DRM_UNLOCK();
-				tsleep(&ret, 0, "rdnrel", 1);
-				crit_exit();
-				DRM_LOCK();
-#else
-				tsleep(&ret, PZERO, "rdnrel", 1);
-#endif
-#endif
+			if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
+				while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
+					DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
+                			crit_enter();
+                			tsleep_interlock((void *)&dev->lock.lock_queue);
+                			DRM_UNLOCK();
+                			ret = tsleep((void *)&dev->lock.lock_queue, PCATCH,
+                    			    "rdnrel", 0);
+                			crit_exit();
+                			DRM_LOCK();
+				}
+			} else {
+				while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
+					DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
+                			crit_enter();
+                			tsleep_interlock((void *)&dev->lock.lock_queue);
+                			DRM_UNLOCK();
+                			ret = tsleep((void *)&dev->lock.lock_queue, PCATCH,
+                    			    "rdnrel", 0);
+                			crit_exit();
+                			DRM_LOCK();
+				}
+			}
+			if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
+				r600_do_cp_stop(dev_priv);
+				r600_do_engine_reset(dev);
+			} else {
+				radeon_do_cp_stop(dev_priv);
+				radeon_do_engine_reset(dev);
 			}
-			radeon_do_cp_stop(dev_priv);
-			radeon_do_engine_reset(dev);
 		}
 
-		/* Disable *all* interrupts */
-		if (dev_priv->mmio)	/* remove this after permanent addmaps */
-			RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
-
-		if (dev_priv->mmio) {	/* remove all surfaces */
-			for (i = 0; i < RADEON_MAX_SURFACES; i++) {
-				RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
-				RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
-					     16 * i, 0);
-				RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
-					     16 * i, 0);
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
+			/* Disable *all* interrupts */
+			if (dev_priv->mmio)	/* remove this after permanent addmaps */
+				RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
+
+			if (dev_priv->mmio) {	/* remove all surfaces */
+				for (i = 0; i < RADEON_MAX_SURFACES; i++) {
+					RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
+					RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
+						     16 * i, 0);
+					RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
+						     16 * i, 0);
+				}
 			}
 		}
 
@@ -2018,7 +1755,10 @@ void radeon_do_release(struct drm_device * dev)
 		radeon_mem_takedown(&(dev_priv->fb_heap));
 
 		/* deallocate kernel resources */
-		radeon_do_cleanup_cp(dev);
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+			r600_do_cleanup_cp(dev);
+		else
+			radeon_do_cleanup_cp(dev);
 	}
 }
 
@@ -2036,7 +1776,10 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
 		return -EINVAL;
 	}
 
-	radeon_do_cp_reset(dev_priv);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		r600_do_cp_reset(dev_priv);
+	else
+		radeon_do_cp_reset(dev_priv);
 
 	/* The CP is no longer running after an engine reset */
 	dev_priv->cp_running = 0;
@@ -2051,24 +1794,36 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	return radeon_do_cp_idle(dev_priv);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return r600_do_cp_idle(dev_priv);
+	else
+		return radeon_do_cp_idle(dev_priv);
 }
 
 /* Added by Charl P. Botha to call radeon_do_resume_cp().
  */
 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+	DRM_DEBUG("\n");
 
-	return radeon_do_resume_cp(dev);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return r600_do_resume_cp(dev, file_priv);
+	else
+		return radeon_do_resume_cp(dev, file_priv);
 }
 
 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
 {
+	drm_radeon_private_t *dev_priv = dev->dev_private;
 	DRM_DEBUG("\n");
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	return radeon_do_engine_reset(dev);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		return r600_do_engine_reset(dev);
+	else
+		return radeon_do_engine_reset(dev);
 }
 
 /* ================================================================
@@ -2118,7 +1873,7 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
 	start = dev_priv->last_buf;
 
 	for (t = 0; t < dev_priv->usec_timeout; t++) {
-		u32 done_age = GET_SCRATCH(1);
+		u32 done_age = GET_SCRATCH(dev_priv, 1);
 		DRM_DEBUG("done_age = %d\n", done_age);
 		for (i = start; i < dma->buf_count; i++) {
 			buf = dma->buflist[i];
@@ -2152,8 +1907,9 @@ struct drm_buf *radeon_freelist_get(struct drm_device * dev)
 	struct drm_buf *buf;
 	int i, t;
 	int start;
-	u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
+	u32 done_age;
 
+	done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 	if (++dev_priv->last_buf >= dma->buf_count)
 		dev_priv->last_buf = 0;
 
@@ -2308,6 +2064,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
 	case CHIP_R300:
 	case CHIP_R350:
 	case CHIP_R420:
+	case CHIP_R423:
 	case CHIP_RV410:
 	case CHIP_RV515:
 	case CHIP_R520:
@@ -2327,6 +2084,18 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
 	else
 		dev_priv->flags |= RADEON_IS_PCI;
 
+	ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
+			 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
+			 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
+	if (ret != 0)
+		return ret;
+
+	ret = drm_vblank_init(dev, 2);
+	if (ret) {
+		radeon_driver_unload(dev);
+		return ret;
+	}
+
 	DRM_DEBUG("%s card detected\n",
 		  ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
 	return ret;
@@ -2343,12 +2112,6 @@ int radeon_driver_firstopen(struct drm_device *dev)
 
 	dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
 
-	ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
-			 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
-			 _DRM_READ_ONLY, &dev_priv->mmio);
-	if (ret != 0)
-		return ret;
-
 	dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
 	ret = drm_addmap(dev, dev_priv->fb_aper_offset,
 			 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
@@ -2364,8 +2127,49 @@ int radeon_driver_unload(struct drm_device *dev)
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 
 	DRM_DEBUG("\n");
+
+	drm_rmmap(dev, dev_priv->mmio);
+
 	drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
 
 	dev->dev_private = NULL;
 	return 0;
 }
+
+void radeon_commit_ring(drm_radeon_private_t *dev_priv)
+{
+	int i;
+	u32 *ring;
+	int tail_aligned;
+
+	/* check if the ring is padded out to 16-dword alignment */
+
+	tail_aligned = dev_priv->ring.tail & 0xf;
+	if (tail_aligned) {
+		int num_p2 = 16 - tail_aligned;
+
+		ring = dev_priv->ring.start;
+		/* pad with some CP_PACKET2 */
+		for (i = 0; i < num_p2; i++)
+			ring[dev_priv->ring.tail + i] = CP_PACKET2();
+
+		dev_priv->ring.tail += i;
+
+		dev_priv->ring.space -= num_p2 * sizeof(u32);
+	}
+
+	dev_priv->ring.tail &= dev_priv->ring.tail_mask;
+
+	DRM_MEMORYBARRIER();
+	GET_RING_HEAD( dev_priv );
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
+		RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
+		/* read from PCI bus to ensure correct posting */
+		RADEON_READ(R600_CP_RB_RPTR);
+	} else {
+		RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
+		/* read from PCI bus to ensure correct posting */
+		RADEON_READ(RADEON_CP_RB_RPTR);
+	}
+}
diff --git a/sys/dev/drm/radeon_drm.h b/sys/dev/drm/radeon_drm.h
index 90c389518c..c0d566cdee 100644
--- a/sys/dev/drm/radeon_drm.h
+++ b/sys/dev/drm/radeon_drm.h
@@ -28,8 +28,6 @@
  *    Kevin E. Martin <martin@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *    Keith Whitwell <keith@tungstengraphics.com>
- *
- * $DragonFly: src/sys/dev/drm/radeon_drm.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __RADEON_DRM_H__
@@ -227,9 +225,22 @@ typedef union {
 #define R300_CMD_WAIT			7
 #	define R300_WAIT_2D		0x1
 #	define R300_WAIT_3D		0x2
+/* these two defines are DOING IT WRONG - however
+ * we have userspace which relies on using these.
+ * The wait interface is backwards compat new 
+ * code should use the NEW_WAIT defines below
+ * THESE ARE NOT BIT FIELDS
+ */
 #	define R300_WAIT_2D_CLEAN	0x3
 #	define R300_WAIT_3D_CLEAN	0x4
+
+#	define R300_NEW_WAIT_2D_3D	0x3
+#	define R300_NEW_WAIT_2D_2D_CLEAN	0x4
+#	define R300_NEW_WAIT_3D_3D_CLEAN	0x6
+#	define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN	0x8
+
 #define R300_CMD_SCRATCH		8
+#define R300_CMD_R500FP                 9
 
 typedef union {
 	unsigned int u;
@@ -258,6 +269,9 @@ typedef union {
 	struct {
 		unsigned char cmd_type, reg, n_bufs, flags;
 	} scratch;
+	struct {
+		unsigned char cmd_type, count, adrlo, adrhi_flags;
+	} r500fp;
 } drm_r300_cmd_header_t;
 
 #define RADEON_FRONT			0x1
@@ -268,6 +282,9 @@ typedef union {
 #define RADEON_USE_HIERZ		0x40000000
 #define RADEON_USE_COMP_ZBUF		0x20000000
 
+#define R500FP_CONSTANT_TYPE  (1 << 1)
+#define R500FP_CONSTANT_CLAMP (1 << 2)
+
 /* Primitive types
  */
 #define RADEON_POINTS			0x1
@@ -286,6 +303,7 @@ typedef union {
 #define RADEON_INDEX_PRIM_OFFSET	20
 
 #define RADEON_SCRATCH_REG_OFFSET	32
+#define R600_SCRATCH_REG_OFFSET	        256
 
 #define RADEON_NR_SAREA_CLIPRECTS	12
 
@@ -509,7 +527,8 @@ typedef struct drm_radeon_init {
 		RADEON_INIT_CP = 0x01,
 		RADEON_CLEANUP_CP = 0x02,
 		RADEON_INIT_R200_CP = 0x03,
-		RADEON_INIT_R300_CP = 0x04
+		RADEON_INIT_R300_CP = 0x04,
+		RADEON_INIT_R600_CP = 0x05,
 	} func;
 	unsigned long sarea_priv_offset;
 	int is_pci; /* for overriding only */
@@ -635,6 +654,9 @@ typedef struct drm_radeon_indirect {
 	int discard;
 } drm_radeon_indirect_t;
 
+#define RADEON_INDIRECT_DISCARD (1 << 0)
+#define RADEON_INDIRECT_NOFLUSH (1 << 1)
+
 /* enum for card type parameters */
 #define RADEON_CARD_PCI 0
 #define RADEON_CARD_AGP 1
@@ -659,6 +681,7 @@ typedef struct drm_radeon_indirect {
 #define RADEON_PARAM_CARD_TYPE             12
 #define RADEON_PARAM_VBLANK_CRTC           13   /* VBLANK CRTC */
 #define RADEON_PARAM_FB_LOCATION           14   /* FB location */
+#define RADEON_PARAM_NUM_GB_PIPES          15   /* num GB pipes */
 
 typedef struct drm_radeon_getparam {
 	int param;
diff --git a/sys/dev/drm/radeon_drv.c b/sys/dev/drm/radeon_drv.c
index f22120cc3c..86f73de238 100644
--- a/sys/dev/drm/radeon_drv.c
+++ b/sys/dev/drm/radeon_drv.c
@@ -27,14 +27,13 @@
  * Authors:
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/radeon_drv.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
-#include "drm_pciids.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/radeon_drm.h"
+#include "dev/drm/radeon_drv.h"
+#include "dev/drm/drm_pciids.h"
 
 int radeon_no_wb;
 
@@ -43,66 +42,77 @@ static drm_pci_id_list_t radeon_pciidlist[] = {
 	radeon_PCI_IDS
 };
 
-static void radeon_configure(drm_device_t *dev)
+static void radeon_configure(struct drm_device *dev)
 {
-	dev->driver.buf_priv_size	= sizeof(drm_radeon_buf_priv_t);
-	dev->driver.load		= radeon_driver_load;
-	dev->driver.unload		= radeon_driver_unload;
-	dev->driver.firstopen		= radeon_driver_firstopen;
-	dev->driver.open		= radeon_driver_open;
-	dev->driver.preclose		= radeon_driver_preclose;
-	dev->driver.postclose		= radeon_driver_postclose;
-	dev->driver.lastclose		= radeon_driver_lastclose;
-	dev->driver.vblank_wait		= radeon_driver_vblank_wait;
-	dev->driver.vblank_wait2	= radeon_driver_vblank_wait2;
-	dev->driver.irq_preinstall	= radeon_driver_irq_preinstall;
-	dev->driver.irq_postinstall	= radeon_driver_irq_postinstall;
-	dev->driver.irq_uninstall	= radeon_driver_irq_uninstall;
-	dev->driver.irq_handler		= radeon_driver_irq_handler;
-	dev->driver.dma_ioctl		= radeon_cp_buffers;
-
-	dev->driver.ioctls		= radeon_ioctls;
-	dev->driver.max_ioctl		= radeon_max_ioctl;
-
-	dev->driver.name		= DRIVER_NAME;
-	dev->driver.desc		= DRIVER_DESC;
-	dev->driver.date		= DRIVER_DATE;
-	dev->driver.major		= DRIVER_MAJOR;
-	dev->driver.minor		= DRIVER_MINOR;
-	dev->driver.patchlevel		= DRIVER_PATCHLEVEL;
-
-	dev->driver.use_agp		= 1;
-	dev->driver.use_mtrr		= 1;
-	dev->driver.use_pci_dma		= 1;
-	dev->driver.use_sg		= 1;
-	dev->driver.use_dma		= 1;
-	dev->driver.use_irq		= 1;
-	dev->driver.use_vbl_irq		= 1;
-	dev->driver.use_vbl_irq2	= 1;
+	dev->driver->driver_features =
+	    DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA |
+	    DRIVER_SG | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ;
+
+	dev->driver->buf_priv_size	= sizeof(drm_radeon_buf_priv_t);
+	dev->driver->load		= radeon_driver_load;
+	dev->driver->unload		= radeon_driver_unload;
+	dev->driver->firstopen		= radeon_driver_firstopen;
+	dev->driver->open		= radeon_driver_open;
+	dev->driver->preclose		= radeon_driver_preclose;
+	dev->driver->postclose		= radeon_driver_postclose;
+	dev->driver->lastclose		= radeon_driver_lastclose;
+	dev->driver->get_vblank_counter	= radeon_get_vblank_counter;
+	dev->driver->enable_vblank	= radeon_enable_vblank;
+	dev->driver->disable_vblank	= radeon_disable_vblank;
+	dev->driver->irq_preinstall	= radeon_driver_irq_preinstall;
+	dev->driver->irq_postinstall	= radeon_driver_irq_postinstall;
+	dev->driver->irq_uninstall	= radeon_driver_irq_uninstall;
+	dev->driver->irq_handler	= radeon_driver_irq_handler;
+	dev->driver->dma_ioctl		= radeon_cp_buffers;
+
+	dev->driver->ioctls		= radeon_ioctls;
+	dev->driver->max_ioctl		= radeon_max_ioctl;
+
+	dev->driver->name		= DRIVER_NAME;
+	dev->driver->desc		= DRIVER_DESC;
+	dev->driver->date		= DRIVER_DATE;
+	dev->driver->major		= DRIVER_MAJOR;
+	dev->driver->minor		= DRIVER_MINOR;
+	dev->driver->patchlevel		= DRIVER_PATCHLEVEL;
 }
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 static int
-radeon_probe(device_t dev)
+radeon_probe(device_t kdev)
 {
-	return drm_probe(dev, radeon_pciidlist);
+	return drm_probe(kdev, radeon_pciidlist);
 }
 
 static int
-radeon_attach(device_t nbdev)
+radeon_attach(device_t kdev)
 {
-	drm_device_t *dev = device_get_softc(nbdev);
+	struct drm_device *dev = device_get_softc(kdev);
+
+	dev->driver = malloc(sizeof(struct drm_driver_info), DRM_MEM_DRIVER,
+	    M_WAITOK | M_ZERO);
 
-	bzero(dev, sizeof(drm_device_t));
 	radeon_configure(dev);
-	return drm_attach(nbdev, radeon_pciidlist);
+
+	return drm_attach(kdev, radeon_pciidlist);
+}
+
+static int
+radeon_detach(device_t kdev)
+{
+	struct drm_device *dev = device_get_softc(kdev);
+	int ret;
+
+	ret = drm_detach(kdev);
+
+	free(dev->driver, DRM_MEM_DRIVER);
+
+	return ret;
 }
 
 static device_method_t radeon_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		radeon_probe),
 	DEVMETHOD(device_attach,	radeon_attach),
-	DEVMETHOD(device_detach,	drm_detach),
+	DEVMETHOD(device_detach,	radeon_detach),
 
 	{ 0, 0 }
 };
@@ -110,7 +120,7 @@ static device_method_t radeon_methods[] = {
 static driver_t radeon_driver = {
 	"drm",
 	radeon_methods,
-	sizeof(drm_device_t)
+	sizeof(struct drm_device)
 };
 
 extern devclass_t drm_devclass;
@@ -120,12 +130,3 @@ DRIVER_MODULE(radeon, vgapci, radeon_driver, drm_devclass, 0, 0);
 DRIVER_MODULE(radeon, pci, radeon_driver, drm_devclass, 0, 0);
 #endif
 MODULE_DEPEND(radeon, drm, 1, 1, 1);
-
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-#ifdef _LKM
-CFDRIVER_DECL(radeon, DV_TTY, NULL);
-#else
-CFATTACH_DECL(radeon, sizeof(drm_device_t), drm_probe, drm_attach, drm_detach,
-    drm_activate);
-#endif
-#endif /* __FreeBSD__ || __DragonFly__ */
diff --git a/sys/dev/drm/radeon_drv.h b/sys/dev/drm/radeon_drv.h
index dd78a1084c..245e8bafb1 100644
--- a/sys/dev/drm/radeon_drv.h
+++ b/sys/dev/drm/radeon_drv.h
@@ -26,8 +26,6 @@
  * Authors:
  *    Kevin E. Martin <martin@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/radeon_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __RADEON_DRV_H__
@@ -40,7 +38,7 @@
 
 #define DRIVER_NAME		"radeon"
 #define DRIVER_DESC		"ATI Radeon"
-#define DRIVER_DATE		"20060524"
+#define DRIVER_DATE		"20080528"
 
 /* Interface history:
  *
@@ -100,10 +98,10 @@
  * 1.26- Add support for variable size PCI(E) gart aperture
  * 1.27- Add support for IGP GART
  * 1.28- Add support for VBL on CRTC2
+ * 1.29- R500 3D cmd buffer support
  */
-
 #define DRIVER_MAJOR		1
-#define DRIVER_MINOR		28
+#define DRIVER_MINOR		29
 #define DRIVER_PATCHLEVEL	0
 
 /*
@@ -124,14 +122,29 @@ enum radeon_family {
 	CHIP_RV350,
 	CHIP_RV380,
 	CHIP_R420,
+	CHIP_R423,
 	CHIP_RV410,
 	CHIP_RS400,
+	CHIP_RS480,
+	CHIP_RS600,
+	CHIP_RS690,
+	CHIP_RS740,
 	CHIP_RV515,
 	CHIP_R520,
 	CHIP_RV530,
 	CHIP_RV560,
 	CHIP_RV570,
 	CHIP_R580,
+	CHIP_R600,
+	CHIP_RV610,
+	CHIP_RV630,
+	CHIP_RV620,
+	CHIP_RV635,
+	CHIP_RV670,
+	CHIP_RS780,
+	CHIP_RV770,
+	CHIP_RV730,
+	CHIP_RV710,
 	CHIP_LAST,
 };
 
@@ -158,10 +171,6 @@ enum radeon_chip_flags {
 	RADEON_IS_IGPGART = 0x01000000UL,
 };
 
-#define GET_RING_HEAD(dev_priv)	(dev_priv->writeback_works ? \
-        DRM_READ32(  (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
-#define SET_RING_HEAD(dev_priv,val)	DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
-
 typedef struct drm_radeon_freelist {
 	unsigned int age;
 	struct drm_buf *buf;
@@ -172,8 +181,8 @@ typedef struct drm_radeon_freelist {
 typedef struct drm_radeon_ring_buffer {
 	u32 *start;
 	u32 *end;
-	int size; /* Double Words */
-	int size_l2qw; /* log2 Quad Words */
+	int size;
+	int size_l2qw;
 
 	int rptr_update; /* Double Words */
 	int rptr_update_l2qw; /* log2 Quad Words */
@@ -219,10 +228,13 @@ struct radeon_virt_surface {
 	u32 upper;
 	u32 flags;
 	struct drm_file *file_priv;
+#define PCIGART_FILE_PRIV	((void *) -1L)
 };
 
-typedef struct drm_radeon_private {
+#define RADEON_FLUSH_EMITED	(1 << 0)
+#define RADEON_PURGE_EMITED	(1 << 1)
 
+typedef struct drm_radeon_private {
 	drm_radeon_ring_buffer_t ring;
 	drm_radeon_sarea_t *sarea_priv;
 
@@ -240,7 +252,6 @@ typedef struct drm_radeon_private {
 	drm_radeon_freelist_t *head;
 	drm_radeon_freelist_t *tail;
 	int last_buf;
-	volatile u32 *scratch;
 	int writeback_works;
 
 	int usec_timeout;
@@ -283,7 +294,6 @@ typedef struct drm_radeon_private {
 	unsigned long gart_textures_offset;
 
 	drm_local_map_t *sarea;
-	drm_local_map_t *mmio;
 	drm_local_map_t *cp_ring;
 	drm_local_map_t *ring_rptr;
 	drm_local_map_t *gart_textures;
@@ -297,6 +307,7 @@ typedef struct drm_radeon_private {
 	int vblank_crtc;
 	uint32_t irq_enable_reg;
 	int irq_enabled;
+	uint32_t r500_disp_irq_reg;
 
 	struct radeon_surface surfaces[RADEON_MAX_SURFACES];
 	struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -311,6 +322,29 @@ typedef struct drm_radeon_private {
 	uint32_t flags;		/* see radeon_chip_flags */
 	unsigned long fb_aper_offset;
 
+	int num_gb_pipes;
+	int track_flush;
+	drm_local_map_t *mmio;
+
+	/* r6xx/r7xx pipe/shader config */
+	int r600_max_pipes;
+	int r600_max_tile_pipes;
+	int r600_max_simds;
+	int r600_max_backends;
+	int r600_max_gprs;
+	int r600_max_threads;
+	int r600_max_stack_entries;
+	int r600_max_hw_contexts;
+	int r600_max_gs_threads;
+	int r600_sx_max_export_size;
+	int r600_sx_max_export_pos_size;
+	int r600_sx_max_export_smx_size;
+	int r600_sq_num_cf_insts;
+	int r700_sx_num_of_sets;
+	int r700_sc_prim_fifo_size;
+	int r700_sc_hiz_tile_fifo_size;
+	int r700_sc_earlyz_tile_fifo_fize;
+
 } drm_radeon_private_t;
 
 typedef struct drm_radeon_buf_priv {
@@ -328,6 +362,12 @@ extern int radeon_no_wb;
 extern struct drm_ioctl_desc radeon_ioctls[];
 extern int radeon_max_ioctl;
 
+extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
+extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
+
+#define GET_RING_HEAD(dev_priv)	radeon_get_ring_head(dev_priv)
+#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
+
 /* Check whether the given hardware address is inside the framebuffer or the
  * GART area.
  */
@@ -354,6 +394,9 @@ extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_fi
 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
+extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
+extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
+extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
 
 extern void radeon_freelist_reset(struct drm_device * dev);
 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
@@ -362,6 +405,10 @@ extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
 
 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
 
+extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
+extern int radeon_presetup(struct drm_device *dev);
+extern int radeon_driver_postcleanup(struct drm_device *dev);
+
 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
@@ -369,34 +416,39 @@ extern void radeon_mem_takedown(struct mem_block **heap);
 extern void radeon_mem_release(struct drm_file *file_priv,
 			       struct mem_block *heap);
 
+extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
+extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
+extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
+
 				/* radeon_irq.c */
+extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
 
 extern void radeon_do_release(struct drm_device * dev);
-extern int radeon_driver_vblank_wait(struct drm_device * dev,
-				     unsigned int *sequence);
-extern int radeon_driver_vblank_wait2(struct drm_device * dev,
-				      unsigned int *sequence);
+extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
+extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
+extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
-extern void radeon_driver_irq_postinstall(struct drm_device * dev);
+extern int radeon_driver_irq_postinstall(struct drm_device *dev);
 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
+extern void radeon_enable_interrupt(struct drm_device *dev);
 extern int radeon_vblank_crtc_get(struct drm_device *dev);
 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
 
 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
 extern int radeon_driver_unload(struct drm_device *dev);
 extern int radeon_driver_firstopen(struct drm_device *dev);
-extern void radeon_driver_preclose(struct drm_device * dev,
+extern void radeon_driver_preclose(struct drm_device *dev,
 				   struct drm_file *file_priv);
-extern void radeon_driver_postclose(struct drm_device * dev,
+extern void radeon_driver_postclose(struct drm_device *dev,
 				    struct drm_file *file_priv);
 extern void radeon_driver_lastclose(struct drm_device * dev);
-extern int radeon_driver_open(struct drm_device * dev,
-			      struct drm_file * file_priv);
+extern int radeon_driver_open(struct drm_device *dev,
+			      struct drm_file *file_priv);
 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
-					 unsigned long arg);
+				unsigned long arg);
 
 /* r300_cmdbuf.c */
 extern void r300_init_reg_flags(struct drm_device *dev);
@@ -405,6 +457,21 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 			     struct drm_file *file_priv,
 			     drm_radeon_kcmd_buffer_t *cmdbuf);
 
+/* r600_cp.c */
+extern int r600_do_engine_reset(struct drm_device *dev);
+extern int r600_do_cleanup_cp(struct drm_device *dev);
+extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
+			   struct drm_file *file_priv);
+extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
+extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
+extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
+extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
+extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
+extern int r600_cp_dispatch_indirect(struct drm_device *dev,
+				     struct drm_buf *buf, int start, int end);
+extern int r600_page_table_init(struct drm_device *dev);
+extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
+
 /* Flags for stats.boxes
  */
 #define RADEON_BOX_DMA_IDLE      0x1
@@ -416,9 +483,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 /* Register definitions, register access macros and drmAddMap constants
  * for Radeon kernel driver.
  */
+#define RADEON_MM_INDEX		        0x0000
+#define RADEON_MM_DATA		        0x0004
+
 #define RADEON_AGP_COMMAND		0x0f60
-#define RADEON_AGP_COMMAND_PCI_CONFIG	0x0060	/* offset in PCI config */
-#       define RADEON_AGP_ENABLE            (1<<8)
+#define RADEON_AGP_COMMAND_PCI_CONFIG   0x0060	/* offset in PCI config */
+#	define RADEON_AGP_ENABLE	(1<<8)
 #define RADEON_AUX_SCISSOR_CNTL		0x26f0
 #	define RADEON_EXCLUSIVE_SCISSOR_0	(1 << 24)
 #	define RADEON_EXCLUSIVE_SCISSOR_1	(1 << 25)
@@ -427,14 +497,37 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #	define RADEON_SCISSOR_1_ENABLE		(1 << 29)
 #	define RADEON_SCISSOR_2_ENABLE		(1 << 30)
 
+/*
+ * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
+ * don't have an explicit bus mastering disable bit.  It's handled
+ * by the PCI D-states.  PMI_BM_DIS disables D-state bus master
+ * handling, not bus mastering itself.
+ */
 #define RADEON_BUS_CNTL			0x0030
+/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 #	define RADEON_BUS_MASTER_DIS		(1 << 6)
+/* rs600/rs690/rs740 */
+#	define RS600_BUS_MASTER_DIS		(1 << 14)
+#	define RS600_MSI_REARM		        (1 << 20)
+/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
+
+#define RADEON_BUS_CNTL1		0x0034
+#	define RADEON_PMI_BM_DIS		(1 << 2)
+#	define RADEON_PMI_INT_DIS		(1 << 3)
+
+#define RV370_BUS_CNTL			0x004c
+#	define RV370_PMI_BM_DIS		        (1 << 5)
+#	define RV370_PMI_INT_DIS		(1 << 6)
+
+#define RADEON_MSI_REARM_EN		0x0160
+/* rv370/rv380, rv410, r423/r430/r480, r5xx */
+#	define RV370_MSI_REARM_EN		(1 << 0)
 
 #define RADEON_CLOCK_CNTL_DATA		0x000c
 #	define RADEON_PLL_WR_EN			(1 << 7)
 #define RADEON_CLOCK_CNTL_INDEX		0x0008
 #define RADEON_CONFIG_APER_SIZE		0x0108
-#define RADEON_CONFIG_MEMSIZE           0x00f8
+#define RADEON_CONFIG_MEMSIZE		0x00f8
 #define RADEON_CRTC_OFFSET		0x0224
 #define RADEON_CRTC_OFFSET_CNTL		0x0228
 #	define RADEON_CRTC_TILE_EN		(1 << 15)
@@ -446,13 +539,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_PCIE_DATA                0x0034
 #define RADEON_PCIE_TX_GART_CNTL	0x10
 #	define RADEON_PCIE_TX_GART_EN		(1 << 0)
-#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
-#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1<<1)
-#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3<<1)
-#	define RADEON_PCIE_TX_GART_MODE_32_128_CACHE	(0<<3)
-#	define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE	(1<<3)
-#	define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1<<5)
-#	define RADEON_PCIE_TX_GART_INVALIDATE_TLB	(1<<8)
+#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
+#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1 << 1)
+#	define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3 << 1)
+#	define RADEON_PCIE_TX_GART_MODE_32_128_CACHE	(0 << 3)
+#	define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE	(1 << 3)
+#	define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1 << 5)
+#	define RADEON_PCIE_TX_GART_INVALIDATE_TLB	(1 << 8)
 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
 #define RADEON_PCIE_TX_GART_BASE	0x13
@@ -461,30 +554,151 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_PCIE_TX_GART_END_LO	0x16
 #define RADEON_PCIE_TX_GART_END_HI	0x17
 
-#define RADEON_IGPGART_INDEX            0x168
-#define RADEON_IGPGART_DATA             0x16c
-#define RADEON_IGPGART_UNK_18           0x18
-#define RADEON_IGPGART_CTRL             0x2b
-#define RADEON_IGPGART_BASE_ADDR        0x2c
-#define RADEON_IGPGART_FLUSH            0x2e
-#define RADEON_IGPGART_ENABLE           0x38
-#define RADEON_IGPGART_UNK_39           0x39
+#define RS480_NB_MC_INDEX               0x168
+#	define RS480_NB_MC_IND_WR_EN	(1 << 8)
+#define RS480_NB_MC_DATA                0x16c
+
+#define RS690_MC_INDEX                  0x78
+#   define RS690_MC_INDEX_MASK          0x1ff
+#   define RS690_MC_INDEX_WR_EN         (1 << 9)
+#   define RS690_MC_INDEX_WR_ACK        0x7f
+#define RS690_MC_DATA                   0x7c
+
+/* MC indirect registers */
+#define RS480_MC_MISC_CNTL              0x18
+#	define RS480_DISABLE_GTW	(1 << 1)
+/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
+#	define RS480_GART_INDEX_REG_EN	(1 << 12)
+#	define RS690_BLOCK_GFX_D3_EN	(1 << 14)
+#define RS480_K8_FB_LOCATION            0x1e
+#define RS480_GART_FEATURE_ID           0x2b
+#	define RS480_HANG_EN	        (1 << 11)
+#	define RS480_TLB_ENABLE	        (1 << 18)
+#	define RS480_P2P_ENABLE	        (1 << 19)
+#	define RS480_GTW_LAC_EN	        (1 << 25)
+#	define RS480_2LEVEL_GART	(0 << 30)
+#	define RS480_1LEVEL_GART	(1 << 30)
+#	define RS480_PDC_EN	        (1 << 31)
+#define RS480_GART_BASE                 0x2c
+#define RS480_GART_CACHE_CNTRL          0x2e
+#	define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
+#define RS480_AGP_ADDRESS_SPACE_SIZE    0x38
+#	define RS480_GART_EN	        (1 << 0)
+#	define RS480_VA_SIZE_32MB	(0 << 1)
+#	define RS480_VA_SIZE_64MB	(1 << 1)
+#	define RS480_VA_SIZE_128MB	(2 << 1)
+#	define RS480_VA_SIZE_256MB	(3 << 1)
+#	define RS480_VA_SIZE_512MB	(4 << 1)
+#	define RS480_VA_SIZE_1GB	(5 << 1)
+#	define RS480_VA_SIZE_2GB	(6 << 1)
+#define RS480_AGP_MODE_CNTL             0x39
+#	define RS480_POST_GART_Q_SIZE	(1 << 18)
+#	define RS480_NONGART_SNOOP	(1 << 19)
+#	define RS480_AGP_RD_BUF_SIZE	(1 << 20)
+#	define RS480_REQ_TYPE_SNOOP_SHIFT 22
+#	define RS480_REQ_TYPE_SNOOP_MASK  0x3
+#	define RS480_REQ_TYPE_SNOOP_DIS	(1 << 24)
+#define RS480_MC_MISC_UMA_CNTL          0x5f
+#define RS480_MC_MCLK_CNTL              0x7a
+#define RS480_MC_UMA_DUALCH_CNTL        0x86
+
+#define RS690_MC_FB_LOCATION            0x100
+#define RS690_MC_AGP_LOCATION           0x101
+#define RS690_MC_AGP_BASE               0x102
+#define RS690_MC_AGP_BASE_2             0x103
+
+#define RS600_MC_INDEX                          0x70
+#       define RS600_MC_ADDR_MASK               0xffff
+#       define RS600_MC_IND_SEQ_RBS_0           (1 << 16)
+#       define RS600_MC_IND_SEQ_RBS_1           (1 << 17)
+#       define RS600_MC_IND_SEQ_RBS_2           (1 << 18)
+#       define RS600_MC_IND_SEQ_RBS_3           (1 << 19)
+#       define RS600_MC_IND_AIC_RBS             (1 << 20)
+#       define RS600_MC_IND_CITF_ARB0           (1 << 21)
+#       define RS600_MC_IND_CITF_ARB1           (1 << 22)
+#       define RS600_MC_IND_WR_EN               (1 << 23)
+#define RS600_MC_DATA                           0x74
+
+#define RS600_MC_STATUS                         0x0
+#       define RS600_MC_IDLE                    (1 << 1)
+#define RS600_MC_FB_LOCATION                    0x4
+#define RS600_MC_AGP_LOCATION                   0x5
+#define RS600_AGP_BASE                          0x6
+#define RS600_AGP_BASE_2                        0x7
+#define RS600_MC_CNTL1                          0x9
+#       define RS600_ENABLE_PAGE_TABLES         (1 << 26)
+#define RS600_MC_PT0_CNTL                       0x100
+#       define RS600_ENABLE_PT                  (1 << 0)
+#       define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
+#       define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
+#       define RS600_INVALIDATE_ALL_L1_TLBS     (1 << 28)
+#       define RS600_INVALIDATE_L2_CACHE        (1 << 29)
+#define RS600_MC_PT0_CONTEXT0_CNTL              0x102
+#       define RS600_ENABLE_PAGE_TABLE          (1 << 0)
+#       define RS600_PAGE_TABLE_TYPE_FLAT       (0 << 1)
+#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR   0x112
+#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR  0x114
+#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
+#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR    0x12c
+#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR   0x13c
+#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR     0x14c
+#define RS600_MC_PT0_CLIENT0_CNTL               0x16c
+#       define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE       (1 << 0)
+#       define RS600_TRANSLATION_MODE_OVERRIDE              (1 << 1)
+#       define RS600_SYSTEM_ACCESS_MODE_MASK                (3 << 8)
+#       define RS600_SYSTEM_ACCESS_MODE_PA_ONLY             (0 << 8)
+#       define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP         (1 << 8)
+#       define RS600_SYSTEM_ACCESS_MODE_IN_SYS              (2 << 8)
+#       define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS          (3 << 8)
+#       define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH        (0 << 10)
+#       define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE       (1 << 10)
+#       define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
+#       define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
+#       define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
+#       define RS600_INVALIDATE_L1_TLB          (1 << 20)
 
 #define R520_MC_IND_INDEX 0x70
-#define R520_MC_IND_WR_EN (1<<24)
+#define R520_MC_IND_WR_EN (1 << 24)
 #define R520_MC_IND_DATA  0x74
 
 #define RV515_MC_FB_LOCATION 0x01
 #define RV515_MC_AGP_LOCATION 0x02
+#define RV515_MC_AGP_BASE     0x03
+#define RV515_MC_AGP_BASE_2   0x04
 
 #define R520_MC_FB_LOCATION 0x04
 #define R520_MC_AGP_LOCATION 0x05
+#define R520_MC_AGP_BASE     0x06
+#define R520_MC_AGP_BASE_2   0x07
 
 #define RADEON_MPP_TB_CONFIG		0x01c0
 #define RADEON_MEM_CNTL			0x0140
 #define RADEON_MEM_SDRAM_MODE_REG	0x0158
+#define RADEON_AGP_BASE_2		0x015c /* r200+ only */
+#define RS480_AGP_BASE_2		0x0164
 #define RADEON_AGP_BASE			0x0170
 
+/* pipe config regs */
+#define R400_GB_PIPE_SELECT             0x402c
+#define R500_DYN_SCLK_PWMEM_PIPE        0x000d /* PLL */
+#define R500_SU_REG_DEST                0x42c8
+#define R300_GB_TILE_CONFIG             0x4018
+#       define R300_ENABLE_TILING       (1 << 0)
+#       define R300_PIPE_COUNT_RV350    (0 << 1)
+#       define R300_PIPE_COUNT_R300     (3 << 1)
+#       define R300_PIPE_COUNT_R420_3P  (6 << 1)
+#       define R300_PIPE_COUNT_R420     (7 << 1)
+#       define R300_TILE_SIZE_8         (0 << 4)
+#       define R300_TILE_SIZE_16        (1 << 4)
+#       define R300_TILE_SIZE_32        (2 << 4)
+#       define R300_SUBPIXEL_1_12       (0 << 16)
+#       define R300_SUBPIXEL_1_16       (1 << 16)
+#define R300_DST_PIPE_CONFIG            0x170c
+#       define R300_PIPE_AUTO_CONFIG    (1 << 31)
+#define R300_RB2D_DSTCACHE_MODE         0x3428
+#       define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
+#       define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
+
 #define RADEON_RB3D_COLOROFFSET		0x1c40
 #define RADEON_RB3D_COLORPITCH		0x1c48
 
@@ -526,9 +740,22 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 #define RADEON_SCRATCHOFF( x )		(RADEON_SCRATCH_REG_OFFSET + 4*(x))
 
-#define GET_SCRATCH( x )	(dev_priv->writeback_works			\
-				? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
-				: RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
+extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
+
+#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
+
+#define R600_SCRATCH_REG0		0x8500
+#define R600_SCRATCH_REG1		0x8504
+#define R600_SCRATCH_REG2		0x8508
+#define R600_SCRATCH_REG3		0x850c
+#define R600_SCRATCH_REG4		0x8510
+#define R600_SCRATCH_REG5		0x8514
+#define R600_SCRATCH_REG6		0x8518
+#define R600_SCRATCH_REG7		0x851c
+#define R600_SCRATCH_UMSK		0x8540
+#define R600_SCRATCH_ADDR		0x8544
+
+#define R600_SCRATCHOFF(x)		(R600_SCRATCH_REG_OFFSET + 4*(x))
 
 #define RADEON_GEN_INT_CNTL		0x0040
 #	define RADEON_CRTC_VBLANK_MASK		(1 << 0)
@@ -545,6 +772,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #	define RADEON_SW_INT_TEST		(1 << 25)
 #	define RADEON_SW_INT_TEST_ACK		(1 << 25)
 #	define RADEON_SW_INT_FIRE		(1 << 26)
+#       define R500_DISPLAY_INT_STATUS          (1 << 0)
 
 #define RADEON_HOST_PATH_CNTL		0x0130
 #	define RADEON_HDP_SOFT_RESET		(1 << 26)
@@ -588,11 +816,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_PP_TXFILTER_1		0x1c6c
 #define RADEON_PP_TXFILTER_2		0x1c84
 
-#define RADEON_RB2D_DSTCACHE_CTLSTAT	0x342c
-#	define RADEON_RB2D_DC_FLUSH		(3 << 0)
-#	define RADEON_RB2D_DC_FREE		(3 << 2)
-#	define RADEON_RB2D_DC_FLUSH_ALL		0xf
-#	define RADEON_RB2D_DC_BUSY		(1 << 31)
+#define R300_RB2D_DSTCACHE_CTLSTAT	0x342c /* use R300_DSTCACHE_CTLSTAT */
+#define R300_DSTCACHE_CTLSTAT		0x1714
+#	define R300_RB2D_DC_FLUSH		(3 << 0)
+#	define R300_RB2D_DC_FREE		(3 << 2)
+#	define R300_RB2D_DC_FLUSH_ALL		0xf
+#	define R300_RB2D_DC_BUSY		(1 << 31)
 #define RADEON_RB3D_CNTL		0x1c3c
 #	define RADEON_ALPHA_BLEND_ENABLE	(1 << 0)
 #	define RADEON_PLANE_MASK_ENABLE		(1 << 1)
@@ -615,23 +844,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #	define RADEON_RB3D_ZC_FREE		(1 << 2)
 #	define RADEON_RB3D_ZC_FLUSH_ALL		0x5
 #	define RADEON_RB3D_ZC_BUSY		(1 << 31)
-#define RADEON_RB3D_DSTCACHE_CTLSTAT            0x325c
+#define R300_ZB_ZCACHE_CTLSTAT                  0x4f18
+#	define R300_ZC_FLUSH		        (1 << 0)
+#	define R300_ZC_FREE		        (1 << 1)
+#	define R300_ZC_BUSY		        (1 << 31)
+#define RADEON_RB3D_DSTCACHE_CTLSTAT	0x325c
 #	define RADEON_RB3D_DC_FLUSH		(3 << 0)
 #	define RADEON_RB3D_DC_FREE		(3 << 2)
 #	define RADEON_RB3D_DC_FLUSH_ALL		0xf
 #	define RADEON_RB3D_DC_BUSY		(1 << 31)
+#define R300_RB3D_DSTCACHE_CTLSTAT              0x4e4c
+#	define R300_RB3D_DC_FLUSH		(2 << 0)
+#	define R300_RB3D_DC_FREE		(2 << 2)
+#	define R300_RB3D_DC_FINISH		(1 << 4)
 #define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
 #	define RADEON_Z_TEST_MASK		(7 << 4)
 #	define RADEON_Z_TEST_ALWAYS		(7 << 4)
-#	define RADEON_Z_HIERARCHY_ENABLE        (1 << 8)
+#	define RADEON_Z_HIERARCHY_ENABLE	(1 << 8)
 #	define RADEON_STENCIL_TEST_ALWAYS	(7 << 12)
 #	define RADEON_STENCIL_S_FAIL_REPLACE	(2 << 16)
 #	define RADEON_STENCIL_ZPASS_REPLACE	(2 << 20)
 #	define RADEON_STENCIL_ZFAIL_REPLACE	(2 << 24)
-#	define RADEON_Z_COMPRESSION_ENABLE      (1 << 28)
-#	define RADEON_FORCE_Z_DIRTY             (1 << 29)
+#	define RADEON_Z_COMPRESSION_ENABLE	(1 << 28)
+#	define RADEON_FORCE_Z_DIRTY		(1 << 29)
 #	define RADEON_Z_WRITE_ENABLE		(1 << 30)
-#	define RADEON_Z_DECOMPRESSION_ENABLE    (1 << 31)
+#	define RADEON_Z_DECOMPRESSION_ENABLE	(1 << 31)
 #define RADEON_RBBM_SOFT_RESET		0x00f0
 #	define RADEON_SOFT_RESET_CP		(1 <<  0)
 #	define RADEON_SOFT_RESET_HI		(1 <<  1)
@@ -799,6 +1036,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_CP_RB_CNTL		0x0704
 #	define RADEON_BUF_SWAP_32BIT		(2 << 16)
 #	define RADEON_RB_NO_UPDATE		(1 << 27)
+#	define RADEON_RB_RPTR_WR_ENA		(1 << 31)
 #define RADEON_CP_RB_RPTR_ADDR		0x070c
 #define RADEON_CP_RB_RPTR		0x0710
 #define RADEON_CP_RB_WPTR		0x0714
@@ -820,6 +1058,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 #define RADEON_AIC_CNTL			0x01d0
 #	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)
+#	define RS400_MSI_REARM	                (1 << 3)
 #define RADEON_AIC_STAT			0x01d4
 #define RADEON_AIC_PT_BASE		0x01d8
 #define RADEON_AIC_LO_ADDR		0x01dc
@@ -837,7 +1076,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #       define RADEON_CP_NEXT_CHAR              0x00001900
 #       define RADEON_CP_PLY_NEXTSCAN           0x00001D00
 #       define RADEON_CP_SET_SCISSORS           0x00001E00
-             /* GEN_INDX_PRIM is unsupported starting with R300 */
+	     /* GEN_INDX_PRIM is unsupported starting with R300 */
 #	define RADEON_3D_RNDR_GEN_INDX_PRIM	0x00002300
 #	define RADEON_WAIT_FOR_IDLE		0x00002600
 #	define RADEON_3D_DRAW_VBUF		0x00002800
@@ -859,6 +1098,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #	define RADEON_CNTL_BITBLT_MULTI		0x00009B00
 #	define RADEON_CNTL_SET_SCISSORS		0xC0001E00
 
+#	define R600_IT_INDIRECT_BUFFER		0x00003200
+#	define R600_IT_ME_INITIALIZE		0x00004400
+#	       define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
+#	define R600_IT_EVENT_WRITE		0x00004600
+#	define R600_IT_SET_CONFIG_REG		0x00006800
+#	define R600_SET_CONFIG_REG_OFFSET       0x00008000
+#	define R600_SET_CONFIG_REG_END          0x0000ac00
+
 #define RADEON_CP_PACKET_MASK		0xC0000000
 #define RADEON_CP_PACKET_COUNT_MASK	0x3fff0000
 #define RADEON_CP_PACKET0_REG_MASK	0x000007ff
@@ -1022,42 +1269,456 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 
 #define R200_SE_TCL_POINT_SPRITE_CNTL     0x22c4
 
-#define R200_PP_TRI_PERF                  0x2cf8
+#define R200_PP_TRI_PERF 0x2cf8
 
 #define R200_PP_AFS_0                     0x2f80
-#define R200_PP_AFS_1                     0x2f00 /* same as txcblend_0 */
+#define R200_PP_AFS_1                     0x2f00	/* same as txcblend_0 */
 
 #define R200_VAP_PVS_CNTL_1               0x22D0
 
-/* MPEG settings from VHA code */
-#define RADEON_VHA_SETTO16_1                       0x2694
-#define RADEON_VHA_SETTO16_2                       0x2680
-#define RADEON_VHA_SETTO0_1                        0x1840
-#define RADEON_VHA_FB_OFFSET                       0x19e4
-#define RADEON_VHA_SETTO1AND70S                    0x19d8
-#define RADEON_VHA_DST_PITCH                       0x1408
-
-/* set as reference header */
-#define RADEON_VHA_BACKFRAME0_OFF_Y              0x1840
-#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y        0x1844
-#define RADEON_VHA_BACKFRAME0_OFF_U              0x1848
-#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U        0x184c
-#define RADOEN_VHA_BACKFRAME0_OFF_V              0x1850
-#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V        0x1854
-#define RADEON_VHA_FORWFRAME0_OFF_Y              0x1858
-#define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y        0x185c
-#define RADEON_VHA_FORWFRAME0_OFF_U              0x1860
-#define RADEON_VHA_FORWFRAME1_OFF_PITCH_U        0x1864
-#define RADEON_VHA_FORWFRAME0_OFF_V              0x1868
-#define RADEON_VHA_FORWFRAME0_OFF_PITCH_V        0x1880
-#define RADEON_VHA_BACKFRAME0_OFF_Y_2            0x1884
-#define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2      0x1888
-#define RADEON_VHA_BACKFRAME0_OFF_U_2            0x188c
-#define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2      0x1890
-#define RADEON_VHA_BACKFRAME0_OFF_V_2            0x1894
-#define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2      0x1898
-
-
+#define RADEON_CRTC_CRNT_FRAME 0x0214
+#define RADEON_CRTC2_CRNT_FRAME 0x0314
+
+#define R500_D1CRTC_STATUS 0x609c
+#define R500_D2CRTC_STATUS 0x689c
+#define R500_CRTC_V_BLANK (1<<0)
+
+#define R500_D1CRTC_FRAME_COUNT 0x60a4
+#define R500_D2CRTC_FRAME_COUNT 0x68a4
+
+#define R500_D1MODE_V_COUNTER 0x6530
+#define R500_D2MODE_V_COUNTER 0x6d30
+
+#define R500_D1MODE_VBLANK_STATUS 0x6534
+#define R500_D2MODE_VBLANK_STATUS 0x6d34
+#define R500_VBLANK_OCCURED (1<<0)
+#define R500_VBLANK_ACK     (1<<4)
+#define R500_VBLANK_STAT    (1<<12)
+#define R500_VBLANK_INT     (1<<16)
+
+#define R500_DxMODE_INT_MASK 0x6540
+#define R500_D1MODE_INT_MASK (1<<0)
+#define R500_D2MODE_INT_MASK (1<<8)
+
+#define R500_DISP_INTERRUPT_STATUS 0x7edc
+#define R500_D1_VBLANK_INTERRUPT (1 << 4)
+#define R500_D2_VBLANK_INTERRUPT (1 << 5)
+
+/* R6xx/R7xx registers */
+#define R600_MC_VM_FB_LOCATION                                 0x2180
+#define R600_MC_VM_AGP_TOP                                     0x2184
+#define R600_MC_VM_AGP_BOT                                     0x2188
+#define R600_MC_VM_AGP_BASE                                    0x218c
+#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR                    0x2190
+#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR                   0x2194
+#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR                0x2198
+
+#define R700_MC_VM_FB_LOCATION                                 0x2024
+#define R700_MC_VM_AGP_TOP                                     0x2028
+#define R700_MC_VM_AGP_BOT                                     0x202c
+#define R700_MC_VM_AGP_BASE                                    0x2030
+#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR                    0x2034
+#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR                   0x2038
+#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR                0x203c
+
+#define R600_MCD_RD_A_CNTL                                     0x219c
+#define R600_MCD_RD_B_CNTL                                     0x21a0
+
+#define R600_MCD_WR_A_CNTL                                     0x21a4
+#define R600_MCD_WR_B_CNTL                                     0x21a8
+
+#define R600_MCD_RD_SYS_CNTL                                   0x2200
+#define R600_MCD_WR_SYS_CNTL                                   0x2214
+
+#define R600_MCD_RD_GFX_CNTL                                   0x21fc
+#define R600_MCD_RD_HDP_CNTL                                   0x2204
+#define R600_MCD_RD_PDMA_CNTL                                  0x2208
+#define R600_MCD_RD_SEM_CNTL                                   0x220c
+#define R600_MCD_WR_GFX_CNTL                                   0x2210
+#define R600_MCD_WR_HDP_CNTL                                   0x2218
+#define R600_MCD_WR_PDMA_CNTL                                  0x221c
+#define R600_MCD_WR_SEM_CNTL                                   0x2220
+
+#       define R600_MCD_L1_TLB                                 (1 << 0)
+#       define R600_MCD_L1_FRAG_PROC                           (1 << 1)
+#       define R600_MCD_L1_STRICT_ORDERING                     (1 << 2)
+
+#       define R600_MCD_SYSTEM_ACCESS_MODE_MASK                (3 << 6)
+#       define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY             (0 << 6)
+#       define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP         (1 << 6)
+#       define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS              (2 << 6)
+#       define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS          (3 << 6)
+
+#       define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU    (0 << 8)
+#       define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
+
+#       define R600_MCD_SEMAPHORE_MODE                         (1 << 10)
+#       define R600_MCD_WAIT_L2_QUERY                          (1 << 11)
+#       define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x)               ((x) << 12)
+#       define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x)             ((x) << 15)
+
+#define R700_MC_VM_MD_L1_TLB0_CNTL                             0x2654
+#define R700_MC_VM_MD_L1_TLB1_CNTL                             0x2658
+#define R700_MC_VM_MD_L1_TLB2_CNTL                             0x265c
+
+#define R700_MC_VM_MB_L1_TLB0_CNTL                             0x2234
+#define R700_MC_VM_MB_L1_TLB1_CNTL                             0x2238
+#define R700_MC_VM_MB_L1_TLB2_CNTL                             0x223c
+#define R700_MC_VM_MB_L1_TLB3_CNTL                             0x2240
+
+#       define R700_ENABLE_L1_TLB                              (1 << 0)
+#       define R700_ENABLE_L1_FRAGMENT_PROCESSING              (1 << 1)
+#       define R700_SYSTEM_ACCESS_MODE_IN_SYS                  (2 << 3)
+#       define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU  (0 << 5)
+#       define R700_EFFECTIVE_L1_TLB_SIZE(x)                   ((x) << 15)
+#       define R700_EFFECTIVE_L1_QUEUE_SIZE(x)                 ((x) << 18)
+
+#define R700_MC_ARB_RAMCFG                                     0x2760
+#       define R700_NOOFBANK_SHIFT                             0
+#       define R700_NOOFBANK_MASK                              0x3
+#       define R700_NOOFRANK_SHIFT                             2
+#       define R700_NOOFRANK_MASK                              0x1
+#       define R700_NOOFROWS_SHIFT                             3
+#       define R700_NOOFROWS_MASK                              0x7
+#       define R700_NOOFCOLS_SHIFT                             6
+#       define R700_NOOFCOLS_MASK                              0x3
+#       define R700_CHANSIZE_SHIFT                             8
+#       define R700_CHANSIZE_MASK                              0x1
+#       define R700_BURSTLENGTH_SHIFT                          9
+#       define R700_BURSTLENGTH_MASK                           0x1
+#define R600_RAMCFG                                            0x2408
+#       define R600_NOOFBANK_SHIFT                             0
+#       define R600_NOOFBANK_MASK                              0x1
+#       define R600_NOOFRANK_SHIFT                             1
+#       define R600_NOOFRANK_MASK                              0x1
+#       define R600_NOOFROWS_SHIFT                             2
+#       define R600_NOOFROWS_MASK                              0x7
+#       define R600_NOOFCOLS_SHIFT                             5
+#       define R600_NOOFCOLS_MASK                              0x3
+#       define R600_CHANSIZE_SHIFT                             7
+#       define R600_CHANSIZE_MASK                              0x1
+#       define R600_BURSTLENGTH_SHIFT                          8
+#       define R600_BURSTLENGTH_MASK                           0x1
+
+#define R600_VM_L2_CNTL                                        0x1400
+#       define R600_VM_L2_CACHE_EN                             (1 << 0)
+#       define R600_VM_L2_FRAG_PROC                            (1 << 1)
+#       define R600_VM_ENABLE_PTE_CACHE_LRU_W                  (1 << 9)
+#       define R600_VM_L2_CNTL_QUEUE_SIZE(x)                   ((x) << 13)
+#       define R700_VM_L2_CNTL_QUEUE_SIZE(x)                   ((x) << 14)
+
+#define R600_VM_L2_CNTL2                                       0x1404
+#       define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS         (1 << 0)
+#       define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE            (1 << 1)
+#define R600_VM_L2_CNTL3                                       0x1408
+#       define R600_VM_L2_CNTL3_BANK_SELECT_0(x)               ((x) << 0)
+#       define R600_VM_L2_CNTL3_BANK_SELECT_1(x)               ((x) << 5)
+#       define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x)           ((x) << 10)
+#       define R700_VM_L2_CNTL3_BANK_SELECT(x)                 ((x) << 0)
+#       define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x)           ((x) << 6)
+
+#define R600_VM_L2_STATUS                                      0x140c
+
+#define R600_VM_CONTEXT0_CNTL                                  0x1410
+#       define R600_VM_ENABLE_CONTEXT                          (1 << 0)
+#       define R600_VM_PAGE_TABLE_DEPTH_FLAT                   (0 << 1)
+
+#define R600_VM_CONTEXT0_CNTL2                                 0x1430
+#define R600_VM_CONTEXT0_REQUEST_RESPONSE                      0x1470
+#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR                 0x1490
+#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR                0x14b0
+#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                  0x1574
+#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR                 0x1594
+#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR                   0x15b4
+
+#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                  0x153c
+#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR                 0x155c
+#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR                   0x157c
+
+#define R600_HDP_HOST_PATH_CNTL                                0x2c00
+
+#define R600_GRBM_CNTL                                         0x8000
+#       define R600_GRBM_READ_TIMEOUT(x)                       ((x) << 0)
+
+#define R600_GRBM_STATUS                                       0x8010
+#       define R600_CMDFIFO_AVAIL_MASK                         0x1f
+#       define R700_CMDFIFO_AVAIL_MASK                         0xf
+#       define R600_GUI_ACTIVE                                 (1 << 31)
+#define R600_GRBM_STATUS2                                      0x8014
+#define R600_GRBM_SOFT_RESET                                   0x8020
+#       define R600_SOFT_RESET_CP                              (1 << 0)
+#define R600_WAIT_UNTIL		                               0x8040
+
+#define R600_CP_SEM_WAIT_TIMER                                 0x85bc
+#define R600_CP_ME_CNTL                                        0x86d8
+#       define R600_CP_ME_HALT                                 (1 << 28)
+#define R600_CP_QUEUE_THRESHOLDS                               0x8760
+#       define R600_ROQ_IB1_START(x)                           ((x) << 0)
+#       define R600_ROQ_IB2_START(x)                           ((x) << 8)
+#define R600_CP_MEQ_THRESHOLDS                                 0x8764
+#       define R700_STQ_SPLIT(x)                               ((x) << 0)
+#       define R600_MEQ_END(x)                                 ((x) << 16)
+#       define R600_ROQ_END(x)                                 ((x) << 24)
+#define R600_CP_PERFMON_CNTL                                   0x87fc
+#define R600_CP_RB_BASE                                        0xc100
+#define R600_CP_RB_CNTL                                        0xc104
+#       define R600_RB_BUFSZ(x)                                ((x) << 0)
+#       define R600_RB_BLKSZ(x)                                ((x) << 8)
+#       define R600_RB_NO_UPDATE                               (1 << 27)
+#       define R600_RB_RPTR_WR_ENA                             (1 << 31)
+#define R600_CP_RB_RPTR_WR                                     0xc108
+#define R600_CP_RB_RPTR_ADDR                                   0xc10c
+#define R600_CP_RB_RPTR_ADDR_HI                                0xc110
+#define R600_CP_RB_WPTR                                        0xc114
+#define R600_CP_RB_WPTR_ADDR                                   0xc118
+#define R600_CP_RB_WPTR_ADDR_HI                                0xc11c
+#define R600_CP_RB_RPTR                                        0x8700
+#define R600_CP_RB_WPTR_DELAY                                  0x8704
+#define R600_CP_PFP_UCODE_ADDR                                 0xc150
+#define R600_CP_PFP_UCODE_DATA                                 0xc154
+#define R600_CP_ME_RAM_RADDR                                   0xc158
+#define R600_CP_ME_RAM_WADDR                                   0xc15c
+#define R600_CP_ME_RAM_DATA                                    0xc160
+#define R600_CP_DEBUG                                          0xc1fc
+
+#define R600_PA_CL_ENHANCE                                     0x8a14
+#       define R600_CLIP_VTX_REORDER_ENA                       (1 << 0)
+#       define R600_NUM_CLIP_SEQ(x)                            ((x) << 1)
+#define R600_PA_SC_LINE_STIPPLE_STATE                          0x8b10
+#define R600_PA_SC_MULTI_CHIP_CNTL                             0x8b20
+#define R700_PA_SC_FORCE_EOV_MAX_CNTS                          0x8b24
+#       define R700_FORCE_EOV_MAX_CLK_CNT(x)                   ((x) << 0)
+#       define R700_FORCE_EOV_MAX_REZ_CNT(x)                   ((x) << 16)
+#define R600_PA_SC_AA_SAMPLE_LOCS_2S                           0x8b40
+#define R600_PA_SC_AA_SAMPLE_LOCS_4S                           0x8b44
+#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0                       0x8b48
+#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1                       0x8b4c
+#       define R600_S0_X(x)                                    ((x) << 0)
+#       define R600_S0_Y(x)                                    ((x) << 4)
+#       define R600_S1_X(x)                                    ((x) << 8)
+#       define R600_S1_Y(x)                                    ((x) << 12)
+#       define R600_S2_X(x)                                    ((x) << 16)
+#       define R600_S2_Y(x)                                    ((x) << 20)
+#       define R600_S3_X(x)                                    ((x) << 24)
+#       define R600_S3_Y(x)                                    ((x) << 28)
+#       define R600_S4_X(x)                                    ((x) << 0)
+#       define R600_S4_Y(x)                                    ((x) << 4)
+#       define R600_S5_X(x)                                    ((x) << 8)
+#       define R600_S5_Y(x)                                    ((x) << 12)
+#       define R600_S6_X(x)                                    ((x) << 16)
+#       define R600_S6_Y(x)                                    ((x) << 20)
+#       define R600_S7_X(x)                                    ((x) << 24)
+#       define R600_S7_Y(x)                                    ((x) << 28)
+#define R600_PA_SC_FIFO_SIZE                                   0x8bd0
+#       define R600_SC_PRIM_FIFO_SIZE(x)                       ((x) << 0)
+#       define R600_SC_HIZ_TILE_FIFO_SIZE(x)                   ((x) << 8)
+#       define R600_SC_EARLYZ_TILE_FIFO_SIZE(x)                ((x) << 16)
+#define R700_PA_SC_FIFO_SIZE_R7XX                              0x8bcc
+#       define R700_SC_PRIM_FIFO_SIZE(x)                       ((x) << 0)
+#       define R700_SC_HIZ_TILE_FIFO_SIZE(x)                   ((x) << 12)
+#       define R700_SC_EARLYZ_TILE_FIFO_SIZE(x)                ((x) << 20)
+#define R600_PA_SC_ENHANCE                                     0x8bf0
+#       define R600_FORCE_EOV_MAX_CLK_CNT(x)                   ((x) << 0)
+#       define R600_FORCE_EOV_MAX_TILE_CNT(x)                  ((x) << 12)
+#define R600_PA_SC_CLIPRECT_RULE                               0x2820c
+#define R700_PA_SC_EDGERULE                                    0x28230
+#define R600_PA_SC_LINE_STIPPLE                                0x28a0c
+#define R600_PA_SC_MODE_CNTL                                   0x28a4c
+#define R600_PA_SC_AA_CONFIG                                   0x28c04
+
+#define R600_SX_EXPORT_BUFFER_SIZES                            0x900c
+#       define R600_COLOR_BUFFER_SIZE(x)                       ((x) << 0)
+#       define R600_POSITION_BUFFER_SIZE(x)                    ((x) << 8)
+#       define R600_SMX_BUFFER_SIZE(x)                         ((x) << 16)
+#define R600_SX_DEBUG_1                                        0x9054
+#       define R600_SMX_EVENT_RELEASE                          (1 << 0)
+#       define R600_ENABLE_NEW_SMX_ADDRESS                     (1 << 16)
+#define R700_SX_DEBUG_1                                        0x9058
+#       define R700_ENABLE_NEW_SMX_ADDRESS                     (1 << 16)
+#define R600_SX_MISC                                           0x28350
+
+#define R600_DB_DEBUG                                          0x9830
+#       define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE              (1 << 31)
+#define R600_DB_WATERMARKS                                     0x9838
+#       define R600_DEPTH_FREE(x)                              ((x) << 0)
+#       define R600_DEPTH_FLUSH(x)                             ((x) << 5)
+#       define R600_DEPTH_PENDING_FREE(x)                      ((x) << 15)
+#       define R600_DEPTH_CACHELINE_FREE(x)                    ((x) << 20)
+#define R700_DB_DEBUG3                                         0x98b0
+#       define R700_DB_CLK_OFF_DELAY(x)                        ((x) << 11)
+#define RV700_DB_DEBUG4                                        0x9b8c
+#       define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER          (1 << 6)
+
+#define R600_VGT_CACHE_INVALIDATION                            0x88c4
+#       define R600_CACHE_INVALIDATION(x)                      ((x) << 0)
+#       define R600_VC_ONLY                                    0
+#       define R600_TC_ONLY                                    1
+#       define R600_VC_AND_TC                                  2
+#       define R700_AUTO_INVLD_EN(x)                           ((x) << 6)
+#       define R700_NO_AUTO                                    0
+#       define R700_ES_AUTO                                    1
+#       define R700_GS_AUTO                                    2
+#       define R700_ES_AND_GS_AUTO                             3
+#define R600_VGT_GS_PER_ES                                     0x88c8
+#define R600_VGT_ES_PER_GS                                     0x88cc
+#define R600_VGT_GS_PER_VS                                     0x88e8
+#define R600_VGT_GS_VERTEX_REUSE                               0x88d4
+#define R600_VGT_NUM_INSTANCES                                 0x8974
+#define R600_VGT_STRMOUT_EN                                    0x28ab0
+#define R600_VGT_EVENT_INITIATOR                               0x28a90
+#       define R600_CACHE_FLUSH_AND_INV_EVENT                  (0x16 << 0)
+#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL                       0x28c58
+#       define R600_VTX_REUSE_DEPTH_MASK                       0xff
+#define R600_VGT_OUT_DEALLOC_CNTL                              0x28c5c
+#       define R600_DEALLOC_DIST_MASK                          0x7f
+
+#define R600_CB_COLOR0_BASE                                    0x28040
+#define R600_CB_COLOR1_BASE                                    0x28044
+#define R600_CB_COLOR2_BASE                                    0x28048
+#define R600_CB_COLOR3_BASE                                    0x2804c
+#define R600_CB_COLOR4_BASE                                    0x28050
+#define R600_CB_COLOR5_BASE                                    0x28054
+#define R600_CB_COLOR6_BASE                                    0x28058
+#define R600_CB_COLOR7_BASE                                    0x2805c
+#define R600_CB_COLOR7_FRAG                                    0x280fc
+
+#define R600_TC_CNTL                                           0x9608
+#       define R600_TC_L2_SIZE(x)                              ((x) << 5)
+#       define R600_L2_DISABLE_LATE_HIT                        (1 << 9)
+
+#define R600_ARB_POP                                           0x2418
+#       define R600_ENABLE_TC128                               (1 << 30)
+#define R600_ARB_GDEC_RD_CNTL                                  0x246c
+
+#define R600_TA_CNTL_AUX                                       0x9508
+#       define R600_DISABLE_CUBE_WRAP                          (1 << 0)
+#       define R600_DISABLE_CUBE_ANISO                         (1 << 1)
+#       define R700_GETLOD_SELECT(x)                           ((x) << 2)
+#       define R600_SYNC_GRADIENT                              (1 << 24)
+#       define R600_SYNC_WALKER                                (1 << 25)
+#       define R600_SYNC_ALIGNER                               (1 << 26)
+#       define R600_BILINEAR_PRECISION_6_BIT                   (0 << 31)
+#       define R600_BILINEAR_PRECISION_8_BIT                   (1 << 31)
+
+#define R700_TCP_CNTL                                          0x9610
+
+#define R600_SMX_DC_CTL0                                       0xa020
+#       define R700_USE_HASH_FUNCTION                          (1 << 0)
+#       define R700_CACHE_DEPTH(x)                             ((x) << 1)
+#       define R700_FLUSH_ALL_ON_EVENT                         (1 << 10)
+#       define R700_STALL_ON_EVENT                             (1 << 11)
+#define R700_SMX_EVENT_CTL                                     0xa02c
+#       define R700_ES_FLUSH_CTL(x)                            ((x) << 0)
+#       define R700_GS_FLUSH_CTL(x)                            ((x) << 3)
+#       define R700_ACK_FLUSH_CTL(x)                           ((x) << 6)
+#       define R700_SYNC_FLUSH_CTL                             (1 << 8)
+
+#define R600_SQ_CONFIG                                         0x8c00
+#       define R600_VC_ENABLE                                  (1 << 0)
+#       define R600_EXPORT_SRC_C                               (1 << 1)
+#       define R600_DX9_CONSTS                                 (1 << 2)
+#       define R600_ALU_INST_PREFER_VECTOR                     (1 << 3)
+#       define R600_DX10_CLAMP                                 (1 << 4)
+#       define R600_CLAUSE_SEQ_PRIO(x)                         ((x) << 8)
+#       define R600_PS_PRIO(x)                                 ((x) << 24)
+#       define R600_VS_PRIO(x)                                 ((x) << 26)
+#       define R600_GS_PRIO(x)                                 ((x) << 28)
+#       define R600_ES_PRIO(x)                                 ((x) << 30)
+#define R600_SQ_GPR_RESOURCE_MGMT_1                            0x8c04
+#       define R600_NUM_PS_GPRS(x)                             ((x) << 0)
+#       define R600_NUM_VS_GPRS(x)                             ((x) << 16)
+#       define R700_DYN_GPR_ENABLE                             (1 << 27)
+#       define R600_NUM_CLAUSE_TEMP_GPRS(x)                    ((x) << 28)
+#define R600_SQ_GPR_RESOURCE_MGMT_2                            0x8c08
+#       define R600_NUM_GS_GPRS(x)                             ((x) << 0)
+#       define R600_NUM_ES_GPRS(x)                             ((x) << 16)
+#define R600_SQ_THREAD_RESOURCE_MGMT                           0x8c0c
+#       define R600_NUM_PS_THREADS(x)                          ((x) << 0)
+#       define R600_NUM_VS_THREADS(x)                          ((x) << 8)
+#       define R600_NUM_GS_THREADS(x)                          ((x) << 16)
+#       define R600_NUM_ES_THREADS(x)                          ((x) << 24)
+#define R600_SQ_STACK_RESOURCE_MGMT_1                          0x8c10
+#       define R600_NUM_PS_STACK_ENTRIES(x)                    ((x) << 0)
+#       define R600_NUM_VS_STACK_ENTRIES(x)                    ((x) << 16)
+#define R600_SQ_STACK_RESOURCE_MGMT_2                          0x8c14
+#       define R600_NUM_GS_STACK_ENTRIES(x)                    ((x) << 0)
+#       define R600_NUM_ES_STACK_ENTRIES(x)                    ((x) << 16)
+#define R600_SQ_MS_FIFO_SIZES                                  0x8cf0
+#       define R600_CACHE_FIFO_SIZE(x)                         ((x) << 0)
+#       define R600_FETCH_FIFO_HIWATER(x)                      ((x) << 8)
+#       define R600_DONE_FIFO_HIWATER(x)                       ((x) << 16)
+#       define R600_ALU_UPDATE_FIFO_HIWATER(x)                 ((x) << 24)
+#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0                         0x8db0
+#       define R700_SIMDA_RING0(x)                             ((x) << 0)
+#       define R700_SIMDA_RING1(x)                             ((x) << 8)
+#       define R700_SIMDB_RING0(x)                             ((x) << 16)
+#       define R700_SIMDB_RING1(x)                             ((x) << 24)
+#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1                         0x8db4
+#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2                         0x8db8
+#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3                         0x8dbc
+#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4                         0x8dc0
+#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5                         0x8dc4
+#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6                         0x8dc8
+#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7                         0x8dcc
+
+#define R600_SPI_PS_IN_CONTROL_0                               0x286cc
+#       define R600_NUM_INTERP(x)                              ((x) << 0)
+#       define R600_POSITION_ENA                               (1 << 8)
+#       define R600_POSITION_CENTROID                          (1 << 9)
+#       define R600_POSITION_ADDR(x)                           ((x) << 10)
+#       define R600_PARAM_GEN(x)                               ((x) << 15)
+#       define R600_PARAM_GEN_ADDR(x)                          ((x) << 19)
+#       define R600_BARYC_SAMPLE_CNTL(x)                       ((x) << 26)
+#       define R600_PERSP_GRADIENT_ENA                         (1 << 28)
+#       define R600_LINEAR_GRADIENT_ENA                        (1 << 29)
+#       define R600_POSITION_SAMPLE                            (1 << 30)
+#       define R600_BARYC_AT_SAMPLE_ENA                        (1 << 31)
+#define R600_SPI_PS_IN_CONTROL_1                               0x286d0
+#       define R600_GEN_INDEX_PIX                              (1 << 0)
+#       define R600_GEN_INDEX_PIX_ADDR(x)                      ((x) << 1)
+#       define R600_FRONT_FACE_ENA                             (1 << 8)
+#       define R600_FRONT_FACE_CHAN(x)                         ((x) << 9)
+#       define R600_FRONT_FACE_ALL_BITS                        (1 << 11)
+#       define R600_FRONT_FACE_ADDR(x)                         ((x) << 12)
+#       define R600_FOG_ADDR(x)                                ((x) << 17)
+#       define R600_FIXED_PT_POSITION_ENA                      (1 << 24)
+#       define R600_FIXED_PT_POSITION_ADDR(x)                  ((x) << 25)
+#       define R700_POSITION_ULC                               (1 << 30)
+#define R600_SPI_INPUT_Z                                       0x286d8
+
+#define R600_SPI_CONFIG_CNTL                                   0x9100
+#       define R600_GPR_WRITE_PRIORITY(x)                      ((x) << 0)
+#       define R600_DISABLE_INTERP_1                           (1 << 5)
+#define R600_SPI_CONFIG_CNTL_1                                 0x913c
+#       define R600_VTX_DONE_DELAY(x)                          ((x) << 0)
+#       define R600_INTERP_ONE_PRIM_PER_ROW                    (1 << 4)
+
+#define R600_GB_TILING_CONFIG                                  0x98f0
+#       define R600_PIPE_TILING(x)                             ((x) << 1)
+#       define R600_BANK_TILING(x)                             ((x) << 4)
+#       define R600_GROUP_SIZE(x)                              ((x) << 6)
+#       define R600_ROW_TILING(x)                              ((x) << 8)
+#       define R600_BANK_SWAPS(x)                              ((x) << 11)
+#       define R600_SAMPLE_SPLIT(x)                            ((x) << 14)
+#       define R600_BACKEND_MAP(x)                             ((x) << 16)
+#define R600_DCP_TILING_CONFIG                                 0x6ca0
+#define R600_HDP_TILING_CONFIG                                 0x2f3c
+
+#define R600_CC_RB_BACKEND_DISABLE                             0x98f4
+#define R700_CC_SYS_RB_BACKEND_DISABLE                         0x3f88
+#       define R600_BACKEND_DISABLE(x)                         ((x) << 16)
+
+#define R600_CC_GC_SHADER_PIPE_CONFIG                          0x8950
+#define R600_GC_USER_SHADER_PIPE_CONFIG                        0x8954
+#       define R600_INACTIVE_QD_PIPES(x)                       ((x) << 8)
+#       define R600_INACTIVE_QD_PIPES_MASK                     (0xff << 8)
+#       define R600_INACTIVE_SIMDS(x)                          ((x) << 16)
+#       define R600_INACTIVE_SIMDS_MASK                        (0xff << 16)
+
+#define R700_CGTS_SYS_TCC_DISABLE                              0x3f90
+#define R700_CGTS_USER_SYS_TCC_DISABLE                         0x3f94
+#define R700_CGTS_TCC_DISABLE                                  0x9148
+#define R700_CGTS_USER_TCC_DISABLE                             0x914c
 
 /* Constants */
 #define RADEON_MAX_USEC_TIMEOUT		100000	/* 100 ms */
@@ -1068,6 +1729,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_LAST_SWI_REG		RADEON_SCRATCH_REG3
 #define RADEON_LAST_DISPATCH		1
 
+#define R600_LAST_FRAME_REG		R600_SCRATCH_REG0
+#define R600_LAST_DISPATCH_REG	        R600_SCRATCH_REG1
+#define R600_LAST_CLEAR_REG		R600_SCRATCH_REG2
+#define R600_LAST_SWI_REG		R600_SCRATCH_REG3
+
 #define RADEON_MAX_VB_AGE		0x7fffffff
 #define RADEON_MAX_VB_VERTS		(0xffff)
 
@@ -1076,38 +1742,70 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
 #define RADEON_PCIGART_TABLE_SIZE      (32*1024)
 
 #define RADEON_READ(reg)	DRM_READ32(  dev_priv->mmio, (reg) )
-#define RADEON_WRITE(reg,val)	DRM_WRITE32( dev_priv->mmio, (reg), (val) )
+#define RADEON_WRITE(reg, val)                                          \
+do {									\
+	if (reg < 0x10000) {				                \
+		DRM_WRITE32(dev_priv->mmio, (reg), (val));		\
+	} else {                                                        \
+		DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg));	\
+		DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val));	\
+	}                                                               \
+} while (0)
 #define RADEON_READ8(reg)	DRM_READ8(  dev_priv->mmio, (reg) )
 #define RADEON_WRITE8(reg,val)	DRM_WRITE8( dev_priv->mmio, (reg), (val) )
 
-#define RADEON_WRITE_PLL( addr, val )					\
+#define RADEON_WRITE_PLL(addr, val)					\
 do {									\
-	RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX,				\
+	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX,				\
 		       ((addr) & 0x1f) | RADEON_PLL_WR_EN );		\
-	RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) );			\
+	RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val));			\
 } while (0)
 
-#define RADEON_WRITE_IGPGART( addr, val )				\
+#define RADEON_WRITE_PCIE(addr, val)					\
 do {									\
-	RADEON_WRITE( RADEON_IGPGART_INDEX,				\
-			((addr) & 0x7f) | (1 << 8));			\
-	RADEON_WRITE( RADEON_IGPGART_DATA, (val) );			\
-	RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f );			\
+	RADEON_WRITE8(RADEON_PCIE_INDEX,				\
+			((addr) & 0xff));				\
+	RADEON_WRITE(RADEON_PCIE_DATA, (val));			\
 } while (0)
 
-#define RADEON_WRITE_PCIE( addr, val )					\
+#define R500_WRITE_MCIND(addr, val)					\
+do {								\
+	RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));	\
+	RADEON_WRITE(R520_MC_IND_DATA, (val));			\
+	RADEON_WRITE(R520_MC_IND_INDEX, 0);	\
+} while (0)
+
+#define RS480_WRITE_MCIND(addr, val)				\
 do {									\
-	RADEON_WRITE8( RADEON_PCIE_INDEX,				\
-			((addr) & 0xff));				\
-	RADEON_WRITE( RADEON_PCIE_DATA, (val) );			\
+	RADEON_WRITE(RS480_NB_MC_INDEX,				\
+			((addr) & 0xff) | RS480_NB_MC_IND_WR_EN);	\
+	RADEON_WRITE(RS480_NB_MC_DATA, (val));			\
+	RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);			\
 } while (0)
 
-#define RADEON_WRITE_MCIND( addr, val )					\
-	do {								\
-		RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));	\
-		RADEON_WRITE(R520_MC_IND_DATA, (val));			\
-		RADEON_WRITE(R520_MC_IND_INDEX, 0);	\
-	} while (0)
+#define RS690_WRITE_MCIND(addr, val)					\
+do {								\
+	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK));	\
+	RADEON_WRITE(RS690_MC_DATA, val);			\
+	RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);	\
+} while (0)
+
+#define RS600_WRITE_MCIND(addr, val)				\
+do {							        \
+	RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
+	RADEON_WRITE(RS600_MC_DATA, val);                       \
+} while (0)
+
+#define IGP_WRITE_MCIND(addr, val)				\
+do {									\
+	if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||   \
+	    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))      \
+		RS690_WRITE_MCIND(addr, val);				\
+	else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)  \
+		RS600_WRITE_MCIND(addr, val);				\
+	else								\
+		RS480_WRITE_MCIND(addr, val);				\
+} while (0)
 
 #define CP_PACKET0( reg, n )						\
 	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
@@ -1149,23 +1847,43 @@ do {									\
 } while (0)
 
 #define RADEON_FLUSH_CACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB3D_DC_FLUSH );				\
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH);				\
+	} else {                                                        \
+		OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(R300_RB3D_DC_FLUSH);				\
+	}                                                               \
 } while (0)
 
 #define RADEON_PURGE_CACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB3D_DC_FLUSH_ALL );				\
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE);	\
+	} else {                                                        \
+		OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));	\
+		OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);	\
+	}                                                               \
 } while (0)
 
 #define RADEON_FLUSH_ZCACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB3D_ZC_FLUSH );				\
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_ZC_FLUSH);				\
+	} else {                                                        \
+		OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(R300_ZC_FLUSH);				\
+	}                                                               \
 } while (0)
 
 #define RADEON_PURGE_ZCACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );				\
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {	\
+		OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE);			\
+	} else {                                                        \
+		OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));	\
+		OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE);				\
+	}                                                               \
 } while (0)
 
 /* ================================================================
@@ -1184,10 +1902,14 @@ do {									\
 } while (0)
 
 #define VB_AGE_TEST_WITH_RETURN( dev_priv )				\
-do {									\
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;		\
+do {								\
+	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;	\
 	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
-		int __ret = radeon_do_cp_idle( dev_priv );		\
+		int __ret;						\
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
+			__ret = r600_do_cp_idle(dev_priv);		\
+		else							\
+			__ret = radeon_do_cp_idle(dev_priv);		\
 		if ( __ret ) return __ret;				\
 		sarea_priv->last_dispatch = 0;				\
 		radeon_freelist_reset( dev );				\
@@ -1209,21 +1931,40 @@ do {									\
 	OUT_RING( age );						\
 } while (0)
 
+#define R600_DISPATCH_AGE(age) do {					\
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));		\
+	OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2);  \
+	OUT_RING(age);							\
+} while (0)
+
+#define R600_FRAME_AGE(age) do {					\
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));		\
+	OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2);  \
+	OUT_RING(age);							\
+} while (0)
+
+#define R600_CLEAR_AGE(age) do {					\
+	OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));		\
+	OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2);  \
+	OUT_RING(age);							\
+} while (0)
+
 /* ================================================================
  * Ring control
  */
 
 #define RADEON_VERBOSE	0
 
-#define RING_LOCALS	int write, _nr; unsigned int mask; u32 *ring;
+#define RING_LOCALS	int write, _nr, _align_nr; unsigned int mask; u32 *ring;
 
 #define BEGIN_RING( n ) do {						\
 	if ( RADEON_VERBOSE ) {						\
 		DRM_INFO( "BEGIN_RING( %d )\n", (n));			\
 	}								\
-	if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {		\
-		COMMIT_RING();						\
-		radeon_wait_ring( dev_priv, (n) * sizeof(u32) );	\
+	_align_nr = (n + 0xf) & ~0xf;					\
+	if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) {	\
+                COMMIT_RING();						\
+		radeon_wait_ring( dev_priv, _align_nr * sizeof(u32));	\
 	}								\
 	_nr = n; dev_priv->ring.space -= (n) * sizeof(u32);		\
 	ring = dev_priv->ring.start;					\
@@ -1240,19 +1981,16 @@ do {									\
 		DRM_ERROR(						\
 			"ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n",	\
 			((dev_priv->ring.tail + _nr) & mask),		\
-			write, __LINE__);						\
+			write, __LINE__);				\
 	} else								\
 		dev_priv->ring.tail = write;				\
 } while (0)
 
+extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
+
 #define COMMIT_RING() do {						\
-	/* Flush writes to ring */					\
-	DRM_MEMORYBARRIER();						\
-	GET_RING_HEAD( dev_priv );					\
-	RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );		\
-	/* read from PCI bus to ensure correct posting */		\
-	RADEON_READ( RADEON_CP_RB_RPTR );				\
-} while (0)
+		radeon_commit_ring(dev_priv);				\
+	} while(0)
 
 #define OUT_RING( x ) do {						\
 	if ( RADEON_VERBOSE ) {						\
@@ -1268,14 +2006,14 @@ do {									\
 	OUT_RING( val );						\
 } while (0)
 
-#define OUT_RING_TABLE( tab, sz ) do {				\
+#define OUT_RING_TABLE( tab, sz ) do {					\
 	int _size = (sz);					\
 	int *_tab = (int *)(tab);				\
 								\
 	if (write + _size > mask) {				\
 		int _i = (mask+1) - write;			\
 		_size -= _i;					\
-		while (_i > 0) {				\
+		while (_i > 0 ) {				\
 			*(int *)(ring + write) = *_tab++;	\
 			write++;				\
 			_i--;					\
diff --git a/sys/dev/drm/radeon_irq.c b/sys/dev/drm/radeon_irq.c
index e45f493c6c..9d4841f986 100644
--- a/sys/dev/drm/radeon_irq.c
+++ b/sys/dev/drm/radeon_irq.c
@@ -1,5 +1,5 @@
 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
-/*
+/*-
  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
  *
  * The Weather Channel (TM) funded Tungsten Graphics to develop the
@@ -28,21 +28,139 @@
  * Authors:
  *    Keith Whitwell <keith@tungstengraphics.com>
  *    Michel D�zer <michel@daenzer.net>
- *
- * $DragonFly: src/sys/dev/drm/radeon_irq.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/radeon_drm.h"
+#include "dev/drm/radeon_drv.h"
+
+void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	if (state)
+		dev_priv->irq_enable_reg |= mask;
+	else
+		dev_priv->irq_enable_reg &= ~mask;
+
+	if (dev->irq_enabled)
+		RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
+}
+
+static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	if (state)
+		dev_priv->r500_disp_irq_reg |= mask;
+	else
+		dev_priv->r500_disp_irq_reg &= ~mask;
+
+	if (dev->irq_enabled)
+		RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
+}
+
+int radeon_enable_vblank(struct drm_device *dev, int crtc)
+{
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {	
+		switch (crtc) {
+		case 0:
+			r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
+			break;
+		case 1:
+			r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
+			break;
+		default:
+			DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
+				  crtc);
+			return EINVAL;
+		}
+	} else {
+		switch (crtc) {
+		case 0:
+			radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
+			break;
+		case 1:
+			radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
+			break;
+		default:
+			DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
+				  crtc);
+			return EINVAL;
+		}
+	}
 
-static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv,
-					      u32 mask)
+	return 0;
+}
+
+void radeon_disable_vblank(struct drm_device *dev, int crtc)
 {
-	u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {	
+		switch (crtc) {
+		case 0:
+			r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
+			break;
+		case 1:
+			r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
+			break;
+		default:
+			DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
+				  crtc);
+			break;
+		}
+	} else {
+		switch (crtc) {
+		case 0:
+			radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
+			break;
+		case 1:
+			radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
+			break;
+		default:
+			DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
+				  crtc);
+			break;
+		}
+	}
+}
+
+static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
+{
+	u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
+	u32 irq_mask = RADEON_SW_INT_TEST;
+
+	*r500_disp_int = 0;
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
+		/* vbl interrupts in a different place */
+
+		if (irqs & R500_DISPLAY_INT_STATUS) {
+			/* if a display interrupt */
+			u32 disp_irq;
+
+			disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
+
+			*r500_disp_int = disp_irq;
+			if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
+				RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
+			}
+			if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
+				RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
+			}
+		}
+		irq_mask |= R500_DISPLAY_INT_STATUS;
+	} else
+		irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
+
+	irqs &=	irq_mask;
+
 	if (irqs)
 		RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
+	
 	return irqs;
 }
 
@@ -70,44 +188,62 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 	drm_radeon_private_t *dev_priv =
 	    (drm_radeon_private_t *) dev->dev_private;
 	u32 stat;
+	u32 r500_disp_int;
+	u32 tmp;
 
 	/* Only consider the bits we're interested in - others could be used
 	 * outside the DRM
 	 */
-	stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
-						  RADEON_CRTC_VBLANK_STAT |
-						  RADEON_CRTC2_VBLANK_STAT));
+	stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
 	if (!stat)
 		return IRQ_NONE;
 
 	stat &= dev_priv->irq_enable_reg;
 
 	/* SW interrupt */
-	if (stat & RADEON_SW_INT_TEST) {
+	if (stat & RADEON_SW_INT_TEST)
 		DRM_WAKEUP(&dev_priv->swi_queue);
-	}
 
 	/* VBLANK interrupt */
-	if (stat & (RADEON_CRTC_VBLANK_STAT|RADEON_CRTC2_VBLANK_STAT)) {
-		int vblank_crtc = dev_priv->vblank_crtc;
-
-		if ((vblank_crtc &
-		     (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
-		    (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
-			if (stat & RADEON_CRTC_VBLANK_STAT)
-				atomic_inc(&dev->vbl_received);
-			if (stat & RADEON_CRTC2_VBLANK_STAT)
-				atomic_inc(&dev->vbl_received2);
-		} else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
-			   (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
-			   ((stat & RADEON_CRTC2_VBLANK_STAT) &&
-			    (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
-			atomic_inc(&dev->vbl_received);
-
-		DRM_WAKEUP(&dev->vbl_queue);
-		drm_vbl_send_signals(dev);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
+		if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
+			drm_handle_vblank(dev, 0);
+		if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
+			drm_handle_vblank(dev, 1);
+	} else {
+		if (stat & RADEON_CRTC_VBLANK_STAT)
+			drm_handle_vblank(dev, 0);
+		if (stat & RADEON_CRTC2_VBLANK_STAT)
+			drm_handle_vblank(dev, 1);
+	}
+	if (dev->msi_enabled) {
+		switch(dev_priv->flags & RADEON_FAMILY_MASK) {
+			case CHIP_RS400:
+			case CHIP_RS480:
+				tmp = RADEON_READ(RADEON_AIC_CNTL) &
+				    ~RS400_MSI_REARM;
+				RADEON_WRITE(RADEON_AIC_CNTL, tmp);
+				RADEON_WRITE(RADEON_AIC_CNTL,
+				    tmp | RS400_MSI_REARM);
+				break;
+			case CHIP_RS600:
+			case CHIP_RS690:
+			case CHIP_RS740:
+				tmp = RADEON_READ(RADEON_BUS_CNTL) &
+				    ~RS600_MSI_REARM;
+				RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+				RADEON_WRITE(RADEON_BUS_CNTL, tmp |
+				    RS600_MSI_REARM);
+				break;
+			 default:
+				tmp = RADEON_READ(RADEON_MSI_REARM_EN) &
+				    ~RV370_MSI_REARM_EN;
+				RADEON_WRITE(RADEON_MSI_REARM_EN, tmp);
+				RADEON_WRITE(RADEON_MSI_REARM_EN,
+				    tmp | RV370_MSI_REARM_EN);
+				break;
+		}
 	}
-
 	return IRQ_HANDLED;
 }
 
@@ -143,57 +279,37 @@ static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
 	DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 		    RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 
+	if (ret == -ERESTART)
+		DRM_DEBUG("restarting syscall");
+
 	return ret;
 }
 
-static int radeon_driver_vblank_do_wait(struct drm_device * dev,
-					unsigned int *sequence, int crtc)
+u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
 {
-	drm_radeon_private_t *dev_priv =
-	    (drm_radeon_private_t *) dev->dev_private;
-	unsigned int cur_vblank;
-	int ret = 0;
-	int ack = 0;
-	atomic_t *counter;
+	drm_radeon_private_t *dev_priv = dev->dev_private;
+
 	if (!dev_priv) {
 		DRM_ERROR("called with no initialization\n");
 		return -EINVAL;
 	}
 
-	if (crtc == DRM_RADEON_VBLANK_CRTC1) {
-		counter = &dev->vbl_received;
-		ack |= RADEON_CRTC_VBLANK_STAT;
-	} else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
-		counter = &dev->vbl_received2;
-		ack |= RADEON_CRTC2_VBLANK_STAT;
-	} else
+	if (crtc < 0 || crtc > 1) {
+		DRM_ERROR("Invalid crtc %d\n", crtc);
 		return -EINVAL;
+	}
 
-	radeon_acknowledge_irqs(dev_priv, ack);
-
-	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
-
-	/* Assume that the user has missed the current sequence number
-	 * by about a day rather than she wants to wait for years
-	 * using vertical blanks...
-	 */
-	DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
-		    (((cur_vblank = atomic_read(counter))
-		      - *sequence) <= (1 << 23)));
-
-	*sequence = cur_vblank;
-
-	return ret;
-}
-
-int radeon_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
-{
-	return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC1);
-}
-
-int radeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
-{
-	return radeon_driver_vblank_do_wait(dev, sequence, DRM_RADEON_VBLANK_CRTC2);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
+		if (crtc == 0)
+			return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
+		else
+			return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
+	} else {
+		if (crtc == 0)
+			return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
+		else
+			return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
+	}
 }
 
 /* Needs the lock as it touches the ring.
@@ -236,38 +352,24 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr
 	return radeon_wait_irq(dev, irqwait->irq_seq);
 }
 
-static void radeon_enable_interrupt(struct drm_device *dev)
-{
-	drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
-
-	dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
-	if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1)
-		dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
-
-	if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2)
-		dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
-
-	RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
-	dev_priv->irq_enabled = 1;
-}
-
 /* drm_dma.h hooks
 */
 void radeon_driver_irq_preinstall(struct drm_device * dev)
 {
 	drm_radeon_private_t *dev_priv =
 	    (drm_radeon_private_t *) dev->dev_private;
+	u32 dummy;
 
 	/* Disable *all* interrupts */
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
+		RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 
 	/* Clear bits if they're already high */
-	radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
-					   RADEON_CRTC_VBLANK_STAT |
-					   RADEON_CRTC2_VBLANK_STAT));
+	radeon_acknowledge_irqs(dev_priv, &dummy);
 }
 
-void radeon_driver_irq_postinstall(struct drm_device * dev)
+int radeon_driver_irq_postinstall(struct drm_device * dev)
 {
 	drm_radeon_private_t *dev_priv =
 	    (drm_radeon_private_t *) dev->dev_private;
@@ -275,7 +377,11 @@ void radeon_driver_irq_postinstall(struct drm_device * dev)
 	atomic_set(&dev_priv->swi_emitted, 0);
 	DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 
-	radeon_enable_interrupt(dev);
+	dev->max_vblank_count = 0x001fffff;
+
+	radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
+
+	return 0;
 }
 
 void radeon_driver_irq_uninstall(struct drm_device * dev)
@@ -287,6 +393,8 @@ void radeon_driver_irq_uninstall(struct drm_device * dev)
 
 	dev_priv->irq_enabled = 0;
 
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
+		RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 	/* Disable *all* interrupts */
 	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 }
@@ -295,18 +403,8 @@ void radeon_driver_irq_uninstall(struct drm_device * dev)
 int radeon_vblank_crtc_get(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
-	u32 flag;
-	u32 value;
-
-	flag = RADEON_READ(RADEON_GEN_INT_CNTL);
-	value = 0;
-
-	if (flag & RADEON_CRTC_VBLANK_MASK)
-		value |= DRM_RADEON_VBLANK_CRTC1;
 
-	if (flag & RADEON_CRTC2_VBLANK_MASK)
-		value |= DRM_RADEON_VBLANK_CRTC2;
-	return value;
+	return dev_priv->vblank_crtc;
 }
 
 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
@@ -317,6 +415,5 @@ int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
 		return -EINVAL;
 	}
 	dev_priv->vblank_crtc = (unsigned int)value;
-	radeon_enable_interrupt(dev);
 	return 0;
 }
diff --git a/sys/dev/drm/radeon_mem.c b/sys/dev/drm/radeon_mem.c
index da06f10421..0c569db304 100644
--- a/sys/dev/drm/radeon_mem.c
+++ b/sys/dev/drm/radeon_mem.c
@@ -1,5 +1,5 @@
 /* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- */
-/*
+/*-
  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
  *
  * The Weather Channel (TM) funded Tungsten Graphics to develop the
@@ -27,14 +27,12 @@
  *
  * Authors:
  *    Keith Whitwell <keith@tungstengraphics.com>
- *
- * $DragonFly: src/sys/dev/drm/radeon_mem.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/radeon_drm.h"
+#include "dev/drm/radeon_drv.h"
 
 /* Very simple allocator for GART memory, working on a static range
  * already mapped into each client's address space.
@@ -90,7 +88,7 @@ static struct mem_block *alloc_block(struct mem_block *heap, int size,
 
 	list_for_each(p, heap) {
 		int start = (p->start + mask) & ~mask;
-		if (p->file_priv == 0 && start + size <= p->start + p->size)
+		if (p->file_priv == NULL && start + size <= p->start + p->size)
 			return split_block(p, start, size, file_priv);
 	}
 
@@ -115,7 +113,7 @@ static void free_block(struct mem_block *p)
 	/* Assumes a single contiguous range.  Needs a special file_priv in
 	 * 'heap' to stop it being subsumed.
 	 */
-	if (p->next->file_priv == 0) {
+	if (p->next->file_priv == NULL) {
 		struct mem_block *q = p->next;
 		p->size += q->size;
 		p->next = q->next;
@@ -123,7 +121,7 @@ static void free_block(struct mem_block *p)
 		drm_free(q, sizeof(*q), DRM_MEM_BUFS);
 	}
 
-	if (p->prev->file_priv == 0) {
+	if (p->prev->file_priv == NULL) {
 		struct mem_block *q = p->prev;
 		q->size += p->size;
 		q->next = p->next;
@@ -176,7 +174,7 @@ void radeon_mem_release(struct drm_file *file_priv, struct mem_block *heap)
 	 * 'heap' to stop it being subsumed.
 	 */
 	list_for_each(p, heap) {
-		while (p->file_priv == 0 && p->next->file_priv == 0) {
+		while (p->file_priv == NULL && p->next->file_priv == NULL) {
 			struct mem_block *q = p->next;
 			p->size += q->size;
 			p->next = q->next;
diff --git a/sys/dev/drm/radeon_microcode.h b/sys/dev/drm/radeon_microcode.h
new file mode 100644
index 0000000000..ce8bb2fbf8
--- /dev/null
+++ b/sys/dev/drm/radeon_microcode.h
@@ -0,0 +1,1844 @@
+/*-
+ * Copyright 2007 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef RADEON_MICROCODE_H
+#define RADEON_MICROCODE_H
+
+/* production radeon ucode r1xx-r6xx */
+static const u32 R100_cp_microcode[][2]={
+    { 0x21007000, 0000000000 },
+    { 0x20007000, 0000000000 },
+    { 0x000000b4, 0x00000004 },
+    { 0x000000b8, 0x00000004 },
+    { 0x6f5b4d4c, 0000000000 },
+    { 0x4c4c427f, 0000000000 },
+    { 0x5b568a92, 0000000000 },
+    { 0x4ca09c6d, 0000000000 },
+    { 0xad4c4c4c, 0000000000 },
+    { 0x4ce1af3d, 0000000000 },
+    { 0xd8afafaf, 0000000000 },
+    { 0xd64c4cdc, 0000000000 },
+    { 0x4cd10d10, 0000000000 },
+    { 0x000f0000, 0x00000016 },
+    { 0x362f242d, 0000000000 },
+    { 0x00000012, 0x00000004 },
+    { 0x000f0000, 0x00000016 },
+    { 0x362f282d, 0000000000 },
+    { 0x000380e7, 0x00000002 },
+    { 0x04002c97, 0x00000002 },
+    { 0x000f0001, 0x00000016 },
+    { 0x333a3730, 0000000000 },
+    { 0x000077ef, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000021, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000021, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000021, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00000017, 0x00000004 },
+    { 0x0003802b, 0x00000002 },
+    { 0x040067e0, 0x00000002 },
+    { 0x00000017, 0x00000004 },
+    { 0x000077e0, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x000037e1, 0x00000002 },
+    { 0x040067e1, 0x00000006 },
+    { 0x000077e0, 0x00000002 },
+    { 0x000077e1, 0x00000002 },
+    { 0x000077e1, 0x00000006 },
+    { 0xffffffff, 0000000000 },
+    { 0x10000000, 0000000000 },
+    { 0x0003802b, 0x00000002 },
+    { 0x040067e0, 0x00000006 },
+    { 0x00007675, 0x00000002 },
+    { 0x00007676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0000002f, 0x00000018 },
+    { 0x0000002f, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x00000030, 0x00000018 },
+    { 0x00000030, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x01605000, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00098000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x64c0603e, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00080000, 0x00000016 },
+    { 0000000000, 0000000000 },
+    { 0x0400251d, 0x00000002 },
+    { 0x00007580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x04002580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x00000049, 0x00000004 },
+    { 0x00005000, 0000000000 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x00019000, 0x00000002 },
+    { 0x00011055, 0x00000014 },
+    { 0x00000055, 0x00000012 },
+    { 0x0400250f, 0x00000002 },
+    { 0x0000504f, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00007565, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x00000058, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x01e655b4, 0x00000002 },
+    { 0x4401b0e4, 0x00000002 },
+    { 0x01c110e4, 0x00000002 },
+    { 0x26667066, 0x00000018 },
+    { 0x040c2565, 0x00000002 },
+    { 0x00000066, 0x00000018 },
+    { 0x04002564, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x0000005d, 0x00000004 },
+    { 0x00401069, 0x00000008 },
+    { 0x00101000, 0x00000002 },
+    { 0x000d80ff, 0x00000002 },
+    { 0x0080006c, 0x00000008 },
+    { 0x000f9000, 0x00000002 },
+    { 0x000e00ff, 0x00000002 },
+    { 0000000000, 0x00000006 },
+    { 0x0000008f, 0x00000018 },
+    { 0x0000005b, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00007576, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00009000, 0x00000002 },
+    { 0x00041000, 0x00000002 },
+    { 0x0c00350e, 0x00000002 },
+    { 0x00049000, 0x00000002 },
+    { 0x00051000, 0x00000002 },
+    { 0x01e785f8, 0x00000002 },
+    { 0x00200000, 0x00000002 },
+    { 0x0060007e, 0x0000000c },
+    { 0x00007563, 0x00000002 },
+    { 0x006075f0, 0x00000021 },
+    { 0x20007073, 0x00000004 },
+    { 0x00005073, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00007576, 0x00000002 },
+    { 0x00007577, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x0000750f, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00600083, 0x0000000c },
+    { 0x006075f0, 0x00000021 },
+    { 0x000075f8, 0x00000002 },
+    { 0x00000083, 0x00000004 },
+    { 0x000a750e, 0x00000002 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x0020750f, 0x00000002 },
+    { 0x00600086, 0x00000004 },
+    { 0x00007570, 0x00000002 },
+    { 0x00007571, 0x00000002 },
+    { 0x00007572, 0x00000006 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00005000, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00007568, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000095, 0x0000000c },
+    { 0x00058000, 0x00000002 },
+    { 0x0c607562, 0x00000002 },
+    { 0x00000097, 0x00000004 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x00600096, 0x00000004 },
+    { 0x400070e5, 0000000000 },
+    { 0x000380e6, 0x00000002 },
+    { 0x040025c5, 0x00000002 },
+    { 0x000380e5, 0x00000002 },
+    { 0x000000a8, 0x0000001c },
+    { 0x000650aa, 0x00000018 },
+    { 0x040025bb, 0x00000002 },
+    { 0x000610ab, 0x00000018 },
+    { 0x040075bc, 0000000000 },
+    { 0x000075bb, 0x00000002 },
+    { 0x000075bc, 0000000000 },
+    { 0x00090000, 0x00000006 },
+    { 0x00090000, 0x00000002 },
+    { 0x000d8002, 0x00000006 },
+    { 0x00007832, 0x00000002 },
+    { 0x00005000, 0x00000002 },
+    { 0x000380e7, 0x00000002 },
+    { 0x04002c97, 0x00000002 },
+    { 0x00007820, 0x00000002 },
+    { 0x00007821, 0x00000002 },
+    { 0x00007800, 0000000000 },
+    { 0x01200000, 0x00000002 },
+    { 0x20077000, 0x00000002 },
+    { 0x01200000, 0x00000002 },
+    { 0x20007000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x0120751b, 0x00000002 },
+    { 0x8040750a, 0x00000002 },
+    { 0x8040750b, 0x00000002 },
+    { 0x00110000, 0x00000002 },
+    { 0x000380e5, 0x00000002 },
+    { 0x000000c6, 0x0000001c },
+    { 0x000610ab, 0x00000018 },
+    { 0x844075bd, 0x00000002 },
+    { 0x000610aa, 0x00000018 },
+    { 0x840075bb, 0x00000002 },
+    { 0x000610ab, 0x00000018 },
+    { 0x844075bc, 0x00000002 },
+    { 0x000000c9, 0x00000004 },
+    { 0x804075bd, 0x00000002 },
+    { 0x800075bb, 0x00000002 },
+    { 0x804075bc, 0x00000002 },
+    { 0x00108000, 0x00000002 },
+    { 0x01400000, 0x00000002 },
+    { 0x006000cd, 0x0000000c },
+    { 0x20c07000, 0x00000020 },
+    { 0x000000cf, 0x00000012 },
+    { 0x00800000, 0x00000006 },
+    { 0x0080751d, 0x00000006 },
+    { 0000000000, 0000000000 },
+    { 0x0000775c, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00661000, 0x00000002 },
+    { 0x0460275d, 0x00000020 },
+    { 0x00004000, 0000000000 },
+    { 0x01e00830, 0x00000002 },
+    { 0x21007000, 0000000000 },
+    { 0x6464614d, 0000000000 },
+    { 0x69687420, 0000000000 },
+    { 0x00000073, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x00005000, 0x00000002 },
+    { 0x000380d0, 0x00000002 },
+    { 0x040025e0, 0x00000002 },
+    { 0x000075e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000380e0, 0x00000002 },
+    { 0x04002394, 0x00000002 },
+    { 0x00005000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x00000008, 0000000000 },
+    { 0x00000004, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R200_cp_microcode[][2]={
+    { 0x21007000, 0000000000 },
+    { 0x20007000, 0000000000 },
+    { 0x000000bf, 0x00000004 },
+    { 0x000000c3, 0x00000004 },
+    { 0x7a685e5d, 0000000000 },
+    { 0x5d5d5588, 0000000000 },
+    { 0x68659197, 0000000000 },
+    { 0x5da19f78, 0000000000 },
+    { 0x5d5d5d5d, 0000000000 },
+    { 0x5dee5d50, 0000000000 },
+    { 0xf2acacac, 0000000000 },
+    { 0xe75df9e9, 0000000000 },
+    { 0xb1dd0e11, 0000000000 },
+    { 0xe2afafaf, 0000000000 },
+    { 0x000f0000, 0x00000016 },
+    { 0x452f232d, 0000000000 },
+    { 0x00000013, 0x00000004 },
+    { 0x000f0000, 0x00000016 },
+    { 0x452f272d, 0000000000 },
+    { 0x000f0001, 0x00000016 },
+    { 0x3e4d4a37, 0000000000 },
+    { 0x000077ef, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000020, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000020, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00061000, 0x00000002 },
+    { 0x00000020, 0x0000001a },
+    { 0x00004000, 0x0000001e },
+    { 0x00000016, 0x00000004 },
+    { 0x0003802a, 0x00000002 },
+    { 0x040067e0, 0x00000002 },
+    { 0x00000016, 0x00000004 },
+    { 0x000077e0, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x000037e1, 0x00000002 },
+    { 0x040067e1, 0x00000006 },
+    { 0x000077e0, 0x00000002 },
+    { 0x000077e1, 0x00000002 },
+    { 0x000077e1, 0x00000006 },
+    { 0xffffffff, 0000000000 },
+    { 0x10000000, 0000000000 },
+    { 0x07f007f0, 0000000000 },
+    { 0x0003802a, 0x00000002 },
+    { 0x040067e0, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007675, 0x00000002 },
+    { 0x00007676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802b, 0x00000002 },
+    { 0x04002676, 0x00000002 },
+    { 0x00007677, 0x00000002 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0003802c, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002741, 0x00000002 },
+    { 0x04002743, 0x00000002 },
+    { 0x00007678, 0x00000006 },
+    { 0x0000002f, 0x00000018 },
+    { 0x0000002f, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x00000037, 0x00000018 },
+    { 0x00000037, 0x00000018 },
+    { 0000000000, 0x00000006 },
+    { 0x01605000, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00098000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x64c06051, 0x00000004 },
+    { 0x00080000, 0x00000016 },
+    { 0000000000, 0000000000 },
+    { 0x0400251d, 0x00000002 },
+    { 0x00007580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x04002580, 0x00000002 },
+    { 0x00067581, 0x00000002 },
+    { 0x0000005a, 0x00000004 },
+    { 0x00005000, 0000000000 },
+    { 0x00061000, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x00019000, 0x00000002 },
+    { 0x00011064, 0x00000014 },
+    { 0x00000064, 0x00000012 },
+    { 0x0400250f, 0x00000002 },
+    { 0x0000505e, 0x00000004 },
+    { 0x00007565, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x00000065, 0x00000004 },
+    { 0x01e655b4, 0x00000002 },
+    { 0x4401b0f0, 0x00000002 },
+    { 0x01c110f0, 0x00000002 },
+    { 0x26667071, 0x00000018 },
+    { 0x040c2565, 0x00000002 },
+    { 0x00000071, 0x00000018 },
+    { 0x04002564, 0x00000002 },
+    { 0x00007566, 0x00000002 },
+    { 0x00000068, 0x00000004 },
+    { 0x00401074, 0x00000008 },
+    { 0x00101000, 0x00000002 },
+    { 0x000d80ff, 0x00000002 },
+    { 0x00800077, 0x00000008 },
+    { 0x000f9000, 0x00000002 },
+    { 0x000e00ff, 0x00000002 },
+    { 0000000000, 0x00000006 },
+    { 0x00000094, 0x00000018 },
+    { 0x00000068, 0x00000004 },
+    { 0x00007576, 0x00000002 },
+    { 0x00065000, 0x00000002 },
+    { 0x00009000, 0x00000002 },
+    { 0x00041000, 0x00000002 },
+    { 0x0c00350e, 0x00000002 },
+    { 0x00049000, 0x00000002 },
+    { 0x00051000, 0x00000002 },
+    { 0x01e785f8, 0x00000002 },
+    { 0x00200000, 0x00000002 },
+    { 0x00600087, 0x0000000c },
+    { 0x00007563, 0x00000002 },
+    { 0x006075f0, 0x00000021 },
+    { 0x2000707c, 0x00000004 },
+    { 0x0000507c, 0x00000004 },
+    { 0x00007576, 0x00000002 },
+    { 0x00007577, 0x00000002 },
+    { 0x0000750e, 0x00000002 },
+    { 0x0000750f, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x0060008a, 0x0000000c },
+    { 0x006075f0, 0x00000021 },
+    { 0x000075f8, 0x00000002 },
+    { 0x0000008a, 0x00000004 },
+    { 0x000a750e, 0x00000002 },
+    { 0x0020750f, 0x00000002 },
+    { 0x0060008d, 0x00000004 },
+    { 0x00007570, 0x00000002 },
+    { 0x00007571, 0x00000002 },
+    { 0x00007572, 0x00000006 },
+    { 0x00005000, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00007568, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x00000098, 0x0000000c },
+    { 0x00058000, 0x00000002 },
+    { 0x0c607562, 0x00000002 },
+    { 0x0000009a, 0x00000004 },
+    { 0x00600099, 0x00000004 },
+    { 0x400070f1, 0000000000 },
+    { 0x000380f1, 0x00000002 },
+    { 0x000000a7, 0x0000001c },
+    { 0x000650a9, 0x00000018 },
+    { 0x040025bb, 0x00000002 },
+    { 0x000610aa, 0x00000018 },
+    { 0x040075bc, 0000000000 },
+    { 0x000075bb, 0x00000002 },
+    { 0x000075bc, 0000000000 },
+    { 0x00090000, 0x00000006 },
+    { 0x00090000, 0x00000002 },
+    { 0x000d8002, 0x00000006 },
+    { 0x00005000, 0x00000002 },
+    { 0x00007821, 0x00000002 },
+    { 0x00007800, 0000000000 },
+    { 0x00007821, 0x00000002 },
+    { 0x00007800, 0000000000 },
+    { 0x01665000, 0x00000002 },
+    { 0x000a0000, 0x00000002 },
+    { 0x000671cc, 0x00000002 },
+    { 0x0286f1cd, 0x00000002 },
+    { 0x000000b7, 0x00000010 },
+    { 0x21007000, 0000000000 },
+    { 0x000000be, 0x0000001c },
+    { 0x00065000, 0x00000002 },
+    { 0x000a0000, 0x00000002 },
+    { 0x00061000, 0x00000002 },
+    { 0x000b0000, 0x00000002 },
+    { 0x38067000, 0x00000002 },
+    { 0x000a00ba, 0x00000004 },
+    { 0x20007000, 0000000000 },
+    { 0x01200000, 0x00000002 },
+    { 0x20077000, 0x00000002 },
+    { 0x01200000, 0x00000002 },
+    { 0x20007000, 0000000000 },
+    { 0x00061000, 0x00000002 },
+    { 0x0120751b, 0x00000002 },
+    { 0x8040750a, 0x00000002 },
+    { 0x8040750b, 0x00000002 },
+    { 0x00110000, 0x00000002 },
+    { 0x000380f1, 0x00000002 },
+    { 0x000000d1, 0x0000001c },
+    { 0x000610aa, 0x00000018 },
+    { 0x844075bd, 0x00000002 },
+    { 0x000610a9, 0x00000018 },
+    { 0x840075bb, 0x00000002 },
+    { 0x000610aa, 0x00000018 },
+    { 0x844075bc, 0x00000002 },
+    { 0x000000d4, 0x00000004 },
+    { 0x804075bd, 0x00000002 },
+    { 0x800075bb, 0x00000002 },
+    { 0x804075bc, 0x00000002 },
+    { 0x00108000, 0x00000002 },
+    { 0x01400000, 0x00000002 },
+    { 0x006000d8, 0x0000000c },
+    { 0x20c07000, 0x00000020 },
+    { 0x000000da, 0x00000012 },
+    { 0x00800000, 0x00000006 },
+    { 0x0080751d, 0x00000006 },
+    { 0x000025bb, 0x00000002 },
+    { 0x000040d4, 0x00000004 },
+    { 0x0000775c, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00661000, 0x00000002 },
+    { 0x0460275d, 0x00000020 },
+    { 0x00004000, 0000000000 },
+    { 0x00007999, 0x00000002 },
+    { 0x00a05000, 0x00000002 },
+    { 0x00661000, 0x00000002 },
+    { 0x0460299b, 0x00000020 },
+    { 0x00004000, 0000000000 },
+    { 0x01e00830, 0x00000002 },
+    { 0x21007000, 0000000000 },
+    { 0x00005000, 0x00000002 },
+    { 0x00038056, 0x00000002 },
+    { 0x040025e0, 0x00000002 },
+    { 0x000075e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000380ed, 0x00000002 },
+    { 0x04007394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000078c4, 0x00000002 },
+    { 0x000078c5, 0x00000002 },
+    { 0x000078c6, 0x00000002 },
+    { 0x00007924, 0x00000002 },
+    { 0x00007925, 0x00000002 },
+    { 0x00007926, 0x00000002 },
+    { 0x000000f2, 0x00000004 },
+    { 0x00007924, 0x00000002 },
+    { 0x00007925, 0x00000002 },
+    { 0x00007926, 0x00000002 },
+    { 0x000000f9, 0x00000004 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R300_cp_microcode[][2]={
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x000000ae, 0x00000008 },
+    { 0x000000b2, 0x00000008 },
+    { 0x67554b4a, 0000000000 },
+    { 0x4a4a4475, 0000000000 },
+    { 0x55527d83, 0000000000 },
+    { 0x4a8c8b65, 0000000000 },
+    { 0x4aef4af6, 0000000000 },
+    { 0x4ae14a4a, 0000000000 },
+    { 0xe4979797, 0000000000 },
+    { 0xdb4aebdd, 0000000000 },
+    { 0x9ccc4a4a, 0000000000 },
+    { 0xd1989898, 0000000000 },
+    { 0x4a0f9ad6, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000080, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00012000, 0x00000004 },
+    { 0x00082000, 0x00000004 },
+    { 0x1800650e, 0x00000004 },
+    { 0x00092000, 0x00000004 },
+    { 0x000a2000, 0x00000004 },
+    { 0x000f0000, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x00000074, 0x00000018 },
+    { 0x0000e563, 0x00000004 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0000a069, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000077, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000077, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0007a, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000084, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000086, 0x00000008 },
+    { 0x00c00085, 0x00000008 },
+    { 0x000700e3, 0x00000004 },
+    { 0x00000092, 0x00000038 },
+    { 0x000ca094, 0x00000030 },
+    { 0x080045bb, 0x00000004 },
+    { 0x000c2095, 0x00000030 },
+    { 0x0800e5bc, 0000000000 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x00120000, 0x0000000c },
+    { 0x00120000, 0x00000004 },
+    { 0x001b0002, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x000000a4, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x000000a1, 0x00000008 },
+    { 0x000000a6, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x000000ad, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x001400a9, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700e3, 0x00000004 },
+    { 0x000000c0, 0x00000038 },
+    { 0x000c2095, 0x00000030 },
+    { 0x0880e5bd, 0x00000005 },
+    { 0x000c2094, 0x00000030 },
+    { 0x0800e5bb, 0x00000005 },
+    { 0x000c2095, 0x00000030 },
+    { 0x0880e5bc, 0x00000005 },
+    { 0x000000c3, 0x00000008 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000c7, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000c9, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080c3, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700e0, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000e4, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000eb, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000f3, 0x00000034 },
+    { 0x000000f0, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R420_cp_microcode[][2]={
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x00000099, 0x00000008 },
+    { 0x0000009d, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0xd9d3dff6, 0000000000 },
+    { 0x4ac54a4a, 0000000000 },
+    { 0xc8828282, 0000000000 },
+    { 0xbf4acfc1, 0000000000 },
+    { 0x87b04a4a, 0000000000 },
+    { 0xb5838383, 0000000000 },
+    { 0x4a0f85ba, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700c7, 0x00000004 },
+    { 0x00000080, 0x00000038 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x0000008f, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x0000008c, 0x00000008 },
+    { 0x00000091, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x00000098, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x00140094, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700c7, 0x00000004 },
+    { 0x000000a4, 0x00000038 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000ab, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000ad, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080a7, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700c4, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000c8, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000cf, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000d7, 0x00000034 },
+    { 0x000000d4, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0x0000e1cc, 0x00000004 },
+    { 0x0500e1cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000de, 0x00000034 },
+    { 0x000000da, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x0019e1cc, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x0500a000, 0x00000004 },
+    { 0x080041cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 RS600_cp_microcode[][2]={
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x000000a0, 0x00000008 },
+    { 0x000000a4, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0x4ae74af6, 0000000000 },
+    { 0x4ad34a4a, 0000000000 },
+    { 0xd6898989, 0000000000 },
+    { 0xcd4addcf, 0000000000 },
+    { 0x8ebe4ae2, 0000000000 },
+    { 0xc38a8a8a, 0000000000 },
+    { 0x4a0f8cc8, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700d5, 0x00000004 },
+    { 0x00000084, 0x00000038 },
+    { 0x000ca086, 0x00000030 },
+    { 0x080045bb, 0x00000004 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0800e5bc, 0000000000 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x00120000, 0x0000000c },
+    { 0x00120000, 0x00000004 },
+    { 0x001b0002, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x00000096, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x00000093, 0x00000008 },
+    { 0x00000098, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000009f, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x0014009b, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700d5, 0x00000004 },
+    { 0x000000b2, 0x00000038 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bd, 0x00000005 },
+    { 0x000c2086, 0x00000030 },
+    { 0x0800e5bb, 0x00000005 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bc, 0x00000005 },
+    { 0x000000b5, 0x00000008 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000b9, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000bb, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080b5, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700d2, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000d6, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000dd, 0x00000008 },
+    { 0x00e00116, 0000000000 },
+    { 0x000700e1, 0x00000004 },
+    { 0x0800401c, 0x00000004 },
+    { 0x200050e7, 0x00000004 },
+    { 0x0000e01d, 0x00000004 },
+    { 0x000000e4, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000eb, 0x00000034 },
+    { 0x000000e8, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 RS690_cp_microcode[][2]={
+    { 0x000000dd, 0x00000008 },
+    { 0x000000df, 0x00000008 },
+    { 0x000000a0, 0x00000008 },
+    { 0x000000a4, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0x4ad74af6, 0000000000 },
+    { 0x4ac94a4a, 0000000000 },
+    { 0xcc898989, 0000000000 },
+    { 0xc34ad3c5, 0000000000 },
+    { 0x8e4a4a4a, 0000000000 },
+    { 0x4a8a8a8a, 0000000000 },
+    { 0x4a0f8c4a, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000f041, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000f184, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000f185, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000f186, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000f187, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700cb, 0x00000004 },
+    { 0x00000084, 0x00000038 },
+    { 0x000ca086, 0x00000030 },
+    { 0x080045bb, 0x00000004 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0800e5bc, 0000000000 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x00120000, 0x0000000c },
+    { 0x00120000, 0x00000004 },
+    { 0x001b0002, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x00000096, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x00000093, 0x00000008 },
+    { 0x00000098, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000009f, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x0014009b, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x00100000, 0x0000002c },
+    { 0x00004000, 0000000000 },
+    { 0x080045c8, 0x00000004 },
+    { 0x00240005, 0x00000004 },
+    { 0x08004d0b, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700cb, 0x00000004 },
+    { 0x000000b7, 0x00000038 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bd, 0x00000005 },
+    { 0x000c2086, 0x00000030 },
+    { 0x0800e5bb, 0x00000005 },
+    { 0x000c2087, 0x00000030 },
+    { 0x0880e5bc, 0x00000005 },
+    { 0x000000ba, 0x00000008 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000be, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000c0, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080ba, 0x00000008 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700c8, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000cc, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000d3, 0x00000008 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000db, 0x00000034 },
+    { 0x000000d8, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0x000000e1, 0x00000030 },
+    { 0x4200e000, 0000000000 },
+    { 0x000000e1, 0x00000030 },
+    { 0x4000e000, 0000000000 },
+    { 0x0025001b, 0x00000004 },
+    { 0x00230000, 0x00000004 },
+    { 0x00250005, 0x00000004 },
+    { 0x000000e6, 0x00000034 },
+    { 0000000000, 0x0000000c },
+    { 0x00244000, 0x00000004 },
+    { 0x080045c8, 0x00000004 },
+    { 0x00240005, 0x00000004 },
+    { 0x08004d0b, 0x0000000c },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+static const u32 R520_cp_microcode[][2]={
+    { 0x4200e000, 0000000000 },
+    { 0x4000e000, 0000000000 },
+    { 0x00000099, 0x00000008 },
+    { 0x0000009d, 0x00000008 },
+    { 0x4a554b4a, 0000000000 },
+    { 0x4a4a4467, 0000000000 },
+    { 0x55526f75, 0000000000 },
+    { 0x4a7e7d65, 0000000000 },
+    { 0xe0dae6f6, 0000000000 },
+    { 0x4ac54a4a, 0000000000 },
+    { 0xc8828282, 0000000000 },
+    { 0xbf4acfc1, 0000000000 },
+    { 0x87b04ad5, 0000000000 },
+    { 0xb5838383, 0000000000 },
+    { 0x4a0f85ba, 0000000000 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000d0012, 0x00000038 },
+    { 0x0000e8b4, 0x00000004 },
+    { 0x000d0014, 0x00000038 },
+    { 0x0000e8b6, 0x00000004 },
+    { 0x000d0016, 0x00000038 },
+    { 0x0000e854, 0x00000004 },
+    { 0x000d0018, 0x00000038 },
+    { 0x0000e855, 0x00000004 },
+    { 0x000d001a, 0x00000038 },
+    { 0x0000e856, 0x00000004 },
+    { 0x000d001c, 0x00000038 },
+    { 0x0000e857, 0x00000004 },
+    { 0x000d001e, 0x00000038 },
+    { 0x0000e824, 0x00000004 },
+    { 0x000d0020, 0x00000038 },
+    { 0x0000e825, 0x00000004 },
+    { 0x000d0022, 0x00000038 },
+    { 0x0000e830, 0x00000004 },
+    { 0x000d0024, 0x00000038 },
+    { 0x0000f0c0, 0x00000004 },
+    { 0x000d0026, 0x00000038 },
+    { 0x0000f0c1, 0x00000004 },
+    { 0x000d0028, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d002a, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d002c, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d002e, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d0030, 0x00000038 },
+    { 0x0000e000, 0x00000004 },
+    { 0x000d0032, 0x00000038 },
+    { 0x0000f180, 0x00000004 },
+    { 0x000d0034, 0x00000038 },
+    { 0x0000f393, 0x00000004 },
+    { 0x000d0036, 0x00000038 },
+    { 0x0000f38a, 0x00000004 },
+    { 0x000d0038, 0x00000038 },
+    { 0x0000f38e, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000043, 0x00000018 },
+    { 0x00cce800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x08004800, 0x00000004 },
+    { 0x0000003a, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x2000451d, 0x00000004 },
+    { 0x0000e580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x08004580, 0x00000004 },
+    { 0x000ce581, 0x00000004 },
+    { 0x00000047, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x00032000, 0x00000004 },
+    { 0x00022051, 0x00000028 },
+    { 0x00000051, 0x00000024 },
+    { 0x0800450f, 0x00000004 },
+    { 0x0000a04b, 0x00000008 },
+    { 0x0000e565, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000052, 0x00000008 },
+    { 0x03cca5b4, 0x00000004 },
+    { 0x05432000, 0x00000004 },
+    { 0x00022000, 0x00000004 },
+    { 0x4ccce05e, 0x00000030 },
+    { 0x08274565, 0x00000004 },
+    { 0x0000005e, 0x00000030 },
+    { 0x08004564, 0x00000004 },
+    { 0x0000e566, 0x00000004 },
+    { 0x00000055, 0x00000008 },
+    { 0x00802061, 0x00000010 },
+    { 0x00202000, 0x00000004 },
+    { 0x001b00ff, 0x00000004 },
+    { 0x01000064, 0x00000010 },
+    { 0x001f2000, 0x00000004 },
+    { 0x001c00ff, 0x00000004 },
+    { 0000000000, 0x0000000c },
+    { 0x00000072, 0x00000030 },
+    { 0x00000055, 0x00000008 },
+    { 0x0000e576, 0x00000004 },
+    { 0x0000e577, 0x00000004 },
+    { 0x0000e50e, 0x00000004 },
+    { 0x0000e50f, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00000069, 0x00000018 },
+    { 0x00c0e5f9, 0x000000c2 },
+    { 0x00000069, 0x00000008 },
+    { 0x0014e50e, 0x00000004 },
+    { 0x0040e50f, 0x00000004 },
+    { 0x00c0006c, 0x00000008 },
+    { 0x0000e570, 0x00000004 },
+    { 0x0000e571, 0x00000004 },
+    { 0x0000e572, 0x0000000c },
+    { 0x0000a000, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x0000e568, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00000076, 0x00000018 },
+    { 0x000b0000, 0x00000004 },
+    { 0x18c0e562, 0x00000004 },
+    { 0x00000078, 0x00000008 },
+    { 0x00c00077, 0x00000008 },
+    { 0x000700c7, 0x00000004 },
+    { 0x00000080, 0x00000038 },
+    { 0x0000e5bb, 0x00000004 },
+    { 0x0000e5bc, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e800, 0000000000 },
+    { 0x0000e821, 0x00000004 },
+    { 0x0000e82e, 0000000000 },
+    { 0x02cca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000ce1cc, 0x00000004 },
+    { 0x050de1cd, 0x00000004 },
+    { 0x00400000, 0x00000004 },
+    { 0x0000008f, 0x00000018 },
+    { 0x00c0a000, 0x00000004 },
+    { 0x0000008c, 0x00000008 },
+    { 0x00000091, 0x00000020 },
+    { 0x4200e000, 0000000000 },
+    { 0x00000098, 0x00000038 },
+    { 0x000ca000, 0x00000004 },
+    { 0x00140000, 0x00000004 },
+    { 0x000c2000, 0x00000004 },
+    { 0x00160000, 0x00000004 },
+    { 0x700ce000, 0x00000004 },
+    { 0x00140094, 0x00000008 },
+    { 0x4000e000, 0000000000 },
+    { 0x02400000, 0x00000004 },
+    { 0x400ee000, 0x00000004 },
+    { 0x02400000, 0x00000004 },
+    { 0x4000e000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x0240e51b, 0x00000004 },
+    { 0x0080e50a, 0x00000005 },
+    { 0x0080e50b, 0x00000005 },
+    { 0x00220000, 0x00000004 },
+    { 0x000700c7, 0x00000004 },
+    { 0x000000a4, 0x00000038 },
+    { 0x0080e5bd, 0x00000005 },
+    { 0x0000e5bb, 0x00000005 },
+    { 0x0080e5bc, 0x00000005 },
+    { 0x00210000, 0x00000004 },
+    { 0x02800000, 0x00000004 },
+    { 0x00c000ab, 0x00000018 },
+    { 0x4180e000, 0x00000040 },
+    { 0x000000ad, 0x00000024 },
+    { 0x01000000, 0x0000000c },
+    { 0x0100e51d, 0x0000000c },
+    { 0x000045bb, 0x00000004 },
+    { 0x000080a7, 0x00000008 },
+    { 0x0000f3ce, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053cf, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f3d2, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c053d3, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x0000f39d, 0x00000004 },
+    { 0x0140a000, 0x00000004 },
+    { 0x00cc2000, 0x00000004 },
+    { 0x08c0539e, 0x00000040 },
+    { 0x00008000, 0000000000 },
+    { 0x03c00830, 0x00000004 },
+    { 0x4200e000, 0000000000 },
+    { 0x0000a000, 0x00000004 },
+    { 0x200045e0, 0x00000004 },
+    { 0x0000e5e1, 0000000000 },
+    { 0x00000001, 0000000000 },
+    { 0x000700c4, 0x00000004 },
+    { 0x0800e394, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x0000e8c4, 0x00000004 },
+    { 0x0000e8c5, 0x00000004 },
+    { 0x0000e8c6, 0x00000004 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000c8, 0x00000008 },
+    { 0x0000e928, 0x00000004 },
+    { 0x0000e929, 0x00000004 },
+    { 0x0000e92a, 0x00000004 },
+    { 0x000000cf, 0x00000008 },
+    { 0xdeadbeef, 0000000000 },
+    { 0x00000116, 0000000000 },
+    { 0x000700d3, 0x00000004 },
+    { 0x080050e7, 0x00000004 },
+    { 0x000700d4, 0x00000004 },
+    { 0x0800401c, 0x00000004 },
+    { 0x0000e01d, 0000000000 },
+    { 0x02c02000, 0x00000004 },
+    { 0x00060000, 0x00000004 },
+    { 0x000000de, 0x00000034 },
+    { 0x000000db, 0x00000008 },
+    { 0x00008000, 0x00000004 },
+    { 0xc000e000, 0000000000 },
+    { 0x0000e1cc, 0x00000004 },
+    { 0x0500e1cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000e5, 0x00000034 },
+    { 0x000000e1, 0x00000008 },
+    { 0x0000a000, 0000000000 },
+    { 0x0019e1cc, 0x00000004 },
+    { 0x001b0001, 0x00000004 },
+    { 0x0500a000, 0x00000004 },
+    { 0x080041cd, 0x00000004 },
+    { 0x000ca000, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0x000c2000, 0x00000004 },
+    { 0x001d0018, 0x00000004 },
+    { 0x001a0001, 0x00000004 },
+    { 0x000000fb, 0x00000034 },
+    { 0x0000004a, 0x00000008 },
+    { 0x0500a04a, 0x00000008 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+    { 0000000000, 0000000000 },
+};
+
+
+#endif
diff --git a/sys/dev/drm/radeon_state.c b/sys/dev/drm/radeon_state.c
index f2044ee618..e7c5c5e43a 100644
--- a/sys/dev/drm/radeon_state.c
+++ b/sys/dev/drm/radeon_state.c
@@ -1,5 +1,4 @@
-/* radeon_state.c -- State support for Radeon -*- linux-c -*- */
-/*
+/*-
  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
  * All Rights Reserved.
  *
@@ -25,15 +24,13 @@
  * Authors:
  *    Gareth Hughes <gareth@valinux.com>
  *    Kevin E. Martin <martin@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/radeon_state.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "drm_sarea.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/drm_sarea.h"
+#include "dev/drm/radeon_drm.h"
+#include "dev/drm/radeon_drv.h"
 
 /* ================================================================
  * Helper functions for client state checking and fixup
@@ -42,7 +39,7 @@
 static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
 						    dev_priv,
 						    struct drm_file *file_priv,
-						    u32 * offset)
+						    u32 *offset)
 {
 	u64 off = *offset;
 	u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
@@ -792,7 +789,7 @@ static void radeon_clear_box(drm_radeon_private_t * dev_priv,
 	ADVANCE_RING();
 }
 
-static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv)
+static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv)
 {
 	/* Collapse various things into a wait flag -- trying to
 	 * guess if userspase slept -- better just to have them tell us.
@@ -866,7 +863,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
 
 	dev_priv->stats.clears++;
 
-	if (dev_priv->sarea_priv->pfCurrentPage == 1) {
+	if (sarea_priv->pfCurrentPage == 1) {
 		unsigned int tmp = flags;
 
 		flags &= ~(RADEON_FRONT | RADEON_BACK);
@@ -892,7 +889,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
 
 		/* Make sure we restore the 3D state next time.
 		 */
-		dev_priv->sarea_priv->ctx_owner = 0;
+		sarea_priv->ctx_owner = 0;
 
 		for (i = 0; i < nbox; i++) {
 			int x = pbox[i].x1;
@@ -969,7 +966,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
 		/* Make sure we restore the 3D state next time.
 		 * we haven't touched any "normal" state - still need this?
 		 */
-		dev_priv->sarea_priv->ctx_owner = 0;
+		sarea_priv->ctx_owner = 0;
 
 		if ((dev_priv->flags & RADEON_HAS_HIERZ)
 		    && (flags & RADEON_USE_HIERZ)) {
@@ -1216,7 +1213,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
 
 		/* Make sure we restore the 3D state next time.
 		 */
-		dev_priv->sarea_priv->ctx_owner = 0;
+		sarea_priv->ctx_owner = 0;
 
 		for (i = 0; i < nbox; i++) {
 
@@ -1287,7 +1284,7 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
 
 		/* Make sure we restore the 3D state next time.
 		 */
-		dev_priv->sarea_priv->ctx_owner = 0;
+		sarea_priv->ctx_owner = 0;
 
 		for (i = 0; i < nbox; i++) {
 
@@ -1330,17 +1327,17 @@ static void radeon_cp_dispatch_clear(struct drm_device * dev,
 	 * wait on this value before performing the clear ioctl.  We
 	 * need this because the card's so damned fast...
 	 */
-	dev_priv->sarea_priv->last_clear++;
+	sarea_priv->last_clear++;
 
 	BEGIN_RING(4);
 
-	RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear);
+	RADEON_CLEAR_AGE(sarea_priv->last_clear);
 	RADEON_WAIT_UNTIL_IDLE();
 
 	ADVANCE_RING();
 }
 
-static void radeon_cp_dispatch_swap(struct drm_device * dev)
+static void radeon_cp_dispatch_swap(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
@@ -1387,7 +1384,7 @@ static void radeon_cp_dispatch_swap(struct drm_device * dev)
 		/* Make this work even if front & back are flipped:
 		 */
 		OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
-		if (dev_priv->sarea_priv->pfCurrentPage == 0) {
+		if (sarea_priv->pfCurrentPage == 0) {
 			OUT_RING(dev_priv->back_pitch_offset);
 			OUT_RING(dev_priv->front_pitch_offset);
 		} else {
@@ -1407,20 +1404,20 @@ static void radeon_cp_dispatch_swap(struct drm_device * dev)
 	 * throttle the framerate by waiting for this value before
 	 * performing the swapbuffer ioctl.
 	 */
-	dev_priv->sarea_priv->last_frame++;
+	sarea_priv->last_frame++;
 
 	BEGIN_RING(4);
 
-	RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame);
+	RADEON_FRAME_AGE(sarea_priv->last_frame);
 	RADEON_WAIT_UNTIL_2D_IDLE();
 
 	ADVANCE_RING();
 }
 
-static void radeon_cp_dispatch_flip(struct drm_device * dev)
+static void radeon_cp_dispatch_flip(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
-	struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle;
+	struct drm_sarea *sarea = (struct drm_sarea *)dev_priv->sarea->handle;
 	int offset = (dev_priv->sarea_priv->pfCurrentPage == 1)
 	    ? dev_priv->front_offset : dev_priv->back_offset;
 	RING_LOCALS;
@@ -1541,7 +1538,7 @@ static void radeon_cp_dispatch_vertex(struct drm_device * dev,
 	} while (i < nbox);
 }
 
-static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
+static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_buf *buf)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
@@ -1550,9 +1547,15 @@ static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * b
 	buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
 
 	/* Emit the vertex buffer age */
-	BEGIN_RING(2);
-	RADEON_DISPATCH_AGE(buf_priv->age);
-	ADVANCE_RING();
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
+		BEGIN_RING(3);
+		R600_DISPATCH_AGE(buf_priv->age);
+		ADVANCE_RING();
+	} else {
+		BEGIN_RING(2);
+		RADEON_DISPATCH_AGE(buf_priv->age);
+		ADVANCE_RING();
+	}
 
 	buf->pending = 1;
 	buf->used = 0;
@@ -1592,7 +1595,7 @@ static void radeon_cp_dispatch_indirect(struct drm_device * dev,
 	}
 }
 
-static void radeon_cp_dispatch_indices(struct drm_device * dev,
+static void radeon_cp_dispatch_indices(struct drm_device *dev,
 				       struct drm_buf * elt_buf,
 				       drm_radeon_tcl_prim_t * prim)
 {
@@ -1664,7 +1667,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
 	u32 height;
 	int i;
 	u32 texpitch, microtile;
-	u32 offset;
+	u32 offset, byte_offset;
 	RING_LOCALS;
 
 	if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
@@ -1729,6 +1732,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
 	} else
 		microtile = 0;
 
+	/* this might fail for zero-sized uploads - are those illegal? */
+	if (!radeon_check_offset(dev_priv, tex->offset + image->height *
+				blit_width - 1)) {
+		DRM_ERROR("Invalid final destination offset\n");
+		return -EINVAL;
+	}
+
 	DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
 
 	do {
@@ -1842,6 +1852,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
 		}
 
 #undef RADEON_COPY_MT
+		byte_offset = (image->y & ~2047) * blit_width;
 		buf->file_priv = file_priv;
 		buf->used = size;
 		offset = dev_priv->gart_buffers_offset + buf->offset;
@@ -1856,9 +1867,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev,
 			 RADEON_DP_SRC_SOURCE_MEMORY |
 			 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
 		OUT_RING((spitch << 22) | (offset >> 10));
-		OUT_RING((texpitch << 22) | (tex->offset >> 10));
+		OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
 		OUT_RING(0);
-		OUT_RING((image->x << 16) | image->y);
+		OUT_RING((image->x << 16) | (image->y % 2048));
 		OUT_RING((image->width << 16) | height);
 		RADEON_WAIT_UNTIL_2D_IDLE();
 		ADVANCE_RING();
@@ -2084,11 +2095,6 @@ static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_f
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_surface_alloc_t *alloc = data;
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
-
 	if (alloc_surface(alloc, dev_priv, file_priv) == -1)
 		return -EINVAL;
 	else
@@ -2100,11 +2106,6 @@ static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_fi
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_surface_free_t *memfree = data;
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
-
 	if (free_surface(file_priv, dev_priv, memfree->address))
 		return -EINVAL;
 	else
@@ -2138,7 +2139,7 @@ static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *
 
 /* Not sure why this isn't set all the time:
  */
-static int radeon_do_init_pageflip(struct drm_device * dev)
+static int radeon_do_init_pageflip(struct drm_device *dev)
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	RING_LOCALS;
@@ -2188,6 +2189,7 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
+
 	DRM_DEBUG("\n");
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
@@ -2198,7 +2200,7 @@ static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *f
 		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
 
 	radeon_cp_dispatch_swap(dev);
-	dev_priv->sarea_priv->ctx_owner = 0;
+	sarea_priv->ctx_owner = 0;
 
 	COMMIT_RING();
 	return 0;
@@ -2215,11 +2217,6 @@ static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
-
 	sarea_priv = dev_priv->sarea_priv;
 
 	DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
@@ -2274,7 +2271,7 @@ static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file
 		prim.finish = vertex->count;	/* unused */
 		prim.prim = vertex->prim;
 		prim.numverts = vertex->count;
-		prim.vc_format = dev_priv->sarea_priv->vc_format;
+		prim.vc_format = sarea_priv->vc_format;
 
 		radeon_cp_dispatch_vertex(dev, buf, &prim);
 	}
@@ -2299,10 +2296,6 @@ static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
 	sarea_priv = dev_priv->sarea_priv;
 
 	DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
@@ -2370,7 +2363,7 @@ static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file
 	prim.prim = elts->prim;
 	prim.offset = 0;	/* offset from start of dma buffers */
 	prim.numverts = RADEON_MAX_VB_VERTS;	/* duh */
-	prim.vc_format = dev_priv->sarea_priv->vc_format;
+	prim.vc_format = sarea_priv->vc_format;
 
 	radeon_cp_dispatch_indices(dev, buf, &prim);
 	if (elts->discard) {
@@ -2475,24 +2468,25 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
 
 	buf->used = indirect->end;
 
-	/* Wait for the 3D stream to idle before the indirect buffer
-	 * containing 2D acceleration commands is processed.
-	 */
-	BEGIN_RING(2);
-
-	RADEON_WAIT_UNTIL_3D_IDLE();
-
-	ADVANCE_RING();
-
 	/* Dispatch the indirect buffer full of commands from the
 	 * X server.  This is insecure and is thus only available to
 	 * privileged clients.
 	 */
-	radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
-	if (indirect->discard) {
-		radeon_cp_discard_buffer(dev, buf);
+	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+		r600_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
+	else {
+		/* Wait for the 3D stream to idle before the indirect buffer
+		 * containing 2D acceleration commands is processed.
+		 */
+		BEGIN_RING(2);
+		RADEON_WAIT_UNTIL_3D_IDLE();
+		ADVANCE_RING();
+		radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
 	}
 
+	if (indirect->discard)
+		radeon_cp_discard_buffer(dev, buf);
+
 	COMMIT_RING();
 	return 0;
 }
@@ -2509,11 +2503,6 @@ static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
-
 	sarea_priv = dev_priv->sarea_priv;
 
 	DRM_DEBUG("pid=%d index=%d discard=%d\n",
@@ -2704,10 +2693,10 @@ static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
 	int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
 	RING_LOCALS;
 
-	if (!sz)
-		return 0;
-	if (sz * 4 > cmdbuf->bufsz)
-		return -EINVAL;
+        if (!sz)
+                return 0;
+        if (sz * 4 > cmdbuf->bufsz)
+                return -EINVAL;
 
 	BEGIN_RING(5 + sz);
 	OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
@@ -2852,11 +2841,6 @@ static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file
 
 	LOCK_TEST_WITH_RETURN(dev, file_priv);
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
-
 	RING_SPACE_TEST_WITH_RETURN(dev_priv);
 	VB_AGE_TEST_WITH_RETURN(dev_priv);
 
@@ -3013,11 +2997,6 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
 	drm_radeon_getparam_t *param = data;
 	int value;
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
-
 	DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
 
 	switch (param->param) {
@@ -3026,14 +3005,14 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
 		break;
 	case RADEON_PARAM_LAST_FRAME:
 		dev_priv->stats.last_frame_reads++;
-		value = GET_SCRATCH(0);
+		value = GET_SCRATCH(dev_priv, 0);
 		break;
 	case RADEON_PARAM_LAST_DISPATCH:
-		value = GET_SCRATCH(1);
+		value = GET_SCRATCH(dev_priv, 1);
 		break;
 	case RADEON_PARAM_LAST_CLEAR:
 		dev_priv->stats.last_clear_reads++;
-		value = GET_SCRATCH(2);
+		value = GET_SCRATCH(dev_priv, 2);
 		break;
 	case RADEON_PARAM_IRQ_NR:
 		value = dev->irq;
@@ -3068,9 +3047,11 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
 	case RADEON_PARAM_SCRATCH_OFFSET:
 		if (!dev_priv->writeback_works)
 			return -EINVAL;
-		value = RADEON_SCRATCH_REG_OFFSET;
+		if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
+			value = R600_SCRATCH_REG_OFFSET;
+		else
+			value = RADEON_SCRATCH_REG_OFFSET;
 		break;
-
 	case RADEON_PARAM_CARD_TYPE:
 		if (dev_priv->flags & RADEON_IS_PCIE)
 			value = RADEON_CARD_PCIE;
@@ -3085,8 +3066,11 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
 	case RADEON_PARAM_FB_LOCATION:
 		value = radeon_read_fb_location(dev_priv);
 		break;
+	case RADEON_PARAM_NUM_GB_PIPES:
+		value = dev_priv->num_gb_pipes;
+		break;
 	default:
-		DRM_DEBUG( "Invalid parameter %d\n", param->param );
+		DRM_DEBUG("Invalid parameter %d\n", param->param);
 		return -EINVAL;
 	}
 
@@ -3104,11 +3088,6 @@ static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_fil
 	drm_radeon_setparam_t *sp = data;
 	struct drm_radeon_driver_file_fields *radeon_priv;
 
-	if (!dev_priv) {
-		DRM_ERROR("called with no initialization\n");
-		return -EINVAL;
-	}
-
 	switch (sp->param) {
 	case RADEON_SETPARAM_FB_LOCATION:
 		radeon_priv = file_priv->driver_priv;
@@ -3120,12 +3099,14 @@ static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_fil
 			DRM_DEBUG("color tiling disabled\n");
 			dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
 			dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
-			dev_priv->sarea_priv->tiling_enabled = 0;
+			if (dev_priv->sarea_priv)
+				dev_priv->sarea_priv->tiling_enabled = 0;
 		} else if (sp->value == 1) {
 			DRM_DEBUG("color tiling enabled\n");
 			dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
 			dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
-			dev_priv->sarea_priv->tiling_enabled = 1;
+			if (dev_priv->sarea_priv)
+				dev_priv->sarea_priv->tiling_enabled = 1;
 		}
 		break;
 	case RADEON_SETPARAM_PCIGART_LOCATION:
@@ -3158,8 +3139,7 @@ static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_fil
  *
  * DRM infrastructure takes care of reclaiming dma buffers.
  */
-void radeon_driver_preclose(struct drm_device *dev,
-			    struct drm_file *file_priv)
+void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
 {
 	if (dev->dev_private) {
 		drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -3172,14 +3152,7 @@ void radeon_driver_preclose(struct drm_device *dev,
 
 void radeon_driver_lastclose(struct drm_device *dev)
 {
-	if (dev->dev_private) {
-		drm_radeon_private_t *dev_priv = dev->dev_private;
-
-		if (dev_priv->sarea_priv &&
-		    dev_priv->sarea_priv->pfCurrentPage != 0)
-			radeon_cp_dispatch_flip(dev);
-	}
-
+	radeon_surfaces_release(PCIGART_FILE_PRIV, dev->dev_private);
 	radeon_do_release(dev);
 }
 
@@ -3228,7 +3201,7 @@ struct drm_ioctl_desc radeon_ioctls[] = {
 	DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
-	DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+	DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_ROOT_ONLY),
 	DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
 	DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
diff --git a/sys/dev/drm/savage_bci.c b/sys/dev/drm/savage_bci.c
index 16f7df64e5..9dcf4f768b 100644
--- a/sys/dev/drm/savage_bci.c
+++ b/sys/dev/drm/savage_bci.c
@@ -21,12 +21,11 @@
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/savage_bci.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
-#include "drmP.h"
-#include "savage_drm.h"
-#include "savage_drv.h"
+
+#include "dev/drm/drmP.h"
+#include "dev/drm/savage_drm.h"
+#include "dev/drm/savage_drv.h"
 
 /* Need a long timeout for shadow status updates can take a while
  * and so can waiting for events when the queue is full. */
diff --git a/sys/dev/drm/savage_drm.h b/sys/dev/drm/savage_drm.h
index 72a9b48553..b960d5573a 100644
--- a/sys/dev/drm/savage_drm.h
+++ b/sys/dev/drm/savage_drm.h
@@ -21,8 +21,6 @@
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/savage_drm.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __SAVAGE_DRM_H__
diff --git a/sys/dev/drm/savage_drv.c b/sys/dev/drm/savage_drv.c
index c7edb60f1f..97783de409 100644
--- a/sys/dev/drm/savage_drv.c
+++ b/sys/dev/drm/savage_drv.c
@@ -24,69 +24,81 @@
  *
  * Authors:
  *    Eric Anholt <anholt@FreeBSD.org>
- *
- * $DragonFly: src/sys/dev/drm/savage_drv.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "savage_drm.h"
-#include "savage_drv.h"
-#include "drm_pciids.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/savage_drm.h"
+#include "dev/drm/savage_drv.h"
+#include "dev/drm/drm_pciids.h"
 
 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
 static drm_pci_id_list_t savage_pciidlist[] = {
 	savage_PCI_IDS
 };
 
-static void savage_configure(drm_device_t *dev)
+static void savage_configure(struct drm_device *dev)
 {
-	dev->driver.buf_priv_size	= sizeof(drm_savage_buf_priv_t);
-	dev->driver.load		= savage_driver_load;
-	dev->driver.firstopen		= savage_driver_firstopen;
-	dev->driver.lastclose		= savage_driver_lastclose;
-	dev->driver.unload		= savage_driver_unload;
-	dev->driver.reclaim_buffers_locked = savage_reclaim_buffers;
-	dev->driver.dma_ioctl		= savage_bci_buffers;
-
-	dev->driver.ioctls		= savage_ioctls;
-	dev->driver.max_ioctl		= savage_max_ioctl;
-
-	dev->driver.name		= DRIVER_NAME;
-	dev->driver.desc		= DRIVER_DESC;
-	dev->driver.date		= DRIVER_DATE;
-	dev->driver.major		= DRIVER_MAJOR;
-	dev->driver.minor		= DRIVER_MINOR;
-	dev->driver.patchlevel		= DRIVER_PATCHLEVEL;
-
-	dev->driver.use_agp		= 1;
-	dev->driver.use_mtrr		= 1;
-	dev->driver.use_pci_dma		= 1;
-	dev->driver.use_dma		= 1;
+	dev->driver->driver_features =
+	    DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA |
+	    DRIVER_HAVE_DMA;
+
+	dev->driver->buf_priv_size	= sizeof(drm_savage_buf_priv_t);
+	dev->driver->load		= savage_driver_load;
+	dev->driver->firstopen		= savage_driver_firstopen;
+	dev->driver->lastclose		= savage_driver_lastclose;
+	dev->driver->unload		= savage_driver_unload;
+	dev->driver->reclaim_buffers_locked = savage_reclaim_buffers;
+	dev->driver->dma_ioctl		= savage_bci_buffers;
+
+	dev->driver->ioctls		= savage_ioctls;
+	dev->driver->max_ioctl		= savage_max_ioctl;
+
+	dev->driver->name		= DRIVER_NAME;
+	dev->driver->desc		= DRIVER_DESC;
+	dev->driver->date		= DRIVER_DATE;
+	dev->driver->major		= DRIVER_MAJOR;
+	dev->driver->minor		= DRIVER_MINOR;
+	dev->driver->patchlevel		= DRIVER_PATCHLEVEL;
 }
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 static int
-savage_probe(device_t dev)
+savage_probe(device_t kdev)
 {
-	return drm_probe(dev, savage_pciidlist);
+	return drm_probe(kdev, savage_pciidlist);
 }
 
 static int
-savage_attach(device_t nbdev)
+savage_attach(device_t kdev)
 {
-	drm_device_t *dev = device_get_softc(nbdev);
+	struct drm_device *dev = device_get_softc(kdev);
+
+	dev->driver = malloc(sizeof(struct drm_driver_info), DRM_MEM_DRIVER,
+	    M_WAITOK | M_ZERO);
 
-	bzero(dev, sizeof(drm_device_t));
 	savage_configure(dev);
-	return drm_attach(nbdev, savage_pciidlist);
+
+	return drm_attach(kdev, savage_pciidlist);
+}
+
+static int
+savage_detach(device_t kdev)
+{
+	struct drm_device *dev = device_get_softc(kdev);
+	int ret;
+
+	ret = drm_detach(kdev);
+
+	free(dev->driver, DRM_MEM_DRIVER);
+
+	return ret;
 }
 
 static device_method_t savage_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		savage_probe),
 	DEVMETHOD(device_attach,	savage_attach),
-	DEVMETHOD(device_detach,	drm_detach),
+	DEVMETHOD(device_detach,	savage_detach),
 
 	{ 0, 0 }
 };
@@ -94,7 +106,7 @@ static device_method_t savage_methods[] = {
 static driver_t savage_driver = {
 	"drm",
 	savage_methods,
-	sizeof(drm_device_t)
+	sizeof(struct drm_device)
 };
 
 extern devclass_t drm_devclass;
@@ -104,7 +116,3 @@ DRIVER_MODULE(savage, vgapci, savage_driver, drm_devclass, 0, 0);
 DRIVER_MODULE(savage, pci, savage_driver, drm_devclass, 0, 0);
 #endif
 MODULE_DEPEND(savage, drm, 1, 1, 1);
-
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-CFDRIVER_DECL(savage, DV_TTY, NULL);
-#endif
diff --git a/sys/dev/drm/savage_drv.h b/sys/dev/drm/savage_drv.h
index 183dd2e1c2..9d5b8b395e 100644
--- a/sys/dev/drm/savage_drv.h
+++ b/sys/dev/drm/savage_drv.h
@@ -1,5 +1,5 @@
 /* savage_drv.h -- Private header for the savage driver */
-/*
+/*-
  * Copyright 2004  Felix Kuehling
  * All Rights Reserved.
  *
@@ -21,8 +21,6 @@
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/savage_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __SAVAGE_DRV_H__
diff --git a/sys/dev/drm/savage_state.c b/sys/dev/drm/savage_state.c
index e152e18e77..ac0bc3de6e 100644
--- a/sys/dev/drm/savage_state.c
+++ b/sys/dev/drm/savage_state.c
@@ -21,12 +21,11 @@
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * $DragonFly: src/sys/dev/drm/savage_state.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
-#include "drmP.h"
-#include "savage_drm.h"
-#include "savage_drv.h"
+
+#include "dev/drm/drmP.h"
+#include "dev/drm/savage_drm.h"
+#include "dev/drm/savage_drv.h"
 
 void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv,
 			       const struct drm_clip_rect *pbox)
diff --git a/sys/dev/drm/sis_drm.h b/sys/dev/drm/sis_drm.h
index 66fd626f19..319ee6d10e 100644
--- a/sys/dev/drm/sis_drm.h
+++ b/sys/dev/drm/sis_drm.h
@@ -1,5 +1,5 @@
 /* sis_drv.h -- Private header for sis driver -*- linux-c -*- */
-/*
+/*-
  * Copyright 2005 Eric Anholt
  * All Rights Reserved.
  *
@@ -22,7 +22,6 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
- * $DragonFly: src/sys/dev/drm/sis_drm.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __SIS_DRM_H__
diff --git a/sys/dev/drm/sis_drv.c b/sys/dev/drm/sis_drv.c
index ee802d051e..eb087369a4 100644
--- a/sys/dev/drm/sis_drv.c
+++ b/sys/dev/drm/sis_drv.c
@@ -24,61 +24,75 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  *
- * $DragonFly: src/sys/dev/drm/sis_drv.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "sis_drm.h"
-#include "sis_drv.h"
-#include "drm_pciids.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/sis_drm.h"
+#include "dev/drm/sis_drv.h"
+#include "dev/drm/drm_pciids.h"
 
 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
 static drm_pci_id_list_t sis_pciidlist[] = {
 	sis_PCI_IDS
 };
 
-static void sis_configure(drm_device_t *dev)
+static void sis_configure(struct drm_device *dev)
 {
-	dev->driver.buf_priv_size	= 1; /* No dev_priv */
-	dev->driver.context_ctor	= sis_init_context;
-	dev->driver.context_dtor	= sis_final_context;
-
-	dev->driver.ioctls		= sis_ioctls;
-	dev->driver.max_ioctl		= sis_max_ioctl;
-
-	dev->driver.name		= DRIVER_NAME;
-	dev->driver.desc		= DRIVER_DESC;
-	dev->driver.date		= DRIVER_DATE;
-	dev->driver.major		= DRIVER_MAJOR;
-	dev->driver.minor		= DRIVER_MINOR;
-	dev->driver.patchlevel		= DRIVER_PATCHLEVEL;
-
-	dev->driver.use_agp		= 1;
-	dev->driver.use_mtrr		= 1;
+	dev->driver->driver_features =
+	    DRIVER_USE_AGP | DRIVER_USE_MTRR;
+
+	dev->driver->buf_priv_size	= 1; /* No dev_priv */
+	dev->driver->context_ctor	= sis_init_context;
+	dev->driver->context_dtor	= sis_final_context;
+
+	dev->driver->ioctls		= sis_ioctls;
+	dev->driver->max_ioctl		= sis_max_ioctl;
+
+	dev->driver->name		= DRIVER_NAME;
+	dev->driver->desc		= DRIVER_DESC;
+	dev->driver->date		= DRIVER_DATE;
+	dev->driver->major		= DRIVER_MAJOR;
+	dev->driver->minor		= DRIVER_MINOR;
+	dev->driver->patchlevel		= DRIVER_PATCHLEVEL;
 }
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 static int
-sis_probe(device_t dev)
+sis_probe(device_t kdev)
 {
-	return drm_probe(dev, sis_pciidlist);
+	return drm_probe(kdev, sis_pciidlist);
 }
 
 static int
-sis_attach(device_t nbdev)
+sis_attach(device_t kdev)
 {
-	drm_device_t *dev = device_get_softc(nbdev);
+	struct drm_device *dev = device_get_softc(kdev);
+
+	dev->driver = malloc(sizeof(struct drm_driver_info), DRM_MEM_DRIVER,
+	    M_WAITOK | M_ZERO);
 
-	bzero(dev, sizeof(drm_device_t));
 	sis_configure(dev);
-	return drm_attach(nbdev, sis_pciidlist);
+
+	return drm_attach(kdev, sis_pciidlist);
+}
+
+static int
+sis_detach(device_t kdev)
+{
+	struct drm_device *dev = device_get_softc(kdev);
+	int ret;
+
+	ret = drm_detach(kdev);
+
+	free(dev->driver, DRM_MEM_DRIVER);
+
+	return ret;
 }
 
 static device_method_t sis_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		sis_probe),
 	DEVMETHOD(device_attach,	sis_attach),
-	DEVMETHOD(device_detach,	drm_detach),
+	DEVMETHOD(device_detach,	sis_detach),
 
 	{ 0, 0 }
 };
@@ -86,7 +100,7 @@ static device_method_t sis_methods[] = {
 static driver_t sis_driver = {
 	"drm",
 	sis_methods,
-	sizeof(drm_device_t)
+	sizeof(struct drm_device)
 };
 
 extern devclass_t drm_devclass;
@@ -96,12 +110,3 @@ DRIVER_MODULE(sisdrm, vgapci, sis_driver, drm_devclass, 0, 0);
 DRIVER_MODULE(sisdrm, pci, sis_driver, drm_devclass, 0, 0);
 #endif
 MODULE_DEPEND(sisdrm, drm, 1, 1, 1);
-
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-#ifdef _LKM
-CFDRIVER_DECL(sis, DV_TTY, NULL);
-#else
-CFATTACH_DECL(sis, sizeof(drm_device_t), drm_probe, drm_attach, drm_detach,
-    drm_activate);
-#endif
-#endif
diff --git a/sys/dev/drm/sis_drv.h b/sys/dev/drm/sis_drv.h
index e59a2b8bd2..879cc0cef2 100644
--- a/sys/dev/drm/sis_drv.h
+++ b/sys/dev/drm/sis_drv.h
@@ -1,5 +1,5 @@
 /* sis_drv.h -- Private header for sis driver -*- linux-c -*- */
-/*
+/*-
  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All rights reserved.
@@ -23,7 +23,6 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  *
- * $DragonFly: src/sys/dev/drm/sis_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef _SIS_DRV_H_
@@ -50,7 +49,7 @@ enum sis_family {
 #endif
 
 #ifdef SIS_HAVE_CORE_MM
-#include "drm_sman.h"
+#include "dev/drm/drm_sman.h"
 
 #define SIS_BASE (dev_priv->mmio)
 #define SIS_READ(reg)	 DRM_READ32(SIS_BASE, reg);
@@ -73,7 +72,7 @@ extern void sis_reclaim_buffers_locked(struct drm_device *dev,
 extern void sis_lastclose(struct drm_device *dev);
 
 #else
-#include "sis_ds.h"
+#include "dev/drm/sis_ds.h"
 
 typedef struct drm_sis_private {
 	memHeap_t *AGPHeap;
diff --git a/sys/dev/drm/sis_ds.c b/sys/dev/drm/sis_ds.c
index 623fa0e2c9..4002ce3458 100644
--- a/sys/dev/drm/sis_ds.c
+++ b/sys/dev/drm/sis_ds.c
@@ -26,12 +26,11 @@
  * Authors:
  *    Sung-Ching Lin <sclin@sis.com.tw>
  *
- * $DragonFly: src/sys/dev/drm/sis_ds.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "drmP.h"
-#include "drm.h"
-#include "sis_ds.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm.h"
+#include "dev/drm/sis_ds.h"
 
 /* Set Data Structure, not check repeated value
  * temporarily used
diff --git a/sys/dev/drm/sis_ds.h b/sys/dev/drm/sis_ds.h
index 5012d26ea3..7f5c533f73 100644
--- a/sys/dev/drm/sis_ds.h
+++ b/sys/dev/drm/sis_ds.h
@@ -1,7 +1,7 @@
 /* sis_ds.h -- Private header for Direct Rendering Manager -*- linux-c -*-
  * Created: Mon Jan  4 10:05:05 1999 by sclin@sis.com.tw
  */
-/*
+/*-
  * Copyright 2000 Silicon Integrated Systems Corp, Inc., HsinChu, Taiwan.
  * All rights reserved.
  *
@@ -27,7 +27,6 @@
  * Authors:
  *    Sung-Ching Lin <sclin@sis.com.tw>
  *
- * $DragonFly: src/sys/dev/drm/sis_ds.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __SIS_DS_H__
diff --git a/sys/dev/drm/sis_mm.c b/sys/dev/drm/sis_mm.c
index b24d47c0ab..d8a0e0bcae 100644
--- a/sys/dev/drm/sis_mm.c
+++ b/sys/dev/drm/sis_mm.c
@@ -26,7 +26,6 @@
  * Authors:
  *    Sung-Ching Lin <sclin@sis.com.tw>
  *
- * $DragonFly: src/sys/dev/drm/sis_mm.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #if defined(__linux__) && defined(CONFIG_FB_SIS)
@@ -36,10 +35,10 @@
 #include <linux/sisfb.h>
 #endif
 #endif
-#include "drmP.h"
-#include "sis_drm.h"
-#include "sis_drv.h"
-#include "sis_ds.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/sis_drm.h"
+#include "dev/drm/sis_drv.h"
+#include "dev/drm/sis_ds.h"
 
 #define MAX_CONTEXT 100
 #define VIDEO_TYPE 0
diff --git a/sys/dev/drm/tdfx_drv.c b/sys/dev/drm/tdfx_drv.c
index 8794a4259a..d023aa6bfa 100644
--- a/sys/dev/drm/tdfx_drv.c
+++ b/sys/dev/drm/tdfx_drv.c
@@ -30,56 +30,71 @@
  *    Daryll Strauss <daryll@valinux.com>
  *    Gareth Hughes <gareth@valinux.com>
  *
- * $DragonFly: src/sys/dev/drm/tdfx_drv.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
-#include "tdfx_drv.h"
-#include "drmP.h"
-#include "drm_pciids.h"
+#include "dev/drm/tdfx_drv.h"
+#include "dev/drm/drmP.h"
+#include "dev/drm/drm_pciids.h"
 
 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
 static drm_pci_id_list_t tdfx_pciidlist[] = {
 	tdfx_PCI_IDS
 };
 
-static void tdfx_configure(drm_device_t *dev)
+static void tdfx_configure(struct drm_device *dev)
 {
-	dev->driver.buf_priv_size	= 1; /* No dev_priv */
+	dev->driver->driver_features =
+	    DRIVER_USE_MTRR;
 
-	dev->driver.max_ioctl		= 0;
+	dev->driver->buf_priv_size	= 1; /* No dev_priv */
 
-	dev->driver.name		= DRIVER_NAME;
-	dev->driver.desc		= DRIVER_DESC;
-	dev->driver.date		= DRIVER_DATE;
-	dev->driver.major		= DRIVER_MAJOR;
-	dev->driver.minor		= DRIVER_MINOR;
-	dev->driver.patchlevel		= DRIVER_PATCHLEVEL;
+	dev->driver->max_ioctl		= 0;
 
-	dev->driver.use_mtrr		= 1;
+	dev->driver->name		= DRIVER_NAME;
+	dev->driver->desc		= DRIVER_DESC;
+	dev->driver->date		= DRIVER_DATE;
+	dev->driver->major		= DRIVER_MAJOR;
+	dev->driver->minor		= DRIVER_MINOR;
+	dev->driver->patchlevel		= DRIVER_PATCHLEVEL;
 }
 
-#if defined(__FreeBSD__) || defined(__DragonFly__)
 static int
-tdfx_probe(device_t dev)
+tdfx_probe(device_t kdev)
 {
-	return drm_probe(dev, tdfx_pciidlist);
+	return drm_probe(kdev, tdfx_pciidlist);
 }
 
 static int
-tdfx_attach(device_t nbdev)
+tdfx_attach(device_t kdev)
 {
-	drm_device_t *dev = device_get_softc(nbdev);
+	struct drm_device *dev = device_get_softc(kdev);
+
+	dev->driver = malloc(sizeof(struct drm_driver_info), DRM_MEM_DRIVER,
+	    M_WAITOK | M_ZERO);
 
-	bzero(dev, sizeof(drm_device_t));
 	tdfx_configure(dev);
-	return drm_attach(nbdev, tdfx_pciidlist);
+
+	return drm_attach(kdev, tdfx_pciidlist);
+}
+
+static int
+tdfx_detach(device_t kdev)
+{
+	struct drm_device *dev = device_get_softc(kdev);
+	int ret;
+
+	ret = drm_detach(kdev);
+
+	free(dev->driver, DRM_MEM_DRIVER);
+
+	return ret;
 }
 
 static device_method_t tdfx_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe,		tdfx_probe),
 	DEVMETHOD(device_attach,	tdfx_attach),
-	DEVMETHOD(device_detach,	drm_detach),
+	DEVMETHOD(device_detach,	tdfx_detach),
 
 	{ 0, 0 }
 };
@@ -87,7 +102,7 @@ static device_method_t tdfx_methods[] = {
 static driver_t tdfx_driver = {
 	"drm",
 	tdfx_methods,
-	sizeof(drm_device_t)
+	sizeof(struct drm_device)
 };
 
 extern devclass_t drm_devclass;
@@ -97,12 +112,3 @@ DRIVER_MODULE(tdfx, vgapci, tdfx_driver, drm_devclass, 0, 0);
 DRIVER_MODULE(tdfx, pci, tdfx_driver, drm_devclass, 0, 0);
 #endif
 MODULE_DEPEND(tdfx, drm, 1, 1, 1);
-
-#elif defined(__NetBSD__) || defined(__OpenBSD__)
-#ifdef _LKM
-CFDRIVER_DECL(tdfx, DV_TTY, NULL);
-#else
-CFATTACH_DECL(tdfx, sizeof(drm_device_t), drm_probe, drm_attach, drm_detach,
-    drm_activate);
-#endif
-#endif
diff --git a/sys/dev/drm/tdfx_drv.h b/sys/dev/drm/tdfx_drv.h
index f9f7c257d9..44208083e6 100644
--- a/sys/dev/drm/tdfx_drv.h
+++ b/sys/dev/drm/tdfx_drv.h
@@ -1,7 +1,7 @@
 /* tdfx.h -- 3dfx DRM template customization -*- linux-c -*-
  * Created: Wed Feb 14 12:32:32 2001 by gareth@valinux.com
  */
-/*
+/*-
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
  *
@@ -26,8 +26,6 @@
  *
  * Authors:
  *    Gareth Hughes <gareth@valinux.com>
- *
- * $DragonFly: src/sys/dev/drm/tdfx_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  */
 
 #ifndef __TDFX_H__