sys/dev/drm/radeon/r600_hdmi.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Christian König.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Christian König
  25  */
  26 #include <linux/hdmi.h>
  27 #include <linux/gcd.h>
  28 #include <drm/drmP.h>
  29 #include <uapi_drm/radeon_drm.h>
  30 #include "radeon.h"
  31 #include "radeon_asic.h"
  32 #include "radeon_audio.h"
  33 #include "r600d.h"
  34 #include "atom.h"
  35
  36 /*
  37  * HDMI color format
  38  */
  39 enum r600_hdmi_color_format {
  40         RGB = 0,
  41         YCC_422 = 1,
  42         YCC_444 = 2
  43 };
  44
  45 /*
  46  * IEC60958 status bits
  47  */
  48 enum r600_hdmi_iec_status_bits {
  49         AUDIO_STATUS_DIG_ENABLE   = 0x01,
  50         AUDIO_STATUS_V            = 0x02,
  51         AUDIO_STATUS_VCFG         = 0x04,
  52         AUDIO_STATUS_EMPHASIS     = 0x08,
  53         AUDIO_STATUS_COPYRIGHT    = 0x10,
  54         AUDIO_STATUS_NONAUDIO     = 0x20,
  55         AUDIO_STATUS_PROFESSIONAL = 0x40,
  56         AUDIO_STATUS_LEVEL        = 0x80
  57 };
  58
  59 static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev)
  60 {
  61         struct r600_audio_pin status;
  62         uint32_t value;
  63
  64         value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
  65
  66         /* number of channels */
  67         status.channels = (value & 0x7) + 1;
  68
  69         /* bits per sample */
  70         switch ((value & 0xF0) >> 4) {
  71         case 0x0:
  72                 status.bits_per_sample = 8;
  73                 break;
  74         case 0x1:
  75                 status.bits_per_sample = 16;
  76                 break;
  77         case 0x2:
  78                 status.bits_per_sample = 20;
  79                 break;
  80         case 0x3:
  81                 status.bits_per_sample = 24;
  82                 break;
  83         case 0x4:
  84                 status.bits_per_sample = 32;
  85                 break;
  86         default:
  87                 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n",
  88                         (int)value);
  89                 status.bits_per_sample = 16;
  90         }
  91
  92         /* current sampling rate in HZ */
  93         if (value & 0x4000)
  94                 status.rate = 44100;
  95         else
  96                 status.rate = 48000;
  97         status.rate *= ((value >> 11) & 0x7) + 1;
  98         status.rate /= ((value >> 8) & 0x7) + 1;
  99
 100         value = RREG32(R600_AUDIO_STATUS_BITS);
 101
 102         /* iec 60958 status bits */
 103         status.status_bits = value & 0xff;
 104
 105         /* iec 60958 category code */
 106         status.category_code = (value >> 8) & 0xff;
 107
 108         return status;
 109 }
 110
 111 /*
 112  * update all hdmi interfaces with current audio parameters
 113  */
 114 void r600_audio_update_hdmi(void *arg, int pending)
 115 {
 116         struct radeon_device *rdev = arg;
 117         struct drm_device *dev = rdev->ddev;
 118         struct r600_audio_pin audio_status = r600_audio_status(rdev);
 119         struct drm_encoder *encoder;
 120         bool changed = false;
 121
 122         if (rdev->audio.pin[0].channels != audio_status.channels ||
 123             rdev->audio.pin[0].rate != audio_status.rate ||
 124             rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample ||
 125             rdev->audio.pin[0].status_bits != audio_status.status_bits ||
 126             rdev->audio.pin[0].category_code != audio_status.category_code) {
 127                 rdev->audio.pin[0] = audio_status;
 128                 changed = true;
 129         }
 130
 131         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 132                 if (!radeon_encoder_is_digital(encoder))
 133                         continue;
 134                 if (changed || r600_hdmi_buffer_status_changed(encoder))
 135                         r600_hdmi_update_audio_settings(encoder);
 136         }
 137 }
 138
 139 /* enable the audio stream */
 140 void r600_audio_enable(struct radeon_device *rdev,
 141                        struct r600_audio_pin *pin,
 142                        u8 enable_mask)
 143 {
 144         u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
 145
 146         if (!pin)
 147                 return;
 148
 149         if (enable_mask) {
 150                 tmp |= AUDIO_ENABLED;
 151                 if (enable_mask & 1)
 152                         tmp |= PIN0_AUDIO_ENABLED;
 153                 if (enable_mask & 2)
 154                         tmp |= PIN1_AUDIO_ENABLED;
 155                 if (enable_mask & 4)
 156                         tmp |= PIN2_AUDIO_ENABLED;
 157                 if (enable_mask & 8)
 158                         tmp |= PIN3_AUDIO_ENABLED;
 159         } else {
 160                 tmp &= ~(AUDIO_ENABLED |
 161                          PIN0_AUDIO_ENABLED |
 162                          PIN1_AUDIO_ENABLED |
 163                          PIN2_AUDIO_ENABLED |
 164                          PIN3_AUDIO_ENABLED);
 165         }
 166
 167         WREG32(AZ_HOT_PLUG_CONTROL, tmp);
 168 }
 169
 170 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev)
 171 {
 172         /* only one pin on 6xx-NI */
 173         return &rdev->audio.pin[0];
 174 }
 175
 176 void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset,
 177         const struct radeon_hdmi_acr *acr)
 178 {
 179         struct drm_device *dev = encoder->dev;
 180         struct radeon_device *rdev = dev->dev_private;
 181
 182         /* DCE 3.0 uses register that's normally for CRC_CONTROL */
 183         uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
 184                                        HDMI0_ACR_PACKET_CONTROL;
 185         WREG32_P(acr_ctl + offset,
 186                 HDMI0_ACR_SOURCE |              /* select SW CTS value */
 187                 HDMI0_ACR_AUTO_SEND,    /* allow hw to sent ACR packets when required */
 188                 ~(HDMI0_ACR_SOURCE |
 189                 HDMI0_ACR_AUTO_SEND));
 190
 191         WREG32_P(HDMI0_ACR_32_0 + offset,
 192                 HDMI0_ACR_CTS_32(acr->cts_32khz),
 193                 ~HDMI0_ACR_CTS_32_MASK);
 194         WREG32_P(HDMI0_ACR_32_1 + offset,
 195                 HDMI0_ACR_N_32(acr->n_32khz),
 196                 ~HDMI0_ACR_N_32_MASK);
 197
 198         WREG32_P(HDMI0_ACR_44_0 + offset,
 199                 HDMI0_ACR_CTS_44(acr->cts_44_1khz),
 200                 ~HDMI0_ACR_CTS_44_MASK);
 201         WREG32_P(HDMI0_ACR_44_1 + offset,
 202                 HDMI0_ACR_N_44(acr->n_44_1khz),
 203                 ~HDMI0_ACR_N_44_MASK);
 204
 205         WREG32_P(HDMI0_ACR_48_0 + offset,
 206                 HDMI0_ACR_CTS_48(acr->cts_48khz),
 207                 ~HDMI0_ACR_CTS_48_MASK);
 208         WREG32_P(HDMI0_ACR_48_1 + offset,
 209                 HDMI0_ACR_N_48(acr->n_48khz),
 210                 ~HDMI0_ACR_N_48_MASK);
 211 }
 212
 213 /*
 214  * build a HDMI Video Info Frame
 215  */
 216 void r600_set_avi_packet(struct radeon_device *rdev, u32 offset,
 217     unsigned char *buffer, size_t size)
 218 {
 219         uint8_t *frame = (uint8_t*)buffer + 3;
 220
 221         WREG32(HDMI0_AVI_INFO0 + offset,
 222                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 223         WREG32(HDMI0_AVI_INFO1 + offset,
 224                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
 225         WREG32(HDMI0_AVI_INFO2 + offset,
 226                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
 227         WREG32(HDMI0_AVI_INFO3 + offset,
 228                 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));
 229
 230         WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
 231                   HDMI0_AVI_INFO_LINE(2));      /* anything other than 0 */
 232
 233         WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
 234                   HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
 235                   HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */
 236
 237 }
 238
 239 /*
 240  * build a Audio Info Frame
 241  */
 242 static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
 243                                              const void *buffer, size_t size)
 244 {
 245         struct drm_device *dev = encoder->dev;
 246         struct radeon_device *rdev = dev->dev_private;
 247         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 248         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 249         uint32_t offset = dig->afmt->offset;
 250         const u8 *frame = (const u8*)buffer + 3;
 251
 252         WREG32(HDMI0_AUDIO_INFO0 + offset,
 253                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 254         WREG32(HDMI0_AUDIO_INFO1 + offset,
 255                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
 256 }
 257
 258 /*
 259  * test if audio buffer is filled enough to start playing
 260  */
 261 static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
 262 {
 263         struct drm_device *dev = encoder->dev;
 264         struct radeon_device *rdev = dev->dev_private;
 265         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 266         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 267         uint32_t offset = dig->afmt->offset;
 268
 269         return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
 270 }
 271
 272 /*
 273  * have buffer status changed since last call?
 274  */
 275 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
 276 {
 277         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 278         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 279         int status, result;
 280
 281         if (!dig->afmt || !dig->afmt->enabled)
 282                 return 0;
 283
 284         status = r600_hdmi_is_audio_buffer_filled(encoder);
 285         result = dig->afmt->last_buffer_filled_status != status;
 286         dig->afmt->last_buffer_filled_status = status;
 287
 288         return result;
 289 }
 290
 291 /*
 292  * write the audio workaround status to the hardware
 293  */
 294 void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
 295 {
 296         struct drm_device *dev = encoder->dev;
 297         struct radeon_device *rdev = dev->dev_private;
 298         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 299         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 300         uint32_t offset = dig->afmt->offset;
 301         bool hdmi_audio_workaround = false; /* FIXME */
 302         u32 value;
 303
 304         if (!hdmi_audio_workaround ||
 305             r600_hdmi_is_audio_buffer_filled(encoder))
 306                 value = 0; /* disable workaround */
 307         else
 308                 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
 309         WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
 310                  value, ~HDMI0_AUDIO_TEST_EN);
 311 }
 312
 313 void r600_hdmi_audio_set_dto(struct radeon_device *rdev,
 314     struct radeon_crtc *crtc, unsigned int clock)
 315 {
 316         struct radeon_encoder *radeon_encoder;
 317         struct radeon_encoder_atom_dig *dig;
 318
 319         if (!crtc)
 320                 return;
 321
 322         radeon_encoder = to_radeon_encoder(crtc->encoder);
 323         dig = radeon_encoder->enc_priv;
 324
 325         if (!dig)
 326                 return;
 327
 328         if (dig->dig_encoder == 0) {
 329                 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);
 330                 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
 331                 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
 332         } else {
 333                 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);
 334                 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
 335                 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
 336         }
 337 }
 338
 339 void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset)
 340 {
 341         struct drm_device *dev = encoder->dev;
 342         struct radeon_device *rdev = dev->dev_private;
 343
 344         WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
 345                 HDMI0_NULL_SEND |       /* send null packets when required */
 346                 HDMI0_GC_SEND |         /* send general control packets */
 347                 HDMI0_GC_CONT);         /* send general control packets every frame */
 348 }
 349
 350 void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)
 351 {
 352         struct drm_device *dev = encoder->dev;
 353         struct radeon_device *rdev = dev->dev_private;
 354
 355         WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
 356                 HDMI0_AUDIO_SAMPLE_SEND |                       /* send audio packets */
 357                 HDMI0_AUDIO_DELAY_EN(1) |                       /* default audio delay */
 358                 HDMI0_AUDIO_PACKETS_PER_LINE(3) |       /* should be suffient for all audio modes and small enough for all hblanks */
 359                 HDMI0_60958_CS_UPDATE,                          /* allow 60958 channel status fields to be updated */
 360                 ~(HDMI0_AUDIO_SAMPLE_SEND |
 361                 HDMI0_AUDIO_DELAY_EN_MASK |
 362                 HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
 363                 HDMI0_60958_CS_UPDATE));
 364
 365         WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
 366                 HDMI0_AUDIO_INFO_SEND |         /* enable audio info frames (frames won't be set until audio is enabled) */
 367                 HDMI0_AUDIO_INFO_UPDATE);       /* required for audio info values to be updated */
 368
 369         WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
 370                 HDMI0_AUDIO_INFO_LINE(2),       /* anything other than 0 */
 371                 ~HDMI0_AUDIO_INFO_LINE_MASK);
 372
 373         WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
 374                 ~(HDMI0_GENERIC0_SEND |
 375                 HDMI0_GENERIC0_CONT |
 376                 HDMI0_GENERIC0_UPDATE |
 377                 HDMI0_GENERIC1_SEND |
 378                 HDMI0_GENERIC1_CONT |
 379                 HDMI0_GENERIC0_LINE_MASK |
 380                 HDMI0_GENERIC1_LINE_MASK));
 381
 382         WREG32_P(HDMI0_60958_0 + offset,
 383                 HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
 384                 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
 385                 HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
 386
 387         WREG32_P(HDMI0_60958_1 + offset,
 388                 HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
 389                 ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
 390 }
 391
 392 void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)
 393 {
 394         struct drm_device *dev = encoder->dev;
 395         struct radeon_device *rdev = dev->dev_private;
 396
 397         if (mute)
 398                 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
 399         else
 400                 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);
 401 }
 402
 403 /**
 404  * r600_hdmi_update_audio_settings - Update audio infoframe
 405  *
 406  * @encoder: drm encoder
 407  *
 408  * Gets info about current audio stream and updates audio infoframe.
 409  */
 410 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
 411 {
 412         struct drm_device *dev = encoder->dev;
 413         struct radeon_device *rdev = dev->dev_private;
 414         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 415         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 416         struct r600_audio_pin audio = r600_audio_status(rdev);
 417         uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
 418         struct hdmi_audio_infoframe frame;
 419         uint32_t offset;
 420         uint32_t value;
 421         ssize_t err;
 422
 423         if (!dig->afmt || !dig->afmt->enabled)
 424                 return;
 425         offset = dig->afmt->offset;
 426
 427         DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
 428                  r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
 429                   audio.channels, audio.rate, audio.bits_per_sample);
 430         DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
 431                   (int)audio.status_bits, (int)audio.category_code);
 432
 433         err = hdmi_audio_infoframe_init(&frame);
 434         if (err < 0) {
 435                 DRM_ERROR("failed to setup audio infoframe\n");
 436                 return;
 437         }
 438
 439         frame.channels = audio.channels;
 440
 441         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
 442         if (err < 0) {
 443                 DRM_ERROR("failed to pack audio infoframe\n");
 444                 return;
 445         }
 446
 447         value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
 448         if (value & HDMI0_AUDIO_TEST_EN)
 449                 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
 450                        value & ~HDMI0_AUDIO_TEST_EN);
 451
 452         WREG32_OR(HDMI0_CONTROL + offset,
 453                   HDMI0_ERROR_ACK);
 454
 455         WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
 456                    ~HDMI0_AUDIO_INFO_SOURCE);
 457
 458         r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
 459
 460         WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
 461                   HDMI0_AUDIO_INFO_CONT |
 462                   HDMI0_AUDIO_INFO_UPDATE);
 463 }
 464
 465 /*
 466  * enable the HDMI engine
 467  */
 468 void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
 469 {
 470         struct drm_device *dev = encoder->dev;
 471         struct radeon_device *rdev = dev->dev_private;
 472         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 473         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 474         u32 hdmi = HDMI0_ERROR_ACK;
 475
 476         if (!dig || !dig->afmt)
 477                 return;
 478
 479         /* Older chipsets require setting HDMI and routing manually */
 480         if (!ASIC_IS_DCE3(rdev)) {
 481                 if (enable)
 482                         hdmi |= HDMI0_ENABLE;
 483                 switch (radeon_encoder->encoder_id) {
 484                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 485                         if (enable) {
 486                                 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
 487                                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
 488                         } else {
 489                                 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
 490                         }
 491                         break;
 492                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 493                         if (enable) {
 494                                 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
 495                                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
 496                         } else {
 497                                 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
 498                         }
 499                         break;
 500                 case ENCODER_OBJECT_ID_INTERNAL_DDI:
 501                         if (enable) {
 502                                 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
 503                                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
 504                         } else {
 505                                 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
 506                         }
 507                         break;
 508                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 509                         if (enable)
 510                                 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
 511                         break;
 512                 default:
 513                         dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
 514                                 radeon_encoder->encoder_id);
 515                         break;
 516                 }
 517                 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
 518         }
 519
 520         if (rdev->irq.installed) {
 521                 /* if irq is available use it */
 522                 /* XXX: shouldn't need this on any asics.  Double check DCE2/3 */
 523                 if (enable)
 524                         radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
 525                 else
 526                         radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
 527         }
 528
 529         dig->afmt->enabled = enable;
 530
 531         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 532                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
 533 }
 534