sys/dev/drm/radeon/radeon_bios.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *
  28  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 255572 2013-09-14 17:22:34Z dumbbell $
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "atom.h"
  35
  36 #include <linux/slab.h>
  37 /*
  38  * BIOS.
  39  */
  40
  41 /* If you boot an IGP board with a discrete card as the primary,
  42  * the IGP rom is not accessible via the rom bar as the IGP rom is
  43  * part of the system bios.  On boot, the system bios puts a
  44  * copy of the igp rom at the start of vram if a discrete card is
  45  * present.
  46  */
  47 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
  48 {
  49         uint8_t __iomem *bios;
  50         resource_size_t vram_base;
  51         resource_size_t size = 256 * 1024; /* ??? */
  52
  53         if (!(rdev->flags & RADEON_IS_IGP))
  54                 if (!radeon_card_posted(rdev))
  55                         return false;
  56
  57         rdev->bios = NULL;
  58         vram_base = pci_resource_start(rdev->pdev, 0);
  59         bios = ioremap(vram_base, size);
  60         if (!bios) {
  61                 return false;
  62         }
  63
  64         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  65                 iounmap(bios);
  66                 return false;
  67         }
  68         rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
  69         if (rdev->bios == NULL) {
  70                 iounmap(bios);
  71                 return false;
  72         }
  73         memcpy_fromio(rdev->bios, bios, size);
  74         iounmap(bios);
  75         return true;
  76 }
  77
  78 static bool radeon_read_bios(struct radeon_device *rdev)
  79 {
  80         device_t vga_dev;
  81         uint8_t __iomem *bios, val1, val2;
  82         size_t size;
  83
  84         DRM_INFO("%s: ===> Try PCI Expansion ROM...\n", __func__);
  85
  86         vga_dev = device_get_parent(rdev->dev->bsddev);
  87         rdev->bios = NULL;
  88         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  89         bios = vga_pci_map_bios(vga_dev, &size);
  90         if (!bios) {
  91                 return false;
  92         }
  93         DRM_INFO("%s: Map address: %p (%zu bytes)\n", __func__, bios, size);
  94
  95         val1 = readb(&bios[0]);
  96         val2 = readb(&bios[1]);
  97
  98         if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
  99                 if (size == 0) {
 100                         DRM_INFO("%s: Incorrect BIOS size\n", __func__);
 101                 } else {
 102                         DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
 103                             __func__, bios[0], bios[1]);
 104                 }
 105                 vga_pci_unmap_bios(vga_dev, bios);
 106                 return false;
 107         }
 108         rdev->bios = kmalloc(size, M_DRM, M_WAITOK | M_ZERO);
 109         if (rdev->bios == NULL) {
 110                 vga_pci_unmap_bios(vga_dev, bios);
 111                 return false;
 112         }
 113         memcpy_fromio(rdev->bios, bios, size);
 114         vga_pci_unmap_bios(vga_dev, bios);
 115         return true;
 116 }
 117
 118 static bool radeon_read_platform_bios(struct radeon_device *rdev)
 119 {
 120         uint8_t __iomem *bios;
 121         size_t size;
 122
 123         rdev->bios = NULL;
 124
 125         #if 0
 126         // XXX: FIXME
 127         bios = pci_platform_rom(rdev->pdev, &size);
 128         #else
 129         size = 0;
 130         bios = NULL;
 131         #endif
 132         if (!bios) {
 133                 return false;
 134         }
 135
 136         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
 137                 return false;
 138         }
 139         rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
 140         if (rdev->bios == NULL) {
 141                 return false;
 142         }
 143         memcpy(rdev->bios, bios, size);
 144         return true;
 145 }
 146
 147 #ifdef CONFIG_ACPI
 148 /* ATRM is used to get the BIOS on the discrete cards in
 149  * dual-gpu systems.
 150  */
 151 /* retrieve the ROM in 4k blocks */
 152 #define ATRM_BIOS_PAGE 4096
 153 /**
 154  * radeon_atrm_call - fetch a chunk of the vbios
 155  *
 156  * @atrm_handle: acpi ATRM handle
 157  * @bios: vbios image pointer
 158  * @offset: offset of vbios image data to fetch
 159  * @len: length of vbios image data to fetch
 160  *
 161  * Executes ATRM to fetch a chunk of the discrete
 162  * vbios image on PX systems (all asics).
 163  * Returns the length of the buffer fetched.
 164  */
 165 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios,
 166                             int offset, int len)
 167 {
 168         ACPI_STATUS status;
 169         ACPI_OBJECT atrm_arg_elements[2], *obj;
 170         ACPI_OBJECT_LIST atrm_arg;
 171         ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL};
 172
 173         atrm_arg.Count = 2;
 174         atrm_arg.Pointer = &atrm_arg_elements[0];
 175
 176         atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER;
 177         atrm_arg_elements[0].Integer.Value = offset;
 178
 179         atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER;
 180         atrm_arg_elements[1].Integer.Value = len;
 181
 182         status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer);
 183         if (ACPI_FAILURE(status)) {
 184                 printk("failed to evaluate ATRM got %s\n", AcpiFormatException(status));
 185                 return -ENODEV;
 186         }
 187
 188         obj = (ACPI_OBJECT *)buffer.Pointer;
 189         memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length);
 190         len = obj->Buffer.Length;
 191         AcpiOsFree(buffer.Pointer);
 192         return len;
 193 }
 194
 195 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
 196 {
 197         int ret;
 198         int size = 256 * 1024;
 199         int i;
 200         device_t dev;
 201         ACPI_HANDLE dhandle, atrm_handle;
 202         ACPI_STATUS status;
 203         bool found = false;
 204
 205         DRM_INFO("%s: ===> Try ATRM...\n", __func__);
 206
 207         /* ATRM is for the discrete card only */
 208         if (rdev->flags & RADEON_IS_IGP) {
 209                 DRM_INFO("%s: IGP card detected, skipping this method...\n",
 210                     __func__);
 211                 return false;
 212         }
 213
 214 #ifdef DUMBBELL_WIP
 215         while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
 216 #endif /* DUMBBELL_WIP */
 217         if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) {
 218                 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n",
 219                     __func__,
 220                     pci_get_domain(dev),
 221                     pci_get_bus(dev),
 222                     pci_get_slot(dev),
 223                     pci_get_function(dev),
 224                     pci_get_vendor(dev),
 225                     pci_get_device(dev));
 226                 DRM_INFO("%s: Get ACPI device handle\n", __func__);
 227                 dhandle = acpi_get_handle(dev);
 228 #ifdef DUMBBELL_WIP
 229                 if (!dhandle)
 230                         continue;
 231 #endif /* DUMBBELL_WIP */
 232                 if (!dhandle)
 233                         return false;
 234
 235                 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__);
 236                 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle);
 237                 if (!ACPI_FAILURE(status)) {
 238                         found = true;
 239 #ifdef DUMBBELL_WIP
 240                         break;
 241 #endif /* DUMBBELL_WIP */
 242                 } else {
 243                         DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n",
 244                             __func__, AcpiFormatException(status));
 245                 }
 246         }
 247
 248         if (!found)
 249                 return false;
 250
 251         rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
 252         if (!rdev->bios) {
 253                 DRM_ERROR("Unable to allocate bios\n");
 254                 return false;
 255         }
 256
 257         for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
 258                 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__);
 259                 ret = radeon_atrm_call(atrm_handle,
 260                                        rdev->bios,
 261                                        (i * ATRM_BIOS_PAGE),
 262                                        ATRM_BIOS_PAGE);
 263                 if (ret < ATRM_BIOS_PAGE)
 264                         break;
 265         }
 266
 267         if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 268                 if (i == 0) {
 269                         DRM_INFO("%s: Incorrect BIOS size\n", __func__);
 270                 } else {
 271                         DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
 272                             __func__, rdev->bios[0], rdev->bios[1]);
 273                 }
 274                 kfree(rdev->bios);
 275                 return false;
 276         }
 277         return true;
 278 }
 279 #else
 280 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
 281 {
 282         return false;
 283 }
 284 #endif
 285
 286 static bool ni_read_disabled_bios(struct radeon_device *rdev)
 287 {
 288         u32 bus_cntl;
 289         u32 d1vga_control;
 290         u32 d2vga_control;
 291         u32 vga_render_control;
 292         u32 rom_cntl;
 293         bool r;
 294
 295         DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__);
 296
 297         bus_cntl = RREG32(R600_BUS_CNTL);
 298         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 299         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 300         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 301         rom_cntl = RREG32(R600_ROM_CNTL);
 302
 303         /* enable the rom */
 304         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 305         if (!ASIC_IS_NODCE(rdev)) {
 306                 /* Disable VGA mode */
 307                 WREG32(AVIVO_D1VGA_CONTROL,
 308                        (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 309                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 310                 WREG32(AVIVO_D2VGA_CONTROL,
 311                        (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 312                                           AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 313                 WREG32(AVIVO_VGA_RENDER_CONTROL,
 314                        (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 315         }
 316         WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
 317
 318         r = radeon_read_bios(rdev);
 319
 320         /* restore regs */
 321         WREG32(R600_BUS_CNTL, bus_cntl);
 322         if (!ASIC_IS_NODCE(rdev)) {
 323                 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 324                 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 325                 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 326         }
 327         WREG32(R600_ROM_CNTL, rom_cntl);
 328         return r;
 329 }
 330
 331 static bool r700_read_disabled_bios(struct radeon_device *rdev)
 332 {
 333         uint32_t viph_control;
 334         uint32_t bus_cntl;
 335         uint32_t d1vga_control;
 336         uint32_t d2vga_control;
 337         uint32_t vga_render_control;
 338         uint32_t rom_cntl;
 339         uint32_t cg_spll_func_cntl = 0;
 340         uint32_t cg_spll_status;
 341         bool r;
 342
 343         DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__);
 344
 345         viph_control = RREG32(RADEON_VIPH_CONTROL);
 346         bus_cntl = RREG32(R600_BUS_CNTL);
 347         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 348         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 349         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 350         rom_cntl = RREG32(R600_ROM_CNTL);
 351
 352         /* disable VIP */
 353         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 354         /* enable the rom */
 355         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 356         /* Disable VGA mode */
 357         WREG32(AVIVO_D1VGA_CONTROL,
 358                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 359                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 360         WREG32(AVIVO_D2VGA_CONTROL,
 361                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 362                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 363         WREG32(AVIVO_VGA_RENDER_CONTROL,
 364                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 365
 366         if (rdev->family == CHIP_RV730) {
 367                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
 368
 369                 /* enable bypass mode */
 370                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
 371                                                 R600_SPLL_BYPASS_EN));
 372
 373                 /* wait for SPLL_CHG_STATUS to change to 1 */
 374                 cg_spll_status = 0;
 375                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 376                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 377
 378                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
 379         } else
 380                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
 381
 382         r = radeon_read_bios(rdev);
 383
 384         /* restore regs */
 385         if (rdev->family == CHIP_RV730) {
 386                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
 387
 388                 /* wait for SPLL_CHG_STATUS to change to 1 */
 389                 cg_spll_status = 0;
 390                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
 391                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
 392         }
 393         WREG32(RADEON_VIPH_CONTROL, viph_control);
 394         WREG32(R600_BUS_CNTL, bus_cntl);
 395         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 396         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 397         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 398         WREG32(R600_ROM_CNTL, rom_cntl);
 399         return r;
 400 }
 401
 402 static bool r600_read_disabled_bios(struct radeon_device *rdev)
 403 {
 404         uint32_t viph_control;
 405         uint32_t bus_cntl;
 406         uint32_t d1vga_control;
 407         uint32_t d2vga_control;
 408         uint32_t vga_render_control;
 409         uint32_t rom_cntl;
 410         uint32_t general_pwrmgt;
 411         uint32_t low_vid_lower_gpio_cntl;
 412         uint32_t medium_vid_lower_gpio_cntl;
 413         uint32_t high_vid_lower_gpio_cntl;
 414         uint32_t ctxsw_vid_lower_gpio_cntl;
 415         uint32_t lower_gpio_enable;
 416         bool r;
 417
 418         DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__);
 419
 420         viph_control = RREG32(RADEON_VIPH_CONTROL);
 421         bus_cntl = RREG32(R600_BUS_CNTL);
 422         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 423         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 424         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 425         rom_cntl = RREG32(R600_ROM_CNTL);
 426         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
 427         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
 428         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
 429         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
 430         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
 431         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
 432
 433         /* disable VIP */
 434         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 435         /* enable the rom */
 436         WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
 437         /* Disable VGA mode */
 438         WREG32(AVIVO_D1VGA_CONTROL,
 439                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 440                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 441         WREG32(AVIVO_D2VGA_CONTROL,
 442                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 443                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 444         WREG32(AVIVO_VGA_RENDER_CONTROL,
 445                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 446
 447         WREG32(R600_ROM_CNTL,
 448                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
 449                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
 450                 R600_SCK_OVERWRITE));
 451
 452         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
 453         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
 454                (low_vid_lower_gpio_cntl & ~0x400));
 455         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
 456                (medium_vid_lower_gpio_cntl & ~0x400));
 457         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
 458                (high_vid_lower_gpio_cntl & ~0x400));
 459         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
 460                (ctxsw_vid_lower_gpio_cntl & ~0x400));
 461         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
 462
 463         r = radeon_read_bios(rdev);
 464
 465         /* restore regs */
 466         WREG32(RADEON_VIPH_CONTROL, viph_control);
 467         WREG32(R600_BUS_CNTL, bus_cntl);
 468         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 469         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 470         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 471         WREG32(R600_ROM_CNTL, rom_cntl);
 472         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
 473         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
 474         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
 475         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
 476         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
 477         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
 478         return r;
 479 }
 480
 481 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
 482 {
 483         uint32_t seprom_cntl1;
 484         uint32_t viph_control;
 485         uint32_t bus_cntl;
 486         uint32_t d1vga_control;
 487         uint32_t d2vga_control;
 488         uint32_t vga_render_control;
 489         uint32_t gpiopad_a;
 490         uint32_t gpiopad_en;
 491         uint32_t gpiopad_mask;
 492         bool r;
 493
 494         DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__);
 495
 496         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 497         viph_control = RREG32(RADEON_VIPH_CONTROL);
 498         bus_cntl = RREG32(RV370_BUS_CNTL);
 499         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
 500         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
 501         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
 502         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
 503         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
 504         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
 505
 506         WREG32(RADEON_SEPROM_CNTL1,
 507                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 508                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 509         WREG32(RADEON_GPIOPAD_A, 0);
 510         WREG32(RADEON_GPIOPAD_EN, 0);
 511         WREG32(RADEON_GPIOPAD_MASK, 0);
 512
 513         /* disable VIP */
 514         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 515
 516         /* enable the rom */
 517         WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 518
 519         /* Disable VGA mode */
 520         WREG32(AVIVO_D1VGA_CONTROL,
 521                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 522                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 523         WREG32(AVIVO_D2VGA_CONTROL,
 524                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
 525                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
 526         WREG32(AVIVO_VGA_RENDER_CONTROL,
 527                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
 528
 529         r = radeon_read_bios(rdev);
 530
 531         /* restore regs */
 532         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 533         WREG32(RADEON_VIPH_CONTROL, viph_control);
 534         WREG32(RV370_BUS_CNTL, bus_cntl);
 535         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
 536         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
 537         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
 538         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
 539         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
 540         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
 541         return r;
 542 }
 543
 544 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
 545 {
 546         uint32_t seprom_cntl1;
 547         uint32_t viph_control;
 548         uint32_t bus_cntl;
 549         uint32_t crtc_gen_cntl;
 550         uint32_t crtc2_gen_cntl;
 551         uint32_t crtc_ext_cntl;
 552         uint32_t fp2_gen_cntl;
 553         bool r;
 554
 555         DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__);
 556
 557         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
 558         viph_control = RREG32(RADEON_VIPH_CONTROL);
 559         if (rdev->flags & RADEON_IS_PCIE)
 560                 bus_cntl = RREG32(RV370_BUS_CNTL);
 561         else
 562                 bus_cntl = RREG32(RADEON_BUS_CNTL);
 563         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
 564         crtc2_gen_cntl = 0;
 565         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 566         fp2_gen_cntl = 0;
 567
 568 #define PCI_DEVICE_ID_ATI_RADEON_QY     0x5159
 569
 570         if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 571                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 572         }
 573
 574         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 575                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 576         }
 577
 578         WREG32(RADEON_SEPROM_CNTL1,
 579                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
 580                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
 581
 582         /* disable VIP */
 583         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
 584
 585         /* enable the rom */
 586         if (rdev->flags & RADEON_IS_PCIE)
 587                 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
 588         else
 589                 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
 590
 591         /* Turn off mem requests and CRTC for both controllers */
 592         WREG32(RADEON_CRTC_GEN_CNTL,
 593                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
 594                 (RADEON_CRTC_DISP_REQ_EN_B |
 595                  RADEON_CRTC_EXT_DISP_EN)));
 596         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 597                 WREG32(RADEON_CRTC2_GEN_CNTL,
 598                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
 599                         RADEON_CRTC2_DISP_REQ_EN_B));
 600         }
 601         /* Turn off CRTC */
 602         WREG32(RADEON_CRTC_EXT_CNTL,
 603                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
 604                 (RADEON_CRTC_SYNC_TRISTAT |
 605                  RADEON_CRTC_DISPLAY_DIS)));
 606
 607         if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 608                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
 609         }
 610
 611         r = radeon_read_bios(rdev);
 612
 613         /* restore regs */
 614         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
 615         WREG32(RADEON_VIPH_CONTROL, viph_control);
 616         if (rdev->flags & RADEON_IS_PCIE)
 617                 WREG32(RV370_BUS_CNTL, bus_cntl);
 618         else
 619                 WREG32(RADEON_BUS_CNTL, bus_cntl);
 620         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 621         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
 622                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 623         }
 624         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 625         if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
 626                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 627         }
 628         return r;
 629 }
 630
 631 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
 632 {
 633         if (rdev->flags & RADEON_IS_IGP)
 634                 return igp_read_bios_from_vram(rdev);
 635         else if (rdev->family >= CHIP_BARTS)
 636                 return ni_read_disabled_bios(rdev);
 637         else if (rdev->family >= CHIP_RV770)
 638                 return r700_read_disabled_bios(rdev);
 639         else if (rdev->family >= CHIP_R600)
 640                 return r600_read_disabled_bios(rdev);
 641         else if (rdev->family >= CHIP_RS600)
 642                 return avivo_read_disabled_bios(rdev);
 643         else
 644                 return legacy_read_disabled_bios(rdev);
 645 }
 646
 647 #ifdef CONFIG_ACPI
 648 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 649 {
 650         bool ret = false;
 651         ACPI_TABLE_HEADER *hdr;
 652         ACPI_SIZE tbl_size;
 653         UEFI_ACPI_VFCT *vfct;
 654         GOP_VBIOS_CONTENT *vbios;
 655         VFCT_IMAGE_HEADER *vhdr;
 656         ACPI_STATUS status;
 657
 658         DRM_INFO("%s: ===> Try VFCT...\n", __func__);
 659
 660         DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__);
 661         status = AcpiGetTable("VFCT", 1, &hdr);
 662         if (!ACPI_SUCCESS(status)) {
 663                 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n",
 664                     __func__, AcpiFormatException(status));
 665                 return false;
 666         }
 667         tbl_size = hdr->Length;
 668         if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
 669                 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
 670                 goto out_unmap;
 671         }
 672
 673         vfct = (UEFI_ACPI_VFCT *)hdr;
 674         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
 675                 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
 676                 goto out_unmap;
 677         }
 678
 679         vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
 680         vhdr = &vbios->VbiosHeader;
 681         DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
 682                         vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
 683                         vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
 684
 685         if (vhdr->PCIBus != rdev->pdev->bus->number ||
 686             vhdr->PCIDevice != rdev->ddev->pci_slot ||
 687             vhdr->PCIFunction != rdev->ddev->pci_func ||
 688             vhdr->VendorID != rdev->pdev->vendor ||
 689             vhdr->DeviceID != rdev->pdev->device) {
 690                 DRM_INFO("ACPI VFCT table is not for this card\n");
 691                 goto out_unmap;
 692         }
 693
 694         if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
 695                 DRM_ERROR("ACPI VFCT image truncated\n");
 696                 goto out_unmap;
 697         }
 698
 699         rdev->bios = kmalloc(vhdr->ImageLength, M_DRM, M_WAITOK);
 700         memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength);
 701         ret = !!rdev->bios;
 702
 703 out_unmap:
 704         return ret;
 705 }
 706 #else
 707 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
 708 {
 709         return false;
 710 }
 711 #endif
 712
 713 bool radeon_get_bios(struct radeon_device *rdev)
 714 {
 715         bool r;
 716         uint16_t tmp;
 717
 718         r = radeon_atrm_get_bios(rdev);
 719         if (r == false)
 720                 r = radeon_acpi_vfct_bios(rdev);
 721         if (r == false)
 722                 r = igp_read_bios_from_vram(rdev);
 723         if (r == false)
 724                 r = radeon_read_bios(rdev);
 725         if (r == false)
 726                 r = radeon_read_disabled_bios(rdev);
 727         if (r == false)
 728                 r = radeon_read_platform_bios(rdev);
 729         if (r == false || rdev->bios == NULL) {
 730                 DRM_ERROR("Unable to locate a BIOS ROM\n");
 731                 rdev->bios = NULL;
 732                 return false;
 733         }
 734         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
 735                 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
 736                 goto free_bios;
 737         }
 738
 739         tmp = RBIOS16(0x18);
 740         if (RBIOS8(tmp + 0x14) != 0x0) {
 741                 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
 742                 goto free_bios;
 743         }
 744
 745         rdev->bios_header_start = RBIOS16(0x48);
 746         if (!rdev->bios_header_start) {
 747                 goto free_bios;
 748         }
 749         tmp = rdev->bios_header_start + 4;
 750         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
 751             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
 752                 rdev->is_atom_bios = true;
 753         } else {
 754                 rdev->is_atom_bios = false;
 755         }
 756
 757         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
 758         return true;
 759 free_bios:
 760         kfree(rdev->bios);
 761         rdev->bios = NULL;
 762         return false;
 763 }