2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <uapi_drm/radeon_drm.h>
30 #include "radeon_asic.h"
32 #include <linux/delay.h>
34 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
36 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
37 const struct drm_encoder_helper_funcs *encoder_funcs;
39 encoder_funcs = encoder->helper_private;
40 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
41 radeon_encoder->active_device = 0;
44 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
46 struct drm_device *dev = encoder->dev;
47 struct radeon_device *rdev = dev->dev_private;
48 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
49 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
50 int panel_pwr_delay = 2000;
52 uint8_t backlight_level;
55 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
56 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
58 if (radeon_encoder->enc_priv) {
59 if (rdev->is_atom_bios) {
60 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
61 panel_pwr_delay = lvds->panel_pwr_delay;
63 backlight_level = lvds->backlight_level;
65 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
66 panel_pwr_delay = lvds->panel_pwr_delay;
68 backlight_level = lvds->backlight_level;
72 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
73 * Taken from radeonfb.
75 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
76 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
77 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
78 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
82 case DRM_MODE_DPMS_ON:
83 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
84 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
85 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
86 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
87 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
88 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
91 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
92 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
93 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
95 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
96 RADEON_LVDS_BL_MOD_LEVEL_MASK);
97 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
98 RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
99 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
101 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
102 mdelay(panel_pwr_delay);
103 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
105 case DRM_MODE_DPMS_STANDBY:
106 case DRM_MODE_DPMS_SUSPEND:
107 case DRM_MODE_DPMS_OFF:
108 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
109 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
110 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
112 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
113 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
114 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
116 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
117 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
119 mdelay(panel_pwr_delay);
120 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
121 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
122 mdelay(panel_pwr_delay);
126 if (rdev->is_atom_bios)
127 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
129 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
133 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
135 struct radeon_device *rdev = encoder->dev->dev_private;
136 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
139 if (radeon_encoder->enc_priv) {
140 if (rdev->is_atom_bios) {
141 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
142 lvds->dpms_mode = mode;
144 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
145 lvds->dpms_mode = mode;
149 radeon_legacy_lvds_update(encoder, mode);
152 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
154 struct radeon_device *rdev = encoder->dev->dev_private;
156 if (rdev->is_atom_bios)
157 radeon_atom_output_lock(encoder, true);
159 radeon_combios_output_lock(encoder, true);
160 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
163 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
165 struct radeon_device *rdev = encoder->dev->dev_private;
167 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
168 if (rdev->is_atom_bios)
169 radeon_atom_output_lock(encoder, false);
171 radeon_combios_output_lock(encoder, false);
174 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
175 struct drm_display_mode *mode,
176 struct drm_display_mode *adjusted_mode)
178 struct drm_device *dev = encoder->dev;
179 struct radeon_device *rdev = dev->dev_private;
180 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
181 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
182 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
186 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
187 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
189 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
190 if (rdev->is_atom_bios) {
191 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
192 * need to call that on resume to set up the reg properly.
194 radeon_encoder->pixel_clock = adjusted_mode->clock;
195 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
196 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
198 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
200 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
201 lvds_gen_cntl = lvds->lvds_gen_cntl;
202 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
203 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
204 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
205 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
207 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
209 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
210 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
215 if (ASIC_IS_R300(rdev))
216 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
218 if (radeon_crtc->crtc_id == 0) {
219 if (ASIC_IS_R300(rdev)) {
220 if (radeon_encoder->rmx_type != RMX_OFF)
221 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
223 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
225 if (ASIC_IS_R300(rdev))
226 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
228 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
231 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
232 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
233 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
235 if (rdev->family == CHIP_RV410)
236 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
238 if (rdev->is_atom_bios)
239 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
241 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
244 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
245 const struct drm_display_mode *mode,
246 struct drm_display_mode *adjusted_mode)
248 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
250 /* set the active encoder to connector routing */
251 radeon_encoder_set_active_device(encoder);
252 drm_mode_set_crtcinfo(adjusted_mode, 0);
254 /* get the native mode for LVDS */
255 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
256 radeon_panel_mode_fixup(encoder, adjusted_mode);
261 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
262 .dpms = radeon_legacy_lvds_dpms,
263 .mode_fixup = radeon_legacy_mode_fixup,
264 .prepare = radeon_legacy_lvds_prepare,
265 .mode_set = radeon_legacy_lvds_mode_set,
266 .commit = radeon_legacy_lvds_commit,
267 .disable = radeon_legacy_encoder_disable,
271 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder)
273 struct drm_device *dev = radeon_encoder->base.dev;
274 struct radeon_device *rdev = dev->dev_private;
277 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
278 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
280 return backlight_level;
284 radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
286 struct drm_device *dev = radeon_encoder->base.dev;
287 struct radeon_device *rdev = dev->dev_private;
288 int dpms_mode = DRM_MODE_DPMS_ON;
290 if (radeon_encoder->enc_priv) {
291 if (rdev->is_atom_bios) {
292 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
293 if (lvds->backlight_level > 0)
294 dpms_mode = lvds->dpms_mode;
296 dpms_mode = DRM_MODE_DPMS_OFF;
297 lvds->backlight_level = level;
299 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
300 if (lvds->backlight_level > 0)
301 dpms_mode = lvds->dpms_mode;
303 dpms_mode = DRM_MODE_DPMS_OFF;
304 lvds->backlight_level = level;
308 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
311 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
313 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
315 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
318 /* Convert brightness to hardware level */
319 if (bd->props.brightness < 0)
321 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
322 level = RADEON_MAX_BL_LEVEL;
324 level = bd->props.brightness;
327 level = RADEON_MAX_BL_LEVEL - level;
332 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
334 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
335 struct radeon_encoder *radeon_encoder = pdata->encoder;
337 radeon_legacy_set_backlight_level(radeon_encoder,
338 radeon_legacy_lvds_level(bd));
343 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
345 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
346 struct radeon_encoder *radeon_encoder = pdata->encoder;
347 struct drm_device *dev = radeon_encoder->base.dev;
348 struct radeon_device *rdev = dev->dev_private;
349 uint8_t backlight_level;
351 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
352 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
354 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level;
357 static const struct backlight_ops radeon_backlight_ops = {
358 .get_brightness = radeon_legacy_backlight_get_brightness,
359 .update_status = radeon_legacy_backlight_update_status,
362 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
363 struct drm_connector *drm_connector)
365 struct drm_device *dev = radeon_encoder->base.dev;
366 struct radeon_device *rdev = dev->dev_private;
367 struct backlight_device *bd;
368 struct backlight_properties props;
369 struct radeon_backlight_privdata *pdata;
370 uint8_t backlight_level;
373 if (!radeon_encoder->enc_priv)
376 #ifdef CONFIG_PMAC_BACKLIGHT
377 if (!pmac_has_backlight_type("ati") &&
378 !pmac_has_backlight_type("mnca"))
382 pdata = kmalloc(sizeof(struct radeon_backlight_privdata),
385 DRM_ERROR("Memory allocation failed\n");
389 memset(&props, 0, sizeof(props));
390 props.max_brightness = RADEON_MAX_BL_LEVEL;
391 props.type = BACKLIGHT_RAW;
392 ksnprintf(bl_name, sizeof(bl_name),
393 "radeon_bl%d", dev->primary->index);
394 bd = backlight_device_register(bl_name, drm_connector->kdev,
395 pdata, &radeon_backlight_ops, &props);
397 DRM_ERROR("Backlight registration failed\n");
401 pdata->encoder = radeon_encoder;
403 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
404 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
406 /* First, try to detect backlight level sense based on the assumption
407 * that firmware set it up at full brightness
409 if (backlight_level == 0)
410 pdata->negative = true;
411 else if (backlight_level == 0xff)
412 pdata->negative = false;
414 /* XXX hack... maybe some day we can figure out in what direction
415 * backlight should work on a given panel?
417 pdata->negative = (rdev->family != CHIP_RV200 &&
418 rdev->family != CHIP_RV250 &&
419 rdev->family != CHIP_RV280 &&
420 rdev->family != CHIP_RV350);
422 #ifdef CONFIG_PMAC_BACKLIGHT
423 pdata->negative = (pdata->negative ||
424 of_machine_is_compatible("PowerBook4,3") ||
425 of_machine_is_compatible("PowerBook6,3") ||
426 of_machine_is_compatible("PowerBook6,5"));
430 if (rdev->is_atom_bios) {
431 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
434 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
438 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
439 bd->props.power = FB_BLANK_UNBLANK;
440 backlight_update_status(bd);
442 DRM_INFO("radeon legacy LVDS backlight initialized\n");
443 rdev->mode_info.bl_encoder = radeon_encoder;
452 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
454 struct drm_device *dev = radeon_encoder->base.dev;
455 struct radeon_device *rdev = dev->dev_private;
456 struct backlight_device *bd = NULL;
458 if (!radeon_encoder->enc_priv)
461 if (rdev->is_atom_bios) {
462 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
466 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
472 struct radeon_backlight_privdata *pdata;
474 pdata = bl_get_data(bd);
475 backlight_device_unregister(bd);
478 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
482 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
484 void radeon_legacy_backlight_init(struct radeon_encoder *encoder,
485 struct drm_connector *drm_connector)
489 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
496 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
498 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
500 if (radeon_encoder->enc_priv) {
501 radeon_legacy_backlight_exit(radeon_encoder);
502 kfree(radeon_encoder->enc_priv);
504 drm_encoder_cleanup(encoder);
505 kfree(radeon_encoder);
508 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
509 .destroy = radeon_lvds_enc_destroy,
512 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
514 struct drm_device *dev = encoder->dev;
515 struct radeon_device *rdev = dev->dev_private;
516 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
517 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
518 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
523 case DRM_MODE_DPMS_ON:
524 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
525 dac_cntl &= ~RADEON_DAC_PDWN;
526 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
530 case DRM_MODE_DPMS_STANDBY:
531 case DRM_MODE_DPMS_SUSPEND:
532 case DRM_MODE_DPMS_OFF:
533 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
534 dac_cntl |= RADEON_DAC_PDWN;
535 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
541 /* handled in radeon_crtc_dpms() */
542 if (!(rdev->flags & RADEON_SINGLE_CRTC))
543 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
544 WREG32(RADEON_DAC_CNTL, dac_cntl);
545 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
547 if (rdev->is_atom_bios)
548 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
550 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
554 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
556 struct radeon_device *rdev = encoder->dev->dev_private;
558 if (rdev->is_atom_bios)
559 radeon_atom_output_lock(encoder, true);
561 radeon_combios_output_lock(encoder, true);
562 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
565 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
567 struct radeon_device *rdev = encoder->dev->dev_private;
569 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
571 if (rdev->is_atom_bios)
572 radeon_atom_output_lock(encoder, false);
574 radeon_combios_output_lock(encoder, false);
577 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
578 struct drm_display_mode *mode,
579 struct drm_display_mode *adjusted_mode)
581 struct drm_device *dev = encoder->dev;
582 struct radeon_device *rdev = dev->dev_private;
583 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
584 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
585 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
589 if (radeon_crtc->crtc_id == 0) {
590 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
591 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
592 ~(RADEON_DISP_DAC_SOURCE_MASK);
593 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
595 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
596 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
599 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
600 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
601 ~(RADEON_DISP_DAC_SOURCE_MASK);
602 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
603 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
605 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
606 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
610 dac_cntl = (RADEON_DAC_MASK_ALL |
611 RADEON_DAC_VGA_ADR_EN |
615 WREG32_P(RADEON_DAC_CNTL,
617 RADEON_DAC_RANGE_CNTL |
618 RADEON_DAC_BLANKING);
620 if (radeon_encoder->enc_priv) {
621 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
622 dac_macro_cntl = p_dac->ps2_pdac_adj;
624 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
625 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
626 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
628 if (rdev->is_atom_bios)
629 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
631 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
634 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
635 struct drm_connector *connector)
637 struct drm_device *dev = encoder->dev;
638 struct radeon_device *rdev = dev->dev_private;
639 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
640 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
641 enum drm_connector_status found = connector_status_disconnected;
644 /* just don't bother on RN50 those chip are often connected to remoting
645 * console hw and often we get failure to load detect those. So to make
646 * everyone happy report the encoder as always connected.
648 if (ASIC_IS_RN50(rdev)) {
649 return connector_status_connected;
652 /* save the regs we need */
653 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
654 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
655 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
656 dac_cntl = RREG32(RADEON_DAC_CNTL);
657 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
659 tmp = vclk_ecp_cntl &
660 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
661 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
663 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
664 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
666 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
667 RADEON_DAC_FORCE_DATA_EN;
670 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
672 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
674 if (ASIC_IS_R300(rdev))
675 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
676 else if (ASIC_IS_RV100(rdev))
677 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT);
679 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
681 WREG32(RADEON_DAC_EXT_CNTL, tmp);
683 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
684 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
685 WREG32(RADEON_DAC_CNTL, tmp);
687 tmp = dac_macro_cntl;
688 tmp &= ~(RADEON_DAC_PDWN_R |
692 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
696 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
697 found = connector_status_connected;
699 /* restore the regs we used */
700 WREG32(RADEON_DAC_CNTL, dac_cntl);
701 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
702 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
703 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
704 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
709 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
710 .dpms = radeon_legacy_primary_dac_dpms,
711 .mode_fixup = radeon_legacy_mode_fixup,
712 .prepare = radeon_legacy_primary_dac_prepare,
713 .mode_set = radeon_legacy_primary_dac_mode_set,
714 .commit = radeon_legacy_primary_dac_commit,
715 .detect = radeon_legacy_primary_dac_detect,
716 .disable = radeon_legacy_encoder_disable,
720 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
721 .destroy = radeon_enc_destroy,
724 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
726 struct drm_device *dev = encoder->dev;
727 struct radeon_device *rdev = dev->dev_private;
728 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
732 case DRM_MODE_DPMS_ON:
733 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
735 case DRM_MODE_DPMS_STANDBY:
736 case DRM_MODE_DPMS_SUSPEND:
737 case DRM_MODE_DPMS_OFF:
738 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
742 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
744 if (rdev->is_atom_bios)
745 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
747 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
751 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
753 struct radeon_device *rdev = encoder->dev->dev_private;
755 if (rdev->is_atom_bios)
756 radeon_atom_output_lock(encoder, true);
758 radeon_combios_output_lock(encoder, true);
759 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
762 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
764 struct radeon_device *rdev = encoder->dev->dev_private;
766 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
768 if (rdev->is_atom_bios)
769 radeon_atom_output_lock(encoder, true);
771 radeon_combios_output_lock(encoder, true);
774 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
775 struct drm_display_mode *mode,
776 struct drm_display_mode *adjusted_mode)
778 struct drm_device *dev = encoder->dev;
779 struct radeon_device *rdev = dev->dev_private;
780 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
781 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
782 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
787 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
789 if (rdev->family == CHIP_RV280) {
790 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
792 tmds_pll_cntl ^= (1 << 22);
795 if (radeon_encoder->enc_priv) {
796 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
798 for (i = 0; i < 4; i++) {
799 if (tmds->tmds_pll[i].freq == 0)
801 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
802 tmp = tmds->tmds_pll[i].value ;
808 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
809 if (tmp & 0xfff00000)
812 tmds_pll_cntl &= 0xfff00000;
813 tmds_pll_cntl |= tmp;
818 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
819 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
821 if (rdev->family == CHIP_R200 ||
822 rdev->family == CHIP_R100 ||
824 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
825 else /* RV chips got this bit reversed */
826 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
828 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
829 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
830 RADEON_FP_CRTC_DONT_SHADOW_HEND));
832 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
834 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
835 RADEON_FP_DFP_SYNC_SEL |
836 RADEON_FP_CRT_SYNC_SEL |
837 RADEON_FP_CRTC_LOCK_8DOT |
838 RADEON_FP_USE_SHADOW_EN |
839 RADEON_FP_CRTC_USE_SHADOW_VEND |
840 RADEON_FP_CRT_SYNC_ALT);
842 if (1) /* FIXME rgbBits == 8 */
843 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
845 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
847 if (radeon_crtc->crtc_id == 0) {
848 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
849 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
850 if (radeon_encoder->rmx_type != RMX_OFF)
851 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
853 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
855 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
857 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
858 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
859 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
861 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
864 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
865 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
866 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
868 if (rdev->is_atom_bios)
869 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
871 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
874 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
875 .dpms = radeon_legacy_tmds_int_dpms,
876 .mode_fixup = radeon_legacy_mode_fixup,
877 .prepare = radeon_legacy_tmds_int_prepare,
878 .mode_set = radeon_legacy_tmds_int_mode_set,
879 .commit = radeon_legacy_tmds_int_commit,
880 .disable = radeon_legacy_encoder_disable,
884 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
885 .destroy = radeon_enc_destroy,
888 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
890 struct drm_device *dev = encoder->dev;
891 struct radeon_device *rdev = dev->dev_private;
892 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
896 case DRM_MODE_DPMS_ON:
897 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
898 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
900 case DRM_MODE_DPMS_STANDBY:
901 case DRM_MODE_DPMS_SUSPEND:
902 case DRM_MODE_DPMS_OFF:
903 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
904 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
908 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
910 if (rdev->is_atom_bios)
911 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
913 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
917 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
919 struct radeon_device *rdev = encoder->dev->dev_private;
921 if (rdev->is_atom_bios)
922 radeon_atom_output_lock(encoder, true);
924 radeon_combios_output_lock(encoder, true);
925 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
928 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
930 struct radeon_device *rdev = encoder->dev->dev_private;
931 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
933 if (rdev->is_atom_bios)
934 radeon_atom_output_lock(encoder, false);
936 radeon_combios_output_lock(encoder, false);
939 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
940 struct drm_display_mode *mode,
941 struct drm_display_mode *adjusted_mode)
943 struct drm_device *dev = encoder->dev;
944 struct radeon_device *rdev = dev->dev_private;
945 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
946 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
947 uint32_t fp2_gen_cntl;
951 if (rdev->is_atom_bios) {
952 radeon_encoder->pixel_clock = adjusted_mode->clock;
953 atombios_dvo_setup(encoder, ATOM_ENABLE);
954 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
956 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
958 if (1) /* FIXME rgbBits == 8 */
959 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
961 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
963 fp2_gen_cntl &= ~(RADEON_FP2_ON |
965 RADEON_FP2_DVO_RATE_SEL_SDR);
967 /* XXX: these are oem specific */
968 if (ASIC_IS_R300(rdev)) {
969 if ((dev->pdev->device == 0x4850) &&
970 (dev->pdev->subsystem_vendor == 0x1028) &&
971 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
972 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
974 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
976 /*if (mode->clock > 165000)
977 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
979 if (!radeon_combios_external_tmds_setup(encoder))
980 radeon_external_tmds_setup(encoder);
983 if (radeon_crtc->crtc_id == 0) {
984 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
985 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
986 if (radeon_encoder->rmx_type != RMX_OFF)
987 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
989 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
991 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
993 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
994 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
995 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
997 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
1000 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1002 if (rdev->is_atom_bios)
1003 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1005 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1008 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
1010 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1011 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
1012 kfree(radeon_encoder->enc_priv);
1013 drm_encoder_cleanup(encoder);
1014 kfree(radeon_encoder);
1017 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
1018 .dpms = radeon_legacy_tmds_ext_dpms,
1019 .mode_fixup = radeon_legacy_mode_fixup,
1020 .prepare = radeon_legacy_tmds_ext_prepare,
1021 .mode_set = radeon_legacy_tmds_ext_mode_set,
1022 .commit = radeon_legacy_tmds_ext_commit,
1023 .disable = radeon_legacy_encoder_disable,
1027 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1028 .destroy = radeon_ext_tmds_enc_destroy,
1031 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1033 struct drm_device *dev = encoder->dev;
1034 struct radeon_device *rdev = dev->dev_private;
1035 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1036 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1037 uint32_t tv_master_cntl = 0;
1039 DRM_DEBUG_KMS("\n");
1041 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1043 if (rdev->family == CHIP_R200)
1044 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1047 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1049 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1050 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1054 case DRM_MODE_DPMS_ON:
1055 if (rdev->family == CHIP_R200) {
1056 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1059 tv_master_cntl |= RADEON_TV_ON;
1061 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1063 if (rdev->family == CHIP_R420 ||
1064 rdev->family == CHIP_R423 ||
1065 rdev->family == CHIP_RV410)
1066 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1067 R420_TV_DAC_GDACPD |
1068 R420_TV_DAC_BDACPD |
1069 RADEON_TV_DAC_BGSLEEP);
1071 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1072 RADEON_TV_DAC_GDACPD |
1073 RADEON_TV_DAC_BDACPD |
1074 RADEON_TV_DAC_BGSLEEP);
1077 case DRM_MODE_DPMS_STANDBY:
1078 case DRM_MODE_DPMS_SUSPEND:
1079 case DRM_MODE_DPMS_OFF:
1080 if (rdev->family == CHIP_R200)
1081 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1084 tv_master_cntl &= ~RADEON_TV_ON;
1086 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1088 if (rdev->family == CHIP_R420 ||
1089 rdev->family == CHIP_R423 ||
1090 rdev->family == CHIP_RV410)
1091 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1092 R420_TV_DAC_GDACPD |
1093 R420_TV_DAC_BDACPD |
1094 RADEON_TV_DAC_BGSLEEP);
1096 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1097 RADEON_TV_DAC_GDACPD |
1098 RADEON_TV_DAC_BDACPD |
1099 RADEON_TV_DAC_BGSLEEP);
1104 if (rdev->family == CHIP_R200) {
1105 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1108 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1109 /* handled in radeon_crtc_dpms() */
1110 else if (!(rdev->flags & RADEON_SINGLE_CRTC))
1111 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1112 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1115 if (rdev->is_atom_bios)
1116 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1118 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1122 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1124 struct radeon_device *rdev = encoder->dev->dev_private;
1126 if (rdev->is_atom_bios)
1127 radeon_atom_output_lock(encoder, true);
1129 radeon_combios_output_lock(encoder, true);
1130 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1133 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1135 struct radeon_device *rdev = encoder->dev->dev_private;
1137 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1139 if (rdev->is_atom_bios)
1140 radeon_atom_output_lock(encoder, true);
1142 radeon_combios_output_lock(encoder, true);
1145 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1146 struct drm_display_mode *mode,
1147 struct drm_display_mode *adjusted_mode)
1149 struct drm_device *dev = encoder->dev;
1150 struct radeon_device *rdev = dev->dev_private;
1151 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1152 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1153 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1154 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1155 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1158 DRM_DEBUG_KMS("\n");
1160 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1162 if (rdev->family != CHIP_R200) {
1163 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1164 if (rdev->family == CHIP_R420 ||
1165 rdev->family == CHIP_R423 ||
1166 rdev->family == CHIP_RV410) {
1167 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1168 RADEON_TV_DAC_BGADJ_MASK |
1169 R420_TV_DAC_DACADJ_MASK |
1170 R420_TV_DAC_RDACPD |
1171 R420_TV_DAC_GDACPD |
1172 R420_TV_DAC_BDACPD |
1173 R420_TV_DAC_TVENABLE);
1175 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1176 RADEON_TV_DAC_BGADJ_MASK |
1177 RADEON_TV_DAC_DACADJ_MASK |
1178 RADEON_TV_DAC_RDACPD |
1179 RADEON_TV_DAC_GDACPD |
1180 RADEON_TV_DAC_BDACPD);
1183 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1186 if (tv_dac->tv_std == TV_STD_NTSC ||
1187 tv_dac->tv_std == TV_STD_NTSC_J ||
1188 tv_dac->tv_std == TV_STD_PAL_M ||
1189 tv_dac->tv_std == TV_STD_PAL_60)
1190 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1192 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1194 if (tv_dac->tv_std == TV_STD_NTSC ||
1195 tv_dac->tv_std == TV_STD_NTSC_J)
1196 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1198 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1200 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1201 tv_dac->ps2_tvdac_adj);
1203 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1206 if (ASIC_IS_R300(rdev)) {
1207 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1208 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1209 } else if (rdev->family != CHIP_R200)
1210 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1211 else if (rdev->family == CHIP_R200)
1212 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1214 if (rdev->family >= CHIP_R200)
1215 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1220 dac_cntl = RREG32(RADEON_DAC_CNTL);
1221 dac_cntl &= ~RADEON_DAC_TVO_EN;
1222 WREG32(RADEON_DAC_CNTL, dac_cntl);
1224 if (ASIC_IS_R300(rdev))
1225 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1227 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1228 if (radeon_crtc->crtc_id == 0) {
1229 if (ASIC_IS_R300(rdev)) {
1230 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1231 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1232 RADEON_DISP_TV_SOURCE_CRTC);
1234 if (rdev->family >= CHIP_R200) {
1235 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1237 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1240 if (ASIC_IS_R300(rdev)) {
1241 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1242 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1244 if (rdev->family >= CHIP_R200) {
1245 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1247 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1250 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1253 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1255 if (radeon_crtc->crtc_id == 0) {
1256 if (ASIC_IS_R300(rdev)) {
1257 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1258 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1259 } else if (rdev->family == CHIP_R200) {
1260 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1261 RADEON_FP2_DVO_RATE_SEL_SDR);
1263 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1265 if (ASIC_IS_R300(rdev)) {
1266 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1267 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1268 } else if (rdev->family == CHIP_R200) {
1269 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1270 RADEON_FP2_DVO_RATE_SEL_SDR);
1271 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1273 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1275 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1278 if (ASIC_IS_R300(rdev)) {
1279 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1280 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1281 } else if (rdev->family != CHIP_R200)
1282 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1283 else if (rdev->family == CHIP_R200)
1284 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1286 if (rdev->family >= CHIP_R200)
1287 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1290 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1292 if (rdev->is_atom_bios)
1293 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1295 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1299 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1300 struct drm_connector *connector)
1302 struct drm_device *dev = encoder->dev;
1303 struct radeon_device *rdev = dev->dev_private;
1304 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1305 uint32_t disp_output_cntl, gpiopad_a, tmp;
1308 /* save regs needed */
1309 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1310 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1311 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1312 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1313 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1314 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1316 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1318 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1320 WREG32(RADEON_CRTC2_GEN_CNTL,
1321 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1323 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1324 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1325 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1327 WREG32(RADEON_DAC_EXT_CNTL,
1328 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1329 RADEON_DAC2_FORCE_DATA_EN |
1330 RADEON_DAC_FORCE_DATA_SEL_RGB |
1331 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1333 WREG32(RADEON_TV_DAC_CNTL,
1334 RADEON_TV_DAC_STD_NTSC |
1335 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1336 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1338 RREG32(RADEON_TV_DAC_CNTL);
1341 WREG32(RADEON_TV_DAC_CNTL,
1342 RADEON_TV_DAC_NBLANK |
1343 RADEON_TV_DAC_NHOLD |
1344 RADEON_TV_MONITOR_DETECT_EN |
1345 RADEON_TV_DAC_STD_NTSC |
1346 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1347 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1349 RREG32(RADEON_TV_DAC_CNTL);
1352 tmp = RREG32(RADEON_TV_DAC_CNTL);
1353 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1355 DRM_DEBUG_KMS("S-video TV connection detected\n");
1356 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1358 DRM_DEBUG_KMS("Composite TV connection detected\n");
1361 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1362 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1363 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1364 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1365 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1366 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1370 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1371 struct drm_connector *connector)
1373 struct drm_device *dev = encoder->dev;
1374 struct radeon_device *rdev = dev->dev_private;
1375 uint32_t tv_dac_cntl, dac_cntl2;
1376 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1379 if (ASIC_IS_R300(rdev))
1380 return r300_legacy_tv_detect(encoder, connector);
1382 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1383 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1384 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1385 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1386 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1388 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1389 WREG32(RADEON_DAC_CNTL2, tmp);
1391 tmp = tv_master_cntl | RADEON_TV_ON;
1392 tmp &= ~(RADEON_TV_ASYNC_RST |
1393 RADEON_RESTART_PHASE_FIX |
1394 RADEON_CRT_FIFO_CE_EN |
1395 RADEON_TV_FIFO_CE_EN |
1396 RADEON_RE_SYNC_NOW_SEL_MASK);
1397 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1398 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1400 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1401 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1402 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1404 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1405 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1407 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1408 WREG32(RADEON_TV_DAC_CNTL, tmp);
1410 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1411 RADEON_RED_MX_FORCE_DAC_DATA |
1412 RADEON_GRN_MX_FORCE_DAC_DATA |
1413 RADEON_BLU_MX_FORCE_DAC_DATA |
1414 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1415 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1418 tmp = RREG32(RADEON_TV_DAC_CNTL);
1419 if (tmp & RADEON_TV_DAC_GDACDET) {
1421 DRM_DEBUG_KMS("S-video TV connection detected\n");
1422 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1424 DRM_DEBUG_KMS("Composite TV connection detected\n");
1427 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1428 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1429 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1430 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1434 static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder,
1435 struct drm_connector *connector)
1437 struct drm_device *dev = encoder->dev;
1438 struct radeon_device *rdev = dev->dev_private;
1439 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl;
1440 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c;
1441 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f;
1442 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp;
1443 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid;
1447 /* save the regs we need */
1448 gpio_monid = RREG32(RADEON_GPIO_MONID);
1449 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1450 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1451 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1452 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
1453 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
1454 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
1455 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
1456 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
1457 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
1458 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
1459 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
1460 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
1461 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
1463 tmp = RREG32(RADEON_GPIO_MONID);
1464 tmp &= ~RADEON_GPIO_A_0;
1465 WREG32(RADEON_GPIO_MONID, tmp);
1467 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |
1468 RADEON_FP2_PANEL_FORMAT |
1469 R200_FP2_SOURCE_SEL_TRANS_UNIT |
1471 R200_FP2_DVO_RATE_SEL_SDR));
1473 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |
1474 RADEON_DISP_TRANS_MATRIX_GRAPHICS));
1476 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |
1477 RADEON_CRTC2_DISP_REQ_EN_B));
1479 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);
1480 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);
1481 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);
1482 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);
1483 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);
1484 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);
1486 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);
1487 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);
1488 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);
1489 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);
1491 for (i = 0; i < 200; i++) {
1492 tmp = RREG32(RADEON_GPIO_MONID);
1493 if (tmp & RADEON_GPIO_Y_0)
1500 if (!drm_can_sleep())
1506 /* restore the regs we used */
1507 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);
1508 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);
1509 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);
1510 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);
1511 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);
1512 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);
1513 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);
1514 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);
1515 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
1516 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
1517 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1518 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1519 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1520 WREG32(RADEON_GPIO_MONID, gpio_monid);
1525 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1526 struct drm_connector *connector)
1528 struct drm_device *dev = encoder->dev;
1529 struct radeon_device *rdev = dev->dev_private;
1530 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1531 uint32_t gpiopad_a = 0, pixclks_cntl, tmp;
1532 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0;
1533 enum drm_connector_status found = connector_status_disconnected;
1534 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1535 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1537 struct drm_crtc *crtc;
1539 /* find out if crtc2 is in use or if this encoder is using it */
1540 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1541 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1542 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1543 if (encoder->crtc != crtc) {
1544 return connector_status_disconnected;
1549 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1550 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1551 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1554 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1555 return connector_status_disconnected;
1557 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1558 if (tv_detect && tv_dac)
1559 found = connector_status_connected;
1563 /* don't probe if the encoder is being used for something else not CRT related */
1564 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1565 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1566 return connector_status_disconnected;
1569 /* R200 uses an external DAC for secondary DAC */
1570 if (rdev->family == CHIP_R200) {
1571 if (radeon_legacy_ext_dac_detect(encoder, connector))
1572 found = connector_status_connected;
1576 /* save the regs we need */
1577 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1579 if (rdev->flags & RADEON_SINGLE_CRTC) {
1580 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
1582 if (ASIC_IS_R300(rdev)) {
1583 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1584 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1586 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1588 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1590 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1591 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1592 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1594 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1595 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1596 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1598 if (rdev->flags & RADEON_SINGLE_CRTC) {
1599 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
1600 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
1602 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1603 tmp |= RADEON_CRTC2_CRT2_ON |
1604 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1605 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1607 if (ASIC_IS_R300(rdev)) {
1608 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1609 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1610 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1611 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1613 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1614 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1618 tmp = RADEON_TV_DAC_NBLANK |
1619 RADEON_TV_DAC_NHOLD |
1620 RADEON_TV_MONITOR_DETECT_EN |
1621 RADEON_TV_DAC_STD_PS2;
1623 WREG32(RADEON_TV_DAC_CNTL, tmp);
1625 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1626 RADEON_DAC2_FORCE_DATA_EN;
1629 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1631 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1633 if (ASIC_IS_R300(rdev))
1634 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1636 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1638 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1640 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1641 WREG32(RADEON_DAC_CNTL2, tmp);
1645 if (ASIC_IS_R300(rdev)) {
1646 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1647 found = connector_status_connected;
1649 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1650 found = connector_status_connected;
1653 /* restore regs we used */
1654 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1655 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1656 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1658 if (rdev->flags & RADEON_SINGLE_CRTC) {
1659 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
1661 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1662 if (ASIC_IS_R300(rdev)) {
1663 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1664 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1666 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1670 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1676 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1677 .dpms = radeon_legacy_tv_dac_dpms,
1678 .mode_fixup = radeon_legacy_mode_fixup,
1679 .prepare = radeon_legacy_tv_dac_prepare,
1680 .mode_set = radeon_legacy_tv_dac_mode_set,
1681 .commit = radeon_legacy_tv_dac_commit,
1682 .detect = radeon_legacy_tv_dac_detect,
1683 .disable = radeon_legacy_encoder_disable,
1687 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1688 .destroy = radeon_enc_destroy,
1692 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1694 struct drm_device *dev = encoder->base.dev;
1695 struct radeon_device *rdev = dev->dev_private;
1696 struct radeon_encoder_int_tmds *tmds = NULL;
1699 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1704 if (rdev->is_atom_bios)
1705 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1707 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1710 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1715 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1717 struct drm_device *dev = encoder->base.dev;
1718 struct radeon_device *rdev = dev->dev_private;
1719 struct radeon_encoder_ext_tmds *tmds = NULL;
1722 if (rdev->is_atom_bios)
1725 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1730 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1733 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1739 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1741 struct radeon_device *rdev = dev->dev_private;
1742 struct drm_encoder *encoder;
1743 struct radeon_encoder *radeon_encoder;
1745 /* see if we already added it */
1746 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1747 radeon_encoder = to_radeon_encoder(encoder);
1748 if (radeon_encoder->encoder_enum == encoder_enum) {
1749 radeon_encoder->devices |= supported_device;
1756 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1757 if (!radeon_encoder)
1760 encoder = &radeon_encoder->base;
1761 if (rdev->flags & RADEON_SINGLE_CRTC)
1762 encoder->possible_crtcs = 0x1;
1764 encoder->possible_crtcs = 0x3;
1766 radeon_encoder->enc_priv = NULL;
1768 radeon_encoder->encoder_enum = encoder_enum;
1769 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1770 radeon_encoder->devices = supported_device;
1771 radeon_encoder->rmx_type = RMX_OFF;
1773 switch (radeon_encoder->encoder_id) {
1774 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1775 encoder->possible_crtcs = 0x1;
1776 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
1777 DRM_MODE_ENCODER_LVDS, NULL);
1778 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1779 if (rdev->is_atom_bios)
1780 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1782 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1783 radeon_encoder->rmx_type = RMX_FULL;
1785 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1786 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
1787 DRM_MODE_ENCODER_TMDS, NULL);
1788 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1789 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1791 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1792 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
1793 DRM_MODE_ENCODER_DAC, NULL);
1794 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1795 if (rdev->is_atom_bios)
1796 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1798 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1800 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1801 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1802 DRM_MODE_ENCODER_TVDAC, NULL);
1803 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1804 if (rdev->is_atom_bios)
1805 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1807 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1809 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1810 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
1811 DRM_MODE_ENCODER_TMDS, NULL);
1812 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1813 if (!rdev->is_atom_bios)
1814 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);