2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include "radeon_asic.h"
33 #include "rv515_reg_safe.h"
35 /* This files gather functions specifics to: rv515 */
36 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
37 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
38 static void rv515_gpu_init(struct radeon_device *rdev);
40 static const u32 crtc_offsets[2] =
43 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
46 void rv515_debugfs(struct radeon_device *rdev)
48 if (r100_debugfs_rbbm_init(rdev)) {
49 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
51 if (rv515_debugfs_pipes_info_init(rdev)) {
52 DRM_ERROR("Failed to register debugfs file for pipes !\n");
54 if (rv515_debugfs_ga_info_init(rdev)) {
55 DRM_ERROR("Failed to register debugfs file for pipes !\n");
59 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
63 r = radeon_ring_lock(rdev, ring, 64);
67 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
68 radeon_ring_write(ring,
72 ISYNC_CPSCRATCH_IDLEGUI);
73 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
74 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
75 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
76 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
77 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
78 radeon_ring_write(ring, 0);
79 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
80 radeon_ring_write(ring, 0);
81 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
82 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
83 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
84 radeon_ring_write(ring, 0);
85 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
86 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
87 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
88 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
89 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
90 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
91 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
92 radeon_ring_write(ring, 0);
93 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
94 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
95 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
96 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
97 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
98 radeon_ring_write(ring,
105 (6 << MSBD0_Y_SHIFT) |
106 (6 << MSBD0_X_SHIFT)));
107 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
108 radeon_ring_write(ring,
109 ((6 << MS_X3_SHIFT) |
115 (6 << MSBD1_SHIFT)));
116 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
117 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
118 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
119 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
120 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
121 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
122 radeon_ring_write(ring, PACKET0(0x20C8, 0));
123 radeon_ring_write(ring, 0);
124 radeon_ring_unlock_commit(rdev, ring, false);
127 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
132 for (i = 0; i < rdev->usec_timeout; i++) {
134 tmp = RREG32_MC(MC_STATUS);
135 if (tmp & MC_STATUS_IDLE) {
143 void rv515_vga_render_disable(struct radeon_device *rdev)
145 WREG32(R_000300_VGA_RENDER_CONTROL,
146 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
149 static void rv515_gpu_init(struct radeon_device *rdev)
151 unsigned pipe_select_current, gb_pipe_select, tmp;
153 if (r100_gui_wait_for_idle(rdev)) {
154 printk(KERN_WARNING "Failed to wait GUI idle while "
155 "resetting GPU. Bad things might happen.\n");
157 rv515_vga_render_disable(rdev);
158 r420_pipes_init(rdev);
159 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
160 tmp = RREG32(R300_DST_PIPE_CONFIG);
161 pipe_select_current = (tmp >> 2) & 3;
162 tmp = (1 << pipe_select_current) |
163 (((gb_pipe_select >> 8) & 0xF) << 4);
164 WREG32_PLL(0x000D, tmp);
165 if (r100_gui_wait_for_idle(rdev)) {
166 printk(KERN_WARNING "Failed to wait GUI idle while "
167 "resetting GPU. Bad things might happen.\n");
169 if (rv515_mc_wait_for_idle(rdev)) {
170 printk(KERN_WARNING "Failed to wait MC idle while "
171 "programming pipes. Bad things might happen.\n");
175 static void rv515_vram_get_type(struct radeon_device *rdev)
179 rdev->mc.vram_width = 128;
180 rdev->mc.vram_is_ddr = true;
181 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
184 rdev->mc.vram_width = 64;
187 rdev->mc.vram_width = 128;
190 rdev->mc.vram_width = 128;
195 static void rv515_mc_init(struct radeon_device *rdev)
198 rv515_vram_get_type(rdev);
199 r100_vram_init_sizes(rdev);
200 radeon_vram_location(rdev, &rdev->mc, 0);
201 rdev->mc.gtt_base_align = 0;
202 if (!(rdev->flags & RADEON_IS_AGP))
203 radeon_gtt_location(rdev, &rdev->mc);
204 radeon_update_bandwidth_info(rdev);
207 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
212 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
213 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
214 r = RREG32(MC_IND_DATA);
215 WREG32(MC_IND_INDEX, 0);
216 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
221 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
225 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
226 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
227 WREG32(MC_IND_DATA, (v));
228 WREG32(MC_IND_INDEX, 0);
229 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
232 #if defined(CONFIG_DEBUG_FS)
233 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
235 struct drm_info_node *node = (struct drm_info_node *) m->private;
236 struct drm_device *dev = node->minor->dev;
237 struct radeon_device *rdev = dev->dev_private;
240 tmp = RREG32(GB_PIPE_SELECT);
241 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
242 tmp = RREG32(SU_REG_DEST);
243 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
244 tmp = RREG32(GB_TILE_CONFIG);
245 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
246 tmp = RREG32(DST_PIPE_CONFIG);
247 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
251 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
253 struct drm_info_node *node = (struct drm_info_node *) m->private;
254 struct drm_device *dev = node->minor->dev;
255 struct radeon_device *rdev = dev->dev_private;
258 tmp = RREG32(0x2140);
259 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
260 radeon_asic_reset(rdev);
261 tmp = RREG32(0x425C);
262 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
266 static struct drm_info_list rv515_pipes_info_list[] = {
267 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
270 static struct drm_info_list rv515_ga_info_list[] = {
271 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
275 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
277 #if defined(CONFIG_DEBUG_FS)
278 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
284 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
286 #if defined(CONFIG_DEBUG_FS)
287 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
293 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
295 u32 crtc_enabled, tmp, frame_count, blackout;
298 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
299 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
301 /* disable VGA render */
302 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
303 /* blank the display controllers */
304 for (i = 0; i < rdev->num_crtc; i++) {
305 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
307 save->crtc_enabled[i] = true;
308 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
309 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
310 radeon_wait_for_vblank(rdev, i);
311 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
312 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
313 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
314 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
316 /* wait for the next frame */
317 frame_count = radeon_get_vblank_counter(rdev, i);
318 for (j = 0; j < rdev->usec_timeout; j++) {
319 if (radeon_get_vblank_counter(rdev, i) != frame_count)
324 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
325 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
326 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
327 tmp &= ~AVIVO_CRTC_EN;
328 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
329 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
330 save->crtc_enabled[i] = false;
333 save->crtc_enabled[i] = false;
337 radeon_mc_wait_for_idle(rdev);
339 if (rdev->family >= CHIP_R600) {
340 if (rdev->family >= CHIP_RV770)
341 blackout = RREG32(R700_MC_CITF_CNTL);
343 blackout = RREG32(R600_CITF_CNTL);
344 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
345 /* Block CPU access */
346 WREG32(R600_BIF_FB_EN, 0);
347 /* blackout the MC */
348 blackout |= R600_BLACKOUT_MASK;
349 if (rdev->family >= CHIP_RV770)
350 WREG32(R700_MC_CITF_CNTL, blackout);
352 WREG32(R600_CITF_CNTL, blackout);
355 /* wait for the MC to settle */
358 /* lock double buffered regs */
359 for (i = 0; i < rdev->num_crtc; i++) {
360 if (save->crtc_enabled[i]) {
361 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
362 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
363 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
364 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
366 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
369 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
375 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
377 u32 tmp, frame_count;
380 /* update crtc base addresses */
381 for (i = 0; i < rdev->num_crtc; i++) {
382 if (rdev->family >= CHIP_RV770) {
384 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
385 upper_32_bits(rdev->mc.vram_start));
386 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
387 upper_32_bits(rdev->mc.vram_start));
389 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
390 upper_32_bits(rdev->mc.vram_start));
391 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
392 upper_32_bits(rdev->mc.vram_start));
395 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
396 (u32)rdev->mc.vram_start);
397 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
398 (u32)rdev->mc.vram_start);
400 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
402 /* unlock regs and wait for update */
403 for (i = 0; i < rdev->num_crtc; i++) {
404 if (save->crtc_enabled[i]) {
405 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
406 if ((tmp & 0x7) != 3) {
409 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
411 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
412 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
413 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
414 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
416 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
419 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
421 for (j = 0; j < rdev->usec_timeout; j++) {
422 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
423 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
430 if (rdev->family >= CHIP_R600) {
431 /* unblackout the MC */
432 if (rdev->family >= CHIP_RV770)
433 tmp = RREG32(R700_MC_CITF_CNTL);
435 tmp = RREG32(R600_CITF_CNTL);
436 tmp &= ~R600_BLACKOUT_MASK;
437 if (rdev->family >= CHIP_RV770)
438 WREG32(R700_MC_CITF_CNTL, tmp);
440 WREG32(R600_CITF_CNTL, tmp);
441 /* allow CPU access */
442 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
445 for (i = 0; i < rdev->num_crtc; i++) {
446 if (save->crtc_enabled[i]) {
447 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
448 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
449 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
450 /* wait for the next frame */
451 frame_count = radeon_get_vblank_counter(rdev, i);
452 for (j = 0; j < rdev->usec_timeout; j++) {
453 if (radeon_get_vblank_counter(rdev, i) != frame_count)
459 /* Unlock vga access */
460 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
462 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
465 static void rv515_mc_program(struct radeon_device *rdev)
467 struct rv515_mc_save save;
469 /* Stops all mc clients */
470 rv515_mc_stop(rdev, &save);
472 /* Wait for mc idle */
473 if (rv515_mc_wait_for_idle(rdev))
474 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
475 /* Write VRAM size in case we are limiting it */
476 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
477 /* Program MC, should be a 32bits limited address space */
478 WREG32_MC(R_000001_MC_FB_LOCATION,
479 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
480 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
481 WREG32(R_000134_HDP_FB_LOCATION,
482 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
483 if (rdev->flags & RADEON_IS_AGP) {
484 WREG32_MC(R_000002_MC_AGP_LOCATION,
485 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
486 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
487 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
488 WREG32_MC(R_000004_MC_AGP_BASE_2,
489 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
491 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
492 WREG32_MC(R_000003_MC_AGP_BASE, 0);
493 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
496 rv515_mc_resume(rdev, &save);
499 void rv515_clock_startup(struct radeon_device *rdev)
501 if (radeon_dynclks != -1 && radeon_dynclks)
502 radeon_atom_set_clock_gating(rdev, 1);
503 /* We need to force on some of the block */
504 WREG32_PLL(R_00000F_CP_DYN_CNTL,
505 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
506 WREG32_PLL(R_000011_E2_DYN_CNTL,
507 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
508 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
509 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
512 static int rv515_startup(struct radeon_device *rdev)
516 rv515_mc_program(rdev);
518 rv515_clock_startup(rdev);
519 /* Initialize GPU configuration (# pipes, ...) */
520 rv515_gpu_init(rdev);
521 /* Initialize GART (initialize after TTM so we can allocate
522 * memory through TTM but finalize after TTM) */
523 if (rdev->flags & RADEON_IS_PCIE) {
524 r = rv370_pcie_gart_enable(rdev);
529 /* allocate wb buffer */
530 r = radeon_wb_init(rdev);
534 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
536 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
541 if (!rdev->irq.installed) {
542 r = radeon_irq_kms_init(rdev);
548 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
550 r = r100_cp_init(rdev, 1024 * 1024);
552 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
556 r = radeon_ib_pool_init(rdev);
558 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
565 int rv515_resume(struct radeon_device *rdev)
569 /* Make sur GART are not working */
570 if (rdev->flags & RADEON_IS_PCIE)
571 rv370_pcie_gart_disable(rdev);
572 /* Resume clock before doing reset */
573 rv515_clock_startup(rdev);
574 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
575 if (radeon_asic_reset(rdev)) {
576 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
577 RREG32(R_000E40_RBBM_STATUS),
578 RREG32(R_0007C0_CP_STAT));
581 atom_asic_init(rdev->mode_info.atom_context);
582 /* Resume clock after posting */
583 rv515_clock_startup(rdev);
584 /* Initialize surface registers */
585 radeon_surface_init(rdev);
587 rdev->accel_working = true;
588 r = rv515_startup(rdev);
590 rdev->accel_working = false;
595 int rv515_suspend(struct radeon_device *rdev)
597 radeon_pm_suspend(rdev);
598 r100_cp_disable(rdev);
599 radeon_wb_disable(rdev);
600 rs600_irq_disable(rdev);
601 if (rdev->flags & RADEON_IS_PCIE)
602 rv370_pcie_gart_disable(rdev);
606 void rv515_set_safe_registers(struct radeon_device *rdev)
608 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
609 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
612 void rv515_fini(struct radeon_device *rdev)
614 radeon_pm_fini(rdev);
616 radeon_wb_fini(rdev);
617 radeon_ib_pool_fini(rdev);
618 radeon_gem_fini(rdev);
619 rv370_pcie_gart_fini(rdev);
620 radeon_agp_fini(rdev);
621 radeon_irq_kms_fini(rdev);
622 radeon_fence_driver_fini(rdev);
623 radeon_bo_fini(rdev);
624 radeon_atombios_fini(rdev);
629 int rv515_init(struct radeon_device *rdev)
633 /* Initialize scratch registers */
634 radeon_scratch_init(rdev);
635 /* Initialize surface registers */
636 radeon_surface_init(rdev);
637 /* TODO: disable VGA need to use VGA request */
638 /* restore some register to sane defaults */
639 r100_restore_sanity(rdev);
641 if (!radeon_get_bios(rdev)) {
642 if (ASIC_IS_AVIVO(rdev))
645 if (rdev->is_atom_bios) {
646 r = radeon_atombios_init(rdev);
650 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
653 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
654 if (radeon_asic_reset(rdev)) {
656 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
657 RREG32(R_000E40_RBBM_STATUS),
658 RREG32(R_0007C0_CP_STAT));
660 /* check if cards are posted or not */
661 if (radeon_boot_test_post_card(rdev) == false)
663 /* Initialize clocks */
664 radeon_get_clock_info(rdev->ddev);
666 if (rdev->flags & RADEON_IS_AGP) {
667 r = radeon_agp_init(rdev);
669 radeon_agp_disable(rdev);
672 /* initialize memory controller */
676 r = radeon_fence_driver_init(rdev);
680 r = radeon_bo_init(rdev);
683 r = rv370_pcie_gart_init(rdev);
686 rv515_set_safe_registers(rdev);
688 /* Initialize power management */
689 radeon_pm_init(rdev);
691 rdev->accel_working = true;
692 r = rv515_startup(rdev);
694 /* Somethings want wront with the accel init stop accel */
695 dev_err(rdev->dev, "Disabling GPU acceleration\n");
697 radeon_wb_fini(rdev);
698 radeon_ib_pool_fini(rdev);
699 radeon_irq_kms_fini(rdev);
700 rv370_pcie_gart_fini(rdev);
701 radeon_agp_fini(rdev);
702 rdev->accel_working = false;
707 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
709 int index_reg = 0x6578 + crtc->crtc_offset;
710 int data_reg = 0x657c + crtc->crtc_offset;
712 WREG32(0x659C + crtc->crtc_offset, 0x0);
713 WREG32(0x6594 + crtc->crtc_offset, 0x705);
714 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
715 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
716 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
717 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
718 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
719 WREG32(index_reg, 0x0);
720 WREG32(data_reg, 0x841880A8);
721 WREG32(index_reg, 0x1);
722 WREG32(data_reg, 0x84208680);
723 WREG32(index_reg, 0x2);
724 WREG32(data_reg, 0xBFF880B0);
725 WREG32(index_reg, 0x100);
726 WREG32(data_reg, 0x83D88088);
727 WREG32(index_reg, 0x101);
728 WREG32(data_reg, 0x84608680);
729 WREG32(index_reg, 0x102);
730 WREG32(data_reg, 0xBFF080D0);
731 WREG32(index_reg, 0x200);
732 WREG32(data_reg, 0x83988068);
733 WREG32(index_reg, 0x201);
734 WREG32(data_reg, 0x84A08680);
735 WREG32(index_reg, 0x202);
736 WREG32(data_reg, 0xBFF080F8);
737 WREG32(index_reg, 0x300);
738 WREG32(data_reg, 0x83588058);
739 WREG32(index_reg, 0x301);
740 WREG32(data_reg, 0x84E08660);
741 WREG32(index_reg, 0x302);
742 WREG32(data_reg, 0xBFF88120);
743 WREG32(index_reg, 0x400);
744 WREG32(data_reg, 0x83188040);
745 WREG32(index_reg, 0x401);
746 WREG32(data_reg, 0x85008660);
747 WREG32(index_reg, 0x402);
748 WREG32(data_reg, 0xBFF88150);
749 WREG32(index_reg, 0x500);
750 WREG32(data_reg, 0x82D88030);
751 WREG32(index_reg, 0x501);
752 WREG32(data_reg, 0x85408640);
753 WREG32(index_reg, 0x502);
754 WREG32(data_reg, 0xBFF88180);
755 WREG32(index_reg, 0x600);
756 WREG32(data_reg, 0x82A08018);
757 WREG32(index_reg, 0x601);
758 WREG32(data_reg, 0x85808620);
759 WREG32(index_reg, 0x602);
760 WREG32(data_reg, 0xBFF081B8);
761 WREG32(index_reg, 0x700);
762 WREG32(data_reg, 0x82608010);
763 WREG32(index_reg, 0x701);
764 WREG32(data_reg, 0x85A08600);
765 WREG32(index_reg, 0x702);
766 WREG32(data_reg, 0x800081F0);
767 WREG32(index_reg, 0x800);
768 WREG32(data_reg, 0x8228BFF8);
769 WREG32(index_reg, 0x801);
770 WREG32(data_reg, 0x85E085E0);
771 WREG32(index_reg, 0x802);
772 WREG32(data_reg, 0xBFF88228);
773 WREG32(index_reg, 0x10000);
774 WREG32(data_reg, 0x82A8BF00);
775 WREG32(index_reg, 0x10001);
776 WREG32(data_reg, 0x82A08CC0);
777 WREG32(index_reg, 0x10002);
778 WREG32(data_reg, 0x8008BEF8);
779 WREG32(index_reg, 0x10100);
780 WREG32(data_reg, 0x81F0BF28);
781 WREG32(index_reg, 0x10101);
782 WREG32(data_reg, 0x83608CA0);
783 WREG32(index_reg, 0x10102);
784 WREG32(data_reg, 0x8018BED0);
785 WREG32(index_reg, 0x10200);
786 WREG32(data_reg, 0x8148BF38);
787 WREG32(index_reg, 0x10201);
788 WREG32(data_reg, 0x84408C80);
789 WREG32(index_reg, 0x10202);
790 WREG32(data_reg, 0x8008BEB8);
791 WREG32(index_reg, 0x10300);
792 WREG32(data_reg, 0x80B0BF78);
793 WREG32(index_reg, 0x10301);
794 WREG32(data_reg, 0x85008C20);
795 WREG32(index_reg, 0x10302);
796 WREG32(data_reg, 0x8020BEA0);
797 WREG32(index_reg, 0x10400);
798 WREG32(data_reg, 0x8028BF90);
799 WREG32(index_reg, 0x10401);
800 WREG32(data_reg, 0x85E08BC0);
801 WREG32(index_reg, 0x10402);
802 WREG32(data_reg, 0x8018BE90);
803 WREG32(index_reg, 0x10500);
804 WREG32(data_reg, 0xBFB8BFB0);
805 WREG32(index_reg, 0x10501);
806 WREG32(data_reg, 0x86C08B40);
807 WREG32(index_reg, 0x10502);
808 WREG32(data_reg, 0x8010BE90);
809 WREG32(index_reg, 0x10600);
810 WREG32(data_reg, 0xBF58BFC8);
811 WREG32(index_reg, 0x10601);
812 WREG32(data_reg, 0x87A08AA0);
813 WREG32(index_reg, 0x10602);
814 WREG32(data_reg, 0x8010BE98);
815 WREG32(index_reg, 0x10700);
816 WREG32(data_reg, 0xBF10BFF0);
817 WREG32(index_reg, 0x10701);
818 WREG32(data_reg, 0x886089E0);
819 WREG32(index_reg, 0x10702);
820 WREG32(data_reg, 0x8018BEB0);
821 WREG32(index_reg, 0x10800);
822 WREG32(data_reg, 0xBED8BFE8);
823 WREG32(index_reg, 0x10801);
824 WREG32(data_reg, 0x89408940);
825 WREG32(index_reg, 0x10802);
826 WREG32(data_reg, 0xBFE8BED8);
827 WREG32(index_reg, 0x20000);
828 WREG32(data_reg, 0x80008000);
829 WREG32(index_reg, 0x20001);
830 WREG32(data_reg, 0x90008000);
831 WREG32(index_reg, 0x20002);
832 WREG32(data_reg, 0x80008000);
833 WREG32(index_reg, 0x20003);
834 WREG32(data_reg, 0x80008000);
835 WREG32(index_reg, 0x20100);
836 WREG32(data_reg, 0x80108000);
837 WREG32(index_reg, 0x20101);
838 WREG32(data_reg, 0x8FE0BF70);
839 WREG32(index_reg, 0x20102);
840 WREG32(data_reg, 0xBFE880C0);
841 WREG32(index_reg, 0x20103);
842 WREG32(data_reg, 0x80008000);
843 WREG32(index_reg, 0x20200);
844 WREG32(data_reg, 0x8018BFF8);
845 WREG32(index_reg, 0x20201);
846 WREG32(data_reg, 0x8F80BF08);
847 WREG32(index_reg, 0x20202);
848 WREG32(data_reg, 0xBFD081A0);
849 WREG32(index_reg, 0x20203);
850 WREG32(data_reg, 0xBFF88000);
851 WREG32(index_reg, 0x20300);
852 WREG32(data_reg, 0x80188000);
853 WREG32(index_reg, 0x20301);
854 WREG32(data_reg, 0x8EE0BEC0);
855 WREG32(index_reg, 0x20302);
856 WREG32(data_reg, 0xBFB082A0);
857 WREG32(index_reg, 0x20303);
858 WREG32(data_reg, 0x80008000);
859 WREG32(index_reg, 0x20400);
860 WREG32(data_reg, 0x80188000);
861 WREG32(index_reg, 0x20401);
862 WREG32(data_reg, 0x8E00BEA0);
863 WREG32(index_reg, 0x20402);
864 WREG32(data_reg, 0xBF8883C0);
865 WREG32(index_reg, 0x20403);
866 WREG32(data_reg, 0x80008000);
867 WREG32(index_reg, 0x20500);
868 WREG32(data_reg, 0x80188000);
869 WREG32(index_reg, 0x20501);
870 WREG32(data_reg, 0x8D00BE90);
871 WREG32(index_reg, 0x20502);
872 WREG32(data_reg, 0xBF588500);
873 WREG32(index_reg, 0x20503);
874 WREG32(data_reg, 0x80008008);
875 WREG32(index_reg, 0x20600);
876 WREG32(data_reg, 0x80188000);
877 WREG32(index_reg, 0x20601);
878 WREG32(data_reg, 0x8BC0BE98);
879 WREG32(index_reg, 0x20602);
880 WREG32(data_reg, 0xBF308660);
881 WREG32(index_reg, 0x20603);
882 WREG32(data_reg, 0x80008008);
883 WREG32(index_reg, 0x20700);
884 WREG32(data_reg, 0x80108000);
885 WREG32(index_reg, 0x20701);
886 WREG32(data_reg, 0x8A80BEB0);
887 WREG32(index_reg, 0x20702);
888 WREG32(data_reg, 0xBF0087C0);
889 WREG32(index_reg, 0x20703);
890 WREG32(data_reg, 0x80008008);
891 WREG32(index_reg, 0x20800);
892 WREG32(data_reg, 0x80108000);
893 WREG32(index_reg, 0x20801);
894 WREG32(data_reg, 0x8920BED0);
895 WREG32(index_reg, 0x20802);
896 WREG32(data_reg, 0xBED08920);
897 WREG32(index_reg, 0x20803);
898 WREG32(data_reg, 0x80008010);
899 WREG32(index_reg, 0x30000);
900 WREG32(data_reg, 0x90008000);
901 WREG32(index_reg, 0x30001);
902 WREG32(data_reg, 0x80008000);
903 WREG32(index_reg, 0x30100);
904 WREG32(data_reg, 0x8FE0BF90);
905 WREG32(index_reg, 0x30101);
906 WREG32(data_reg, 0xBFF880A0);
907 WREG32(index_reg, 0x30200);
908 WREG32(data_reg, 0x8F60BF40);
909 WREG32(index_reg, 0x30201);
910 WREG32(data_reg, 0xBFE88180);
911 WREG32(index_reg, 0x30300);
912 WREG32(data_reg, 0x8EC0BF00);
913 WREG32(index_reg, 0x30301);
914 WREG32(data_reg, 0xBFC88280);
915 WREG32(index_reg, 0x30400);
916 WREG32(data_reg, 0x8DE0BEE0);
917 WREG32(index_reg, 0x30401);
918 WREG32(data_reg, 0xBFA083A0);
919 WREG32(index_reg, 0x30500);
920 WREG32(data_reg, 0x8CE0BED0);
921 WREG32(index_reg, 0x30501);
922 WREG32(data_reg, 0xBF7884E0);
923 WREG32(index_reg, 0x30600);
924 WREG32(data_reg, 0x8BA0BED8);
925 WREG32(index_reg, 0x30601);
926 WREG32(data_reg, 0xBF508640);
927 WREG32(index_reg, 0x30700);
928 WREG32(data_reg, 0x8A60BEE8);
929 WREG32(index_reg, 0x30701);
930 WREG32(data_reg, 0xBF2087A0);
931 WREG32(index_reg, 0x30800);
932 WREG32(data_reg, 0x8900BF00);
933 WREG32(index_reg, 0x30801);
934 WREG32(data_reg, 0xBF008900);
937 struct rv515_watermark {
938 u32 lb_request_fifo_depth;
939 fixed20_12 num_line_pair;
940 fixed20_12 estimated_width;
941 fixed20_12 worst_case_latency;
942 fixed20_12 consumption_rate;
943 fixed20_12 active_time;
945 fixed20_12 priority_mark_max;
946 fixed20_12 priority_mark;
950 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
951 struct radeon_crtc *crtc,
952 struct rv515_watermark *wm,
955 struct drm_display_mode *mode = &crtc->base.mode;
957 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
958 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
962 bzero(wm, sizeof(*wm)); /* avoid gcc warning */
963 if (!crtc->base.enabled) {
964 /* FIXME: wouldn't it better to set priority mark to maximum */
965 wm->lb_request_fifo_depth = 4;
970 if ((rdev->family >= CHIP_RV610) &&
971 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
972 selected_sclk = radeon_dpm_get_sclk(rdev, low);
974 selected_sclk = rdev->pm.current_sclk;
977 a.full = dfixed_const(100);
978 sclk.full = dfixed_const(selected_sclk);
979 sclk.full = dfixed_div(sclk, a);
981 if (crtc->vsc.full > dfixed_const(2))
982 wm->num_line_pair.full = dfixed_const(2);
984 wm->num_line_pair.full = dfixed_const(1);
986 b.full = dfixed_const(mode->crtc_hdisplay);
987 c.full = dfixed_const(256);
988 a.full = dfixed_div(b, c);
989 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
990 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
991 if (a.full < dfixed_const(4)) {
992 wm->lb_request_fifo_depth = 4;
994 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
997 /* Determine consumption rate
998 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
999 * vtaps = number of vertical taps,
1000 * vsc = vertical scaling ratio, defined as source/destination
1001 * hsc = horizontal scaling ration, defined as source/destination
1003 a.full = dfixed_const(mode->clock);
1004 b.full = dfixed_const(1000);
1005 a.full = dfixed_div(a, b);
1006 pclk.full = dfixed_div(b, a);
1007 if (crtc->rmx_type != RMX_OFF) {
1008 b.full = dfixed_const(2);
1009 if (crtc->vsc.full > b.full)
1010 b.full = crtc->vsc.full;
1011 b.full = dfixed_mul(b, crtc->hsc);
1012 c.full = dfixed_const(2);
1013 b.full = dfixed_div(b, c);
1014 consumption_time.full = dfixed_div(pclk, b);
1016 consumption_time.full = pclk.full;
1018 a.full = dfixed_const(1);
1019 wm->consumption_rate.full = dfixed_div(a, consumption_time);
1022 /* Determine line time
1023 * LineTime = total time for one line of displayhtotal
1024 * LineTime = total number of horizontal pixels
1025 * pclk = pixel clock period(ns)
1027 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1028 line_time.full = dfixed_mul(a, pclk);
1030 /* Determine active time
1031 * ActiveTime = time of active region of display within one line,
1032 * hactive = total number of horizontal active pixels
1033 * htotal = total number of horizontal pixels
1035 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1036 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1037 wm->active_time.full = dfixed_mul(line_time, b);
1038 wm->active_time.full = dfixed_div(wm->active_time, a);
1040 /* Determine chunk time
1041 * ChunkTime = the time it takes the DCP to send one chunk of data
1042 * to the LB which consists of pipeline delay and inter chunk gap
1043 * sclk = system clock(Mhz)
1045 a.full = dfixed_const(600 * 1000);
1046 chunk_time.full = dfixed_div(a, sclk);
1047 read_delay_latency.full = dfixed_const(1000);
1049 /* Determine the worst case latency
1050 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1051 * WorstCaseLatency = worst case time from urgent to when the MC starts
1053 * READ_DELAY_IDLE_MAX = constant of 1us
1054 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1055 * which consists of pipeline delay and inter chunk gap
1057 if (dfixed_trunc(wm->num_line_pair) > 1) {
1058 a.full = dfixed_const(3);
1059 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1060 wm->worst_case_latency.full += read_delay_latency.full;
1062 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1065 /* Determine the tolerable latency
1066 * TolerableLatency = Any given request has only 1 line time
1067 * for the data to be returned
1068 * LBRequestFifoDepth = Number of chunk requests the LB can
1069 * put into the request FIFO for a display
1070 * LineTime = total time for one line of display
1071 * ChunkTime = the time it takes the DCP to send one chunk
1072 * of data to the LB which consists of
1073 * pipeline delay and inter chunk gap
1075 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1076 tolerable_latency.full = line_time.full;
1078 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1079 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1080 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1081 tolerable_latency.full = line_time.full - tolerable_latency.full;
1083 /* We assume worst case 32bits (4 bytes) */
1084 wm->dbpp.full = dfixed_const(2 * 16);
1086 /* Determine the maximum priority mark
1087 * width = viewport width in pixels
1089 a.full = dfixed_const(16);
1090 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1091 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1092 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1094 /* Determine estimated width */
1095 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1096 estimated_width.full = dfixed_div(estimated_width, consumption_time);
1097 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1098 wm->priority_mark.full = wm->priority_mark_max.full;
1100 a.full = dfixed_const(16);
1101 wm->priority_mark.full = dfixed_div(estimated_width, a);
1102 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1103 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1107 static void rv515_compute_mode_priority(struct radeon_device *rdev,
1108 struct rv515_watermark *wm0,
1109 struct rv515_watermark *wm1,
1110 struct drm_display_mode *mode0,
1111 struct drm_display_mode *mode1,
1112 u32 *d1mode_priority_a_cnt,
1113 u32 *d2mode_priority_a_cnt)
1115 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1118 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1119 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1121 if (mode0 && mode1) {
1122 if (dfixed_trunc(wm0->dbpp) > 64)
1123 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1125 a.full = wm0->num_line_pair.full;
1126 if (dfixed_trunc(wm1->dbpp) > 64)
1127 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1129 b.full = wm1->num_line_pair.full;
1131 fill_rate.full = dfixed_div(wm0->sclk, a);
1132 if (wm0->consumption_rate.full > fill_rate.full) {
1133 b.full = wm0->consumption_rate.full - fill_rate.full;
1134 b.full = dfixed_mul(b, wm0->active_time);
1135 a.full = dfixed_const(16);
1136 b.full = dfixed_div(b, a);
1137 a.full = dfixed_mul(wm0->worst_case_latency,
1138 wm0->consumption_rate);
1139 priority_mark02.full = a.full + b.full;
1141 a.full = dfixed_mul(wm0->worst_case_latency,
1142 wm0->consumption_rate);
1143 b.full = dfixed_const(16 * 1000);
1144 priority_mark02.full = dfixed_div(a, b);
1146 if (wm1->consumption_rate.full > fill_rate.full) {
1147 b.full = wm1->consumption_rate.full - fill_rate.full;
1148 b.full = dfixed_mul(b, wm1->active_time);
1149 a.full = dfixed_const(16);
1150 b.full = dfixed_div(b, a);
1151 a.full = dfixed_mul(wm1->worst_case_latency,
1152 wm1->consumption_rate);
1153 priority_mark12.full = a.full + b.full;
1155 a.full = dfixed_mul(wm1->worst_case_latency,
1156 wm1->consumption_rate);
1157 b.full = dfixed_const(16 * 1000);
1158 priority_mark12.full = dfixed_div(a, b);
1160 if (wm0->priority_mark.full > priority_mark02.full)
1161 priority_mark02.full = wm0->priority_mark.full;
1162 if (wm0->priority_mark_max.full > priority_mark02.full)
1163 priority_mark02.full = wm0->priority_mark_max.full;
1164 if (wm1->priority_mark.full > priority_mark12.full)
1165 priority_mark12.full = wm1->priority_mark.full;
1166 if (wm1->priority_mark_max.full > priority_mark12.full)
1167 priority_mark12.full = wm1->priority_mark_max.full;
1168 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1169 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1170 if (rdev->disp_priority == 2) {
1171 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1172 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1175 if (dfixed_trunc(wm0->dbpp) > 64)
1176 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1178 a.full = wm0->num_line_pair.full;
1179 fill_rate.full = dfixed_div(wm0->sclk, a);
1180 if (wm0->consumption_rate.full > fill_rate.full) {
1181 b.full = wm0->consumption_rate.full - fill_rate.full;
1182 b.full = dfixed_mul(b, wm0->active_time);
1183 a.full = dfixed_const(16);
1184 b.full = dfixed_div(b, a);
1185 a.full = dfixed_mul(wm0->worst_case_latency,
1186 wm0->consumption_rate);
1187 priority_mark02.full = a.full + b.full;
1189 a.full = dfixed_mul(wm0->worst_case_latency,
1190 wm0->consumption_rate);
1191 b.full = dfixed_const(16);
1192 priority_mark02.full = dfixed_div(a, b);
1194 if (wm0->priority_mark.full > priority_mark02.full)
1195 priority_mark02.full = wm0->priority_mark.full;
1196 if (wm0->priority_mark_max.full > priority_mark02.full)
1197 priority_mark02.full = wm0->priority_mark_max.full;
1198 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1199 if (rdev->disp_priority == 2)
1200 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1202 if (dfixed_trunc(wm1->dbpp) > 64)
1203 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1205 a.full = wm1->num_line_pair.full;
1206 fill_rate.full = dfixed_div(wm1->sclk, a);
1207 if (wm1->consumption_rate.full > fill_rate.full) {
1208 b.full = wm1->consumption_rate.full - fill_rate.full;
1209 b.full = dfixed_mul(b, wm1->active_time);
1210 a.full = dfixed_const(16);
1211 b.full = dfixed_div(b, a);
1212 a.full = dfixed_mul(wm1->worst_case_latency,
1213 wm1->consumption_rate);
1214 priority_mark12.full = a.full + b.full;
1216 a.full = dfixed_mul(wm1->worst_case_latency,
1217 wm1->consumption_rate);
1218 b.full = dfixed_const(16 * 1000);
1219 priority_mark12.full = dfixed_div(a, b);
1221 if (wm1->priority_mark.full > priority_mark12.full)
1222 priority_mark12.full = wm1->priority_mark.full;
1223 if (wm1->priority_mark_max.full > priority_mark12.full)
1224 priority_mark12.full = wm1->priority_mark_max.full;
1225 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1226 if (rdev->disp_priority == 2)
1227 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1231 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1233 struct drm_display_mode *mode0 = NULL;
1234 struct drm_display_mode *mode1 = NULL;
1235 struct rv515_watermark wm0_high, wm0_low;
1236 struct rv515_watermark wm1_high, wm1_low;
1238 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
1239 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1241 if (rdev->mode_info.crtcs[0]->base.enabled)
1242 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1243 if (rdev->mode_info.crtcs[1]->base.enabled)
1244 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1245 rs690_line_buffer_adjust(rdev, mode0, mode1);
1247 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
1248 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1250 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
1251 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
1253 tmp = wm0_high.lb_request_fifo_depth;
1254 tmp |= wm1_high.lb_request_fifo_depth << 16;
1255 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1257 rv515_compute_mode_priority(rdev,
1258 &wm0_high, &wm1_high,
1260 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
1261 rv515_compute_mode_priority(rdev,
1264 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1266 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1267 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
1268 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1269 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
1272 void rv515_bandwidth_update(struct radeon_device *rdev)
1275 struct drm_display_mode *mode0 = NULL;
1276 struct drm_display_mode *mode1 = NULL;
1278 if (!rdev->mode_info.mode_config_initialized)
1281 radeon_update_display_priority(rdev);
1283 if (rdev->mode_info.crtcs[0]->base.enabled)
1284 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1285 if (rdev->mode_info.crtcs[1]->base.enabled)
1286 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1288 * Set display0/1 priority up in the memory controller for
1289 * modes if the user specifies HIGH for displaypriority
1292 if ((rdev->disp_priority == 2) &&
1293 (rdev->family == CHIP_RV515)) {
1294 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1295 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1296 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1298 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1300 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1301 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1303 rv515_bandwidth_avivo_update(rdev);