2 * Copyright (c) 1998 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/i386/include/atomic.h,v 1.9.2.1 2000/07/07 00:38:47 obrien Exp $
27 * $DragonFly: src/sys/cpu/i386/include/atomic.h,v 1.15 2005/10/13 00:02:46 dillon Exp $
29 #ifndef _MACHINE_ATOMIC_H_
30 #define _MACHINE_ATOMIC_H_
33 * Various simple arithmetic on memory which is atomic in the presence
34 * of interrupts and multiple processors.
36 * atomic_set_char(P, V) (*(u_char*)(P) |= (V))
37 * atomic_clear_char(P, V) (*(u_char*)(P) &= ~(V))
38 * atomic_add_char(P, V) (*(u_char*)(P) += (V))
39 * atomic_subtract_char(P, V) (*(u_char*)(P) -= (V))
41 * atomic_set_short(P, V) (*(u_short*)(P) |= (V))
42 * atomic_clear_short(P, V) (*(u_short*)(P) &= ~(V))
43 * atomic_add_short(P, V) (*(u_short*)(P) += (V))
44 * atomic_subtract_short(P, V) (*(u_short*)(P) -= (V))
46 * atomic_set_int(P, V) (*(u_int*)(P) |= (V))
47 * atomic_clear_int(P, V) (*(u_int*)(P) &= ~(V))
48 * atomic_add_int(P, V) (*(u_int*)(P) += (V))
49 * atomic_subtract_int(P, V) (*(u_int*)(P) -= (V))
51 * atomic_set_long(P, V) (*(u_long*)(P) |= (V))
52 * atomic_clear_long(P, V) (*(u_long*)(P) &= ~(V))
53 * atomic_add_long(P, V) (*(u_long*)(P) += (V))
54 * atomic_subtract_long(P, V) (*(u_long*)(P) -= (V))
58 * The above functions are expanded inline in the statically-linked
59 * kernel. Lock prefixes are generated if an SMP kernel is being
62 * Kernel modules call real functions which are built into the kernel.
63 * This allows kernel modules to be portable between UP and SMP systems.
65 #if defined(KLD_MODULE)
66 #define ATOMIC_ASM(NAME, TYPE, OP, V) \
67 extern void atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v); \
68 extern void atomic_##NAME##_##TYPE##_nonlocked(volatile u_##TYPE *p, u_##TYPE v);
69 #else /* !KLD_MODULE */
71 #define MPLOCKED "lock ; "
77 * The assembly is volatilized to demark potential before-and-after side
78 * effects if an interrupt or SMP collision were to occur. The primary
79 * atomic instructions are MP safe, the nonlocked instructions are
80 * local-interrupt-safe (so we don't depend on C 'X |= Y' generating an
81 * atomic instruction).
83 * +m - memory is read and written (=m - memory is only written)
84 * iq - integer constant or %ax/%bx/%cx/%dx (ir = int constant or any reg)
85 * (Note: byte instructions only work on %ax,%bx,%cx, or %dx). iq
86 * is good enough for our needs so don't get fancy.
89 /* egcs 1.1.2+ version */
90 #define ATOMIC_ASM(NAME, TYPE, OP, V) \
91 static __inline void \
92 atomic_##NAME##_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
94 __asm __volatile(MPLOCKED OP \
98 static __inline void \
99 atomic_##NAME##_##TYPE##_nonlocked(volatile u_##TYPE *p, u_##TYPE v)\
101 __asm __volatile(OP \
106 #endif /* KLD_MODULE */
108 /* egcs 1.1.2+ version */
109 ATOMIC_ASM(set, char, "orb %b1,%0", v)
110 ATOMIC_ASM(clear, char, "andb %b1,%0", ~v)
111 ATOMIC_ASM(add, char, "addb %b1,%0", v)
112 ATOMIC_ASM(subtract, char, "subb %b1,%0", v)
114 ATOMIC_ASM(set, short, "orw %w1,%0", v)
115 ATOMIC_ASM(clear, short, "andw %w1,%0", ~v)
116 ATOMIC_ASM(add, short, "addw %w1,%0", v)
117 ATOMIC_ASM(subtract, short, "subw %w1,%0", v)
119 ATOMIC_ASM(set, int, "orl %1,%0", v)
120 ATOMIC_ASM(clear, int, "andl %1,%0", ~v)
121 ATOMIC_ASM(add, int, "addl %1,%0", v)
122 ATOMIC_ASM(subtract, int, "subl %1,%0", v)
124 ATOMIC_ASM(set, long, "orl %1,%0", v)
125 ATOMIC_ASM(clear, long, "andl %1,%0", ~v)
126 ATOMIC_ASM(add, long, "addl %1,%0", v)
127 ATOMIC_ASM(subtract, long, "subl %1,%0", v)
130 * atomic_poll_acquire_int(P) Returns non-zero on success, 0 if the lock
131 * has already been acquired.
132 * atomic_poll_release_int(P)
134 * These support the NDIS driver and are also used for IPIQ interlocks
135 * between cpus. Both the acquisition and release must be
136 * cache-synchronizing instructions.
139 #if defined(KLD_MODULE)
141 extern int atomic_swap_int(volatile int *addr, int value);
142 extern int atomic_poll_acquire_int(volatile u_int *p);
143 extern void atomic_poll_release_int(volatile u_int *p);
148 atomic_swap_int(volatile int *addr, int value)
150 __asm __volatile("xchgl %0, %1" :
151 "=r" (value), "=m" (*addr) : "0" (value) : "memory");
157 atomic_poll_acquire_int(volatile u_int *p)
161 __asm __volatile(MPLOCKED "btsl $0,%0; setnc %%al; andl $255,%%eax" : "+m" (*p), "=a" (data));
167 atomic_poll_release_int(volatile u_int *p)
169 __asm __volatile(MPLOCKED "btrl $0,%0" : "+m" (*p));
175 * These functions operate on a 32 bit interrupt interlock which is defined
178 * bit 0-30 interrupt handler disabled bits (counter)
179 * bit 31 interrupt handler currently running bit (1 = run)
181 * atomic_intr_cond_test(P) Determine if the interlock is in an
182 * acquired state. Returns 0 if it not
183 * acquired, non-zero if it is.
185 * atomic_intr_cond_try(P)
186 * Increment the request counter and attempt to
187 * set bit 31 to acquire the interlock. If
188 * we are unable to set bit 31 the request
189 * counter is decremented and we return -1,
190 * otherwise we return 0.
192 * atomic_intr_cond_enter(P, func, arg)
193 * Increment the request counter and attempt to
194 * set bit 31 to acquire the interlock. If
195 * we are unable to set bit 31 func(arg) is
196 * called in a loop until we are able to set
199 * atomic_intr_cond_exit(P, func, arg)
200 * Decrement the request counter and clear bit
201 * 31. If the request counter is still non-zero
202 * call func(arg) once.
204 * atomic_intr_handler_disable(P)
205 * Set bit 30, indicating that the interrupt
206 * handler has been disabled. Must be called
207 * after the hardware is disabled.
209 * Returns bit 31 indicating whether a serialized
210 * accessor is active (typically the interrupt
211 * handler is running). 0 == not active,
212 * non-zero == active.
214 * atomic_intr_handler_enable(P)
215 * Clear bit 30, indicating that the interrupt
216 * handler has been enabled. Must be called
217 * before the hardware is actually enabled.
219 * atomic_intr_handler_is_enabled(P)
220 * Returns bit 30, 0 indicates that the handler
221 * is enabled, non-zero indicates that it is
222 * disabled. The request counter portion of
223 * the field is ignored.
226 #ifndef __ATOMIC_INTR_T
227 #define __ATOMIC_INTR_T
228 typedef volatile int atomic_intr_t;
231 #if defined(KLD_MODULE)
233 void atomic_intr_init(atomic_intr_t *p);
234 int atomic_intr_handler_disable(atomic_intr_t *p);
235 void atomic_intr_handler_enable(atomic_intr_t *p);
236 int atomic_intr_handler_is_enabled(atomic_intr_t *p);
237 int atomic_intr_cond_test(atomic_intr_t *p);
238 int atomic_intr_cond_try(atomic_intr_t *p);
239 void atomic_intr_cond_enter(atomic_intr_t *p, void (*func)(void *), void *arg);
240 void atomic_intr_cond_exit(atomic_intr_t *p, void (*func)(void *), void *arg);
246 atomic_intr_init(atomic_intr_t *p)
253 atomic_intr_handler_disable(atomic_intr_t *p)
257 __asm __volatile(MPLOCKED "orl $0x40000000,%1; movl %1,%%eax; " \
258 "andl $0x80000000,%%eax" \
259 : "=a"(data) , "+m"(*p));
265 atomic_intr_handler_enable(atomic_intr_t *p)
267 __asm __volatile(MPLOCKED "andl $0xBFFFFFFF,%0" : "+m" (*p));
272 atomic_intr_handler_is_enabled(atomic_intr_t *p)
276 __asm __volatile("movl %1,%%eax; andl $0x40000000,%%eax" \
277 : "=a"(data) : "m"(*p));
283 atomic_intr_cond_enter(atomic_intr_t *p, void (*func)(void *), void *arg)
285 __asm __volatile(MPLOCKED "incl %0; " \
287 MPLOCKED "btsl $31,%0; jnc 2f; " \
288 "pushl %2; call *%1; addl $4,%%esp; " \
292 : "r"(func), "m"(arg) \
297 * Attempt to enter the interrupt condition variable. Returns zero on
298 * success, 1 on failure.
302 atomic_intr_cond_try(atomic_intr_t *p)
306 __asm __volatile(MPLOCKED "incl %0; " \
308 "subl %%eax,%%eax; " \
309 MPLOCKED "btsl $31,%0; jnc 2f; " \
310 MPLOCKED "decl %0; " \
313 : "+m" (*p), "=a"(ret) \
321 atomic_intr_cond_test(atomic_intr_t *p)
323 return((int)(*p & 0x80000000));
328 atomic_intr_cond_exit(atomic_intr_t *p, void (*func)(void *), void *arg)
330 __asm __volatile(MPLOCKED "decl %0; " \
331 MPLOCKED "btrl $31,%0; " \
332 "testl $0x3FFFFFFF,%0; jz 1f; " \
333 "pushl %2; call *%1; addl $4,%%esp; " \
336 : "r"(func), "m"(arg) \
342 #endif /* ! _MACHINE_ATOMIC_H_ */