2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * __FBSDID("$FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $");
30 #include <sys/cdefs.h>
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/linker.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/sysctl.h>
45 #include <sys/endian.h>
48 #include <machine/smp.h>
53 #include <vm/vm_extern.h>
57 #include <sys/device.h>
59 #include <sys/pciio.h>
60 #include <bus/pci/pcireg.h>
61 #include <bus/pci/pcivar.h>
62 #include <bus/pci/pci_private.h>
68 #include <contrib/dev/acpica/acpi.h>
71 #define ACPI_PWR_FOR_SLEEP(x, y, z)
74 extern struct dev_ops pcic_ops; /* XXX */
76 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
78 static uint32_t pci_mapbase(unsigned mapreg);
79 static const char *pci_maptype(unsigned mapreg);
80 static int pci_mapsize(unsigned testval);
81 static int pci_maprange(unsigned mapreg);
82 static void pci_fixancient(pcicfgregs *cfg);
84 static int pci_porten(device_t pcib, int b, int s, int f);
85 static int pci_memen(device_t pcib, int b, int s, int f);
86 static void pci_assign_interrupt(device_t bus, device_t dev,
88 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
89 int b, int s, int f, int reg,
90 struct resource_list *rl, int force, int prefetch);
91 static int pci_probe(device_t dev);
92 static int pci_attach(device_t dev);
93 static void pci_child_detached(device_t, device_t);
94 static void pci_load_vendor_data(void);
95 static int pci_describe_parse_line(char **ptr, int *vendor,
96 int *device, char **desc);
97 static char *pci_describe_device(device_t dev);
98 static int pci_modevent(module_t mod, int what, void *arg);
99 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
101 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
102 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
103 int reg, uint32_t *data);
105 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
106 int reg, uint32_t data);
108 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
109 static void pci_disable_msi(device_t dev);
110 static void pci_enable_msi(device_t dev, uint64_t address,
112 static void pci_enable_msix(device_t dev, u_int index,
113 uint64_t address, uint32_t data);
114 static void pci_mask_msix(device_t dev, u_int index);
115 static void pci_unmask_msix(device_t dev, u_int index);
116 static int pci_msi_blacklisted(void);
117 static void pci_resume_msi(device_t dev);
118 static void pci_resume_msix(device_t dev);
119 static int pcie_slotimpl(const pcicfgregs *);
120 static void pci_print_verbose_expr(const pcicfgregs *);
122 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
127 static void pci_read_cap_subvendor(device_t, int, int,
129 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
130 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
132 static device_method_t pci_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, pci_probe),
135 DEVMETHOD(device_attach, pci_attach),
136 DEVMETHOD(device_detach, bus_generic_detach),
137 DEVMETHOD(device_shutdown, bus_generic_shutdown),
138 DEVMETHOD(device_suspend, pci_suspend),
139 DEVMETHOD(device_resume, pci_resume),
142 DEVMETHOD(bus_print_child, pci_print_child),
143 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
144 DEVMETHOD(bus_read_ivar, pci_read_ivar),
145 DEVMETHOD(bus_write_ivar, pci_write_ivar),
146 DEVMETHOD(bus_driver_added, pci_driver_added),
147 DEVMETHOD(bus_child_detached, pci_child_detached),
148 DEVMETHOD(bus_setup_intr, pci_setup_intr),
149 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
151 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
152 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
153 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
154 DEVMETHOD(bus_delete_resource, pci_delete_resource),
155 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
156 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
157 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
158 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
159 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
160 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
163 DEVMETHOD(pci_read_config, pci_read_config_method),
164 DEVMETHOD(pci_write_config, pci_write_config_method),
165 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
166 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
167 DEVMETHOD(pci_enable_io, pci_enable_io_method),
168 DEVMETHOD(pci_disable_io, pci_disable_io_method),
169 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
170 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
171 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
172 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
173 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
174 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
175 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
176 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
177 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
178 DEVMETHOD(pci_release_msi, pci_release_msi_method),
179 DEVMETHOD(pci_msi_count, pci_msi_count_method),
180 DEVMETHOD(pci_msix_count, pci_msix_count_method),
185 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
187 static devclass_t pci_devclass;
188 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
189 MODULE_VERSION(pci, 1);
191 static char *pci_vendordata;
192 static size_t pci_vendordata_size;
195 static const struct pci_read_cap {
197 pci_read_cap_t read_cap;
198 } pci_read_caps[] = {
199 { PCIY_PMG, pci_read_cap_pmgt },
200 { PCIY_HT, pci_read_cap_ht },
201 { PCIY_MSI, pci_read_cap_msi },
202 { PCIY_MSIX, pci_read_cap_msix },
203 { PCIY_VPD, pci_read_cap_vpd },
204 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
205 { PCIY_PCIX, pci_read_cap_pcix },
206 { PCIY_EXPRESS, pci_read_cap_express },
207 { 0, NULL } /* required last entry */
211 uint32_t devid; /* Vendor/device of the card */
213 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
214 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
219 struct pci_quirk pci_quirks[] = {
220 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
221 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
223 /* As does the Serverworks OSB4 (the SMBus mapping register) */
224 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
227 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
228 * or the CMIC-SL (AKA ServerWorks GC_LE).
230 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
231 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 * MSI doesn't work on earlier Intel chipsets including
235 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
237 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
243 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
246 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
249 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
254 /* map register information */
255 #define PCI_MAPMEM 0x01 /* memory map */
256 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
257 #define PCI_MAPPORT 0x04 /* port map */
259 struct devlist pci_devq;
260 uint32_t pci_generation;
261 uint32_t pci_numdevs = 0;
262 static int pcie_chipset, pcix_chipset;
265 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
267 static int pci_enable_io_modes = 1;
268 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
269 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
270 &pci_enable_io_modes, 1,
271 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
272 enable these bits correctly. We'd like to do this all the time, but there\n\
273 are some peripherals that this causes problems with.");
275 static int pci_do_power_nodriver = 0;
276 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
277 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
278 &pci_do_power_nodriver, 0,
279 "Place a function into D3 state when no driver attaches to it. 0 means\n\
280 disable. 1 means conservatively place devices into D3 state. 2 means\n\
281 aggressively place devices into D3 state. 3 means put absolutely everything\n\
284 static int pci_do_power_resume = 1;
285 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
286 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
287 &pci_do_power_resume, 1,
288 "Transition from D3 -> D0 on resume.");
290 static int pci_do_msi = 1;
291 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
292 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
293 "Enable support for MSI interrupts");
295 static int pci_do_msix = 1;
296 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
297 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
298 "Enable support for MSI-X interrupts");
300 static int pci_honor_msi_blacklist = 1;
301 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
302 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
303 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
305 /* Find a device_t by bus/slot/function in domain 0 */
308 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
311 return (pci_find_dbsf(0, bus, slot, func));
314 /* Find a device_t by domain/bus/slot/function */
317 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
319 struct pci_devinfo *dinfo;
321 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
322 if ((dinfo->cfg.domain == domain) &&
323 (dinfo->cfg.bus == bus) &&
324 (dinfo->cfg.slot == slot) &&
325 (dinfo->cfg.func == func)) {
326 return (dinfo->cfg.dev);
333 /* Find a device_t by vendor/device ID */
336 pci_find_device(uint16_t vendor, uint16_t device)
338 struct pci_devinfo *dinfo;
340 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
341 if ((dinfo->cfg.vendor == vendor) &&
342 (dinfo->cfg.device == device)) {
343 return (dinfo->cfg.dev);
350 /* return base address of memory or port map */
353 pci_mapbase(uint32_t mapreg)
356 if (PCI_BAR_MEM(mapreg))
357 return (mapreg & PCIM_BAR_MEM_BASE);
359 return (mapreg & PCIM_BAR_IO_BASE);
362 /* return map type of memory or port map */
365 pci_maptype(unsigned mapreg)
368 if (PCI_BAR_IO(mapreg))
370 if (mapreg & PCIM_BAR_MEM_PREFETCH)
371 return ("Prefetchable Memory");
375 /* return log2 of map size decoded for memory or port map */
378 pci_mapsize(uint32_t testval)
382 testval = pci_mapbase(testval);
385 while ((testval & 1) == 0)
394 /* return log2 of address range supported by map register */
397 pci_maprange(unsigned mapreg)
401 if (PCI_BAR_IO(mapreg))
404 switch (mapreg & PCIM_BAR_MEM_TYPE) {
405 case PCIM_BAR_MEM_32:
408 case PCIM_BAR_MEM_1MB:
411 case PCIM_BAR_MEM_64:
418 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
421 pci_fixancient(pcicfgregs *cfg)
423 if (cfg->hdrtype != 0)
426 /* PCI to PCI bridges use header type 1 */
427 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
431 /* extract header type specific config data */
434 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
436 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
437 switch (cfg->hdrtype) {
439 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
440 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
441 cfg->nummaps = PCI_MAXMAPS_0;
444 cfg->nummaps = PCI_MAXMAPS_1;
446 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
450 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
451 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
452 cfg->nummaps = PCI_MAXMAPS_2;
454 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
461 /* read configuration header into pcicfgregs structure */
463 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
465 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
466 pcicfgregs *cfg = NULL;
467 struct pci_devinfo *devlist_entry;
468 struct devlist *devlist_head;
470 devlist_head = &pci_devq;
472 devlist_entry = NULL;
474 if (REG(PCIR_DEVVENDOR, 4) != -1) {
475 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
477 cfg = &devlist_entry->cfg;
483 cfg->vendor = REG(PCIR_VENDOR, 2);
484 cfg->device = REG(PCIR_DEVICE, 2);
485 cfg->cmdreg = REG(PCIR_COMMAND, 2);
486 cfg->statreg = REG(PCIR_STATUS, 2);
487 cfg->baseclass = REG(PCIR_CLASS, 1);
488 cfg->subclass = REG(PCIR_SUBCLASS, 1);
489 cfg->progif = REG(PCIR_PROGIF, 1);
490 cfg->revid = REG(PCIR_REVID, 1);
491 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
492 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
493 cfg->lattimer = REG(PCIR_LATTIMER, 1);
494 cfg->intpin = REG(PCIR_INTPIN, 1);
495 cfg->intline = REG(PCIR_INTLINE, 1);
499 * If using the APIC the intpin is probably wrong, since it
500 * is often setup by the BIOS with the PIC in mind.
502 if (cfg->intpin != 0) {
505 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
507 /* PCI specific entry found in MP table */
508 if (airq != cfg->intline) {
509 undirect_pci_irq(cfg->intline);
514 * PCI interrupts might be redirected to the
515 * ISA bus according to some MP tables. Use the
516 * same methods as used by the ISA devices
517 * devices to find the proper IOAPIC int pin.
519 airq = isa_apic_irq(cfg->intline);
520 if ((airq >= 0) && (airq != cfg->intline)) {
521 /* XXX: undirect_pci_irq() ? */
522 undirect_isa_irq(cfg->intline);
529 cfg->mingnt = REG(PCIR_MINGNT, 1);
530 cfg->maxlat = REG(PCIR_MAXLAT, 1);
532 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
533 cfg->hdrtype &= ~PCIM_MFDEV;
536 pci_hdrtypedata(pcib, b, s, f, cfg);
538 pci_read_capabilities(pcib, cfg);
540 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
542 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
543 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
544 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
545 devlist_entry->conf.pc_sel.pc_func = cfg->func;
546 devlist_entry->conf.pc_hdr = cfg->hdrtype;
548 devlist_entry->conf.pc_subvendor = cfg->subvendor;
549 devlist_entry->conf.pc_subdevice = cfg->subdevice;
550 devlist_entry->conf.pc_vendor = cfg->vendor;
551 devlist_entry->conf.pc_device = cfg->device;
553 devlist_entry->conf.pc_class = cfg->baseclass;
554 devlist_entry->conf.pc_subclass = cfg->subclass;
555 devlist_entry->conf.pc_progif = cfg->progif;
556 devlist_entry->conf.pc_revid = cfg->revid;
561 return (devlist_entry);
566 pci_fixup_nextptr(int *nextptr0)
568 int nextptr = *nextptr0;
570 /* "Next pointer" is only one byte */
571 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
575 * PCI local bus spec 3.0:
577 * "... The bottom two bits of all pointers are reserved
578 * and must be implemented as 00b although software must
579 * mask them to allow for future uses of these bits ..."
582 kprintf("Illegal PCI extended capability "
583 "offset, fixup 0x%02x -> 0x%02x\n",
584 nextptr, nextptr & ~0x3);
590 if (nextptr < 0x40) {
592 kprintf("Illegal PCI extended capability "
593 "offset 0x%02x", nextptr);
601 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
604 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
606 struct pcicfg_pp *pp = &cfg->pp;
611 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
612 pp->pp_status = ptr + PCIR_POWER_STATUS;
613 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
615 if ((nextptr - ptr) > PCIR_POWER_DATA) {
618 * We should write to data_select and read back from
619 * data_scale to determine whether data register is
623 pp->pp_data = ptr + PCIR_POWER_DATA;
633 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
636 #if defined(__i386__) || defined(__amd64__)
639 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
641 struct pcicfg_ht *ht = &cfg->ht;
645 /* Determine HT-specific capability type. */
646 val = REG(ptr + PCIR_HT_COMMAND, 2);
648 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
651 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
652 /* Sanity check the mapping window. */
653 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
655 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
656 if (addr != MSI_INTEL_ADDR_BASE) {
657 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
658 "has non-default MSI window 0x%llx\n",
659 cfg->domain, cfg->bus, cfg->slot, cfg->func,
663 addr = MSI_INTEL_ADDR_BASE;
667 ht->ht_msictrl = val;
668 ht->ht_msiaddr = addr;
672 #endif /* __i386__ || __amd64__ */
677 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
680 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
682 struct pcicfg_msi *msi = &cfg->msi;
684 msi->msi_location = ptr;
685 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
686 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
692 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
695 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
697 struct pcicfg_msix *msix = &cfg->msix;
700 msix->msix_location = ptr;
701 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
702 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
704 val = REG(ptr + PCIR_MSIX_TABLE, 4);
705 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
706 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
708 val = REG(ptr + PCIR_MSIX_PBA, 4);
709 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
710 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
716 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
718 cfg->vpd.vpd_reg = ptr;
722 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
725 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
727 /* Should always be true. */
728 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
731 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
732 cfg->subvendor = val & 0xffff;
733 cfg->subdevice = val >> 16;
740 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
743 * Assume we have a PCI-X chipset if we have
744 * at least one PCI-PCI bridge with a PCI-X
745 * capability. Note that some systems with
746 * PCI-express or HT chipsets might match on
747 * this check as well.
749 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
752 cfg->pcix.pcix_ptr = ptr;
756 pcie_slotimpl(const pcicfgregs *cfg)
758 const struct pcicfg_expr *expr = &cfg->expr;
762 * Only version 1 can be parsed currently
764 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
768 * - Slot implemented bit is meaningful iff current port is
769 * root port or down stream port.
770 * - Testing for root port or down stream port is meanningful
771 * iff PCI configure has type 1 header.
774 if (cfg->hdrtype != 1)
777 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
778 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
781 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
788 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
791 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
793 struct pcicfg_expr *expr = &cfg->expr;
796 * Assume we have a PCI-express chipset if we have
797 * at least one PCI-express device.
801 expr->expr_ptr = ptr;
802 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
805 * Only version 1 can be parsed currently
807 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
811 * Read slot capabilities. Slot capabilities exists iff
812 * current port's slot is implemented
814 if (pcie_slotimpl(cfg))
815 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
821 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
823 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
824 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
829 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
830 /* No capabilities */
834 switch (cfg->hdrtype & PCIM_HDRTYPE) {
837 ptrptr = PCIR_CAP_PTR;
840 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
843 return; /* no capabilities support */
845 nextptr = REG(ptrptr, 1); /* sanity check? */
848 * Read capability entries.
850 while (pci_fixup_nextptr(&nextptr)) {
851 const struct pci_read_cap *rc;
854 /* Find the next entry */
855 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
857 /* Process this entry */
858 val = REG(ptr + PCICAP_ID, 1);
859 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
860 if (rc->cap == val) {
861 rc->read_cap(pcib, ptr, nextptr, cfg);
866 /* REG and WREG use carry through to next functions */
870 * PCI Vital Product Data
873 #define PCI_VPD_TIMEOUT 1000000
876 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
878 int count = PCI_VPD_TIMEOUT;
880 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
882 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
884 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
887 DELAY(1); /* limit looping */
889 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
896 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
898 int count = PCI_VPD_TIMEOUT;
900 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
902 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
903 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
904 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
907 DELAY(1); /* limit looping */
914 #undef PCI_VPD_TIMEOUT
916 struct vpd_readstate {
926 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
931 if (vrs->bytesinval == 0) {
932 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
934 vrs->val = le32toh(reg);
936 byte = vrs->val & 0xff;
939 vrs->val = vrs->val >> 8;
940 byte = vrs->val & 0xff;
950 pcie_slot_implemented(device_t dev)
952 struct pci_devinfo *dinfo = device_get_ivars(dev);
954 return pcie_slotimpl(&dinfo->cfg);
958 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
963 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
964 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
965 panic("%s: invalid max read request size 0x%02x\n",
966 device_get_nameunit(dev), rqsize);
969 expr_ptr = pci_get_pciecap_ptr(dev);
971 panic("%s: not PCIe device\n", device_get_nameunit(dev));
973 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
974 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
976 device_printf(dev, "adjust device control 0x%04x", val);
978 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
980 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
983 kprintf(" -> 0x%04x\n", val);
988 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
990 struct vpd_readstate vrs;
995 int alloc, off; /* alloc/off for RO/W arrays */
1001 /* init vpd reader */
1009 name = remain = i = 0; /* shut up stupid gcc */
1010 alloc = off = 0; /* shut up stupid gcc */
1011 dflen = 0; /* shut up stupid gcc */
1013 while (state >= 0) {
1014 if (vpd_nextbyte(&vrs, &byte)) {
1019 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1020 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1021 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1024 case 0: /* item name */
1026 if (vpd_nextbyte(&vrs, &byte2)) {
1031 if (vpd_nextbyte(&vrs, &byte2)) {
1035 remain |= byte2 << 8;
1036 if (remain > (0x7f*4 - vrs.off)) {
1039 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1040 cfg->domain, cfg->bus, cfg->slot,
1045 remain = byte & 0x7;
1046 name = (byte >> 3) & 0xf;
1049 case 0x2: /* String */
1050 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1051 M_DEVBUF, M_WAITOK);
1058 case 0x10: /* VPD-R */
1061 cfg->vpd.vpd_ros = kmalloc(alloc *
1062 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1066 case 0x11: /* VPD-W */
1069 cfg->vpd.vpd_w = kmalloc(alloc *
1070 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1074 default: /* Invalid data, abort */
1080 case 1: /* Identifier String */
1081 cfg->vpd.vpd_ident[i++] = byte;
1084 cfg->vpd.vpd_ident[i] = '\0';
1089 case 2: /* VPD-R Keyword Header */
1091 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1092 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1093 M_DEVBUF, M_WAITOK | M_ZERO);
1095 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1096 if (vpd_nextbyte(&vrs, &byte2)) {
1100 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1101 if (vpd_nextbyte(&vrs, &byte2)) {
1107 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1110 * if this happens, we can't trust the rest
1114 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1115 cfg->domain, cfg->bus, cfg->slot,
1120 } else if (dflen == 0) {
1121 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1122 sizeof(*cfg->vpd.vpd_ros[off].value),
1123 M_DEVBUF, M_WAITOK);
1124 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1126 cfg->vpd.vpd_ros[off].value = kmalloc(
1128 sizeof(*cfg->vpd.vpd_ros[off].value),
1129 M_DEVBUF, M_WAITOK);
1132 /* keep in sync w/ state 3's transistions */
1133 if (dflen == 0 && remain == 0)
1135 else if (dflen == 0)
1141 case 3: /* VPD-R Keyword Value */
1142 cfg->vpd.vpd_ros[off].value[i++] = byte;
1143 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1144 "RV", 2) == 0 && cksumvalid == -1) {
1150 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1151 cfg->domain, cfg->bus,
1152 cfg->slot, cfg->func,
1161 /* keep in sync w/ state 2's transistions */
1163 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1164 if (dflen == 0 && remain == 0) {
1165 cfg->vpd.vpd_rocnt = off;
1166 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1167 off * sizeof(*cfg->vpd.vpd_ros),
1168 M_DEVBUF, M_WAITOK | M_ZERO);
1170 } else if (dflen == 0)
1180 case 5: /* VPD-W Keyword Header */
1182 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1183 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1184 M_DEVBUF, M_WAITOK | M_ZERO);
1186 cfg->vpd.vpd_w[off].keyword[0] = byte;
1187 if (vpd_nextbyte(&vrs, &byte2)) {
1191 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1192 if (vpd_nextbyte(&vrs, &byte2)) {
1196 cfg->vpd.vpd_w[off].len = dflen = byte2;
1197 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1198 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1199 sizeof(*cfg->vpd.vpd_w[off].value),
1200 M_DEVBUF, M_WAITOK);
1203 /* keep in sync w/ state 6's transistions */
1204 if (dflen == 0 && remain == 0)
1206 else if (dflen == 0)
1212 case 6: /* VPD-W Keyword Value */
1213 cfg->vpd.vpd_w[off].value[i++] = byte;
1216 /* keep in sync w/ state 5's transistions */
1218 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1219 if (dflen == 0 && remain == 0) {
1220 cfg->vpd.vpd_wcnt = off;
1221 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1222 off * sizeof(*cfg->vpd.vpd_w),
1223 M_DEVBUF, M_WAITOK | M_ZERO);
1225 } else if (dflen == 0)
1230 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1231 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1238 if (cksumvalid == 0 || state < -1) {
1239 /* read-only data bad, clean up */
1240 if (cfg->vpd.vpd_ros != NULL) {
1241 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1242 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1243 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1244 cfg->vpd.vpd_ros = NULL;
1248 /* I/O error, clean up */
1249 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1250 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1251 if (cfg->vpd.vpd_ident != NULL) {
1252 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1253 cfg->vpd.vpd_ident = NULL;
1255 if (cfg->vpd.vpd_w != NULL) {
1256 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1257 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1258 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1259 cfg->vpd.vpd_w = NULL;
1262 cfg->vpd.vpd_cached = 1;
1268 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1270 struct pci_devinfo *dinfo = device_get_ivars(child);
1271 pcicfgregs *cfg = &dinfo->cfg;
1273 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1274 pci_read_vpd(device_get_parent(dev), cfg);
1276 *identptr = cfg->vpd.vpd_ident;
1278 if (*identptr == NULL)
1285 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1288 struct pci_devinfo *dinfo = device_get_ivars(child);
1289 pcicfgregs *cfg = &dinfo->cfg;
1292 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1293 pci_read_vpd(device_get_parent(dev), cfg);
1295 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1296 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1297 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1298 *vptr = cfg->vpd.vpd_ros[i].value;
1301 if (i != cfg->vpd.vpd_rocnt)
1309 * Return the offset in configuration space of the requested extended
1310 * capability entry or 0 if the specified capability was not found.
1313 pci_find_extcap_method(device_t dev, device_t child, int capability,
1316 struct pci_devinfo *dinfo = device_get_ivars(child);
1317 pcicfgregs *cfg = &dinfo->cfg;
1322 * Check the CAP_LIST bit of the PCI status register first.
1324 status = pci_read_config(child, PCIR_STATUS, 2);
1325 if (!(status & PCIM_STATUS_CAPPRESENT))
1329 * Determine the start pointer of the capabilities list.
1331 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1337 ptr = PCIR_CAP_PTR_2;
1341 return (ENXIO); /* no extended capabilities support */
1343 ptr = pci_read_config(child, ptr, 1);
1346 * Traverse the capabilities list.
1349 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1354 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1361 * Support for MSI-X message interrupts.
1364 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1366 struct pci_devinfo *dinfo = device_get_ivars(dev);
1367 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1370 KASSERT(msix->msix_table_len > index, ("bogus index"));
1371 offset = msix->msix_table_offset + index * 16;
1372 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1373 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1374 bus_write_4(msix->msix_table_res, offset + 8, data);
1376 /* Enable MSI -> HT mapping. */
1377 pci_ht_map_msi(dev, address);
1381 pci_mask_msix(device_t dev, u_int index)
1383 struct pci_devinfo *dinfo = device_get_ivars(dev);
1384 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1385 uint32_t offset, val;
1387 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1388 offset = msix->msix_table_offset + index * 16 + 12;
1389 val = bus_read_4(msix->msix_table_res, offset);
1390 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1391 val |= PCIM_MSIX_VCTRL_MASK;
1392 bus_write_4(msix->msix_table_res, offset, val);
1397 pci_unmask_msix(device_t dev, u_int index)
1399 struct pci_devinfo *dinfo = device_get_ivars(dev);
1400 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1401 uint32_t offset, val;
1403 KASSERT(msix->msix_table_len > index, ("bogus index"));
1404 offset = msix->msix_table_offset + index * 16 + 12;
1405 val = bus_read_4(msix->msix_table_res, offset);
1406 if (val & PCIM_MSIX_VCTRL_MASK) {
1407 val &= ~PCIM_MSIX_VCTRL_MASK;
1408 bus_write_4(msix->msix_table_res, offset, val);
1413 pci_pending_msix(device_t dev, u_int index)
1415 struct pci_devinfo *dinfo = device_get_ivars(dev);
1416 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1417 uint32_t offset, bit;
1419 KASSERT(msix->msix_table_len > index, ("bogus index"));
1420 offset = msix->msix_pba_offset + (index / 32) * 4;
1421 bit = 1 << index % 32;
1422 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1426 * Restore MSI-X registers and table during resume. If MSI-X is
1427 * enabled then walk the virtual table to restore the actual MSI-X
1431 pci_resume_msix(device_t dev)
1433 struct pci_devinfo *dinfo = device_get_ivars(dev);
1434 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1435 struct msix_table_entry *mte;
1436 struct msix_vector *mv;
1439 if (msix->msix_alloc > 0) {
1440 /* First, mask all vectors. */
1441 for (i = 0; i < msix->msix_msgnum; i++)
1442 pci_mask_msix(dev, i);
1444 /* Second, program any messages with at least one handler. */
1445 for (i = 0; i < msix->msix_table_len; i++) {
1446 mte = &msix->msix_table[i];
1447 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1449 mv = &msix->msix_vectors[mte->mte_vector - 1];
1450 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1451 pci_unmask_msix(dev, i);
1454 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1455 msix->msix_ctrl, 2);
1459 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1460 * returned in *count. After this function returns, each message will be
1461 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1464 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1466 struct pci_devinfo *dinfo = device_get_ivars(child);
1467 pcicfgregs *cfg = &dinfo->cfg;
1468 struct resource_list_entry *rle;
1469 int actual, error, i, irq, max;
1471 /* Don't let count == 0 get us into trouble. */
1475 /* If rid 0 is allocated, then fail. */
1476 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1477 if (rle != NULL && rle->res != NULL)
1480 /* Already have allocated messages? */
1481 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1484 /* If MSI is blacklisted for this system, fail. */
1485 if (pci_msi_blacklisted())
1488 /* MSI-X capability present? */
1489 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1492 /* Make sure the appropriate BARs are mapped. */
1493 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1494 cfg->msix.msix_table_bar);
1495 if (rle == NULL || rle->res == NULL ||
1496 !(rman_get_flags(rle->res) & RF_ACTIVE))
1498 cfg->msix.msix_table_res = rle->res;
1499 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1500 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1501 cfg->msix.msix_pba_bar);
1502 if (rle == NULL || rle->res == NULL ||
1503 !(rman_get_flags(rle->res) & RF_ACTIVE))
1506 cfg->msix.msix_pba_res = rle->res;
1509 device_printf(child,
1510 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1511 *count, cfg->msix.msix_msgnum);
1512 max = min(*count, cfg->msix.msix_msgnum);
1513 for (i = 0; i < max; i++) {
1514 /* Allocate a message. */
1515 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1518 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1524 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1526 device_printf(child, "using IRQ %lu for MSI-X\n",
1532 * Be fancy and try to print contiguous runs of
1533 * IRQ values as ranges. 'irq' is the previous IRQ.
1534 * 'run' is true if we are in a range.
1536 device_printf(child, "using IRQs %lu", rle->start);
1539 for (i = 1; i < actual; i++) {
1540 rle = resource_list_find(&dinfo->resources,
1541 SYS_RES_IRQ, i + 1);
1543 /* Still in a run? */
1544 if (rle->start == irq + 1) {
1550 /* Finish previous range. */
1552 kprintf("-%d", irq);
1556 /* Start new range. */
1557 kprintf(",%lu", rle->start);
1561 /* Unfinished range? */
1563 kprintf("-%d", irq);
1564 kprintf(" for MSI-X\n");
1568 /* Mask all vectors. */
1569 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1570 pci_mask_msix(child, i);
1572 /* Allocate and initialize vector data and virtual table. */
1573 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1574 M_DEVBUF, M_WAITOK | M_ZERO);
1575 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1576 M_DEVBUF, M_WAITOK | M_ZERO);
1577 for (i = 0; i < actual; i++) {
1578 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1579 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1580 cfg->msix.msix_table[i].mte_vector = i + 1;
1583 /* Update control register to enable MSI-X. */
1584 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1585 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1586 cfg->msix.msix_ctrl, 2);
1588 /* Update counts of alloc'd messages. */
1589 cfg->msix.msix_alloc = actual;
1590 cfg->msix.msix_table_len = actual;
1596 * By default, pci_alloc_msix() will assign the allocated IRQ
1597 * resources consecutively to the first N messages in the MSI-X table.
1598 * However, device drivers may want to use different layouts if they
1599 * either receive fewer messages than they asked for, or they wish to
1600 * populate the MSI-X table sparsely. This method allows the driver
1601 * to specify what layout it wants. It must be called after a
1602 * successful pci_alloc_msix() but before any of the associated
1603 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1605 * The 'vectors' array contains 'count' message vectors. The array
1606 * maps directly to the MSI-X table in that index 0 in the array
1607 * specifies the vector for the first message in the MSI-X table, etc.
1608 * The vector value in each array index can either be 0 to indicate
1609 * that no vector should be assigned to a message slot, or it can be a
1610 * number from 1 to N (where N is the count returned from a
1611 * succcessful call to pci_alloc_msix()) to indicate which message
1612 * vector (IRQ) to be used for the corresponding message.
1614 * On successful return, each message with a non-zero vector will have
1615 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1616 * 1. Additionally, if any of the IRQs allocated via the previous
1617 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1618 * will be kfreed back to the system automatically.
1620 * For example, suppose a driver has a MSI-X table with 6 messages and
1621 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1622 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1623 * C. After the call to pci_alloc_msix(), the device will be setup to
1624 * have an MSI-X table of ABC--- (where - means no vector assigned).
1625 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1626 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1627 * be kfreed back to the system. This device will also have valid
1628 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1630 * In any case, the SYS_RES_IRQ rid X will always map to the message
1631 * at MSI-X table index X - 1 and will only be valid if a vector is
1632 * assigned to that table entry.
1635 pci_remap_msix_method(device_t dev, device_t child, int count,
1636 const u_int *vectors)
1638 struct pci_devinfo *dinfo = device_get_ivars(child);
1639 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1640 struct resource_list_entry *rle;
1641 int i, irq, j, *used;
1644 * Have to have at least one message in the table but the
1645 * table can't be bigger than the actual MSI-X table in the
1648 if (count == 0 || count > msix->msix_msgnum)
1651 /* Sanity check the vectors. */
1652 for (i = 0; i < count; i++)
1653 if (vectors[i] > msix->msix_alloc)
1657 * Make sure there aren't any holes in the vectors to be used.
1658 * It's a big pain to support it, and it doesn't really make
1659 * sense anyway. Also, at least one vector must be used.
1661 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1663 for (i = 0; i < count; i++)
1664 if (vectors[i] != 0)
1665 used[vectors[i] - 1] = 1;
1666 for (i = 0; i < msix->msix_alloc - 1; i++)
1667 if (used[i] == 0 && used[i + 1] == 1) {
1668 kfree(used, M_DEVBUF);
1672 kfree(used, M_DEVBUF);
1676 /* Make sure none of the resources are allocated. */
1677 for (i = 0; i < msix->msix_table_len; i++) {
1678 if (msix->msix_table[i].mte_vector == 0)
1680 if (msix->msix_table[i].mte_handlers > 0)
1682 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1683 KASSERT(rle != NULL, ("missing resource"));
1684 if (rle->res != NULL)
1688 /* Free the existing resource list entries. */
1689 for (i = 0; i < msix->msix_table_len; i++) {
1690 if (msix->msix_table[i].mte_vector == 0)
1692 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1696 * Build the new virtual table keeping track of which vectors are
1699 kfree(msix->msix_table, M_DEVBUF);
1700 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1701 M_DEVBUF, M_WAITOK | M_ZERO);
1702 for (i = 0; i < count; i++)
1703 msix->msix_table[i].mte_vector = vectors[i];
1704 msix->msix_table_len = count;
1706 /* Free any unused IRQs and resize the vectors array if necessary. */
1707 j = msix->msix_alloc - 1;
1709 struct msix_vector *vec;
1711 while (used[j] == 0) {
1712 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1713 msix->msix_vectors[j].mv_irq);
1716 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1718 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1720 kfree(msix->msix_vectors, M_DEVBUF);
1721 msix->msix_vectors = vec;
1722 msix->msix_alloc = j + 1;
1724 kfree(used, M_DEVBUF);
1726 /* Map the IRQs onto the rids. */
1727 for (i = 0; i < count; i++) {
1728 if (vectors[i] == 0)
1730 irq = msix->msix_vectors[vectors[i]].mv_irq;
1731 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1736 device_printf(child, "Remapped MSI-X IRQs as: ");
1737 for (i = 0; i < count; i++) {
1740 if (vectors[i] == 0)
1744 msix->msix_vectors[vectors[i]].mv_irq);
1753 pci_release_msix(device_t dev, device_t child)
1755 struct pci_devinfo *dinfo = device_get_ivars(child);
1756 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1757 struct resource_list_entry *rle;
1760 /* Do we have any messages to release? */
1761 if (msix->msix_alloc == 0)
1764 /* Make sure none of the resources are allocated. */
1765 for (i = 0; i < msix->msix_table_len; i++) {
1766 if (msix->msix_table[i].mte_vector == 0)
1768 if (msix->msix_table[i].mte_handlers > 0)
1770 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1771 KASSERT(rle != NULL, ("missing resource"));
1772 if (rle->res != NULL)
1776 /* Update control register to disable MSI-X. */
1777 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1778 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1779 msix->msix_ctrl, 2);
1781 /* Free the resource list entries. */
1782 for (i = 0; i < msix->msix_table_len; i++) {
1783 if (msix->msix_table[i].mte_vector == 0)
1785 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1787 kfree(msix->msix_table, M_DEVBUF);
1788 msix->msix_table_len = 0;
1790 /* Release the IRQs. */
1791 for (i = 0; i < msix->msix_alloc; i++)
1792 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1793 msix->msix_vectors[i].mv_irq);
1794 kfree(msix->msix_vectors, M_DEVBUF);
1795 msix->msix_alloc = 0;
1800 * Return the max supported MSI-X messages this device supports.
1801 * Basically, assuming the MD code can alloc messages, this function
1802 * should return the maximum value that pci_alloc_msix() can return.
1803 * Thus, it is subject to the tunables, etc.
1806 pci_msix_count_method(device_t dev, device_t child)
1808 struct pci_devinfo *dinfo = device_get_ivars(child);
1809 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1811 if (pci_do_msix && msix->msix_location != 0)
1812 return (msix->msix_msgnum);
1817 * HyperTransport MSI mapping control
1820 pci_ht_map_msi(device_t dev, uint64_t addr)
1822 struct pci_devinfo *dinfo = device_get_ivars(dev);
1823 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1828 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1829 ht->ht_msiaddr >> 20 == addr >> 20) {
1830 /* Enable MSI -> HT mapping. */
1831 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1832 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1836 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1837 /* Disable MSI -> HT mapping. */
1838 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1839 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1845 * Support for MSI message signalled interrupts.
1848 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1850 struct pci_devinfo *dinfo = device_get_ivars(dev);
1851 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1853 /* Write data and address values. */
1854 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1855 address & 0xffffffff, 4);
1856 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1857 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1859 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1862 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1865 /* Enable MSI in the control register. */
1866 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1867 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1870 /* Enable MSI -> HT mapping. */
1871 pci_ht_map_msi(dev, address);
1875 pci_disable_msi(device_t dev)
1877 struct pci_devinfo *dinfo = device_get_ivars(dev);
1878 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1880 /* Disable MSI -> HT mapping. */
1881 pci_ht_map_msi(dev, 0);
1883 /* Disable MSI in the control register. */
1884 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1885 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1890 * Restore MSI registers during resume. If MSI is enabled then
1891 * restore the data and address registers in addition to the control
1895 pci_resume_msi(device_t dev)
1897 struct pci_devinfo *dinfo = device_get_ivars(dev);
1898 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1902 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1903 address = msi->msi_addr;
1904 data = msi->msi_data;
1905 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1906 address & 0xffffffff, 4);
1907 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1908 pci_write_config(dev, msi->msi_location +
1909 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1910 pci_write_config(dev, msi->msi_location +
1911 PCIR_MSI_DATA_64BIT, data, 2);
1913 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1916 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1921 pci_remap_msi_irq(device_t dev, u_int irq)
1923 struct pci_devinfo *dinfo = device_get_ivars(dev);
1924 pcicfgregs *cfg = &dinfo->cfg;
1925 struct resource_list_entry *rle;
1926 struct msix_table_entry *mte;
1927 struct msix_vector *mv;
1933 bus = device_get_parent(dev);
1936 * Handle MSI first. We try to find this IRQ among our list
1937 * of MSI IRQs. If we find it, we request updated address and
1938 * data registers and apply the results.
1940 if (cfg->msi.msi_alloc > 0) {
1942 /* If we don't have any active handlers, nothing to do. */
1943 if (cfg->msi.msi_handlers == 0)
1945 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1946 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1948 if (rle->start == irq) {
1949 error = PCIB_MAP_MSI(device_get_parent(bus),
1950 dev, irq, &addr, &data);
1953 pci_disable_msi(dev);
1954 dinfo->cfg.msi.msi_addr = addr;
1955 dinfo->cfg.msi.msi_data = data;
1956 pci_enable_msi(dev, addr, data);
1964 * For MSI-X, we check to see if we have this IRQ. If we do,
1965 * we request the updated mapping info. If that works, we go
1966 * through all the slots that use this IRQ and update them.
1968 if (cfg->msix.msix_alloc > 0) {
1969 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1970 mv = &cfg->msix.msix_vectors[i];
1971 if (mv->mv_irq == irq) {
1972 error = PCIB_MAP_MSI(device_get_parent(bus),
1973 dev, irq, &addr, &data);
1976 mv->mv_address = addr;
1978 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1979 mte = &cfg->msix.msix_table[j];
1980 if (mte->mte_vector != i + 1)
1982 if (mte->mte_handlers == 0)
1984 pci_mask_msix(dev, j);
1985 pci_enable_msix(dev, j, addr, data);
1986 pci_unmask_msix(dev, j);
1997 * Returns true if the specified device is blacklisted because MSI
2001 pci_msi_device_blacklisted(device_t dev)
2003 struct pci_quirk *q;
2005 if (!pci_honor_msi_blacklist)
2008 for (q = &pci_quirks[0]; q->devid; q++) {
2009 if (q->devid == pci_get_devid(dev) &&
2010 q->type == PCI_QUIRK_DISABLE_MSI)
2017 * Determine if MSI is blacklisted globally on this sytem. Currently,
2018 * we just check for blacklisted chipsets as represented by the
2019 * host-PCI bridge at device 0:0:0. In the future, it may become
2020 * necessary to check other system attributes, such as the kenv values
2021 * that give the motherboard manufacturer and model number.
2024 pci_msi_blacklisted(void)
2028 if (!pci_honor_msi_blacklist)
2031 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2032 if (!(pcie_chipset || pcix_chipset))
2035 dev = pci_find_bsf(0, 0, 0);
2037 return (pci_msi_device_blacklisted(dev));
2042 * Attempt to allocate *count MSI messages. The actual number allocated is
2043 * returned in *count. After this function returns, each message will be
2044 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2047 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2049 struct pci_devinfo *dinfo = device_get_ivars(child);
2050 pcicfgregs *cfg = &dinfo->cfg;
2051 struct resource_list_entry *rle;
2052 int actual, error, i, irqs[32];
2055 /* Don't let count == 0 get us into trouble. */
2059 /* If rid 0 is allocated, then fail. */
2060 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2061 if (rle != NULL && rle->res != NULL)
2064 /* Already have allocated messages? */
2065 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2068 /* If MSI is blacklisted for this system, fail. */
2069 if (pci_msi_blacklisted())
2072 /* MSI capability present? */
2073 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2077 device_printf(child,
2078 "attempting to allocate %d MSI vectors (%d supported)\n",
2079 *count, cfg->msi.msi_msgnum);
2081 /* Don't ask for more than the device supports. */
2082 actual = min(*count, cfg->msi.msi_msgnum);
2084 /* Don't ask for more than 32 messages. */
2085 actual = min(actual, 32);
2087 /* MSI requires power of 2 number of messages. */
2088 if (!powerof2(actual))
2092 /* Try to allocate N messages. */
2093 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2094 cfg->msi.msi_msgnum, irqs);
2105 * We now have N actual messages mapped onto SYS_RES_IRQ
2106 * resources in the irqs[] array, so add new resources
2107 * starting at rid 1.
2109 for (i = 0; i < actual; i++)
2110 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2111 irqs[i], irqs[i], 1);
2115 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2120 * Be fancy and try to print contiguous runs
2121 * of IRQ values as ranges. 'run' is true if
2122 * we are in a range.
2124 device_printf(child, "using IRQs %d", irqs[0]);
2126 for (i = 1; i < actual; i++) {
2128 /* Still in a run? */
2129 if (irqs[i] == irqs[i - 1] + 1) {
2134 /* Finish previous range. */
2136 kprintf("-%d", irqs[i - 1]);
2140 /* Start new range. */
2141 kprintf(",%d", irqs[i]);
2144 /* Unfinished range? */
2146 kprintf("-%d", irqs[actual - 1]);
2147 kprintf(" for MSI\n");
2151 /* Update control register with actual count. */
2152 ctrl = cfg->msi.msi_ctrl;
2153 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2154 ctrl |= (ffs(actual) - 1) << 4;
2155 cfg->msi.msi_ctrl = ctrl;
2156 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2158 /* Update counts of alloc'd messages. */
2159 cfg->msi.msi_alloc = actual;
2160 cfg->msi.msi_handlers = 0;
2165 /* Release the MSI messages associated with this device. */
2167 pci_release_msi_method(device_t dev, device_t child)
2169 struct pci_devinfo *dinfo = device_get_ivars(child);
2170 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2171 struct resource_list_entry *rle;
2172 int error, i, irqs[32];
2174 /* Try MSI-X first. */
2175 error = pci_release_msix(dev, child);
2176 if (error != ENODEV)
2179 /* Do we have any messages to release? */
2180 if (msi->msi_alloc == 0)
2182 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2184 /* Make sure none of the resources are allocated. */
2185 if (msi->msi_handlers > 0)
2187 for (i = 0; i < msi->msi_alloc; i++) {
2188 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2189 KASSERT(rle != NULL, ("missing MSI resource"));
2190 if (rle->res != NULL)
2192 irqs[i] = rle->start;
2195 /* Update control register with 0 count. */
2196 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2197 ("%s: MSI still enabled", __func__));
2198 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2199 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2202 /* Release the messages. */
2203 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2204 for (i = 0; i < msi->msi_alloc; i++)
2205 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2207 /* Update alloc count. */
2215 * Return the max supported MSI messages this device supports.
2216 * Basically, assuming the MD code can alloc messages, this function
2217 * should return the maximum value that pci_alloc_msi() can return.
2218 * Thus, it is subject to the tunables, etc.
2221 pci_msi_count_method(device_t dev, device_t child)
2223 struct pci_devinfo *dinfo = device_get_ivars(child);
2224 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2226 if (pci_do_msi && msi->msi_location != 0)
2227 return (msi->msi_msgnum);
2231 /* kfree pcicfgregs structure and all depending data structures */
2234 pci_freecfg(struct pci_devinfo *dinfo)
2236 struct devlist *devlist_head;
2239 devlist_head = &pci_devq;
2241 if (dinfo->cfg.vpd.vpd_reg) {
2242 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2243 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2244 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2245 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2246 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2247 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2248 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2250 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2251 kfree(dinfo, M_DEVBUF);
2253 /* increment the generation count */
2256 /* we're losing one device */
2262 * PCI power manangement
2265 pci_set_powerstate_method(device_t dev, device_t child, int state)
2267 struct pci_devinfo *dinfo = device_get_ivars(child);
2268 pcicfgregs *cfg = &dinfo->cfg;
2270 int result, oldstate, highest, delay;
2272 if (cfg->pp.pp_cap == 0)
2273 return (EOPNOTSUPP);
2276 * Optimize a no state change request away. While it would be OK to
2277 * write to the hardware in theory, some devices have shown odd
2278 * behavior when going from D3 -> D3.
2280 oldstate = pci_get_powerstate(child);
2281 if (oldstate == state)
2285 * The PCI power management specification states that after a state
2286 * transition between PCI power states, system software must
2287 * guarantee a minimal delay before the function accesses the device.
2288 * Compute the worst case delay that we need to guarantee before we
2289 * access the device. Many devices will be responsive much more
2290 * quickly than this delay, but there are some that don't respond
2291 * instantly to state changes. Transitions to/from D3 state require
2292 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2293 * is done below with DELAY rather than a sleeper function because
2294 * this function can be called from contexts where we cannot sleep.
2296 highest = (oldstate > state) ? oldstate : state;
2297 if (highest == PCI_POWERSTATE_D3)
2299 else if (highest == PCI_POWERSTATE_D2)
2303 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2304 & ~PCIM_PSTAT_DMASK;
2307 case PCI_POWERSTATE_D0:
2308 status |= PCIM_PSTAT_D0;
2310 case PCI_POWERSTATE_D1:
2311 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2312 return (EOPNOTSUPP);
2313 status |= PCIM_PSTAT_D1;
2315 case PCI_POWERSTATE_D2:
2316 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2317 return (EOPNOTSUPP);
2318 status |= PCIM_PSTAT_D2;
2320 case PCI_POWERSTATE_D3:
2321 status |= PCIM_PSTAT_D3;
2329 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2330 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2331 dinfo->cfg.func, oldstate, state);
2333 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2340 pci_get_powerstate_method(device_t dev, device_t child)
2342 struct pci_devinfo *dinfo = device_get_ivars(child);
2343 pcicfgregs *cfg = &dinfo->cfg;
2347 if (cfg->pp.pp_cap != 0) {
2348 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2349 switch (status & PCIM_PSTAT_DMASK) {
2351 result = PCI_POWERSTATE_D0;
2354 result = PCI_POWERSTATE_D1;
2357 result = PCI_POWERSTATE_D2;
2360 result = PCI_POWERSTATE_D3;
2363 result = PCI_POWERSTATE_UNKNOWN;
2367 /* No support, device is always at D0 */
2368 result = PCI_POWERSTATE_D0;
2374 * Some convenience functions for PCI device drivers.
2377 static __inline void
2378 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2382 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2384 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2387 static __inline void
2388 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2392 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2394 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2398 pci_enable_busmaster_method(device_t dev, device_t child)
2400 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2405 pci_disable_busmaster_method(device_t dev, device_t child)
2407 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2412 pci_enable_io_method(device_t dev, device_t child, int space)
2422 case SYS_RES_IOPORT:
2423 bit = PCIM_CMD_PORTEN;
2426 case SYS_RES_MEMORY:
2427 bit = PCIM_CMD_MEMEN;
2433 pci_set_command_bit(dev, child, bit);
2434 /* Some devices seem to need a brief stall here, what do to? */
2435 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2438 device_printf(child, "failed to enable %s mapping!\n", error);
2443 pci_disable_io_method(device_t dev, device_t child, int space)
2453 case SYS_RES_IOPORT:
2454 bit = PCIM_CMD_PORTEN;
2457 case SYS_RES_MEMORY:
2458 bit = PCIM_CMD_MEMEN;
2464 pci_clear_command_bit(dev, child, bit);
2465 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2466 if (command & bit) {
2467 device_printf(child, "failed to disable %s mapping!\n", error);
2474 * New style pci driver. Parent device is either a pci-host-bridge or a
2475 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2479 pci_print_verbose(struct pci_devinfo *dinfo)
2483 pcicfgregs *cfg = &dinfo->cfg;
2485 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2486 cfg->vendor, cfg->device, cfg->revid);
2487 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2488 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2489 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2490 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2492 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2493 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2494 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2495 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2496 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2497 if (cfg->intpin > 0)
2498 kprintf("\tintpin=%c, irq=%d\n",
2499 cfg->intpin +'a' -1, cfg->intline);
2500 if (cfg->pp.pp_cap) {
2503 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2504 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2505 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2506 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2507 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2508 status & PCIM_PSTAT_DMASK);
2510 if (cfg->msi.msi_location) {
2513 ctrl = cfg->msi.msi_ctrl;
2514 kprintf("\tMSI supports %d message%s%s%s\n",
2515 cfg->msi.msi_msgnum,
2516 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2517 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2518 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2520 if (cfg->msix.msix_location) {
2521 kprintf("\tMSI-X supports %d message%s ",
2522 cfg->msix.msix_msgnum,
2523 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2524 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2525 kprintf("in map 0x%x\n",
2526 cfg->msix.msix_table_bar);
2528 kprintf("in maps 0x%x and 0x%x\n",
2529 cfg->msix.msix_table_bar,
2530 cfg->msix.msix_pba_bar);
2532 pci_print_verbose_expr(cfg);
2537 pci_print_verbose_expr(const pcicfgregs *cfg)
2539 const struct pcicfg_expr *expr = &cfg->expr;
2540 const char *port_name;
2546 if (expr->expr_ptr == 0) /* No PCI Express capability */
2549 kprintf("\tPCI Express ver.%d cap=0x%04x",
2550 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2551 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2554 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2556 switch (port_type) {
2557 case PCIE_END_POINT:
2558 port_name = "DEVICE";
2560 case PCIE_LEG_END_POINT:
2561 port_name = "LEGDEV";
2563 case PCIE_ROOT_PORT:
2566 case PCIE_UP_STREAM_PORT:
2567 port_name = "UPSTREAM";
2569 case PCIE_DOWN_STREAM_PORT:
2570 port_name = "DOWNSTRM";
2572 case PCIE_PCIE2PCI_BRIDGE:
2573 port_name = "PCIE2PCI";
2575 case PCIE_PCI2PCIE_BRIDGE:
2576 port_name = "PCI2PCIE";
2582 if ((port_type == PCIE_ROOT_PORT ||
2583 port_type == PCIE_DOWN_STREAM_PORT) &&
2584 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2586 if (port_name != NULL)
2587 kprintf("[%s]", port_name);
2589 if (pcie_slotimpl(cfg)) {
2590 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2591 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2592 kprintf("[HOTPLUG]");
2599 pci_porten(device_t pcib, int b, int s, int f)
2601 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2602 & PCIM_CMD_PORTEN) != 0;
2606 pci_memen(device_t pcib, int b, int s, int f)
2608 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2609 & PCIM_CMD_MEMEN) != 0;
2613 * Add a resource based on a pci map register. Return 1 if the map
2614 * register is a 32bit map register or 2 if it is a 64bit register.
2617 pci_add_map(device_t pcib, device_t bus, device_t dev,
2618 int b, int s, int f, int reg, struct resource_list *rl, int force,
2623 pci_addr_t start, end, count;
2630 struct resource *res;
2632 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2633 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2634 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2635 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2637 if (PCI_BAR_MEM(map)) {
2638 type = SYS_RES_MEMORY;
2639 if (map & PCIM_BAR_MEM_PREFETCH)
2642 type = SYS_RES_IOPORT;
2643 ln2size = pci_mapsize(testval);
2644 ln2range = pci_maprange(testval);
2645 base = pci_mapbase(map);
2646 barlen = ln2range == 64 ? 2 : 1;
2649 * For I/O registers, if bottom bit is set, and the next bit up
2650 * isn't clear, we know we have a BAR that doesn't conform to the
2651 * spec, so ignore it. Also, sanity check the size of the data
2652 * areas to the type of memory involved. Memory must be at least
2653 * 16 bytes in size, while I/O ranges must be at least 4.
2655 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2657 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2658 (type == SYS_RES_IOPORT && ln2size < 2))
2662 /* Read the other half of a 64bit map register */
2663 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2665 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2666 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2667 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2668 kprintf(", port disabled\n");
2669 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2670 kprintf(", memory disabled\n");
2672 kprintf(", enabled\n");
2676 * If base is 0, then we have problems. It is best to ignore
2677 * such entries for the moment. These will be allocated later if
2678 * the driver specifically requests them. However, some
2679 * removable busses look better when all resources are allocated,
2680 * so allow '0' to be overriden.
2682 * Similarly treat maps whose values is the same as the test value
2683 * read back. These maps have had all f's written to them by the
2684 * BIOS in an attempt to disable the resources.
2686 if (!force && (base == 0 || map == testval))
2688 if ((u_long)base != base) {
2690 "pci%d:%d:%d:%d bar %#x too many address bits",
2691 pci_get_domain(dev), b, s, f, reg);
2696 * This code theoretically does the right thing, but has
2697 * undesirable side effects in some cases where peripherals
2698 * respond oddly to having these bits enabled. Let the user
2699 * be able to turn them off (since pci_enable_io_modes is 1 by
2702 if (pci_enable_io_modes) {
2703 /* Turn on resources that have been left off by a lazy BIOS */
2704 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2705 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2706 cmd |= PCIM_CMD_PORTEN;
2707 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2709 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2710 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2711 cmd |= PCIM_CMD_MEMEN;
2712 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2715 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2717 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2721 count = 1 << ln2size;
2722 if (base == 0 || base == pci_mapbase(testval)) {
2723 start = 0; /* Let the parent decide. */
2727 end = base + (1 << ln2size) - 1;
2729 resource_list_add(rl, type, reg, start, end, count);
2732 * Try to allocate the resource for this BAR from our parent
2733 * so that this resource range is already reserved. The
2734 * driver for this device will later inherit this resource in
2735 * pci_alloc_resource().
2737 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2738 prefetch ? RF_PREFETCHABLE : 0);
2741 * If the allocation fails, delete the resource list
2742 * entry to force pci_alloc_resource() to allocate
2743 * resources from the parent.
2745 resource_list_delete(rl, type, reg);
2746 #ifdef PCI_BAR_CLEAR
2749 #else /* !PCI_BAR_CLEAR */
2751 * Don't clear BAR here. Some BIOS lists HPET as a
2752 * PCI function, clearing the BAR causes HPET timer
2756 kprintf("pci:%d:%d:%d: resource reservation failed "
2757 "%#llx - %#llx\n", b, s, f, start, end);
2760 #endif /* PCI_BAR_CLEAR */
2762 start = rman_get_start(res);
2764 pci_write_config(dev, reg, start, 4);
2766 pci_write_config(dev, reg + 4, start >> 32, 4);
2771 * For ATA devices we need to decide early what addressing mode to use.
2772 * Legacy demands that the primary and secondary ATA ports sits on the
2773 * same addresses that old ISA hardware did. This dictates that we use
2774 * those addresses and ignore the BAR's if we cannot set PCI native
2778 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2779 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2781 int rid, type, progif;
2783 /* if this device supports PCI native addressing use it */
2784 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2785 if ((progif & 0x8a) == 0x8a) {
2786 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2787 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2788 kprintf("Trying ATA native PCI addressing mode\n");
2789 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2793 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2794 type = SYS_RES_IOPORT;
2795 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2796 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2797 prefetchmask & (1 << 0));
2798 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2799 prefetchmask & (1 << 1));
2802 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2803 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2806 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2807 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2810 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2811 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2812 prefetchmask & (1 << 2));
2813 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2814 prefetchmask & (1 << 3));
2817 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2818 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2821 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2822 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2825 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2826 prefetchmask & (1 << 4));
2827 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2828 prefetchmask & (1 << 5));
2832 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2834 struct pci_devinfo *dinfo = device_get_ivars(dev);
2835 pcicfgregs *cfg = &dinfo->cfg;
2836 char tunable_name[64];
2839 /* Has to have an intpin to have an interrupt. */
2840 if (cfg->intpin == 0)
2843 /* Let the user override the IRQ with a tunable. */
2844 irq = PCI_INVALID_IRQ;
2845 ksnprintf(tunable_name, sizeof(tunable_name),
2846 "hw.pci%d.%d.%d.INT%c.irq",
2847 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2848 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2849 irq = PCI_INVALID_IRQ;
2852 * If we didn't get an IRQ via the tunable, then we either use the
2853 * IRQ value in the intline register or we ask the bus to route an
2854 * interrupt for us. If force_route is true, then we only use the
2855 * value in the intline register if the bus was unable to assign an
2858 if (!PCI_INTERRUPT_VALID(irq)) {
2859 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2860 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2861 if (!PCI_INTERRUPT_VALID(irq))
2865 /* If after all that we don't have an IRQ, just bail. */
2866 if (!PCI_INTERRUPT_VALID(irq))
2869 /* Update the config register if it changed. */
2870 if (irq != cfg->intline) {
2872 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2875 /* Add this IRQ as rid 0 interrupt resource. */
2876 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2880 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2882 struct pci_devinfo *dinfo = device_get_ivars(dev);
2883 pcicfgregs *cfg = &dinfo->cfg;
2884 struct resource_list *rl = &dinfo->resources;
2885 struct pci_quirk *q;
2892 /* ATA devices needs special map treatment */
2893 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2894 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2895 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2896 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2897 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2898 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2900 for (i = 0; i < cfg->nummaps;)
2901 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2902 rl, force, prefetchmask & (1 << i));
2905 * Add additional, quirked resources.
2907 for (q = &pci_quirks[0]; q->devid; q++) {
2908 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2909 && q->type == PCI_QUIRK_MAP_REG)
2910 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2914 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2915 #ifdef __PCI_REROUTE_INTERRUPT
2917 * Try to re-route interrupts. Sometimes the BIOS or
2918 * firmware may leave bogus values in these registers.
2919 * If the re-route fails, then just stick with what we
2922 pci_assign_interrupt(bus, dev, 1);
2924 pci_assign_interrupt(bus, dev, 0);
2930 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2932 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2933 device_t pcib = device_get_parent(dev);
2934 struct pci_devinfo *dinfo;
2936 int s, f, pcifunchigh;
2939 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2940 ("dinfo_size too small"));
2941 maxslots = PCIB_MAXSLOTS(pcib);
2942 for (s = 0; s <= maxslots; s++) {
2946 hdrtype = REG(PCIR_HDRTYPE, 1);
2947 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2949 if (hdrtype & PCIM_MFDEV)
2950 pcifunchigh = PCI_FUNCMAX;
2951 for (f = 0; f <= pcifunchigh; f++) {
2952 dinfo = pci_read_device(pcib, domain, busno, s, f,
2954 if (dinfo != NULL) {
2955 pci_add_child(dev, dinfo);
2963 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2967 pcib = device_get_parent(bus);
2968 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2969 device_set_ivars(dinfo->cfg.dev, dinfo);
2970 resource_list_init(&dinfo->resources);
2971 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2972 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2973 pci_print_verbose(dinfo);
2974 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2978 pci_probe(device_t dev)
2980 device_set_desc(dev, "PCI bus");
2982 /* Allow other subclasses to override this driver. */
2987 pci_attach(device_t dev)
2992 * Since there can be multiple independantly numbered PCI
2993 * busses on systems with multiple PCI domains, we can't use
2994 * the unit number to decide which bus we are probing. We ask
2995 * the parent pcib what our domain and bus numbers are.
2997 domain = pcib_get_domain(dev);
2998 busno = pcib_get_bus(dev);
3000 device_printf(dev, "domain=%d, physical bus=%d\n",
3003 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3005 return (bus_generic_attach(dev));
3009 pci_suspend(device_t dev)
3011 int dstate, error, i, numdevs;
3012 device_t acpi_dev, child, *devlist;
3013 struct pci_devinfo *dinfo;
3016 * Save the PCI configuration space for each child and set the
3017 * device in the appropriate power state for this sleep state.
3020 if (pci_do_power_resume)
3021 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3022 device_get_children(dev, &devlist, &numdevs);
3023 for (i = 0; i < numdevs; i++) {
3025 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3026 pci_cfg_save(child, dinfo, 0);
3029 /* Suspend devices before potentially powering them down. */
3030 error = bus_generic_suspend(dev);
3032 kfree(devlist, M_TEMP);
3037 * Always set the device to D3. If ACPI suggests a different
3038 * power state, use it instead. If ACPI is not present, the
3039 * firmware is responsible for managing device power. Skip
3040 * children who aren't attached since they are powered down
3041 * separately. Only manage type 0 devices for now.
3043 for (i = 0; acpi_dev && i < numdevs; i++) {
3045 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3046 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
3047 dstate = PCI_POWERSTATE_D3;
3048 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
3049 pci_set_powerstate(child, dstate);
3052 kfree(devlist, M_TEMP);
3057 pci_resume(device_t dev)
3060 device_t acpi_dev, child, *devlist;
3061 struct pci_devinfo *dinfo;
3064 * Set each child to D0 and restore its PCI configuration space.
3067 if (pci_do_power_resume)
3068 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3069 device_get_children(dev, &devlist, &numdevs);
3070 for (i = 0; i < numdevs; i++) {
3072 * Notify ACPI we're going to D0 but ignore the result. If
3073 * ACPI is not present, the firmware is responsible for
3074 * managing device power. Only manage type 0 devices for now.
3077 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3078 if (acpi_dev && device_is_attached(child) &&
3079 dinfo->cfg.hdrtype == 0) {
3080 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3081 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3084 /* Now the device is powered up, restore its config space. */
3085 pci_cfg_restore(child, dinfo);
3087 kfree(devlist, M_TEMP);
3088 return (bus_generic_resume(dev));
3092 pci_load_vendor_data(void)
3094 caddr_t vendordata, info;
3096 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3097 info = preload_search_info(vendordata, MODINFO_ADDR);
3098 pci_vendordata = *(char **)info;
3099 info = preload_search_info(vendordata, MODINFO_SIZE);
3100 pci_vendordata_size = *(size_t *)info;
3101 /* terminate the database */
3102 pci_vendordata[pci_vendordata_size] = '\n';
3107 pci_driver_added(device_t dev, driver_t *driver)
3112 struct pci_devinfo *dinfo;
3116 device_printf(dev, "driver added\n");
3117 DEVICE_IDENTIFY(driver, dev);
3118 device_get_children(dev, &devlist, &numdevs);
3119 for (i = 0; i < numdevs; i++) {
3121 if (device_get_state(child) != DS_NOTPRESENT)
3123 dinfo = device_get_ivars(child);
3124 pci_print_verbose(dinfo);
3126 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3127 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3129 pci_cfg_restore(child, dinfo);
3130 if (device_probe_and_attach(child) != 0)
3131 pci_cfg_save(child, dinfo, 1);
3133 kfree(devlist, M_TEMP);
3137 pci_child_detached(device_t parent __unused, device_t child)
3139 /* Turn child's power off */
3140 pci_cfg_save(child, device_get_ivars(child), 1);
3144 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3145 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3148 struct pci_devinfo *dinfo;
3149 struct msix_table_entry *mte;
3150 struct msix_vector *mv;
3157 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3158 arg, &cookie, serializer);
3162 /* If this is not a direct child, just bail out. */
3163 if (device_get_parent(child) != dev) {
3168 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3170 rid = rman_get_rid(irq);
3172 /* Make sure that INTx is enabled */
3173 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3176 * Check to see if the interrupt is MSI or MSI-X.
3177 * Ask our parent to map the MSI and give
3178 * us the address and data register values.
3179 * If we fail for some reason, teardown the
3180 * interrupt handler.
3182 dinfo = device_get_ivars(child);
3183 if (dinfo->cfg.msi.msi_alloc > 0) {
3184 if (dinfo->cfg.msi.msi_addr == 0) {
3185 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3186 ("MSI has handlers, but vectors not mapped"));
3187 error = PCIB_MAP_MSI(device_get_parent(dev),
3188 child, rman_get_start(irq), &addr, &data);
3191 dinfo->cfg.msi.msi_addr = addr;
3192 dinfo->cfg.msi.msi_data = data;
3193 pci_enable_msi(child, addr, data);
3195 dinfo->cfg.msi.msi_handlers++;
3197 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3198 ("No MSI or MSI-X interrupts allocated"));
3199 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3200 ("MSI-X index too high"));
3201 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3202 KASSERT(mte->mte_vector != 0, ("no message vector"));
3203 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3204 KASSERT(mv->mv_irq == rman_get_start(irq),
3206 if (mv->mv_address == 0) {
3207 KASSERT(mte->mte_handlers == 0,
3208 ("MSI-X table entry has handlers, but vector not mapped"));
3209 error = PCIB_MAP_MSI(device_get_parent(dev),
3210 child, rman_get_start(irq), &addr, &data);
3213 mv->mv_address = addr;
3216 if (mte->mte_handlers == 0) {
3217 pci_enable_msix(child, rid - 1, mv->mv_address,
3219 pci_unmask_msix(child, rid - 1);
3221 mte->mte_handlers++;
3224 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3225 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3228 (void)bus_generic_teardown_intr(dev, child, irq,
3239 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3243 struct msix_table_entry *mte;
3244 struct resource_list_entry *rle;
3245 struct pci_devinfo *dinfo;
3250 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3253 /* If this isn't a direct child, just bail out */
3254 if (device_get_parent(child) != dev)
3255 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3257 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3259 rid = rman_get_rid(irq);
3262 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3265 * Check to see if the interrupt is MSI or MSI-X. If so,
3266 * decrement the appropriate handlers count and mask the
3267 * MSI-X message, or disable MSI messages if the count
3270 dinfo = device_get_ivars(child);
3271 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3272 if (rle->res != irq)
3274 if (dinfo->cfg.msi.msi_alloc > 0) {
3275 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3276 ("MSI-X index too high"));
3277 if (dinfo->cfg.msi.msi_handlers == 0)
3279 dinfo->cfg.msi.msi_handlers--;
3280 if (dinfo->cfg.msi.msi_handlers == 0)
3281 pci_disable_msi(child);
3283 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3284 ("No MSI or MSI-X interrupts allocated"));
3285 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3286 ("MSI-X index too high"));
3287 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3288 if (mte->mte_handlers == 0)
3290 mte->mte_handlers--;
3291 if (mte->mte_handlers == 0)
3292 pci_mask_msix(child, rid - 1);
3295 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3298 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3300 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3305 pci_print_child(device_t dev, device_t child)
3307 struct pci_devinfo *dinfo;
3308 struct resource_list *rl;
3311 dinfo = device_get_ivars(child);
3312 rl = &dinfo->resources;
3314 retval += bus_print_child_header(dev, child);
3316 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3317 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3318 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3319 if (device_get_flags(dev))
3320 retval += kprintf(" flags %#x", device_get_flags(dev));
3322 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3323 pci_get_function(child));
3325 retval += bus_print_child_footer(dev, child);
3335 } pci_nomatch_tab[] = {
3336 {PCIC_OLD, -1, "old"},
3337 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3338 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3339 {PCIC_STORAGE, -1, "mass storage"},
3340 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3341 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3342 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3343 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3344 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3345 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3346 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3347 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3348 {PCIC_NETWORK, -1, "network"},
3349 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3350 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3351 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3352 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3353 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3354 {PCIC_DISPLAY, -1, "display"},
3355 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3356 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3357 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3358 {PCIC_MULTIMEDIA, -1, "multimedia"},
3359 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3360 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3361 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3362 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3363 {PCIC_MEMORY, -1, "memory"},
3364 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3365 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3366 {PCIC_BRIDGE, -1, "bridge"},
3367 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3368 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3369 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3370 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3371 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3372 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3373 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3374 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3375 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3376 {PCIC_SIMPLECOMM, -1, "simple comms"},
3377 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3378 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3379 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3380 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3381 {PCIC_BASEPERIPH, -1, "base peripheral"},
3382 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3383 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3384 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3385 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3386 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3387 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3388 {PCIC_INPUTDEV, -1, "input device"},
3389 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3390 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3391 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3392 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3393 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3394 {PCIC_DOCKING, -1, "docking station"},
3395 {PCIC_PROCESSOR, -1, "processor"},
3396 {PCIC_SERIALBUS, -1, "serial bus"},
3397 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3398 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3399 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3400 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3401 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3402 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3403 {PCIC_WIRELESS, -1, "wireless controller"},
3404 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3405 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3406 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3407 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3408 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3409 {PCIC_SATCOM, -1, "satellite communication"},
3410 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3411 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3412 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3413 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3414 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3415 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3416 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3417 {PCIC_DASP, -1, "dasp"},
3418 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3423 pci_probe_nomatch(device_t dev, device_t child)
3426 char *cp, *scp, *device;
3429 * Look for a listing for this device in a loaded device database.
3431 if ((device = pci_describe_device(child)) != NULL) {
3432 device_printf(dev, "<%s>", device);
3433 kfree(device, M_DEVBUF);
3436 * Scan the class/subclass descriptions for a general
3441 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3442 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3443 if (pci_nomatch_tab[i].subclass == -1) {
3444 cp = pci_nomatch_tab[i].desc;
3445 } else if (pci_nomatch_tab[i].subclass ==
3446 pci_get_subclass(child)) {
3447 scp = pci_nomatch_tab[i].desc;
3451 device_printf(dev, "<%s%s%s>",
3453 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3456 kprintf(" at device %d.%d (no driver attached)\n",
3457 pci_get_slot(child), pci_get_function(child));
3458 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3463 * Parse the PCI device database, if loaded, and return a pointer to a
3464 * description of the device.
3466 * The database is flat text formatted as follows:
3468 * Any line not in a valid format is ignored.
3469 * Lines are terminated with newline '\n' characters.
3471 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3474 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3475 * - devices cannot be listed without a corresponding VENDOR line.
3476 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3477 * another TAB, then the device name.
3481 * Assuming (ptr) points to the beginning of a line in the database,
3482 * return the vendor or device and description of the next entry.
3483 * The value of (vendor) or (device) inappropriate for the entry type
3484 * is set to -1. Returns nonzero at the end of the database.
3486 * Note that this is slightly unrobust in the face of corrupt data;
3487 * we attempt to safeguard against this by spamming the end of the
3488 * database with a newline when we initialise.
3491 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3500 left = pci_vendordata_size - (cp - pci_vendordata);
3508 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3512 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3515 /* skip to next line */
3516 while (*cp != '\n' && left > 0) {
3525 /* skip to next line */
3526 while (*cp != '\n' && left > 0) {
3530 if (*cp == '\n' && left > 0)
3537 pci_describe_device(device_t dev)
3540 char *desc, *vp, *dp, *line;
3542 desc = vp = dp = NULL;
3545 * If we have no vendor data, we can't do anything.
3547 if (pci_vendordata == NULL)
3551 * Scan the vendor data looking for this device
3553 line = pci_vendordata;
3554 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3557 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3559 if (vendor == pci_get_vendor(dev))
3562 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3565 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3573 if (device == pci_get_device(dev))
3577 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3578 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3580 ksprintf(desc, "%s, %s", vp, dp);
3583 kfree(vp, M_DEVBUF);
3585 kfree(dp, M_DEVBUF);
3590 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3592 struct pci_devinfo *dinfo;
3595 dinfo = device_get_ivars(child);
3599 case PCI_IVAR_ETHADDR:
3601 * The generic accessor doesn't deal with failure, so
3602 * we set the return value, then return an error.
3604 *((uint8_t **) result) = NULL;
3606 case PCI_IVAR_SUBVENDOR:
3607 *result = cfg->subvendor;
3609 case PCI_IVAR_SUBDEVICE:
3610 *result = cfg->subdevice;
3612 case PCI_IVAR_VENDOR:
3613 *result = cfg->vendor;
3615 case PCI_IVAR_DEVICE:
3616 *result = cfg->device;
3618 case PCI_IVAR_DEVID:
3619 *result = (cfg->device << 16) | cfg->vendor;
3621 case PCI_IVAR_CLASS:
3622 *result = cfg->baseclass;
3624 case PCI_IVAR_SUBCLASS:
3625 *result = cfg->subclass;
3627 case PCI_IVAR_PROGIF:
3628 *result = cfg->progif;
3630 case PCI_IVAR_REVID:
3631 *result = cfg->revid;
3633 case PCI_IVAR_INTPIN:
3634 *result = cfg->intpin;
3637 *result = cfg->intline;
3639 case PCI_IVAR_DOMAIN:
3640 *result = cfg->domain;
3646 *result = cfg->slot;
3648 case PCI_IVAR_FUNCTION:
3649 *result = cfg->func;
3651 case PCI_IVAR_CMDREG:
3652 *result = cfg->cmdreg;
3654 case PCI_IVAR_CACHELNSZ:
3655 *result = cfg->cachelnsz;
3657 case PCI_IVAR_MINGNT:
3658 *result = cfg->mingnt;
3660 case PCI_IVAR_MAXLAT:
3661 *result = cfg->maxlat;
3663 case PCI_IVAR_LATTIMER:
3664 *result = cfg->lattimer;
3666 case PCI_IVAR_PCIXCAP_PTR:
3667 *result = cfg->pcix.pcix_ptr;
3669 case PCI_IVAR_PCIECAP_PTR:
3670 *result = cfg->expr.expr_ptr;
3672 case PCI_IVAR_VPDCAP_PTR:
3673 *result = cfg->vpd.vpd_reg;
3682 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3684 struct pci_devinfo *dinfo;
3686 dinfo = device_get_ivars(child);
3689 case PCI_IVAR_INTPIN:
3690 dinfo->cfg.intpin = value;
3692 case PCI_IVAR_ETHADDR:
3693 case PCI_IVAR_SUBVENDOR:
3694 case PCI_IVAR_SUBDEVICE:
3695 case PCI_IVAR_VENDOR:
3696 case PCI_IVAR_DEVICE:
3697 case PCI_IVAR_DEVID:
3698 case PCI_IVAR_CLASS:
3699 case PCI_IVAR_SUBCLASS:
3700 case PCI_IVAR_PROGIF:
3701 case PCI_IVAR_REVID:
3703 case PCI_IVAR_DOMAIN:
3706 case PCI_IVAR_FUNCTION:
3707 return (EINVAL); /* disallow for now */
3714 #include "opt_ddb.h"
3716 #include <ddb/ddb.h>
3717 #include <sys/cons.h>
3720 * List resources based on pci map registers, used for within ddb
3723 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3725 struct pci_devinfo *dinfo;
3726 struct devlist *devlist_head;
3729 int i, error, none_count;
3732 /* get the head of the device queue */
3733 devlist_head = &pci_devq;
3736 * Go through the list of devices and print out devices
3738 for (error = 0, i = 0,
3739 dinfo = STAILQ_FIRST(devlist_head);
3740 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3741 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3743 /* Populate pd_name and pd_unit */
3746 name = device_get_name(dinfo->cfg.dev);
3749 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3750 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3751 (name && *name) ? name : "none",
3752 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3754 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3755 p->pc_sel.pc_func, (p->pc_class << 16) |
3756 (p->pc_subclass << 8) | p->pc_progif,
3757 (p->pc_subdevice << 16) | p->pc_subvendor,
3758 (p->pc_device << 16) | p->pc_vendor,
3759 p->pc_revid, p->pc_hdr);
3765 static struct resource *
3766 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3767 u_long start, u_long end, u_long count, u_int flags)
3769 struct pci_devinfo *dinfo = device_get_ivars(child);
3770 struct resource_list *rl = &dinfo->resources;
3771 struct resource_list_entry *rle;
3772 struct resource *res;
3773 pci_addr_t map, testval;
3777 * Weed out the bogons, and figure out how large the BAR/map
3778 * is. Bars that read back 0 here are bogus and unimplemented.
3779 * Note: atapci in legacy mode are special and handled elsewhere
3780 * in the code. If you have a atapci device in legacy mode and
3781 * it fails here, that other code is broken.
3784 map = pci_read_config(child, *rid, 4);
3785 pci_write_config(child, *rid, 0xffffffff, 4);
3786 testval = pci_read_config(child, *rid, 4);
3787 if (pci_maprange(testval) == 64)
3788 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3789 if (pci_mapbase(testval) == 0)
3793 * Restore the original value of the BAR. We may have reprogrammed
3794 * the BAR of the low-level console device and when booting verbose,
3795 * we need the console device addressable.
3797 pci_write_config(child, *rid, map, 4);
3799 if (PCI_BAR_MEM(testval)) {
3800 if (type != SYS_RES_MEMORY) {
3803 "child %s requested type %d for rid %#x,"
3804 " but the BAR says it is an memio\n",
3805 device_get_nameunit(child), type, *rid);
3809 if (type != SYS_RES_IOPORT) {
3812 "child %s requested type %d for rid %#x,"
3813 " but the BAR says it is an ioport\n",
3814 device_get_nameunit(child), type, *rid);
3819 * For real BARs, we need to override the size that
3820 * the driver requests, because that's what the BAR
3821 * actually uses and we would otherwise have a
3822 * situation where we might allocate the excess to
3823 * another driver, which won't work.
3825 mapsize = pci_mapsize(testval);
3826 count = 1UL << mapsize;
3827 if (RF_ALIGNMENT(flags) < mapsize)
3828 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3829 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3830 flags |= RF_PREFETCHABLE;
3833 * Allocate enough resource, and then write back the
3834 * appropriate bar for that resource.
3836 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3837 start, end, count, flags);
3839 device_printf(child,
3840 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3841 count, *rid, type, start, end);
3844 resource_list_add(rl, type, *rid, start, end, count);
3845 rle = resource_list_find(rl, type, *rid);
3847 panic("pci_alloc_map: unexpectedly can't find resource.");
3849 rle->start = rman_get_start(res);
3850 rle->end = rman_get_end(res);
3853 device_printf(child,
3854 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3855 count, *rid, type, rman_get_start(res));
3856 map = rman_get_start(res);
3858 pci_write_config(child, *rid, map, 4);
3859 if (pci_maprange(testval) == 64)
3860 pci_write_config(child, *rid + 4, map >> 32, 4);
3866 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3867 u_long start, u_long end, u_long count, u_int flags)
3869 struct pci_devinfo *dinfo = device_get_ivars(child);
3870 struct resource_list *rl = &dinfo->resources;
3871 struct resource_list_entry *rle;
3872 pcicfgregs *cfg = &dinfo->cfg;
3875 * Perform lazy resource allocation
3877 if (device_get_parent(child) == dev) {
3881 * Can't alloc legacy interrupt once MSI messages
3882 * have been allocated.
3885 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3886 cfg->msix.msix_alloc > 0))
3890 * If the child device doesn't have an
3891 * interrupt routed and is deserving of an
3892 * interrupt, try to assign it one.
3894 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3896 pci_assign_interrupt(dev, child, 0);
3898 case SYS_RES_IOPORT:
3899 case SYS_RES_MEMORY:
3900 if (*rid < PCIR_BAR(cfg->nummaps)) {
3902 * Enable the I/O mode. We should
3903 * also be assigning resources too
3904 * when none are present. The
3905 * resource_list_alloc kind of sorta does
3908 if (PCI_ENABLE_IO(dev, child, type))
3911 rle = resource_list_find(rl, type, *rid);
3913 return (pci_alloc_map(dev, child, type, rid,
3914 start, end, count, flags));
3918 * If we've already allocated the resource, then
3919 * return it now. But first we may need to activate
3920 * it, since we don't allocate the resource as active
3921 * above. Normally this would be done down in the
3922 * nexus, but since we short-circuit that path we have
3923 * to do its job here. Not sure if we should kfree the
3924 * resource if it fails to activate.
3926 rle = resource_list_find(rl, type, *rid);
3927 if (rle != NULL && rle->res != NULL) {
3929 device_printf(child,
3930 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3931 rman_get_size(rle->res), *rid, type,
3932 rman_get_start(rle->res));
3933 if ((flags & RF_ACTIVE) &&
3934 bus_generic_activate_resource(dev, child, type,
3935 *rid, rle->res) != 0)
3940 return (resource_list_alloc(rl, dev, child, type, rid,
3941 start, end, count, flags));
3945 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3947 struct pci_devinfo *dinfo;
3948 struct resource_list *rl;
3949 struct resource_list_entry *rle;
3951 if (device_get_parent(child) != dev)
3954 dinfo = device_get_ivars(child);
3955 rl = &dinfo->resources;
3956 rle = resource_list_find(rl, type, rid);
3959 if (rman_get_device(rle->res) != dev ||
3960 rman_get_flags(rle->res) & RF_ACTIVE) {
3961 device_printf(dev, "delete_resource: "
3962 "Resource still owned by child, oops. "
3963 "(type=%d, rid=%d, addr=%lx)\n",
3964 rle->type, rle->rid,
3965 rman_get_start(rle->res));
3968 bus_release_resource(dev, type, rid, rle->res);
3970 resource_list_delete(rl, type, rid);
3973 * Why do we turn off the PCI configuration BAR when we delete a
3976 pci_write_config(child, rid, 0, 4);
3977 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3980 struct resource_list *
3981 pci_get_resource_list (device_t dev, device_t child)
3983 struct pci_devinfo *dinfo = device_get_ivars(child);
3988 return (&dinfo->resources);
3992 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3994 struct pci_devinfo *dinfo = device_get_ivars(child);
3995 pcicfgregs *cfg = &dinfo->cfg;
3997 return (PCIB_READ_CONFIG(device_get_parent(dev),
3998 cfg->bus, cfg->slot, cfg->func, reg, width));
4002 pci_write_config_method(device_t dev, device_t child, int reg,
4003 uint32_t val, int width)
4005 struct pci_devinfo *dinfo = device_get_ivars(child);
4006 pcicfgregs *cfg = &dinfo->cfg;
4008 PCIB_WRITE_CONFIG(device_get_parent(dev),
4009 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4013 pci_child_location_str_method(device_t dev, device_t child, char *buf,
4017 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4018 pci_get_function(child));
4023 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4026 struct pci_devinfo *dinfo;
4029 dinfo = device_get_ivars(child);
4031 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4032 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4033 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4039 pci_assign_interrupt_method(device_t dev, device_t child)
4041 struct pci_devinfo *dinfo = device_get_ivars(child);
4042 pcicfgregs *cfg = &dinfo->cfg;
4044 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4049 pci_modevent(module_t mod, int what, void *arg)
4051 static struct cdev *pci_cdev;
4055 STAILQ_INIT(&pci_devq);
4057 dev_ops_add(&pcic_ops, -1, 0);
4058 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
4060 pci_load_vendor_data();
4064 destroy_dev(pci_cdev);
4072 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4077 * Only do header type 0 devices. Type 1 devices are bridges,
4078 * which we know need special treatment. Type 2 devices are
4079 * cardbus bridges which also require special treatment.
4080 * Other types are unknown, and we err on the side of safety
4083 if (dinfo->cfg.hdrtype != 0)
4087 * Restore the device to full power mode. We must do this
4088 * before we restore the registers because moving from D3 to
4089 * D0 will cause the chip's BARs and some other registers to
4090 * be reset to some unknown power on reset values. Cut down
4091 * the noise on boot by doing nothing if we are already in
4094 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4095 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4097 for (i = 0; i < dinfo->cfg.nummaps; i++)
4098 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4099 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4100 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4101 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4102 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4103 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4104 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4105 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4106 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4107 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4108 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4110 /* Restore MSI and MSI-X configurations if they are present. */
4111 if (dinfo->cfg.msi.msi_location != 0)
4112 pci_resume_msi(dev);
4113 if (dinfo->cfg.msix.msix_location != 0)
4114 pci_resume_msix(dev);
4118 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4125 * Only do header type 0 devices. Type 1 devices are bridges, which
4126 * we know need special treatment. Type 2 devices are cardbus bridges
4127 * which also require special treatment. Other types are unknown, and
4128 * we err on the side of safety by ignoring them. Powering down
4129 * bridges should not be undertaken lightly.
4131 if (dinfo->cfg.hdrtype != 0)
4133 for (i = 0; i < dinfo->cfg.nummaps; i++)
4134 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4135 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4138 * Some drivers apparently write to these registers w/o updating our
4139 * cached copy. No harm happens if we update the copy, so do so here
4140 * so we can restore them. The COMMAND register is modified by the
4141 * bus w/o updating the cache. This should represent the normally
4142 * writable portion of the 'defined' part of type 0 headers. In
4143 * theory we also need to save/restore the PCI capability structures
4144 * we know about, but apart from power we don't know any that are
4147 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4148 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4149 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4150 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4151 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4152 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4153 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4154 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4155 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4156 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4157 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4158 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4159 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4160 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4161 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4164 * don't set the state for display devices, base peripherals and
4165 * memory devices since bad things happen when they are powered down.
4166 * We should (a) have drivers that can easily detach and (b) use
4167 * generic drivers for these devices so that some device actually
4168 * attaches. We need to make sure that when we implement (a) we don't
4169 * power the device down on a reattach.
4171 cls = pci_get_class(dev);
4174 switch (pci_do_power_nodriver)
4176 case 0: /* NO powerdown at all */
4178 case 1: /* Conservative about what to power down */
4179 if (cls == PCIC_STORAGE)
4182 case 2: /* Agressive about what to power down */
4183 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4184 cls == PCIC_BASEPERIPH)
4187 case 3: /* Power down everything */
4191 * PCI spec says we can only go into D3 state from D0 state.
4192 * Transition from D[12] into D0 before going to D3 state.
4194 ps = pci_get_powerstate(dev);
4195 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4196 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4197 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4198 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4201 #ifdef COMPAT_OLDPCI
4204 * Locate the parent of a PCI device by scanning the PCI devlist
4205 * and return the entry for the parent.
4206 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4207 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4210 pci_devlist_get_parent(pcicfgregs *cfg)
4212 struct devlist *devlist_head;
4213 struct pci_devinfo *dinfo;
4214 pcicfgregs *bridge_cfg;
4217 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4219 /* If the device is on PCI bus 0, look for the host */
4220 if (cfg->bus == 0) {
4221 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4222 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4223 bridge_cfg = &dinfo->cfg;
4224 if (bridge_cfg->baseclass == PCIC_BRIDGE
4225 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4226 && bridge_cfg->bus == cfg->bus) {
4232 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4234 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4235 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4236 bridge_cfg = &dinfo->cfg;
4237 if (bridge_cfg->baseclass == PCIC_BRIDGE
4238 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4239 && bridge_cfg->secondarybus == cfg->bus) {
4248 #endif /* COMPAT_OLDPCI */