2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.56 2008/09/17 08:51:29 sephe Exp $
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
102 #include "opt_polling.h"
104 #include <sys/param.h>
105 #include <sys/systm.h>
106 #include <sys/sockio.h>
107 #include <sys/endian.h>
108 #include <sys/mbuf.h>
109 #include <sys/kernel.h>
110 #include <sys/socket.h>
111 #include <sys/serialize.h>
113 #include <sys/rman.h>
114 #include <sys/thread2.h>
115 #include <sys/interrupt.h>
118 #include <net/ifq_var.h>
119 #include <net/if_arp.h>
120 #include <net/ethernet.h>
121 #include <net/if_dl.h>
122 #include <net/if_media.h>
123 #include <net/vlan/if_vlan_var.h>
127 #include "../mii_layer/mii.h"
128 #include "../mii_layer/miivar.h"
130 #include <bus/pci/pcireg.h>
131 #include <bus/pci/pcivar.h>
133 /* "controller miibus0" required. See GENERIC if you get errors here. */
134 #include "miibus_if.h"
136 #include "if_xlreg.h"
138 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
141 * Various supported device vendors/types and their names.
143 static struct xl_type xl_devs[] = {
144 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
145 "3Com 3c900-TPO Etherlink XL" },
146 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
147 "3Com 3c900-COMBO Etherlink XL" },
148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
149 "3Com 3c905-TX Fast Etherlink XL" },
150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
151 "3Com 3c905-T4 Fast Etherlink XL" },
152 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
153 "3Com 3c900B-TPO Etherlink XL" },
154 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
155 "3Com 3c900B-COMBO Etherlink XL" },
156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
157 "3Com 3c900B-TPC Etherlink XL" },
158 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
159 "3Com 3c900B-FL Etherlink XL" },
160 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
161 "3Com 3c905B-TX Fast Etherlink XL" },
162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
163 "3Com 3c905B-T4 Fast Etherlink XL" },
164 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
165 "3Com 3c905B-FX/SC Fast Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
167 "3Com 3c905B-COMBO Fast Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
169 "3Com 3c905C-TX Fast Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
171 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
173 "3Com 3c980 Fast Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
175 "3Com 3c980C Fast Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
177 "3Com 3cSOHO100-TX OfficeConnect" },
178 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
179 "3Com 3c450-TX HomeConnect" },
180 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
181 "3Com 3c555 Fast Etherlink XL" },
182 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
183 "3Com 3c556 Fast Etherlink XL" },
184 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
185 "3Com 3c556B Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
187 "3Com 3c575TX Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
189 "3Com 3c575B Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
191 "3Com 3c575C Fast Etherlink XL" },
192 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
193 "3Com 3c656 Fast Etherlink XL" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
195 "3Com 3c656B Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
197 "3Com 3c656C Fast Etherlink XL" },
201 static int xl_probe (device_t);
202 static int xl_attach (device_t);
203 static int xl_detach (device_t);
204 static void xl_shutdown (device_t);
205 static int xl_suspend (device_t);
206 static int xl_resume (device_t);
208 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
209 static void xl_stats_update (void *);
210 static void xl_stats_update_serialized(void *);
211 static int xl_encap (struct xl_softc *, struct xl_chain *,
213 static void xl_rxeof (struct xl_softc *, int);
214 static int xl_rx_resync (struct xl_softc *);
215 static void xl_txeof (struct xl_softc *);
216 static void xl_txeof_90xB (struct xl_softc *);
217 static void xl_txeoc (struct xl_softc *);
218 static void xl_intr (void *);
219 static void xl_start_body (struct ifnet *, int);
220 static void xl_start (struct ifnet *);
221 static void xl_start_poll (struct ifnet *);
222 static void xl_start_90xB (struct ifnet *);
223 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
225 static void xl_init (void *);
226 static void xl_stop (struct xl_softc *);
227 static void xl_watchdog (struct ifnet *);
228 #ifdef DEVICE_POLLING
229 static void xl_poll (struct ifnet *, enum poll_cmd, int);
231 static void xl_enable_intrs (struct xl_softc *, uint16_t);
233 static int xl_ifmedia_upd (struct ifnet *);
234 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
236 static int xl_eeprom_wait (struct xl_softc *);
237 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
238 static void xl_mii_sync (struct xl_softc *);
239 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
240 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
241 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
243 static void xl_setcfg (struct xl_softc *);
244 static void xl_setmode (struct xl_softc *, int);
245 static void xl_setmulti (struct xl_softc *);
246 static void xl_setmulti_hash (struct xl_softc *);
247 static void xl_reset (struct xl_softc *);
248 static int xl_list_rx_init (struct xl_softc *);
249 static void xl_list_tx_init (struct xl_softc *);
250 static void xl_list_tx_init_90xB(struct xl_softc *);
251 static void xl_wait (struct xl_softc *);
252 static void xl_mediacheck (struct xl_softc *);
253 static void xl_choose_xcvr (struct xl_softc *, int);
254 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
255 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
257 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
260 static int xl_dma_alloc (device_t);
261 static void xl_dma_free (device_t);
264 static void xl_testpacket (struct xl_softc *);
267 static int xl_miibus_readreg (device_t, int, int);
268 static int xl_miibus_writereg (device_t, int, int, int);
269 static void xl_miibus_statchg (device_t);
270 static void xl_miibus_mediainit (device_t);
272 static device_method_t xl_methods[] = {
273 /* Device interface */
274 DEVMETHOD(device_probe, xl_probe),
275 DEVMETHOD(device_attach, xl_attach),
276 DEVMETHOD(device_detach, xl_detach),
277 DEVMETHOD(device_shutdown, xl_shutdown),
278 DEVMETHOD(device_suspend, xl_suspend),
279 DEVMETHOD(device_resume, xl_resume),
282 DEVMETHOD(bus_print_child, bus_generic_print_child),
283 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
286 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
287 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
288 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
289 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
294 static driver_t xl_driver = {
297 sizeof(struct xl_softc)
300 static devclass_t xl_devclass;
302 DECLARE_DUMMY_MODULE(if_xl);
303 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
304 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
305 DRIVER_MODULE(if_xl, cardbus, xl_driver, xl_devclass, 0, 0);
306 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
309 xl_enable_intrs(struct xl_softc *sc, uint16_t intrs)
311 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | 0xFF);
312 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB | intrs);
313 if (sc->xl_flags & XL_FLAG_FUNCREG)
314 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
318 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
323 *paddr = segs->ds_addr;
327 xl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg,
328 bus_size_t mapsize, int error)
334 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
336 *paddr = segs->ds_addr;
340 xl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg,
341 bus_size_t mapsize, int error)
349 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
353 for (i = 0; i < nseg; i++) {
354 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
355 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
356 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
357 total_len += segs[i].ds_len;
359 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
361 l->xl_status = htole32(total_len);
366 * Murphy's law says that it's possible the chip can wedge and
367 * the 'command in progress' bit may never clear. Hence, we wait
368 * only a finite amount of time to avoid getting caught in an
369 * infinite loop. Normally this delay routine would be a macro,
370 * but it isn't called during normal operation so we can afford
371 * to make it a function.
374 xl_wait(struct xl_softc *sc)
378 for (i = 0; i < XL_TIMEOUT; i++) {
379 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
384 if_printf(&sc->arpcom.ac_if, "command never completed!");
390 * MII access routines are provided for adapters with external
391 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
392 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
393 * Note: if you don't perform the MDIO operations just right,
394 * it's possible to end up with code that works correctly with
395 * some chips/CPUs/processor speeds/bus speeds/etc but not
399 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
400 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
403 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
404 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
407 * Sync the PHYs by setting data bit and strobing the clock 32 times.
410 xl_mii_sync(struct xl_softc *sc)
415 MII_SET(XL_MII_DIR|XL_MII_DATA);
417 for (i = 0; i < 32; i++) {
419 MII_SET(XL_MII_DATA);
420 MII_SET(XL_MII_DATA);
422 MII_SET(XL_MII_DATA);
423 MII_SET(XL_MII_DATA);
430 * Clock a series of bits through the MII.
433 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
440 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
442 MII_SET(XL_MII_DATA);
444 MII_CLR(XL_MII_DATA);
452 * Read an PHY register through the MII.
455 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
460 * Set up frame for RX.
462 frame->mii_stdelim = XL_MII_STARTDELIM;
463 frame->mii_opcode = XL_MII_READOP;
464 frame->mii_turnaround = 0;
468 * Select register window 4.
473 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
482 * Send command/address info.
484 xl_mii_send(sc, frame->mii_stdelim, 2);
485 xl_mii_send(sc, frame->mii_opcode, 2);
486 xl_mii_send(sc, frame->mii_phyaddr, 5);
487 xl_mii_send(sc, frame->mii_regaddr, 5);
490 MII_CLR((XL_MII_CLK|XL_MII_DATA));
498 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
502 * Now try reading data bits. If the ack failed, we still
503 * need to clock through 16 cycles to keep the PHY(s) in sync.
506 for(i = 0; i < 16; i++) {
513 for (i = 0x8000; i; i >>= 1) {
516 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
517 frame->mii_data |= i;
533 * Write to a PHY register through the MII.
536 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
539 * Set up frame for TX.
542 frame->mii_stdelim = XL_MII_STARTDELIM;
543 frame->mii_opcode = XL_MII_WRITEOP;
544 frame->mii_turnaround = XL_MII_TURNAROUND;
547 * Select the window 4.
552 * Turn on data output.
558 xl_mii_send(sc, frame->mii_stdelim, 2);
559 xl_mii_send(sc, frame->mii_opcode, 2);
560 xl_mii_send(sc, frame->mii_phyaddr, 5);
561 xl_mii_send(sc, frame->mii_regaddr, 5);
562 xl_mii_send(sc, frame->mii_turnaround, 2);
563 xl_mii_send(sc, frame->mii_data, 16);
578 xl_miibus_readreg(device_t dev, int phy, int reg)
581 struct xl_mii_frame frame;
583 sc = device_get_softc(dev);
586 * Pretend that PHYs are only available at MII address 24.
587 * This is to guard against problems with certain 3Com ASIC
588 * revisions that incorrectly map the internal transceiver
589 * control registers at all MII addresses. This can cause
590 * the miibus code to attach the same PHY several times over.
592 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
595 bzero((char *)&frame, sizeof(frame));
597 frame.mii_phyaddr = phy;
598 frame.mii_regaddr = reg;
599 xl_mii_readreg(sc, &frame);
601 return(frame.mii_data);
605 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
608 struct xl_mii_frame frame;
610 sc = device_get_softc(dev);
612 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
615 bzero((char *)&frame, sizeof(frame));
617 frame.mii_phyaddr = phy;
618 frame.mii_regaddr = reg;
619 frame.mii_data = data;
621 xl_mii_writereg(sc, &frame);
627 xl_miibus_statchg(device_t dev)
630 struct mii_data *mii;
632 sc = device_get_softc(dev);
633 mii = device_get_softc(sc->xl_miibus);
635 ASSERT_SERIALIZED(sc->arpcom.ac_if.if_serializer);
639 /* Set ASIC's duplex mode to match the PHY. */
641 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
642 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
644 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
645 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
649 * Special support for the 3c905B-COMBO. This card has 10/100 support
650 * plus BNC and AUI ports. This means we will have both an miibus attached
651 * plus some non-MII media settings. In order to allow this, we have to
652 * add the extra media to the miibus's ifmedia struct, but we can't do
653 * that during xl_attach() because the miibus hasn't been attached yet.
654 * So instead, we wait until the miibus probe/attach is done, at which
655 * point we will get a callback telling is that it's safe to add our
659 xl_miibus_mediainit(device_t dev)
662 struct mii_data *mii;
665 sc = device_get_softc(dev);
666 mii = device_get_softc(sc->xl_miibus);
667 ifm = &mii->mii_media;
669 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
671 * Check for a 10baseFL board in disguise.
673 if (sc->xl_type == XL_TYPE_905B &&
674 sc->xl_media == XL_MEDIAOPT_10FL) {
676 device_printf(dev, "found 10baseFL\n");
677 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
678 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
679 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
681 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
684 device_printf(dev, "found AUI\n");
685 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
689 if (sc->xl_media & XL_MEDIAOPT_BNC) {
691 device_printf(dev, "found BNC\n");
692 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
699 * The EEPROM is slow: give it time to come ready after issuing
703 xl_eeprom_wait(struct xl_softc *sc)
707 for (i = 0; i < 100; i++) {
708 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
715 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
723 * Read a sequence of words from the EEPROM. Note that ethernet address
724 * data is stored in the EEPROM in network byte order.
727 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
730 u_int16_t word = 0, *ptr;
731 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
732 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
734 * It's easy to accidentally overwrite the rom content!
735 * Note: the 3c575 uses 8bit EEPROM offsets.
739 if (xl_eeprom_wait(sc))
742 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
745 for (i = 0; i < cnt; i++) {
746 if (sc->xl_flags & XL_FLAG_8BITROM)
747 CSR_WRITE_2(sc, XL_W0_EE_CMD,
748 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
750 CSR_WRITE_2(sc, XL_W0_EE_CMD,
751 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
752 err = xl_eeprom_wait(sc);
755 word = CSR_READ_2(sc, XL_W0_EE_DATA);
756 ptr = (u_int16_t *)(dest + (i * 2));
767 * NICs older than the 3c905B have only one multicast option, which
768 * is to enable reception of all multicast frames.
771 xl_setmulti(struct xl_softc *sc)
774 struct ifmultiaddr *ifma;
778 ifp = &sc->arpcom.ac_if;
781 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
783 if (ifp->if_flags & IFF_ALLMULTI) {
784 rxfilt |= XL_RXFILTER_ALLMULTI;
785 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
789 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
793 rxfilt |= XL_RXFILTER_ALLMULTI;
795 rxfilt &= ~XL_RXFILTER_ALLMULTI;
797 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
803 * 3c905B adapters have a hash filter that we can program.
806 xl_setmulti_hash(struct xl_softc *sc)
810 struct ifmultiaddr *ifma;
814 ifp = &sc->arpcom.ac_if;
817 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
819 if (ifp->if_flags & IFF_ALLMULTI) {
820 rxfilt |= XL_RXFILTER_ALLMULTI;
821 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
824 rxfilt &= ~XL_RXFILTER_ALLMULTI;
827 /* first, zot all the existing hash bits */
828 for (i = 0; i < XL_HASHFILT_SIZE; i++)
829 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
831 /* now program new ones */
832 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
833 if (ifma->ifma_addr->sa_family != AF_LINK)
837 * Note: the 3c905B currently only supports a 64-bit
838 * hash table, which means we really only need 6 bits,
839 * but the manual indicates that future chip revisions
840 * will have a 256-bit hash table, hence the routine is
841 * set up to calculate 8 bits of position info in case
842 * we need it some day.
843 * Note II, The Sequel: _CURRENT_ versions of the 3c905B
844 * have a 256 bit hash table. This means we have to use
845 * all 8 bits regardless. On older cards, the upper 2
846 * bits will be ignored. Grrrr....
849 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
850 ETHER_ADDR_LEN) & 0xff;
851 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
856 rxfilt |= XL_RXFILTER_MULTIHASH;
858 rxfilt &= ~XL_RXFILTER_MULTIHASH;
860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
867 xl_testpacket(struct xl_softc *sc)
872 ifp = &sc->arpcom.ac_if;
874 MGETHDR(m, MB_DONTWAIT, MT_DATA);
879 bcopy(&sc->arpcom.ac_enaddr,
880 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
881 bcopy(&sc->arpcom.ac_enaddr,
882 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
883 mtod(m, struct ether_header *)->ether_type = htons(3);
884 mtod(m, unsigned char *)[14] = 0;
885 mtod(m, unsigned char *)[15] = 0;
886 mtod(m, unsigned char *)[16] = 0xE3;
887 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
888 IF_ENQUEUE(&ifp->if_snd, m);
896 xl_setcfg(struct xl_softc *sc)
901 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
902 icfg &= ~XL_ICFG_CONNECTOR_MASK;
903 if (sc->xl_media & XL_MEDIAOPT_MII ||
904 sc->xl_media & XL_MEDIAOPT_BT4)
905 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
906 if (sc->xl_media & XL_MEDIAOPT_BTX)
907 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
909 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
910 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
916 xl_setmode(struct xl_softc *sc, int media)
918 struct ifnet *ifp = &sc->arpcom.ac_if;
922 if_printf(ifp, "selecting ");
925 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
927 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
929 if (sc->xl_media & XL_MEDIAOPT_BT) {
930 if (IFM_SUBTYPE(media) == IFM_10_T) {
931 kprintf("10baseT transceiver, ");
932 sc->xl_xcvr = XL_XCVR_10BT;
933 icfg &= ~XL_ICFG_CONNECTOR_MASK;
934 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
935 mediastat |= XL_MEDIASTAT_LINKBEAT|
936 XL_MEDIASTAT_JABGUARD;
937 mediastat &= ~XL_MEDIASTAT_SQEENB;
941 if (sc->xl_media & XL_MEDIAOPT_BFX) {
942 if (IFM_SUBTYPE(media) == IFM_100_FX) {
943 kprintf("100baseFX port, ");
944 sc->xl_xcvr = XL_XCVR_100BFX;
945 icfg &= ~XL_ICFG_CONNECTOR_MASK;
946 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
947 mediastat |= XL_MEDIASTAT_LINKBEAT;
948 mediastat &= ~XL_MEDIASTAT_SQEENB;
952 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
953 if (IFM_SUBTYPE(media) == IFM_10_5) {
954 kprintf("AUI port, ");
955 sc->xl_xcvr = XL_XCVR_AUI;
956 icfg &= ~XL_ICFG_CONNECTOR_MASK;
957 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
958 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
959 XL_MEDIASTAT_JABGUARD);
960 mediastat |= ~XL_MEDIASTAT_SQEENB;
962 if (IFM_SUBTYPE(media) == IFM_10_FL) {
963 kprintf("10baseFL transceiver, ");
964 sc->xl_xcvr = XL_XCVR_AUI;
965 icfg &= ~XL_ICFG_CONNECTOR_MASK;
966 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
967 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
968 XL_MEDIASTAT_JABGUARD);
969 mediastat |= ~XL_MEDIASTAT_SQEENB;
973 if (sc->xl_media & XL_MEDIAOPT_BNC) {
974 if (IFM_SUBTYPE(media) == IFM_10_2) {
975 kprintf("BNC port, ");
976 sc->xl_xcvr = XL_XCVR_COAX;
977 icfg &= ~XL_ICFG_CONNECTOR_MASK;
978 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
979 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
980 XL_MEDIASTAT_JABGUARD|
981 XL_MEDIASTAT_SQEENB);
985 if ((media & IFM_GMASK) == IFM_FDX ||
986 IFM_SUBTYPE(media) == IFM_100_FX) {
987 kprintf("full duplex\n");
989 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
991 kprintf("half duplex\n");
993 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
994 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
997 if (IFM_SUBTYPE(media) == IFM_10_2)
998 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1000 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1001 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1003 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1009 xl_reset(struct xl_softc *sc)
1014 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1015 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1016 XL_RESETOPT_DISADVFD:0));
1019 * If we're using memory mapped register mode, pause briefly
1020 * after issuing the reset command before trying to access any
1021 * other registers. With my 3c575C cardbus card, failing to do
1022 * this results in the system locking up while trying to poll
1023 * the command busy bit in the status register.
1025 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1028 for (i = 0; i < XL_TIMEOUT; i++) {
1030 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1034 if (i == XL_TIMEOUT)
1035 if_printf(&sc->arpcom.ac_if, "reset didn't complete\n");
1037 /* Reset TX and RX. */
1038 /* Note: the RX reset takes an absurd amount of time
1039 * on newer versions of the Tornado chips such as those
1040 * on the 3c905CX and newer 3c908C cards. We wait an
1041 * extra amount of time so that xl_wait() doesn't complain
1042 * and annoy the users.
1044 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1047 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1050 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1051 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1053 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1054 XL_W2_RESET_OPTIONS)
1055 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1056 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1060 /* Wait a little while for the chip to get its brains in order. */
1066 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1067 * IDs against our list and return a device name if we find a match.
1070 xl_probe(device_t dev)
1075 vid = pci_get_vendor(dev);
1076 did = pci_get_device(dev);
1077 for (t = xl_devs; t->xl_name != NULL; t++) {
1078 if (vid == t->xl_vid && did == t->xl_did) {
1079 device_set_desc(dev, t->xl_name);
1087 * This routine is a kludge to work around possible hardware faults
1088 * or manufacturing defects that can cause the media options register
1089 * (or reset options register, as it's called for the first generation
1090 * 3c90x adapters) to return an incorrect result. I have encountered
1091 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1092 * which doesn't have any of the 'mediaopt' bits set. This screws up
1093 * the attach routine pretty badly because it doesn't know what media
1094 * to look for. If we find ourselves in this predicament, this routine
1095 * will try to guess the media options values and warn the user of a
1096 * possible manufacturing defect with his adapter/system/whatever.
1099 xl_mediacheck(struct xl_softc *sc)
1101 struct ifnet *ifp = &sc->arpcom.ac_if;
1104 * If some of the media options bits are set, assume they are
1105 * correct. If not, try to figure it out down below.
1106 * XXX I should check for 10baseFL, but I don't have an adapter
1109 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1111 * Check the XCVR value. If it's not in the normal range
1112 * of values, we need to fake it up here.
1114 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1117 if_printf(ifp, "bogus xcvr value in EEPROM (%x)\n",
1120 "choosing new default based on card type\n");
1123 if (sc->xl_type == XL_TYPE_905B &&
1124 sc->xl_media & XL_MEDIAOPT_10FL)
1126 if_printf(ifp, "WARNING: no media options bits set in "
1127 "the media options register!!\n");
1128 if_printf(ifp, "this could be a manufacturing defect in "
1129 "your adapter or system\n");
1130 if_printf(ifp, "attempting to guess media type; you "
1131 "should probably consult your vendor\n");
1134 xl_choose_xcvr(sc, 1);
1138 xl_choose_xcvr(struct xl_softc *sc, int verbose)
1140 struct ifnet *ifp = &sc->arpcom.ac_if;
1144 * Read the device ID from the EEPROM.
1145 * This is what's loaded into the PCI device ID register, so it has
1146 * to be correct otherwise we wouldn't have gotten this far.
1148 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1151 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1152 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1153 sc->xl_media = XL_MEDIAOPT_BT;
1154 sc->xl_xcvr = XL_XCVR_10BT;
1156 if_printf(ifp, "guessing 10BaseT transceiver\n");
1158 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1159 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1160 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1161 sc->xl_xcvr = XL_XCVR_10BT;
1163 if_printf(ifp, "guessing COMBO (AUI/BNC/TP)\n");
1165 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1166 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1167 sc->xl_xcvr = XL_XCVR_10BT;
1169 if_printf(ifp, "guessing TPC (BNC/TP)\n");
1171 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1172 sc->xl_media = XL_MEDIAOPT_10FL;
1173 sc->xl_xcvr = XL_XCVR_AUI;
1175 if_printf(ifp, "guessing 10baseFL\n");
1177 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1178 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1179 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1180 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1181 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1182 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1183 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1184 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1185 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1186 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1187 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1188 sc->xl_media = XL_MEDIAOPT_MII;
1189 sc->xl_xcvr = XL_XCVR_MII;
1191 if_printf(ifp, "guessing MII\n");
1193 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1194 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1195 sc->xl_media = XL_MEDIAOPT_BT4;
1196 sc->xl_xcvr = XL_XCVR_MII;
1198 if_printf(ifp, "guessing 100BaseT4/MII\n");
1200 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1201 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1202 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1203 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1204 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1205 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1206 sc->xl_media = XL_MEDIAOPT_BTX;
1207 sc->xl_xcvr = XL_XCVR_AUTO;
1209 if_printf(ifp, "guessing 10/100 internal\n");
1211 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1212 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1213 sc->xl_xcvr = XL_XCVR_AUTO;
1215 if_printf(ifp, "guessing 10/100 plus BNC/AUI\n");
1219 "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1220 sc->xl_media = XL_MEDIAOPT_BT;
1228 * Attach the interface. Allocate softc structures, do ifmedia
1229 * setup and ethernet/BPF attach.
1232 xl_attach(device_t dev)
1234 u_char eaddr[ETHER_ADDR_LEN];
1236 struct xl_softc *sc;
1238 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1239 int error = 0, rid, res;
1242 sc = device_get_softc(dev);
1244 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1246 did = pci_get_device(dev);
1249 if (did == TC_DEVICEID_HURRICANE_555)
1250 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1251 if (did == TC_DEVICEID_HURRICANE_556 ||
1252 did == TC_DEVICEID_HURRICANE_556B)
1253 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1254 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1255 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1256 if (did == TC_DEVICEID_HURRICANE_555 ||
1257 did == TC_DEVICEID_HURRICANE_556)
1258 sc->xl_flags |= XL_FLAG_8BITROM;
1259 if (did == TC_DEVICEID_HURRICANE_556B)
1260 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1261 if (did == TC_DEVICEID_HURRICANE_575B ||
1262 did == TC_DEVICEID_HURRICANE_575C ||
1263 did == TC_DEVICEID_HURRICANE_656B ||
1264 did == TC_DEVICEID_TORNADO_656C)
1265 sc->xl_flags |= XL_FLAG_FUNCREG;
1266 if (did == TC_DEVICEID_HURRICANE_575A ||
1267 did == TC_DEVICEID_HURRICANE_575B ||
1268 did == TC_DEVICEID_HURRICANE_575C ||
1269 did == TC_DEVICEID_HURRICANE_656B ||
1270 did == TC_DEVICEID_TORNADO_656C)
1271 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1273 if (did == TC_DEVICEID_HURRICANE_656)
1274 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1275 if (did == TC_DEVICEID_HURRICANE_575B)
1276 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1277 if (did == TC_DEVICEID_HURRICANE_575C)
1278 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1279 if (did == TC_DEVICEID_TORNADO_656C)
1280 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1281 if (did == TC_DEVICEID_HURRICANE_656 ||
1282 did == TC_DEVICEID_HURRICANE_656B)
1283 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1284 XL_FLAG_INVERT_LED_PWR;
1285 if (did == TC_DEVICEID_TORNADO_10_100BT_920B)
1286 sc->xl_flags |= XL_FLAG_PHYOK;
1287 #ifndef BURN_BRIDGES
1289 * If this is a 3c905B, we have to check one extra thing.
1290 * The 905B supports power management and may be placed in
1291 * a low-power mode (D3 mode), typically by certain operating
1292 * systems which shall not be named. The PCI BIOS is supposed
1293 * to reset the NIC and bring it out of low-power mode, but
1294 * some do not. Consequently, we have to see if this chip
1295 * supports power management, and if so, make sure it's not
1296 * in low-power mode. If power management is available, the
1297 * capid byte will be 0x01.
1299 * I _think_ that what actually happens is that the chip
1300 * loses its PCI configuration during the transition from
1301 * D3 back to D0; this means that it should be possible for
1302 * us to save the PCI iobase, membase and IRQ, put the chip
1303 * back in the D0 state, then restore the PCI config ourselves.
1306 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1307 u_int32_t iobase, membase, irq;
1309 /* Save important PCI config data. */
1310 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1311 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1312 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1314 /* Reset the power state. */
1315 device_printf(dev, "chip is in D%d power mode "
1316 "-- setting to D0\n", pci_get_powerstate(dev));
1318 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1320 /* Restore PCI config data. */
1321 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1322 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1323 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1327 * Map control/status registers.
1329 pci_enable_busmaster(dev);
1332 res = SYS_RES_MEMORY;
1335 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1338 if (sc->xl_res != NULL) {
1339 sc->xl_flags |= XL_FLAG_USE_MMIO;
1341 device_printf(dev, "using memory mapped I/O\n");
1344 res = SYS_RES_IOPORT;
1345 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1346 if (sc->xl_res == NULL) {
1347 device_printf(dev, "couldn't map ports/memory\n");
1352 device_printf(dev, "using port I/O\n");
1355 sc->xl_btag = rman_get_bustag(sc->xl_res);
1356 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1358 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1359 rid = XL_PCI_FUNCMEM;
1360 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1363 if (sc->xl_fres == NULL) {
1364 device_printf(dev, "couldn't map funcreg memory\n");
1369 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1370 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1373 /* Allocate interrupt */
1375 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1376 RF_SHAREABLE | RF_ACTIVE);
1377 if (sc->xl_irq == NULL) {
1378 device_printf(dev, "couldn't map interrupt\n");
1383 ifp = &sc->arpcom.ac_if;
1384 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1386 /* Reset the adapter. */
1390 * Get station address from the EEPROM.
1392 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1393 device_printf(dev, "failed to read station address\n");
1398 callout_init(&sc->xl_stat_timer);
1400 error = xl_dma_alloc(dev);
1405 * Figure out the card type. 3c905B adapters have the
1406 * 'supportsNoTxLength' bit set in the capabilities
1407 * word in the EEPROM.
1408 * Note: my 3c575C cardbus card lies. It returns a value
1409 * of 0x1578 for its capabilities word, which is somewhat
1410 * nonsensical. Another way to distinguish a 3c90x chip
1411 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1412 * bit. This will only be set for 3c90x boomerage chips.
1414 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1415 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1416 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1417 sc->xl_type = XL_TYPE_905B;
1419 sc->xl_type = XL_TYPE_90X;
1421 device_printf(dev, "type %s\n",
1422 sc->xl_type == XL_TYPE_905B ? "90XB" : "90X");
1426 ifp->if_mtu = ETHERMTU;
1427 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1428 ifp->if_ioctl = xl_ioctl;
1429 if (sc->xl_type == XL_TYPE_905B) {
1430 ifp->if_start = xl_start_90xB;
1431 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_MTU;
1433 ifp->if_start = xl_start;
1435 ifp->if_watchdog = xl_watchdog;
1436 ifp->if_init = xl_init;
1437 #ifdef DEVICE_POLLING
1438 ifp->if_poll = xl_poll;
1440 ifp->if_baudrate = 10000000;
1441 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1442 ifq_set_ready(&ifp->if_snd);
1444 * NOTE: Hardware checksum features disabled by default.
1445 * This seems to corrupt tx packet data one out of a
1446 * million packets or so and then generates a good checksum
1447 * so the receiver doesn't know the packet is bad
1449 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1450 if (ifp->if_capenable & IFCAP_TXCSUM)
1451 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1454 * Now we have to see what sort of media we have.
1455 * This includes probing for an MII interace and a
1459 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1461 if_printf(ifp, "media options word: %x\n", sc->xl_media);
1463 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1464 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1465 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1466 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1470 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1471 || sc->xl_media & XL_MEDIAOPT_BT4) {
1473 if_printf(ifp, "found MII/AUTO\n");
1476 error = mii_phy_probe(dev, &sc->xl_miibus,
1477 xl_ifmedia_upd, xl_ifmedia_sts);
1479 if_printf(ifp, "no PHY found!\n");
1487 * Sanity check. If the user has selected "auto" and this isn't
1488 * a 10/100 card of some kind, we need to force the transceiver
1489 * type to something sane.
1491 if (sc->xl_xcvr == XL_XCVR_AUTO)
1492 xl_choose_xcvr(sc, bootverbose);
1497 if (sc->xl_media & XL_MEDIAOPT_BT) {
1499 if_printf(ifp, "found 10baseT\n");
1500 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1501 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1502 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1503 ifmedia_add(&sc->ifmedia,
1504 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1507 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1509 * Check for a 10baseFL board in disguise.
1511 if (sc->xl_type == XL_TYPE_905B &&
1512 sc->xl_media == XL_MEDIAOPT_10FL) {
1514 if_printf(ifp, "found 10baseFL\n");
1515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1516 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1518 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1519 ifmedia_add(&sc->ifmedia,
1520 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1523 if_printf(ifp, "found AUI\n");
1524 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1528 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1530 if_printf(ifp, "found BNC\n");
1531 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1534 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1536 if_printf(ifp, "found 100baseFX\n");
1537 ifp->if_baudrate = 100000000;
1538 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1541 /* Choose a default media. */
1542 switch(sc->xl_xcvr) {
1544 media = IFM_ETHER|IFM_10_T;
1545 xl_setmode(sc, media);
1548 if (sc->xl_type == XL_TYPE_905B &&
1549 sc->xl_media == XL_MEDIAOPT_10FL) {
1550 media = IFM_ETHER|IFM_10_FL;
1551 xl_setmode(sc, media);
1553 media = IFM_ETHER|IFM_10_5;
1554 xl_setmode(sc, media);
1558 media = IFM_ETHER|IFM_10_2;
1559 xl_setmode(sc, media);
1562 case XL_XCVR_100BTX:
1564 /* Chosen by miibus */
1566 case XL_XCVR_100BFX:
1567 media = IFM_ETHER|IFM_100_FX;
1570 if_printf(ifp, "unknown XCVR type: %d\n", sc->xl_xcvr);
1572 * This will probably be wrong, but it prevents
1573 * the ifmedia code from panicking.
1575 media = IFM_ETHER|IFM_10_T;
1579 if (sc->xl_miibus == NULL)
1580 ifmedia_set(&sc->ifmedia, media);
1584 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1586 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1590 * Call MI attach routine.
1592 ether_ifattach(ifp, eaddr, NULL);
1595 * Tell the upper layer(s) we support long frames.
1597 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1599 /* Hook interrupt last to avoid having to lock softc */
1600 error = bus_setup_intr(dev, sc->xl_irq, INTR_MPSAFE,
1601 xl_intr, sc, &sc->xl_intrhand,
1602 ifp->if_serializer);
1604 if_printf(ifp, "couldn't set up irq\n");
1605 ether_ifdetach(ifp);
1609 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->xl_irq));
1610 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1620 * Shutdown hardware and free up resources. This can be called any
1621 * time after the mutex has been initialized. It is called in both
1622 * the error case in attach and the normal detach case so it needs
1623 * to be careful about only freeing resources that have actually been
1627 xl_detach(device_t dev)
1629 struct xl_softc *sc;
1633 sc = device_get_softc(dev);
1634 ifp = &sc->arpcom.ac_if;
1636 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1638 res = SYS_RES_MEMORY;
1641 res = SYS_RES_IOPORT;
1644 if (device_is_attached(dev)) {
1645 lwkt_serialize_enter(ifp->if_serializer);
1648 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1649 lwkt_serialize_exit(ifp->if_serializer);
1651 ether_ifdetach(ifp);
1655 device_delete_child(dev, sc->xl_miibus);
1656 bus_generic_detach(dev);
1657 ifmedia_removeall(&sc->ifmedia);
1660 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1661 if (sc->xl_fres != NULL)
1662 bus_release_resource(dev, SYS_RES_MEMORY,
1663 XL_PCI_FUNCMEM, sc->xl_fres);
1665 bus_release_resource(dev, res, rid, sc->xl_res);
1673 xl_dma_alloc(device_t dev)
1675 struct xl_softc *sc;
1676 struct xl_chain_data *cd;
1677 struct xl_list_data *ld;
1680 sc = device_get_softc(dev);
1685 * Now allocate a tag for the DMA descriptor lists and a chunk
1686 * of DMA-able memory based on the tag. Also obtain the DMA
1687 * addresses of the RX and TX ring, which we'll need later.
1688 * All of our lists are allocated as a contiguous block
1691 error = bus_dma_tag_create(NULL, 8, 0,
1692 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1694 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ,
1697 device_printf(dev, "failed to allocate rx dma tag\n");
1701 error = bus_dmamem_alloc(ld->xl_rx_tag, (void **)&ld->xl_rx_list,
1702 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1705 device_printf(dev, "no memory for rx list buffers!\n");
1706 bus_dma_tag_destroy(ld->xl_rx_tag);
1707 ld->xl_rx_tag = NULL;
1711 error = bus_dmamap_load(ld->xl_rx_tag, ld->xl_rx_dmamap,
1712 ld->xl_rx_list, XL_RX_LIST_SZ,
1713 xl_dma_map_addr, &ld->xl_rx_dmaaddr,
1716 device_printf(dev, "cannot get dma address of the rx ring!\n");
1717 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1719 bus_dma_tag_destroy(ld->xl_rx_tag);
1720 ld->xl_rx_tag = NULL;
1724 error = bus_dma_tag_create(NULL, 8, 0,
1725 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1727 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ,
1730 device_printf(dev, "failed to allocate tx dma tag\n");
1734 error = bus_dmamem_alloc(ld->xl_tx_tag, (void **)&ld->xl_tx_list,
1735 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1738 device_printf(dev, "no memory for list buffers!\n");
1739 bus_dma_tag_destroy(ld->xl_tx_tag);
1740 ld->xl_tx_tag = NULL;
1744 error = bus_dmamap_load(ld->xl_tx_tag, ld->xl_tx_dmamap,
1745 ld->xl_tx_list, XL_TX_LIST_SZ,
1746 xl_dma_map_addr, &ld->xl_tx_dmaaddr,
1749 device_printf(dev, "cannot get dma address of the tx ring!\n");
1750 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1752 bus_dma_tag_destroy(ld->xl_tx_tag);
1753 ld->xl_tx_tag = NULL;
1758 * Allocate a DMA tag for the mapping of mbufs.
1760 error = bus_dma_tag_create(NULL, 1, 0,
1761 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1763 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS,
1764 MCLBYTES, 0, &sc->xl_mtag);
1766 device_printf(dev, "failed to allocate mbuf dma tag\n");
1771 * Allocate a spare DMA map for the RX ring.
1773 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1775 device_printf(dev, "failed to create mbuf dma map\n");
1776 bus_dma_tag_destroy(sc->xl_mtag);
1781 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1782 error = bus_dmamap_create(sc->xl_mtag, 0,
1783 &cd->xl_rx_chain[i].xl_map);
1785 device_printf(dev, "failed to create %dth "
1786 "rx descriptor dma map!\n", i);
1789 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1792 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1793 error = bus_dmamap_create(sc->xl_mtag, 0,
1794 &cd->xl_tx_chain[i].xl_map);
1796 device_printf(dev, "failed to create %dth "
1797 "tx descriptor dma map!\n", i);
1800 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1806 xl_dma_free(device_t dev)
1808 struct xl_softc *sc;
1809 struct xl_chain_data *cd;
1810 struct xl_list_data *ld;
1813 sc = device_get_softc(dev);
1817 for (i = 0; i < XL_RX_LIST_CNT; ++i) {
1818 if (cd->xl_rx_chain[i].xl_ptr != NULL) {
1819 if (cd->xl_rx_chain[i].xl_mbuf != NULL) {
1820 bus_dmamap_unload(sc->xl_mtag,
1821 cd->xl_rx_chain[i].xl_map);
1822 m_freem(cd->xl_rx_chain[i].xl_mbuf);
1824 bus_dmamap_destroy(sc->xl_mtag,
1825 cd->xl_rx_chain[i].xl_map);
1829 for (i = 0; i < XL_TX_LIST_CNT; ++i) {
1830 if (cd->xl_tx_chain[i].xl_ptr != NULL) {
1831 if (cd->xl_tx_chain[i].xl_mbuf != NULL) {
1832 bus_dmamap_unload(sc->xl_mtag,
1833 cd->xl_tx_chain[i].xl_map);
1834 m_freem(cd->xl_tx_chain[i].xl_mbuf);
1836 bus_dmamap_destroy(sc->xl_mtag,
1837 cd->xl_tx_chain[i].xl_map);
1841 if (ld->xl_rx_tag) {
1842 bus_dmamap_unload(ld->xl_rx_tag, ld->xl_rx_dmamap);
1843 bus_dmamem_free(ld->xl_rx_tag, ld->xl_rx_list,
1845 bus_dma_tag_destroy(ld->xl_rx_tag);
1848 if (ld->xl_tx_tag) {
1849 bus_dmamap_unload(ld->xl_tx_tag, ld->xl_tx_dmamap);
1850 bus_dmamem_free(ld->xl_tx_tag, ld->xl_tx_list,
1852 bus_dma_tag_destroy(ld->xl_tx_tag);
1856 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1857 bus_dma_tag_destroy(sc->xl_mtag);
1862 * Initialize the transmit descriptors.
1865 xl_list_tx_init(struct xl_softc *sc)
1867 struct xl_chain_data *cd;
1868 struct xl_list_data *ld;
1873 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1874 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1875 i * sizeof(struct xl_list);
1876 if (i == (XL_TX_LIST_CNT - 1))
1877 cd->xl_tx_chain[i].xl_next = NULL;
1879 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1882 cd->xl_tx_free = &cd->xl_tx_chain[0];
1883 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1885 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1889 * Initialize the transmit descriptors.
1892 xl_list_tx_init_90xB(struct xl_softc *sc)
1894 struct xl_chain_data *cd;
1895 struct xl_list_data *ld;
1900 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1901 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1902 i * sizeof(struct xl_list);
1903 if (i == (XL_TX_LIST_CNT - 1))
1904 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1906 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1908 cd->xl_tx_chain[i].xl_prev =
1909 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1911 cd->xl_tx_chain[i].xl_prev =
1912 &cd->xl_tx_chain[i - 1];
1916 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1922 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1926 * Initialize the RX descriptors and allocate mbufs for them. Note that
1927 * we arrange the descriptors in a closed ring, so that the last descriptor
1928 * points back to the first.
1931 xl_list_rx_init(struct xl_softc *sc)
1933 struct xl_chain_data *cd;
1934 struct xl_list_data *ld;
1941 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1942 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1945 if (i == (XL_RX_LIST_CNT - 1))
1949 nextptr = ld->xl_rx_dmaaddr +
1950 next * sizeof(struct xl_list_onefrag);
1951 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1952 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1955 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1956 cd->xl_rx_head = &cd->xl_rx_chain[0];
1962 * Initialize an RX descriptor and attach an MBUF cluster.
1963 * If we fail to do so, we need to leave the old mbuf and
1964 * the old DMA map untouched so that it can be reused.
1967 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1974 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1978 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1980 /* Force longword alignment for packet payload. */
1981 m_adj(m_new, ETHER_ALIGN);
1983 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
1984 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
1987 if_printf(&sc->arpcom.ac_if, "can't map mbuf (error %d)\n",
1992 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1994 c->xl_map = sc->xl_tmpmap;
1995 sc->xl_tmpmap = map;
1997 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1998 c->xl_ptr->xl_status = 0;
1999 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
2000 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
2005 xl_rx_resync(struct xl_softc *sc)
2007 struct xl_chain_onefrag *pos;
2010 pos = sc->xl_cdata.xl_rx_head;
2012 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2013 if (pos->xl_ptr->xl_status)
2018 if (i == XL_RX_LIST_CNT)
2021 sc->xl_cdata.xl_rx_head = pos;
2027 * A frame has been uploaded: pass the resulting mbuf chain up to
2028 * the higher level protocols.
2031 xl_rxeof(struct xl_softc *sc, int count)
2035 struct xl_chain_onefrag *cur_rx;
2038 struct mbuf_chain chain[MAXCPU];
2040 ifp = &sc->arpcom.ac_if;
2042 ether_input_chain_init(chain);
2045 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2046 BUS_DMASYNC_POSTREAD);
2047 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2048 #ifdef DEVICE_POLLING
2049 if (count >= 0 && count-- == 0)
2052 cur_rx = sc->xl_cdata.xl_rx_head;
2053 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2054 total_len = rxstat & XL_RXSTAT_LENMASK;
2057 * Since we have told the chip to allow large frames,
2058 * we need to trap giant frame errors in software. We allow
2059 * a little more than the normal frame size to account for
2060 * frames with VLAN tags.
2062 if (total_len > XL_MAX_FRAMELEN)
2063 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2066 * If an error occurs, update stats, clear the
2067 * status word and leave the mbuf cluster in place:
2068 * it should simply get re-used next time this descriptor
2069 * comes up in the ring.
2071 if (rxstat & XL_RXSTAT_UP_ERROR) {
2073 cur_rx->xl_ptr->xl_status = 0;
2074 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2075 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2080 * If the error bit was not set, the upload complete
2081 * bit should be set which means we have a valid packet.
2082 * If not, something truly strange has happened.
2084 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2086 "bad receive status -- packet dropped\n");
2088 cur_rx->xl_ptr->xl_status = 0;
2089 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2090 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2094 /* No errors; receive the packet. */
2095 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2096 BUS_DMASYNC_POSTREAD);
2097 m = cur_rx->xl_mbuf;
2100 * Try to conjure up a new mbuf cluster. If that
2101 * fails, it means we have an out of memory condition and
2102 * should leave the buffer in place and continue. This will
2103 * result in a lost packet, but there's little else we
2104 * can do in this situation.
2106 if (xl_newbuf(sc, cur_rx)) {
2108 cur_rx->xl_ptr->xl_status = 0;
2109 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2110 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2113 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2114 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2117 m->m_pkthdr.rcvif = ifp;
2118 m->m_pkthdr.len = m->m_len = total_len;
2120 if (ifp->if_capenable & IFCAP_RXCSUM) {
2121 /* Do IP checksum checking. */
2122 if (rxstat & XL_RXSTAT_IPCKOK)
2123 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2124 if (!(rxstat & XL_RXSTAT_IPCKERR))
2125 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2126 if ((rxstat & XL_RXSTAT_TCPCOK &&
2127 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2128 (rxstat & XL_RXSTAT_UDPCKOK &&
2129 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2130 m->m_pkthdr.csum_flags |=
2131 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2132 CSUM_FRAG_NOT_CHECKED;
2133 m->m_pkthdr.csum_data = 0xffff;
2137 ether_input_chain(ifp, m, chain);
2140 if (sc->xl_type != XL_TYPE_905B) {
2142 * Handle the 'end of channel' condition. When the upload
2143 * engine hits the end of the RX ring, it will stall. This
2144 * is our cue to flush the RX ring, reload the uplist pointer
2145 * register and unstall the engine.
2146 * XXX This is actually a little goofy. With the ThunderLAN
2147 * chip, you get an interrupt when the receiver hits the end
2148 * of the receive ring, which tells you exactly when you
2149 * you need to reload the ring pointer. Here we have to
2150 * fake it. I'm mad at myself for not being clever enough
2151 * to avoid the use of a goto here.
2153 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2154 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2155 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2157 CSR_WRITE_4(sc, XL_UPLIST_PTR,
2158 sc->xl_ldata.xl_rx_dmaaddr);
2159 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2160 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2165 ether_input_dispatch(chain);
2169 * A frame was downloaded to the chip. It's safe for us to clean up
2173 xl_txeof(struct xl_softc *sc)
2175 struct xl_chain *cur_tx;
2178 ifp = &sc->arpcom.ac_if;
2180 /* Clear the timeout timer. */
2184 * Go through our tx list and free mbufs for those
2185 * frames that have been uploaded. Note: the 3c905B
2186 * sets a special bit in the status word to let us
2187 * know that a frame has been downloaded, but the
2188 * original 3c900/3c905 adapters don't do that.
2189 * Consequently, we have to use a different test if
2190 * xl_type != XL_TYPE_905B.
2192 while(sc->xl_cdata.xl_tx_head != NULL) {
2193 cur_tx = sc->xl_cdata.xl_tx_head;
2195 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2198 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2199 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2200 BUS_DMASYNC_POSTWRITE);
2201 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2202 m_freem(cur_tx->xl_mbuf);
2203 cur_tx->xl_mbuf = NULL;
2206 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2207 sc->xl_cdata.xl_tx_free = cur_tx;
2210 if (sc->xl_cdata.xl_tx_head == NULL) {
2211 ifp->if_flags &= ~IFF_OACTIVE;
2212 sc->xl_cdata.xl_tx_tail = NULL;
2214 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2215 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2216 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2217 sc->xl_cdata.xl_tx_head->xl_phys);
2218 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2226 xl_txeof_90xB(struct xl_softc *sc)
2228 struct xl_chain *cur_tx = NULL;
2232 ifp = &sc->arpcom.ac_if;
2234 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2235 BUS_DMASYNC_POSTREAD);
2236 idx = sc->xl_cdata.xl_tx_cons;
2237 while(idx != sc->xl_cdata.xl_tx_prod) {
2239 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2241 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2242 XL_TXSTAT_DL_COMPLETE))
2245 if (cur_tx->xl_mbuf != NULL) {
2246 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2247 BUS_DMASYNC_POSTWRITE);
2248 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2249 m_freem(cur_tx->xl_mbuf);
2250 cur_tx->xl_mbuf = NULL;
2255 sc->xl_cdata.xl_tx_cnt--;
2256 XL_INC(idx, XL_TX_LIST_CNT);
2260 sc->xl_cdata.xl_tx_cons = idx;
2263 ifp->if_flags &= ~IFF_OACTIVE;
2269 * TX 'end of channel' interrupt handler. Actually, we should
2270 * only get a 'TX complete' interrupt if there's a transmit error,
2271 * so this is really TX error handler.
2274 xl_txeoc(struct xl_softc *sc)
2276 struct ifnet *ifp = &sc->arpcom.ac_if;
2279 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2280 if (txstat & XL_TXSTATUS_UNDERRUN ||
2281 txstat & XL_TXSTATUS_JABBER ||
2282 txstat & XL_TXSTATUS_RECLAIM) {
2283 if_printf(ifp, "transmission error: %x\n", txstat);
2284 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2286 if (sc->xl_type == XL_TYPE_905B) {
2287 if (sc->xl_cdata.xl_tx_cnt) {
2290 i = sc->xl_cdata.xl_tx_cons;
2291 c = &sc->xl_cdata.xl_tx_chain[i];
2292 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2294 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2297 if (sc->xl_cdata.xl_tx_head != NULL)
2298 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2299 sc->xl_cdata.xl_tx_head->xl_phys);
2302 * Remember to set this for the
2303 * first generation 3c90X chips.
2305 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2306 if (txstat & XL_TXSTATUS_UNDERRUN &&
2307 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2308 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2309 if_printf(ifp, "tx underrun, increasing tx start"
2310 " threshold to %d bytes\n",
2313 CSR_WRITE_2(sc, XL_COMMAND,
2314 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2315 if (sc->xl_type == XL_TYPE_905B) {
2316 CSR_WRITE_2(sc, XL_COMMAND,
2317 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2319 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2320 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2322 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2323 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2326 * Write an arbitrary byte to the TX_STATUS register
2327 * to clear this interrupt/error and advance to the next.
2329 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2335 #ifdef DEVICE_POLLING
2338 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2340 struct xl_softc *sc = ifp->if_softc;
2342 ASSERT_SERIALIZED(ifp->if_serializer);
2346 xl_enable_intrs(sc, 0);
2347 if (sc->xl_type != XL_TYPE_905B)
2348 ifp->if_start = xl_start_poll;
2350 case POLL_DEREGISTER:
2351 if (sc->xl_type != XL_TYPE_905B)
2352 ifp->if_start = xl_start;
2353 xl_enable_intrs(sc, XL_INTRS);
2356 case POLL_AND_CHECK_STATUS:
2357 xl_rxeof(sc, count);
2358 if (sc->xl_type == XL_TYPE_905B)
2363 if (!ifq_is_empty(&ifp->if_snd))
2366 if (cmd == POLL_AND_CHECK_STATUS) {
2369 /* XXX copy & pasted from xl_intr() */
2370 status = CSR_READ_2(sc, XL_STATUS);
2371 if ((status & XL_INTRS) && status != 0xFFFF) {
2372 CSR_WRITE_2(sc, XL_COMMAND,
2373 XL_CMD_INTR_ACK | (status & XL_INTRS));
2375 if (status & XL_STAT_TX_COMPLETE) {
2380 if (status & XL_STAT_ADFAIL) {
2385 if (status & XL_STAT_STATSOFLOW) {
2386 sc->xl_stats_no_timeout = 1;
2387 xl_stats_update_serialized(sc);
2388 sc->xl_stats_no_timeout = 0;
2396 #endif /* DEVICE_POLLING */
2401 struct xl_softc *sc;
2406 ifp = &sc->arpcom.ac_if;
2408 ASSERT_SERIALIZED(ifp->if_serializer);
2410 while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) &&
2413 CSR_WRITE_2(sc, XL_COMMAND,
2414 XL_CMD_INTR_ACK|(status & XL_INTRS));
2416 if (status & XL_STAT_UP_COMPLETE) {
2419 curpkts = ifp->if_ipackets;
2421 if (curpkts == ifp->if_ipackets) {
2422 while (xl_rx_resync(sc))
2427 if (status & XL_STAT_DOWN_COMPLETE) {
2428 if (sc->xl_type == XL_TYPE_905B)
2434 if (status & XL_STAT_TX_COMPLETE) {
2439 if (status & XL_STAT_ADFAIL) {
2444 if (status & XL_STAT_STATSOFLOW) {
2445 sc->xl_stats_no_timeout = 1;
2446 xl_stats_update_serialized(sc);
2447 sc->xl_stats_no_timeout = 0;
2451 if (!ifq_is_empty(&ifp->if_snd))
2456 xl_stats_update(void *xsc)
2458 struct xl_softc *sc = xsc;
2460 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2461 xl_stats_update_serialized(xsc);
2462 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2466 xl_stats_update_serialized(void *xsc)
2468 struct xl_softc *sc;
2470 struct xl_stats xl_stats;
2473 struct mii_data *mii = NULL;
2475 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2478 ifp = &sc->arpcom.ac_if;
2479 if (sc->xl_miibus != NULL)
2480 mii = device_get_softc(sc->xl_miibus);
2482 p = (u_int8_t *)&xl_stats;
2484 /* Read all the stats registers. */
2487 for (i = 0; i < 16; i++)
2488 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2490 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2492 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2493 xl_stats.xl_tx_single_collision +
2494 xl_stats.xl_tx_late_collision;
2497 * Boomerang and cyclone chips have an extra stats counter
2498 * in window 4 (BadSSD). We have to read this too in order
2499 * to clear out all the stats registers and avoid a statsoflow
2503 CSR_READ_1(sc, XL_W4_BADSSD);
2505 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2510 if (!sc->xl_stats_no_timeout)
2511 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2517 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2518 * pointers to the fragment pointers.
2521 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
2527 ifp = &sc->arpcom.ac_if;
2530 * Start packing the mbufs in this chain into
2531 * the fragment pointers. Stop when we run out
2532 * of fragments or hit the end of the mbuf chain.
2534 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2535 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2537 if (error && error != EFBIG) {
2539 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2544 * Handle special case: we used up all 63 fragments,
2545 * but we have more mbufs left in the chain. Copy the
2546 * data into an mbuf cluster. Note that we don't
2547 * bother clearing the values in the other fragment
2548 * pointers/counters; it wouldn't gain us anything,
2549 * and would waste cycles.
2554 m_new = m_defrag(m_head, MB_DONTWAIT);
2555 if (m_new == NULL) {
2562 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2563 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2566 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2571 if (sc->xl_type == XL_TYPE_905B) {
2572 status = XL_TXSTAT_RND_DEFEAT;
2574 if (m_head->m_pkthdr.csum_flags) {
2575 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2576 status |= XL_TXSTAT_IPCKSUM;
2577 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2578 status |= XL_TXSTAT_TCPCKSUM;
2579 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2580 status |= XL_TXSTAT_UDPCKSUM;
2582 c->xl_ptr->xl_status = htole32(status);
2585 c->xl_mbuf = m_head;
2586 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2591 xl_start(struct ifnet *ifp)
2593 ASSERT_SERIALIZED(ifp->if_serializer);
2594 xl_start_body(ifp, 1);
2598 xl_start_poll(struct ifnet *ifp)
2600 xl_start_body(ifp, 0);
2604 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2605 * to the mbuf data regions directly in the transmit lists. We also save a
2606 * copy of the pointers since the transmit list fragment pointers are
2607 * physical addresses.
2610 xl_start_body(struct ifnet *ifp, int proc_rx)
2612 struct xl_softc *sc;
2613 struct mbuf *m_head = NULL;
2614 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2615 struct xl_chain *prev_tx;
2621 * Check for an available queue slot. If there are none,
2624 if (sc->xl_cdata.xl_tx_free == NULL) {
2627 if (sc->xl_cdata.xl_tx_free == NULL) {
2628 ifp->if_flags |= IFF_OACTIVE;
2633 start_tx = sc->xl_cdata.xl_tx_free;
2635 while(sc->xl_cdata.xl_tx_free != NULL) {
2636 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2640 /* Pick a descriptor off the free list. */
2642 cur_tx = sc->xl_cdata.xl_tx_free;
2644 /* Pack the data into the descriptor. */
2645 error = xl_encap(sc, cur_tx, m_head);
2651 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2652 cur_tx->xl_next = NULL;
2654 /* Chain it together. */
2656 prev->xl_next = cur_tx;
2657 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2661 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2665 * If there are no packets queued, bail.
2671 * Place the request for the upload interrupt
2672 * in the last descriptor in the chain. This way, if
2673 * we're chaining several packets at once, we'll only
2674 * get an interupt once for the whole chain rather than
2675 * once for each packet.
2677 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2681 * Queue the packets. If the TX channel is clear, update
2682 * the downlist pointer register.
2684 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2687 if (sc->xl_cdata.xl_tx_head != NULL) {
2688 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2689 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2690 htole32(start_tx->xl_phys);
2691 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2692 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2693 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2694 sc->xl_cdata.xl_tx_tail = cur_tx;
2696 sc->xl_cdata.xl_tx_head = start_tx;
2697 sc->xl_cdata.xl_tx_tail = cur_tx;
2699 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2700 BUS_DMASYNC_PREWRITE);
2702 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2703 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2705 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2710 * Set a timeout in case the chip goes out to lunch.
2716 * XXX Under certain conditions, usually on slower machines
2717 * where interrupts may be dropped, it's possible for the
2718 * adapter to chew up all the buffers in the receive ring
2719 * and stall, without us being able to do anything about it.
2720 * To guard against this, we need to make a pass over the
2721 * RX queue to make sure there aren't any packets pending.
2722 * Doing it here means we can flush the receive ring at the
2723 * same time the chip is DMAing the transmit descriptors we
2726 * 3Com goes to some lengths to emphasize the Parallel
2727 * Tasking (tm) nature of their chips in all their marketing
2728 * literature; we may as well take advantage of it. :)
2735 xl_start_90xB(struct ifnet *ifp)
2737 struct xl_softc *sc;
2738 struct mbuf *m_head = NULL;
2739 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2740 struct xl_chain *prev_tx;
2743 ASSERT_SERIALIZED(ifp->if_serializer);
2747 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2750 idx = sc->xl_cdata.xl_tx_prod;
2751 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2753 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2755 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2756 ifp->if_flags |= IFF_OACTIVE;
2760 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2765 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2767 /* Pack the data into the descriptor. */
2768 error = xl_encap(sc, cur_tx, m_head);
2774 /* Chain it together. */
2776 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2779 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2781 XL_INC(idx, XL_TX_LIST_CNT);
2782 sc->xl_cdata.xl_tx_cnt++;
2786 * If there are no packets queued, bail.
2792 * Place the request for the upload interrupt
2793 * in the last descriptor in the chain. This way, if
2794 * we're chaining several packets at once, we'll only
2795 * get an interupt once for the whole chain rather than
2796 * once for each packet.
2798 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2801 /* Start transmission */
2802 sc->xl_cdata.xl_tx_prod = idx;
2803 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2805 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2806 BUS_DMASYNC_PREWRITE);
2809 * Set a timeout in case the chip goes out to lunch.
2817 struct xl_softc *sc = xsc;
2818 struct ifnet *ifp = &sc->arpcom.ac_if;
2820 u_int16_t rxfilt = 0;
2821 struct mii_data *mii = NULL;
2823 ASSERT_SERIALIZED(ifp->if_serializer);
2826 * Cancel pending I/O and free all RX/TX buffers.
2830 if (sc->xl_miibus == NULL) {
2831 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2834 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2838 if (sc->xl_miibus != NULL)
2839 mii = device_get_softc(sc->xl_miibus);
2841 /* Init our MAC address */
2843 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2844 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2845 sc->arpcom.ac_enaddr[i]);
2848 /* Clear the station mask. */
2849 for (i = 0; i < 3; i++)
2850 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2852 /* Reset TX and RX. */
2853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2855 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2858 /* Init circular RX list. */
2859 error = xl_list_rx_init(sc);
2861 if_printf(ifp, "initialization of the rx ring failed (%d)\n",
2867 /* Init TX descriptors. */
2868 if (sc->xl_type == XL_TYPE_905B)
2869 xl_list_tx_init_90xB(sc);
2871 xl_list_tx_init(sc);
2874 * Set the TX freethresh value.
2875 * Note that this has no effect on 3c905B "cyclone"
2876 * cards but is required for 3c900/3c905 "boomerang"
2877 * cards in order to enable the download engine.
2879 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2881 /* Set the TX start threshold for best performance. */
2882 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2883 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2886 * If this is a 3c905B, also set the tx reclaim threshold.
2887 * This helps cut down on the number of tx reclaim errors
2888 * that could happen on a busy network. The chip multiplies
2889 * the register value by 16 to obtain the actual threshold
2890 * in bytes, so we divide by 16 when setting the value here.
2891 * The existing threshold value can be examined by reading
2892 * the register at offset 9 in window 5.
2894 if (sc->xl_type == XL_TYPE_905B) {
2895 CSR_WRITE_2(sc, XL_COMMAND,
2896 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2899 /* Set RX filter bits. */
2901 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2903 /* Set the individual bit to receive frames for this host only. */
2904 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2906 /* If we want promiscuous mode, set the allframes bit. */
2907 if (ifp->if_flags & IFF_PROMISC) {
2908 rxfilt |= XL_RXFILTER_ALLFRAMES;
2909 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2911 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2912 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2916 * Set capture broadcast bit to capture broadcast frames.
2918 if (ifp->if_flags & IFF_BROADCAST) {
2919 rxfilt |= XL_RXFILTER_BROADCAST;
2920 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2922 rxfilt &= ~XL_RXFILTER_BROADCAST;
2923 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2927 * Program the multicast filter, if necessary.
2929 if (sc->xl_type == XL_TYPE_905B)
2930 xl_setmulti_hash(sc);
2934 if (sc->xl_type == XL_TYPE_905B) {
2935 /* Set UP polling interval */
2936 CSR_WRITE_1(sc, XL_UP_POLL, 64);
2940 * Load the address of the RX list. We have to
2941 * stall the upload engine before we can manipulate
2942 * the uplist pointer register, then unstall it when
2943 * we're finished. We also have to wait for the
2944 * stall command to complete before proceeding.
2945 * Note that we have to do this after any RX resets
2946 * have completed since the uplist register is cleared
2949 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2951 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2952 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2955 if (sc->xl_type == XL_TYPE_905B) {
2956 /* Set DN polling interval */
2957 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2959 /* Load the address of the TX list */
2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2962 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2963 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2964 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2969 * If the coax transceiver is on, make sure to enable
2970 * the DC-DC converter.
2973 if (sc->xl_xcvr == XL_XCVR_COAX)
2974 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2976 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2979 * increase packet size to allow reception of 802.1q or ISL packets.
2980 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2981 * control register. For 3c90xB/C chips, use the RX packet size
2985 if (sc->xl_type == XL_TYPE_905B) {
2986 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2989 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2990 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2991 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2994 /* Clear out the stats counters. */
2995 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2996 sc->xl_stats_no_timeout = 1;
2997 xl_stats_update_serialized(sc);
2998 sc->xl_stats_no_timeout = 0;
3000 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
3001 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
3004 * Enable interrupts.
3006 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS);
3007 #ifdef DEVICE_POLLING
3008 /* Do not enable interrupt if polling(4) is enabled */
3009 if ((ifp->if_flags & IFF_POLLING) != 0)
3010 xl_enable_intrs(sc, 0);
3013 xl_enable_intrs(sc, XL_INTRS);
3015 /* Set the RX early threshold */
3016 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
3017 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
3019 /* Enable receiver and transmitter. */
3020 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
3022 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3028 /* Select window 7 for normal operations. */
3031 ifp->if_flags |= IFF_RUNNING;
3032 ifp->if_flags &= ~IFF_OACTIVE;
3034 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
3038 * Set media options.
3041 xl_ifmedia_upd(struct ifnet *ifp)
3043 struct xl_softc *sc;
3044 struct ifmedia *ifm = NULL;
3045 struct mii_data *mii = NULL;
3047 ASSERT_SERIALIZED(ifp->if_serializer);
3050 if (sc->xl_miibus != NULL)
3051 mii = device_get_softc(sc->xl_miibus);
3055 ifm = &mii->mii_media;
3057 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3062 xl_setmode(sc, ifm->ifm_media);
3069 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
3070 || sc->xl_media & XL_MEDIAOPT_BT4) {
3073 xl_setmode(sc, ifm->ifm_media);
3080 * Report current media status.
3083 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3085 struct xl_softc *sc;
3087 struct mii_data *mii = NULL;
3089 ASSERT_SERIALIZED(ifp->if_serializer);
3092 if (sc->xl_miibus != NULL)
3093 mii = device_get_softc(sc->xl_miibus);
3096 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3097 icfg >>= XL_ICFG_CONNECTOR_BITS;
3099 ifmr->ifm_active = IFM_ETHER;
3103 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3104 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3105 ifmr->ifm_active |= IFM_FDX;
3107 ifmr->ifm_active |= IFM_HDX;
3110 if (sc->xl_type == XL_TYPE_905B &&
3111 sc->xl_media == XL_MEDIAOPT_10FL) {
3112 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3113 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3114 ifmr->ifm_active |= IFM_FDX;
3116 ifmr->ifm_active |= IFM_HDX;
3118 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3121 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3124 * XXX MII and BTX/AUTO should be separate cases.
3127 case XL_XCVR_100BTX:
3132 ifmr->ifm_active = mii->mii_media_active;
3133 ifmr->ifm_status = mii->mii_media_status;
3136 case XL_XCVR_100BFX:
3137 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3140 if_printf(ifp, "unknown XCVR type: %d\n", icfg);
3148 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3150 struct xl_softc *sc = ifp->if_softc;
3151 struct ifreq *ifr = (struct ifreq *) data;
3153 struct mii_data *mii = NULL;
3156 ASSERT_SERIALIZED(ifp->if_serializer);
3161 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3162 if (ifp->if_flags & IFF_UP) {
3163 if (ifp->if_flags & IFF_RUNNING &&
3164 ifp->if_flags & IFF_PROMISC &&
3165 !(sc->xl_if_flags & IFF_PROMISC)) {
3166 rxfilt |= XL_RXFILTER_ALLFRAMES;
3167 CSR_WRITE_2(sc, XL_COMMAND,
3168 XL_CMD_RX_SET_FILT|rxfilt);
3170 } else if (ifp->if_flags & IFF_RUNNING &&
3171 !(ifp->if_flags & IFF_PROMISC) &&
3172 sc->xl_if_flags & IFF_PROMISC) {
3173 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3174 CSR_WRITE_2(sc, XL_COMMAND,
3175 XL_CMD_RX_SET_FILT|rxfilt);
3180 if (ifp->if_flags & IFF_RUNNING)
3183 sc->xl_if_flags = ifp->if_flags;
3188 if (sc->xl_type == XL_TYPE_905B)
3189 xl_setmulti_hash(sc);
3196 if (sc->xl_miibus != NULL)
3197 mii = device_get_softc(sc->xl_miibus);
3199 error = ifmedia_ioctl(ifp, ifr,
3200 &sc->ifmedia, command);
3202 error = ifmedia_ioctl(ifp, ifr,
3203 &mii->mii_media, command);
3206 ifp->if_capenable &= ~IFCAP_HWCSUM;
3207 ifp->if_capenable |= (ifr->ifr_reqcap & IFCAP_HWCSUM);
3208 if (ifp->if_capenable & IFCAP_HWCSUM)
3209 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3211 ifp->if_hwassist = 0;
3214 error = ether_ioctl(ifp, command, data);
3221 xl_watchdog(struct ifnet *ifp)
3223 struct xl_softc *sc;
3224 u_int16_t status = 0;
3226 ASSERT_SERIALIZED(ifp->if_serializer);
3232 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3233 if_printf(ifp, "watchdog timeout\n");
3235 if (status & XL_MEDIASTAT_CARRIER)
3236 if_printf(ifp, "no carrier - transceiver cable problem?\n");
3243 if (!ifq_is_empty(&ifp->if_snd))
3248 * Stop the adapter and free any mbufs allocated to the
3252 xl_stop(struct xl_softc *sc)
3257 ifp = &sc->arpcom.ac_if;
3258 ASSERT_SERIALIZED(ifp->if_serializer);
3262 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3263 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3264 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3265 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3267 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3268 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3272 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3274 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3278 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3279 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3280 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3281 if (sc->xl_flags & XL_FLAG_FUNCREG)
3282 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3284 /* Stop the stats updater. */
3285 callout_stop(&sc->xl_stat_timer);
3288 * Free data in the RX lists.
3290 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3291 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3292 bus_dmamap_unload(sc->xl_mtag,
3293 sc->xl_cdata.xl_rx_chain[i].xl_map);
3294 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3295 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3298 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3301 * Free the TX list buffers.
3303 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3304 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3305 bus_dmamap_unload(sc->xl_mtag,
3306 sc->xl_cdata.xl_tx_chain[i].xl_map);
3307 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3308 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3311 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3313 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3317 * Stop all chip I/O so that the kernel's probe routines don't
3318 * get confused by errant DMAs when rebooting.
3321 xl_shutdown(device_t dev)
3323 struct xl_softc *sc = device_get_softc(dev);
3325 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3328 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3332 xl_suspend(device_t dev)
3334 struct xl_softc *sc = device_get_softc(dev);
3336 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
3338 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
3344 xl_resume(device_t dev)
3346 struct xl_softc *sc;
3349 sc = device_get_softc(dev);
3350 ifp = &sc->arpcom.ac_if;
3352 lwkt_serialize_enter(ifp->if_serializer);
3354 if (ifp->if_flags & IFF_UP)
3356 lwkt_serialize_exit(ifp->if_serializer);