2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/acx/acx100.c,v 1.2 2006/05/18 13:51:45 sephe Exp $
37 #include <sys/param.h>
39 #include <sys/endian.h>
41 #include <sys/socket.h>
42 #include <sys/sysctl.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
48 #include <net/if_arp.h>
49 #include <net/if_media.h>
51 #include <netproto/802_11/ieee80211.h>
52 #include <netproto/802_11/ieee80211_var.h>
54 #include <bus/pci/pcireg.h>
58 #include "if_acxreg.h"
59 #include "if_acxvar.h"
62 #define ACX100_CONF_FW_RING 0x0003
63 #define ACX100_CONF_MEMOPT 0x0005
65 #define ACX100_INTR_ENABLE (ACXRV_INTR_TX_FINI | ACXRV_INTR_RX_FINI)
67 * XXX do we really care about following interrupts?
69 * ACXRV_INTR_INFO | ACXRV_INTR_SCAN_FINI
72 #define ACX100_INTR_DISABLE (uint16_t)~(ACXRV_INTR_UNKN)
74 #define ACX100_RATE(rate) ((rate) * 5)
76 #define ACX100_TXPOWER 18
77 #define ACX100_GPIO_POWER_LED 0x0800
78 #define ACX100_EE_EADDR_OFS 0x1a
80 #define ACX100_FW_TXRING_SIZE (ACX_TX_DESC_CNT * sizeof(struct acx_fw_txdesc))
81 #define ACX100_FW_RXRING_SIZE (ACX_RX_DESC_CNT * sizeof(struct acx_fw_rxdesc))
85 * Following structs' fields are little endian
88 struct acx100_bss_join {
94 struct acx100_conf_fw_ring {
95 struct acx_conf confcom;
96 uint32_t fw_ring_size; /* total size of fw (tx + rx) ring */
97 uint32_t fw_rxring_addr; /* start phyaddr of fw rx desc */
98 uint8_t opt; /* see ACX100_RINGOPT_ */
99 uint8_t fw_txring_num; /* num of TX ring */
100 uint8_t fw_rxdesc_num; /* num of fw rx desc */
102 uint32_t fw_ring_end[2]; /* see ACX100_SET_RING_END() */
103 uint32_t fw_txring_addr; /* start phyaddr of fw tx desc */
104 uint8_t fw_txring_prio; /* see ACX100_TXRING_PRIO_ */
105 uint8_t fw_txdesc_num; /* num of fw tx desc */
109 #define ACX100_RINGOPT_AUTO_RESET 0x1
110 #define ACX100_TXRING_PRIO_DEFAULT 0
111 #define ACX100_SET_RING_END(conf, end) \
113 (conf)->fw_ring_end[0] = htole32(end); \
114 (conf)->fw_ring_end[1] = htole32(end + 8); \
117 struct acx100_conf_memblk_size {
118 struct acx_conf confcom;
119 uint16_t memblk_size; /* size of each mem block */
122 struct acx100_conf_mem {
123 struct acx_conf confcom;
124 uint32_t opt; /* see ACX100_MEMOPT_ */
125 uint32_t h_rxring_paddr; /* host rx desc start phyaddr */
128 * Memory blocks are controled by hardware
129 * once after they are initialized
131 uint32_t rx_memblk_addr; /* start addr of rx mem blocks */
132 uint32_t tx_memblk_addr; /* start addr of tx mem blocks */
133 uint16_t rx_memblk_num; /* num of RX mem block */
134 uint16_t tx_memblk_num; /* num of TX mem block */
137 #define ACX100_MEMOPT_MEM_INSTR 0x00000000 /* memory access instruct */
138 #define ACX100_MEMOPT_HOSTDESC 0x00010000 /* host indirect desc */
139 #define ACX100_MEMOPT_MEMBLOCK 0x00020000 /* local mem block list */
140 #define ACX100_MEMOPT_IO_INSTR 0x00040000 /* IO instruct */
141 #define ACX100_MEMOPT_PCICONF 0x00080000 /* PCI conf space */
143 #define ACX100_MEMBLK_ALIGN 0x20
145 struct acx100_conf_cca_mode {
146 struct acx_conf confcom;
151 struct acx100_conf_ed_thresh {
152 struct acx_conf confcom;
157 struct acx100_conf_wepkey {
158 struct acx_conf confcom;
159 uint8_t action; /* see ACX100_WEPKEY_ACT_ */
162 #define ACX100_WEPKEY_LEN 29
163 uint8_t key[ACX100_WEPKEY_LEN];
166 #define ACX100_WEPKEY_ACT_ADD 1
168 #define ACX100_CONF_FUNC(sg, name) _ACX_CONF_FUNC(sg, name, 100)
169 #define ACX_CONF_fw_ring ACX100_CONF_FW_RING
170 #define ACX_CONF_memblk_size ACX_CONF_MEMBLK_SIZE
171 #define ACX_CONF_mem ACX100_CONF_MEMOPT
172 #define ACX_CONF_cca_mode ACX_CONF_CCA_MODE
173 #define ACX_CONF_ed_thresh ACX_CONF_ED_THRESH
174 #define ACX_CONF_wepkey ACX_CONF_WEPKEY
175 ACX100_CONF_FUNC(set, fw_ring);
176 ACX100_CONF_FUNC(set, memblk_size);
177 ACX100_CONF_FUNC(set, mem);
178 ACX100_CONF_FUNC(get, cca_mode);
179 ACX100_CONF_FUNC(set, cca_mode);
180 ACX100_CONF_FUNC(get, ed_thresh);
181 ACX100_CONF_FUNC(set, ed_thresh);
182 ACX100_CONF_FUNC(set, wepkey);
184 #define ACXCMD_init_mem ACXCMD_INIT_MEM
185 ACX_NOARG_FUNC(init_mem);
187 static const uint16_t acx100_reg[ACXREG_MAX] = {
188 ACXREG(SOFT_RESET, 0x0000),
190 ACXREG(FWMEM_ADDR, 0x0014),
191 ACXREG(FWMEM_DATA, 0x0018),
192 ACXREG(FWMEM_CTRL, 0x001c),
193 ACXREG(FWMEM_START, 0x0020),
195 ACXREG(EVENT_MASK, 0x0034),
197 ACXREG(INTR_TRIG, 0x007c),
198 ACXREG(INTR_MASK, 0x0098),
199 ACXREG(INTR_STATUS, 0x00a4),
200 ACXREG(INTR_STATUS_CLR, 0x00a8),
201 ACXREG(INTR_ACK, 0x00ac),
203 ACXREG(HINTR_TRIG, 0x00b0),
204 ACXREG(RADIO_ENABLE, 0x0104),
206 ACXREG(EEPROM_INIT, 0x02d0),
207 ACXREG(EEPROM_CTRL, 0x0250),
208 ACXREG(EEPROM_ADDR, 0x0254),
209 ACXREG(EEPROM_DATA, 0x0258),
210 ACXREG(EEPROM_CONF, 0x025c),
211 ACXREG(EEPROM_INFO, 0x02ac),
213 ACXREG(PHY_ADDR, 0x0268),
214 ACXREG(PHY_DATA, 0x026c),
215 ACXREG(PHY_CTRL, 0x0270),
217 ACXREG(GPIO_OUT_ENABLE, 0x0290),
218 ACXREG(GPIO_OUT, 0x0298),
220 ACXREG(CMD_REG_OFFSET, 0x02a4),
221 ACXREG(INFO_REG_OFFSET, 0x02a8),
223 ACXREG(RESET_SENSE, 0x02d4),
224 ACXREG(ECPU_CTRL, 0x02d8)
227 static const uint8_t acx100_txpower_maxim[21] = {
236 static const uint8_t acx100_txpower_rfmd[21] = {
245 static int acx100_init(struct acx_softc *);
246 static int acx100_init_wep(struct acx_softc *);
247 static int acx100_init_tmplt(struct acx_softc *);
248 static int acx100_init_fw_ring(struct acx_softc *);
249 static int acx100_init_memory(struct acx_softc *);
251 static void acx100_init_fw_txring(struct acx_softc *, uint32_t);
252 static void acx100_init_fw_rxring(struct acx_softc *, uint32_t);
254 static int acx100_read_config(struct acx_softc *, struct acx_config *);
255 static int acx100_write_config(struct acx_softc *, struct acx_config *);
257 static int acx100_set_txpower(struct acx_softc *);
259 static void acx100_set_fw_txdesc_rate(struct acx_softc *,
260 struct acx_txbuf *, int);
261 static void acx100_set_bss_join_param(struct acx_softc *, void *, int);
263 static int acx100_set_wepkey(struct acx_softc *, struct ieee80211_key *,
266 static void acx100_proc_wep_rxbuf(struct acx_softc *, struct mbuf *, int *);
269 acx100_set_param(device_t dev)
271 struct acx_softc *sc = device_get_softc(dev);
273 sc->chip_mem1_rid = PCIR_BAR(1);
274 sc->chip_mem2_rid = PCIR_BAR(2);
275 sc->chip_ioreg = acx100_reg;
276 sc->chip_intr_enable = ACX100_INTR_ENABLE;
277 sc->chip_intr_disable = ACX100_INTR_DISABLE;
278 sc->chip_gpio_pled = ACX100_GPIO_POWER_LED;
279 sc->chip_ee_eaddr_ofs = ACX100_EE_EADDR_OFS;
280 sc->chip_txdesc1_len = ACX_FRAME_HDRLEN;
281 sc->chip_fw_txdesc_ctrl = DESC_CTRL_AUTODMA |
283 DESC_CTRL_FIRST_FRAG;
285 sc->chip_phymode = IEEE80211_MODE_11B;
286 sc->chip_chan_flags = IEEE80211_CHAN_B;
287 sc->sc_ic.ic_phytype = IEEE80211_T_DS;
288 sc->sc_ic.ic_sup_rates[IEEE80211_MODE_11B] = acx_rates_11b;
290 sc->chip_init = acx100_init;
291 sc->chip_set_wepkey = acx100_set_wepkey;
292 sc->chip_read_config = acx100_read_config;
293 sc->chip_write_config = acx100_write_config;
294 sc->chip_set_fw_txdesc_rate = acx100_set_fw_txdesc_rate;
295 sc->chip_set_bss_join_param = acx100_set_bss_join_param;
296 sc->chip_proc_wep_rxbuf = acx100_proc_wep_rxbuf;
300 acx100_init(struct acx_softc *sc)
304 * Order of initialization:
307 * 3) Firmware TX/RX ring
309 * Above order is critical to get a correct memory map
312 if (acx100_init_wep(sc) != 0) {
313 if_printf(&sc->sc_ic.ic_if, "%s can't initialize wep\n",
318 if (acx100_init_tmplt(sc) != 0) {
319 if_printf(&sc->sc_ic.ic_if, "%s can't initialize templates\n",
324 if (acx100_init_fw_ring(sc) != 0) {
325 if_printf(&sc->sc_ic.ic_if, "%s can't initialize fw ring\n",
330 if (acx100_init_memory(sc) != 0) {
331 if_printf(&sc->sc_ic.ic_if, "%s can't initialize hw memory\n",
339 acx100_init_wep(struct acx_softc *sc)
341 struct acx_conf_wepopt wep_opt;
342 struct acx_conf_mmap mem_map;
344 /* Set WEP cache start/end address */
345 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
346 if_printf(&sc->sc_ic.ic_if, "can't get mmap\n");
350 mem_map.wep_cache_start = htole32(le32toh(mem_map.code_end) + 4);
351 mem_map.wep_cache_end = htole32(le32toh(mem_map.code_end) + 4);
352 if (acx_set_mmap_conf(sc, &mem_map) != 0) {
353 if_printf(&sc->sc_ic.ic_if, "can't set mmap\n");
357 /* Set WEP options */
358 wep_opt.nkey = htole16(IEEE80211_WEP_NKID + 10);
359 wep_opt.opt = WEPOPT_HDWEP;
360 if (acx_set_wepopt_conf(sc, &wep_opt) != 0) {
361 if_printf(&sc->sc_ic.ic_if, "can't set wep opt\n");
368 acx100_init_tmplt(struct acx_softc *sc)
370 struct acx_conf_mmap mem_map;
371 struct acx_tmplt_tim tim;
373 /* Set templates start address */
374 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
375 if_printf(&sc->sc_ic.ic_if, "can't get mmap\n");
379 mem_map.pkt_tmplt_start = mem_map.wep_cache_end;
380 if (acx_set_mmap_conf(sc, &mem_map) != 0) {
381 if_printf(&sc->sc_ic.ic_if, "can't set mmap\n");
385 /* Initialize various packet templates */
386 if (acx_init_tmplt_ordered(sc) != 0) {
387 if_printf(&sc->sc_ic.ic_if, "can't init tmplt\n");
391 /* Setup TIM template */
392 bzero(&tim, sizeof(tim));
393 tim.tim_eid = IEEE80211_ELEMID_TIM;
394 tim.tim_len = ACX_TIM_LEN(ACX_TIM_BITMAP_LEN);
395 if (_acx_set_tim_tmplt(sc, &tim,
396 ACX_TMPLT_TIM_SIZ(ACX_TIM_BITMAP_LEN)) != 0) {
397 if_printf(&sc->sc_ic.ic_if, "can't set tim tmplt\n");
404 acx100_init_fw_ring(struct acx_softc *sc)
406 struct acx100_conf_fw_ring ring;
407 struct acx_conf_mmap mem_map;
408 uint32_t txring_start, rxring_start, ring_end;
410 /* Set firmware descriptor ring start address */
411 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
412 if_printf(&sc->sc_ic.ic_if, "can't get mmap\n");
416 txring_start = le32toh(mem_map.pkt_tmplt_end) + 4;
417 rxring_start = txring_start + ACX100_FW_TXRING_SIZE;
418 ring_end = rxring_start + ACX100_FW_RXRING_SIZE;
420 mem_map.fw_desc_start = htole32(txring_start);
421 if (acx_set_mmap_conf(sc, &mem_map) != 0) {
422 if_printf(&sc->sc_ic.ic_if, "can't set mmap\n");
426 /* Set firmware descriptor ring configure */
427 bzero(&ring, sizeof(ring));
428 ring.fw_ring_size = htole32(ACX100_FW_TXRING_SIZE +
429 ACX100_FW_RXRING_SIZE + 8);
431 ring.fw_txring_num = 1;
432 ring.fw_txring_addr = htole32(txring_start);
433 ring.fw_txring_prio = ACX100_TXRING_PRIO_DEFAULT;
434 ring.fw_txdesc_num = 0; /* XXX ignored?? */
436 ring.fw_rxring_addr = htole32(rxring_start);
437 ring.fw_rxdesc_num = 0; /* XXX ignored?? */
439 ring.opt = ACX100_RINGOPT_AUTO_RESET;
440 ACX100_SET_RING_END(&ring, ring_end);
441 if (acx100_set_fw_ring_conf(sc, &ring) != 0) {
442 if_printf(&sc->sc_ic.ic_if, "can't set fw ring configure\n");
446 /* Setup firmware TX/RX descriptor ring */
447 acx100_init_fw_txring(sc, txring_start);
448 acx100_init_fw_rxring(sc, rxring_start);
453 #define MEMBLK_ALIGN(addr) \
454 (((addr) + (ACX100_MEMBLK_ALIGN - 1)) & ~(ACX100_MEMBLK_ALIGN - 1))
457 acx100_init_memory(struct acx_softc *sc)
459 struct acx100_conf_memblk_size memblk_sz;
460 struct acx100_conf_mem mem;
461 struct acx_conf_mmap mem_map;
462 uint32_t memblk_start, memblk_end;
463 int total_memblk, txblk_num, rxblk_num;
465 /* Set memory block start address */
466 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
467 if_printf(&sc->sc_ic.ic_if, "can't get mmap\n");
471 mem_map.memblk_start =
472 htole32(MEMBLK_ALIGN(le32toh(mem_map.fw_desc_end) + 4));
474 if (acx_set_mmap_conf(sc, &mem_map) != 0) {
475 if_printf(&sc->sc_ic.ic_if, "can't set mmap\n");
479 /* Set memory block size */
480 memblk_sz.memblk_size = htole16(ACX_MEMBLOCK_SIZE);
481 if (acx100_set_memblk_size_conf(sc, &memblk_sz) != 0) {
482 if_printf(&sc->sc_ic.ic_if, "can't set mem block size\n");
486 /* Get memory map after setting it */
487 if (acx_get_mmap_conf(sc, &mem_map) != 0) {
488 if_printf(&sc->sc_ic.ic_if, "can't get mmap again\n");
491 memblk_start = le32toh(mem_map.memblk_start);
492 memblk_end = le32toh(mem_map.memblk_end);
494 /* Set memory options */
495 mem.opt = htole32(ACX100_MEMOPT_MEMBLOCK | ACX100_MEMOPT_HOSTDESC);
496 mem.h_rxring_paddr = htole32(sc->sc_ring_data.rx_ring_paddr);
498 total_memblk = (memblk_end - memblk_start) / ACX_MEMBLOCK_SIZE;
500 rxblk_num = total_memblk / 2; /* 50% */
501 txblk_num = total_memblk - rxblk_num; /* 50% */
503 DPRINTF((&sc->sc_ic.ic_if, "\ttotal memory blocks\t%d\n"
504 "\trx memory blocks\t%d\n"
505 "\ttx memory blocks\t%d\n",
506 total_memblk, rxblk_num, txblk_num));
508 mem.rx_memblk_num = htole16(rxblk_num);
509 mem.tx_memblk_num = htole16(txblk_num);
511 mem.rx_memblk_addr = htole32(MEMBLK_ALIGN(memblk_start));
513 htole32(MEMBLK_ALIGN(memblk_start +
514 (ACX_MEMBLOCK_SIZE * rxblk_num)));
516 if (acx100_set_mem_conf(sc, &mem) != 0) {
517 if_printf(&sc->sc_ic.ic_if, "can't set mem options\n");
521 /* Initialize memory */
522 if (acx_init_mem(sc) != 0) {
523 if_printf(&sc->sc_ic.ic_if, "can't init mem\n");
532 acx100_init_fw_txring(struct acx_softc *sc, uint32_t fw_txdesc_start)
534 struct acx_fw_txdesc fw_desc;
535 struct acx_txbuf *tx_buf;
536 uint32_t desc_paddr, fw_desc_offset;
539 bzero(&fw_desc, sizeof(fw_desc));
540 fw_desc.f_tx_ctrl = DESC_CTRL_HOSTOWN |
543 DESC_CTRL_FIRST_FRAG;
545 tx_buf = sc->sc_buf_data.tx_buf;
546 fw_desc_offset = fw_txdesc_start;
547 desc_paddr = sc->sc_ring_data.tx_ring_paddr;
549 for (i = 0; i < ACX_TX_DESC_CNT; ++i) {
550 fw_desc.f_tx_host_desc = htole32(desc_paddr);
552 if (i == ACX_TX_DESC_CNT - 1) {
553 fw_desc.f_tx_next_desc = htole32(fw_txdesc_start);
555 fw_desc.f_tx_next_desc =
556 htole32(fw_desc_offset +
557 sizeof(struct acx_fw_txdesc));
560 tx_buf[i].tb_fwdesc_ofs = fw_desc_offset;
561 DESC_WRITE_REGION_1(sc, fw_desc_offset, &fw_desc,
564 desc_paddr += (2 * sizeof(struct acx_host_desc));
565 fw_desc_offset += sizeof(fw_desc);
570 acx100_init_fw_rxring(struct acx_softc *sc, uint32_t fw_rxdesc_start)
572 struct acx_fw_rxdesc fw_desc;
573 uint32_t fw_desc_offset;
576 bzero(&fw_desc, sizeof(fw_desc));
577 fw_desc.f_rx_ctrl = DESC_CTRL_RECLAIM | DESC_CTRL_AUTODMA;
579 fw_desc_offset = fw_rxdesc_start;
581 for (i = 0; i < ACX_RX_DESC_CNT; ++i) {
582 if (i == ACX_RX_DESC_CNT - 1) {
583 fw_desc.f_rx_next_desc = htole32(fw_rxdesc_start);
585 fw_desc.f_rx_next_desc =
586 htole32(fw_desc_offset +
587 sizeof(struct acx_fw_rxdesc));
590 DESC_WRITE_REGION_1(sc, fw_desc_offset, &fw_desc,
593 fw_desc_offset += sizeof(fw_desc);
598 acx100_read_config(struct acx_softc *sc, struct acx_config *conf)
600 struct acx100_conf_cca_mode cca;
601 struct acx100_conf_ed_thresh ed;
605 * CCA mode and ED threshold MUST be read during initialization
606 * or the acx100 card won't work as expected
610 if (acx100_get_cca_mode_conf(sc, &cca) != 0) {
611 if_printf(&sc->sc_ic.ic_if, "%s can't get cca mode\n",
615 conf->cca_mode = cca.cca_mode;
616 DPRINTF((&sc->sc_ic.ic_if, "cca mode %02x\n", cca.cca_mode));
618 /* Get ED threshold */
619 if (acx100_get_ed_thresh_conf(sc, &ed) != 0) {
620 if_printf(&sc->sc_ic.ic_if, "%s can't get ed threshold\n",
624 conf->ed_thresh = ed.ed_thresh;
625 DPRINTF((&sc->sc_ic.ic_if, "ed threshold %02x\n", ed.ed_thresh));
631 acx100_write_config(struct acx_softc *sc, struct acx_config *conf)
633 struct acx100_conf_cca_mode cca;
634 struct acx100_conf_ed_thresh ed;
637 cca.cca_mode = conf->cca_mode;
638 if (acx100_set_cca_mode_conf(sc, &cca) != 0) {
639 if_printf(&sc->sc_ic.ic_if, "%s can't set cca mode\n",
644 /* Set ED threshold */
645 ed.ed_thresh = conf->ed_thresh;
646 if (acx100_set_ed_thresh_conf(sc, &ed) != 0) {
647 if_printf(&sc->sc_ic.ic_if, "%s can't set ed threshold\n",
653 acx100_set_txpower(sc); /* ignore return value */
659 acx100_set_txpower(struct acx_softc *sc)
663 switch (sc->sc_radio_type) {
664 case ACX_RADIO_TYPE_MAXIM:
665 map = acx100_txpower_maxim;
667 case ACX_RADIO_TYPE_RFMD:
668 case ACX_RADIO_TYPE_RALINK:
669 map = acx100_txpower_rfmd;
672 if_printf(&sc->sc_ic.ic_if, "TX power for radio type 0x%02x "
673 "can't be set yet\n", sc->sc_radio_type);
677 acx_write_phyreg(sc, ACXRV_PHYREG_TXPOWER, map[ACX100_TXPOWER]);
682 acx100_set_fw_txdesc_rate(struct acx_softc *sc, struct acx_txbuf *tx_buf,
685 FW_TXDESC_SETFIELD_1(sc, tx_buf, f_tx_rate100, ACX100_RATE(rate));
689 acx100_set_bss_join_param(struct acx_softc *sc, void *param, int dtim_intvl)
691 struct acx100_bss_join *bj = param;
693 bj->dtim_intvl = dtim_intvl;
694 bj->basic_rates = 15; /* XXX */
695 bj->all_rates = 31; /* XXX */
699 acx100_set_wepkey(struct acx_softc *sc, struct ieee80211_key *wk, int wk_idx)
701 struct acx100_conf_wepkey conf_wk;
703 if (wk->wk_keylen > ACX100_WEPKEY_LEN) {
704 if_printf(&sc->sc_ic.ic_if, "%dth WEP key size beyond %d\n",
705 wk_idx, ACX100_WEPKEY_LEN);
709 conf_wk.action = ACX100_WEPKEY_ACT_ADD;
710 conf_wk.key_len = wk->wk_keylen;
711 conf_wk.key_idx = wk_idx;
712 bcopy(wk->wk_key, conf_wk.key, wk->wk_keylen);
713 if (acx100_set_wepkey_conf(sc, &conf_wk) != 0) {
714 if_printf(&sc->sc_ic.ic_if, "%s set %dth WEP key failed\n",
722 acx100_proc_wep_rxbuf(struct acx_softc *sc, struct mbuf *m, int *len)
725 struct ieee80211_frame *f;
728 * Strip leading IV and KID, and trailing CRC
731 f = mtod(m, struct ieee80211_frame *);
733 if ((f->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS)
734 mac_hdrlen = sizeof(struct ieee80211_frame_addr4);
736 mac_hdrlen = sizeof(struct ieee80211_frame);
738 #define IEEEWEP_IVLEN (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN)
739 #define IEEEWEP_EXLEN (IEEEWEP_IVLEN + IEEE80211_WEP_CRCLEN)
741 *len = *len - IEEEWEP_EXLEN;
743 /* Move MAC header toward frame body */
744 ovbcopy(f, (uint8_t *)f + IEEEWEP_IVLEN, mac_hdrlen);
745 m_adj(m, IEEEWEP_IVLEN);