1 /* $OpenBSD: rgephy.c,v 1.12 2006/06/27 05:36:58 brad Exp $ */
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/mii/rgephy.c,v 1.7 2005/09/30 19:39:27 imp Exp $
35 * $DragonFly: src/sys/dev/netif/mii_layer/rgephy.c,v 1.3 2006/08/19 09:33:37 sephe Exp $
39 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/socket.h>
49 #include <machine/bus.h>
50 #include <machine/clock.h>
53 #include <net/if_arp.h>
54 #include <net/if_media.h>
56 #include <dev/netif/mii_layer/mii.h>
57 #include <dev/netif/mii_layer/miivar.h>
58 #include <dev/netif/mii_layer/miidevs.h>
60 #include <dev/netif/re/if_rereg.h>
61 #include <dev/netif/mii_layer/rgephyreg.h>
63 #include "miibus_if.h"
65 #include <machine/bus.h>
67 static int rgephy_probe(device_t);
68 static int rgephy_attach(device_t);
70 static device_method_t rgephy_methods[] = {
71 /* device interface */
72 DEVMETHOD(device_probe, rgephy_probe),
73 DEVMETHOD(device_attach, rgephy_attach),
74 DEVMETHOD(device_detach, ukphy_detach),
75 DEVMETHOD(device_shutdown, bus_generic_shutdown),
79 static const struct mii_phydesc rgephys[] = {
80 MII_PHYDESC(REALTEK2, RTL8169S),
81 MII_PHYDESC(xxREALTEK, RTL8169S),
85 static devclass_t rgephy_devclass;
87 static driver_t rgephy_driver = {
90 sizeof(struct mii_softc)
93 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
95 static int rgephy_service(struct mii_softc *, struct mii_data *, int);
96 static void rgephy_status(struct mii_softc *);
97 static int rgephy_mii_phy_auto(struct mii_softc *);
98 static void rgephy_reset(struct mii_softc *);
99 static void rgephy_loop(struct mii_softc *);
100 static void rgephy_load_dspcode(struct mii_softc *);
103 rgephy_probe(device_t dev)
105 struct mii_attach_args *ma = device_get_ivars(dev);
106 const struct mii_phydesc *mpd;
108 mpd = mii_phy_match(ma, rgephys);
110 device_set_desc(dev, mpd->mpd_name);
112 device_printf(dev, "rev: %d\n", MII_REV(ma->mii_id2));
119 rgephy_attach(device_t dev)
121 struct mii_softc *sc;
122 struct mii_attach_args *ma;
123 struct mii_data *mii;
125 sc = device_get_softc(dev);
126 ma = device_get_ivars(dev);
127 mii_softc_init(sc, ma);
128 sc->mii_dev = device_get_parent(dev);
130 mii = device_get_softc(sc->mii_dev);
131 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
133 sc->mii_inst = mii->mii_instance;
134 sc->mii_service = rgephy_service;
135 sc->mii_reset = rgephy_reset;
138 sc->mii_flags |= MIIF_NOISOLATE;
143 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
144 if (sc->mii_capabilities & BMSR_EXTSTAT)
145 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
147 device_printf(dev, " ");
148 if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
149 (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
150 printf("no media present");
152 mii_phy_add_media(sc);
155 MIIBUS_MEDIAINIT(sc->mii_dev);
160 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
162 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
168 * If we're not polling our PHY instance, just return.
170 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
176 * If the media indicates a different PHY instance,
179 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
180 reg = PHY_READ(sc, MII_BMCR);
181 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
186 * If the interface is not up, don't do anything.
188 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
191 rgephy_reset(sc); /* XXX hardware bug work-around */
193 switch (IFM_SUBTYPE(ife->ifm_media)) {
197 * If we're already in auto mode, just return.
199 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
202 rgephy_mii_phy_auto(sc);
205 speed = RGEPHY_S1000;
214 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
215 speed |= RGEPHY_BMCR_FDX;
216 gig = RGEPHY_1000CTL_AFD;
218 gig = RGEPHY_1000CTL_AHD;
221 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
222 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
223 PHY_WRITE(sc, RGEPHY_MII_ANAR, RGEPHY_SEL_TYPE);
225 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
228 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
229 PHY_WRITE(sc, RGEPHY_MII_BMCR,
230 speed|RGEPHY_BMCR_AUTOEN|RGEPHY_BMCR_STARTNEG);
233 * When settning the link manually, one side must
234 * be the master and the other the slave. However
235 * ifmedia doesn't give us a good way to specify
236 * this, so we fake it by using one of the LINK
237 * flags. If LINK0 is set, we program the PHY to
238 * be a master, otherwise it's a slave.
240 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
241 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
242 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
244 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
245 gig|RGEPHY_1000CTL_MSE);
250 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
261 * If we're not currently selected, just return.
263 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
267 * Is the interface even up?
269 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
273 * Only used for autonegotiation.
275 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
279 * Check to see if we have link. If we do, we don't
280 * need to restart the autonegotiation process.
282 * XXX Read the BMSR twice in case it's latched?
284 reg = PHY_READ(sc, RE_GMEDIASTAT);
285 if (reg & RE_GMEDIASTAT_LINK)
289 * Only retry autonegotiation every mii_anegticks seconds.
291 if (++sc->mii_ticks <= sc->mii_anegticks)
297 * Although rgephy_mii_phy_auto() always returns EJUSTRETURN,
298 * we should not rely on that.
300 if (rgephy_mii_phy_auto(sc) == EJUSTRETURN)
305 /* Update the media status. */
309 * Callback if something changed. Note that we need to poke
310 * the DSP on the RealTek PHYs if the media changes.
312 if (sc->mii_media_active != mii->mii_media_active ||
313 sc->mii_media_status != mii->mii_media_status ||
315 rgephy_load_dspcode(sc);
316 mii_phy_update(sc, cmd);
321 rgephy_status(struct mii_softc *sc)
323 struct mii_data *mii = sc->mii_pdata;
326 mii->mii_media_status = IFM_AVALID;
327 mii->mii_media_active = IFM_ETHER;
329 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
331 if (bmsr & RE_GMEDIASTAT_LINK)
332 mii->mii_media_status |= IFM_ACTIVE;
333 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
335 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
337 if (bmcr & RGEPHY_BMCR_LOOP)
338 mii->mii_media_active |= IFM_LOOP;
340 if (bmcr & RGEPHY_BMCR_AUTOEN) {
341 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
342 /* Erg, still trying, I guess... */
343 mii->mii_media_active |= IFM_NONE;
348 bmsr = PHY_READ(sc, RE_GMEDIASTAT);
350 if (bmsr & RE_GMEDIASTAT_1000MBPS) {
351 mii->mii_media_active |= IFM_1000_T;
352 } else if (bmsr & RE_GMEDIASTAT_100MBPS) {
353 mii->mii_media_active |= IFM_100_TX;
354 } else if (bmsr & RE_GMEDIASTAT_10MBPS) {
355 mii->mii_media_active |= IFM_10_T;
357 mii->mii_media_active |= IFM_NONE;
361 if (bmsr & RE_GMEDIASTAT_FDX)
362 mii->mii_media_active |= IFM_FDX;
366 rgephy_mii_phy_auto(struct mii_softc *sc)
371 PHY_WRITE(sc, RGEPHY_MII_ANAR,
372 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
374 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
375 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
377 PHY_WRITE(sc, RGEPHY_MII_BMCR,
378 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
381 return (EJUSTRETURN);
385 rgephy_loop(struct mii_softc *sc)
390 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
393 for (i = 0; i < 15000; i++) {
394 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
395 if (!(bmsr & RGEPHY_BMSR_LINK)) {
397 device_printf(sc->mii_dev, "looped %d\n", i);
405 #define PHY_SETBIT(x, y, z) \
406 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
407 #define PHY_CLRBIT(x, y, z) \
408 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
411 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
412 * existing revisions of the 8169S/8110S chips need to be tuned in
413 * order to reliably negotiate a 1000Mbps link. This is only needed
414 * for rev 0 and rev 1 of the PHY. Later versions work without
418 rgephy_load_dspcode(struct mii_softc *sc)
425 PHY_WRITE(sc, 31, 0x0001);
426 PHY_WRITE(sc, 21, 0x1000);
427 PHY_WRITE(sc, 24, 0x65C7);
428 PHY_CLRBIT(sc, 4, 0x0800);
429 val = PHY_READ(sc, 4) & 0xFFF;
430 PHY_WRITE(sc, 4, val);
431 PHY_WRITE(sc, 3, 0x00A1);
432 PHY_WRITE(sc, 2, 0x0008);
433 PHY_WRITE(sc, 1, 0x1020);
434 PHY_WRITE(sc, 0, 0x1000);
435 PHY_SETBIT(sc, 4, 0x0800);
436 PHY_CLRBIT(sc, 4, 0x0800);
437 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
438 PHY_WRITE(sc, 4, val);
439 PHY_WRITE(sc, 3, 0xFF41);
440 PHY_WRITE(sc, 2, 0xDE60);
441 PHY_WRITE(sc, 1, 0x0140);
442 PHY_WRITE(sc, 0, 0x0077);
443 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
444 PHY_WRITE(sc, 4, val);
445 PHY_WRITE(sc, 3, 0xDF01);
446 PHY_WRITE(sc, 2, 0xDF20);
447 PHY_WRITE(sc, 1, 0xFF95);
448 PHY_WRITE(sc, 0, 0xFA00);
449 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
450 PHY_WRITE(sc, 4, val);
451 PHY_WRITE(sc, 3, 0xFF41);
452 PHY_WRITE(sc, 2, 0xDE20);
453 PHY_WRITE(sc, 1, 0x0140);
454 PHY_WRITE(sc, 0, 0x00BB);
455 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
456 PHY_WRITE(sc, 4, val);
457 PHY_WRITE(sc, 3, 0xDF01);
458 PHY_WRITE(sc, 2, 0xDF20);
459 PHY_WRITE(sc, 1, 0xFF95);
460 PHY_WRITE(sc, 0, 0xBF00);
461 PHY_SETBIT(sc, 4, 0x0800);
462 PHY_CLRBIT(sc, 4, 0x0800);
463 PHY_WRITE(sc, 31, 0x0000);
469 rgephy_reset(struct mii_softc *sc)
473 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_AUTOEN);
475 rgephy_load_dspcode(sc);