1 /*******************************************************************************
3 Copyright (c) 2001-2003, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 *******************************************************************************/
34 /*$FreeBSD: src/sys/dev/em/if_em_hw.c,v 1.1.2.8 2003/06/09 21:43:41 pdeuskar Exp $*/
36 * Shared functions for accessing and configuring the MAC
39 #include <dev/em/if_em_hw.h>
41 static int32_t em_set_phy_type(struct em_hw *hw);
42 static void em_phy_init_script(struct em_hw *hw);
43 static int32_t em_setup_fiber_link(struct em_hw *hw);
44 static int32_t em_setup_copper_link(struct em_hw *hw);
45 static int32_t em_phy_force_speed_duplex(struct em_hw *hw);
46 static int32_t em_config_mac_to_phy(struct em_hw *hw);
47 static int32_t em_force_mac_fc(struct em_hw *hw);
48 static void em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
49 static void em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl);
50 static void em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count);
51 static uint16_t em_shift_in_mdi_bits(struct em_hw *hw);
52 static int32_t em_phy_reset_dsp(struct em_hw *hw);
53 static int32_t em_write_eeprom_spi(struct em_hw *hw, uint16_t offset,
54 uint16_t words, uint16_t *data);
55 static int32_t em_write_eeprom_microwire(struct em_hw *hw,
56 uint16_t offset, uint16_t words,
58 static int32_t em_spi_eeprom_ready(struct em_hw *hw);
59 static void em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd);
60 static void em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd);
61 static void em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count);
62 static uint16_t em_shift_in_ee_bits(struct em_hw *hw, uint16_t count);
63 static int32_t em_acquire_eeprom(struct em_hw *hw);
64 static void em_release_eeprom(struct em_hw *hw);
65 static void em_standby_eeprom(struct em_hw *hw);
66 static int32_t em_id_led_init(struct em_hw * hw);
70 /******************************************************************************
71 * Set the phy type member in the hw struct.
73 * hw - Struct containing variables accessed by shared code
74 *****************************************************************************/
76 em_set_phy_type(struct em_hw *hw)
78 DEBUGFUNC("em_set_phy_type");
81 case M88E1000_E_PHY_ID:
82 case M88E1000_I_PHY_ID:
83 case M88E1011_I_PHY_ID:
84 hw->phy_type = em_phy_m88;
86 case IGP01E1000_I_PHY_ID:
87 hw->phy_type = em_phy_igp;
90 /* Should never have loaded on this device */
91 hw->phy_type = em_phy_undefined;
92 return -E1000_ERR_PHY_TYPE;
98 /******************************************************************************
99 * IGP phy init script - initializes the GbE PHY
101 * hw - Struct containing variables accessed by shared code
102 *****************************************************************************/
104 em_phy_init_script(struct em_hw *hw)
106 DEBUGFUNC("em_phy_init_script");
108 if(hw->phy_init_script) {
111 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x0000);
112 em_write_phy_reg(hw,0x0000,0x0140);
115 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F95);
116 em_write_phy_reg(hw,0x0015,0x0001);
118 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F71);
119 em_write_phy_reg(hw,0x0011,0xBD21);
121 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F79);
122 em_write_phy_reg(hw,0x0019,0x0018);
124 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F30);
125 em_write_phy_reg(hw,0x0010,0x1600);
127 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F31);
128 em_write_phy_reg(hw,0x0011,0x0014);
130 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F32);
131 em_write_phy_reg(hw,0x0012,0x161C);
133 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F94);
134 em_write_phy_reg(hw,0x0014,0x0003);
136 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x1F96);
137 em_write_phy_reg(hw,0x0016,0x003F);
139 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x2010);
140 em_write_phy_reg(hw,0x0010,0x0008);
142 em_write_phy_reg(hw,IGP01E1000_PHY_PAGE_SELECT,0x0000);
143 em_write_phy_reg(hw,0x0000,0x3300);
147 /******************************************************************************
148 * Set the mac type member in the hw struct.
150 * hw - Struct containing variables accessed by shared code
151 *****************************************************************************/
153 em_set_mac_type(struct em_hw *hw)
155 DEBUGFUNC("em_set_mac_type");
157 switch (hw->device_id) {
158 case E1000_DEV_ID_82542:
159 switch (hw->revision_id) {
160 case E1000_82542_2_0_REV_ID:
161 hw->mac_type = em_82542_rev2_0;
163 case E1000_82542_2_1_REV_ID:
164 hw->mac_type = em_82542_rev2_1;
167 /* Invalid 82542 revision ID */
168 return -E1000_ERR_MAC_TYPE;
171 case E1000_DEV_ID_82543GC_FIBER:
172 case E1000_DEV_ID_82543GC_COPPER:
173 hw->mac_type = em_82543;
175 case E1000_DEV_ID_82544EI_COPPER:
176 case E1000_DEV_ID_82544EI_FIBER:
177 case E1000_DEV_ID_82544GC_COPPER:
178 case E1000_DEV_ID_82544GC_LOM:
179 hw->mac_type = em_82544;
181 case E1000_DEV_ID_82540EM:
182 case E1000_DEV_ID_82540EM_LOM:
183 case E1000_DEV_ID_82540EP:
184 case E1000_DEV_ID_82540EP_LOM:
185 case E1000_DEV_ID_82540EP_LP:
186 hw->mac_type = em_82540;
188 case E1000_DEV_ID_82545EM_COPPER:
189 case E1000_DEV_ID_82545EM_FIBER:
190 hw->mac_type = em_82545;
192 case E1000_DEV_ID_82546EB_COPPER:
193 case E1000_DEV_ID_82546EB_FIBER:
194 case E1000_DEV_ID_82546EB_QUAD_COPPER:
195 hw->mac_type = em_82546;
197 case E1000_DEV_ID_82541EI:
198 case E1000_DEV_ID_82541EP:
199 hw->mac_type = em_82541;
201 case E1000_DEV_ID_82547EI:
202 hw->mac_type = em_82547;
205 /* Should never have loaded on this device */
206 return -E1000_ERR_MAC_TYPE;
210 return E1000_SUCCESS;
212 /******************************************************************************
213 * Reset the transmit and receive units; mask and clear all interrupts.
215 * hw - Struct containing variables accessed by shared code
216 *****************************************************************************/
218 em_reset_hw(struct em_hw *hw)
226 DEBUGFUNC("em_reset_hw");
228 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
229 if(hw->mac_type == em_82542_rev2_0) {
230 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
231 em_pci_clear_mwi(hw);
234 /* Clear interrupt mask to stop board from generating interrupts */
235 DEBUGOUT("Masking off all interrupts\n");
236 E1000_WRITE_REG(hw, IMC, 0xffffffff);
238 /* Disable the Transmit and Receive units. Then delay to allow
239 * any pending transactions to complete before we hit the MAC with
242 E1000_WRITE_REG(hw, RCTL, 0);
243 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
244 E1000_WRITE_FLUSH(hw);
246 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
247 hw->tbi_compatibility_on = FALSE;
249 /* Delay to allow any outstanding PCI transactions to complete before
250 * resetting the device
254 /* Issue a global reset to the MAC. This will reset the chip's
255 * transmit, receive, DMA, and link units. It will not effect
256 * the current PCI configuration. The global reset bit is self-
257 * clearing, and should clear within a microsecond.
259 DEBUGOUT("Issuing a global reset to MAC\n");
260 ctrl = E1000_READ_REG(hw, CTRL);
262 /* Must reset the PHY before resetting the MAC */
263 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
264 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
268 switch(hw->mac_type) {
274 /* These controllers can't ack the 64-bit write when issuing the
275 * reset, so use IO-mapping as a workaround to issue the reset */
276 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
279 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
283 /* Force a reload from the EEPROM if necessary */
284 if(hw->mac_type < em_82540) {
285 /* Wait for reset to complete */
287 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
288 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
289 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
290 E1000_WRITE_FLUSH(hw);
291 /* Wait for EEPROM reload */
294 /* Wait for EEPROM reload (it happens automatically) */
296 /* Dissable HW ARPs on ASF enabled adapters */
297 manc = E1000_READ_REG(hw, MANC);
298 manc &= ~(E1000_MANC_ARP_EN);
299 E1000_WRITE_REG(hw, MANC, manc);
302 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
303 em_phy_init_script(hw);
305 /* Configure activity LED after PHY reset */
306 led_ctrl = E1000_READ_REG(hw, LEDCTL);
307 led_ctrl &= IGP_ACTIVITY_LED_MASK;
308 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
309 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
312 /* Clear interrupt mask to stop board from generating interrupts */
313 DEBUGOUT("Masking off all interrupts\n");
314 E1000_WRITE_REG(hw, IMC, 0xffffffff);
316 /* Clear any pending interrupt events. */
317 icr = E1000_READ_REG(hw, ICR);
319 /* If MWI was previously enabled, reenable it. */
320 if(hw->mac_type == em_82542_rev2_0) {
321 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
326 /******************************************************************************
327 * Performs basic configuration of the adapter.
329 * hw - Struct containing variables accessed by shared code
331 * Assumes that the controller has previously been reset and is in a
332 * post-reset uninitialized state. Initializes the receive address registers,
333 * multicast table, and VLAN filter table. Calls routines to setup link
334 * configuration and flow control settings. Clears all on-chip counters. Leaves
335 * the transmit and receive units disabled and uninitialized.
336 *****************************************************************************/
338 em_init_hw(struct em_hw *hw)
340 uint32_t ctrl, status;
343 uint16_t pcix_cmd_word;
344 uint16_t pcix_stat_hi_word;
348 DEBUGFUNC("em_init_hw");
350 /* Initialize Identification LED */
351 ret_val = em_id_led_init(hw);
353 DEBUGOUT("Error Initializing Identification LED\n");
357 /* Set the Media Type and exit with error if it is not valid. */
358 if(hw->mac_type != em_82543) {
359 /* tbi_compatibility is only valid on 82543 */
360 hw->tbi_compatibility_en = FALSE;
363 if(hw->mac_type >= em_82543) {
364 status = E1000_READ_REG(hw, STATUS);
365 if(status & E1000_STATUS_TBIMODE) {
366 hw->media_type = em_media_type_fiber;
367 /* tbi_compatibility not valid on fiber */
368 hw->tbi_compatibility_en = FALSE;
370 hw->media_type = em_media_type_copper;
373 /* This is an 82542 (fiber only) */
374 hw->media_type = em_media_type_fiber;
377 /* Disabling VLAN filtering. */
378 DEBUGOUT("Initializing the IEEE VLAN\n");
379 E1000_WRITE_REG(hw, VET, 0);
383 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
384 if(hw->mac_type == em_82542_rev2_0) {
385 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
386 em_pci_clear_mwi(hw);
387 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
388 E1000_WRITE_FLUSH(hw);
392 /* Setup the receive address. This involves initializing all of the Receive
393 * Address Registers (RARs 0 - 15).
395 em_init_rx_addrs(hw);
397 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
398 if(hw->mac_type == em_82542_rev2_0) {
399 E1000_WRITE_REG(hw, RCTL, 0);
400 E1000_WRITE_FLUSH(hw);
402 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
406 /* Zero out the Multicast HASH table */
407 DEBUGOUT("Zeroing the MTA\n");
408 for(i = 0; i < E1000_MC_TBL_SIZE; i++)
409 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
411 /* Set the PCI priority bit correctly in the CTRL register. This
412 * determines if the adapter gives priority to receives, or if it
413 * gives equal priority to transmits and receives.
415 if(hw->dma_fairness) {
416 ctrl = E1000_READ_REG(hw, CTRL);
417 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
420 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
421 if(hw->bus_type == em_bus_type_pcix) {
422 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
423 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
424 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
425 PCIX_COMMAND_MMRBC_SHIFT;
426 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
427 PCIX_STATUS_HI_MMRBC_SHIFT;
428 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
429 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
430 if(cmd_mmrbc > stat_mmrbc) {
431 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
432 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
433 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
437 /* Call a subroutine to configure the link and setup flow control. */
438 ret_val = em_setup_link(hw);
440 /* Set the transmit descriptor write-back policy */
441 if(hw->mac_type > em_82544) {
442 ctrl = E1000_READ_REG(hw, TXDCTL);
443 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
444 E1000_WRITE_REG(hw, TXDCTL, ctrl);
447 /* Clear all of the statistics registers (clear on read). It is
448 * important that we do this after we have tried to establish link
449 * because the symbol error count will increment wildly if there
452 em_clear_hw_cntrs(hw);
457 /******************************************************************************
458 * Configures flow control and link settings.
460 * hw - Struct containing variables accessed by shared code
462 * Determines which flow control settings to use. Calls the apropriate media-
463 * specific link configuration function. Configures the flow control settings.
464 * Assuming the adapter has a valid link partner, a valid link should be
465 * established. Assumes the hardware has previously been reset and the
466 * transmitter and receiver are not enabled.
467 *****************************************************************************/
469 em_setup_link(struct em_hw *hw)
473 uint16_t eeprom_data;
475 DEBUGFUNC("em_setup_link");
477 /* Read and store word 0x0F of the EEPROM. This word contains bits
478 * that determine the hardware's default PAUSE (flow control) mode,
479 * a bit that determines whether the HW defaults to enabling or
480 * disabling auto-negotiation, and the direction of the
481 * SW defined pins. If there is no SW over-ride of the flow
482 * control setting, then the variable hw->fc will
483 * be initialized based on a value in the EEPROM.
485 if(em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
486 DEBUGOUT("EEPROM Read Error\n");
487 return -E1000_ERR_EEPROM;
490 if(hw->fc == em_fc_default) {
491 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
493 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
494 EEPROM_WORD0F_ASM_DIR)
495 hw->fc = em_fc_tx_pause;
500 /* We want to save off the original Flow Control configuration just
501 * in case we get disconnected and then reconnected into a different
502 * hub or switch with different Flow Control capabilities.
504 if(hw->mac_type == em_82542_rev2_0)
505 hw->fc &= (~em_fc_tx_pause);
507 if((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
508 hw->fc &= (~em_fc_rx_pause);
510 hw->original_fc = hw->fc;
512 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
514 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
515 * polarity value for the SW controlled pins, and setup the
516 * Extended Device Control reg with that info.
517 * This is needed because one of the SW controlled pins is used for
518 * signal detection. So this should be done before em_setup_pcs_link()
519 * or em_phy_setup() is called.
521 if(hw->mac_type == em_82543) {
522 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
524 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
527 /* Call the necessary subroutine to configure the link. */
528 ret_val = (hw->media_type == em_media_type_fiber) ?
529 em_setup_fiber_link(hw) :
530 em_setup_copper_link(hw);
532 /* Initialize the flow control address, type, and PAUSE timer
533 * registers to their default values. This is done even if flow
534 * control is disabled, because it does not hurt anything to
535 * initialize these registers.
537 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
539 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
540 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
541 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
542 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
544 /* Set the flow control receive threshold registers. Normally,
545 * these registers will be set to a default threshold that may be
546 * adjusted later by the driver's runtime code. However, if the
547 * ability to transmit pause frames in not enabled, then these
548 * registers will be set to 0.
550 if(!(hw->fc & em_fc_tx_pause)) {
551 E1000_WRITE_REG(hw, FCRTL, 0);
552 E1000_WRITE_REG(hw, FCRTH, 0);
554 /* We need to set up the Receive Threshold high and low water marks
555 * as well as (optionally) enabling the transmission of XON frames.
557 if(hw->fc_send_xon) {
558 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
559 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
561 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
562 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
568 /******************************************************************************
569 * Sets up link for a fiber based adapter
571 * hw - Struct containing variables accessed by shared code
573 * Manipulates Physical Coding Sublayer functions in order to configure
574 * link. Assumes the hardware has been previously reset and the transmitter
575 * and receiver are not enabled.
576 *****************************************************************************/
578 em_setup_fiber_link(struct em_hw *hw)
587 DEBUGFUNC("em_setup_fiber_link");
589 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
590 * set when the optics detect a signal. On older adapters, it will be
591 * cleared when there is a signal
593 ctrl = E1000_READ_REG(hw, CTRL);
594 if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
597 /* Take the link out of reset */
598 ctrl &= ~(E1000_CTRL_LRST);
600 em_config_collision_dist(hw);
602 /* Check for a software override of the flow control settings, and setup
603 * the device accordingly. If auto-negotiation is enabled, then software
604 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
605 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
606 * auto-negotiation is disabled, then software will have to manually
607 * configure the two flow control enable bits in the CTRL register.
609 * The possible values of the "fc" parameter are:
610 * 0: Flow control is completely disabled
611 * 1: Rx flow control is enabled (we can receive pause frames, but
612 * not send pause frames).
613 * 2: Tx flow control is enabled (we can send pause frames but we do
614 * not support receiving pause frames).
615 * 3: Both Rx and TX flow control (symmetric) are enabled.
619 /* Flow control is completely disabled by a software over-ride. */
620 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
623 /* RX Flow control is enabled and TX Flow control is disabled by a
624 * software over-ride. Since there really isn't a way to advertise
625 * that we are capable of RX Pause ONLY, we will advertise that we
626 * support both symmetric and asymmetric RX PAUSE. Later, we will
627 * disable the adapter's ability to send PAUSE frames.
629 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
632 /* TX Flow control is enabled, and RX Flow control is disabled, by a
633 * software over-ride.
635 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
638 /* Flow control (both RX and TX) is enabled by a software over-ride. */
639 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
642 DEBUGOUT("Flow control param set incorrectly\n");
643 return -E1000_ERR_CONFIG;
647 /* Since auto-negotiation is enabled, take the link out of reset (the link
648 * will be in reset, because we previously reset the chip). This will
649 * restart auto-negotiation. If auto-neogtiation is successful then the
650 * link-up status bit will be set and the flow control enable bits (RFCE
651 * and TFCE) will be set according to their negotiated value.
653 DEBUGOUT("Auto-negotiation enabled\n");
655 E1000_WRITE_REG(hw, TXCW, txcw);
656 E1000_WRITE_REG(hw, CTRL, ctrl);
657 E1000_WRITE_FLUSH(hw);
662 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
663 * indication in the Device Status Register. Time-out if a link isn't
664 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
665 * less than 500 milliseconds even if the other end is doing it in SW).
667 if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
668 DEBUGOUT("Looking for Link\n");
669 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
671 status = E1000_READ_REG(hw, STATUS);
672 if(status & E1000_STATUS_LU) break;
674 if(i == (LINK_UP_TIMEOUT / 10)) {
675 /* AutoNeg failed to achieve a link, so we'll call
676 * em_check_for_link. This routine will force the link up if we
677 * detect a signal. This will allow us to communicate with
678 * non-autonegotiating link partners.
680 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
681 hw->autoneg_failed = 1;
682 ret_val = em_check_for_link(hw);
684 DEBUGOUT("Error while checking for link\n");
687 hw->autoneg_failed = 0;
689 hw->autoneg_failed = 0;
690 DEBUGOUT("Valid Link Found\n");
693 DEBUGOUT("No Signal Detected\n");
698 /******************************************************************************
699 * Detects which PHY is present and the speed and duplex
701 * hw - Struct containing variables accessed by shared code
702 ******************************************************************************/
704 em_setup_copper_link(struct em_hw *hw)
712 DEBUGFUNC("em_setup_copper_link");
714 ctrl = E1000_READ_REG(hw, CTRL);
715 /* With 82543, we need to force speed and duplex on the MAC equal to what
716 * the PHY speed and duplex configuration is. In addition, we need to
717 * perform a hardware reset on the PHY to take it out of reset.
719 if(hw->mac_type > em_82543) {
720 ctrl |= E1000_CTRL_SLU;
721 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
722 E1000_WRITE_REG(hw, CTRL, ctrl);
724 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
725 E1000_WRITE_REG(hw, CTRL, ctrl);
729 /* Make sure we have a valid PHY */
730 ret_val = em_detect_gig_phy(hw);
732 DEBUGOUT("Error, did not detect valid phy.\n");
735 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
737 if (hw->phy_type == em_phy_igp) {
739 ret_val = em_phy_reset(hw);
741 DEBUGOUT("Error Resetting the PHY\n");
745 /* Wait 10ms for MAC to configure PHY from eeprom settings */
748 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0000) < 0) {
749 DEBUGOUT("PHY Write Error\n");
750 return -E1000_ERR_PHY;
753 /* Configure activity LED after PHY reset */
754 led_ctrl = E1000_READ_REG(hw, LEDCTL);
755 led_ctrl &= IGP_ACTIVITY_LED_MASK;
756 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
757 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
759 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
760 /* Disable SmartSpeed */
761 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
763 DEBUGOUT("PHY Read Error\n");
764 return -E1000_ERR_PHY;
766 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
767 if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
769 DEBUGOUT("PHY Write Error\n");
770 return -E1000_ERR_PHY;
772 /* Set auto Master/Slave resolution process */
773 if(em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data) < 0) {
774 DEBUGOUT("PHY Read Error\n");
775 return -E1000_ERR_PHY;
777 phy_data &= ~CR_1000T_MS_ENABLE;
778 if(em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data) < 0) {
779 DEBUGOUT("PHY Write Error\n");
780 return -E1000_ERR_PHY;
784 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data) < 0) {
785 DEBUGOUT("PHY Read Error\n");
786 return -E1000_ERR_PHY;
789 /* Force MDI for IGP PHY */
790 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
791 IGP01E1000_PSCR_FORCE_MDI_MDIX);
795 if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data) < 0) {
796 DEBUGOUT("PHY Write Error\n");
797 return -E1000_ERR_PHY;
801 /* Enable CRS on TX. This must be set for half-duplex operation. */
802 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
803 DEBUGOUT("PHY Read Error\n");
804 return -E1000_ERR_PHY;
806 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
809 * MDI/MDI-X = 0 (default)
810 * 0 - Auto for all speeds
813 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
815 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
819 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
822 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
825 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
829 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
834 * disable_polarity_correction = 0 (default)
835 * Automatic Correction for Reversed Cable Polarity
839 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
840 if(hw->disable_polarity_correction == 1)
841 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
842 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
843 DEBUGOUT("PHY Write Error\n");
844 return -E1000_ERR_PHY;
847 /* Force TX_CLK in the Extended PHY Specific Control Register
850 if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
851 DEBUGOUT("PHY Read Error\n");
852 return -E1000_ERR_PHY;
854 phy_data |= M88E1000_EPSCR_TX_CLK_25;
856 if (hw->phy_revision < M88E1011_I_REV_4) {
857 /* Configure Master and Slave downshift values */
858 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
859 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
860 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
861 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
862 if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
864 DEBUGOUT("PHY Write Error\n");
865 return -E1000_ERR_PHY;
869 /* SW Reset the PHY so all changes take effect */
870 ret_val = em_phy_reset(hw);
872 DEBUGOUT("Error Resetting the PHY\n");
878 * autoneg = 1 (default)
879 * PHY will advertise value(s) parsed from
880 * autoneg_advertised and fc
882 * PHY will be set to 10H, 10F, 100H, or 100F
883 * depending on value parsed from forced_speed_duplex.
886 /* Is autoneg enabled? This is enabled by default or by software override.
887 * If so, call em_phy_setup_autoneg routine to parse the
888 * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
889 * user should have provided a speed/duplex override. If so, then call
890 * em_phy_force_speed_duplex to parse and set this up.
893 /* Perform some bounds checking on the hw->autoneg_advertised
894 * parameter. If this variable is zero, then set it to the default.
896 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
898 /* If autoneg_advertised is zero, we assume it was not defaulted
899 * by the calling code so we set to advertise full capability.
901 if(hw->autoneg_advertised == 0)
902 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
904 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
905 ret_val = em_phy_setup_autoneg(hw);
907 DEBUGOUT("Error Setting up Auto-Negotiation\n");
910 DEBUGOUT("Restarting Auto-Neg\n");
912 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
913 * the Auto Neg Restart bit in the PHY control register.
915 if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
916 DEBUGOUT("PHY Read Error\n");
917 return -E1000_ERR_PHY;
919 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
920 if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
921 DEBUGOUT("PHY Write Error\n");
922 return -E1000_ERR_PHY;
925 /* Does the user want to wait for Auto-Neg to complete here, or
926 * check at a later time (for example, callback routine).
928 if(hw->wait_autoneg_complete) {
929 ret_val = em_wait_autoneg(hw);
931 DEBUGOUT("Error while waiting for autoneg to complete\n");
935 hw->get_link_status = TRUE;
937 DEBUGOUT("Forcing speed and duplex\n");
938 ret_val = em_phy_force_speed_duplex(hw);
940 DEBUGOUT("Error Forcing Speed and Duplex\n");
945 /* Check link status. Wait up to 100 microseconds for link to become
948 for(i = 0; i < 10; i++) {
949 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
950 DEBUGOUT("PHY Read Error\n");
951 return -E1000_ERR_PHY;
953 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
954 DEBUGOUT("PHY Read Error\n");
955 return -E1000_ERR_PHY;
957 if(phy_data & MII_SR_LINK_STATUS) {
958 /* We have link, so we need to finish the config process:
959 * 1) Set up the MAC to the current PHY speed/duplex
960 * if we are on 82543. If we
961 * are on newer silicon, we only need to configure
962 * collision distance in the Transmit Control Register.
963 * 2) Set up flow control on the MAC to that established with
966 if(hw->mac_type >= em_82544) {
967 em_config_collision_dist(hw);
969 ret_val = em_config_mac_to_phy(hw);
971 DEBUGOUT("Error configuring MAC to PHY settings\n");
975 ret_val = em_config_fc_after_link_up(hw);
977 DEBUGOUT("Error Configuring Flow Control\n");
980 DEBUGOUT("Valid link established!!!\n");
986 DEBUGOUT("Unable to establish link!!!\n");
990 /******************************************************************************
991 * Configures PHY autoneg and flow control advertisement settings
993 * hw - Struct containing variables accessed by shared code
994 ******************************************************************************/
996 em_phy_setup_autoneg(struct em_hw *hw)
998 uint16_t mii_autoneg_adv_reg;
999 uint16_t mii_1000t_ctrl_reg;
1001 DEBUGFUNC("em_phy_setup_autoneg");
1003 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1004 if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
1005 DEBUGOUT("PHY Read Error\n");
1006 return -E1000_ERR_PHY;
1009 /* Read the MII 1000Base-T Control Register (Address 9). */
1010 if(em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
1011 DEBUGOUT("PHY Read Error\n");
1012 return -E1000_ERR_PHY;
1015 /* Need to parse both autoneg_advertised and fc and set up
1016 * the appropriate PHY registers. First we will parse for
1017 * autoneg_advertised software override. Since we can advertise
1018 * a plethora of combinations, we need to check each bit
1022 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1023 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1024 * the 1000Base-T Control Register (Address 9).
1026 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1027 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1029 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1031 /* Do we want to advertise 10 Mb Half Duplex? */
1032 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1033 DEBUGOUT("Advertise 10mb Half duplex\n");
1034 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1037 /* Do we want to advertise 10 Mb Full Duplex? */
1038 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1039 DEBUGOUT("Advertise 10mb Full duplex\n");
1040 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1043 /* Do we want to advertise 100 Mb Half Duplex? */
1044 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1045 DEBUGOUT("Advertise 100mb Half duplex\n");
1046 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1049 /* Do we want to advertise 100 Mb Full Duplex? */
1050 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1051 DEBUGOUT("Advertise 100mb Full duplex\n");
1052 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1055 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1056 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1057 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1060 /* Do we want to advertise 1000 Mb Full Duplex? */
1061 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1062 DEBUGOUT("Advertise 1000mb Full duplex\n");
1063 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1066 /* Check for a software override of the flow control settings, and
1067 * setup the PHY advertisement registers accordingly. If
1068 * auto-negotiation is enabled, then software will have to set the
1069 * "PAUSE" bits to the correct value in the Auto-Negotiation
1070 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1072 * The possible values of the "fc" parameter are:
1073 * 0: Flow control is completely disabled
1074 * 1: Rx flow control is enabled (we can receive pause frames
1075 * but not send pause frames).
1076 * 2: Tx flow control is enabled (we can send pause frames
1077 * but we do not support receiving pause frames).
1078 * 3: Both Rx and TX flow control (symmetric) are enabled.
1079 * other: No software override. The flow control configuration
1080 * in the EEPROM is used.
1083 case em_fc_none: /* 0 */
1084 /* Flow control (RX & TX) is completely disabled by a
1085 * software over-ride.
1087 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1089 case em_fc_rx_pause: /* 1 */
1090 /* RX Flow control is enabled, and TX Flow control is
1091 * disabled, by a software over-ride.
1093 /* Since there really isn't a way to advertise that we are
1094 * capable of RX Pause ONLY, we will advertise that we
1095 * support both symmetric and asymmetric RX PAUSE. Later
1096 * (in em_config_fc_after_link_up) we will disable the
1097 *hw's ability to send PAUSE frames.
1099 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1101 case em_fc_tx_pause: /* 2 */
1102 /* TX Flow control is enabled, and RX Flow control is
1103 * disabled, by a software over-ride.
1105 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1106 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1108 case em_fc_full: /* 3 */
1109 /* Flow control (both RX and TX) is enabled by a software
1112 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1115 DEBUGOUT("Flow control param set incorrectly\n");
1116 return -E1000_ERR_CONFIG;
1119 if(em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
1120 DEBUGOUT("PHY Write Error\n");
1121 return -E1000_ERR_PHY;
1124 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1126 if(em_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
1127 DEBUGOUT("PHY Write Error\n");
1128 return -E1000_ERR_PHY;
1133 /******************************************************************************
1134 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1136 * hw - Struct containing variables accessed by shared code
1137 ******************************************************************************/
1139 em_phy_force_speed_duplex(struct em_hw *hw)
1143 uint16_t mii_ctrl_reg;
1144 uint16_t mii_status_reg;
1148 DEBUGFUNC("em_phy_force_speed_duplex");
1150 /* Turn off Flow control if we are forcing speed and duplex. */
1151 hw->fc = em_fc_none;
1153 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1155 /* Read the Device Control Register. */
1156 ctrl = E1000_READ_REG(hw, CTRL);
1158 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1159 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1160 ctrl &= ~(DEVICE_SPEED_MASK);
1162 /* Clear the Auto Speed Detect Enable bit. */
1163 ctrl &= ~E1000_CTRL_ASDE;
1165 /* Read the MII Control Register. */
1166 if(em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg) < 0) {
1167 DEBUGOUT("PHY Read Error\n");
1168 return -E1000_ERR_PHY;
1171 /* We need to disable autoneg in order to force link and duplex. */
1173 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1175 /* Are we forcing Full or Half Duplex? */
1176 if(hw->forced_speed_duplex == em_100_full ||
1177 hw->forced_speed_duplex == em_10_full) {
1178 /* We want to force full duplex so we SET the full duplex bits in the
1179 * Device and MII Control Registers.
1181 ctrl |= E1000_CTRL_FD;
1182 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1183 DEBUGOUT("Full Duplex\n");
1185 /* We want to force half duplex so we CLEAR the full duplex bits in
1186 * the Device and MII Control Registers.
1188 ctrl &= ~E1000_CTRL_FD;
1189 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1190 DEBUGOUT("Half Duplex\n");
1193 /* Are we forcing 100Mbps??? */
1194 if(hw->forced_speed_duplex == em_100_full ||
1195 hw->forced_speed_duplex == em_100_half) {
1196 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1197 ctrl |= E1000_CTRL_SPD_100;
1198 mii_ctrl_reg |= MII_CR_SPEED_100;
1199 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1200 DEBUGOUT("Forcing 100mb ");
1202 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1203 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1204 mii_ctrl_reg |= MII_CR_SPEED_10;
1205 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1206 DEBUGOUT("Forcing 10mb ");
1209 em_config_collision_dist(hw);
1211 /* Write the configured values back to the Device Control Reg. */
1212 E1000_WRITE_REG(hw, CTRL, ctrl);
1214 if (hw->phy_type == em_phy_m88) {
1215 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
1216 DEBUGOUT("PHY Read Error\n");
1217 return -E1000_ERR_PHY;
1220 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1221 * forced whenever speed are duplex are forced.
1223 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1224 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
1225 DEBUGOUT("PHY Write Error\n");
1226 return -E1000_ERR_PHY;
1228 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1230 /* Need to reset the PHY or these changes will be ignored */
1231 mii_ctrl_reg |= MII_CR_RESET;
1233 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1234 * forced whenever speed or duplex are forced.
1236 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data) < 0) {
1237 DEBUGOUT("PHY Read Error\n");
1238 return -E1000_ERR_PHY;
1241 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1242 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1244 if(em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data) < 0) {
1245 DEBUGOUT("PHY Write Error\n");
1246 return -E1000_ERR_PHY;
1250 /* Write back the modified PHY MII control register. */
1251 if(em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
1252 DEBUGOUT("PHY Write Error\n");
1253 return -E1000_ERR_PHY;
1257 /* The wait_autoneg_complete flag may be a little misleading here.
1258 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1259 * But we do want to delay for a period while forcing only so we
1260 * don't generate false No Link messages. So we will wait here
1261 * only if the user has set wait_autoneg_complete to 1, which is
1264 if(hw->wait_autoneg_complete) {
1265 /* We will wait for autoneg to complete. */
1266 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1269 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1270 for(i = PHY_FORCE_TIME; i > 0; i--) {
1271 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1274 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1275 DEBUGOUT("PHY Read Error\n");
1276 return -E1000_ERR_PHY;
1278 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1279 DEBUGOUT("PHY Read Error\n");
1280 return -E1000_ERR_PHY;
1282 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1285 if(i == 0) { /* We didn't get link */
1286 /* Reset the DSP and wait again for link. */
1288 ret_val = em_phy_reset_dsp(hw);
1290 DEBUGOUT("Error Resetting PHY DSP\n");
1294 /* This loop will early-out if the link condition has been met. */
1295 for(i = PHY_FORCE_TIME; i > 0; i--) {
1296 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1298 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1301 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1302 DEBUGOUT("PHY Read Error\n");
1303 return -E1000_ERR_PHY;
1305 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1306 DEBUGOUT("PHY Read Error\n");
1307 return -E1000_ERR_PHY;
1312 if (hw->phy_type == em_phy_m88) {
1313 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1314 * Extended PHY Specific Control Register to 25MHz clock. This value
1315 * defaults back to a 2.5MHz clock when the PHY is reset.
1317 if(em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
1318 DEBUGOUT("PHY Read Error\n");
1319 return -E1000_ERR_PHY;
1321 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1322 if(em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
1323 DEBUGOUT("PHY Write Error\n");
1324 return -E1000_ERR_PHY;
1327 /* In addition, because of the s/w reset above, we need to enable CRS on
1328 * TX. This must be set for both full and half duplex operation.
1330 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
1331 DEBUGOUT("PHY Read Error\n");
1332 return -E1000_ERR_PHY;
1334 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1335 if(em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
1336 DEBUGOUT("PHY Write Error\n");
1337 return -E1000_ERR_PHY;
1343 /******************************************************************************
1344 * Sets the collision distance in the Transmit Control register
1346 * hw - Struct containing variables accessed by shared code
1348 * Link should have been established previously. Reads the speed and duplex
1349 * information from the Device Status register.
1350 ******************************************************************************/
1352 em_config_collision_dist(struct em_hw *hw)
1356 DEBUGFUNC("em_config_collision_dist");
1358 tctl = E1000_READ_REG(hw, TCTL);
1360 tctl &= ~E1000_TCTL_COLD;
1361 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1363 E1000_WRITE_REG(hw, TCTL, tctl);
1364 E1000_WRITE_FLUSH(hw);
1367 /******************************************************************************
1368 * Sets MAC speed and duplex settings to reflect the those in the PHY
1370 * hw - Struct containing variables accessed by shared code
1371 * mii_reg - data to write to the MII control register
1373 * The contents of the PHY register containing the needed information need to
1375 ******************************************************************************/
1377 em_config_mac_to_phy(struct em_hw *hw)
1382 DEBUGFUNC("em_config_mac_to_phy");
1384 /* Read the Device Control Register and set the bits to Force Speed
1387 ctrl = E1000_READ_REG(hw, CTRL);
1388 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1389 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1391 /* Set up duplex in the Device Control and Transmit Control
1392 * registers depending on negotiated values.
1394 if (hw->phy_type == em_phy_igp) {
1395 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0) {
1396 DEBUGOUT("PHY Read Error\n");
1397 return -E1000_ERR_PHY;
1399 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1400 else ctrl &= ~E1000_CTRL_FD;
1402 em_config_collision_dist(hw);
1404 /* Set up speed in the Device Control register depending on
1405 * negotiated values.
1407 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1408 IGP01E1000_PSSR_SPEED_1000MBPS)
1409 ctrl |= E1000_CTRL_SPD_1000;
1410 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1411 IGP01E1000_PSSR_SPEED_100MBPS)
1412 ctrl |= E1000_CTRL_SPD_100;
1414 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
1415 DEBUGOUT("PHY Read Error\n");
1416 return -E1000_ERR_PHY;
1418 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1419 else ctrl &= ~E1000_CTRL_FD;
1421 em_config_collision_dist(hw);
1423 /* Set up speed in the Device Control register depending on
1424 * negotiated values.
1426 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1427 ctrl |= E1000_CTRL_SPD_1000;
1428 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1429 ctrl |= E1000_CTRL_SPD_100;
1431 /* Write the configured values back to the Device Control Reg. */
1432 E1000_WRITE_REG(hw, CTRL, ctrl);
1436 /******************************************************************************
1437 * Forces the MAC's flow control settings.
1439 * hw - Struct containing variables accessed by shared code
1441 * Sets the TFCE and RFCE bits in the device control register to reflect
1442 * the adapter settings. TFCE and RFCE need to be explicitly set by
1443 * software when a Copper PHY is used because autonegotiation is managed
1444 * by the PHY rather than the MAC. Software must also configure these
1445 * bits when link is forced on a fiber connection.
1446 *****************************************************************************/
1448 em_force_mac_fc(struct em_hw *hw)
1452 DEBUGFUNC("em_force_mac_fc");
1454 /* Get the current configuration of the Device Control Register */
1455 ctrl = E1000_READ_REG(hw, CTRL);
1457 /* Because we didn't get link via the internal auto-negotiation
1458 * mechanism (we either forced link or we got link via PHY
1459 * auto-neg), we have to manually enable/disable transmit an
1460 * receive flow control.
1462 * The "Case" statement below enables/disable flow control
1463 * according to the "hw->fc" parameter.
1465 * The possible values of the "fc" parameter are:
1466 * 0: Flow control is completely disabled
1467 * 1: Rx flow control is enabled (we can receive pause
1468 * frames but not send pause frames).
1469 * 2: Tx flow control is enabled (we can send pause frames
1470 * frames but we do not receive pause frames).
1471 * 3: Both Rx and TX flow control (symmetric) is enabled.
1472 * other: No other values should be possible at this point.
1477 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1479 case em_fc_rx_pause:
1480 ctrl &= (~E1000_CTRL_TFCE);
1481 ctrl |= E1000_CTRL_RFCE;
1483 case em_fc_tx_pause:
1484 ctrl &= (~E1000_CTRL_RFCE);
1485 ctrl |= E1000_CTRL_TFCE;
1488 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1491 DEBUGOUT("Flow control param set incorrectly\n");
1492 return -E1000_ERR_CONFIG;
1495 /* Disable TX Flow Control for 82542 (rev 2.0) */
1496 if(hw->mac_type == em_82542_rev2_0)
1497 ctrl &= (~E1000_CTRL_TFCE);
1499 E1000_WRITE_REG(hw, CTRL, ctrl);
1503 /******************************************************************************
1504 * Configures flow control settings after link is established
1506 * hw - Struct containing variables accessed by shared code
1508 * Should be called immediately after a valid link has been established.
1509 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1510 * and autonegotiation is enabled, the MAC flow control settings will be set
1511 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1512 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1513 *****************************************************************************/
1515 em_config_fc_after_link_up(struct em_hw *hw)
1518 uint16_t mii_status_reg;
1519 uint16_t mii_nway_adv_reg;
1520 uint16_t mii_nway_lp_ability_reg;
1524 DEBUGFUNC("em_config_fc_after_link_up");
1526 /* Check for the case where we have fiber media and auto-neg failed
1527 * so we had to force link. In this case, we need to force the
1528 * configuration of the MAC to match the "fc" parameter.
1530 if(((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) ||
1531 ((hw->media_type == em_media_type_copper) && (!hw->autoneg))) {
1532 ret_val = em_force_mac_fc(hw);
1534 DEBUGOUT("Error forcing flow control settings\n");
1539 /* Check for the case where we have copper media and auto-neg is
1540 * enabled. In this case, we need to check and see if Auto-Neg
1541 * has completed, and if so, how the PHY and link partner has
1542 * flow control configured.
1544 if((hw->media_type == em_media_type_copper) && hw->autoneg) {
1545 /* Read the MII Status Register and check to see if AutoNeg
1546 * has completed. We read this twice because this reg has
1547 * some "sticky" (latched) bits.
1549 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1550 DEBUGOUT("PHY Read Error \n");
1551 return -E1000_ERR_PHY;
1553 if(em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
1554 DEBUGOUT("PHY Read Error \n");
1555 return -E1000_ERR_PHY;
1558 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1559 /* The AutoNeg process has completed, so we now need to
1560 * read both the Auto Negotiation Advertisement Register
1561 * (Address 4) and the Auto_Negotiation Base Page Ability
1562 * Register (Address 5) to determine how flow control was
1565 if(em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
1566 DEBUGOUT("PHY Read Error\n");
1567 return -E1000_ERR_PHY;
1569 if(em_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg) < 0) {
1570 DEBUGOUT("PHY Read Error\n");
1571 return -E1000_ERR_PHY;
1574 /* Two bits in the Auto Negotiation Advertisement Register
1575 * (Address 4) and two bits in the Auto Negotiation Base
1576 * Page Ability Register (Address 5) determine flow control
1577 * for both the PHY and the link partner. The following
1578 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1579 * 1999, describes these PAUSE resolution bits and how flow
1580 * control is determined based upon these settings.
1581 * NOTE: DC = Don't Care
1583 * LOCAL DEVICE | LINK PARTNER
1584 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1585 *-------|---------|-------|---------|--------------------
1586 * 0 | 0 | DC | DC | em_fc_none
1587 * 0 | 1 | 0 | DC | em_fc_none
1588 * 0 | 1 | 1 | 0 | em_fc_none
1589 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1590 * 1 | 0 | 0 | DC | em_fc_none
1591 * 1 | DC | 1 | DC | em_fc_full
1592 * 1 | 1 | 0 | 0 | em_fc_none
1593 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1596 /* Are both PAUSE bits set to 1? If so, this implies
1597 * Symmetric Flow Control is enabled at both ends. The
1598 * ASM_DIR bits are irrelevant per the spec.
1600 * For Symmetric Flow Control:
1602 * LOCAL DEVICE | LINK PARTNER
1603 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1604 *-------|---------|-------|---------|--------------------
1605 * 1 | DC | 1 | DC | em_fc_full
1608 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1609 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1610 /* Now we need to check if the user selected RX ONLY
1611 * of pause frames. In this case, we had to advertise
1612 * FULL flow control because we could not advertise RX
1613 * ONLY. Hence, we must now check to see if we need to
1614 * turn OFF the TRANSMISSION of PAUSE frames.
1616 if(hw->original_fc == em_fc_full) {
1617 hw->fc = em_fc_full;
1618 DEBUGOUT("Flow Control = FULL.\r\n");
1620 hw->fc = em_fc_rx_pause;
1621 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1624 /* For receiving PAUSE frames ONLY.
1626 * LOCAL DEVICE | LINK PARTNER
1627 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1628 *-------|---------|-------|---------|--------------------
1629 * 0 | 1 | 1 | 1 | em_fc_tx_pause
1632 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1633 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1634 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1635 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1636 hw->fc = em_fc_tx_pause;
1637 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1639 /* For transmitting PAUSE frames ONLY.
1641 * LOCAL DEVICE | LINK PARTNER
1642 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1643 *-------|---------|-------|---------|--------------------
1644 * 1 | 1 | 0 | 1 | em_fc_rx_pause
1647 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1648 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1649 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1650 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1651 hw->fc = em_fc_rx_pause;
1652 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1654 /* Per the IEEE spec, at this point flow control should be
1655 * disabled. However, we want to consider that we could
1656 * be connected to a legacy switch that doesn't advertise
1657 * desired flow control, but can be forced on the link
1658 * partner. So if we advertised no flow control, that is
1659 * what we will resolve to. If we advertised some kind of
1660 * receive capability (Rx Pause Only or Full Flow Control)
1661 * and the link partner advertised none, we will configure
1662 * ourselves to enable Rx Flow Control only. We can do
1663 * this safely for two reasons: If the link partner really
1664 * didn't want flow control enabled, and we enable Rx, no
1665 * harm done since we won't be receiving any PAUSE frames
1666 * anyway. If the intent on the link partner was to have
1667 * flow control enabled, then by us enabling RX only, we
1668 * can at least receive pause frames and process them.
1669 * This is a good idea because in most cases, since we are
1670 * predominantly a server NIC, more times than not we will
1671 * be asked to delay transmission of packets than asking
1672 * our link partner to pause transmission of frames.
1674 else if(hw->original_fc == em_fc_none ||
1675 hw->original_fc == em_fc_tx_pause) {
1676 hw->fc = em_fc_none;
1677 DEBUGOUT("Flow Control = NONE.\r\n");
1679 hw->fc = em_fc_rx_pause;
1680 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1683 /* Now we need to do one last check... If we auto-
1684 * negotiated to HALF DUPLEX, flow control should not be
1685 * enabled per IEEE 802.3 spec.
1687 em_get_speed_and_duplex(hw, &speed, &duplex);
1689 if(duplex == HALF_DUPLEX)
1690 hw->fc = em_fc_none;
1692 /* Now we call a subroutine to actually force the MAC
1693 * controller to use the correct flow control settings.
1695 ret_val = em_force_mac_fc(hw);
1697 DEBUGOUT("Error forcing flow control settings\n");
1701 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1707 /******************************************************************************
1708 * Checks to see if the link status of the hardware has changed.
1710 * hw - Struct containing variables accessed by shared code
1712 * Called by any function that needs to check the link status of the adapter.
1713 *****************************************************************************/
1715 em_check_for_link(struct em_hw *hw)
1724 uint16_t lp_capability;
1726 DEBUGFUNC("em_check_for_link");
1728 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1729 * set when the optics detect a signal. On older adapters, it will be
1730 * cleared when there is a signal
1732 if(hw->mac_type > em_82544) signal = E1000_CTRL_SWDPIN1;
1735 ctrl = E1000_READ_REG(hw, CTRL);
1736 status = E1000_READ_REG(hw, STATUS);
1737 rxcw = E1000_READ_REG(hw, RXCW);
1739 /* If we have a copper PHY then we only want to go out to the PHY
1740 * registers to see if Auto-Neg has completed and/or if our link
1741 * status has changed. The get_link_status flag will be set if we
1742 * receive a Link Status Change interrupt or we have Rx Sequence
1745 if((hw->media_type == em_media_type_copper) && hw->get_link_status) {
1746 /* First we want to see if the MII Status Register reports
1747 * link. If so, then we want to get the current speed/duplex
1749 * Read the register twice since the link bit is sticky.
1751 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1752 DEBUGOUT("PHY Read Error\n");
1753 return -E1000_ERR_PHY;
1755 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1756 DEBUGOUT("PHY Read Error\n");
1757 return -E1000_ERR_PHY;
1760 if(phy_data & MII_SR_LINK_STATUS) {
1761 hw->get_link_status = FALSE;
1762 /* Check if there was DownShift, must be checked immediately after
1764 em_check_downshift(hw);
1767 /* No link detected */
1771 /* If we are forcing speed/duplex, then we simply return since
1772 * we have already determined whether we have link or not.
1774 if(!hw->autoneg) return -E1000_ERR_CONFIG;
1776 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
1777 * have Si on board that is 82544 or newer, Auto
1778 * Speed Detection takes care of MAC speed/duplex
1779 * configuration. So we only need to configure Collision
1780 * Distance in the MAC. Otherwise, we need to force
1781 * speed/duplex on the MAC to the current PHY speed/duplex
1784 if(hw->mac_type >= em_82544)
1785 em_config_collision_dist(hw);
1787 ret_val = em_config_mac_to_phy(hw);
1789 DEBUGOUT("Error configuring MAC to PHY settings\n");
1794 /* Configure Flow Control now that Auto-Neg has completed. First, we
1795 * need to restore the desired flow control settings because we may
1796 * have had to re-autoneg with a different link partner.
1798 ret_val = em_config_fc_after_link_up(hw);
1800 DEBUGOUT("Error configuring flow control\n");
1804 /* At this point we know that we are on copper and we have
1805 * auto-negotiated link. These are conditions for checking the link
1806 * parter capability register. We use the link partner capability to
1807 * determine if TBI Compatibility needs to be turned on or off. If
1808 * the link partner advertises any speed in addition to Gigabit, then
1809 * we assume that they are GMII-based, and TBI compatibility is not
1810 * needed. If no other speeds are advertised, we assume the link
1811 * partner is TBI-based, and we turn on TBI Compatibility.
1813 if(hw->tbi_compatibility_en) {
1814 if(em_read_phy_reg(hw, PHY_LP_ABILITY, &lp_capability) < 0) {
1815 DEBUGOUT("PHY Read Error\n");
1816 return -E1000_ERR_PHY;
1818 if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
1819 NWAY_LPAR_10T_FD_CAPS |
1820 NWAY_LPAR_100TX_HD_CAPS |
1821 NWAY_LPAR_100TX_FD_CAPS |
1822 NWAY_LPAR_100T4_CAPS)) {
1823 /* If our link partner advertises anything in addition to
1824 * gigabit, we do not need to enable TBI compatibility.
1826 if(hw->tbi_compatibility_on) {
1827 /* If we previously were in the mode, turn it off. */
1828 rctl = E1000_READ_REG(hw, RCTL);
1829 rctl &= ~E1000_RCTL_SBP;
1830 E1000_WRITE_REG(hw, RCTL, rctl);
1831 hw->tbi_compatibility_on = FALSE;
1834 /* If TBI compatibility is was previously off, turn it on. For
1835 * compatibility with a TBI link partner, we will store bad
1836 * packets. Some frames have an additional byte on the end and
1837 * will look like CRC errors to to the hardware.
1839 if(!hw->tbi_compatibility_on) {
1840 hw->tbi_compatibility_on = TRUE;
1841 rctl = E1000_READ_REG(hw, RCTL);
1842 rctl |= E1000_RCTL_SBP;
1843 E1000_WRITE_REG(hw, RCTL, rctl);
1848 /* If we don't have link (auto-negotiation failed or link partner cannot
1849 * auto-negotiate), the cable is plugged in (we have signal), and our
1850 * link partner is not trying to auto-negotiate with us (we are receiving
1851 * idles or data), we need to force link up. We also need to give
1852 * auto-negotiation time to complete, in case the cable was just plugged
1853 * in. The autoneg_failed flag does this.
1855 else if((hw->media_type == em_media_type_fiber) &&
1856 (!(status & E1000_STATUS_LU)) &&
1857 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
1858 (!(rxcw & E1000_RXCW_C))) {
1859 if(hw->autoneg_failed == 0) {
1860 hw->autoneg_failed = 1;
1863 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
1865 /* Disable auto-negotiation in the TXCW register */
1866 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
1868 /* Force link-up and also force full-duplex. */
1869 ctrl = E1000_READ_REG(hw, CTRL);
1870 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1871 E1000_WRITE_REG(hw, CTRL, ctrl);
1873 /* Configure Flow Control after forcing link up. */
1874 ret_val = em_config_fc_after_link_up(hw);
1876 DEBUGOUT("Error configuring flow control\n");
1880 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
1881 * auto-negotiation in the TXCW register and disable forced link in the
1882 * Device Control register in an attempt to auto-negotiate with our link
1885 else if((hw->media_type == em_media_type_fiber) &&
1886 (ctrl & E1000_CTRL_SLU) &&
1887 (rxcw & E1000_RXCW_C)) {
1888 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
1889 E1000_WRITE_REG(hw, TXCW, hw->txcw);
1890 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
1895 /******************************************************************************
1896 * Detects the current speed and duplex settings of the hardware.
1898 * hw - Struct containing variables accessed by shared code
1899 * speed - Speed of the connection
1900 * duplex - Duplex setting of the connection
1901 *****************************************************************************/
1903 em_get_speed_and_duplex(struct em_hw *hw,
1909 DEBUGFUNC("em_get_speed_and_duplex");
1911 if(hw->mac_type >= em_82543) {
1912 status = E1000_READ_REG(hw, STATUS);
1913 if(status & E1000_STATUS_SPEED_1000) {
1914 *speed = SPEED_1000;
1915 DEBUGOUT("1000 Mbs, ");
1916 } else if(status & E1000_STATUS_SPEED_100) {
1918 DEBUGOUT("100 Mbs, ");
1921 DEBUGOUT("10 Mbs, ");
1924 if(status & E1000_STATUS_FD) {
1925 *duplex = FULL_DUPLEX;
1926 DEBUGOUT("Full Duplex\r\n");
1928 *duplex = HALF_DUPLEX;
1929 DEBUGOUT(" Half Duplex\r\n");
1932 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
1933 *speed = SPEED_1000;
1934 *duplex = FULL_DUPLEX;
1938 /******************************************************************************
1939 * Blocks until autoneg completes or times out (~4.5 seconds)
1941 * hw - Struct containing variables accessed by shared code
1942 ******************************************************************************/
1944 em_wait_autoneg(struct em_hw *hw)
1949 DEBUGFUNC("em_wait_autoneg");
1950 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
1952 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1953 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
1954 /* Read the MII Status Register and wait for Auto-Neg
1955 * Complete bit to be set.
1957 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1958 DEBUGOUT("PHY Read Error\n");
1959 return -E1000_ERR_PHY;
1961 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
1962 DEBUGOUT("PHY Read Error\n");
1963 return -E1000_ERR_PHY;
1965 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
1973 /******************************************************************************
1974 * Raises the Management Data Clock
1976 * hw - Struct containing variables accessed by shared code
1977 * ctrl - Device control register's current value
1978 ******************************************************************************/
1980 em_raise_mdi_clk(struct em_hw *hw,
1983 /* Raise the clock input to the Management Data Clock (by setting the MDC
1984 * bit), and then delay 2 microseconds.
1986 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
1987 E1000_WRITE_FLUSH(hw);
1991 /******************************************************************************
1992 * Lowers the Management Data Clock
1994 * hw - Struct containing variables accessed by shared code
1995 * ctrl - Device control register's current value
1996 ******************************************************************************/
1998 em_lower_mdi_clk(struct em_hw *hw,
2001 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2002 * bit), and then delay 2 microseconds.
2004 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2005 E1000_WRITE_FLUSH(hw);
2009 /******************************************************************************
2010 * Shifts data bits out to the PHY
2012 * hw - Struct containing variables accessed by shared code
2013 * data - Data to send out to the PHY
2014 * count - Number of bits to shift out
2016 * Bits are shifted out in MSB to LSB order.
2017 ******************************************************************************/
2019 em_shift_out_mdi_bits(struct em_hw *hw,
2026 /* We need to shift "count" number of bits out to the PHY. So, the value
2027 * in the "data" parameter will be shifted out to the PHY one bit at a
2028 * time. In order to do this, "data" must be broken down into bits.
2031 mask <<= (count - 1);
2033 ctrl = E1000_READ_REG(hw, CTRL);
2035 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2036 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2039 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2040 * then raising and lowering the Management Data Clock. A "0" is
2041 * shifted out to the PHY by setting the MDIO bit to "0" and then
2042 * raising and lowering the clock.
2044 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2045 else ctrl &= ~E1000_CTRL_MDIO;
2047 E1000_WRITE_REG(hw, CTRL, ctrl);
2048 E1000_WRITE_FLUSH(hw);
2052 em_raise_mdi_clk(hw, &ctrl);
2053 em_lower_mdi_clk(hw, &ctrl);
2059 /******************************************************************************
2060 * Shifts data bits in from the PHY
2062 * hw - Struct containing variables accessed by shared code
2064 * Bits are shifted in in MSB to LSB order.
2065 ******************************************************************************/
2067 em_shift_in_mdi_bits(struct em_hw *hw)
2073 /* In order to read a register from the PHY, we need to shift in a total
2074 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2075 * to avoid contention on the MDIO pin when a read operation is performed.
2076 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2077 * by raising the input to the Management Data Clock (setting the MDC bit),
2078 * and then reading the value of the MDIO bit.
2080 ctrl = E1000_READ_REG(hw, CTRL);
2082 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2083 ctrl &= ~E1000_CTRL_MDIO_DIR;
2084 ctrl &= ~E1000_CTRL_MDIO;
2086 E1000_WRITE_REG(hw, CTRL, ctrl);
2087 E1000_WRITE_FLUSH(hw);
2089 /* Raise and Lower the clock before reading in the data. This accounts for
2090 * the turnaround bits. The first clock occurred when we clocked out the
2091 * last bit of the Register Address.
2093 em_raise_mdi_clk(hw, &ctrl);
2094 em_lower_mdi_clk(hw, &ctrl);
2096 for(data = 0, i = 0; i < 16; i++) {
2098 em_raise_mdi_clk(hw, &ctrl);
2099 ctrl = E1000_READ_REG(hw, CTRL);
2100 /* Check to see if we shifted in a "1". */
2101 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2102 em_lower_mdi_clk(hw, &ctrl);
2105 em_raise_mdi_clk(hw, &ctrl);
2106 em_lower_mdi_clk(hw, &ctrl);
2111 /*****************************************************************************
2112 * Reads the value from a PHY register
2114 * hw - Struct containing variables accessed by shared code
2115 * reg_addr - address of the PHY register to read
2116 ******************************************************************************/
2118 em_read_phy_reg(struct em_hw *hw,
2124 const uint32_t phy_addr = 1;
2126 DEBUGFUNC("em_read_phy_reg");
2128 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2129 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2130 return -E1000_ERR_PARAM;
2133 if(hw->mac_type > em_82543) {
2134 /* Set up Op-code, Phy Address, and register address in the MDI
2135 * Control register. The MAC will take care of interfacing with the
2136 * PHY to retrieve the desired data.
2138 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2139 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2140 (E1000_MDIC_OP_READ));
2142 E1000_WRITE_REG(hw, MDIC, mdic);
2144 /* Poll the ready bit to see if the MDI read completed */
2145 for(i = 0; i < 64; i++) {
2147 mdic = E1000_READ_REG(hw, MDIC);
2148 if(mdic & E1000_MDIC_READY) break;
2150 if(!(mdic & E1000_MDIC_READY)) {
2151 DEBUGOUT("MDI Read did not complete\n");
2152 return -E1000_ERR_PHY;
2154 if(mdic & E1000_MDIC_ERROR) {
2155 DEBUGOUT("MDI Error\n");
2156 return -E1000_ERR_PHY;
2158 *phy_data = (uint16_t) mdic;
2160 /* We must first send a preamble through the MDIO pin to signal the
2161 * beginning of an MII instruction. This is done by sending 32
2162 * consecutive "1" bits.
2164 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2166 /* Now combine the next few fields that are required for a read
2167 * operation. We use this method instead of calling the
2168 * em_shift_out_mdi_bits routine five different times. The format of
2169 * a MII read instruction consists of a shift out of 14 bits and is
2170 * defined as follows:
2171 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2172 * followed by a shift in of 18 bits. This first two bits shifted in
2173 * are TurnAround bits used to avoid contention on the MDIO pin when a
2174 * READ operation is performed. These two bits are thrown away
2175 * followed by a shift in of 16 bits which contains the desired data.
2177 mdic = ((reg_addr) | (phy_addr << 5) |
2178 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2180 em_shift_out_mdi_bits(hw, mdic, 14);
2182 /* Now that we've shifted out the read command to the MII, we need to
2183 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2186 *phy_data = em_shift_in_mdi_bits(hw);
2191 /******************************************************************************
2192 * Writes a value to a PHY register
2194 * hw - Struct containing variables accessed by shared code
2195 * reg_addr - address of the PHY register to write
2196 * data - data to write to the PHY
2197 ******************************************************************************/
2199 em_write_phy_reg(struct em_hw *hw,
2205 const uint32_t phy_addr = 1;
2207 DEBUGFUNC("em_write_phy_reg");
2209 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2210 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2211 return -E1000_ERR_PARAM;
2214 if(hw->mac_type > em_82543) {
2215 /* Set up Op-code, Phy Address, register address, and data intended
2216 * for the PHY register in the MDI Control register. The MAC will take
2217 * care of interfacing with the PHY to send the desired data.
2219 mdic = (((uint32_t) phy_data) |
2220 (reg_addr << E1000_MDIC_REG_SHIFT) |
2221 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2222 (E1000_MDIC_OP_WRITE));
2224 E1000_WRITE_REG(hw, MDIC, mdic);
2226 /* Poll the ready bit to see if the MDI read completed */
2227 for(i = 0; i < 64; i++) {
2229 mdic = E1000_READ_REG(hw, MDIC);
2230 if(mdic & E1000_MDIC_READY) break;
2232 if(!(mdic & E1000_MDIC_READY)) {
2233 DEBUGOUT("MDI Write did not complete\n");
2234 return -E1000_ERR_PHY;
2237 /* We'll need to use the SW defined pins to shift the write command
2238 * out to the PHY. We first send a preamble to the PHY to signal the
2239 * beginning of the MII instruction. This is done by sending 32
2240 * consecutive "1" bits.
2242 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2244 /* Now combine the remaining required fields that will indicate a
2245 * write operation. We use this method instead of calling the
2246 * em_shift_out_mdi_bits routine for each field in the command. The
2247 * format of a MII write instruction is as follows:
2248 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2250 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2251 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2253 mdic |= (uint32_t) phy_data;
2255 em_shift_out_mdi_bits(hw, mdic, 32);
2261 /******************************************************************************
2262 * Returns the PHY to the power-on reset state
2264 * hw - Struct containing variables accessed by shared code
2265 ******************************************************************************/
2267 em_phy_hw_reset(struct em_hw *hw)
2269 uint32_t ctrl, ctrl_ext;
2272 DEBUGFUNC("em_phy_hw_reset");
2274 DEBUGOUT("Resetting Phy...\n");
2276 if(hw->mac_type > em_82543) {
2277 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2278 * bit. Then, take it out of reset.
2280 ctrl = E1000_READ_REG(hw, CTRL);
2281 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2282 E1000_WRITE_FLUSH(hw);
2284 E1000_WRITE_REG(hw, CTRL, ctrl);
2285 E1000_WRITE_FLUSH(hw);
2287 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2288 * bit to put the PHY into reset. Then, take it out of reset.
2290 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2291 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2292 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2293 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2294 E1000_WRITE_FLUSH(hw);
2296 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2297 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2298 E1000_WRITE_FLUSH(hw);
2302 if((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
2303 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0000) < 0) {
2304 DEBUGOUT("PHY Write Error\n");
2308 /* Configure activity LED after PHY reset */
2309 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2310 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2311 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2312 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2316 /******************************************************************************
2319 * hw - Struct containing variables accessed by shared code
2321 * Sets bit 15 of the MII Control regiser
2322 ******************************************************************************/
2324 em_phy_reset(struct em_hw *hw)
2328 DEBUGFUNC("em_phy_reset");
2330 if(em_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
2331 DEBUGOUT("PHY Read Error\n");
2332 return -E1000_ERR_PHY;
2334 phy_data |= MII_CR_RESET;
2335 if(em_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
2336 DEBUGOUT("PHY Write Error\n");
2337 return -E1000_ERR_PHY;
2340 if (hw->phy_type == em_phy_igp) {
2341 em_phy_init_script(hw);
2346 /******************************************************************************
2347 * Probes the expected PHY address for known PHY IDs
2349 * hw - Struct containing variables accessed by shared code
2350 ******************************************************************************/
2352 em_detect_gig_phy(struct em_hw *hw)
2354 uint16_t phy_id_high, phy_id_low;
2355 boolean_t match = FALSE;
2356 int32_t phy_init_status;
2358 DEBUGFUNC("em_detect_gig_phy");
2360 /* Read the PHY ID Registers to identify which PHY is onboard. */
2361 if(em_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
2362 DEBUGOUT("PHY Read Error\n");
2363 return -E1000_ERR_PHY;
2365 hw->phy_id = (uint32_t) (phy_id_high << 16);
2367 if(em_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
2368 DEBUGOUT("PHY Read Error\n");
2369 return -E1000_ERR_PHY;
2371 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2372 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2374 switch(hw->mac_type) {
2376 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2379 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2384 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2388 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2391 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2392 return -E1000_ERR_CONFIG;
2394 phy_init_status = em_set_phy_type(hw);
2396 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2397 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2400 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2401 return -E1000_ERR_PHY;
2404 /******************************************************************************
2405 * Resets the PHY's DSP
2407 * hw - Struct containing variables accessed by shared code
2408 ******************************************************************************/
2410 em_phy_reset_dsp(struct em_hw *hw)
2412 int32_t ret_val = -E1000_ERR_PHY;
2413 DEBUGFUNC("em_phy_reset_dsp");
2416 if(em_write_phy_reg(hw, 29, 0x001d) < 0) break;
2417 if(em_write_phy_reg(hw, 30, 0x00c1) < 0) break;
2418 if(em_write_phy_reg(hw, 30, 0x0000) < 0) break;
2422 if(ret_val < 0) DEBUGOUT("PHY Write Error\n");
2426 /******************************************************************************
2427 * Get PHY information from various PHY registers for igp PHY only.
2429 * hw - Struct containing variables accessed by shared code
2430 * phy_info - PHY information structure
2431 ******************************************************************************/
2433 em_phy_igp_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
2435 uint16_t phy_data, polarity, min_length, max_length, average;
2437 DEBUGFUNC("em_phy_igp_get_info");
2439 /* The downshift status is checked only once, after link is established,
2440 * and it stored in the hw->speed_downgraded parameter. */
2441 phy_info->downshift = hw->speed_downgraded;
2443 /* IGP01E1000 does not need to support it. */
2444 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_normal;
2446 /* IGP01E1000 always correct polarity reversal */
2447 phy_info->polarity_correction = em_polarity_reversal_enabled;
2449 /* Check polarity status */
2450 if(em_check_polarity(hw, &polarity) < 0)
2451 return -E1000_ERR_PHY;
2453 phy_info->cable_polarity = polarity;
2455 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0)
2456 return -E1000_ERR_PHY;
2458 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
2459 IGP01E1000_PSSR_MDIX_SHIFT;
2461 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2462 IGP01E1000_PSSR_SPEED_1000MBPS) {
2463 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
2464 if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0)
2465 return -E1000_ERR_PHY;
2467 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2468 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2469 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2470 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2472 /* Get cable length */
2473 if(em_get_cable_length(hw, &min_length, &max_length) < 0)
2474 return -E1000_ERR_PHY;
2476 /* transalte to old method */
2477 average = (max_length + min_length) / 2;
2479 if(average <= em_igp_cable_length_50)
2480 phy_info->cable_length = em_cable_length_50;
2481 else if(average <= em_igp_cable_length_80)
2482 phy_info->cable_length = em_cable_length_50_80;
2483 else if(average <= em_igp_cable_length_110)
2484 phy_info->cable_length = em_cable_length_80_110;
2485 else if(average <= em_igp_cable_length_140)
2486 phy_info->cable_length = em_cable_length_110_140;
2488 phy_info->cable_length = em_cable_length_140;
2491 return E1000_SUCCESS;
2494 /******************************************************************************
2495 * Get PHY information from various PHY registers fot m88 PHY only.
2497 * hw - Struct containing variables accessed by shared code
2498 * phy_info - PHY information structure
2499 ******************************************************************************/
2501 em_phy_m88_get_info(struct em_hw *hw, struct em_phy_info *phy_info)
2503 uint16_t phy_data, polarity;
2505 DEBUGFUNC("em_phy_m88_get_info");
2507 /* The downshift status is checked only once, after link is established,
2508 * and it stored in the hw->speed_downgraded parameter. */
2509 phy_info->downshift = hw->speed_downgraded;
2511 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0)
2512 return -E1000_ERR_PHY;
2514 phy_info->extended_10bt_distance =
2515 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
2516 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
2517 phy_info->polarity_correction =
2518 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
2519 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
2521 /* Check polarity status */
2522 if(em_check_polarity(hw, &polarity) < 0)
2523 return -E1000_ERR_PHY;
2525 phy_info->cable_polarity = polarity;
2527 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
2528 return -E1000_ERR_PHY;
2530 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
2531 M88E1000_PSSR_MDIX_SHIFT;
2533 if(phy_data & M88E1000_PSSR_1000MBS) {
2534 /* Cable Length Estimation and Local/Remote Receiver Informatoion
2535 * are only valid at 1000 Mbps
2537 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2538 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2540 if(em_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0)
2541 return -E1000_ERR_PHY;
2543 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
2544 SR_1000T_LOCAL_RX_STATUS_SHIFT;
2546 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
2547 SR_1000T_REMOTE_RX_STATUS_SHIFT;
2550 return E1000_SUCCESS;
2553 /******************************************************************************
2554 * Get PHY information from various PHY registers
2556 * hw - Struct containing variables accessed by shared code
2557 * phy_info - PHY information structure
2558 ******************************************************************************/
2560 em_phy_get_info(struct em_hw *hw,
2561 struct em_phy_info *phy_info)
2565 DEBUGFUNC("em_phy_get_info");
2567 phy_info->cable_length = em_cable_length_undefined;
2568 phy_info->extended_10bt_distance = em_10bt_ext_dist_enable_undefined;
2569 phy_info->cable_polarity = em_rev_polarity_undefined;
2570 phy_info->downshift = em_downshift_undefined;
2571 phy_info->polarity_correction = em_polarity_reversal_undefined;
2572 phy_info->mdix_mode = em_auto_x_mode_undefined;
2573 phy_info->local_rx = em_1000t_rx_status_undefined;
2574 phy_info->remote_rx = em_1000t_rx_status_undefined;
2576 if(hw->media_type != em_media_type_copper) {
2577 DEBUGOUT("PHY info is only valid for copper media\n");
2578 return -E1000_ERR_CONFIG;
2581 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
2582 DEBUGOUT("PHY Read Error\n");
2583 return -E1000_ERR_PHY;
2585 if(em_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
2586 DEBUGOUT("PHY Read Error\n");
2587 return -E1000_ERR_PHY;
2589 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
2590 DEBUGOUT("PHY info is only valid if link is up\n");
2591 return -E1000_ERR_CONFIG;
2594 if (hw->phy_type == em_phy_igp)
2595 return em_phy_igp_get_info(hw, phy_info);
2597 return em_phy_m88_get_info(hw, phy_info);
2601 em_validate_mdi_setting(struct em_hw *hw)
2603 DEBUGFUNC("em_validate_mdi_settings");
2605 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
2606 DEBUGOUT("Invalid MDI setting detected\n");
2608 return -E1000_ERR_CONFIG;
2614 /******************************************************************************
2615 * Sets up eeprom variables in the hw struct. Must be called after mac_type
2618 * hw - Struct containing variables accessed by shared code
2619 *****************************************************************************/
2621 em_init_eeprom_params(struct em_hw *hw)
2623 struct em_eeprom_info *eeprom = &hw->eeprom;
2624 uint32_t eecd = E1000_READ_REG(hw, EECD);
2625 uint16_t eeprom_size;
2627 DEBUGFUNC("em_init_eeprom_params");
2629 switch (hw->mac_type) {
2630 case em_82542_rev2_0:
2631 case em_82542_rev2_1:
2634 eeprom->type = em_eeprom_microwire;
2635 eeprom->word_size = 64;
2636 eeprom->opcode_bits = 3;
2637 eeprom->address_bits = 6;
2638 eeprom->delay_usec = 50;
2643 eeprom->type = em_eeprom_microwire;
2644 eeprom->opcode_bits = 3;
2645 eeprom->delay_usec = 50;
2646 if(eecd & E1000_EECD_SIZE) {
2647 eeprom->word_size = 256;
2648 eeprom->address_bits = 8;
2650 eeprom->word_size = 64;
2651 eeprom->address_bits = 6;
2657 if (eecd & E1000_EECD_TYPE) {
2658 eeprom->type = em_eeprom_spi;
2659 eeprom->opcode_bits = 8;
2660 eeprom->delay_usec = 1;
2661 if (eecd & E1000_EECD_ADDR_BITS) {
2662 eeprom->page_size = 32;
2663 eeprom->address_bits = 16;
2665 eeprom->page_size = 8;
2666 eeprom->address_bits = 8;
2669 eeprom->type = em_eeprom_microwire;
2670 eeprom->opcode_bits = 3;
2671 eeprom->delay_usec = 50;
2672 if (eecd & E1000_EECD_ADDR_BITS) {
2673 eeprom->word_size = 256;
2674 eeprom->address_bits = 8;
2676 eeprom->word_size = 64;
2677 eeprom->address_bits = 6;
2683 if (eeprom->type == em_eeprom_spi) {
2684 eeprom->word_size = 64;
2685 if (em_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
2686 eeprom_size &= EEPROM_SIZE_MASK;
2688 switch (eeprom_size) {
2689 case EEPROM_SIZE_16KB:
2690 eeprom->word_size = 8192;
2692 case EEPROM_SIZE_8KB:
2693 eeprom->word_size = 4096;
2695 case EEPROM_SIZE_4KB:
2696 eeprom->word_size = 2048;
2698 case EEPROM_SIZE_2KB:
2699 eeprom->word_size = 1024;
2701 case EEPROM_SIZE_1KB:
2702 eeprom->word_size = 512;
2704 case EEPROM_SIZE_512B:
2705 eeprom->word_size = 256;
2707 case EEPROM_SIZE_128B:
2709 eeprom->word_size = 64;
2716 /******************************************************************************
2717 * Raises the EEPROM's clock input.
2719 * hw - Struct containing variables accessed by shared code
2720 * eecd - EECD's current value
2721 *****************************************************************************/
2723 em_raise_ee_clk(struct em_hw *hw,
2726 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
2727 * wait <delay> microseconds.
2729 *eecd = *eecd | E1000_EECD_SK;
2730 E1000_WRITE_REG(hw, EECD, *eecd);
2731 E1000_WRITE_FLUSH(hw);
2732 usec_delay(hw->eeprom.delay_usec);
2735 /******************************************************************************
2736 * Lowers the EEPROM's clock input.
2738 * hw - Struct containing variables accessed by shared code
2739 * eecd - EECD's current value
2740 *****************************************************************************/
2742 em_lower_ee_clk(struct em_hw *hw,
2745 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
2746 * wait 50 microseconds.
2748 *eecd = *eecd & ~E1000_EECD_SK;
2749 E1000_WRITE_REG(hw, EECD, *eecd);
2750 E1000_WRITE_FLUSH(hw);
2751 usec_delay(hw->eeprom.delay_usec);
2754 /******************************************************************************
2755 * Shift data bits out to the EEPROM.
2757 * hw - Struct containing variables accessed by shared code
2758 * data - data to send to the EEPROM
2759 * count - number of bits to shift out
2760 *****************************************************************************/
2762 em_shift_out_ee_bits(struct em_hw *hw,
2766 struct em_eeprom_info *eeprom = &hw->eeprom;
2770 /* We need to shift "count" bits out to the EEPROM. So, value in the
2771 * "data" parameter will be shifted out to the EEPROM one bit at a time.
2772 * In order to do this, "data" must be broken down into bits.
2774 mask = 0x01 << (count - 1);
2775 eecd = E1000_READ_REG(hw, EECD);
2776 if (eeprom->type == em_eeprom_microwire) {
2777 eecd &= ~E1000_EECD_DO;
2778 } else if (eeprom->type == em_eeprom_spi) {
2779 eecd |= E1000_EECD_DO;
2782 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
2783 * and then raising and then lowering the clock (the SK bit controls
2784 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
2785 * by setting "DI" to "0" and then raising and then lowering the clock.
2787 eecd &= ~E1000_EECD_DI;
2790 eecd |= E1000_EECD_DI;
2792 E1000_WRITE_REG(hw, EECD, eecd);
2793 E1000_WRITE_FLUSH(hw);
2795 usec_delay(eeprom->delay_usec);
2797 em_raise_ee_clk(hw, &eecd);
2798 em_lower_ee_clk(hw, &eecd);
2804 /* We leave the "DI" bit set to "0" when we leave this routine. */
2805 eecd &= ~E1000_EECD_DI;
2806 E1000_WRITE_REG(hw, EECD, eecd);
2809 /******************************************************************************
2810 * Shift data bits in from the EEPROM
2812 * hw - Struct containing variables accessed by shared code
2813 *****************************************************************************/
2815 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count)
2821 /* In order to read a register from the EEPROM, we need to shift 'count'
2822 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
2823 * input to the EEPROM (setting the SK bit), and then reading the value of
2824 * the "DO" bit. During this "shifting in" process the "DI" bit should
2828 eecd = E1000_READ_REG(hw, EECD);
2830 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
2833 for(i = 0; i < count; i++) {
2835 em_raise_ee_clk(hw, &eecd);
2837 eecd = E1000_READ_REG(hw, EECD);
2839 eecd &= ~(E1000_EECD_DI);
2840 if(eecd & E1000_EECD_DO)
2843 em_lower_ee_clk(hw, &eecd);
2849 /******************************************************************************
2850 * Prepares EEPROM for access
2852 * hw - Struct containing variables accessed by shared code
2854 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
2855 * function should be called before issuing a command to the EEPROM.
2856 *****************************************************************************/
2858 em_acquire_eeprom(struct em_hw *hw)
2860 struct em_eeprom_info *eeprom = &hw->eeprom;
2863 DEBUGFUNC("em_acquire_eeprom");
2865 eecd = E1000_READ_REG(hw, EECD);
2867 /* Request EEPROM Access */
2868 if(hw->mac_type > em_82544) {
2869 eecd |= E1000_EECD_REQ;
2870 E1000_WRITE_REG(hw, EECD, eecd);
2871 eecd = E1000_READ_REG(hw, EECD);
2872 while((!(eecd & E1000_EECD_GNT)) &&
2873 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
2876 eecd = E1000_READ_REG(hw, EECD);
2878 if(!(eecd & E1000_EECD_GNT)) {
2879 eecd &= ~E1000_EECD_REQ;
2880 E1000_WRITE_REG(hw, EECD, eecd);
2881 DEBUGOUT("Could not acquire EEPROM grant\n");
2882 return -E1000_ERR_EEPROM;
2886 /* Setup EEPROM for Read/Write */
2888 if (eeprom->type == em_eeprom_microwire) {
2889 /* Clear SK and DI */
2890 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
2891 E1000_WRITE_REG(hw, EECD, eecd);
2894 eecd |= E1000_EECD_CS;
2895 E1000_WRITE_REG(hw, EECD, eecd);
2896 } else if (eeprom->type == em_eeprom_spi) {
2897 /* Clear SK and CS */
2898 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2899 E1000_WRITE_REG(hw, EECD, eecd);
2903 return E1000_SUCCESS;
2906 /******************************************************************************
2907 * Returns EEPROM to a "standby" state
2909 * hw - Struct containing variables accessed by shared code
2910 *****************************************************************************/
2912 em_standby_eeprom(struct em_hw *hw)
2914 struct em_eeprom_info *eeprom = &hw->eeprom;
2917 eecd = E1000_READ_REG(hw, EECD);
2919 if(eeprom->type == em_eeprom_microwire) {
2920 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2921 E1000_WRITE_REG(hw, EECD, eecd);
2922 E1000_WRITE_FLUSH(hw);
2923 usec_delay(eeprom->delay_usec);
2926 eecd |= E1000_EECD_SK;
2927 E1000_WRITE_REG(hw, EECD, eecd);
2928 E1000_WRITE_FLUSH(hw);
2929 usec_delay(eeprom->delay_usec);
2932 eecd |= E1000_EECD_CS;
2933 E1000_WRITE_REG(hw, EECD, eecd);
2934 E1000_WRITE_FLUSH(hw);
2935 usec_delay(eeprom->delay_usec);
2938 eecd &= ~E1000_EECD_SK;
2939 E1000_WRITE_REG(hw, EECD, eecd);
2940 E1000_WRITE_FLUSH(hw);
2941 usec_delay(eeprom->delay_usec);
2942 } else if(eeprom->type == em_eeprom_spi) {
2943 /* Toggle CS to flush commands */
2944 eecd |= E1000_EECD_CS;
2945 E1000_WRITE_REG(hw, EECD, eecd);
2946 E1000_WRITE_FLUSH(hw);
2947 usec_delay(eeprom->delay_usec);
2948 eecd &= ~E1000_EECD_CS;
2949 E1000_WRITE_REG(hw, EECD, eecd);
2950 E1000_WRITE_FLUSH(hw);
2951 usec_delay(eeprom->delay_usec);
2955 /******************************************************************************
2956 * Terminates a command by inverting the EEPROM's chip select pin
2958 * hw - Struct containing variables accessed by shared code
2959 *****************************************************************************/
2961 em_release_eeprom(struct em_hw *hw)
2965 DEBUGFUNC("em_release_eeprom");
2967 eecd = E1000_READ_REG(hw, EECD);
2969 if (hw->eeprom.type == em_eeprom_spi) {
2970 eecd |= E1000_EECD_CS; /* Pull CS high */
2971 eecd &= ~E1000_EECD_SK; /* Lower SCK */
2973 E1000_WRITE_REG(hw, EECD, eecd);
2975 usec_delay(hw->eeprom.delay_usec);
2976 } else if(hw->eeprom.type == em_eeprom_microwire) {
2977 /* cleanup eeprom */
2979 /* CS on Microwire is active-high */
2980 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
2982 E1000_WRITE_REG(hw, EECD, eecd);
2984 /* Rising edge of clock */
2985 eecd |= E1000_EECD_SK;
2986 E1000_WRITE_REG(hw, EECD, eecd);
2987 E1000_WRITE_FLUSH(hw);
2988 usec_delay(hw->eeprom.delay_usec);
2990 /* Falling edge of clock */
2991 eecd &= ~E1000_EECD_SK;
2992 E1000_WRITE_REG(hw, EECD, eecd);
2993 E1000_WRITE_FLUSH(hw);
2994 usec_delay(hw->eeprom.delay_usec);
2997 /* Stop requesting EEPROM access */
2998 if(hw->mac_type > em_82544) {
2999 eecd &= ~E1000_EECD_REQ;
3000 E1000_WRITE_REG(hw, EECD, eecd);
3004 /******************************************************************************
3005 * Reads a 16 bit word from the EEPROM.
3007 * hw - Struct containing variables accessed by shared code
3008 *****************************************************************************/
3010 em_spi_eeprom_ready(struct em_hw *hw)
3012 uint16_t retry_count = 0;
3013 uint8_t spi_stat_reg;
3015 DEBUGFUNC("em_spi_eeprom_ready");
3017 /* Read "Status Register" repeatedly until the LSB is cleared. The
3018 * EEPROM will signal that the command has been completed by clearing
3019 * bit 0 of the internal status register. If it's not cleared within
3020 * 5 milliseconds, then error out.
3024 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3025 hw->eeprom.opcode_bits);
3026 spi_stat_reg = (uint8_t)em_shift_in_ee_bits(hw, 8);
3027 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3033 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3035 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3036 * only 0-5mSec on 5V devices)
3038 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3039 DEBUGOUT("SPI EEPROM Status error\n");
3040 return -E1000_ERR_EEPROM;
3043 return E1000_SUCCESS;
3046 /******************************************************************************
3047 * Reads a 16 bit word from the EEPROM.
3049 * hw - Struct containing variables accessed by shared code
3050 * offset - offset of word in the EEPROM to read
3051 * data - word read from the EEPROM
3052 * words - number of words to read
3053 *****************************************************************************/
3055 em_read_eeprom(struct em_hw *hw,
3060 struct em_eeprom_info *eeprom = &hw->eeprom;
3063 DEBUGFUNC("em_read_eeprom");
3065 /* A check for invalid values: offset too large, too many words, and not
3068 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3070 DEBUGOUT("\"words\" parameter out of bounds\n");
3071 return -E1000_ERR_EEPROM;
3074 /* Prepare the EEPROM for reading */
3075 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
3076 return -E1000_ERR_EEPROM;
3078 if(eeprom->type == em_eeprom_spi) {
3079 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3081 if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3083 em_standby_eeprom(hw);
3085 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3086 if((eeprom->address_bits == 8) && (offset >= 128))
3087 read_opcode |= EEPROM_A8_OPCODE_SPI;
3089 /* Send the READ command (opcode + addr) */
3090 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3091 em_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3093 else if(eeprom->type == em_eeprom_microwire) {
3094 /* Send the READ command (opcode + addr) */
3095 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3096 eeprom->opcode_bits);
3097 em_shift_out_ee_bits(hw, offset, eeprom->address_bits);
3100 /* Read the data. The address of the eeprom internally increments with
3101 * each word (microwire) or byte (spi) being read, saving on the overhead
3102 * of eeprom setup and tear-down. The address counter will roll over if
3103 * reading beyond the size of the eeprom, thus allowing the entire memory
3104 * to be read starting from any offset. */
3105 for (i = 0; i < words; i++) {
3106 uint16_t word_in = em_shift_in_ee_bits(hw, 16);
3107 if (eeprom->type == em_eeprom_spi)
3108 word_in = (word_in >> 8) | (word_in << 8);
3112 /* End this read operation */
3113 em_release_eeprom(hw);
3118 /******************************************************************************
3119 * Verifies that the EEPROM has a valid checksum
3121 * hw - Struct containing variables accessed by shared code
3123 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3124 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3126 *****************************************************************************/
3128 em_validate_eeprom_checksum(struct em_hw *hw)
3130 uint16_t checksum = 0;
3131 uint16_t i, eeprom_data;
3133 DEBUGFUNC("em_validate_eeprom_checksum");
3135 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3136 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3137 DEBUGOUT("EEPROM Read Error\n");
3138 return -E1000_ERR_EEPROM;
3140 checksum += eeprom_data;
3143 if(checksum == (uint16_t) EEPROM_SUM) {
3146 DEBUGOUT("EEPROM Checksum Invalid\n");
3147 return -E1000_ERR_EEPROM;
3151 /******************************************************************************
3152 * Calculates the EEPROM checksum and writes it to the EEPROM
3154 * hw - Struct containing variables accessed by shared code
3156 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3157 * Writes the difference to word offset 63 of the EEPROM.
3158 *****************************************************************************/
3160 em_update_eeprom_checksum(struct em_hw *hw)
3162 uint16_t checksum = 0;
3163 uint16_t i, eeprom_data;
3165 DEBUGFUNC("em_update_eeprom_checksum");
3167 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3168 if(em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3169 DEBUGOUT("EEPROM Read Error\n");
3170 return -E1000_ERR_EEPROM;
3172 checksum += eeprom_data;
3174 checksum = (uint16_t) EEPROM_SUM - checksum;
3175 if(em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3176 DEBUGOUT("EEPROM Write Error\n");
3177 return -E1000_ERR_EEPROM;
3182 /******************************************************************************
3183 * Parent function for writing words to the different EEPROM types.
3185 * hw - Struct containing variables accessed by shared code
3186 * offset - offset within the EEPROM to be written to
3187 * words - number of words to write
3188 * data - 16 bit word to be written to the EEPROM
3190 * If em_update_eeprom_checksum is not called after this function, the
3191 * EEPROM will most likely contain an invalid checksum.
3192 *****************************************************************************/
3194 em_write_eeprom(struct em_hw *hw,
3199 struct em_eeprom_info *eeprom = &hw->eeprom;
3202 DEBUGFUNC("em_write_eeprom");
3204 /* A check for invalid values: offset too large, too many words, and not
3207 if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3209 DEBUGOUT("\"words\" parameter out of bounds\n");
3210 return -E1000_ERR_EEPROM;
3213 /* Prepare the EEPROM for writing */
3214 if (em_acquire_eeprom(hw) != E1000_SUCCESS)
3215 return -E1000_ERR_EEPROM;
3217 if(eeprom->type == em_eeprom_microwire)
3218 status = em_write_eeprom_microwire(hw, offset, words, data);
3220 status = em_write_eeprom_spi(hw, offset, words, data);
3222 /* Done with writing */
3223 em_release_eeprom(hw);
3228 /******************************************************************************
3229 * Writes a 16 bit word to a given offset in an SPI EEPROM.
3231 * hw - Struct containing variables accessed by shared code
3232 * offset - offset within the EEPROM to be written to
3233 * words - number of words to write
3234 * data - pointer to array of 8 bit words to be written to the EEPROM
3236 *****************************************************************************/
3238 em_write_eeprom_spi(struct em_hw *hw,
3243 struct em_eeprom_info *eeprom = &hw->eeprom;
3246 DEBUGFUNC("em_write_eeprom_spi");
3248 while (widx < words) {
3249 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
3251 if(em_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
3253 em_standby_eeprom(hw);
3255 /* Send the WRITE ENABLE command (8 bit opcode ) */
3256 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3257 eeprom->opcode_bits);
3259 em_standby_eeprom(hw);
3261 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3262 if((eeprom->address_bits == 8) && (offset >= 128))
3263 write_opcode |= EEPROM_A8_OPCODE_SPI;
3265 /* Send the Write command (8-bit opcode + addr) */
3266 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
3268 em_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
3269 eeprom->address_bits);
3273 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
3274 while (widx < words) {
3275 uint16_t word_out = data[widx];
3276 word_out = (word_out >> 8) | (word_out << 8);
3277 em_shift_out_ee_bits(hw, word_out, 16);
3280 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
3281 * operation, while the smaller eeproms are capable of an 8-byte
3282 * PAGE WRITE operation. Break the inner loop to pass new address
3284 if((((offset + widx)*2) % eeprom->page_size) == 0) {
3285 em_standby_eeprom(hw);
3291 return E1000_SUCCESS;
3294 /******************************************************************************
3295 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
3297 * hw - Struct containing variables accessed by shared code
3298 * offset - offset within the EEPROM to be written to
3299 * words - number of words to write
3300 * data - pointer to array of 16 bit words to be written to the EEPROM
3302 *****************************************************************************/
3304 em_write_eeprom_microwire(struct em_hw *hw,
3309 struct em_eeprom_info *eeprom = &hw->eeprom;
3311 uint16_t words_written = 0;
3314 DEBUGFUNC("em_write_eeprom_microwire");
3316 /* Send the write enable command to the EEPROM (3-bit opcode plus
3317 * 6/8-bit dummy address beginning with 11). It's less work to include
3318 * the 11 of the dummy address as part of the opcode than it is to shift
3319 * it over the correct number of bits for the address. This puts the
3320 * EEPROM into write/erase mode.
3322 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
3323 (uint16_t)(eeprom->opcode_bits + 2));
3325 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3327 /* Prepare the EEPROM */
3328 em_standby_eeprom(hw);
3330 while (words_written < words) {
3331 /* Send the Write command (3-bit opcode + addr) */
3332 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
3333 eeprom->opcode_bits);
3335 em_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
3336 eeprom->address_bits);
3339 em_shift_out_ee_bits(hw, data[words_written], 16);
3341 /* Toggle the CS line. This in effect tells the EEPROM to execute
3342 * the previous command.
3344 em_standby_eeprom(hw);
3346 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
3347 * signal that the command has been completed by raising the DO signal.
3348 * If DO does not go high in 10 milliseconds, then error out.
3350 for(i = 0; i < 200; i++) {
3351 eecd = E1000_READ_REG(hw, EECD);
3352 if(eecd & E1000_EECD_DO) break;
3356 DEBUGOUT("EEPROM Write did not complete\n");
3357 return -E1000_ERR_EEPROM;
3360 /* Recover from write */
3361 em_standby_eeprom(hw);
3366 /* Send the write disable command to the EEPROM (3-bit opcode plus
3367 * 6/8-bit dummy address beginning with 10). It's less work to include
3368 * the 10 of the dummy address as part of the opcode than it is to shift
3369 * it over the correct number of bits for the address. This takes the
3370 * EEPROM out of write/erase mode.
3372 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
3373 (uint16_t)(eeprom->opcode_bits + 2));
3375 em_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
3380 /******************************************************************************
3381 * Reads the adapter's part number from the EEPROM
3383 * hw - Struct containing variables accessed by shared code
3384 * part_num - Adapter's part number
3385 *****************************************************************************/
3387 em_read_part_num(struct em_hw *hw,
3390 uint16_t offset = EEPROM_PBA_BYTE_1;
3391 uint16_t eeprom_data;
3393 DEBUGFUNC("em_read_part_num");
3395 /* Get word 0 from EEPROM */
3396 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3397 DEBUGOUT("EEPROM Read Error\n");
3398 return -E1000_ERR_EEPROM;
3400 /* Save word 0 in upper half of part_num */
3401 *part_num = (uint32_t) (eeprom_data << 16);
3403 /* Get word 1 from EEPROM */
3404 if(em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
3405 DEBUGOUT("EEPROM Read Error\n");
3406 return -E1000_ERR_EEPROM;
3408 /* Save word 1 in lower half of part_num */
3409 *part_num |= eeprom_data;
3414 /******************************************************************************
3415 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3416 * second function of dual function devices
3418 * hw - Struct containing variables accessed by shared code
3419 *****************************************************************************/
3421 em_read_mac_addr(struct em_hw * hw)
3424 uint16_t eeprom_data, i;
3426 DEBUGFUNC("em_read_mac_addr");
3428 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3430 if(em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3431 DEBUGOUT("EEPROM Read Error\n");
3432 return -E1000_ERR_EEPROM;
3434 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
3435 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
3437 if((hw->mac_type == em_82546) &&
3438 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3439 if(hw->perm_mac_addr[5] & 0x01)
3440 hw->perm_mac_addr[5] &= ~(0x01);
3442 hw->perm_mac_addr[5] |= 0x01;
3444 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
3445 hw->mac_addr[i] = hw->perm_mac_addr[i];
3449 /******************************************************************************
3450 * Initializes receive address filters.
3452 * hw - Struct containing variables accessed by shared code
3454 * Places the MAC address in receive address register 0 and clears the rest
3455 * of the receive addresss registers. Clears the multicast table. Assumes
3456 * the receiver is in reset when the routine is called.
3457 *****************************************************************************/
3459 em_init_rx_addrs(struct em_hw *hw)
3465 DEBUGFUNC("em_init_rx_addrs");
3467 /* Setup the receive address. */
3468 DEBUGOUT("Programming MAC Address into RAR[0]\n");
3469 addr_low = (hw->mac_addr[0] |
3470 (hw->mac_addr[1] << 8) |
3471 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
3473 addr_high = (hw->mac_addr[4] |
3474 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
3476 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
3477 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
3479 /* Zero out the other 15 receive addresses. */
3480 DEBUGOUT("Clearing RAR[1-15]\n");
3481 for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3482 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3483 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3487 /******************************************************************************
3488 * Updates the MAC's list of multicast addresses.
3490 * hw - Struct containing variables accessed by shared code
3491 * mc_addr_list - the list of new multicast addresses
3492 * mc_addr_count - number of addresses
3493 * pad - number of bytes between addresses in the list
3495 * The given list replaces any existing list. Clears the last 15 receive
3496 * address registers and the multicast table. Uses receive address registers
3497 * for the first 15 multicast addresses, and hashes the rest into the
3499 *****************************************************************************/
3501 em_mc_addr_list_update(struct em_hw *hw,
3502 uint8_t *mc_addr_list,
3503 uint32_t mc_addr_count,
3506 uint32_t hash_value;
3508 uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
3510 DEBUGFUNC("em_mc_addr_list_update");
3512 /* Set the new number of MC addresses that we are being requested to use. */
3513 hw->num_mc_addrs = mc_addr_count;
3515 /* Clear RAR[1-15] */
3516 DEBUGOUT(" Clearing RAR[1-15]\n");
3517 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) {
3518 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3519 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3523 DEBUGOUT(" Clearing MTA\n");
3524 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) {
3525 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3528 /* Add the new addresses */
3529 for(i = 0; i < mc_addr_count; i++) {
3530 DEBUGOUT(" Adding the multicast addresses:\n");
3531 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
3532 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
3533 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
3534 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
3535 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
3536 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
3537 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
3539 hash_value = em_hash_mc_addr(hw,
3541 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
3543 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
3545 /* Place this multicast address in the RAR if there is room, *
3546 * else put it in the MTA
3548 if(rar_used_count < E1000_RAR_ENTRIES) {
3550 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3554 em_mta_set(hw, hash_value);
3557 DEBUGOUT("MC Update Complete\n");
3560 /******************************************************************************
3561 * Hashes an address to determine its location in the multicast table
3563 * hw - Struct containing variables accessed by shared code
3564 * mc_addr - the multicast address to hash
3565 *****************************************************************************/
3567 em_hash_mc_addr(struct em_hw *hw,
3570 uint32_t hash_value = 0;
3572 /* The portion of the address that is used for the hash table is
3573 * determined by the mc_filter_type setting.
3575 switch (hw->mc_filter_type) {
3576 /* [0] [1] [2] [3] [4] [5]
3581 /* [47:36] i.e. 0x563 for above example address */
3582 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
3585 /* [46:35] i.e. 0xAC6 for above example address */
3586 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
3589 /* [45:34] i.e. 0x5D8 for above example address */
3590 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
3593 /* [43:32] i.e. 0x634 for above example address */
3594 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
3598 hash_value &= 0xFFF;
3602 /******************************************************************************
3603 * Sets the bit in the multicast table corresponding to the hash value.
3605 * hw - Struct containing variables accessed by shared code
3606 * hash_value - Multicast address hash value
3607 *****************************************************************************/
3609 em_mta_set(struct em_hw *hw,
3610 uint32_t hash_value)
3612 uint32_t hash_bit, hash_reg;
3616 /* The MTA is a register array of 128 32-bit registers.
3617 * It is treated like an array of 4096 bits. We want to set
3618 * bit BitArray[hash_value]. So we figure out what register
3619 * the bit is in, read it, OR in the new bit, then write
3620 * back the new value. The register is determined by the
3621 * upper 7 bits of the hash value and the bit within that
3622 * register are determined by the lower 5 bits of the value.
3624 hash_reg = (hash_value >> 5) & 0x7F;
3625 hash_bit = hash_value & 0x1F;
3627 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
3629 mta |= (1 << hash_bit);
3631 /* If we are on an 82544 and we are trying to write an odd offset
3632 * in the MTA, save off the previous entry before writing and
3633 * restore the old value after writing.
3635 if((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
3636 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
3637 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
3638 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
3640 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
3644 /******************************************************************************
3645 * Puts an ethernet address into a receive address register.
3647 * hw - Struct containing variables accessed by shared code
3648 * addr - Address to put into receive address register
3649 * index - Receive address register to write
3650 *****************************************************************************/
3652 em_rar_set(struct em_hw *hw,
3656 uint32_t rar_low, rar_high;
3658 /* HW expects these in little endian so we reverse the byte order
3659 * from network order (big endian) to little endian
3661 rar_low = ((uint32_t) addr[0] |
3662 ((uint32_t) addr[1] << 8) |
3663 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
3665 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
3667 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
3668 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
3671 /******************************************************************************
3672 * Writes a value to the specified offset in the VLAN filter table.
3674 * hw - Struct containing variables accessed by shared code
3675 * offset - Offset in VLAN filer table to write
3676 * value - Value to write into VLAN filter table
3677 *****************************************************************************/
3679 em_write_vfta(struct em_hw *hw,
3685 if((hw->mac_type == em_82544) && ((offset & 0x1) == 1)) {
3686 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
3687 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
3688 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
3690 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
3694 /******************************************************************************
3695 * Clears the VLAN filer table
3697 * hw - Struct containing variables accessed by shared code
3698 *****************************************************************************/
3700 em_clear_vfta(struct em_hw *hw)
3704 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
3705 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
3709 em_id_led_init(struct em_hw * hw)
3712 const uint32_t ledctl_mask = 0x000000FF;
3713 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
3714 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
3715 uint16_t eeprom_data, i, temp;
3716 const uint16_t led_mask = 0x0F;
3718 DEBUGFUNC("em_id_led_init");
3720 if(hw->mac_type < em_82540) {
3725 ledctl = E1000_READ_REG(hw, LEDCTL);
3726 hw->ledctl_default = ledctl;
3727 hw->ledctl_mode1 = hw->ledctl_default;
3728 hw->ledctl_mode2 = hw->ledctl_default;
3730 if(em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
3731 DEBUGOUT("EEPROM Read Error\n");
3732 return -E1000_ERR_EEPROM;
3734 if((eeprom_data== ID_LED_RESERVED_0000) ||
3735 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
3736 for(i = 0; i < 4; i++) {
3737 temp = (eeprom_data >> (i << 2)) & led_mask;
3739 case ID_LED_ON1_DEF2:
3740 case ID_LED_ON1_ON2:
3741 case ID_LED_ON1_OFF2:
3742 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
3743 hw->ledctl_mode1 |= ledctl_on << (i << 3);
3745 case ID_LED_OFF1_DEF2:
3746 case ID_LED_OFF1_ON2:
3747 case ID_LED_OFF1_OFF2:
3748 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
3749 hw->ledctl_mode1 |= ledctl_off << (i << 3);
3756 case ID_LED_DEF1_ON2:
3757 case ID_LED_ON1_ON2:
3758 case ID_LED_OFF1_ON2:
3759 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
3760 hw->ledctl_mode2 |= ledctl_on << (i << 3);
3762 case ID_LED_DEF1_OFF2:
3763 case ID_LED_ON1_OFF2:
3764 case ID_LED_OFF1_OFF2:
3765 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
3766 hw->ledctl_mode2 |= ledctl_off << (i << 3);
3776 /******************************************************************************
3777 * Prepares SW controlable LED for use and saves the current state of the LED.
3779 * hw - Struct containing variables accessed by shared code
3780 *****************************************************************************/
3782 em_setup_led(struct em_hw *hw)
3786 DEBUGFUNC("em_setup_led");
3788 switch(hw->device_id) {
3789 case E1000_DEV_ID_82542:
3790 case E1000_DEV_ID_82543GC_FIBER:
3791 case E1000_DEV_ID_82543GC_COPPER:
3792 case E1000_DEV_ID_82544EI_COPPER:
3793 case E1000_DEV_ID_82544EI_FIBER:
3794 case E1000_DEV_ID_82544GC_COPPER:
3795 case E1000_DEV_ID_82544GC_LOM:
3796 /* No setup necessary */
3798 case E1000_DEV_ID_82545EM_FIBER:
3799 case E1000_DEV_ID_82546EB_FIBER:
3800 ledctl = E1000_READ_REG(hw, LEDCTL);
3801 /* Save current LEDCTL settings */
3802 hw->ledctl_default = ledctl;
3804 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
3805 E1000_LEDCTL_LED0_BLINK |
3806 E1000_LEDCTL_LED0_MODE_MASK);
3807 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT);
3808 E1000_WRITE_REG(hw, LEDCTL, ledctl);
3810 case E1000_DEV_ID_82540EP:
3811 case E1000_DEV_ID_82540EP_LOM:
3812 case E1000_DEV_ID_82540EP_LP:
3813 case E1000_DEV_ID_82540EM:
3814 case E1000_DEV_ID_82540EM_LOM:
3815 case E1000_DEV_ID_82545EM_COPPER:
3816 case E1000_DEV_ID_82546EB_COPPER:
3817 case E1000_DEV_ID_82546EB_QUAD_COPPER:
3818 case E1000_DEV_ID_82541EI:
3819 case E1000_DEV_ID_82541EP:
3820 case E1000_DEV_ID_82547EI:
3821 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
3824 DEBUGOUT("Invalid device ID\n");
3825 return -E1000_ERR_CONFIG;
3830 /******************************************************************************
3831 * Restores the saved state of the SW controlable LED.
3833 * hw - Struct containing variables accessed by shared code
3834 *****************************************************************************/
3836 em_cleanup_led(struct em_hw *hw)
3838 DEBUGFUNC("em_cleanup_led");
3840 switch(hw->device_id) {
3841 case E1000_DEV_ID_82542:
3842 case E1000_DEV_ID_82543GC_FIBER:
3843 case E1000_DEV_ID_82543GC_COPPER:
3844 case E1000_DEV_ID_82544EI_COPPER:
3845 case E1000_DEV_ID_82544EI_FIBER:
3846 case E1000_DEV_ID_82544GC_COPPER:
3847 case E1000_DEV_ID_82544GC_LOM:
3848 /* No cleanup necessary */
3850 case E1000_DEV_ID_82540EP:
3851 case E1000_DEV_ID_82540EP_LOM:
3852 case E1000_DEV_ID_82540EP_LP:
3853 case E1000_DEV_ID_82540EM:
3854 case E1000_DEV_ID_82540EM_LOM:
3855 case E1000_DEV_ID_82545EM_COPPER:
3856 case E1000_DEV_ID_82545EM_FIBER:
3857 case E1000_DEV_ID_82546EB_COPPER:
3858 case E1000_DEV_ID_82546EB_FIBER:
3859 case E1000_DEV_ID_82546EB_QUAD_COPPER:
3860 case E1000_DEV_ID_82541EI:
3861 case E1000_DEV_ID_82541EP:
3862 case E1000_DEV_ID_82547EI:
3863 /* Restore LEDCTL settings */
3864 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
3867 DEBUGOUT("Invalid device ID\n");
3868 return -E1000_ERR_CONFIG;
3873 /******************************************************************************
3874 * Turns on the software controllable LED
3876 * hw - Struct containing variables accessed by shared code
3877 *****************************************************************************/
3879 em_led_on(struct em_hw *hw)
3883 DEBUGFUNC("em_led_on");
3885 switch(hw->device_id) {
3886 case E1000_DEV_ID_82542:
3887 case E1000_DEV_ID_82543GC_FIBER:
3888 case E1000_DEV_ID_82543GC_COPPER:
3889 case E1000_DEV_ID_82544EI_FIBER:
3890 ctrl = E1000_READ_REG(hw, CTRL);
3891 /* Set SW Defineable Pin 0 to turn on the LED */
3892 ctrl |= E1000_CTRL_SWDPIN0;
3893 ctrl |= E1000_CTRL_SWDPIO0;
3894 E1000_WRITE_REG(hw, CTRL, ctrl);
3896 case E1000_DEV_ID_82544EI_COPPER:
3897 case E1000_DEV_ID_82544GC_COPPER:
3898 case E1000_DEV_ID_82544GC_LOM:
3899 case E1000_DEV_ID_82545EM_FIBER:
3900 case E1000_DEV_ID_82546EB_FIBER:
3901 ctrl = E1000_READ_REG(hw, CTRL);
3902 /* Clear SW Defineable Pin 0 to turn on the LED */
3903 ctrl &= ~E1000_CTRL_SWDPIN0;
3904 ctrl |= E1000_CTRL_SWDPIO0;
3905 E1000_WRITE_REG(hw, CTRL, ctrl);
3907 case E1000_DEV_ID_82540EP:
3908 case E1000_DEV_ID_82540EP_LOM:
3909 case E1000_DEV_ID_82540EP_LP:
3910 case E1000_DEV_ID_82540EM:
3911 case E1000_DEV_ID_82540EM_LOM:
3912 case E1000_DEV_ID_82545EM_COPPER:
3913 case E1000_DEV_ID_82546EB_COPPER:
3914 case E1000_DEV_ID_82546EB_QUAD_COPPER:
3915 case E1000_DEV_ID_82541EI:
3916 case E1000_DEV_ID_82541EP:
3917 case E1000_DEV_ID_82547EI:
3918 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
3921 DEBUGOUT("Invalid device ID\n");
3922 return -E1000_ERR_CONFIG;
3927 /******************************************************************************
3928 * Turns off the software controllable LED
3930 * hw - Struct containing variables accessed by shared code
3931 *****************************************************************************/
3933 em_led_off(struct em_hw *hw)
3937 DEBUGFUNC("em_led_off");
3939 switch(hw->device_id) {
3940 case E1000_DEV_ID_82542:
3941 case E1000_DEV_ID_82543GC_FIBER:
3942 case E1000_DEV_ID_82543GC_COPPER:
3943 case E1000_DEV_ID_82544EI_FIBER:
3944 ctrl = E1000_READ_REG(hw, CTRL);
3945 /* Clear SW Defineable Pin 0 to turn off the LED */
3946 ctrl &= ~E1000_CTRL_SWDPIN0;
3947 ctrl |= E1000_CTRL_SWDPIO0;
3948 E1000_WRITE_REG(hw, CTRL, ctrl);
3950 case E1000_DEV_ID_82544EI_COPPER:
3951 case E1000_DEV_ID_82544GC_COPPER:
3952 case E1000_DEV_ID_82544GC_LOM:
3953 case E1000_DEV_ID_82545EM_FIBER:
3954 case E1000_DEV_ID_82546EB_FIBER:
3955 ctrl = E1000_READ_REG(hw, CTRL);
3956 /* Set SW Defineable Pin 0 to turn off the LED */
3957 ctrl |= E1000_CTRL_SWDPIN0;
3958 ctrl |= E1000_CTRL_SWDPIO0;
3959 E1000_WRITE_REG(hw, CTRL, ctrl);
3961 case E1000_DEV_ID_82540EP:
3962 case E1000_DEV_ID_82540EP_LOM:
3963 case E1000_DEV_ID_82540EP_LP:
3964 case E1000_DEV_ID_82540EM:
3965 case E1000_DEV_ID_82540EM_LOM:
3966 case E1000_DEV_ID_82545EM_COPPER:
3967 case E1000_DEV_ID_82546EB_COPPER:
3968 case E1000_DEV_ID_82546EB_QUAD_COPPER:
3969 case E1000_DEV_ID_82541EI:
3970 case E1000_DEV_ID_82541EP:
3971 case E1000_DEV_ID_82547EI:
3972 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
3975 DEBUGOUT("Invalid device ID\n");
3976 return -E1000_ERR_CONFIG;
3981 /******************************************************************************
3982 * Clears all hardware statistics counters.
3984 * hw - Struct containing variables accessed by shared code
3985 *****************************************************************************/
3987 em_clear_hw_cntrs(struct em_hw *hw)
3989 volatile uint32_t temp;
3991 temp = E1000_READ_REG(hw, CRCERRS);
3992 temp = E1000_READ_REG(hw, SYMERRS);
3993 temp = E1000_READ_REG(hw, MPC);
3994 temp = E1000_READ_REG(hw, SCC);
3995 temp = E1000_READ_REG(hw, ECOL);
3996 temp = E1000_READ_REG(hw, MCC);
3997 temp = E1000_READ_REG(hw, LATECOL);
3998 temp = E1000_READ_REG(hw, COLC);
3999 temp = E1000_READ_REG(hw, DC);
4000 temp = E1000_READ_REG(hw, SEC);
4001 temp = E1000_READ_REG(hw, RLEC);
4002 temp = E1000_READ_REG(hw, XONRXC);
4003 temp = E1000_READ_REG(hw, XONTXC);
4004 temp = E1000_READ_REG(hw, XOFFRXC);
4005 temp = E1000_READ_REG(hw, XOFFTXC);
4006 temp = E1000_READ_REG(hw, FCRUC);
4007 temp = E1000_READ_REG(hw, PRC64);
4008 temp = E1000_READ_REG(hw, PRC127);
4009 temp = E1000_READ_REG(hw, PRC255);
4010 temp = E1000_READ_REG(hw, PRC511);
4011 temp = E1000_READ_REG(hw, PRC1023);
4012 temp = E1000_READ_REG(hw, PRC1522);
4013 temp = E1000_READ_REG(hw, GPRC);
4014 temp = E1000_READ_REG(hw, BPRC);
4015 temp = E1000_READ_REG(hw, MPRC);
4016 temp = E1000_READ_REG(hw, GPTC);
4017 temp = E1000_READ_REG(hw, GORCL);
4018 temp = E1000_READ_REG(hw, GORCH);
4019 temp = E1000_READ_REG(hw, GOTCL);
4020 temp = E1000_READ_REG(hw, GOTCH);
4021 temp = E1000_READ_REG(hw, RNBC);
4022 temp = E1000_READ_REG(hw, RUC);
4023 temp = E1000_READ_REG(hw, RFC);
4024 temp = E1000_READ_REG(hw, ROC);
4025 temp = E1000_READ_REG(hw, RJC);
4026 temp = E1000_READ_REG(hw, TORL);
4027 temp = E1000_READ_REG(hw, TORH);
4028 temp = E1000_READ_REG(hw, TOTL);
4029 temp = E1000_READ_REG(hw, TOTH);
4030 temp = E1000_READ_REG(hw, TPR);
4031 temp = E1000_READ_REG(hw, TPT);
4032 temp = E1000_READ_REG(hw, PTC64);
4033 temp = E1000_READ_REG(hw, PTC127);
4034 temp = E1000_READ_REG(hw, PTC255);
4035 temp = E1000_READ_REG(hw, PTC511);
4036 temp = E1000_READ_REG(hw, PTC1023);
4037 temp = E1000_READ_REG(hw, PTC1522);
4038 temp = E1000_READ_REG(hw, MPTC);
4039 temp = E1000_READ_REG(hw, BPTC);
4041 if(hw->mac_type < em_82543) return;
4043 temp = E1000_READ_REG(hw, ALGNERRC);
4044 temp = E1000_READ_REG(hw, RXERRC);
4045 temp = E1000_READ_REG(hw, TNCRS);
4046 temp = E1000_READ_REG(hw, CEXTERR);
4047 temp = E1000_READ_REG(hw, TSCTC);
4048 temp = E1000_READ_REG(hw, TSCTFC);
4050 if(hw->mac_type <= em_82544) return;
4052 temp = E1000_READ_REG(hw, MGTPRC);
4053 temp = E1000_READ_REG(hw, MGTPDC);
4054 temp = E1000_READ_REG(hw, MGTPTC);
4057 /******************************************************************************
4058 * Resets Adaptive IFS to its default state.
4060 * hw - Struct containing variables accessed by shared code
4062 * Call this after em_init_hw. You may override the IFS defaults by setting
4063 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
4064 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4065 * before calling this function.
4066 *****************************************************************************/
4068 em_reset_adaptive(struct em_hw *hw)
4070 DEBUGFUNC("em_reset_adaptive");
4072 if(hw->adaptive_ifs) {
4073 if(!hw->ifs_params_forced) {
4074 hw->current_ifs_val = 0;
4075 hw->ifs_min_val = IFS_MIN;
4076 hw->ifs_max_val = IFS_MAX;
4077 hw->ifs_step_size = IFS_STEP;
4078 hw->ifs_ratio = IFS_RATIO;
4080 hw->in_ifs_mode = FALSE;
4081 E1000_WRITE_REG(hw, AIT, 0);
4083 DEBUGOUT("Not in Adaptive IFS mode!\n");
4087 /******************************************************************************
4088 * Called during the callback/watchdog routine to update IFS value based on
4089 * the ratio of transmits to collisions.
4091 * hw - Struct containing variables accessed by shared code
4092 * tx_packets - Number of transmits since last callback
4093 * total_collisions - Number of collisions since last callback
4094 *****************************************************************************/
4096 em_update_adaptive(struct em_hw *hw)
4098 DEBUGFUNC("em_update_adaptive");
4100 if(hw->adaptive_ifs) {
4101 if((hw->collision_delta * hw->ifs_ratio) >
4102 hw->tx_packet_delta) {
4103 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
4104 hw->in_ifs_mode = TRUE;
4105 if(hw->current_ifs_val < hw->ifs_max_val) {
4106 if(hw->current_ifs_val == 0)
4107 hw->current_ifs_val = hw->ifs_min_val;
4109 hw->current_ifs_val += hw->ifs_step_size;
4110 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
4114 if((hw->in_ifs_mode == TRUE) &&
4115 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4116 hw->current_ifs_val = 0;
4117 hw->in_ifs_mode = FALSE;
4118 E1000_WRITE_REG(hw, AIT, 0);
4122 DEBUGOUT("Not in Adaptive IFS mode!\n");
4126 /******************************************************************************
4127 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4129 * hw - Struct containing variables accessed by shared code
4130 * frame_len - The length of the frame in question
4131 * mac_addr - The Ethernet destination address of the frame in question
4132 *****************************************************************************/
4134 em_tbi_adjust_stats(struct em_hw *hw,
4135 struct em_hw_stats *stats,
4141 /* First adjust the frame length. */
4143 /* We need to adjust the statistics counters, since the hardware
4144 * counters overcount this packet as a CRC error and undercount
4145 * the packet as a good packet
4147 /* This packet should not be counted as a CRC error. */
4149 /* This packet does count as a Good Packet Received. */
4152 /* Adjust the Good Octets received counters */
4153 carry_bit = 0x80000000 & stats->gorcl;
4154 stats->gorcl += frame_len;
4155 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4156 * Received Count) was one before the addition,
4157 * AND it is zero after, then we lost the carry out,
4158 * need to add one to Gorch (Good Octets Received Count High).
4159 * This could be simplified if all environments supported
4162 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
4164 /* Is this a broadcast or multicast? Check broadcast first,
4165 * since the test for a multicast frame will test positive on
4166 * a broadcast frame.
4168 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
4169 /* Broadcast packet */
4171 else if(*mac_addr & 0x01)
4172 /* Multicast packet */
4175 if(frame_len == hw->max_frame_size) {
4176 /* In this case, the hardware has overcounted the number of
4183 /* Adjust the bin counters when the extra byte put the frame in the
4184 * wrong bin. Remember that the frame_len was adjusted above.
4186 if(frame_len == 64) {
4189 } else if(frame_len == 127) {
4192 } else if(frame_len == 255) {
4195 } else if(frame_len == 511) {
4198 } else if(frame_len == 1023) {
4201 } else if(frame_len == 1522) {
4206 /******************************************************************************
4207 * Gets the current PCI bus type, speed, and width of the hardware
4209 * hw - Struct containing variables accessed by shared code
4210 *****************************************************************************/
4212 em_get_bus_info(struct em_hw *hw)
4216 if(hw->mac_type < em_82543) {
4217 hw->bus_type = em_bus_type_unknown;
4218 hw->bus_speed = em_bus_speed_unknown;
4219 hw->bus_width = em_bus_width_unknown;
4223 status = E1000_READ_REG(hw, STATUS);
4224 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4225 em_bus_type_pcix : em_bus_type_pci;
4227 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4228 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
4229 em_bus_speed_66 : em_bus_speed_120;
4230 } else if(hw->bus_type == em_bus_type_pci) {
4231 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4232 em_bus_speed_66 : em_bus_speed_33;
4234 switch (status & E1000_STATUS_PCIX_SPEED) {
4235 case E1000_STATUS_PCIX_SPEED_66:
4236 hw->bus_speed = em_bus_speed_66;
4238 case E1000_STATUS_PCIX_SPEED_100:
4239 hw->bus_speed = em_bus_speed_100;
4241 case E1000_STATUS_PCIX_SPEED_133:
4242 hw->bus_speed = em_bus_speed_133;
4245 hw->bus_speed = em_bus_speed_reserved;
4249 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4250 em_bus_width_64 : em_bus_width_32;
4252 /******************************************************************************
4253 * Reads a value from one of the devices registers using port I/O (as opposed
4254 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4256 * hw - Struct containing variables accessed by shared code
4257 * offset - offset to read from
4258 *****************************************************************************/
4260 em_read_reg_io(struct em_hw *hw,
4263 uint32_t io_addr = hw->io_base;
4264 uint32_t io_data = hw->io_base + 4;
4266 em_io_write(hw, io_addr, offset);
4267 return em_io_read(hw, io_data);
4270 /******************************************************************************
4271 * Writes a value to one of the devices registers using port I/O (as opposed to
4272 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4274 * hw - Struct containing variables accessed by shared code
4275 * offset - offset to write to
4276 * value - value to write
4277 *****************************************************************************/
4279 em_write_reg_io(struct em_hw *hw,
4283 uint32_t io_addr = hw->io_base;
4284 uint32_t io_data = hw->io_base + 4;
4286 em_io_write(hw, io_addr, offset);
4287 em_io_write(hw, io_data, value);
4291 /******************************************************************************
4292 * Estimates the cable length.
4294 * hw - Struct containing variables accessed by shared code
4295 * min_length - The estimated minimum length
4296 * max_length - The estimated maximum length
4298 * returns: E1000_SUCCESS / -E1000_ERR_XXX
4300 * This function always returns a ranged length (minimum & maximum).
4301 * So for M88 phy's, this function interprets the one value returned from the
4302 * register to the minimum and maximum range.
4303 * For IGP phy's, the function calculates the range by the AGC registers.
4304 *****************************************************************************/
4306 em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
4307 uint16_t *max_length)
4309 uint16_t agc_value = 0;
4310 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4311 uint16_t i, phy_data;
4313 DEBUGFUNC("em_get_cable_length");
4315 *min_length = *max_length = 0;
4317 /* Use old method for Phy older than IGP */
4318 if(hw->phy_type == em_phy_m88) {
4319 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
4320 return -E1000_ERR_PHY;
4322 /* Convert the enum value to ranged values */
4323 switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4324 M88E1000_PSSR_CABLE_LENGTH_SHIFT) {
4325 case em_cable_length_50:
4327 *max_length = em_igp_cable_length_50;
4329 case em_cable_length_50_80:
4330 *min_length = em_igp_cable_length_50;
4331 *max_length = em_igp_cable_length_80;
4333 case em_cable_length_80_110:
4334 *min_length = em_igp_cable_length_80;
4335 *max_length = em_igp_cable_length_110;
4337 case em_cable_length_110_140:
4338 *min_length = em_igp_cable_length_110;
4339 *max_length = em_igp_cable_length_140;
4341 case em_cable_length_140:
4342 *min_length = em_igp_cable_length_140;
4343 *max_length = em_igp_cable_length_170;
4346 return -E1000_ERR_PHY;
4349 } else if(hw->phy_type == em_phy_igp) { /* For IGP PHY */
4350 uint16_t agc_reg_array[IGP01E1000_PHY_AGC_NUM] = {IGP01E1000_PHY_AGC_A,
4351 IGP01E1000_PHY_AGC_B,
4352 IGP01E1000_PHY_AGC_C,
4353 IGP01E1000_PHY_AGC_D};
4354 /* Read the AGC registers for all channels */
4355 for(i = 0; i < IGP01E1000_PHY_AGC_NUM; i++) {
4356 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
4357 agc_reg_array[i]) != E1000_SUCCESS)
4358 return -E1000_ERR_PHY;
4359 if(em_read_phy_reg(hw, agc_reg_array[i] &
4360 IGP01E1000_PHY_PAGE_SELECT, &phy_data) !=
4362 return -E1000_ERR_PHY;
4364 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4366 /* Array bound check. */
4367 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4369 return -E1000_ERR_PHY;
4371 agc_value += cur_agc;
4373 /* Update minimal AGC value. */
4374 if(min_agc > cur_agc)
4378 /* Return to page 0 */
4379 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0) !=
4381 return -E1000_ERR_PHY;
4383 /* Remove the minimal AGC result for length < 50m */
4384 if(agc_value < IGP01E1000_PHY_AGC_NUM * em_igp_cable_length_50) {
4385 agc_value -= min_agc;
4387 /* Get the average length of the remaining 3 channels */
4388 agc_value /= (IGP01E1000_PHY_AGC_NUM - 1);
4390 /* Get the average length of all the 4 channels. */
4391 agc_value /= IGP01E1000_PHY_AGC_NUM;
4394 /* Set the range of the calculated length. */
4395 *min_length = ((em_igp_cable_length_table[agc_value] -
4396 IGP01E1000_AGC_RANGE) > 0) ?
4397 (em_igp_cable_length_table[agc_value] -
4398 IGP01E1000_AGC_RANGE) : 0;
4399 *max_length = em_igp_cable_length_table[agc_value] +
4400 IGP01E1000_AGC_RANGE;
4403 return E1000_SUCCESS;
4406 /******************************************************************************
4407 * Check the cable polarity
4409 * hw - Struct containing variables accessed by shared code
4410 * polarity - output parameter : 0 - Polarity is not reversed
4411 * 1 - Polarity is reversed.
4413 * returns: E1000_SUCCESS / -E1000_ERR_XXX
4415 * For phy's older then IGP, this function simply reads the polarity bit in the
4416 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
4417 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4418 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4419 * IGP01E1000_PHY_PCS_INIT_REG.
4420 *****************************************************************************/
4422 em_check_polarity(struct em_hw *hw, uint16_t *polarity)
4426 DEBUGFUNC("em_check_polarity");
4428 if(hw->phy_type == em_phy_m88) {
4429 /* return the Polarity bit in the Status register. */
4430 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
4431 return -E1000_ERR_PHY;
4432 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4433 M88E1000_PSSR_REV_POLARITY_SHIFT;
4434 } else if(hw->phy_type == em_phy_igp) {
4435 /* Read the Status register to check the speed */
4436 if(em_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data) < 0)
4437 return -E1000_ERR_PHY;
4439 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
4440 * find the polarity status */
4441 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4442 IGP01E1000_PSSR_SPEED_1000MBPS) {
4444 /* Read the GIG initialization PCS register (0x00B4) */
4445 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
4446 IGP01E1000_PHY_PCS_INIT_REG) < 0)
4447 return -E1000_ERR_PHY;
4449 if(em_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG &
4450 IGP01E1000_PHY_PAGE_SELECT, &phy_data) < 0)
4451 return -E1000_ERR_PHY;
4453 /* Return to page 0 */
4454 if(em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0) !=
4456 return -E1000_ERR_PHY;
4458 /* Check the polarity bits */
4459 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
4461 /* For 10 Mbps, read the polarity bit in the status register. (for
4462 * 100 Mbps this bit is always 0) */
4463 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
4466 return E1000_SUCCESS;
4469 /******************************************************************************
4470 * Check if Downshift occured
4472 * hw - Struct containing variables accessed by shared code
4473 * downshift - output parameter : 0 - No Downshift ocured.
4474 * 1 - Downshift ocured.
4476 * returns: E1000_SUCCESS / -E1000_ERR_XXX
4478 * For phy's older then IGP, this function reads the Downshift bit in the Phy
4479 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
4480 * Link Health register. In IGP this bit is latched high, so the driver must
4481 * read it immediately after link is established.
4482 *****************************************************************************/
4484 em_check_downshift(struct em_hw *hw)
4488 DEBUGFUNC("em_check_downshift");
4490 if(hw->phy_type == em_phy_igp) {
4491 if(em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, &phy_data) < 0) {
4492 DEBUGOUT("PHY Read Error\n");
4493 return -E1000_ERR_PHY;
4495 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
4497 else if(hw->phy_type == em_phy_m88) {
4498 if(em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
4499 DEBUGOUT("PHY Read Error\n");
4500 return -E1000_ERR_PHY;
4502 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4503 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4505 return E1000_SUCCESS;