2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
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9 * modification, are permitted provided that the following conditions
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17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
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20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
37 * $FreeBSD: src/sys/i386/isa/isa_dma.c,v 1.4.2.1 2000/08/08 19:49:53 peter Exp $
41 * code to manage AT bus
43 * 92/08/18 Frank P. MacLachlan (fpm@crash.cts.com):
44 * Fixed uninitialized variable problem and added code to deal
45 * with DMA page boundaries in isa_dmarangecheck(). Fixed word
46 * mode DMA count compution and reorganized DMA setup code in
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/kernel.h>
54 #include <sys/malloc.h>
57 #include <vm/vm_param.h>
60 #include <machine_base/isa/ic/i8237.h>
61 #include <machine/pmap.h>
62 #include <bus/isa/isavar.h>
65 ** Register definitions for DMA controller 1 (channels 0..3):
67 #define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
68 #define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
69 #define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
70 #define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
73 ** Register definitions for DMA controller 2 (channels 4..7):
75 #define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
76 #define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
77 #define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
78 #define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
80 static int isa_dmarangecheck (caddr_t va, u_int length, int chan);
82 static caddr_t dma_bouncebuf[8];
83 static u_int dma_bouncebufsize[8];
84 static u_int8_t dma_bounced = 0;
85 static u_int8_t dma_busy = 0; /* Used in isa_dmastart() */
86 static u_int8_t dma_inuse = 0; /* User for acquire/release */
87 static u_int8_t dma_auto_mode = 0;
89 #define VALID_DMA_MASK (7)
91 /* high byte of address is stored in this port for i-th dma channel */
92 static int dmapageport[8] = { 0x87, 0x83, 0x81, 0x82, 0x8f, 0x8b, 0x89, 0x8a };
95 * Setup a DMA channel's bounce buffer.
98 isa_dmainit(int chan, u_int bouncebufsize)
103 if (chan & ~VALID_DMA_MASK)
104 panic("isa_dmainit: channel out of range");
106 if (dma_bouncebuf[chan] != NULL)
107 panic("isa_dmainit: impossible request");
110 dma_bouncebufsize[chan] = bouncebufsize;
112 /* Try malloc() first. It works better if it works. */
113 buf = kmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT);
115 if (isa_dmarangecheck(buf, bouncebufsize, chan) == 0) {
116 dma_bouncebuf[chan] = buf;
119 kfree(buf, M_DEVBUF);
121 buf = contigmalloc(bouncebufsize, M_DEVBUF, M_NOWAIT, 0ul, 0xfffffful,
122 1ul, chan & 4 ? 0x20000ul : 0x10000ul);
124 kprintf("isa_dmainit(%d, %d) failed\n", chan, bouncebufsize);
126 dma_bouncebuf[chan] = buf;
130 * Register a DMA channel's usage. Usually called from a device driver
131 * in open() or during its initialization.
134 isa_dma_acquire(int chan)
137 if (chan & ~VALID_DMA_MASK)
138 panic("isa_dma_acquire: channel out of range");
141 if (dma_inuse & (1 << chan)) {
142 kprintf("isa_dma_acquire: channel %d already in use\n", chan);
145 dma_inuse |= (1 << chan);
146 dma_auto_mode &= ~(1 << chan);
152 * Unregister a DMA channel's usage. Usually called from a device driver
153 * during close() or during its shutdown.
156 isa_dma_release(int chan)
159 if (chan & ~VALID_DMA_MASK)
160 panic("isa_dma_release: channel out of range");
162 if ((dma_inuse & (1 << chan)) == 0)
163 kprintf("isa_dma_release: channel %d not in use\n", chan);
166 if (dma_busy & (1 << chan)) {
167 dma_busy &= ~(1 << chan);
169 * XXX We should also do "dma_bounced &= (1 << chan);"
170 * because we are acting on behalf of isa_dmadone() which
171 * was not called to end the last DMA operation. This does
172 * not matter now, but it may in the future.
176 dma_inuse &= ~(1 << chan);
177 dma_auto_mode &= ~(1 << chan);
181 * isa_dmacascade(): program 8237 DMA controller channel to accept
182 * external dma control by a board.
185 isa_dmacascade(int chan)
188 if (chan & ~VALID_DMA_MASK)
189 panic("isa_dmacascade: channel out of range");
192 /* set dma channel mode, and set dma channel mode */
193 if ((chan & 4) == 0) {
194 outb(DMA1_MODE, DMA37MD_CASCADE | chan);
195 outb(DMA1_SMSK, chan);
197 outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));
198 outb(DMA2_SMSK, chan & 3);
203 * isa_dmastart(): program 8237 DMA controller channel, avoid page alignment
204 * problems by using a bounce buffer.
207 isa_dmastart(int flags, caddr_t addr, u_int nbytes, int chan)
214 if (chan & ~VALID_DMA_MASK)
215 panic("isa_dmastart: channel out of range");
217 if ((chan < 4 && nbytes > (1<<16))
218 || (chan >= 4 && (nbytes > (1<<17) || (u_int)(uintptr_t)addr & 1)))
219 panic("isa_dmastart: impossible request");
221 if ((dma_inuse & (1 << chan)) == 0)
222 kprintf("isa_dmastart: channel %d not acquired\n", chan);
227 * XXX This should be checked, but drivers like ad1848 only call
228 * isa_dmastart() once because they use Auto DMA mode. If we
229 * leave this in, drivers that do this will print this continuously.
231 if (dma_busy & (1 << chan))
232 kprintf("isa_dmastart: channel %d busy\n", chan);
235 dma_busy |= (1 << chan);
237 if (isa_dmarangecheck(addr, nbytes, chan)) {
238 if (dma_bouncebuf[chan] == NULL
239 || dma_bouncebufsize[chan] < nbytes)
240 panic("isa_dmastart: bad bounce buffer");
241 dma_bounced |= (1 << chan);
242 newaddr = dma_bouncebuf[chan];
244 /* copy bounce buffer on write */
245 if (flags & ISADMA_WRITE)
246 bcopy(addr, newaddr, nbytes);
250 /* translate to physical */
251 phys = pmap_extract(&kernel_pmap, (vm_offset_t)addr);
253 if (flags & ISADMA_RAW) {
254 dma_auto_mode |= (1 << chan);
256 dma_auto_mode &= ~(1 << chan);
259 if ((chan & 4) == 0) {
261 * Program one of DMA channels 0..3. These are
262 * byte mode channels.
264 /* set dma channel mode, and reset address ff */
266 /* If ISADMA_RAW flag is set, then use autoinitialise mode */
267 if (flags & ISADMA_RAW) {
268 if (flags & ISADMA_READ)
269 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan);
271 outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan);
274 if (flags & ISADMA_READ)
275 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);
277 outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);
280 /* send start address */
281 waport = DMA1_CHN(chan);
283 outb(waport, phys>>8);
284 outb(dmapageport[chan], phys>>16);
287 outb(waport + 1, --nbytes);
288 outb(waport + 1, nbytes>>8);
291 outb(DMA1_SMSK, chan);
294 * Program one of DMA channels 4..7. These are
295 * word mode channels.
297 /* set dma channel mode, and reset address ff */
299 /* If ISADMA_RAW flag is set, then use autoinitialise mode */
300 if (flags & ISADMA_RAW) {
301 if (flags & ISADMA_READ)
302 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3));
304 outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3));
307 if (flags & ISADMA_READ)
308 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));
310 outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));
313 /* send start address */
314 waport = DMA2_CHN(chan - 4);
315 outb(waport, phys>>1);
316 outb(waport, phys>>9);
317 outb(dmapageport[chan], phys>>16);
321 outb(waport + 2, --nbytes);
322 outb(waport + 2, nbytes>>8);
325 outb(DMA2_SMSK, chan & 3);
330 isa_dmadone(int flags, caddr_t addr, int nbytes, int chan)
333 if (chan & ~VALID_DMA_MASK)
334 panic("isa_dmadone: channel out of range");
336 if ((dma_inuse & (1 << chan)) == 0)
337 kprintf("isa_dmadone: channel %d not acquired\n", chan);
340 if (((dma_busy & (1 << chan)) == 0) &&
341 (dma_auto_mode & (1 << chan)) == 0 )
342 kprintf("isa_dmadone: channel %d not busy\n", chan);
344 if ((dma_auto_mode & (1 << chan)) == 0)
345 outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4);
347 if (dma_bounced & (1 << chan)) {
348 /* copy bounce buffer on read */
349 if (flags & ISADMA_READ)
350 bcopy(dma_bouncebuf[chan], addr, nbytes);
352 dma_bounced &= ~(1 << chan);
354 dma_busy &= ~(1 << chan);
358 * Check for problems with the address range of a DMA transfer
359 * (non-contiguous physical pages, outside of bus address space,
360 * crossing DMA page boundaries).
361 * Return true if special handling needed.
365 isa_dmarangecheck(caddr_t va, u_int length, int chan)
367 vm_paddr_t phys, priorpage = 0;
369 u_int dma_pgmsk = (chan & 4) ? ~(128*1024-1) : ~(64*1024-1);
371 endva = (vm_offset_t)round_page((vm_offset_t)va + length);
372 for (; va < (caddr_t) endva ; va += PAGE_SIZE) {
373 phys = trunc_page(pmap_extract(&kernel_pmap, (vm_offset_t)va));
374 #define ISARAM_END RAM_END
376 panic("isa_dmacheck: no physical page present");
377 if (phys >= ISARAM_END)
380 if (priorpage + PAGE_SIZE != phys)
382 /* check if crossing a DMA page boundary */
383 if (((u_int)priorpage ^ (u_int)phys) & dma_pgmsk)
392 * Query the progress of a transfer on a DMA channel.
394 * To avoid having to interrupt a transfer in progress, we sample
395 * each of the high and low databytes twice, and apply the following
396 * logic to determine the correct count.
398 * Reads are performed with interrupts disabled, thus it is to be
399 * expected that the time between reads is very small. At most
400 * one rollover in the low count byte can be expected within the
401 * four reads that are performed.
403 * There are three gaps in which a rollover can occur :
413 * If a rollover occurs in gap1 or gap2, the low2 value will be
414 * greater than the low1 value. In this case, low2 and high2 are a
415 * corresponding pair.
417 * In any other case, low1 and high1 can be considered to be correct.
419 * The function returns the number of bytes remaining in the transfer,
420 * or -1 if the channel requested is not active.
424 isa_dmastatus(int chan)
428 u_long low1, high1, low2, high2;
430 /* channel active? */
431 if ((dma_inuse & (1 << chan)) == 0) {
432 kprintf("isa_dmastatus: channel %d not active\n", chan);
437 if (((dma_busy & (1 << chan)) == 0) &&
438 (dma_auto_mode & (1 << chan)) == 0 ) {
439 kprintf("chan %d not busy\n", chan);
442 if (chan < 4) { /* low DMA controller */
444 waport = DMA1_CHN(chan) + 1;
445 } else { /* high DMA controller */
447 waport = DMA2_CHN(chan - 4) + 2;
450 cpu_disable_intr(); /* YYY *//* no interrupts Mr Jones! */
451 outb(ffport, 0); /* clear register LSB flipflop */
454 outb(ffport, 0); /* clear again */
457 cpu_enable_intr(); /* enable interrupts again */
460 * Now decide if a wrap has tried to skew our results.
461 * Note that after TC, the count will read 0xffff, while we want
462 * to return zero, so we add and then mask to compensate.
465 cnt = (low1 + (high1 << 8) + 1) & 0xffff;
467 cnt = (low2 + (high2 << 8) + 1) & 0xffff;
470 if (chan >= 4) /* high channels move words */
476 * Stop a DMA transfer currently in progress.
479 isa_dmastop(int chan)
481 if ((dma_inuse & (1 << chan)) == 0)
482 kprintf("isa_dmastop: channel %d not acquired\n", chan);
484 if (((dma_busy & (1 << chan)) == 0) &&
485 ((dma_auto_mode & (1 << chan)) == 0)) {
486 kprintf("chan %d not busy\n", chan);
490 if ((chan & 4) == 0) {
491 outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */);
493 outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */);
495 return(isa_dmastatus(chan));
499 isa_dmabp(struct buf *bp)
503 KKASSERT(bp->b_cmd != BUF_CMD_DONE);
504 if (bp->b_flags & B_RAW)
506 if (bp->b_cmd == BUF_CMD_READ) {
507 flags |= ISADMA_READ;
509 /* BUF_CMD_WRITE, BUF_CMD_FORMAT */
510 flags |= ISADMA_WRITE;