Merge branch 'vendor/GCC47'
[dragonfly.git] / contrib / gcc-4.7 / gcc / config / i386 / i386.md
CommitLineData
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1;; GCC machine description for IA-32 and x86-64.
2;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4;; Free Software Foundation, Inc.
5;; Mostly by William Schelter.
6;; x86_64 support added by Jan Hubicka
7;;
8;; This file is part of GCC.
9;;
10;; GCC is free software; you can redistribute it and/or modify
11;; it under the terms of the GNU General Public License as published by
12;; the Free Software Foundation; either version 3, or (at your option)
13;; any later version.
14;;
15;; GCC is distributed in the hope that it will be useful,
16;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18;; GNU General Public License for more details.
19;;
20;; You should have received a copy of the GNU General Public License
21;; along with GCC; see the file COPYING3. If not see
22;; <http://www.gnu.org/licenses/>. */
23;;
24;; The original PO technology requires these to be ordered by speed,
25;; so that assigner will pick the fastest.
26;;
27;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
28;;
29;; The special asm out single letter directives following a '%' are:
30;; L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
31;; C -- print opcode suffix for set/cmov insn.
32;; c -- like C, but print reversed condition
33;; F,f -- likewise, but for floating-point.
34;; O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
35;; otherwise nothing
36;; R -- print the prefix for register names.
37;; z -- print the opcode suffix for the size of the current operand.
38;; Z -- likewise, with special suffixes for x87 instructions.
39;; * -- print a star (in certain assembler syntax)
40;; A -- print an absolute memory reference.
41;; E -- print address with DImode register names if TARGET_64BIT.
42;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
43;; s -- print a shift double count, followed by the assemblers argument
44;; delimiter.
45;; b -- print the QImode name of the register for the indicated operand.
46;; %b0 would print %al if operands[0] is reg 0.
47;; w -- likewise, print the HImode name of the register.
48;; k -- likewise, print the SImode name of the register.
49;; q -- likewise, print the DImode name of the register.
50;; x -- likewise, print the V4SFmode name of the register.
51;; t -- likewise, print the V8SFmode name of the register.
52;; h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
53;; y -- print "st(0)" instead of "st" as a register.
54;; d -- print duplicated register operand for AVX instruction.
55;; D -- print condition for SSE cmp instruction.
56;; P -- if PIC, print an @PLT suffix.
57;; p -- print raw symbol name.
58;; X -- don't print any sort of PIC '@' suffix for a symbol.
59;; & -- print some in-use local-dynamic symbol name.
60;; H -- print a memory address offset by 8; used for sse high-parts
61;; Y -- print condition for XOP pcom* instruction.
62;; + -- print a branch hint as 'cs' or 'ds' prefix
63;; ; -- print a semicolon (after prefixes due to bug in older gas).
64;; @ -- print a segment register of thread base pointer load
65
66(define_c_enum "unspec" [
67 ;; Relocation specifiers
68 UNSPEC_GOT
69 UNSPEC_GOTOFF
70 UNSPEC_GOTPCREL
71 UNSPEC_GOTTPOFF
72 UNSPEC_TPOFF
73 UNSPEC_NTPOFF
74 UNSPEC_DTPOFF
75 UNSPEC_GOTNTPOFF
76 UNSPEC_INDNTPOFF
77 UNSPEC_PLTOFF
78 UNSPEC_MACHOPIC_OFFSET
79 UNSPEC_PCREL
80
81 ;; Prologue support
82 UNSPEC_STACK_ALLOC
83 UNSPEC_SET_GOT
84 UNSPEC_SET_RIP
85 UNSPEC_SET_GOT_OFFSET
86 UNSPEC_MEMORY_BLOCKAGE
87 UNSPEC_STACK_CHECK
88
89 ;; TLS support
90 UNSPEC_TP
91 UNSPEC_TLS_GD
92 UNSPEC_TLS_LD_BASE
93 UNSPEC_TLSDESC
94 UNSPEC_TLS_IE_SUN
95
96 ;; Other random patterns
97 UNSPEC_SCAS
98 UNSPEC_FNSTSW
99 UNSPEC_SAHF
100 UNSPEC_PARITY
101 UNSPEC_FSTCW
102 UNSPEC_ADD_CARRY
103 UNSPEC_FLDCW
104 UNSPEC_REP
105 UNSPEC_LD_MPIC ; load_macho_picbase
106 UNSPEC_TRUNC_NOOP
107 UNSPEC_DIV_ALREADY_SPLIT
108 UNSPEC_MS_TO_SYSV_CALL
109 UNSPEC_CALL_NEEDS_VZEROUPPER
110 UNSPEC_PAUSE
111 UNSPEC_LEA_ADDR
95d28233 112 UNSPEC_STOS
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113
114 ;; For SSE/MMX support:
115 UNSPEC_FIX_NOTRUNC
116 UNSPEC_MASKMOV
117 UNSPEC_MOVMSK
118 UNSPEC_RCP
119 UNSPEC_RSQRT
120 UNSPEC_PSADBW
121
122 ;; Generic math support
123 UNSPEC_COPYSIGN
124 UNSPEC_IEEE_MIN ; not commutative
125 UNSPEC_IEEE_MAX ; not commutative
126
127 ;; x87 Floating point
128 UNSPEC_SIN
129 UNSPEC_COS
130 UNSPEC_FPATAN
131 UNSPEC_FYL2X
132 UNSPEC_FYL2XP1
133 UNSPEC_FRNDINT
134 UNSPEC_FIST
135 UNSPEC_F2XM1
136 UNSPEC_TAN
137 UNSPEC_FXAM
138
139 ;; x87 Rounding
140 UNSPEC_FRNDINT_FLOOR
141 UNSPEC_FRNDINT_CEIL
142 UNSPEC_FRNDINT_TRUNC
143 UNSPEC_FRNDINT_MASK_PM
144 UNSPEC_FIST_FLOOR
145 UNSPEC_FIST_CEIL
146
147 ;; x87 Double output FP
148 UNSPEC_SINCOS_COS
149 UNSPEC_SINCOS_SIN
150 UNSPEC_XTRACT_FRACT
151 UNSPEC_XTRACT_EXP
152 UNSPEC_FSCALE_FRACT
153 UNSPEC_FSCALE_EXP
154 UNSPEC_FPREM_F
155 UNSPEC_FPREM_U
156 UNSPEC_FPREM1_F
157 UNSPEC_FPREM1_U
158
159 UNSPEC_C2_FLAG
160 UNSPEC_FXAM_MEM
161
162 ;; SSP patterns
163 UNSPEC_SP_SET
164 UNSPEC_SP_TEST
165 UNSPEC_SP_TLS_SET
166 UNSPEC_SP_TLS_TEST
167
168 ;; For ROUND support
169 UNSPEC_ROUND
170
171 ;; For CRC32 support
172 UNSPEC_CRC32
173
174 ;; For BMI support
175 UNSPEC_BEXTR
176
177 ;; For BMI2 support
178 UNSPEC_PDEP
179 UNSPEC_PEXT
180])
181
182(define_c_enum "unspecv" [
183 UNSPECV_BLOCKAGE
184 UNSPECV_STACK_PROBE
185 UNSPECV_PROBE_STACK_RANGE
186 UNSPECV_ALIGN
187 UNSPECV_PROLOGUE_USE
188 UNSPECV_SPLIT_STACK_RETURN
189 UNSPECV_CLD
190 UNSPECV_NOPS
191 UNSPECV_RDTSC
192 UNSPECV_RDTSCP
193 UNSPECV_RDPMC
194 UNSPECV_LLWP_INTRINSIC
195 UNSPECV_SLWP_INTRINSIC
196 UNSPECV_LWPVAL_INTRINSIC
197 UNSPECV_LWPINS_INTRINSIC
198 UNSPECV_RDFSBASE
199 UNSPECV_RDGSBASE
200 UNSPECV_WRFSBASE
201 UNSPECV_WRGSBASE
202
203 ;; For RDRAND support
204 UNSPECV_RDRAND
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205
206 ;; Non-local goto.
207 UNSPECV_NLGR
208 ])
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209
210;; Constants to represent rounding modes in the ROUND instruction
211(define_constants
212 [(ROUND_FLOOR 0x1)
213 (ROUND_CEIL 0x2)
214 (ROUND_TRUNC 0x3)
215 (ROUND_MXCSR 0x4)
216 (ROUND_NO_EXC 0x8)
217 ])
218
219;; Constants to represent pcomtrue/pcomfalse variants
220(define_constants
221 [(PCOM_FALSE 0)
222 (PCOM_TRUE 1)
223 (COM_FALSE_S 2)
224 (COM_FALSE_P 3)
225 (COM_TRUE_S 4)
226 (COM_TRUE_P 5)
227 ])
228
229;; Constants used in the XOP pperm instruction
230(define_constants
231 [(PPERM_SRC 0x00) /* copy source */
232 (PPERM_INVERT 0x20) /* invert source */
233 (PPERM_REVERSE 0x40) /* bit reverse source */
234 (PPERM_REV_INV 0x60) /* bit reverse & invert src */
235 (PPERM_ZERO 0x80) /* all 0's */
236 (PPERM_ONES 0xa0) /* all 1's */
237 (PPERM_SIGN 0xc0) /* propagate sign bit */
238 (PPERM_INV_SIGN 0xe0) /* invert & propagate sign */
239 (PPERM_SRC1 0x00) /* use first source byte */
240 (PPERM_SRC2 0x10) /* use second source byte */
241 ])
242
243;; Registers by name.
244(define_constants
245 [(AX_REG 0)
246 (DX_REG 1)
247 (CX_REG 2)
248 (BX_REG 3)
249 (SI_REG 4)
250 (DI_REG 5)
251 (BP_REG 6)
252 (SP_REG 7)
253 (ST0_REG 8)
254 (ST1_REG 9)
255 (ST2_REG 10)
256 (ST3_REG 11)
257 (ST4_REG 12)
258 (ST5_REG 13)
259 (ST6_REG 14)
260 (ST7_REG 15)
261 (FLAGS_REG 17)
262 (FPSR_REG 18)
263 (FPCR_REG 19)
264 (XMM0_REG 21)
265 (XMM1_REG 22)
266 (XMM2_REG 23)
267 (XMM3_REG 24)
268 (XMM4_REG 25)
269 (XMM5_REG 26)
270 (XMM6_REG 27)
271 (XMM7_REG 28)
272 (MM0_REG 29)
273 (MM1_REG 30)
274 (MM2_REG 31)
275 (MM3_REG 32)
276 (MM4_REG 33)
277 (MM5_REG 34)
278 (MM6_REG 35)
279 (MM7_REG 36)
280 (R8_REG 37)
281 (R9_REG 38)
282 (R10_REG 39)
283 (R11_REG 40)
284 (R12_REG 41)
285 (R13_REG 42)
286 (XMM8_REG 45)
287 (XMM9_REG 46)
288 (XMM10_REG 47)
289 (XMM11_REG 48)
290 (XMM12_REG 49)
291 (XMM13_REG 50)
292 (XMM14_REG 51)
293 (XMM15_REG 52)
294 ])
295
296;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
297;; from i386.c.
298
299;; In C guard expressions, put expressions which may be compile-time
300;; constants first. This allows for better optimization. For
301;; example, write "TARGET_64BIT && reload_completed", not
302;; "reload_completed && TARGET_64BIT".
303
304\f
305;; Processor type.
306(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7,
307 atom,generic64,amdfam10,bdver1,bdver2,btver1"
308 (const (symbol_ref "ix86_schedule")))
309
310;; A basic instruction type. Refinements due to arguments to be
311;; provided in other attributes.
312(define_attr "type"
313 "other,multi,
314 alu,alu1,negnot,imov,imovx,lea,
315 incdec,ishift,ishiftx,ishift1,rotate,rotatex,rotate1,imul,imulx,idiv,
316 icmp,test,ibr,setcc,icmov,
317 push,pop,call,callv,leave,
318 str,bitmanip,
319 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
320 sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,
321 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins,
322 ssemuladd,sse4arg,lwp,
323 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
324 (const_string "other"))
325
326;; Main data type used by the insn
327(define_attr "mode"
328 "unknown,none,QI,HI,SI,DI,TI,OI,SF,DF,XF,TF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF"
329 (const_string "unknown"))
330
331;; The CPU unit operations uses.
332(define_attr "unit" "integer,i387,sse,mmx,unknown"
333 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")
334 (const_string "i387")
335 (eq_attr "type" "sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,
336 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,
337 ssecvt1,sseicvt,ssediv,sseins,ssemuladd,sse4arg")
338 (const_string "sse")
339 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
340 (const_string "mmx")
341 (eq_attr "type" "other")
342 (const_string "unknown")]
343 (const_string "integer")))
344
345;; The (bounding maximum) length of an instruction immediate.
346(define_attr "length_immediate" ""
347 (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
348 bitmanip,imulx")
349 (const_int 0)
350 (eq_attr "unit" "i387,sse,mmx")
351 (const_int 0)
352 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,ishiftx,ishift1,
353 rotate,rotatex,rotate1,imul,icmp,push,pop")
354 (symbol_ref "ix86_attr_length_immediate_default (insn, true)")
355 (eq_attr "type" "imov,test")
356 (symbol_ref "ix86_attr_length_immediate_default (insn, false)")
357 (eq_attr "type" "call")
358 (if_then_else (match_operand 0 "constant_call_address_operand" "")
359 (const_int 4)
360 (const_int 0))
361 (eq_attr "type" "callv")
362 (if_then_else (match_operand 1 "constant_call_address_operand" "")
363 (const_int 4)
364 (const_int 0))
365 ;; We don't know the size before shorten_branches. Expect
366 ;; the instruction to fit for better scheduling.
367 (eq_attr "type" "ibr")
368 (const_int 1)
369 ]
370 (symbol_ref "/* Update immediate_length and other attributes! */
371 gcc_unreachable (),1")))
372
373;; The (bounding maximum) length of an instruction address.
374(define_attr "length_address" ""
375 (cond [(eq_attr "type" "str,other,multi,fxch")
376 (const_int 0)
377 (and (eq_attr "type" "call")
378 (match_operand 0 "constant_call_address_operand" ""))
379 (const_int 0)
380 (and (eq_attr "type" "callv")
381 (match_operand 1 "constant_call_address_operand" ""))
382 (const_int 0)
383 ]
384 (symbol_ref "ix86_attr_length_address_default (insn)")))
385
386;; Set when length prefix is used.
387(define_attr "prefix_data16" ""
388 (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
389 (const_int 0)
390 (eq_attr "mode" "HI")
391 (const_int 1)
392 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI"))
393 (const_int 1)
394 ]
395 (const_int 0)))
396
397;; Set when string REP prefix is used.
398(define_attr "prefix_rep" ""
399 (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
400 (const_int 0)
401 (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
402 (const_int 1)
403 ]
404 (const_int 0)))
405
406;; Set when 0f opcode prefix is used.
407(define_attr "prefix_0f" ""
408 (if_then_else
409 (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip")
410 (eq_attr "unit" "sse,mmx"))
411 (const_int 1)
412 (const_int 0)))
413
414;; Set when REX opcode prefix is used.
415(define_attr "prefix_rex" ""
416 (cond [(not (match_test "TARGET_64BIT"))
417 (const_int 0)
418 (and (eq_attr "mode" "DI")
419 (and (eq_attr "type" "!push,pop,call,callv,leave,ibr")
420 (eq_attr "unit" "!mmx")))
421 (const_int 1)
422 (and (eq_attr "mode" "QI")
423 (match_test "x86_extended_QIreg_mentioned_p (insn)"))
424 (const_int 1)
425 (match_test "x86_extended_reg_mentioned_p (insn)")
426 (const_int 1)
427 (and (eq_attr "type" "imovx")
428 (match_operand:QI 1 "ext_QIreg_operand" ""))
429 (const_int 1)
430 ]
431 (const_int 0)))
432
433;; There are also additional prefixes in 3DNOW, SSSE3.
434;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
435;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
436;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
437(define_attr "prefix_extra" ""
438 (cond [(eq_attr "type" "ssemuladd,sse4arg")
439 (const_int 2)
440 (eq_attr "type" "sseiadd1,ssecvt1")
441 (const_int 1)
442 ]
443 (const_int 0)))
444
445;; Prefix used: original, VEX or maybe VEX.
446(define_attr "prefix" "orig,vex,maybe_vex"
447 (if_then_else (eq_attr "mode" "OI,V8SF,V4DF")
448 (const_string "vex")
449 (const_string "orig")))
450
451;; VEX W bit is used.
452(define_attr "prefix_vex_w" "" (const_int 0))
453
454;; The length of VEX prefix
455;; Only instructions with 0f prefix can have 2 byte VEX prefix,
456;; 0f38/0f3a prefixes can't. In i386.md 0f3[8a] is
457;; still prefix_0f 1, with prefix_extra 1.
458(define_attr "length_vex" ""
459 (if_then_else (and (eq_attr "prefix_0f" "1")
460 (eq_attr "prefix_extra" "0"))
461 (if_then_else (eq_attr "prefix_vex_w" "1")
462 (symbol_ref "ix86_attr_length_vex_default (insn, true, true)")
463 (symbol_ref "ix86_attr_length_vex_default (insn, true, false)"))
464 (if_then_else (eq_attr "prefix_vex_w" "1")
465 (symbol_ref "ix86_attr_length_vex_default (insn, false, true)")
466 (symbol_ref "ix86_attr_length_vex_default (insn, false, false)"))))
467
468;; Set when modrm byte is used.
469(define_attr "modrm" ""
470 (cond [(eq_attr "type" "str,leave")
471 (const_int 0)
472 (eq_attr "unit" "i387")
473 (const_int 0)
474 (and (eq_attr "type" "incdec")
475 (and (not (match_test "TARGET_64BIT"))
476 (ior (match_operand:SI 1 "register_operand" "")
477 (match_operand:HI 1 "register_operand" ""))))
478 (const_int 0)
479 (and (eq_attr "type" "push")
480 (not (match_operand 1 "memory_operand" "")))
481 (const_int 0)
482 (and (eq_attr "type" "pop")
483 (not (match_operand 0 "memory_operand" "")))
484 (const_int 0)
485 (and (eq_attr "type" "imov")
486 (and (not (eq_attr "mode" "DI"))
487 (ior (and (match_operand 0 "register_operand" "")
488 (match_operand 1 "immediate_operand" ""))
489 (ior (and (match_operand 0 "ax_reg_operand" "")
490 (match_operand 1 "memory_displacement_only_operand" ""))
491 (and (match_operand 0 "memory_displacement_only_operand" "")
492 (match_operand 1 "ax_reg_operand" ""))))))
493 (const_int 0)
494 (and (eq_attr "type" "call")
495 (match_operand 0 "constant_call_address_operand" ""))
496 (const_int 0)
497 (and (eq_attr "type" "callv")
498 (match_operand 1 "constant_call_address_operand" ""))
499 (const_int 0)
500 (and (eq_attr "type" "alu,alu1,icmp,test")
501 (match_operand 0 "ax_reg_operand" ""))
502 (symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))")
503 ]
504 (const_int 1)))
505
506;; The (bounding maximum) length of an instruction in bytes.
507;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
508;; Later we may want to split them and compute proper length as for
509;; other insns.
510(define_attr "length" ""
511 (cond [(eq_attr "type" "other,multi,fistp,frndint")
512 (const_int 16)
513 (eq_attr "type" "fcmp")
514 (const_int 4)
515 (eq_attr "unit" "i387")
516 (plus (const_int 2)
517 (plus (attr "prefix_data16")
518 (attr "length_address")))
519 (ior (eq_attr "prefix" "vex")
520 (and (eq_attr "prefix" "maybe_vex")
521 (match_test "TARGET_AVX")))
522 (plus (attr "length_vex")
523 (plus (attr "length_immediate")
524 (plus (attr "modrm")
525 (attr "length_address"))))]
526 (plus (plus (attr "modrm")
527 (plus (attr "prefix_0f")
528 (plus (attr "prefix_rex")
529 (plus (attr "prefix_extra")
530 (const_int 1)))))
531 (plus (attr "prefix_rep")
532 (plus (attr "prefix_data16")
533 (plus (attr "length_immediate")
534 (attr "length_address")))))))
535
536;; The `memory' attribute is `none' if no memory is referenced, `load' or
537;; `store' if there is a simple memory reference therein, or `unknown'
538;; if the instruction is complex.
539
540(define_attr "memory" "none,load,store,both,unknown"
541 (cond [(eq_attr "type" "other,multi,str,lwp")
542 (const_string "unknown")
543 (eq_attr "type" "lea,fcmov,fpspc")
544 (const_string "none")
545 (eq_attr "type" "fistp,leave")
546 (const_string "both")
547 (eq_attr "type" "frndint")
548 (const_string "load")
549 (eq_attr "type" "push")
550 (if_then_else (match_operand 1 "memory_operand" "")
551 (const_string "both")
552 (const_string "store"))
553 (eq_attr "type" "pop")
554 (if_then_else (match_operand 0 "memory_operand" "")
555 (const_string "both")
556 (const_string "load"))
557 (eq_attr "type" "setcc")
558 (if_then_else (match_operand 0 "memory_operand" "")
559 (const_string "store")
560 (const_string "none"))
561 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
562 (if_then_else (ior (match_operand 0 "memory_operand" "")
563 (match_operand 1 "memory_operand" ""))
564 (const_string "load")
565 (const_string "none"))
566 (eq_attr "type" "ibr")
567 (if_then_else (match_operand 0 "memory_operand" "")
568 (const_string "load")
569 (const_string "none"))
570 (eq_attr "type" "call")
571 (if_then_else (match_operand 0 "constant_call_address_operand" "")
572 (const_string "none")
573 (const_string "load"))
574 (eq_attr "type" "callv")
575 (if_then_else (match_operand 1 "constant_call_address_operand" "")
576 (const_string "none")
577 (const_string "load"))
578 (and (eq_attr "type" "alu1,negnot,ishift1,sselog1")
579 (match_operand 1 "memory_operand" ""))
580 (const_string "both")
581 (and (match_operand 0 "memory_operand" "")
582 (match_operand 1 "memory_operand" ""))
583 (const_string "both")
584 (match_operand 0 "memory_operand" "")
585 (const_string "store")
586 (match_operand 1 "memory_operand" "")
587 (const_string "load")
588 (and (eq_attr "type"
589 "!alu1,negnot,ishift1,
590 imov,imovx,icmp,test,bitmanip,
591 fmov,fcmp,fsgn,
592 sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1,
593 sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt")
594 (match_operand 2 "memory_operand" ""))
595 (const_string "load")
596 (and (eq_attr "type" "icmov,ssemuladd,sse4arg")
597 (match_operand 3 "memory_operand" ""))
598 (const_string "load")
599 ]
600 (const_string "none")))
601
602;; Indicates if an instruction has both an immediate and a displacement.
603
604(define_attr "imm_disp" "false,true,unknown"
605 (cond [(eq_attr "type" "other,multi")
606 (const_string "unknown")
607 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
608 (and (match_operand 0 "memory_displacement_operand" "")
609 (match_operand 1 "immediate_operand" "")))
610 (const_string "true")
611 (and (eq_attr "type" "alu,ishift,ishiftx,rotate,rotatex,imul,idiv")
612 (and (match_operand 0 "memory_displacement_operand" "")
613 (match_operand 2 "immediate_operand" "")))
614 (const_string "true")
615 ]
616 (const_string "false")))
617
618;; Indicates if an FP operation has an integer source.
619
620(define_attr "fp_int_src" "false,true"
621 (const_string "false"))
622
623;; Defines rounding mode of an FP operation.
624
625(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
626 (const_string "any"))
627
628;; Define attribute to classify add/sub insns that consumes carry flag (CF)
629(define_attr "use_carry" "0,1" (const_string "0"))
630
631;; Define attribute to indicate unaligned ssemov insns
632(define_attr "movu" "0,1" (const_string "0"))
633
634;; Used to control the "enabled" attribute on a per-instruction basis.
635(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,
5ce9237c 636 bmi2,fma4,fma"
e4b17023
JM
637 (const_string "base"))
638
639(define_attr "enabled" ""
640 (cond [(eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2")
641 (eq_attr "isa" "sse2_noavx")
642 (symbol_ref "TARGET_SSE2 && !TARGET_AVX")
643 (eq_attr "isa" "sse3") (symbol_ref "TARGET_SSE3")
644 (eq_attr "isa" "sse4") (symbol_ref "TARGET_SSE4_1")
645 (eq_attr "isa" "sse4_noavx")
646 (symbol_ref "TARGET_SSE4_1 && !TARGET_AVX")
647 (eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
648 (eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
649 (eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
5ce9237c 650 (eq_attr "isa" "fma4") (symbol_ref "TARGET_FMA4")
e4b17023 651 (eq_attr "isa" "fma") (symbol_ref "TARGET_FMA")
e4b17023
JM
652 ]
653 (const_int 1)))
654
655;; Describe a user's asm statement.
656(define_asm_attributes
657 [(set_attr "length" "128")
658 (set_attr "type" "multi")])
659
660(define_code_iterator plusminus [plus minus])
661
662(define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus])
663
664;; Base name for define_insn
665(define_code_attr plusminus_insn
666 [(plus "add") (ss_plus "ssadd") (us_plus "usadd")
667 (minus "sub") (ss_minus "sssub") (us_minus "ussub")])
668
669;; Base name for insn mnemonic.
670(define_code_attr plusminus_mnemonic
671 [(plus "add") (ss_plus "adds") (us_plus "addus")
672 (minus "sub") (ss_minus "subs") (us_minus "subus")])
673(define_code_attr plusminus_carry_mnemonic
674 [(plus "adc") (minus "sbb")])
675
676;; Mark commutative operators as such in constraints.
677(define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%")
678 (minus "") (ss_minus "") (us_minus "")])
679
680;; Mapping of max and min
681(define_code_iterator maxmin [smax smin umax umin])
682
683;; Mapping of signed max and min
684(define_code_iterator smaxmin [smax smin])
685
686;; Mapping of unsigned max and min
687(define_code_iterator umaxmin [umax umin])
688
689;; Base name for integer and FP insn mnemonic
690(define_code_attr maxmin_int [(smax "maxs") (smin "mins")
691 (umax "maxu") (umin "minu")])
692(define_code_attr maxmin_float [(smax "max") (smin "min")])
693
694;; Mapping of logic operators
695(define_code_iterator any_logic [and ior xor])
696(define_code_iterator any_or [ior xor])
697
698;; Base name for insn mnemonic.
699(define_code_attr logic [(and "and") (ior "or") (xor "xor")])
700
701;; Mapping of logic-shift operators
702(define_code_iterator any_lshift [ashift lshiftrt])
703
704;; Mapping of shift-right operators
705(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
706
707;; Base name for define_insn
708(define_code_attr shift_insn
709 [(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")])
710
711;; Base name for insn mnemonic.
712(define_code_attr shift [(ashift "sll") (lshiftrt "shr") (ashiftrt "sar")])
713(define_code_attr vshift [(ashift "sll") (lshiftrt "srl") (ashiftrt "sra")])
714
715;; Mapping of rotate operators
716(define_code_iterator any_rotate [rotate rotatert])
717
718;; Base name for define_insn
719(define_code_attr rotate_insn [(rotate "rotl") (rotatert "rotr")])
720
721;; Base name for insn mnemonic.
722(define_code_attr rotate [(rotate "rol") (rotatert "ror")])
723
724;; Mapping of abs neg operators
725(define_code_iterator absneg [abs neg])
726
727;; Base name for x87 insn mnemonic.
728(define_code_attr absneg_mnemonic [(abs "abs") (neg "chs")])
729
730;; Used in signed and unsigned widening multiplications.
731(define_code_iterator any_extend [sign_extend zero_extend])
732
733;; Prefix for insn menmonic.
734(define_code_attr sgnprefix [(sign_extend "i") (zero_extend "")])
735
736;; Prefix for define_insn
737(define_code_attr u [(sign_extend "") (zero_extend "u")])
738(define_code_attr s [(sign_extend "s") (zero_extend "u")])
739
740;; All integer modes.
741(define_mode_iterator SWI1248x [QI HI SI DI])
742
743;; All integer modes without QImode.
744(define_mode_iterator SWI248x [HI SI DI])
745
746;; All integer modes without QImode and HImode.
747(define_mode_iterator SWI48x [SI DI])
748
749;; All integer modes without SImode and DImode.
750(define_mode_iterator SWI12 [QI HI])
751
752;; All integer modes without DImode.
753(define_mode_iterator SWI124 [QI HI SI])
754
755;; All integer modes without QImode and DImode.
756(define_mode_iterator SWI24 [HI SI])
757
758;; Single word integer modes.
759(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])
760
761;; Single word integer modes without QImode.
762(define_mode_iterator SWI248 [HI SI (DI "TARGET_64BIT")])
763
764;; Single word integer modes without QImode and HImode.
765(define_mode_iterator SWI48 [SI (DI "TARGET_64BIT")])
766
767;; All math-dependant single and double word integer modes.
768(define_mode_iterator SDWIM [(QI "TARGET_QIMODE_MATH")
769 (HI "TARGET_HIMODE_MATH")
770 SI DI (TI "TARGET_64BIT")])
771
772;; Math-dependant single word integer modes.
773(define_mode_iterator SWIM [(QI "TARGET_QIMODE_MATH")
774 (HI "TARGET_HIMODE_MATH")
775 SI (DI "TARGET_64BIT")])
776
777;; Math-dependant integer modes without DImode.
778(define_mode_iterator SWIM124 [(QI "TARGET_QIMODE_MATH")
779 (HI "TARGET_HIMODE_MATH")
780 SI])
781
782;; Math-dependant single word integer modes without QImode.
783(define_mode_iterator SWIM248 [(HI "TARGET_HIMODE_MATH")
784 SI (DI "TARGET_64BIT")])
785
786;; Double word integer modes.
787(define_mode_iterator DWI [(DI "!TARGET_64BIT")
788 (TI "TARGET_64BIT")])
789
790;; Double word integer modes as mode attribute.
791(define_mode_attr DWI [(SI "DI") (DI "TI")])
792(define_mode_attr dwi [(SI "di") (DI "ti")])
793
794;; Half mode for double word integer modes.
795(define_mode_iterator DWIH [(SI "!TARGET_64BIT")
796 (DI "TARGET_64BIT")])
797
798;; Instruction suffix for integer modes.
799(define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])
800
801;; Pointer size prefix for integer modes (Intel asm dialect)
802(define_mode_attr iptrsize [(QI "BYTE")
803 (HI "WORD")
804 (SI "DWORD")
805 (DI "QWORD")])
806
807;; Register class for integer modes.
808(define_mode_attr r [(QI "q") (HI "r") (SI "r") (DI "r")])
809
810;; Immediate operand constraint for integer modes.
811(define_mode_attr i [(QI "n") (HI "n") (SI "e") (DI "e")])
812
813;; General operand constraint for word modes.
814(define_mode_attr g [(QI "qmn") (HI "rmn") (SI "rme") (DI "rme")])
815
816;; Immediate operand constraint for double integer modes.
817(define_mode_attr di [(SI "nF") (DI "e")])
818
819;; Immediate operand constraint for shifts.
820(define_mode_attr S [(QI "I") (HI "I") (SI "I") (DI "J") (TI "O")])
821
822;; General operand predicate for integer modes.
823(define_mode_attr general_operand
824 [(QI "general_operand")
825 (HI "general_operand")
826 (SI "x86_64_general_operand")
827 (DI "x86_64_general_operand")
828 (TI "x86_64_general_operand")])
829
830;; General sign/zero extend operand predicate for integer modes.
831(define_mode_attr general_szext_operand
832 [(QI "general_operand")
833 (HI "general_operand")
834 (SI "x86_64_szext_general_operand")
835 (DI "x86_64_szext_general_operand")])
836
837;; Immediate operand predicate for integer modes.
838(define_mode_attr immediate_operand
839 [(QI "immediate_operand")
840 (HI "immediate_operand")
841 (SI "x86_64_immediate_operand")
842 (DI "x86_64_immediate_operand")])
843
844;; Nonmemory operand predicate for integer modes.
845(define_mode_attr nonmemory_operand
846 [(QI "nonmemory_operand")
847 (HI "nonmemory_operand")
848 (SI "x86_64_nonmemory_operand")
849 (DI "x86_64_nonmemory_operand")])
850
851;; Operand predicate for shifts.
852(define_mode_attr shift_operand
853 [(QI "nonimmediate_operand")
854 (HI "nonimmediate_operand")
855 (SI "nonimmediate_operand")
856 (DI "shiftdi_operand")
857 (TI "register_operand")])
858
859;; Operand predicate for shift argument.
860(define_mode_attr shift_immediate_operand
861 [(QI "const_1_to_31_operand")
862 (HI "const_1_to_31_operand")
863 (SI "const_1_to_31_operand")
864 (DI "const_1_to_63_operand")])
865
866;; Input operand predicate for arithmetic left shifts.
867(define_mode_attr ashl_input_operand
868 [(QI "nonimmediate_operand")
869 (HI "nonimmediate_operand")
870 (SI "nonimmediate_operand")
871 (DI "ashldi_input_operand")
872 (TI "reg_or_pm1_operand")])
873
874;; SSE and x87 SFmode and DFmode floating point modes
875(define_mode_iterator MODEF [SF DF])
876
877;; All x87 floating point modes
878(define_mode_iterator X87MODEF [SF DF XF])
879
880;; SSE instruction suffix for various modes
881(define_mode_attr ssemodesuffix
882 [(SF "ss") (DF "sd")
883 (V8SF "ps") (V4DF "pd")
884 (V4SF "ps") (V2DF "pd")
885 (V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")
886 (V32QI "b") (V16HI "w") (V8SI "d") (V4DI "q")])
887
888;; SSE vector suffix for floating point modes
889(define_mode_attr ssevecmodesuffix [(SF "ps") (DF "pd")])
890
891;; SSE vector mode corresponding to a scalar mode
892(define_mode_attr ssevecmode
893 [(QI "V16QI") (HI "V8HI") (SI "V4SI") (DI "V2DI") (SF "V4SF") (DF "V2DF")])
894
895;; Instruction suffix for REX 64bit operators.
896(define_mode_attr rex64suffix [(SI "") (DI "{q}")])
897
898;; This mode iterator allows :P to be used for patterns that operate on
899;; pointer-sized quantities. Exactly one of the two alternatives will match.
900(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
901
902;; This mode iterator allows :PTR to be used for patterns that operate on
903;; ptr_mode sized quantities.
904(define_mode_iterator PTR
905 [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
906\f
907;; Scheduling descriptions
908
909(include "pentium.md")
910(include "ppro.md")
911(include "k6.md")
912(include "athlon.md")
913(include "bdver1.md")
914(include "geode.md")
915(include "atom.md")
916(include "core2.md")
917
918\f
919;; Operand and operator predicates and constraints
920
921(include "predicates.md")
922(include "constraints.md")
923
924\f
925;; Compare and branch/compare and store instructions.
926
927(define_expand "cbranch<mode>4"
928 [(set (reg:CC FLAGS_REG)
929 (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand" "")
930 (match_operand:SDWIM 2 "<general_operand>" "")))
931 (set (pc) (if_then_else
932 (match_operator 0 "ordered_comparison_operator"
933 [(reg:CC FLAGS_REG) (const_int 0)])
934 (label_ref (match_operand 3 "" ""))
935 (pc)))]
936 ""
937{
938 if (MEM_P (operands[1]) && MEM_P (operands[2]))
939 operands[1] = force_reg (<MODE>mode, operands[1]);
940 ix86_expand_branch (GET_CODE (operands[0]),
941 operands[1], operands[2], operands[3]);
942 DONE;
943})
944
945(define_expand "cstore<mode>4"
946 [(set (reg:CC FLAGS_REG)
947 (compare:CC (match_operand:SWIM 2 "nonimmediate_operand" "")
948 (match_operand:SWIM 3 "<general_operand>" "")))
949 (set (match_operand:QI 0 "register_operand" "")
950 (match_operator 1 "ordered_comparison_operator"
951 [(reg:CC FLAGS_REG) (const_int 0)]))]
952 ""
953{
954 if (MEM_P (operands[2]) && MEM_P (operands[3]))
955 operands[2] = force_reg (<MODE>mode, operands[2]);
956 ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
957 operands[2], operands[3]);
958 DONE;
959})
960
961(define_expand "cmp<mode>_1"
962 [(set (reg:CC FLAGS_REG)
963 (compare:CC (match_operand:SWI48 0 "nonimmediate_operand" "")
964 (match_operand:SWI48 1 "<general_operand>" "")))])
965
966(define_insn "*cmp<mode>_ccno_1"
967 [(set (reg FLAGS_REG)
968 (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>,?m<r>")
969 (match_operand:SWI 1 "const0_operand" "")))]
970 "ix86_match_ccmode (insn, CCNOmode)"
971 "@
972 test{<imodesuffix>}\t%0, %0
973 cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
974 [(set_attr "type" "test,icmp")
975 (set_attr "length_immediate" "0,1")
976 (set_attr "mode" "<MODE>")])
977
978(define_insn "*cmp<mode>_1"
979 [(set (reg FLAGS_REG)
980 (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
981 (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m")))]
982 "ix86_match_ccmode (insn, CCmode)"
983 "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
984 [(set_attr "type" "icmp")
985 (set_attr "mode" "<MODE>")])
986
987(define_insn "*cmp<mode>_minus_1"
988 [(set (reg FLAGS_REG)
989 (compare
990 (minus:SWI (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
991 (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
992 (const_int 0)))]
993 "ix86_match_ccmode (insn, CCGOCmode)"
994 "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
995 [(set_attr "type" "icmp")
996 (set_attr "mode" "<MODE>")])
997
998(define_insn "*cmpqi_ext_1"
999 [(set (reg FLAGS_REG)
1000 (compare
1001 (match_operand:QI 0 "general_operand" "Qm")
1002 (subreg:QI
1003 (zero_extract:SI
1004 (match_operand 1 "ext_register_operand" "Q")
1005 (const_int 8)
1006 (const_int 8)) 0)))]
1007 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1008 "cmp{b}\t{%h1, %0|%0, %h1}"
1009 [(set_attr "type" "icmp")
1010 (set_attr "mode" "QI")])
1011
1012(define_insn "*cmpqi_ext_1_rex64"
1013 [(set (reg FLAGS_REG)
1014 (compare
1015 (match_operand:QI 0 "register_operand" "Q")
1016 (subreg:QI
1017 (zero_extract:SI
1018 (match_operand 1 "ext_register_operand" "Q")
1019 (const_int 8)
1020 (const_int 8)) 0)))]
1021 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1022 "cmp{b}\t{%h1, %0|%0, %h1}"
1023 [(set_attr "type" "icmp")
1024 (set_attr "mode" "QI")])
1025
1026(define_insn "*cmpqi_ext_2"
1027 [(set (reg FLAGS_REG)
1028 (compare
1029 (subreg:QI
1030 (zero_extract:SI
1031 (match_operand 0 "ext_register_operand" "Q")
1032 (const_int 8)
1033 (const_int 8)) 0)
1034 (match_operand:QI 1 "const0_operand" "")))]
1035 "ix86_match_ccmode (insn, CCNOmode)"
1036 "test{b}\t%h0, %h0"
1037 [(set_attr "type" "test")
1038 (set_attr "length_immediate" "0")
1039 (set_attr "mode" "QI")])
1040
1041(define_expand "cmpqi_ext_3"
1042 [(set (reg:CC FLAGS_REG)
1043 (compare:CC
1044 (subreg:QI
1045 (zero_extract:SI
1046 (match_operand 0 "ext_register_operand" "")
1047 (const_int 8)
1048 (const_int 8)) 0)
1049 (match_operand:QI 1 "immediate_operand" "")))])
1050
1051(define_insn "*cmpqi_ext_3_insn"
1052 [(set (reg FLAGS_REG)
1053 (compare
1054 (subreg:QI
1055 (zero_extract:SI
1056 (match_operand 0 "ext_register_operand" "Q")
1057 (const_int 8)
1058 (const_int 8)) 0)
1059 (match_operand:QI 1 "general_operand" "Qmn")))]
1060 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1061 "cmp{b}\t{%1, %h0|%h0, %1}"
1062 [(set_attr "type" "icmp")
1063 (set_attr "modrm" "1")
1064 (set_attr "mode" "QI")])
1065
1066(define_insn "*cmpqi_ext_3_insn_rex64"
1067 [(set (reg FLAGS_REG)
1068 (compare
1069 (subreg:QI
1070 (zero_extract:SI
1071 (match_operand 0 "ext_register_operand" "Q")
1072 (const_int 8)
1073 (const_int 8)) 0)
1074 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
1075 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
1076 "cmp{b}\t{%1, %h0|%h0, %1}"
1077 [(set_attr "type" "icmp")
1078 (set_attr "modrm" "1")
1079 (set_attr "mode" "QI")])
1080
1081(define_insn "*cmpqi_ext_4"
1082 [(set (reg FLAGS_REG)
1083 (compare
1084 (subreg:QI
1085 (zero_extract:SI
1086 (match_operand 0 "ext_register_operand" "Q")
1087 (const_int 8)
1088 (const_int 8)) 0)
1089 (subreg:QI
1090 (zero_extract:SI
1091 (match_operand 1 "ext_register_operand" "Q")
1092 (const_int 8)
1093 (const_int 8)) 0)))]
1094 "ix86_match_ccmode (insn, CCmode)"
1095 "cmp{b}\t{%h1, %h0|%h0, %h1}"
1096 [(set_attr "type" "icmp")
1097 (set_attr "mode" "QI")])
1098
1099;; These implement float point compares.
1100;; %%% See if we can get away with VOIDmode operands on the actual insns,
1101;; which would allow mix and match FP modes on the compares. Which is what
1102;; the old patterns did, but with many more of them.
1103
1104(define_expand "cbranchxf4"
1105 [(set (reg:CC FLAGS_REG)
1106 (compare:CC (match_operand:XF 1 "nonmemory_operand" "")
1107 (match_operand:XF 2 "nonmemory_operand" "")))
1108 (set (pc) (if_then_else
1109 (match_operator 0 "ix86_fp_comparison_operator"
1110 [(reg:CC FLAGS_REG)
1111 (const_int 0)])
1112 (label_ref (match_operand 3 "" ""))
1113 (pc)))]
1114 "TARGET_80387"
1115{
1116 ix86_expand_branch (GET_CODE (operands[0]),
1117 operands[1], operands[2], operands[3]);
1118 DONE;
1119})
1120
1121(define_expand "cstorexf4"
1122 [(set (reg:CC FLAGS_REG)
1123 (compare:CC (match_operand:XF 2 "nonmemory_operand" "")
1124 (match_operand:XF 3 "nonmemory_operand" "")))
1125 (set (match_operand:QI 0 "register_operand" "")
1126 (match_operator 1 "ix86_fp_comparison_operator"
1127 [(reg:CC FLAGS_REG)
1128 (const_int 0)]))]
1129 "TARGET_80387"
1130{
1131 ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
1132 operands[2], operands[3]);
1133 DONE;
1134})
1135
1136(define_expand "cbranch<mode>4"
1137 [(set (reg:CC FLAGS_REG)
1138 (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "")
1139 (match_operand:MODEF 2 "cmp_fp_expander_operand" "")))
1140 (set (pc) (if_then_else
1141 (match_operator 0 "ix86_fp_comparison_operator"
1142 [(reg:CC FLAGS_REG)
1143 (const_int 0)])
1144 (label_ref (match_operand 3 "" ""))
1145 (pc)))]
1146 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
1147{
1148 ix86_expand_branch (GET_CODE (operands[0]),
1149 operands[1], operands[2], operands[3]);
1150 DONE;
1151})
1152
1153(define_expand "cstore<mode>4"
1154 [(set (reg:CC FLAGS_REG)
1155 (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "")
1156 (match_operand:MODEF 3 "cmp_fp_expander_operand" "")))
1157 (set (match_operand:QI 0 "register_operand" "")
1158 (match_operator 1 "ix86_fp_comparison_operator"
1159 [(reg:CC FLAGS_REG)
1160 (const_int 0)]))]
1161 "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
1162{
1163 ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
1164 operands[2], operands[3]);
1165 DONE;
1166})
1167
1168(define_expand "cbranchcc4"
1169 [(set (pc) (if_then_else
1170 (match_operator 0 "comparison_operator"
1171 [(match_operand 1 "flags_reg_operand" "")
1172 (match_operand 2 "const0_operand" "")])
1173 (label_ref (match_operand 3 "" ""))
1174 (pc)))]
1175 ""
1176{
1177 ix86_expand_branch (GET_CODE (operands[0]),
1178 operands[1], operands[2], operands[3]);
1179 DONE;
1180})
1181
1182(define_expand "cstorecc4"
1183 [(set (match_operand:QI 0 "register_operand" "")
1184 (match_operator 1 "comparison_operator"
1185 [(match_operand 2 "flags_reg_operand" "")
1186 (match_operand 3 "const0_operand" "")]))]
1187 ""
1188{
1189 ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
1190 operands[2], operands[3]);
1191 DONE;
1192})
1193
1194
1195;; FP compares, step 1:
1196;; Set the FP condition codes.
1197;;
1198;; CCFPmode compare with exceptions
1199;; CCFPUmode compare with no exceptions
1200
1201;; We may not use "#" to split and emit these, since the REG_DEAD notes
1202;; used to manage the reg stack popping would not be preserved.
1203
1204(define_insn "*cmpfp_0"
1205 [(set (match_operand:HI 0 "register_operand" "=a")
1206 (unspec:HI
1207 [(compare:CCFP
1208 (match_operand 1 "register_operand" "f")
1209 (match_operand 2 "const0_operand" ""))]
1210 UNSPEC_FNSTSW))]
1211 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1212 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1213 "* return output_fp_compare (insn, operands, false, false);"
1214 [(set_attr "type" "multi")
1215 (set_attr "unit" "i387")
1216 (set (attr "mode")
1217 (cond [(match_operand:SF 1 "" "")
1218 (const_string "SF")
1219 (match_operand:DF 1 "" "")
1220 (const_string "DF")
1221 ]
1222 (const_string "XF")))])
1223
1224(define_insn_and_split "*cmpfp_0_cc"
1225 [(set (reg:CCFP FLAGS_REG)
1226 (compare:CCFP
1227 (match_operand 1 "register_operand" "f")
1228 (match_operand 2 "const0_operand" "")))
1229 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1230 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1231 && TARGET_SAHF && !TARGET_CMOVE
1232 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1233 "#"
1234 "&& reload_completed"
1235 [(set (match_dup 0)
1236 (unspec:HI
1237 [(compare:CCFP (match_dup 1)(match_dup 2))]
1238 UNSPEC_FNSTSW))
1239 (set (reg:CC FLAGS_REG)
1240 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1241 ""
1242 [(set_attr "type" "multi")
1243 (set_attr "unit" "i387")
1244 (set (attr "mode")
1245 (cond [(match_operand:SF 1 "" "")
1246 (const_string "SF")
1247 (match_operand:DF 1 "" "")
1248 (const_string "DF")
1249 ]
1250 (const_string "XF")))])
1251
1252(define_insn "*cmpfp_xf"
1253 [(set (match_operand:HI 0 "register_operand" "=a")
1254 (unspec:HI
1255 [(compare:CCFP
1256 (match_operand:XF 1 "register_operand" "f")
1257 (match_operand:XF 2 "register_operand" "f"))]
1258 UNSPEC_FNSTSW))]
1259 "TARGET_80387"
1260 "* return output_fp_compare (insn, operands, false, false);"
1261 [(set_attr "type" "multi")
1262 (set_attr "unit" "i387")
1263 (set_attr "mode" "XF")])
1264
1265(define_insn_and_split "*cmpfp_xf_cc"
1266 [(set (reg:CCFP FLAGS_REG)
1267 (compare:CCFP
1268 (match_operand:XF 1 "register_operand" "f")
1269 (match_operand:XF 2 "register_operand" "f")))
1270 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1271 "TARGET_80387
1272 && TARGET_SAHF && !TARGET_CMOVE"
1273 "#"
1274 "&& reload_completed"
1275 [(set (match_dup 0)
1276 (unspec:HI
1277 [(compare:CCFP (match_dup 1)(match_dup 2))]
1278 UNSPEC_FNSTSW))
1279 (set (reg:CC FLAGS_REG)
1280 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1281 ""
1282 [(set_attr "type" "multi")
1283 (set_attr "unit" "i387")
1284 (set_attr "mode" "XF")])
1285
1286(define_insn "*cmpfp_<mode>"
1287 [(set (match_operand:HI 0 "register_operand" "=a")
1288 (unspec:HI
1289 [(compare:CCFP
1290 (match_operand:MODEF 1 "register_operand" "f")
1291 (match_operand:MODEF 2 "nonimmediate_operand" "fm"))]
1292 UNSPEC_FNSTSW))]
1293 "TARGET_80387"
1294 "* return output_fp_compare (insn, operands, false, false);"
1295 [(set_attr "type" "multi")
1296 (set_attr "unit" "i387")
1297 (set_attr "mode" "<MODE>")])
1298
1299(define_insn_and_split "*cmpfp_<mode>_cc"
1300 [(set (reg:CCFP FLAGS_REG)
1301 (compare:CCFP
1302 (match_operand:MODEF 1 "register_operand" "f")
1303 (match_operand:MODEF 2 "nonimmediate_operand" "fm")))
1304 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1305 "TARGET_80387
1306 && TARGET_SAHF && !TARGET_CMOVE"
1307 "#"
1308 "&& reload_completed"
1309 [(set (match_dup 0)
1310 (unspec:HI
1311 [(compare:CCFP (match_dup 1)(match_dup 2))]
1312 UNSPEC_FNSTSW))
1313 (set (reg:CC FLAGS_REG)
1314 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1315 ""
1316 [(set_attr "type" "multi")
1317 (set_attr "unit" "i387")
1318 (set_attr "mode" "<MODE>")])
1319
1320(define_insn "*cmpfp_u"
1321 [(set (match_operand:HI 0 "register_operand" "=a")
1322 (unspec:HI
1323 [(compare:CCFPU
1324 (match_operand 1 "register_operand" "f")
1325 (match_operand 2 "register_operand" "f"))]
1326 UNSPEC_FNSTSW))]
1327 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1328 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1329 "* return output_fp_compare (insn, operands, false, true);"
1330 [(set_attr "type" "multi")
1331 (set_attr "unit" "i387")
1332 (set (attr "mode")
1333 (cond [(match_operand:SF 1 "" "")
1334 (const_string "SF")
1335 (match_operand:DF 1 "" "")
1336 (const_string "DF")
1337 ]
1338 (const_string "XF")))])
1339
1340(define_insn_and_split "*cmpfp_u_cc"
1341 [(set (reg:CCFPU FLAGS_REG)
1342 (compare:CCFPU
1343 (match_operand 1 "register_operand" "f")
1344 (match_operand 2 "register_operand" "f")))
1345 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1346 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1347 && TARGET_SAHF && !TARGET_CMOVE
1348 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1349 "#"
1350 "&& reload_completed"
1351 [(set (match_dup 0)
1352 (unspec:HI
1353 [(compare:CCFPU (match_dup 1)(match_dup 2))]
1354 UNSPEC_FNSTSW))
1355 (set (reg:CC FLAGS_REG)
1356 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1357 ""
1358 [(set_attr "type" "multi")
1359 (set_attr "unit" "i387")
1360 (set (attr "mode")
1361 (cond [(match_operand:SF 1 "" "")
1362 (const_string "SF")
1363 (match_operand:DF 1 "" "")
1364 (const_string "DF")
1365 ]
1366 (const_string "XF")))])
1367
1368(define_insn "*cmpfp_<mode>"
1369 [(set (match_operand:HI 0 "register_operand" "=a")
1370 (unspec:HI
1371 [(compare:CCFP
1372 (match_operand 1 "register_operand" "f")
1373 (match_operator 3 "float_operator"
1374 [(match_operand:SWI24 2 "memory_operand" "m")]))]
1375 UNSPEC_FNSTSW))]
1376 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1377 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
1378 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
1379 "* return output_fp_compare (insn, operands, false, false);"
1380 [(set_attr "type" "multi")
1381 (set_attr "unit" "i387")
1382 (set_attr "fp_int_src" "true")
1383 (set_attr "mode" "<MODE>")])
1384
1385(define_insn_and_split "*cmpfp_<mode>_cc"
1386 [(set (reg:CCFP FLAGS_REG)
1387 (compare:CCFP
1388 (match_operand 1 "register_operand" "f")
1389 (match_operator 3 "float_operator"
1390 [(match_operand:SWI24 2 "memory_operand" "m")])))
1391 (clobber (match_operand:HI 0 "register_operand" "=a"))]
1392 "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
1393 && TARGET_SAHF && !TARGET_CMOVE
1394 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
1395 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
1396 "#"
1397 "&& reload_completed"
1398 [(set (match_dup 0)
1399 (unspec:HI
1400 [(compare:CCFP
1401 (match_dup 1)
1402 (match_op_dup 3 [(match_dup 2)]))]
1403 UNSPEC_FNSTSW))
1404 (set (reg:CC FLAGS_REG)
1405 (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
1406 ""
1407 [(set_attr "type" "multi")
1408 (set_attr "unit" "i387")
1409 (set_attr "fp_int_src" "true")
1410 (set_attr "mode" "<MODE>")])
1411
1412;; FP compares, step 2
1413;; Move the fpsw to ax.
1414
1415(define_insn "x86_fnstsw_1"
1416 [(set (match_operand:HI 0 "register_operand" "=a")
1417 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
1418 "TARGET_80387"
1419 "fnstsw\t%0"
1420 [(set (attr "length")
1421 (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
1422 (set_attr "mode" "SI")
1423 (set_attr "unit" "i387")])
1424
1425;; FP compares, step 3
1426;; Get ax into flags, general case.
1427
1428(define_insn "x86_sahf_1"
1429 [(set (reg:CC FLAGS_REG)
1430 (unspec:CC [(match_operand:HI 0 "register_operand" "a")]
1431 UNSPEC_SAHF))]
1432 "TARGET_SAHF"
1433{
1434#ifndef HAVE_AS_IX86_SAHF
1435 if (TARGET_64BIT)
1436 return ASM_BYTE "0x9e";
1437 else
1438#endif
1439 return "sahf";
1440}
1441 [(set_attr "length" "1")
1442 (set_attr "athlon_decode" "vector")
1443 (set_attr "amdfam10_decode" "direct")
1444 (set_attr "bdver1_decode" "direct")
1445 (set_attr "mode" "SI")])
1446
1447;; Pentium Pro can do steps 1 through 3 in one go.
1448;; comi*, ucomi*, fcomi*, ficomi*, fucomi*
1449;; (these i387 instructions set flags directly)
1450(define_insn "*cmpfp_i_mixed"
1451 [(set (reg:CCFP FLAGS_REG)
1452 (compare:CCFP (match_operand 0 "register_operand" "f,x")
1453 (match_operand 1 "nonimmediate_operand" "f,xm")))]
1454 "TARGET_MIX_SSE_I387
1455 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1456 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1457 "* return output_fp_compare (insn, operands, true, false);"
1458 [(set_attr "type" "fcmp,ssecomi")
1459 (set_attr "prefix" "orig,maybe_vex")
1460 (set (attr "mode")
1461 (if_then_else (match_operand:SF 1 "" "")
1462 (const_string "SF")
1463 (const_string "DF")))
1464 (set (attr "prefix_rep")
1465 (if_then_else (eq_attr "type" "ssecomi")
1466 (const_string "0")
1467 (const_string "*")))
1468 (set (attr "prefix_data16")
1469 (cond [(eq_attr "type" "fcmp")
1470 (const_string "*")
1471 (eq_attr "mode" "DF")
1472 (const_string "1")
1473 ]
1474 (const_string "0")))
1475 (set_attr "athlon_decode" "vector")
1476 (set_attr "amdfam10_decode" "direct")
1477 (set_attr "bdver1_decode" "double")])
1478
1479(define_insn "*cmpfp_i_sse"
1480 [(set (reg:CCFP FLAGS_REG)
1481 (compare:CCFP (match_operand 0 "register_operand" "x")
1482 (match_operand 1 "nonimmediate_operand" "xm")))]
1483 "TARGET_SSE_MATH
1484 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1485 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1486 "* return output_fp_compare (insn, operands, true, false);"
1487 [(set_attr "type" "ssecomi")
1488 (set_attr "prefix" "maybe_vex")
1489 (set (attr "mode")
1490 (if_then_else (match_operand:SF 1 "" "")
1491 (const_string "SF")
1492 (const_string "DF")))
1493 (set_attr "prefix_rep" "0")
1494 (set (attr "prefix_data16")
1495 (if_then_else (eq_attr "mode" "DF")
1496 (const_string "1")
1497 (const_string "0")))
1498 (set_attr "athlon_decode" "vector")
1499 (set_attr "amdfam10_decode" "direct")
1500 (set_attr "bdver1_decode" "double")])
1501
1502(define_insn "*cmpfp_i_i387"
1503 [(set (reg:CCFP FLAGS_REG)
1504 (compare:CCFP (match_operand 0 "register_operand" "f")
1505 (match_operand 1 "register_operand" "f")))]
1506 "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
1507 && TARGET_CMOVE
1508 && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
1509 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1510 "* return output_fp_compare (insn, operands, true, false);"
1511 [(set_attr "type" "fcmp")
1512 (set (attr "mode")
1513 (cond [(match_operand:SF 1 "" "")
1514 (const_string "SF")
1515 (match_operand:DF 1 "" "")
1516 (const_string "DF")
1517 ]
1518 (const_string "XF")))
1519 (set_attr "athlon_decode" "vector")
1520 (set_attr "amdfam10_decode" "direct")
1521 (set_attr "bdver1_decode" "double")])
1522
1523(define_insn "*cmpfp_iu_mixed"
1524 [(set (reg:CCFPU FLAGS_REG)
1525 (compare:CCFPU (match_operand 0 "register_operand" "f,x")
1526 (match_operand 1 "nonimmediate_operand" "f,xm")))]
1527 "TARGET_MIX_SSE_I387
1528 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1529 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1530 "* return output_fp_compare (insn, operands, true, true);"
1531 [(set_attr "type" "fcmp,ssecomi")
1532 (set_attr "prefix" "orig,maybe_vex")
1533 (set (attr "mode")
1534 (if_then_else (match_operand:SF 1 "" "")
1535 (const_string "SF")
1536 (const_string "DF")))
1537 (set (attr "prefix_rep")
1538 (if_then_else (eq_attr "type" "ssecomi")
1539 (const_string "0")
1540 (const_string "*")))
1541 (set (attr "prefix_data16")
1542 (cond [(eq_attr "type" "fcmp")
1543 (const_string "*")
1544 (eq_attr "mode" "DF")
1545 (const_string "1")
1546 ]
1547 (const_string "0")))
1548 (set_attr "athlon_decode" "vector")
1549 (set_attr "amdfam10_decode" "direct")
1550 (set_attr "bdver1_decode" "double")])
1551
1552(define_insn "*cmpfp_iu_sse"
1553 [(set (reg:CCFPU FLAGS_REG)
1554 (compare:CCFPU (match_operand 0 "register_operand" "x")
1555 (match_operand 1 "nonimmediate_operand" "xm")))]
1556 "TARGET_SSE_MATH
1557 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1558 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1559 "* return output_fp_compare (insn, operands, true, true);"
1560 [(set_attr "type" "ssecomi")
1561 (set_attr "prefix" "maybe_vex")
1562 (set (attr "mode")
1563 (if_then_else (match_operand:SF 1 "" "")
1564 (const_string "SF")
1565 (const_string "DF")))
1566 (set_attr "prefix_rep" "0")
1567 (set (attr "prefix_data16")
1568 (if_then_else (eq_attr "mode" "DF")
1569 (const_string "1")
1570 (const_string "0")))
1571 (set_attr "athlon_decode" "vector")
1572 (set_attr "amdfam10_decode" "direct")
1573 (set_attr "bdver1_decode" "double")])
1574
1575(define_insn "*cmpfp_iu_387"
1576 [(set (reg:CCFPU FLAGS_REG)
1577 (compare:CCFPU (match_operand 0 "register_operand" "f")
1578 (match_operand 1 "register_operand" "f")))]
1579 "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
1580 && TARGET_CMOVE
1581 && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
1582 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1583 "* return output_fp_compare (insn, operands, true, true);"
1584 [(set_attr "type" "fcmp")
1585 (set (attr "mode")
1586 (cond [(match_operand:SF 1 "" "")
1587 (const_string "SF")
1588 (match_operand:DF 1 "" "")
1589 (const_string "DF")
1590 ]
1591 (const_string "XF")))
1592 (set_attr "athlon_decode" "vector")
1593 (set_attr "amdfam10_decode" "direct")
1594 (set_attr "bdver1_decode" "direct")])
1595\f
1596;; Push/pop instructions.
1597
1598(define_insn "*push<mode>2"
1599 [(set (match_operand:DWI 0 "push_operand" "=<")
1600 (match_operand:DWI 1 "general_no_elim_operand" "riF*o"))]
1601 ""
1602 "#"
1603 [(set_attr "type" "multi")
1604 (set_attr "mode" "<MODE>")])
1605
1606(define_split
1607 [(set (match_operand:TI 0 "push_operand" "")
1608 (match_operand:TI 1 "general_operand" ""))]
1609 "TARGET_64BIT && reload_completed
1610 && !SSE_REG_P (operands[1])"
1611 [(const_int 0)]
1612 "ix86_split_long_move (operands); DONE;")
1613
1614(define_insn "*pushdi2_rex64"
1615 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1616 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1617 "TARGET_64BIT"
1618 "@
1619 push{q}\t%1
1620 #"
1621 [(set_attr "type" "push,multi")
1622 (set_attr "mode" "DI")])
1623
1624;; Convert impossible pushes of immediate to existing instructions.
1625;; First try to get scratch register and go through it. In case this
1626;; fails, push sign extended lower part first and then overwrite
1627;; upper part by 32bit move.
1628(define_peephole2
1629 [(match_scratch:DI 2 "r")
1630 (set (match_operand:DI 0 "push_operand" "")
1631 (match_operand:DI 1 "immediate_operand" ""))]
1632 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1633 && !x86_64_immediate_operand (operands[1], DImode)"
1634 [(set (match_dup 2) (match_dup 1))
1635 (set (match_dup 0) (match_dup 2))])
1636
1637;; We need to define this as both peepholer and splitter for case
1638;; peephole2 pass is not run.
1639;; "&& 1" is needed to keep it from matching the previous pattern.
1640(define_peephole2
1641 [(set (match_operand:DI 0 "push_operand" "")
1642 (match_operand:DI 1 "immediate_operand" ""))]
1643 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1644 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1645 [(set (match_dup 0) (match_dup 1))
1646 (set (match_dup 2) (match_dup 3))]
1647{
1648 split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);
1649
1650 operands[1] = gen_lowpart (DImode, operands[2]);
95d28233 1651 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,
e4b17023
JM
1652 GEN_INT (4)));
1653})
1654
1655(define_split
1656 [(set (match_operand:DI 0 "push_operand" "")
1657 (match_operand:DI 1 "immediate_operand" ""))]
1658 "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
1659 ? epilogue_completed : reload_completed)
1660 && !symbolic_operand (operands[1], DImode)
1661 && !x86_64_immediate_operand (operands[1], DImode)"
1662 [(set (match_dup 0) (match_dup 1))
1663 (set (match_dup 2) (match_dup 3))]
1664{
1665 split_double_mode (DImode, &operands[1], 1, &operands[2], &operands[3]);
1666
1667 operands[1] = gen_lowpart (DImode, operands[2]);
95d28233 1668 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (Pmode, stack_pointer_rtx,
e4b17023
JM
1669 GEN_INT (4)));
1670})
1671
1672(define_split
1673 [(set (match_operand:DI 0 "push_operand" "")
1674 (match_operand:DI 1 "general_operand" ""))]
1675 "!TARGET_64BIT && reload_completed
1676 && !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
1677 [(const_int 0)]
1678 "ix86_split_long_move (operands); DONE;")
1679
1680(define_insn "*pushsi2"
1681 [(set (match_operand:SI 0 "push_operand" "=<")
1682 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1683 "!TARGET_64BIT"
1684 "push{l}\t%1"
1685 [(set_attr "type" "push")
1686 (set_attr "mode" "SI")])
1687
1688;; emit_push_insn when it calls move_by_pieces requires an insn to
1689;; "push a byte/word". But actually we use pushl, which has the effect
1690;; of rounding the amount pushed up to a word.
1691
1692;; For TARGET_64BIT we always round up to 8 bytes.
1693(define_insn "*push<mode>2_rex64"
1694 [(set (match_operand:SWI124 0 "push_operand" "=X")
1695 (match_operand:SWI124 1 "nonmemory_no_elim_operand" "r<i>"))]
1696 "TARGET_64BIT"
1697 "push{q}\t%q1"
1698 [(set_attr "type" "push")
1699 (set_attr "mode" "DI")])
1700
1701(define_insn "*push<mode>2"
1702 [(set (match_operand:SWI12 0 "push_operand" "=X")
1703 (match_operand:SWI12 1 "nonmemory_no_elim_operand" "rn"))]
1704 "!TARGET_64BIT"
1705 "push{l}\t%k1"
1706 [(set_attr "type" "push")
1707 (set_attr "mode" "SI")])
1708
1709(define_insn "*push<mode>2_prologue"
1710 [(set (match_operand:P 0 "push_operand" "=<")
1711 (match_operand:P 1 "general_no_elim_operand" "r<i>*m"))
1712 (clobber (mem:BLK (scratch)))]
1713 ""
1714 "push{<imodesuffix>}\t%1"
1715 [(set_attr "type" "push")
1716 (set_attr "mode" "<MODE>")])
1717
1718(define_insn "*pop<mode>1"
1719 [(set (match_operand:P 0 "nonimmediate_operand" "=r*m")
1720 (match_operand:P 1 "pop_operand" ">"))]
1721 ""
1722 "pop{<imodesuffix>}\t%0"
1723 [(set_attr "type" "pop")
1724 (set_attr "mode" "<MODE>")])
1725
1726(define_insn "*pop<mode>1_epilogue"
1727 [(set (match_operand:P 0 "nonimmediate_operand" "=r*m")
1728 (match_operand:P 1 "pop_operand" ">"))
1729 (clobber (mem:BLK (scratch)))]
1730 ""
1731 "pop{<imodesuffix>}\t%0"
1732 [(set_attr "type" "pop")
1733 (set_attr "mode" "<MODE>")])
1734\f
1735;; Move instructions.
1736
1737(define_expand "movoi"
1738 [(set (match_operand:OI 0 "nonimmediate_operand" "")
1739 (match_operand:OI 1 "general_operand" ""))]
1740 "TARGET_AVX"
1741 "ix86_expand_move (OImode, operands); DONE;")
1742
1743(define_expand "movti"
1744 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1745 (match_operand:TI 1 "nonimmediate_operand" ""))]
1746 "TARGET_64BIT || TARGET_SSE"
1747{
1748 if (TARGET_64BIT)
1749 ix86_expand_move (TImode, operands);
1750 else if (push_operand (operands[0], TImode))
1751 ix86_expand_push (TImode, operands[1]);
1752 else
1753 ix86_expand_vector_move (TImode, operands);
1754 DONE;
1755})
1756
1757;; This expands to what emit_move_complex would generate if we didn't
1758;; have a movti pattern. Having this avoids problems with reload on
1759;; 32-bit targets when SSE is present, but doesn't seem to be harmful
1760;; to have around all the time.
1761(define_expand "movcdi"
1762 [(set (match_operand:CDI 0 "nonimmediate_operand" "")
1763 (match_operand:CDI 1 "general_operand" ""))]
1764 ""
1765{
1766 if (push_operand (operands[0], CDImode))
1767 emit_move_complex_push (CDImode, operands[0], operands[1]);
1768 else
1769 emit_move_complex_parts (operands[0], operands[1]);
1770 DONE;
1771})
1772
1773(define_expand "mov<mode>"
1774 [(set (match_operand:SWI1248x 0 "nonimmediate_operand" "")
1775 (match_operand:SWI1248x 1 "general_operand" ""))]
1776 ""
1777 "ix86_expand_move (<MODE>mode, operands); DONE;")
1778
1779(define_insn "*mov<mode>_xor"
1780 [(set (match_operand:SWI48 0 "register_operand" "=r")
1781 (match_operand:SWI48 1 "const0_operand" ""))
1782 (clobber (reg:CC FLAGS_REG))]
1783 "reload_completed"
1784 "xor{l}\t%k0, %k0"
1785 [(set_attr "type" "alu1")
1786 (set_attr "mode" "SI")
1787 (set_attr "length_immediate" "0")])
1788
1789(define_insn "*mov<mode>_or"
1790 [(set (match_operand:SWI48 0 "register_operand" "=r")
1791 (match_operand:SWI48 1 "const_int_operand" ""))
1792 (clobber (reg:CC FLAGS_REG))]
1793 "reload_completed
1794 && operands[1] == constm1_rtx"
1795 "or{<imodesuffix>}\t{%1, %0|%0, %1}"
1796 [(set_attr "type" "alu1")
1797 (set_attr "mode" "<MODE>")
1798 (set_attr "length_immediate" "1")])
1799
1800(define_insn "*movoi_internal_avx"
1801 [(set (match_operand:OI 0 "nonimmediate_operand" "=x,x,m")
1802 (match_operand:OI 1 "vector_move_operand" "C,xm,x"))]
1803 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1804{
1805 switch (which_alternative)
1806 {
1807 case 0:
1808 return standard_sse_constant_opcode (insn, operands[1]);
1809 case 1:
1810 case 2:
1811 if (misaligned_operand (operands[0], OImode)
1812 || misaligned_operand (operands[1], OImode))
1813 return "vmovdqu\t{%1, %0|%0, %1}";
1814 else
1815 return "vmovdqa\t{%1, %0|%0, %1}";
1816 default:
1817 gcc_unreachable ();
1818 }
1819}
1820 [(set_attr "type" "sselog1,ssemov,ssemov")
1821 (set_attr "prefix" "vex")
1822 (set_attr "mode" "OI")])
1823
1824(define_insn "*movti_internal_rex64"
5ce9237c
JM
1825 [(set (match_operand:TI 0 "nonimmediate_operand" "=!r,o,x,x,m")
1826 (match_operand:TI 1 "general_operand" "riFo,re,C,xm,x"))]
e4b17023
JM
1827 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1828{
1829 switch (which_alternative)
1830 {
1831 case 0:
1832 case 1:
1833 return "#";
1834 case 2:
1835 return standard_sse_constant_opcode (insn, operands[1]);
1836 case 3:
1837 case 4:
1838 /* TDmode values are passed as TImode on the stack. Moving them
1839 to stack may result in unaligned memory access. */
1840 if (misaligned_operand (operands[0], TImode)
1841 || misaligned_operand (operands[1], TImode))
1842 {
1843 if (get_attr_mode (insn) == MODE_V4SF)
1844 return "%vmovups\t{%1, %0|%0, %1}";
1845 else
1846 return "%vmovdqu\t{%1, %0|%0, %1}";
1847 }
1848 else
1849 {
1850 if (get_attr_mode (insn) == MODE_V4SF)
1851 return "%vmovaps\t{%1, %0|%0, %1}";
1852 else
1853 return "%vmovdqa\t{%1, %0|%0, %1}";
1854 }
1855 default:
1856 gcc_unreachable ();
1857 }
1858}
1859 [(set_attr "type" "*,*,sselog1,ssemov,ssemov")
1860 (set_attr "prefix" "*,*,maybe_vex,maybe_vex,maybe_vex")
1861 (set (attr "mode")
95d28233
JM
1862 (cond [(eq_attr "alternative" "0,1")
1863 (const_string "DI")
1864 (ior (not (match_test "TARGET_SSE2"))
1865 (match_test "optimize_function_for_size_p (cfun)"))
1866 (const_string "V4SF")
1867 (and (eq_attr "alternative" "4")
1868 (match_test "TARGET_SSE_TYPELESS_STORES"))
1869 (const_string "V4SF")
1870 ]
1871 (const_string "TI")))])
e4b17023
JM
1872
1873(define_split
1874 [(set (match_operand:TI 0 "nonimmediate_operand" "")
1875 (match_operand:TI 1 "general_operand" ""))]
1876 "reload_completed
1877 && !SSE_REG_P (operands[0]) && !SSE_REG_P (operands[1])"
1878 [(const_int 0)]
1879 "ix86_split_long_move (operands); DONE;")
1880
1881(define_insn "*movti_internal_sse"
1882 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
1883 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
1884 "TARGET_SSE && !TARGET_64BIT
1885 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1886{
1887 switch (which_alternative)
1888 {
1889 case 0:
1890 return standard_sse_constant_opcode (insn, operands[1]);
1891 case 1:
1892 case 2:
1893 /* TDmode values are passed as TImode on the stack. Moving them
1894 to stack may result in unaligned memory access. */
1895 if (misaligned_operand (operands[0], TImode)
1896 || misaligned_operand (operands[1], TImode))
1897 {
1898 if (get_attr_mode (insn) == MODE_V4SF)
1899 return "%vmovups\t{%1, %0|%0, %1}";
1900 else
1901 return "%vmovdqu\t{%1, %0|%0, %1}";
1902 }
1903 else
1904 {
1905 if (get_attr_mode (insn) == MODE_V4SF)
1906 return "%vmovaps\t{%1, %0|%0, %1}";
1907 else
1908 return "%vmovdqa\t{%1, %0|%0, %1}";
1909 }
1910 default:
1911 gcc_unreachable ();
1912 }
1913}
1914 [(set_attr "type" "sselog1,ssemov,ssemov")
1915 (set_attr "prefix" "maybe_vex")
1916 (set (attr "mode")
1917 (cond [(ior (not (match_test "TARGET_SSE2"))
1918 (match_test "optimize_function_for_size_p (cfun)"))
1919 (const_string "V4SF")
1920 (and (eq_attr "alternative" "2")
1921 (match_test "TARGET_SSE_TYPELESS_STORES"))
1922 (const_string "V4SF")]
1923 (const_string "TI")))])
1924
1925(define_insn "*movdi_internal_rex64"
1926 [(set (match_operand:DI 0 "nonimmediate_operand"
5ce9237c 1927 "=r,r ,r,m ,*y,m*y,?*y,?r ,?*Ym,*x,m ,*x,*x,?r ,?*Yi,?*x,?*Ym")
e4b17023 1928 (match_operand:DI 1 "general_operand"
5ce9237c 1929 "Z ,rem,i,re,C ,*y ,m ,*Ym,r ,C ,*x,*x,m ,*Yi,r ,*Ym,*x"))]
e4b17023
JM
1930 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1931{
1932 switch (get_attr_type (insn))
1933 {
1934 case TYPE_SSECVT:
1935 if (SSE_REG_P (operands[0]))
1936 return "movq2dq\t{%1, %0|%0, %1}";
1937 else
1938 return "movdq2q\t{%1, %0|%0, %1}";
1939
1940 case TYPE_SSEMOV:
1941 if (get_attr_mode (insn) == MODE_TI)
1942 return "%vmovdqa\t{%1, %0|%0, %1}";
1943 /* Handle broken assemblers that require movd instead of movq. */
1944 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1945 return "%vmovd\t{%1, %0|%0, %1}";
1946 else
1947 return "%vmovq\t{%1, %0|%0, %1}";
1948
1949 case TYPE_MMXMOV:
1950 /* Handle broken assemblers that require movd instead of movq. */
1951 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1952 return "movd\t{%1, %0|%0, %1}";
1953 else
1954 return "movq\t{%1, %0|%0, %1}";
1955
1956 case TYPE_SSELOG1:
1957 return standard_sse_constant_opcode (insn, operands[1]);
1958
1959 case TYPE_MMX:
1960 return "pxor\t%0, %0";
1961
e4b17023
JM
1962 case TYPE_LEA:
1963 return "lea{q}\t{%E1, %0|%0, %E1}";
1964
1965 default:
1966 gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
1967 if (get_attr_mode (insn) == MODE_SI)
1968 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1969 else if (which_alternative == 2)
1970 return "movabs{q}\t{%1, %0|%0, %1}";
1971 else if (ix86_use_lea_for_mov (insn, operands))
1972 return "lea{q}\t{%E1, %0|%0, %E1}";
1973 else
1974 return "mov{q}\t{%1, %0|%0, %1}";
1975 }
1976}
1977 [(set (attr "type")
1978 (cond [(eq_attr "alternative" "4")
e4b17023 1979 (const_string "mmx")
5ce9237c 1980 (eq_attr "alternative" "5,6,7,8")
e4b17023 1981 (const_string "mmxmov")
5ce9237c 1982 (eq_attr "alternative" "9")
e4b17023 1983 (const_string "sselog1")
5ce9237c 1984 (eq_attr "alternative" "10,11,12,13,14")
e4b17023 1985 (const_string "ssemov")
5ce9237c 1986 (eq_attr "alternative" "15,16")
e4b17023
JM
1987 (const_string "ssecvt")
1988 (match_operand 1 "pic_32bit_operand" "")
1989 (const_string "lea")
1990 ]
1991 (const_string "imov")))
1992 (set (attr "modrm")
1993 (if_then_else
1994 (and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
1995 (const_string "0")
1996 (const_string "*")))
1997 (set (attr "length_immediate")
1998 (if_then_else
1999 (and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
2000 (const_string "8")
2001 (const_string "*")))
2002 (set (attr "prefix_rex")
5ce9237c 2003 (if_then_else (eq_attr "alternative" "7,8")
e4b17023
JM
2004 (const_string "1")
2005 (const_string "*")))
2006 (set (attr "prefix_data16")
5ce9237c 2007 (if_then_else (eq_attr "alternative" "10")
e4b17023
JM
2008 (const_string "1")
2009 (const_string "*")))
2010 (set (attr "prefix")
5ce9237c 2011 (if_then_else (eq_attr "alternative" "11,12,13,14,15")
e4b17023
JM
2012 (const_string "maybe_vex")
2013 (const_string "orig")))
5ce9237c 2014 (set_attr "mode" "SI,DI,DI,DI,DI,DI,DI,DI,DI,TI,DI,TI,DI,DI,DI,DI,DI")])
e4b17023
JM
2015
2016;; Reload patterns to support multi-word load/store
2017;; with non-offsetable address.
2018(define_expand "reload_noff_store"
2019 [(parallel [(match_operand 0 "memory_operand" "=m")
2020 (match_operand 1 "register_operand" "r")
2021 (match_operand:DI 2 "register_operand" "=&r")])]
2022 "TARGET_64BIT"
2023{
2024 rtx mem = operands[0];
2025 rtx addr = XEXP (mem, 0);
2026
2027 emit_move_insn (operands[2], addr);
2028 mem = replace_equiv_address_nv (mem, operands[2]);
2029
2030 emit_insn (gen_rtx_SET (VOIDmode, mem, operands[1]));
2031 DONE;
2032})
2033
2034(define_expand "reload_noff_load"
2035 [(parallel [(match_operand 0 "register_operand" "=r")
2036 (match_operand 1 "memory_operand" "m")
2037 (match_operand:DI 2 "register_operand" "=r")])]
2038 "TARGET_64BIT"
2039{
2040 rtx mem = operands[1];
2041 rtx addr = XEXP (mem, 0);
2042
2043 emit_move_insn (operands[2], addr);
2044 mem = replace_equiv_address_nv (mem, operands[2]);
2045
2046 emit_insn (gen_rtx_SET (VOIDmode, operands[0], mem));
2047 DONE;
2048})
2049
e4b17023
JM
2050(define_insn "*movdi_internal"
2051 [(set (match_operand:DI 0 "nonimmediate_operand"
2052 "=r ,o ,*y,m*y,*y,*x,m ,*x,*x,*x,m ,*x,*x,?*x,?*Ym")
2053 (match_operand:DI 1 "general_operand"
2054 "riFo,riF,C ,*y ,m ,C ,*x,*x,m ,C ,*x,*x,m ,*Ym,*x"))]
2055 "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
2056{
2057 switch (get_attr_type (insn))
2058 {
2059 case TYPE_SSECVT:
2060 if (SSE_REG_P (operands[0]))
2061 return "movq2dq\t{%1, %0|%0, %1}";
2062 else
2063 return "movdq2q\t{%1, %0|%0, %1}";
2064
2065 case TYPE_SSEMOV:
2066 switch (get_attr_mode (insn))
2067 {
2068 case MODE_TI:
2069 return "%vmovdqa\t{%1, %0|%0, %1}";
2070 case MODE_DI:
2071 return "%vmovq\t{%1, %0|%0, %1}";
2072 case MODE_V4SF:
2073 return "movaps\t{%1, %0|%0, %1}";
2074 case MODE_V2SF:
2075 return "movlps\t{%1, %0|%0, %1}";
2076 default:
2077 gcc_unreachable ();
2078 }
2079
2080 case TYPE_MMXMOV:
2081 return "movq\t{%1, %0|%0, %1}";
2082
2083 case TYPE_SSELOG1:
2084 return standard_sse_constant_opcode (insn, operands[1]);
2085
2086 case TYPE_MMX:
2087 return "pxor\t%0, %0";
2088
2089 case TYPE_MULTI:
2090 return "#";
2091
2092 default:
2093 gcc_unreachable ();
2094 }
2095}
2096 [(set (attr "isa")
2097 (cond [(eq_attr "alternative" "5,6,7,8,13,14")
2098 (const_string "sse2")
2099 (eq_attr "alternative" "9,10,11,12")
2100 (const_string "noavx")
2101 ]
2102 (const_string "*")))
2103 (set (attr "type")
2104 (cond [(eq_attr "alternative" "0,1")
2105 (const_string "multi")
2106 (eq_attr "alternative" "2")
2107 (const_string "mmx")
2108 (eq_attr "alternative" "3,4")
2109 (const_string "mmxmov")
2110 (eq_attr "alternative" "5,9")
2111 (const_string "sselog1")
2112 (eq_attr "alternative" "13,14")
2113 (const_string "ssecvt")
2114 ]
2115 (const_string "ssemov")))
2116 (set (attr "prefix")
2117 (if_then_else (eq_attr "alternative" "5,6,7,8")
2118 (const_string "maybe_vex")
2119 (const_string "orig")))
2120 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF,DI,DI")])
2121
2122(define_split
2123 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2124 (match_operand:DI 1 "general_operand" ""))]
2125 "!TARGET_64BIT && reload_completed
2126 && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))
2127 && !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
2128 [(const_int 0)]
2129 "ix86_split_long_move (operands); DONE;")
2130
2131(define_insn "*movsi_internal"
2132 [(set (match_operand:SI 0 "nonimmediate_operand"
2133 "=r,m ,*y,*y,?rm,?*y,*x,*x,?r ,m ,?*Yi,*x")
2134 (match_operand:SI 1 "general_operand"
2135 "g ,re,C ,*y,*y ,rm ,C ,*x,*Yi,*x,r ,m "))]
2136 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
2137{
2138 switch (get_attr_type (insn))
2139 {
2140 case TYPE_SSELOG1:
2141 return standard_sse_constant_opcode (insn, operands[1]);
2142
2143 case TYPE_SSEMOV:
2144 switch (get_attr_mode (insn))
2145 {
2146 case MODE_TI:
2147 return "%vmovdqa\t{%1, %0|%0, %1}";
2148 case MODE_V4SF:
2149 return "%vmovaps\t{%1, %0|%0, %1}";
2150 case MODE_SI:
2151 return "%vmovd\t{%1, %0|%0, %1}";
2152 case MODE_SF:
2153 return "%vmovss\t{%1, %0|%0, %1}";
2154 default:
2155 gcc_unreachable ();
2156 }
2157
2158 case TYPE_MMX:
2159 return "pxor\t%0, %0";
2160
2161 case TYPE_MMXMOV:
2162 if (get_attr_mode (insn) == MODE_DI)
2163 return "movq\t{%1, %0|%0, %1}";
2164 return "movd\t{%1, %0|%0, %1}";
2165
2166 case TYPE_LEA:
2167 return "lea{l}\t{%E1, %0|%0, %E1}";
2168
2169 default:
2170 gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
2171 if (ix86_use_lea_for_mov (insn, operands))
2172 return "lea{l}\t{%E1, %0|%0, %E1}";
2173 else
2174 return "mov{l}\t{%1, %0|%0, %1}";
2175 }
2176}
2177 [(set (attr "type")
2178 (cond [(eq_attr "alternative" "2")
2179 (const_string "mmx")
2180 (eq_attr "alternative" "3,4,5")
2181 (const_string "mmxmov")
2182 (eq_attr "alternative" "6")
2183 (const_string "sselog1")
2184 (eq_attr "alternative" "7,8,9,10,11")
2185 (const_string "ssemov")
2186 (match_operand 1 "pic_32bit_operand" "")
2187 (const_string "lea")
2188 ]
2189 (const_string "imov")))
2190 (set (attr "prefix")
2191 (if_then_else (eq_attr "alternative" "0,1,2,3,4,5")
2192 (const_string "orig")
2193 (const_string "maybe_vex")))
2194 (set (attr "prefix_data16")
2195 (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
2196 (const_string "1")
2197 (const_string "*")))
2198 (set (attr "mode")
2199 (cond [(eq_attr "alternative" "2,3")
2200 (const_string "DI")
2201 (eq_attr "alternative" "6,7")
2202 (if_then_else
2203 (not (match_test "TARGET_SSE2"))
2204 (const_string "V4SF")
2205 (const_string "TI"))
2206 (and (eq_attr "alternative" "8,9,10,11")
2207 (not (match_test "TARGET_SSE2")))
2208 (const_string "SF")
2209 ]
2210 (const_string "SI")))])
2211
2212(define_insn "*movhi_internal"
2213 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
2214 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
2215 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
2216{
2217 switch (get_attr_type (insn))
2218 {
2219 case TYPE_IMOVX:
2220 /* movzwl is faster than movw on p2 due to partial word stalls,
2221 though not as fast as an aligned movl. */
2222 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
2223 default:
2224 if (get_attr_mode (insn) == MODE_SI)
2225 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2226 else
2227 return "mov{w}\t{%1, %0|%0, %1}";
2228 }
2229}
2230 [(set (attr "type")
2231 (cond [(match_test "optimize_function_for_size_p (cfun)")
2232 (const_string "imov")
2233 (and (eq_attr "alternative" "0")
2234 (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
2235 (not (match_test "TARGET_HIMODE_MATH"))))
2236 (const_string "imov")
2237 (and (eq_attr "alternative" "1,2")
2238 (match_operand:HI 1 "aligned_operand" ""))
2239 (const_string "imov")
2240 (and (match_test "TARGET_MOVX")
2241 (eq_attr "alternative" "0,2"))
2242 (const_string "imovx")
2243 ]
2244 (const_string "imov")))
2245 (set (attr "mode")
2246 (cond [(eq_attr "type" "imovx")
2247 (const_string "SI")
2248 (and (eq_attr "alternative" "1,2")
2249 (match_operand:HI 1 "aligned_operand" ""))
2250 (const_string "SI")
2251 (and (eq_attr "alternative" "0")
2252 (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
2253 (not (match_test "TARGET_HIMODE_MATH"))))
2254 (const_string "SI")
2255 ]
2256 (const_string "HI")))])
2257
2258;; Situation is quite tricky about when to choose full sized (SImode) move
2259;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
2260;; partial register dependency machines (such as AMD Athlon), where QImode
2261;; moves issue extra dependency and for partial register stalls machines
2262;; that don't use QImode patterns (and QImode move cause stall on the next
2263;; instruction).
2264;;
2265;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
2266;; register stall machines with, where we use QImode instructions, since
2267;; partial register stall can be caused there. Then we use movzx.
2268(define_insn "*movqi_internal"
2269 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
2270 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
2271 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
2272{
2273 switch (get_attr_type (insn))
2274 {
2275 case TYPE_IMOVX:
2276 gcc_assert (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]));
2277 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
2278 default:
2279 if (get_attr_mode (insn) == MODE_SI)
2280 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2281 else
2282 return "mov{b}\t{%1, %0|%0, %1}";
2283 }
2284}
2285 [(set (attr "type")
2286 (cond [(and (eq_attr "alternative" "5")
2287 (not (match_operand:QI 1 "aligned_operand" "")))
2288 (const_string "imovx")
2289 (match_test "optimize_function_for_size_p (cfun)")
2290 (const_string "imov")
2291 (and (eq_attr "alternative" "3")
2292 (ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
2293 (not (match_test "TARGET_QIMODE_MATH"))))
2294 (const_string "imov")
2295 (eq_attr "alternative" "3,5")
2296 (const_string "imovx")
2297 (and (match_test "TARGET_MOVX")
2298 (eq_attr "alternative" "2"))
2299 (const_string "imovx")
2300 ]
2301 (const_string "imov")))
2302 (set (attr "mode")
2303 (cond [(eq_attr "alternative" "3,4,5")
2304 (const_string "SI")
2305 (eq_attr "alternative" "6")
2306 (const_string "QI")
2307 (eq_attr "type" "imovx")
2308 (const_string "SI")
2309 (and (eq_attr "type" "imov")
2310 (and (eq_attr "alternative" "0,1")
2311 (and (match_test "TARGET_PARTIAL_REG_DEPENDENCY")
2312 (and (not (match_test "optimize_function_for_size_p (cfun)"))
2313 (not (match_test "TARGET_PARTIAL_REG_STALL"))))))
2314 (const_string "SI")
2315 ;; Avoid partial register stalls when not using QImode arithmetic
2316 (and (eq_attr "type" "imov")
2317 (and (eq_attr "alternative" "0,1")
2318 (and (match_test "TARGET_PARTIAL_REG_STALL")
2319 (not (match_test "TARGET_QIMODE_MATH")))))
2320 (const_string "SI")
2321 ]
2322 (const_string "QI")))])
2323
2324;; Stores and loads of ax to arbitrary constant address.
2325;; We fake an second form of instruction to force reload to load address
2326;; into register when rax is not available
2327(define_insn "*movabs<mode>_1"
2328 [(set (mem:SWI1248x (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2329 (match_operand:SWI1248x 1 "nonmemory_operand" "a,r<i>"))]
2330 "TARGET_LP64 && ix86_check_movabs (insn, 0)"
2331 "@
5ce9237c 2332 movabs{<imodesuffix>}\t{%1, %P0|[%P0], %1}
95d28233 2333 mov{<imodesuffix>}\t{%1, %a0|<iptrsize> PTR %a0, %1}"
e4b17023
JM
2334 [(set_attr "type" "imov")
2335 (set_attr "modrm" "0,*")
2336 (set_attr "length_address" "8,0")
2337 (set_attr "length_immediate" "0,*")
2338 (set_attr "memory" "store")
2339 (set_attr "mode" "<MODE>")])
2340
2341(define_insn "*movabs<mode>_2"
2342 [(set (match_operand:SWI1248x 0 "register_operand" "=a,r")
2343 (mem:SWI1248x (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2344 "TARGET_LP64 && ix86_check_movabs (insn, 1)"
2345 "@
5ce9237c 2346 movabs{<imodesuffix>}\t{%P1, %0|%0, [%P1]}
95d28233 2347 mov{<imodesuffix>}\t{%a1, %0|%0, <iptrsize> PTR %a1}"
e4b17023
JM
2348 [(set_attr "type" "imov")
2349 (set_attr "modrm" "0,*")
2350 (set_attr "length_address" "8,0")
2351 (set_attr "length_immediate" "0")
2352 (set_attr "memory" "load")
2353 (set_attr "mode" "<MODE>")])
2354
2355(define_insn "*swap<mode>"
2356 [(set (match_operand:SWI48 0 "register_operand" "+r")
2357 (match_operand:SWI48 1 "register_operand" "+r"))
2358 (set (match_dup 1)
2359 (match_dup 0))]
2360 ""
2361 "xchg{<imodesuffix>}\t%1, %0"
2362 [(set_attr "type" "imov")
2363 (set_attr "mode" "<MODE>")
2364 (set_attr "pent_pair" "np")
2365 (set_attr "athlon_decode" "vector")
2366 (set_attr "amdfam10_decode" "double")
2367 (set_attr "bdver1_decode" "double")])
2368
2369(define_insn "*swap<mode>_1"
2370 [(set (match_operand:SWI12 0 "register_operand" "+r")
2371 (match_operand:SWI12 1 "register_operand" "+r"))
2372 (set (match_dup 1)
2373 (match_dup 0))]
2374 "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
2375 "xchg{l}\t%k1, %k0"
2376 [(set_attr "type" "imov")
2377 (set_attr "mode" "SI")
2378 (set_attr "pent_pair" "np")
2379 (set_attr "athlon_decode" "vector")
2380 (set_attr "amdfam10_decode" "double")
2381 (set_attr "bdver1_decode" "double")])
2382
2383;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL
2384;; is disabled for AMDFAM10
2385(define_insn "*swap<mode>_2"
2386 [(set (match_operand:SWI12 0 "register_operand" "+<r>")
2387 (match_operand:SWI12 1 "register_operand" "+<r>"))
2388 (set (match_dup 1)
2389 (match_dup 0))]
2390 "TARGET_PARTIAL_REG_STALL"
2391 "xchg{<imodesuffix>}\t%1, %0"
2392 [(set_attr "type" "imov")
2393 (set_attr "mode" "<MODE>")
2394 (set_attr "pent_pair" "np")
2395 (set_attr "athlon_decode" "vector")])
2396
2397(define_expand "movstrict<mode>"
2398 [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand" ""))
2399 (match_operand:SWI12 1 "general_operand" ""))]
2400 ""
2401{
2402 if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
2403 FAIL;
2404 if (GET_CODE (operands[0]) == SUBREG
2405 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (operands[0]))) != MODE_INT)
2406 FAIL;
2407 /* Don't generate memory->memory moves, go through a register */
2408 if (MEM_P (operands[0]) && MEM_P (operands[1]))
2409 operands[1] = force_reg (<MODE>mode, operands[1]);
2410})
2411
2412(define_insn "*movstrict<mode>_1"
2413 [(set (strict_low_part
2414 (match_operand:SWI12 0 "nonimmediate_operand" "+<r>m,<r>"))
2415 (match_operand:SWI12 1 "general_operand" "<r>n,m"))]
2416 "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
2417 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
2418 "mov{<imodesuffix>}\t{%1, %0|%0, %1}"
2419 [(set_attr "type" "imov")
2420 (set_attr "mode" "<MODE>")])
2421
2422(define_insn "*movstrict<mode>_xor"
2423 [(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>"))
2424 (match_operand:SWI12 1 "const0_operand" ""))
2425 (clobber (reg:CC FLAGS_REG))]
2426 "reload_completed"
2427 "xor{<imodesuffix>}\t%0, %0"
2428 [(set_attr "type" "alu1")
2429 (set_attr "mode" "<MODE>")
2430 (set_attr "length_immediate" "0")])
2431
2432(define_insn "*mov<mode>_extv_1"
2433 [(set (match_operand:SWI24 0 "register_operand" "=R")
2434 (sign_extract:SWI24 (match_operand 1 "ext_register_operand" "Q")
2435 (const_int 8)
2436 (const_int 8)))]
2437 ""
2438 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
2439 [(set_attr "type" "imovx")
2440 (set_attr "mode" "SI")])
2441
2442(define_insn "*movqi_extv_1_rex64"
2443 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2444 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2445 (const_int 8)
2446 (const_int 8)))]
2447 "TARGET_64BIT"
2448{
2449 switch (get_attr_type (insn))
2450 {
2451 case TYPE_IMOVX:
2452 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
2453 default:
2454 return "mov{b}\t{%h1, %0|%0, %h1}";
2455 }
2456}
2457 [(set (attr "type")
2458 (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
2459 (match_test "TARGET_MOVX"))
2460 (const_string "imovx")
2461 (const_string "imov")))
2462 (set (attr "mode")
2463 (if_then_else (eq_attr "type" "imovx")
2464 (const_string "SI")
2465 (const_string "QI")))])
2466
2467(define_insn "*movqi_extv_1"
2468 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
2469 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
2470 (const_int 8)
2471 (const_int 8)))]
2472 "!TARGET_64BIT"
2473{
2474 switch (get_attr_type (insn))
2475 {
2476 case TYPE_IMOVX:
2477 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
2478 default:
2479 return "mov{b}\t{%h1, %0|%0, %h1}";
2480 }
2481}
2482 [(set (attr "type")
2483 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2484 (ior (not (match_operand:QI 0 "QIreg_operand" ""))
2485 (match_test "TARGET_MOVX")))
2486 (const_string "imovx")
2487 (const_string "imov")))
2488 (set (attr "mode")
2489 (if_then_else (eq_attr "type" "imovx")
2490 (const_string "SI")
2491 (const_string "QI")))])
2492
2493(define_insn "*mov<mode>_extzv_1"
2494 [(set (match_operand:SWI48 0 "register_operand" "=R")
2495 (zero_extract:SWI48 (match_operand 1 "ext_register_operand" "Q")
2496 (const_int 8)
2497 (const_int 8)))]
2498 ""
2499 "movz{bl|x}\t{%h1, %k0|%k0, %h1}"
2500 [(set_attr "type" "imovx")
2501 (set_attr "mode" "SI")])
2502
2503(define_insn "*movqi_extzv_2_rex64"
2504 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
2505 (subreg:QI
2506 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2507 (const_int 8)
2508 (const_int 8)) 0))]
2509 "TARGET_64BIT"
2510{
2511 switch (get_attr_type (insn))
2512 {
2513 case TYPE_IMOVX:
2514 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
2515 default:
2516 return "mov{b}\t{%h1, %0|%0, %h1}";
2517 }
2518}
2519 [(set (attr "type")
2520 (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
2521 (match_test "TARGET_MOVX"))
2522 (const_string "imovx")
2523 (const_string "imov")))
2524 (set (attr "mode")
2525 (if_then_else (eq_attr "type" "imovx")
2526 (const_string "SI")
2527 (const_string "QI")))])
2528
2529(define_insn "*movqi_extzv_2"
2530 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
2531 (subreg:QI
2532 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
2533 (const_int 8)
2534 (const_int 8)) 0))]
2535 "!TARGET_64BIT"
2536{
2537 switch (get_attr_type (insn))
2538 {
2539 case TYPE_IMOVX:
2540 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
2541 default:
2542 return "mov{b}\t{%h1, %0|%0, %h1}";
2543 }
2544}
2545 [(set (attr "type")
2546 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2547 (ior (not (match_operand:QI 0 "QIreg_operand" ""))
2548 (match_test "TARGET_MOVX")))
2549 (const_string "imovx")
2550 (const_string "imov")))
2551 (set (attr "mode")
2552 (if_then_else (eq_attr "type" "imovx")
2553 (const_string "SI")
2554 (const_string "QI")))])
2555
2556(define_expand "mov<mode>_insv_1"
2557 [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "")
2558 (const_int 8)
2559 (const_int 8))
2560 (match_operand:SWI48 1 "nonmemory_operand" ""))])
2561
2562(define_insn "*mov<mode>_insv_1_rex64"
2563 [(set (zero_extract:SWI48x (match_operand 0 "ext_register_operand" "+Q")
2564 (const_int 8)
2565 (const_int 8))
2566 (match_operand:SWI48x 1 "nonmemory_operand" "Qn"))]
2567 "TARGET_64BIT"
2568{
2569 if (CONST_INT_P (operands[1]))
2570 operands[1] = simplify_gen_subreg (QImode, operands[1], <MODE>mode, 0);
2571 return "mov{b}\t{%b1, %h0|%h0, %b1}";
2572}
2573 [(set_attr "type" "imov")
2574 (set_attr "mode" "QI")])
2575
2576(define_insn "*movsi_insv_1"
2577 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2578 (const_int 8)
2579 (const_int 8))
2580 (match_operand:SI 1 "general_operand" "Qmn"))]
2581 "!TARGET_64BIT"
2582{
2583 if (CONST_INT_P (operands[1]))
2584 operands[1] = simplify_gen_subreg (QImode, operands[1], SImode, 0);
2585 return "mov{b}\t{%b1, %h0|%h0, %b1}";
2586}
2587 [(set_attr "type" "imov")
2588 (set_attr "mode" "QI")])
2589
2590(define_insn "*movqi_insv_2"
2591 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
2592 (const_int 8)
2593 (const_int 8))
2594 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
2595 (const_int 8)))]
2596 ""
2597 "mov{b}\t{%h1, %h0|%h0, %h1}"
2598 [(set_attr "type" "imov")
2599 (set_attr "mode" "QI")])
2600\f
2601;; Floating point push instructions.
2602
2603(define_insn "*pushtf"
2604 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2605 (match_operand:TF 1 "general_no_elim_operand" "x,Fo,*r"))]
2606 "TARGET_SSE2"
2607{
2608 /* This insn should be already split before reg-stack. */
2609 gcc_unreachable ();
2610}
2611 [(set_attr "type" "multi")
2612 (set_attr "unit" "sse,*,*")
2613 (set_attr "mode" "TF,SI,SI")])
2614
2615;; %%% Kill this when call knows how to work this out.
2616(define_split
2617 [(set (match_operand:TF 0 "push_operand" "")
2618 (match_operand:TF 1 "sse_reg_operand" ""))]
2619 "TARGET_SSE2 && reload_completed"
2620 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -16)))
2621 (set (mem:TF (reg:P SP_REG)) (match_dup 1))])
2622
2623(define_insn "*pushxf"
2624 [(set (match_operand:XF 0 "push_operand" "=<,<")
2625 (match_operand:XF 1 "general_no_elim_operand" "f,ro"))]
2626 "optimize_function_for_speed_p (cfun)"
2627{
2628 /* This insn should be already split before reg-stack. */
2629 gcc_unreachable ();
2630}
2631 [(set_attr "type" "multi")
2632 (set_attr "unit" "i387,*")
2633 (set_attr "mode" "XF,SI")])
2634
2635;; Size of pushxf is 3 (for sub) + 2 (for fstp) + memory operand size.
2636;; Size of pushxf using integer instructions is 3+3*memory operand size
2637;; Pushing using integer instructions is longer except for constants
2638;; and direct memory references (assuming that any given constant is pushed
2639;; only once, but this ought to be handled elsewhere).
2640
2641(define_insn "*pushxf_nointeger"
2642 [(set (match_operand:XF 0 "push_operand" "=<,<")
2643 (match_operand:XF 1 "general_no_elim_operand" "f,*rFo"))]
2644 "optimize_function_for_size_p (cfun)"
2645{
2646 /* This insn should be already split before reg-stack. */
2647 gcc_unreachable ();
2648}
2649 [(set_attr "type" "multi")
2650 (set_attr "unit" "i387,*")
2651 (set_attr "mode" "XF,SI")])
2652
2653;; %%% Kill this when call knows how to work this out.
2654(define_split
2655 [(set (match_operand:XF 0 "push_operand" "")
2656 (match_operand:XF 1 "fp_register_operand" ""))]
2657 "reload_completed"
2658 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
2659 (set (mem:XF (reg:P SP_REG)) (match_dup 1))]
2660 "operands[2] = GEN_INT (-GET_MODE_SIZE (XFmode));")
2661
2662(define_insn "*pushdf_rex64"
2663 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2664 (match_operand:DF 1 "general_no_elim_operand" "f,Yd*rFm,x"))]
2665 "TARGET_64BIT"
2666{
2667 /* This insn should be already split before reg-stack. */
2668 gcc_unreachable ();
2669}
2670 [(set_attr "type" "multi")
2671 (set_attr "unit" "i387,*,*")
2672 (set_attr "mode" "DF,DI,DF")])
2673
2674;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2675;; Size of pushdf using integer instructions is 2+2*memory operand size
2676;; On the average, pushdf using integers can be still shorter.
2677
2678(define_insn "*pushdf"
2679 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2680 (match_operand:DF 1 "general_no_elim_operand" "f,Yd*rFo,x"))]
2681 "!TARGET_64BIT"
2682{
2683 /* This insn should be already split before reg-stack. */
2684 gcc_unreachable ();
2685}
2686 [(set_attr "isa" "*,*,sse2")
2687 (set_attr "type" "multi")
2688 (set_attr "unit" "i387,*,*")
2689 (set_attr "mode" "DF,DI,DF")])
2690
2691;; %%% Kill this when call knows how to work this out.
2692(define_split
2693 [(set (match_operand:DF 0 "push_operand" "")
2694 (match_operand:DF 1 "any_fp_register_operand" ""))]
2695 "reload_completed"
2696 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
2697 (set (mem:DF (reg:P SP_REG)) (match_dup 1))])
2698
2699(define_insn "*pushsf_rex64"
2700 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2701 (match_operand:SF 1 "nonmemory_no_elim_operand" "f,rF,x"))]
2702 "TARGET_64BIT"
2703{
2704 /* Anything else should be already split before reg-stack. */
2705 gcc_assert (which_alternative == 1);
2706 return "push{q}\t%q1";
2707}
2708 [(set_attr "type" "multi,push,multi")
2709 (set_attr "unit" "i387,*,*")
2710 (set_attr "mode" "SF,DI,SF")])
2711
2712(define_insn "*pushsf"
2713 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2714 (match_operand:SF 1 "general_no_elim_operand" "f,rFm,x"))]
2715 "!TARGET_64BIT"
2716{
2717 /* Anything else should be already split before reg-stack. */
2718 gcc_assert (which_alternative == 1);
2719 return "push{l}\t%1";
2720}
2721 [(set_attr "type" "multi,push,multi")
2722 (set_attr "unit" "i387,*,*")
2723 (set_attr "mode" "SF,SI,SF")])
2724
2725;; %%% Kill this when call knows how to work this out.
2726(define_split
2727 [(set (match_operand:SF 0 "push_operand" "")
2728 (match_operand:SF 1 "any_fp_register_operand" ""))]
2729 "reload_completed"
2730 [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
2731 (set (mem:SF (reg:P SP_REG)) (match_dup 1))]
2732 "operands[2] = GEN_INT (-GET_MODE_SIZE (<P:MODE>mode));")
2733
2734(define_split
2735 [(set (match_operand:SF 0 "push_operand" "")
2736 (match_operand:SF 1 "memory_operand" ""))]
2737 "reload_completed
2738 && (operands[2] = find_constant_src (insn))"
2739 [(set (match_dup 0) (match_dup 2))])
2740
2741(define_split
2742 [(set (match_operand 0 "push_operand" "")
2743 (match_operand 1 "general_operand" ""))]
2744 "reload_completed
2745 && (GET_MODE (operands[0]) == TFmode
2746 || GET_MODE (operands[0]) == XFmode
2747 || GET_MODE (operands[0]) == DFmode)
2748 && !ANY_FP_REG_P (operands[1])"
2749 [(const_int 0)]
2750 "ix86_split_long_move (operands); DONE;")
2751\f
2752;; Floating point move instructions.
2753
2754(define_expand "movtf"
2755 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2756 (match_operand:TF 1 "nonimmediate_operand" ""))]
5ce9237c 2757 "TARGET_64BIT || TARGET_SSE2"
e4b17023
JM
2758{
2759 ix86_expand_move (TFmode, operands);
2760 DONE;
2761})
2762
2763(define_expand "mov<mode>"
2764 [(set (match_operand:X87MODEF 0 "nonimmediate_operand" "")
2765 (match_operand:X87MODEF 1 "general_operand" ""))]
2766 ""
2767 "ix86_expand_move (<MODE>mode, operands); DONE;")
2768
5ce9237c 2769(define_insn "*movtf_internal_rex64"
e4b17023 2770 [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?*r ,!o")
5ce9237c
JM
2771 (match_operand:TF 1 "general_operand" "xm,x,C,*roF,*r"))]
2772 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
e4b17023
JM
2773 && (!can_create_pseudo_p ()
2774 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2775 || GET_CODE (operands[1]) != CONST_DOUBLE
2776 || (optimize_function_for_size_p (cfun)
2777 && standard_sse_constant_p (operands[1])
2778 && !memory_operand (operands[0], TFmode))
2779 || (!TARGET_MEMORY_MISMATCH_STALL
2780 && memory_operand (operands[0], TFmode)))"
2781{
2782 switch (which_alternative)
2783 {
2784 case 0:
2785 case 1:
2786 /* Handle misaligned load/store since we
2787 don't have movmisaligntf pattern. */
2788 if (misaligned_operand (operands[0], TFmode)
2789 || misaligned_operand (operands[1], TFmode))
2790 {
2791 if (get_attr_mode (insn) == MODE_V4SF)
2792 return "%vmovups\t{%1, %0|%0, %1}";
2793 else
2794 return "%vmovdqu\t{%1, %0|%0, %1}";
2795 }
2796 else
2797 {
2798 if (get_attr_mode (insn) == MODE_V4SF)
2799 return "%vmovaps\t{%1, %0|%0, %1}";
2800 else
2801 return "%vmovdqa\t{%1, %0|%0, %1}";
2802 }
2803
2804 case 2:
2805 return standard_sse_constant_opcode (insn, operands[1]);
2806
2807 case 3:
2808 case 4:
2809 return "#";
2810
2811 default:
2812 gcc_unreachable ();
2813 }
2814}
2815 [(set_attr "type" "ssemov,ssemov,sselog1,*,*")
2816 (set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,*,*")
2817 (set (attr "mode")
2818 (cond [(eq_attr "alternative" "0,2")
2819 (if_then_else
2820 (match_test "optimize_function_for_size_p (cfun)")
2821 (const_string "V4SF")
2822 (const_string "TI"))
2823 (eq_attr "alternative" "1")
2824 (if_then_else
2825 (ior (match_test "TARGET_SSE_TYPELESS_STORES")
2826 (match_test "optimize_function_for_size_p (cfun)"))
2827 (const_string "V4SF")
2828 (const_string "TI"))]
2829 (const_string "DI")))])
2830
5ce9237c
JM
2831(define_insn "*movtf_internal_sse2"
2832 [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x")
2833 (match_operand:TF 1 "general_operand" "xm,x,C"))]
2834 "TARGET_SSE2 && !TARGET_64BIT
2835 && !(MEM_P (operands[0]) && MEM_P (operands[1]))
2836 && (!can_create_pseudo_p ()
2837 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2838 || GET_CODE (operands[1]) != CONST_DOUBLE
2839 || (optimize_function_for_size_p (cfun)
2840 && standard_sse_constant_p (operands[1])
2841 && !memory_operand (operands[0], TFmode))
2842 || (!TARGET_MEMORY_MISMATCH_STALL
2843 && memory_operand (operands[0], TFmode)))"
2844{
2845 switch (which_alternative)
2846 {
2847 case 0:
2848 case 1:
2849 /* Handle misaligned load/store since we
2850 don't have movmisaligntf pattern. */
2851 if (misaligned_operand (operands[0], TFmode)
2852 || misaligned_operand (operands[1], TFmode))
2853 {
2854 if (get_attr_mode (insn) == MODE_V4SF)
2855 return "%vmovups\t{%1, %0|%0, %1}";
2856 else
2857 return "%vmovdqu\t{%1, %0|%0, %1}";
2858 }
2859 else
2860 {
2861 if (get_attr_mode (insn) == MODE_V4SF)
2862 return "%vmovaps\t{%1, %0|%0, %1}";
2863 else
2864 return "%vmovdqa\t{%1, %0|%0, %1}";
2865 }
2866
2867 case 2:
2868 return standard_sse_constant_opcode (insn, operands[1]);
2869
2870 default:
2871 gcc_unreachable ();
2872 }
2873}
2874 [(set_attr "type" "ssemov,ssemov,sselog1")
2875 (set_attr "prefix" "maybe_vex")
2876 (set (attr "mode")
2877 (cond [(eq_attr "alternative" "0,2")
2878 (if_then_else
2879 (match_test "optimize_function_for_size_p (cfun)")
2880 (const_string "V4SF")
2881 (const_string "TI"))
2882 (eq_attr "alternative" "1")
2883 (if_then_else
2884 (ior (match_test "TARGET_SSE_TYPELESS_STORES")
2885 (match_test "optimize_function_for_size_p (cfun)"))
2886 (const_string "V4SF")
2887 (const_string "TI"))]
2888 (const_string "DI")))])
2889
2890(define_insn "*movxf_internal_rex64"
2891 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,?Yx*r ,!o")
2892 (match_operand:XF 1 "general_operand" "fm,f,G,Yx*roF,Yx*rC"))]
2893 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
2894 && (!can_create_pseudo_p ()
2895 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2896 || GET_CODE (operands[1]) != CONST_DOUBLE
2897 || (optimize_function_for_size_p (cfun)
2898 && standard_80387_constant_p (operands[1]) > 0
2899 && !memory_operand (operands[0], XFmode))
2900 || (!TARGET_MEMORY_MISMATCH_STALL
2901 && memory_operand (operands[0], XFmode)))"
2902{
2903 switch (which_alternative)
2904 {
2905 case 0:
2906 case 1:
2907 return output_387_reg_move (insn, operands);
2908
2909 case 2:
2910 return standard_80387_constant_opcode (operands[1]);
2911
2912 case 3:
2913 case 4:
2914 return "#";
2915
2916 default:
2917 gcc_unreachable ();
2918 }
2919}
2920 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2921 (set_attr "mode" "XF,XF,XF,SI,SI")])
2922
e4b17023
JM
2923;; Possible store forwarding (partial memory) stall in alternative 4.
2924(define_insn "*movxf_internal"
2925 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,?Yx*r ,!o")
5ce9237c
JM
2926 (match_operand:XF 1 "general_operand" "fm,f,G,Yx*roF,Yx*rF"))]
2927 "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
e4b17023
JM
2928 && (!can_create_pseudo_p ()
2929 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2930 || GET_CODE (operands[1]) != CONST_DOUBLE
2931 || (optimize_function_for_size_p (cfun)
2932 && standard_80387_constant_p (operands[1]) > 0
2933 && !memory_operand (operands[0], XFmode))
2934 || (!TARGET_MEMORY_MISMATCH_STALL
2935 && memory_operand (operands[0], XFmode)))"
2936{
2937 switch (which_alternative)
2938 {
2939 case 0:
2940 case 1:
2941 return output_387_reg_move (insn, operands);
2942
2943 case 2:
2944 return standard_80387_constant_opcode (operands[1]);
2945
2946 case 3:
2947 case 4:
2948 return "#";
2949
2950 default:
2951 gcc_unreachable ();
2952 }
2953}
2954 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2955 (set_attr "mode" "XF,XF,XF,SI,SI")])
2956
2957(define_insn "*movdf_internal_rex64"
2958 [(set (match_operand:DF 0 "nonimmediate_operand"
5ce9237c 2959 "=?Yf*f,?m ,?Yf*f,?r,?m,?r,?r,x,x,x,m,Yi,r ")
e4b17023 2960 (match_operand:DF 1 "general_operand"
5ce9237c 2961 "Yf*fm ,Yf*f ,G ,rm,rC,C ,F ,C,x,m,x,r ,Yi"))]
e4b17023
JM
2962 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
2963 && (!can_create_pseudo_p ()
2964 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2965 || GET_CODE (operands[1]) != CONST_DOUBLE
2966 || (optimize_function_for_size_p (cfun)
2967 && ((!(TARGET_SSE2 && TARGET_SSE_MATH)
2968 && standard_80387_constant_p (operands[1]) > 0)
2969 || (TARGET_SSE2 && TARGET_SSE_MATH
2970 && standard_sse_constant_p (operands[1]))))
2971 || memory_operand (operands[0], DFmode))"
2972{
2973 switch (which_alternative)
2974 {
2975 case 0:
2976 case 1:
2977 return output_387_reg_move (insn, operands);
2978
2979 case 2:
2980 return standard_80387_constant_opcode (operands[1]);
2981
2982 case 3:
2983 case 4:
2984 return "mov{q}\t{%1, %0|%0, %1}";
2985
2986 case 5:
5ce9237c 2987 return "mov{l}\t{%1, %k0|%k0, %1}";
e4b17023
JM
2988
2989 case 6:
5ce9237c 2990 return "movabs{q}\t{%1, %0|%0, %1}";
e4b17023
JM
2991
2992 case 7:
2993 return standard_sse_constant_opcode (insn, operands[1]);
2994
2995 case 8:
2996 case 9:
2997 case 10:
2998 switch (get_attr_mode (insn))
2999 {
3000 case MODE_V2DF:
3001 if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
3002 return "%vmovapd\t{%1, %0|%0, %1}";
3003 case MODE_V4SF:
3004 return "%vmovaps\t{%1, %0|%0, %1}";
3005
3006 case MODE_DI:
3007 return "%vmovq\t{%1, %0|%0, %1}";
3008 case MODE_DF:
3009 if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
3010 return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
3011 return "%vmovsd\t{%1, %0|%0, %1}";
3012 case MODE_V1DF:
3013 return "%vmovlpd\t{%1, %d0|%d0, %1}";
3014 case MODE_V2SF:
3015 return "%vmovlps\t{%1, %d0|%d0, %1}";
3016 default:
3017 gcc_unreachable ();
3018 }
3019
3020 case 11:
3021 case 12:
3022 /* Handle broken assemblers that require movd instead of movq. */
3023 return "%vmovd\t{%1, %0|%0, %1}";
3024
3025 default:
3026 gcc_unreachable();
3027 }
3028}
3029 [(set (attr "type")
3030 (cond [(eq_attr "alternative" "0,1,2")
3031 (const_string "fmov")
5ce9237c 3032 (eq_attr "alternative" "3,4,5,6")
e4b17023 3033 (const_string "imov")
e4b17023
JM
3034 (eq_attr "alternative" "7")
3035 (const_string "sselog1")
3036 ]
3037 (const_string "ssemov")))
3038 (set (attr "modrm")
3039 (if_then_else
5ce9237c 3040 (and (eq_attr "alternative" "6") (eq_attr "type" "imov"))
e4b17023
JM
3041 (const_string "0")
3042 (const_string "*")))
3043 (set (attr "length_immediate")
3044 (if_then_else
5ce9237c 3045 (and (eq_attr "alternative" "6") (eq_attr "type" "imov"))
e4b17023
JM
3046 (const_string "8")
3047 (const_string "*")))
3048 (set (attr "prefix")
3049 (if_then_else (eq_attr "alternative" "0,1,2,3,4,5,6")
3050 (const_string "orig")
3051 (const_string "maybe_vex")))
3052 (set (attr "prefix_data16")
3053 (if_then_else (eq_attr "mode" "V1DF")
3054 (const_string "1")
3055 (const_string "*")))
3056 (set (attr "mode")
3057 (cond [(eq_attr "alternative" "0,1,2")
3058 (const_string "DF")
5ce9237c 3059 (eq_attr "alternative" "3,4,6,11,12")
e4b17023 3060 (const_string "DI")
5ce9237c
JM
3061 (eq_attr "alternative" "5")
3062 (const_string "SI")
e4b17023
JM
3063
3064 /* xorps is one byte shorter. */
3065 (eq_attr "alternative" "7")
3066 (cond [(match_test "optimize_function_for_size_p (cfun)")
3067 (const_string "V4SF")
3068 (match_test "TARGET_SSE_LOAD0_BY_PXOR")
3069 (const_string "TI")
3070 ]
3071 (const_string "V2DF"))
3072
3073 /* For architectures resolving dependencies on
3074 whole SSE registers use APD move to break dependency
3075 chains, otherwise use short move to avoid extra work.
3076
3077 movaps encodes one byte shorter. */
3078 (eq_attr "alternative" "8")
3079 (cond
3080 [(match_test "optimize_function_for_size_p (cfun)")
3081 (const_string "V4SF")
3082 (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
3083 (const_string "V2DF")
3084 ]
3085 (const_string "DF"))
3086 /* For architectures resolving dependencies on register
3087 parts we may avoid extra work to zero out upper part
3088 of register. */
3089 (eq_attr "alternative" "9")
3090 (if_then_else
3091 (match_test "TARGET_SSE_SPLIT_REGS")
3092 (const_string "V1DF")
3093 (const_string "DF"))
3094 ]
3095 (const_string "DF")))])
3096
3097;; Possible store forwarding (partial memory) stall in alternative 4.
3098(define_insn "*movdf_internal"
3099 [(set (match_operand:DF 0 "nonimmediate_operand"
5ce9237c 3100 "=Yf*f,m ,Yf*f,?Yd*r ,!o ,x,x,x,m,*x,*x,*x,m")
e4b17023 3101 (match_operand:DF 1 "general_operand"
5ce9237c 3102 "Yf*fm,Yf*f,G ,Yd*roF,Yd*rF,C,x,m,x,C ,*x,m ,*x"))]
e4b17023
JM
3103 "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
3104 && (!can_create_pseudo_p ()
3105 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
3106 || GET_CODE (operands[1]) != CONST_DOUBLE
3107 || (optimize_function_for_size_p (cfun)
3108 && ((!(TARGET_SSE2 && TARGET_SSE_MATH)
3109 && standard_80387_constant_p (operands[1]) > 0)
3110 || (TARGET_SSE2 && TARGET_SSE_MATH
3111 && standard_sse_constant_p (operands[1])))
3112 && !memory_operand (operands[0], DFmode))
3113 || (!TARGET_MEMORY_MISMATCH_STALL
3114 && memory_operand (operands[0], DFmode)))"
3115{
3116 switch (which_alternative)
3117 {
3118 case 0:
3119 case 1:
3120 return output_387_reg_move (insn, operands);
3121
3122 case 2:
3123 return standard_80387_constant_opcode (operands[1]);
3124
3125 case 3:
3126 case 4:
3127 return "#";
3128
3129 case 5:
3130 case 9:
3131 return standard_sse_constant_opcode (insn, operands[1]);
3132
3133 case 6:
3134 case 7:
3135 case 8:
3136 case 10:
3137 case 11:
3138 case 12:
3139 switch (get_attr_mode (insn))
3140 {
3141 case MODE_V2DF:
3142 if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
3143 return "%vmovapd\t{%1, %0|%0, %1}";
3144 case MODE_V4SF:
3145 return "%vmovaps\t{%1, %0|%0, %1}";
3146
3147 case MODE_DI:
3148 return "%vmovq\t{%1, %0|%0, %1}";
3149 case MODE_DF:
3150 if (TARGET_AVX && REG_P (operands[0]) && REG_P (operands[1]))
3151 return "vmovsd\t{%1, %0, %0|%0, %0, %1}";
3152 return "%vmovsd\t{%1, %0|%0, %1}";
3153 case MODE_V1DF:
3154 return "%vmovlpd\t{%1, %d0|%d0, %1}";
3155 case MODE_V2SF:
3156 return "%vmovlps\t{%1, %d0|%d0, %1}";
3157 default:
3158 gcc_unreachable ();
3159 }
3160
3161 default:
3162 gcc_unreachable ();
3163 }
3164}
3165 [(set (attr "isa")
3166 (if_then_else (eq_attr "alternative" "5,6,7,8")
3167 (const_string "sse2")
3168 (const_string "*")))
3169 (set (attr "type")
3170 (cond [(eq_attr "alternative" "0,1,2")
3171 (const_string "fmov")
3172 (eq_attr "alternative" "3,4")
3173 (const_string "multi")
3174 (eq_attr "alternative" "5,9")
3175 (const_string "sselog1")
3176 ]
3177 (const_string "ssemov")))
3178 (set (attr "prefix")
3179 (if_then_else (eq_attr "alternative" "0,1,2,3,4")
3180 (const_string "orig")
3181 (const_string "maybe_vex")))
3182 (set (attr "prefix_data16")
3183 (if_then_else (eq_attr "mode" "V1DF")
3184 (const_string "1")
3185 (const_string "*")))
3186 (set (attr "mode")
3187 (cond [(eq_attr "alternative" "0,1,2")
3188 (const_string "DF")
3189 (eq_attr "alternative" "3,4")
3190 (const_string "SI")
3191
3192 /* For SSE1, we have many fewer alternatives. */
3193 (not (match_test "TARGET_SSE2"))
3194 (if_then_else
3195 (eq_attr "alternative" "5,6,9,10")
3196 (const_string "V4SF")
3197 (const_string "V2SF"))
3198
3199 /* xorps is one byte shorter. */
3200 (eq_attr "alternative" "5,9")
3201 (cond [(match_test "optimize_function_for_size_p (cfun)")
3202 (const_string "V4SF")
3203 (match_test "TARGET_SSE_LOAD0_BY_PXOR")
3204 (const_string "TI")
3205 ]
3206 (const_string "V2DF"))
3207
3208 /* For architectures resolving dependencies on
3209 whole SSE registers use APD move to break dependency
3210 chains, otherwise use short move to avoid extra work.
3211
3212 movaps encodes one byte shorter. */
3213 (eq_attr "alternative" "6,10")
3214 (cond
3215 [(match_test "optimize_function_for_size_p (cfun)")
3216 (const_string "V4SF")
3217 (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
3218 (const_string "V2DF")
3219 ]
3220 (const_string "DF"))
3221 /* For architectures resolving dependencies on register
3222 parts we may avoid extra work to zero out upper part
3223 of register. */
3224 (eq_attr "alternative" "7,11")
3225 (if_then_else
3226 (match_test "TARGET_SSE_SPLIT_REGS")
3227 (const_string "V1DF")
3228 (const_string "DF"))
3229 ]
3230 (const_string "DF")))])
3231
3232(define_insn "*movsf_internal"
3233 [(set (match_operand:SF 0 "nonimmediate_operand"
5ce9237c 3234 "=Yf*f,m ,Yf*f,?r ,?m,x,x,x,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
e4b17023 3235 (match_operand:SF 1 "general_operand"
5ce9237c 3236 "Yf*fm,Yf*f,G ,rmF,rF,C,x,m,x,m ,*y,*y ,r ,Yi,r ,*Ym"))]
e4b17023
JM
3237 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
3238 && (!can_create_pseudo_p ()
3239 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
3240 || GET_CODE (operands[1]) != CONST_DOUBLE
3241 || (optimize_function_for_size_p (cfun)
3242 && ((!TARGET_SSE_MATH
3243 && standard_80387_constant_p (operands[1]) > 0)
3244 || (TARGET_SSE_MATH
3245 && standard_sse_constant_p (operands[1]))))
3246 || memory_operand (operands[0], SFmode))"
3247{
3248 switch (which_alternative)
3249 {
3250 case 0:
3251 case 1:
3252 return output_387_reg_move (insn, operands);
3253
3254 case 2:
3255 return standard_80387_constant_opcode (operands[1]);
3256
3257 case 3:
3258 case 4:
3259 return "mov{l}\t{%1, %0|%0, %1}";
3260
3261 case 5:
3262 return standard_sse_constant_opcode (insn, operands[1]);
3263
3264 case 6:
3265 if (get_attr_mode (insn) == MODE_V4SF)
3266 return "%vmovaps\t{%1, %0|%0, %1}";
3267 if (TARGET_AVX)
3268 return "vmovss\t{%1, %0, %0|%0, %0, %1}";
3269
3270 case 7:
3271 case 8:
3272 return "%vmovss\t{%1, %0|%0, %1}";
3273
3274 case 9:
3275 case 10:
3276 case 14:
3277 case 15:
3278 return "movd\t{%1, %0|%0, %1}";
3279
3280 case 11:
3281 return "movq\t{%1, %0|%0, %1}";
3282
3283 case 12:
3284 case 13:
3285 return "%vmovd\t{%1, %0|%0, %1}";
3286
3287 default:
3288 gcc_unreachable ();
3289 }
3290}
3291 [(set (attr "type")
3292 (cond [(eq_attr "alternative" "0,1,2")
3293 (const_string "fmov")
3294 (eq_attr "alternative" "3,4")
5ce9237c 3295 (const_string "imov")
e4b17023
JM
3296 (eq_attr "alternative" "5")
3297 (const_string "sselog1")
3298 (eq_attr "alternative" "9,10,11,14,15")
3299 (const_string "mmxmov")
3300 ]
3301 (const_string "ssemov")))
3302 (set (attr "prefix")
3303 (if_then_else (eq_attr "alternative" "5,6,7,8,12,13")
3304 (const_string "maybe_vex")
3305 (const_string "orig")))
3306 (set (attr "mode")
3307 (cond [(eq_attr "alternative" "3,4,9,10")
3308 (const_string "SI")
3309 (eq_attr "alternative" "5")
3310 (if_then_else
3311 (and (and (match_test "TARGET_SSE_LOAD0_BY_PXOR")
3312 (match_test "TARGET_SSE2"))
3313 (not (match_test "optimize_function_for_size_p (cfun)")))
3314 (const_string "TI")
3315 (const_string "V4SF"))
3316 /* For architectures resolving dependencies on
3317 whole SSE registers use APS move to break dependency
3318 chains, otherwise use short move to avoid extra work.
3319
3320 Do the same for architectures resolving dependencies on
3321 the parts. While in DF mode it is better to always handle
3322 just register parts, the SF mode is different due to lack
3323 of instructions to load just part of the register. It is
3324 better to maintain the whole registers in single format
3325 to avoid problems on using packed logical operations. */
3326 (eq_attr "alternative" "6")
3327 (if_then_else
3328 (ior (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
3329 (match_test "TARGET_SSE_SPLIT_REGS"))
3330 (const_string "V4SF")
3331 (const_string "SF"))
3332 (eq_attr "alternative" "11")
3333 (const_string "DI")]
3334 (const_string "SF")))])
3335
3336(define_split
3337 [(set (match_operand 0 "any_fp_register_operand" "")
3338 (match_operand 1 "memory_operand" ""))]
3339 "reload_completed
3340 && (GET_MODE (operands[0]) == TFmode
3341 || GET_MODE (operands[0]) == XFmode
3342 || GET_MODE (operands[0]) == DFmode
3343 || GET_MODE (operands[0]) == SFmode)
3344 && (operands[2] = find_constant_src (insn))"
3345 [(set (match_dup 0) (match_dup 2))]
3346{
3347 rtx c = operands[2];
3348 int r = REGNO (operands[0]);
3349
3350 if ((SSE_REGNO_P (r) && !standard_sse_constant_p (c))
3351 || (FP_REGNO_P (r) && standard_80387_constant_p (c) < 1))
3352 FAIL;
3353})
3354
3355(define_split
3356 [(set (match_operand 0 "any_fp_register_operand" "")
3357 (float_extend (match_operand 1 "memory_operand" "")))]
3358 "reload_completed
3359 && (GET_MODE (operands[0]) == TFmode
3360 || GET_MODE (operands[0]) == XFmode
3361 || GET_MODE (operands[0]) == DFmode)
3362 && (operands[2] = find_constant_src (insn))"
3363 [(set (match_dup 0) (match_dup 2))]
3364{
3365 rtx c = operands[2];
3366 int r = REGNO (operands[0]);
3367
3368 if ((SSE_REGNO_P (r) && !standard_sse_constant_p (c))
3369 || (FP_REGNO_P (r) && standard_80387_constant_p (c) < 1))
3370 FAIL;
3371})
3372
3373;; Split the load of -0.0 or -1.0 into fldz;fchs or fld1;fchs sequence
3374(define_split
3375 [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
3376 (match_operand:X87MODEF 1 "immediate_operand" ""))]
3377 "reload_completed
3378 && (standard_80387_constant_p (operands[1]) == 8
3379 || standard_80387_constant_p (operands[1]) == 9)"
3380 [(set (match_dup 0)(match_dup 1))
3381 (set (match_dup 0)
3382 (neg:X87MODEF (match_dup 0)))]
3383{
3384 REAL_VALUE_TYPE r;
3385
3386 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
3387 if (real_isnegzero (&r))
3388 operands[1] = CONST0_RTX (<MODE>mode);
3389 else
3390 operands[1] = CONST1_RTX (<MODE>mode);
3391})
3392
3393(define_split
3394 [(set (match_operand 0 "nonimmediate_operand" "")
3395 (match_operand 1 "general_operand" ""))]
3396 "reload_completed
3397 && (GET_MODE (operands[0]) == TFmode
3398 || GET_MODE (operands[0]) == XFmode
3399 || GET_MODE (operands[0]) == DFmode)
3400 && !(ANY_FP_REG_P (operands[0]) || ANY_FP_REG_P (operands[1]))"
3401 [(const_int 0)]
3402 "ix86_split_long_move (operands); DONE;")
3403
3404(define_insn "swapxf"
3405 [(set (match_operand:XF 0 "register_operand" "+f")
3406 (match_operand:XF 1 "register_operand" "+f"))
3407 (set (match_dup 1)
3408 (match_dup 0))]
3409 "TARGET_80387"
3410{
3411 if (STACK_TOP_P (operands[0]))
3412 return "fxch\t%1";
3413 else
3414 return "fxch\t%0";
3415}
3416 [(set_attr "type" "fxch")
3417 (set_attr "mode" "XF")])
3418
3419(define_insn "*swap<mode>"
3420 [(set (match_operand:MODEF 0 "fp_register_operand" "+f")
3421 (match_operand:MODEF 1 "fp_register_operand" "+f"))
3422 (set (match_dup 1)
3423 (match_dup 0))]
3424 "TARGET_80387 || reload_completed"
3425{
3426 if (STACK_TOP_P (operands[0]))
3427 return "fxch\t%1";
3428 else
3429 return "fxch\t%0";
3430}
3431 [(set_attr "type" "fxch")
3432 (set_attr "mode" "<MODE>")])
3433\f
3434;; Zero extension instructions
3435
3436(define_expand "zero_extendsidi2"
3437 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3438 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3439 ""
3440{
3441 if (!TARGET_64BIT)
3442 {
3443 emit_insn (gen_zero_extendsidi2_1 (operands[0], operands[1]));
3444 DONE;
3445 }
3446})
3447
3448(define_insn "*zero_extendsidi2_rex64"
95d28233 3449 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?!*y,?*Yi,*x")
e4b17023 3450 (zero_extend:DI
95d28233 3451 (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
e4b17023
JM
3452 "TARGET_64BIT"
3453 "@
3454 mov{l}\t{%1, %k0|%k0, %1}
3455 #
3456 movd\t{%1, %0|%0, %1}
3457 movd\t{%1, %0|%0, %1}
3458 %vmovd\t{%1, %0|%0, %1}
3459 %vmovd\t{%1, %0|%0, %1}"
3460 [(set_attr "type" "imovx,imov,mmxmov,mmxmov,ssemov,ssemov")
3461 (set_attr "prefix" "orig,*,orig,orig,maybe_vex,maybe_vex")
3462 (set_attr "prefix_0f" "0,*,*,*,*,*")
3463 (set_attr "mode" "SI,DI,DI,DI,TI,TI")])
3464
3465(define_split
3466 [(set (match_operand:DI 0 "memory_operand" "")
3467 (zero_extend:DI (match_dup 0)))]
3468 "TARGET_64BIT"
3469 [(set (match_dup 4) (const_int 0))]
3470 "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
3471
3472;; %%% Kill me once multi-word ops are sane.
3473(define_insn "zero_extendsidi2_1"
95d28233 3474 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?!*y,?*Yi,*x")
e4b17023 3475 (zero_extend:DI
95d28233 3476 (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
e4b17023
JM
3477 (clobber (reg:CC FLAGS_REG))]
3478 "!TARGET_64BIT"
3479 "@
3480 #
3481 #
3482 #
3483 movd\t{%1, %0|%0, %1}
3484 movd\t{%1, %0|%0, %1}
3485 %vmovd\t{%1, %0|%0, %1}
3486 %vmovd\t{%1, %0|%0, %1}"
3487 [(set_attr "isa" "*,*,*,*,*,*,sse2")
3488 (set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")
3489 (set_attr "prefix" "*,*,*,orig,orig,maybe_vex,maybe_vex")
3490 (set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")])
3491
3492(define_split
3493 [(set (match_operand:DI 0 "register_operand" "")
3494 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3495 (clobber (reg:CC FLAGS_REG))]
3496 "!TARGET_64BIT && reload_completed
3497 && true_regnum (operands[0]) == true_regnum (operands[1])"
3498 [(set (match_dup 4) (const_int 0))]
3499 "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
3500
3501(define_split
3502 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3503 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3504 (clobber (reg:CC FLAGS_REG))]
3505 "!TARGET_64BIT && reload_completed
3506 && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))"
3507 [(set (match_dup 3) (match_dup 1))
3508 (set (match_dup 4) (const_int 0))]
3509 "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
3510
3511(define_insn "zero_extend<mode>di2"
3512 [(set (match_operand:DI 0 "register_operand" "=r")
3513 (zero_extend:DI
3514 (match_operand:SWI12 1 "nonimmediate_operand" "<r>m")))]
3515 "TARGET_64BIT"
3516 "movz{<imodesuffix>l|x}\t{%1, %k0|%k0, %1}"
3517 [(set_attr "type" "imovx")
3518 (set_attr "mode" "SI")])
3519
3520(define_expand "zero_extendhisi2"
3521 [(set (match_operand:SI 0 "register_operand" "")
3522 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3523 ""
3524{
3525 if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
3526 {
3527 operands[1] = force_reg (HImode, operands[1]);
3528 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3529 DONE;
3530 }
3531})
3532
3533(define_insn_and_split "zero_extendhisi2_and"
3534 [(set (match_operand:SI 0 "register_operand" "=r")