Add the DragonFly cvs id and perform general cleanups on cvs/rcs/sccs ids. Most
[dragonfly.git] / contrib / binutils / gas / config / tc-i386.h
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1/* tc-i386.h -- Header file for tc-i386.c
2 Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23
24/* $FreeBSD: src/contrib/binutils/gas/config/tc-i386.h,v 1.3.6.4 2002/09/01 23:44:04 obrien Exp $ */
1de703da 25/* $DragonFly: src/contrib/binutils/gas/config/Attic/tc-i386.h,v 1.2 2003/06/17 04:23:58 dillon Exp $ */
984263bc
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26
27
28#ifndef TC_I386
29#define TC_I386 1
30
31#ifdef ANSI_PROTOTYPES
32struct fix;
33#endif
34
35#define TARGET_BYTES_BIG_ENDIAN 0
36
37#ifdef TE_LYNX
38#define TARGET_FORMAT "coff-i386-lynx"
39#endif
40
41#ifdef BFD_ASSEMBLER
42/* This is used to determine relocation types in tc-i386.c. The first
43 parameter is the current relocation type, the second one is the desired
44 type. The idea is that if the original type is already some kind of PIC
45 relocation, we leave it alone, otherwise we give it the desired type */
46
47#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
48extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
49
50#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE)
51/* This arranges for gas/write.c to not apply a relocation if
52 tc_fix_adjustable() says it is not adjustable.
53 The "! symbol_used_in_reloc_p" test is there specifically to cover
54 the case of non-global symbols in linkonce sections. It's the
55 generally correct thing to do though; If a reloc is going to be
56 emitted against a symbol then we don't want to adjust the fixup by
57 applying the reloc during assembly. The reloc will be applied by
58 the linker during final link. */
59#define TC_FIX_ADJUSTABLE(fixP) \
60 (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP))
61#endif
62
63/* This expression evaluates to false if the relocation is for a local object
64 for which we still want to do the relocation at runtime. True if we
65 are willing to perform this relocation while building the .o file.
66 This is only used for pcrel relocations, so GOTOFF does not need to be
67 checked here. I am not sure if some of the others are ever used with
68 pcrel, but it is easier to be safe than sorry. */
69
70#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
71 ((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
72 && (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \
73 && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \
74 && ((FIX)->fx_addsy == NULL \
75 || (! S_IS_EXTERNAL ((FIX)->fx_addsy) \
76 && ! S_IS_WEAK ((FIX)->fx_addsy) \
77 && S_IS_DEFINED ((FIX)->fx_addsy) \
78 && ! S_IS_COMMON ((FIX)->fx_addsy))))
79
80#define TARGET_ARCH bfd_arch_i386
81#define TARGET_MACH (i386_mach ())
82extern unsigned long i386_mach PARAMS ((void));
83
84#ifdef TE_FreeBSD
85#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
86#endif
87#ifdef TE_NetBSD
88#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
89#endif
90#ifdef TE_386BSD
91#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
92#endif
93#ifdef TE_LINUX
94#define AOUT_TARGET_FORMAT "a.out-i386-linux"
95#endif
96#ifdef TE_Mach
97#define AOUT_TARGET_FORMAT "a.out-mach3"
98#endif
99#ifdef TE_DYNIX
100#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
101#endif
102#ifndef AOUT_TARGET_FORMAT
103#define AOUT_TARGET_FORMAT "a.out-i386"
104#endif
105
106#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
107 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
108extern const char *i386_target_format PARAMS ((void));
109#define TARGET_FORMAT i386_target_format ()
110#else
111#ifdef OBJ_ELF
112#define TARGET_FORMAT "elf32-i386"
113#endif
114#ifdef OBJ_AOUT
115#define TARGET_FORMAT AOUT_TARGET_FORMAT
116#endif
117#endif
118
119#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
120#define md_end i386_elf_emit_arch_note
121extern void i386_elf_emit_arch_note PARAMS ((void));
122#endif
123
124#else /* ! BFD_ASSEMBLER */
125
126/* COFF STUFF */
127
128#define COFF_MAGIC I386MAGIC
129#define BFD_ARCH bfd_arch_i386
130#define COFF_FLAGS F_AR32WR
131#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
132#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
133extern short tc_coff_fix2rtype PARAMS ((struct fix *));
134#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
135extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
136
137#ifdef TE_GO32
138/* DJGPP now expects some sections to be 2**4 aligned. */
139#define SUB_SEGMENT_ALIGN(SEG) \
140 ((strcmp (obj_segment_name (SEG), ".text") == 0 \
141 || strcmp (obj_segment_name (SEG), ".data") == 0 \
142 || strcmp (obj_segment_name (SEG), ".bss") == 0 \
143 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \
144 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \
145 || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \
146 ? 4 \
147 : 2)
148#else
149#define SUB_SEGMENT_ALIGN(SEG) 2
150#endif
151
152#define TC_RVA_RELOC 7
153/* Need this for PIC relocations */
154#define NEED_FX_R_TYPE
155
156#ifdef TE_386BSD
157/* The BSDI linker apparently rejects objects with a machine type of
158 M_386 (100). */
159#define AOUT_MACHTYPE 0
160#else
161#define AOUT_MACHTYPE 100
162#endif
163
164#undef REVERSE_SORT_RELOCS
165
166#endif /* ! BFD_ASSEMBLER */
167
168#ifndef LEX_AT
169#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
170extern void x86_cons PARAMS ((expressionS *, int));
171
172#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
173extern void x86_cons_fix_new
174 PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
175#endif
176
177#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
178extern int tc_i386_force_relocation PARAMS ((struct fix *));
179
180#ifdef BFD_ASSEMBLER
181#define NO_RELOC BFD_RELOC_NONE
182#else
183#define NO_RELOC 0
184#endif
185#define tc_coff_symbol_emit_hook(a) ; /* not used */
186
187#ifndef BFD_ASSEMBLER
188#ifndef OBJ_AOUT
189#ifndef TE_PE
190#ifndef TE_GO32
191/* Local labels starts with .L */
192#define LOCAL_LABEL(name) (name[0] == '.' \
193 && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
194#endif
195#endif
196#endif
197#endif
198
199#define LOCAL_LABELS_FB 1
200
201#define tc_aout_pre_write_hook(x) {;} /* not used */
202#define tc_crawl_symbol_chain(a) {;} /* not used */
203#define tc_headers_hook(a) {;} /* not used */
204
205extern const char extra_symbol_chars[];
206#define tc_symbol_chars extra_symbol_chars
207
208#define MAX_OPERANDS 3 /* max operands per insn */
209#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
210#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
211
212/* Prefixes will be emitted in the order defined below.
213 WAIT_PREFIX must be the first prefix since FWAIT is really is an
214 instruction, and so must come before any prefixes. */
215#define WAIT_PREFIX 0
216#define LOCKREP_PREFIX 1
217#define ADDR_PREFIX 2
218#define DATA_PREFIX 3
219#define SEG_PREFIX 4
220#define REX_PREFIX 5 /* must come last. */
221#define MAX_PREFIXES 6 /* max prefixes per opcode */
222
223/* we define the syntax here (modulo base,index,scale syntax) */
224#define REGISTER_PREFIX '%'
225#define IMMEDIATE_PREFIX '$'
226#define ABSOLUTE_PREFIX '*'
227
228#define TWO_BYTE_OPCODE_ESCAPE 0x0f
229#define NOP_OPCODE (char) 0x90
230
231/* register numbers */
232#define EBP_REG_NUM 5
233#define ESP_REG_NUM 4
234
235/* modrm_byte.regmem for twobyte escape */
236#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
237/* index_base_byte.index for no index register addressing */
238#define NO_INDEX_REGISTER ESP_REG_NUM
239/* index_base_byte.base for no base register addressing */
240#define NO_BASE_REGISTER EBP_REG_NUM
241#define NO_BASE_REGISTER_16 6
242
243/* these are the instruction mnemonic suffixes. */
244#define WORD_MNEM_SUFFIX 'w'
245#define BYTE_MNEM_SUFFIX 'b'
246#define SHORT_MNEM_SUFFIX 's'
247#define LONG_MNEM_SUFFIX 'l'
248#define QWORD_MNEM_SUFFIX 'q'
249/* Intel Syntax */
250#define LONG_DOUBLE_MNEM_SUFFIX 'x'
251
252/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
253#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
254#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
255
256#define END_OF_INSN '\0'
257
258/* Intel Syntax */
259/* Values 0-4 map onto scale factor */
260#define BYTE_PTR 0
261#define WORD_PTR 1
262#define DWORD_PTR 2
263#define QWORD_PTR 3
264#define XWORD_PTR 4
265#define SHORT 5
266#define OFFSET_FLAT 6
267#define FLAT 7
268#define NONE_FOUND 8
269
270typedef struct
271{
272 /* instruction name sans width suffix ("mov" for movl insns) */
273 char *name;
274
275 /* how many operands */
276 unsigned int operands;
277
278 /* base_opcode is the fundamental opcode byte without optional
279 prefix(es). */
280 unsigned int base_opcode;
281
282 /* extension_opcode is the 3 bit extension for group <n> insns.
283 This field is also used to store the 8-bit opcode suffix for the
284 AMD 3DNow! instructions.
285 If this template has no extension opcode (the usual case) use None */
286 unsigned int extension_opcode;
287#define None 0xffff /* If no extension_opcode is possible. */
288
289 /* cpu feature flags */
290 unsigned int cpu_flags;
291#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
292#define Cpu186 0x2 /* i186 or better required */
293#define Cpu286 0x4 /* i286 or better required */
294#define Cpu386 0x8 /* i386 or better required */
295#define Cpu486 0x10 /* i486 or better required */
296#define Cpu586 0x20 /* i585 or better required */
297#define Cpu686 0x40 /* i686 or better required */
298#define CpuP4 0x80 /* Pentium4 or better required */
299#define CpuK6 0x100 /* AMD K6 or better required*/
300#define CpuAthlon 0x200 /* AMD Athlon or better required*/
301#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
302#define CpuMMX 0x800 /* MMX support required */
303#define CpuSSE 0x1000 /* Streaming SIMD extensions required */
304#define CpuSSE2 0x2000 /* Streaming SIMD extensions 2 required */
305#define Cpu3dnow 0x4000 /* 3dnow! support required */
306
307 /* These flags are set by gas depending on the flag_code. */
308#define Cpu64 0x4000000 /* 64bit support required */
309#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
310
311 /* The default value for unknown CPUs - enable all features to avoid problems. */
312#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon)
313
314 /* the bits in opcode_modifier are used to generate the final opcode from
315 the base_opcode. These bits also are used to detect alternate forms of
316 the same instruction */
317 unsigned int opcode_modifier;
318
319 /* opcode_modifier bits: */
320#define W 0x1 /* set if operands can be words or dwords
321 encoded the canonical way */
322#define D 0x2 /* D = 0 if Reg --> Regmem;
323 D = 1 if Regmem --> Reg: MUST BE 0x2 */
324#define Modrm 0x4
325#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
326#define ShortForm 0x10 /* register is in low 3 bits of opcode */
327#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
328#define Jump 0x40 /* special case for jump insns. */
329#define JumpDword 0x80 /* call and jump */
330#define JumpByte 0x100 /* loop and jecxz */
331#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
332#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
333#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
334#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
335#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
336#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
337#define Size64 0x8000 /* needs size prefix if in 16-bit mode */
338#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
339#define DefaultSize 0x20000 /* default insn size depends on mode */
340#define No_bSuf 0x40000 /* b suffix on instruction illegal */
341#define No_wSuf 0x80000 /* w suffix on instruction illegal */
342#define No_lSuf 0x100000 /* l suffix on instruction illegal */
343#define No_sSuf 0x200000 /* s suffix on instruction illegal */
344#define No_qSuf 0x400000 /* q suffix on instruction illegal */
345#define No_xSuf 0x800000 /* x suffix on instruction illegal */
346#define FWait 0x1000000 /* instruction needs FWAIT */
347#define IsString 0x2000000 /* quick test for string instructions */
348#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
349#define IsPrefix 0x8000000 /* opcode is a prefix */
350#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
351#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
352#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
353#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
354
355 /* operand_types[i] describes the type of operand i. This is made
356 by OR'ing together all of the possible type masks. (e.g.
357 'operand_types[i] = Reg|Imm' specifies that operand i can be
358 either a register or an immediate operand. */
359 unsigned int operand_types[3];
360
361 /* operand_types[i] bits */
362 /* register */
363#define Reg8 0x1 /* 8 bit reg */
364#define Reg16 0x2 /* 16 bit reg */
365#define Reg32 0x4 /* 32 bit reg */
366#define Reg64 0x8 /* 64 bit reg */
367 /* immediate */
368#define Imm8 0x10 /* 8 bit immediate */
369#define Imm8S 0x20 /* 8 bit immediate sign extended */
370#define Imm16 0x40 /* 16 bit immediate */
371#define Imm32 0x80 /* 32 bit immediate */
372#define Imm32S 0x100 /* 32 bit immediate sign extended */
373#define Imm64 0x200 /* 64 bit immediate */
374#define Imm1 0x400 /* 1 bit immediate */
375 /* memory */
376#define BaseIndex 0x800
377 /* Disp8,16,32 are used in different ways, depending on the
378 instruction. For jumps, they specify the size of the PC relative
379 displacement, for baseindex type instructions, they specify the
380 size of the offset relative to the base register, and for memory
381 offset instructions such as `mov 1234,%al' they specify the size of
382 the offset relative to the segment base. */
383#define Disp8 0x1000 /* 8 bit displacement */
384#define Disp16 0x2000 /* 16 bit displacement */
385#define Disp32 0x4000 /* 32 bit displacement */
386#define Disp32S 0x8000 /* 32 bit signed displacement */
387#define Disp64 0x10000 /* 64 bit displacement */
388 /* specials */
389#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
390#define ShiftCount 0x40000 /* register to hold shift cound = cl */
391#define Control 0x80000 /* Control register */
392#define Debug 0x100000 /* Debug register */
393#define Test 0x200000 /* Test register */
394#define FloatReg 0x400000 /* Float register */
395#define FloatAcc 0x800000 /* Float stack top %st(0) */
396#define SReg2 0x1000000 /* 2 bit segment register */
397#define SReg3 0x2000000 /* 3 bit segment register */
398#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
399#define JumpAbsolute 0x8000000
400#define RegMMX 0x10000000 /* MMX register */
401#define RegXMM 0x20000000 /* XMM registers in PIII */
402#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
403
404 /* InvMem is for instructions with a modrm byte that only allow a
405 general register encoding in the i.tm.mode and i.tm.regmem fields,
406 eg. control reg moves. They really ought to support a memory form,
407 but don't, so we add an InvMem flag to the register operand to
408 indicate that it should be encoded in the i.tm.regmem field. */
409#define InvMem 0x80000000
410
411#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
412#define WordReg (Reg16|Reg32|Reg64)
413#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
414#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
415#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
416#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
417#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
418 /* The following aliases are defined because the opcode table
419 carefully specifies the allowed memory types for each instruction.
420 At the moment we can only tell a memory reference size by the
421 instruction suffix, so there's not much point in defining Mem8,
422 Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
423 the suffix directly to check memory operands. */
424#define LLongMem AnyMem /* 64 bits (or more) */
425#define LongMem AnyMem /* 32 bit memory ref */
426#define ShortMem AnyMem /* 16 bit memory ref */
427#define WordMem AnyMem /* 16 or 32 bit memory ref */
428#define ByteMem AnyMem /* 8 bit memory ref */
429}
430template;
431
432/*
433 'templates' is for grouping together 'template' structures for opcodes
434 of the same name. This is only used for storing the insns in the grand
435 ole hash table of insns.
436 The templates themselves start at START and range up to (but not including)
437 END.
438 */
439typedef struct
440{
441 const template *start;
442 const template *end;
443}
444templates;
445
446/* these are for register name --> number & type hash lookup */
447typedef struct
448{
449 char *reg_name;
450 unsigned int reg_type;
451 unsigned int reg_flags;
452#define RegRex 0x1 /* Extended register. */
453#define RegRex64 0x2 /* Extended 8 bit register. */
454 unsigned int reg_num;
455}
456reg_entry;
457
458typedef struct
459{
460 char *seg_name;
461 unsigned int seg_prefix;
462}
463seg_entry;
464
465/* 386 operand encoding bytes: see 386 book for details of this. */
466typedef struct
467{
468 unsigned int regmem; /* codes register or memory operand */
469 unsigned int reg; /* codes register operand (or extended opcode) */
470 unsigned int mode; /* how to interpret regmem & reg */
471}
472modrm_byte;
473
474/* x86-64 extension prefix. */
475typedef int rex_byte;
476#define REX_OPCODE 0x40
477
478/* Indicates 64 bit operand size. */
479#define REX_MODE64 8
480/* High extension to reg field of modrm byte. */
481#define REX_EXTX 4
482/* High extension to SIB index field. */
483#define REX_EXTY 2
484/* High extension to base field of modrm or SIB, or reg field of opcode. */
485#define REX_EXTZ 1
486
487/* 386 opcode byte to code indirect addressing. */
488typedef struct
489{
490 unsigned base;
491 unsigned index;
492 unsigned scale;
493}
494sib_byte;
495
496/* x86 arch names and features */
497typedef struct
498{
499 const char *name; /* arch name */
500 unsigned int flags; /* cpu feature flags */
501}
502arch_entry;
503
504/* The name of the global offset table generated by the compiler. Allow
505 this to be overridden if need be. */
506#ifndef GLOBAL_OFFSET_TABLE_NAME
507#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
508#endif
509
510#ifdef BFD_ASSEMBLER
511void i386_validate_fix PARAMS ((struct fix *));
512#define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
513#endif
514
515#endif /* TC_I386 */
516
517#define md_operand(x)
518
519extern const struct relax_type md_relax_table[];
520#define TC_GENERIC_RELAX_TABLE md_relax_table
521
522#define md_do_align(n, fill, len, max, around) \
523if ((n) && !need_pass_2 \
524 && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \
525 && subseg_text_p (now_seg)) \
526 { \
527 frag_align_code ((n), (max)); \
528 goto around; \
529 }
530
531#define MAX_MEM_FOR_RS_ALIGN_CODE 15
532
533extern void i386_align_code PARAMS ((fragS *, int));
534
535#define HANDLE_ALIGN(fragP) \
536if (fragP->fr_type == rs_align_code) \
537 i386_align_code (fragP, (fragP->fr_next->fr_address \
538 - fragP->fr_address \
539 - fragP->fr_fix));
540
541void i386_print_statistics PARAMS ((FILE *));
542#define tc_print_statistics i386_print_statistics
543
544#define md_number_to_chars number_to_chars_littleendian
545
546#ifdef SCO_ELF
547#define tc_init_after_args() sco_id ()
548extern void sco_id PARAMS ((void));
549#endif
550
551#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */