Add the DragonFly cvs id and perform general cleanups on cvs/rcs/sccs ids. Most
[dragonfly.git] / contrib / binutils / gas / doc / as.1
984263bc 1.\" $FreeBSD: src/contrib/binutils/gas/doc/as.1,v 2002/09/01 23:44:06 obrien Exp $
1de703da 2.\" $DragonFly: src/contrib/binutils/gas/doc/Attic/as.1,v 1.2 2003/06/17 04:23:58 dillon Exp $
5.\" Automatically generated by Pod::Man v1.3, Pod::Parser v1.13
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132.rm #[ #] #H #V #F C
133.\" ========================================================================
135.IX Title "AS 1"
136.TH AS 1 "2002-05-14" "binutils-2.12.1" "GNU Development Tools"
138.SH "NAME"
139\&\s-1AS\s0 \- the portable \s-1GNU\s0 assembler.
141.IX Header "SYNOPSIS"
142as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR]
143 [\fB\-f\fR] [\fB\-\-gstabs\fR] [\fB\-\-gdwarf2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR]
144 [\fB\-J\fR] [\fB\-K\fR] [\fB\-L\fR]
145 [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR]
146 [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR]
147 [\fB\-\-keep\-locals\fR] [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-statistics\fR] [\fB\-v\fR]
148 [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR]
149 [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB\-\-target\-help\fR] [\fItarget-options\fR]
150 [\fB\-\-\fR|\fIfiles\fR ...]
152\&\fITarget Alpha options:\fR
153 [\fB\-m\fR\fIcpu\fR]
154 [\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
155 [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
156 [\fB\-F\fR] [\fB\-32addr\fR]
158\&\fITarget \s-1ARC\s0 options:\fR
159 [\fB\-marc[5|6|7|8]\fR]
160 [\fB\-EB\fR|\fB\-EL\fR]
162\&\fITarget \s-1ARM\s0 options:\fR
163 [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
164 [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
165 [\fB\-mfpu\fR=\fIfloating-point-fromat\fR]
166 [\fB\-mthumb\fR]
167 [\fB\-EB\fR|\fB\-EL\fR]
168 [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
169 \fB\-mapcs\-reentrant\fR]
170 [\fB\-mthumb\-interwork\fR] [\fB\-moabi\fR] [\fB\-k\fR]
172\&\fITarget \s-1CRIS\s0 options:\fR
173 [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
174 [\fB\-\-pic\fR] [\fB\-N\fR]
175 [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
177\&\fITarget D10V options:\fR
178 [\fB\-O\fR]
180\&\fITarget D30V options:\fR
181 [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
183\&\fITarget i386 options:\fR
184 [\fB\-\-32\fR|\fB\-\-64\fR]
186\&\fITarget i960 options:\fR
187 [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|
188 \fB\-AKC\fR|\fB\-AMC\fR]
189 [\fB\-b\fR] [\fB\-no\-relax\fR]
191\&\fITarget M32R options:\fR
192 [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
193 \fB\-\-W[n]p\fR]
195\&\fITarget M680X0 options:\fR
196 [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
198\&\fITarget M68HC11 options:\fR
199 [\fB\-m68hc11\fR|\fB\-m68hc12\fR]
200 [\fB\-\-force\-long\-branchs\fR] [\fB\-\-short\-branchs\fR]
201 [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
202 [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
204\&\fITarget \s-1MCORE\s0 options:\fR
205 [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
206 [\fB\-mcpu=[210|340]\fR]
208\&\fITarget \s-1MIPS\s0 options:\fR
209 [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-G\fR \fInum\fR] [\fB\-mcpu\fR=\fI\s-1CPU\s0\fR ]
210 [\fB\-mips1\fR] [\fB\-mips2\fR] [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR]
211 [\fB\-mips32\fR] [\fB\-mips64\fR]
212 [\fB\-m4650\fR] [\fB\-no\-m4650\fR]
213 [\fB\-\-trap\fR] [\fB\-\-break\fR] [\fB\-n\fR]
214 [\fB\-\-emulation\fR=\fIname\fR ]
216\&\fITarget \s-1MMIX\s0 options:\fR
217 [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
218 [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
219 [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
220 [\fB\-\-linker\-allocated\-gregs\fR]
222\&\fITarget \s-1PDP11\s0 options:\fR
223 [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
224 [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
225 [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
227\&\fITarget picoJava options:\fR
228 [\fB\-mb\fR|\fB\-me\fR]
230\&\fITarget PowerPC options:\fR
231 [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|
232 \fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|
233 \fB\-mbooke32\fR|\fB\-mbooke64\fR]
234 [\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR]
235 [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
236 [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR]
237 [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR]
238 [\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
240\&\fITarget \s-1SPARC\s0 options:\fR
241 [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
242 \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]
243 [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR]
244 [\fB\-32\fR|\fB\-64\fR]
247\&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
248If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
249should find a fairly similar environment when you use it on another
250architecture. Each version has much in common with the others,
251including object file formats, most assembler directives (often called
252\&\fIpseudo-ops\fR) and assembler syntax.
254\&\fBas\fR is primarily intended to assemble the output of the
255\&\s-1GNU\s0 C compiler for use by the linker
256\&. Nevertheless, we've tried to make \fBas\fR
257assemble correctly everything that other assemblers for the same
258machine would assemble.
259Any exceptions are documented explicitly.
260This doesn't mean \fBas\fR always uses the same syntax as another
261assembler for the same architecture; for example, we know of several
262incompatible versions of 680x0 assembly language syntax.
264Each time you run \fBas\fR it assembles exactly one source
265program. The source program is made up of one or more files.
266(The standard input is also a file.)
268You give \fBas\fR a command line that has zero or more input file
269names. The input files are read (from left file name to right). A
270command line argument (in any position) that has no special meaning
271is taken to be an input file name.
273If you give \fBas\fR no file names it attempts to read one input file
274from the \fBas\fR standard input, which is normally your terminal. You
275may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
276to assemble.
278Use \fB\-\-\fR if you need to explicitly name the standard input file
279in your command line.
281If the source is empty, \fBas\fR produces a small, empty object
284\&\fBas\fR may write warnings and error messages to the standard error
285file (usually your terminal). This should not happen when a compiler
286runs \fBas\fR automatically. Warnings report an assumption made so
287that \fBas\fR could keep assembling a flawed program; errors report a
288grave problem that stops the assembly.
290If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler (version 2),
291you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
292The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
293by commas. For example:
295.Vb 1
296\& gcc -c -g -O -Wa,-alh,-L file.c
298This passes two options to the assembler: \fB\-alh\fR (emit a listing to
299standard output with with high-level and assembly source) and \fB\-L\fR (retain
300local symbols in the symbol table).
302Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
303command-line options are automatically passed to the assembler by the compiler.
304(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
305precisely what options it passes to each compilation pass, including the
308.IX Header "OPTIONS"
309.IP "\fB\-a[cdhlmns]\fR" 4
310.IX Item "-a[cdhlmns]"
311Turn on listings, in any of a variety of ways:
312.RS 4
313.IP "\fB\-ac\fR" 4
314.IX Item "-ac"
315omit false conditionals
316.IP "\fB\-ad\fR" 4
317.IX Item "-ad"
318omit debugging directives
319.IP "\fB\-ah\fR" 4
320.IX Item "-ah"
321include high-level source
322.IP "\fB\-al\fR" 4
323.IX Item "-al"
324include assembly
325.IP "\fB\-am\fR" 4
326.IX Item "-am"
327include macro expansions
328.IP "\fB\-an\fR" 4
329.IX Item "-an"
330omit forms processing
331.IP "\fB\-as\fR" 4
332.IX Item "-as"
333include symbols
334.IP "\fB=file\fR" 4
335.IX Item "=file"
336set the name of the listing file
338.RS 4
340You may combine these options; for example, use \fB\-aln\fR for assembly
341listing without forms processing. The \fB=file\fR option, if used, must be
342the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
344.IP "\fB\-D\fR" 4
345.IX Item "-D"
346Ignored. This option is accepted for script compatibility with calls to
347other assemblers.
348.IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
349.IX Item "--defsym sym=value"
350Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
351\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR
352indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value.
353.IP "\fB\-f\fR" 4
354.IX Item "-f"
355``fast''\-\-\-skip whitespace and comment preprocessing (assume source is
356compiler output).
357.IP "\fB\-\-gstabs\fR" 4
358.IX Item "--gstabs"
359Generate stabs debugging information for each assembler line. This
360may help debugging assembler code, if the debugger can handle it.
361.IP "\fB\-\-gdwarf2\fR" 4
362.IX Item "--gdwarf2"
363Generate \s-1DWARF2\s0 debugging information for each assembler line. This
364may help debugging assembler code, if the debugger can handle it. Note \- this
365option is only supported by some targets, not all of them.
366.IP "\fB\-\-help\fR" 4
367.IX Item "--help"
368Print a summary of the command line options and exit.
369.IP "\fB\-\-target\-help\fR" 4
370.IX Item "--target-help"
371Print a summary of all target specific options and exit.
372.IP "\fB\-I\fR \fIdir\fR" 4
373.IX Item "-I dir"
374Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
375.IP "\fB\-J\fR" 4
376.IX Item "-J"
377Don't warn about signed overflow.
378.IP "\fB\-K\fR" 4
379.IX Item "-K"
380This option is accepted but has no effect on the \s-1TARGET\s0 family.
381.IP "\fB\-L\fR" 4
382.IX Item "-L"
383.PD 0
384.IP "\fB\-\-keep\-locals\fR" 4
385.IX Item "--keep-locals"
387Keep (in the symbol table) local symbols. On traditional a.out systems
388these start with \fBL\fR, but different systems have different local
389label prefixes.
390.IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
391.IX Item "--listing-lhs-width=number"
392Set the maximum width, in words, of the output data column for an assembler
393listing to \fInumber\fR.
394.IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
395.IX Item "--listing-lhs-width2=number"
396Set the maximum width, in words, of the output data column for continuation
397lines in an assembler listing to \fInumber\fR.
398.IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
399.IX Item "--listing-rhs-width=number"
400Set the maximum width of an input source line, as displayed in a listing, to
401\&\fInumber\fR bytes.
402.IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
403.IX Item "--listing-cont-lines=number"
404Set the maximum number of lines printed in a listing for a single line of input
405to \fInumber\fR + 1.
406.IP "\fB\-o\fR \fIobjfile\fR" 4
407.IX Item "-o objfile"
408Name the object-file output from \fBas\fR \fIobjfile\fR.
409.IP "\fB\-R\fR" 4
410.IX Item "-R"
411Fold the data section into the text section.
412.IP "\fB\-\-statistics\fR" 4
413.IX Item "--statistics"
414Print the maximum space (in bytes) and total time (in seconds) used by
416.IP "\fB\-\-strip\-local\-absolute\fR" 4
417.IX Item "--strip-local-absolute"
418Remove local absolute symbols from the outgoing symbol table.
419.IP "\fB\-v\fR" 4
420.IX Item "-v"
421.PD 0
422.IP "\fB\-version\fR" 4
423.IX Item "-version"
425Print the \fBas\fR version.
426.IP "\fB\-\-version\fR" 4
427.IX Item "--version"
428Print the \fBas\fR version and exit.
429.IP "\fB\-W\fR" 4
430.IX Item "-W"
431.PD 0
432.IP "\fB\-\-no\-warn\fR" 4
433.IX Item "--no-warn"
435Suppress warning messages.
436.IP "\fB\-\-fatal\-warnings\fR" 4
437.IX Item "--fatal-warnings"
438Treat warnings as errors.
439.IP "\fB\-\-warn\fR" 4
440.IX Item "--warn"
441Don't suppress warning messages or treat them as errors.
442.IP "\fB\-w\fR" 4
443.IX Item "-w"
445.IP "\fB\-x\fR" 4
446.IX Item "-x"
448.IP "\fB\-Z\fR" 4
449.IX Item "-Z"
450Generate an object file even after errors.
451.IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
452.IX Item "-- | files ..."
453Standard input, or source files to assemble.
455The following options are available when as is configured for
456an \s-1ARC\s0 processor.
457.IP "\fB\-marc[5|6|7|8]\fR" 4
458.IX Item "-marc[5|6|7|8]"
459This option selects the core processor variant.
460.IP "\fB\-EB | \-EL\fR" 4
461.IX Item "-EB | -EL"
462Select either big-endian (\-EB) or little-endian (\-EL) output.
464The following options are available when as is configured for the \s-1ARM\s0
465processor family.
466.IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
467.IX Item "-mcpu=processor[+extension...]"
468Specify which \s-1ARM\s0 processor variant is the target.
469.IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
470.IX Item "-march=architecture[+extension...]"
471Specify which \s-1ARM\s0 architecture variant is used by the target.
472.IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
473.IX Item "-mfpu=floating-point-format"
474Select which Floating Point architecture is the target.
475.IP "\fB\-mthumb\fR" 4
476.IX Item "-mthumb"
477Enable Thumb only instruction decoding.
478.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant | \-moabi\fR" 4
479.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi"
480Select which procedure calling convention is in use.
481.IP "\fB\-EB | \-EL\fR" 4
482.IX Item "-EB | -EL"
483Select either big-endian (\-EB) or little-endian (\-EL) output.
484.IP "\fB\-mthumb\-interwork\fR" 4
485.IX Item "-mthumb-interwork"
486Specify that the code has been generated with interworking between Thumb and
487\&\s-1ARM\s0 code in mind.
488.IP "\fB\-k\fR" 4
489.IX Item "-k"
490Specify that \s-1PIC\s0 code has been generated.
492See the info pages for documentation of the CRIS-specific options.
494The following options are available when as is configured for
495a D10V processor.
496.IP "\fB\-O\fR" 4
497.IX Item "-O"
498Optimize output by parallelizing instructions.
500The following options are available when as is configured for a D30V
502.IP "\fB\-O\fR" 4
503.IX Item "-O"
504Optimize output by parallelizing instructions.
505.IP "\fB\-n\fR" 4
506.IX Item "-n"
507Warn when nops are generated.
508.IP "\fB\-N\fR" 4
509.IX Item "-N"
510Warn when a nop after a 32\-bit multiply instruction is generated.
512The following options are available when as is configured for the
513Intel 80960 processor.
514.IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4
515.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
516Specify which variant of the 960 architecture is the target.
517.IP "\fB\-b\fR" 4
518.IX Item "-b"
519Add code to collect statistics about branches taken.
520.IP "\fB\-no\-relax\fR" 4
521.IX Item "-no-relax"
522Do not alter compare-and-branch instructions for long displacements;
523error if necessary.
525The following options are available when as is configured for the
526Mitsubishi M32R series.
527.IP "\fB\-\-m32rx\fR" 4
528.IX Item "--m32rx"
529Specify which processor in the M32R family is the target. The default
530is normally the M32R, but this option changes it to the M32RX.
531.IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
532.IX Item "--warn-explicit-parallel-conflicts or --Wp"
533Produce warning messages when questionable parallel constructs are
535.IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
536.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
537Do not produce warning messages when questionable parallel constructs are
540The following options are available when as is configured for the
541Motorola 68000 series.
542.IP "\fB\-l\fR" 4
543.IX Item "-l"
544Shorten references to undefined symbols, to one word instead of two.
545.IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
546.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
547.PD 0
548.IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
549.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
550.IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
551.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
553Specify what processor in the 68000 family is the target. The default
554is normally the 68020, but this can be changed at configuration time.
555.IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
556.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
557The target machine does (or does not) have a floating-point coprocessor.
558The default is to assume a coprocessor for 68020, 68030, and cpu32. Although
559the basic 68000 is not compatible with the 68881, a combination of the
560two can be specified, since it's possible to do emulation of the
561coprocessor instructions with the main processor.
562.IP "\fB\-m68851 | \-mno\-68851\fR" 4
563.IX Item "-m68851 | -mno-68851"
564The target machine does (or does not) have a memory-management
565unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up.
567For details about the \s-1PDP\-11\s0 machine dependent features options,
568see \f(CW@ref\fR{PDP\-11\-Options}.
569.IP "\fB\-mpic | \-mno\-pic\fR" 4
570.IX Item "-mpic | -mno-pic"
571Generate position-independent (or position\-dependent) code. The
572default is \fB\-mpic\fR.
573.IP "\fB\-mall\fR" 4
574.IX Item "-mall"
575.PD 0
576.IP "\fB\-mall\-extensions\fR" 4
577.IX Item "-mall-extensions"
579Enable all instruction set extensions. This is the default.
580.IP "\fB\-mno\-extensions\fR" 4
581.IX Item "-mno-extensions"
582Disable all instruction set extensions.
583.IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4
584.IX Item "-mextension | -mno-extension"
585Enable (or disable) a particular instruction set extension.
586.IP "\fB\-m\fR\fIcpu\fR" 4
587.IX Item "-mcpu"
588Enable the instruction set extensions supported by a particular \s-1CPU\s0, and
589disable all other extensions.
590.IP "\fB\-m\fR\fImachine\fR" 4
591.IX Item "-mmachine"
592Enable the instruction set extensions supported by a particular machine
593model, and disable all other extensions.
595The following options are available when as is configured for
596a picoJava processor.
597.IP "\fB\-mb\fR" 4
598.IX Item "-mb"
599Generate ``big endian'' format output.
600.IP "\fB\-ml\fR" 4
601.IX Item "-ml"
602Generate ``little endian'' format output.
604The following options are available when as is configured for the
605Motorola 68HC11 or 68HC12 series.
606.IP "\fB\-m68hc11 | \-m68hc12\fR" 4
607.IX Item "-m68hc11 | -m68hc12"
608Specify what processor is the target. The default is
609defined by the configuration option when building the assembler.
610.IP "\fB\-\-force\-long\-branchs\fR" 4
611.IX Item "--force-long-branchs"
612Relative branches are turned into absolute ones. This concerns
613conditional branches, unconditional branches and branches to a
614sub routine.
615.IP "\fB\-S | \-\-short\-branchs\fR" 4
616.IX Item "-S | --short-branchs"
617Do not turn relative branchs into absolute ones
618when the offset is out of range.
619.IP "\fB\-\-strict\-direct\-mode\fR" 4
620.IX Item "--strict-direct-mode"
621Do not turn the direct addressing mode into extended addressing mode
622when the instruction does not support direct addressing mode.
623.IP "\fB\-\-print\-insn\-syntax\fR" 4
624.IX Item "--print-insn-syntax"
625Print the syntax of instruction in case of error.
626.IP "\fB\-\-print\-opcodes\fR" 4
627.IX Item "--print-opcodes"
628print the list of instructions with syntax and then exit.
629.IP "\fB\-\-generate\-example\fR" 4
630.IX Item "--generate-example"
631print an example of instruction for each possible instruction and then exit.
632This option is only useful for testing \fBas\fR.
634The following options are available when \fBas\fR is configured
635for the \s-1SPARC\s0 architecture:
636.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4
637.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
638.PD 0
639.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4
640.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
642Explicitly select a variant of the \s-1SPARC\s0 architecture.
644\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
645\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
647\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
648UltraSPARC extensions.
649.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4
650.IX Item "-xarch=v8plus | -xarch=v8plusa"
651For compatibility with the Solaris v9 assembler. These options are
652equivalent to \-Av8plus and \-Av8plusa, respectively.
653.IP "\fB\-bump\fR" 4
654.IX Item "-bump"
655Warn when the assembler switches to another architecture.
657The following options are available when as is configured for
658a \s-1MIPS\s0 processor.
659.IP "\fB\-G\fR \fInum\fR" 4
660.IX Item "-G num"
661This option sets the largest size of an object that can be referenced
662implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that
663use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8.
664.IP "\fB\-EB\fR" 4
665.IX Item "-EB"
666Generate ``big endian'' format output.
667.IP "\fB\-EL\fR" 4
668.IX Item "-EL"
669Generate ``little endian'' format output.
670.IP "\fB\-mips1\fR" 4
671.IX Item "-mips1"
672.PD 0
673.IP "\fB\-mips2\fR" 4
674.IX Item "-mips2"
675.IP "\fB\-mips3\fR" 4
676.IX Item "-mips3"
677.IP "\fB\-mips4\fR" 4
678.IX Item "-mips4"
679.IP "\fB\-mips32\fR" 4
680.IX Item "-mips32"
681.IP "\fB\-mips64\fR" 4
682.IX Item "-mips64"
684Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
685\&\fB\-mips1\fR corresponds to the R2000 and R3000 processors,
686\&\fB\-mips2\fR to the R6000 processor, and \fB\-mips3\fR to the R4000
688\&\fB\-mips5\fR, \fB\-mips32\fR, and \fB\-mips64\fR correspond
689to generic \s-1MIPS\s0 V, \s-1MIPS32\s0, and \s-1MIPS64\s0 \s-1ISA\s0
690processors, respectively.
691.IP "\fB\-m4650\fR" 4
692.IX Item "-m4650"
693.PD 0
694.IP "\fB\-no\-m4650\fR" 4
695.IX Item "-no-m4650"
697Generate code for the \s-1MIPS\s0 R4650 chip. This tells the assembler to accept
698the \fBmad\fR and \fBmadu\fR instruction, and to not schedule \fBnop\fR
699instructions around accesses to the \fB\s-1HI\s0\fR and \fB\s-1LO\s0\fR registers.
700\&\fB\-no\-m4650\fR turns off this option.
701.IP "\fB\-mcpu=\fR\fI\s-1CPU\s0\fR" 4
702.IX Item "-mcpu=CPU"
703Generate code for a particular \s-1MIPS\s0 cpu. It is exactly equivalent to
704\&\fB\-m\fR\fIcpu\fR, except that there are more value of \fIcpu\fR
706.IP "\fB\-\-emulation=\fR\fIname\fR" 4
707.IX Item "--emulation=name"
708This option causes \fBas\fR to emulate \fBas\fR configured
709for some other target, in all respects, including output format (choosing
710between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
711debugging information or store symbol table information, and default
712endianness. The available configuration names are: \fBmipsecoff\fR,
713\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
714\&\fBmipsbelf\fR. The first two do not alter the default endianness from that
715of the primary target for which the assembler was configured; the others change
716the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR
717in the name. Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
718selection in any case.
720This option is currently supported only when the primary target
721\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
722Furthermore, the primary target or others specified with
723\&\fB\-\-enable\-targets=...\fR at configuration time must include support for
724the other format, if both are to be available. For example, the Irix 5
725configuration includes support for both.
727Eventually, this option will support more configurations, with more
728fine-grained control over the assembler's behavior, and will be supported for
729more processors.
730.IP "\fB\-nocpp\fR" 4
731.IX Item "-nocpp"
732\&\fBas\fR ignores this option. It is accepted for compatibility with
733the native tools.
734.IP "\fB\-\-trap\fR" 4
735.IX Item "--trap"
736.PD 0
737.IP "\fB\-\-no\-trap\fR" 4
738.IX Item "--no-trap"
739.IP "\fB\-\-break\fR" 4
740.IX Item "--break"
741.IP "\fB\-\-no\-break\fR" 4
742.IX Item "--no-break"
744Control how to deal with multiplication overflow and division by zero.
745\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
746(and only work for Instruction Set Architecture level 2 and higher);
747\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
748break exception.
749.IP "\fB\-n\fR" 4
750.IX Item "-n"
751When this option is used, \fBas\fR will issue a warning every
752time it generates a nop instruction from a macro.
754The following options are available when as is configured for
755an MCore processor.
756.IP "\fB\-jsri2bsr\fR" 4
757.IX Item "-jsri2bsr"
758.PD 0
759.IP "\fB\-nojsri2bsr\fR" 4
760.IX Item "-nojsri2bsr"
762Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation. By default this is enabled.
763The command line option \fB\-nojsri2bsr\fR can be used to disable it.
764.IP "\fB\-sifilter\fR" 4
765.IX Item "-sifilter"
766.PD 0
767.IP "\fB\-nosifilter\fR" 4
768.IX Item "-nosifilter"
770Enable or disable the silicon filter behaviour. By default this is disabled.
771The default can be overridden by the \fB\-sifilter\fR command line option.
772.IP "\fB\-relax\fR" 4
773.IX Item "-relax"
774Alter jump instructions for long displacements.
775.IP "\fB\-mcpu=[210|340]\fR" 4
776.IX Item "-mcpu=[210|340]"
777Select the cpu type on the target hardware. This controls which instructions
778can be assembled.
779.IP "\fB\-EB\fR" 4
780.IX Item "-EB"
781Assemble for a big endian target.
782.IP "\fB\-EL\fR" 4
783.IX Item "-EL"
784Assemble for a little endian target.
786See the info pages for documentation of the MMIX-specific options.
788.IX Header "SEE ALSO"
789\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
791.IX Header "COPYRIGHT"
792Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 Free Software Foundation, Inc.
794Permission is granted to copy, distribute and/or modify this document
795under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
796or any later version published by the Free Software Foundation;
797with no Invariant Sections, with no Front-Cover Texts, and with no
798Back-Cover Texts. A copy of the license is included in the
799section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".