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[dragonfly.git] / sys / dev / agp / agp_i810.c
CommitLineData
ab5a0ec8 1/*
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2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
aa31142a 27 * $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.43 2007/11/12 21:51:36 jhb Exp $
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28 */
29
30/*
31 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
fdc3c5be 32 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
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33 */
34
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35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/malloc.h>
38#include <sys/kernel.h>
39#include <sys/bus.h>
40#include <sys/lock.h>
1f7ab7c9 41#include <sys/rman.h>
984263bc 42
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43#include <bus/pci/pcivar.h>
44#include <bus/pci/pcireg.h>
45#include "agppriv.h"
46#include "agpreg.h"
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47
48#include <vm/vm.h>
49#include <vm/vm_object.h>
50#include <vm/vm_page.h>
51#include <vm/vm_pageout.h>
52#include <vm/pmap.h>
53
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54#include <machine/md_var.h>
55
56#define bus_read_1(r, o) \
57 bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
58#define bus_read_4(r, o) \
59 bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
60#define bus_write_4(r, o, v) \
61 bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
62
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63MALLOC_DECLARE(M_AGP);
64
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65enum {
66 CHIP_I810, /* i810/i815 */
67 CHIP_I830, /* 830M/845G */
68 CHIP_I855, /* 852GM/855GM/865G */
69 CHIP_I915, /* 915G/915GM */
70 CHIP_I965, /* G965 */
71 CHIP_G33, /* G33/Q33/Q35 */
9cac2c04 72 CHIP_IGD, /* G33 like IGD */
f16c0bab 73 CHIP_G4X, /* G45/Q45 */
fdc3c5be 74};
984263bc 75
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76/* The i810 through i855 have the registers at BAR 1, and the GATT gets
77 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
78 * start of the stolen memory, and should only be accessed by the OS through
79 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
80 * is registers, second 512KB is GATT.
81 */
82static struct resource_spec agp_i810_res_spec[] = {
83 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
84 { -1, 0 }
85};
86
87static struct resource_spec agp_i915_res_spec[] = {
88 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
89 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
90 { -1, 0 }
91};
92
93static struct resource_spec agp_i965_res_spec[] = {
94 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
95 { -1, 0 }
96};
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97
98struct agp_i810_softc {
99 struct agp_softc agp;
100 u_int32_t initial_aperture; /* aperture size at startup */
101 struct agp_gatt *gatt;
102 int chiptype; /* i810-like or i830 */
103 u_int32_t dcache_size; /* i810 only */
104 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
105 device_t bdev; /* bridge device */
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106
107 void *argb_cursor; /* contigmalloc area for ARGB cursor */
108
109 struct resource_spec * sc_res_spec;
110 struct resource *sc_res[2];
111};
112
113/* For adding new devices, devid is the id of the graphics controller
114 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
115 * second head should never be added. The bridge_offset is the offset to
116 * subtract from devid to get the id of the hostb that the device is on.
117 */
118static const struct agp_i810_match {
119 int devid;
120 int chiptype;
121 int bridge_offset;
122 char *name;
123} agp_i810_matches[] = {
124 {0x71218086, CHIP_I810, 0x00010000,
125 "Intel 82810 (i810 GMCH) SVGA controller"},
126 {0x71238086, CHIP_I810, 0x00010000,
127 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
128 {0x71258086, CHIP_I810, 0x00010000,
129 "Intel 82810E (i810E GMCH) SVGA controller"},
130 {0x11328086, CHIP_I810, 0x00020000,
131 "Intel 82815 (i815 GMCH) SVGA controller"},
132 {0x35778086, CHIP_I830, 0x00020000,
133 "Intel 82830M (830M GMCH) SVGA controller"},
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134 {0x25628086, CHIP_I830, 0x00020000,
135 "Intel 82845M (845M GMCH) SVGA controller"},
fdc3c5be 136 {0x35828086, CHIP_I855, 0x00020000,
f16c0bab 137 "Intel 82852/855GM SVGA controller"},
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138 {0x25728086, CHIP_I855, 0x00020000,
139 "Intel 82865G (865G GMCH) SVGA controller"},
140 {0x25828086, CHIP_I915, 0x00020000,
141 "Intel 82915G (915G GMCH) SVGA controller"},
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142 {0x258A8086, CHIP_I915, 0x00020000,
143 "Intel E7221 SVGA controller"},
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144 {0x25928086, CHIP_I915, 0x00020000,
145 "Intel 82915GM (915GM GMCH) SVGA controller"},
146 {0x27728086, CHIP_I915, 0x00020000,
147 "Intel 82945G (945G GMCH) SVGA controller"},
148 {0x27A28086, CHIP_I915, 0x00020000,
149 "Intel 82945GM (945GM GMCH) SVGA controller"},
ca275521 150 {0x27AE8086, CHIP_I915, 0x00020000,
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151 "Intel 945GME SVGA controller"},
152 {0x29728086, CHIP_I965, 0x00020000,
153 "Intel 946GZ SVGA controller"},
154 {0x29828086, CHIP_I965, 0x00020000,
155 "Intel G965 SVGA controller"},
156 {0x29928086, CHIP_I965, 0x00020000,
157 "Intel Q965 SVGA controller"},
f16c0bab 158 {0x29A28086, CHIP_I965, 0x00020000,
fdc3c5be 159 "Intel G965 SVGA controller"},
f16c0bab 160 {0x29B28086, CHIP_G33, 0x00020000,
fdc3c5be 161 "Intel Q35 SVGA controller"},
f16c0bab 162 {0x29C28086, CHIP_G33, 0x00020000,
fdc3c5be 163 "Intel G33 SVGA controller"},
f16c0bab 164 {0x29D28086, CHIP_G33, 0x00020000,
fdc3c5be 165 "Intel Q33 SVGA controller"},
f16c0bab 166 {0x2A028086, CHIP_I965, 0x00020000,
fdc3c5be 167 "Intel GM965 SVGA controller"},
f16c0bab 168 {0x2A128086, CHIP_I965, 0x00020000,
fdc3c5be 169 "Intel GME965 SVGA controller"},
a1a3872c 170 {0x2A428086, CHIP_G4X, 0x00020000,
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171 "Intel GM45 SVGA controller"},
172 {0x2E028086, CHIP_G4X, 0x00020000,
173 "Intel 4 Series SVGA controller"},
174 {0x2E128086, CHIP_G4X, 0x00020000,
175 "Intel Q45 SVGA controller"},
176 {0x2E228086, CHIP_G4X, 0x00020000,
177 "Intel G45 SVGA controller"},
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178 {0x2E328086, CHIP_G4X, 0x00020000,
179 "Intel G41 SVGA controller"},
180 {0xA0018086, CHIP_IGD, 0x00010000,
181 "Intel IGD SVGA controller"},
182 {0xA0118086, CHIP_IGD, 0x00010000,
183 "Intel IGD SVGA controller"},
fdc3c5be 184 {0, 0, 0, NULL}
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185};
186
fdc3c5be 187static const struct agp_i810_match*
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188agp_i810_match(device_t dev)
189{
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190 int i, devid;
191
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192 if (pci_get_class(dev) != PCIC_DISPLAY
193 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
194 return NULL;
195
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196 devid = pci_get_devid(dev);
197 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
198 if (agp_i810_matches[i].devid == devid)
199 break;
200 }
201 if (agp_i810_matches[i].devid == 0)
202 return NULL;
203 else
204 return &agp_i810_matches[i];
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205}
206
207/*
208 * Find bridge device.
209 */
210static device_t
211agp_i810_find_bridge(device_t dev)
212{
213 device_t *children, child;
214 int nchildren, i;
215 u_int32_t devid;
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216 const struct agp_i810_match *match;
217
218 match = agp_i810_match(dev);
219 devid = match->devid - match->bridge_offset;
984263bc 220
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221 if (device_get_children(device_get_parent(device_get_parent(dev)),
222 &children, &nchildren))
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223 return 0;
224
225 for (i = 0; i < nchildren; i++) {
226 child = children[i];
227
228 if (pci_get_devid(child) == devid) {
efda3bd0 229 kfree(children, M_TEMP);
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230 return child;
231 }
232 }
efda3bd0 233 kfree(children, M_TEMP);
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234 return 0;
235}
236
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237static void
238agp_i810_identify(driver_t *driver, device_t parent)
239{
240
241 if (device_find_child(parent, "agp", -1) == NULL &&
242 agp_i810_match(parent))
243 device_add_child(parent, "agp", -1);
244}
245
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246static int
247agp_i810_probe(device_t dev)
248{
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249 device_t bdev;
250 const struct agp_i810_match *match;
251 u_int8_t smram;
252 int gcc1, deven;
253
254 if (resource_disabled("agp", device_get_unit(dev)))
255 return (ENXIO);
256 match = agp_i810_match(dev);
257 if (match == NULL)
258 return ENXIO;
984263bc 259
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260 bdev = agp_i810_find_bridge(dev);
261 if (!bdev) {
262 if (bootverbose)
263 kprintf("I810: can't find bridge device\n");
264 return ENXIO;
265 }
984263bc 266
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267 /*
268 * checking whether internal graphics device has been activated.
269 */
270 switch (match->chiptype) {
271 case CHIP_I810:
272 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
273 if ((smram & AGP_I810_SMRAM_GMS) ==
274 AGP_I810_SMRAM_GMS_DISABLED) {
984263bc 275 if (bootverbose)
fdc3c5be 276 kprintf("I810: disabled, not probing\n");
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277 return ENXIO;
278 }
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279 break;
280 case CHIP_I830:
281 case CHIP_I855:
282 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
283 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
284 AGP_I830_GCC1_DEV2_DISABLED) {
285 if (bootverbose)
286 kprintf("I830: disabled, not probing\n");
287 return ENXIO;
288 }
289 break;
290 case CHIP_I915:
291 case CHIP_I965:
292 case CHIP_G33:
9cac2c04 293 case CHIP_IGD:
a1a3872c 294 case CHIP_G4X:
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295 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
296 if ((deven & AGP_I915_DEVEN_D2F0) ==
297 AGP_I915_DEVEN_D2F0_DISABLED) {
298 if (bootverbose)
299 kprintf("I915: disabled, not probing\n");
300 return ENXIO;
301 }
302 break;
303 }
984263bc 304
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305 device_verbose(dev);
306 if (match->devid == 0x35828086) {
307 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
308 case AGP_I855_GME:
309 device_set_desc(dev,
310 "Intel 82855GME (855GME GMCH) SVGA controller");
ab5a0ec8 311 break;
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312 case AGP_I855_GM:
313 device_set_desc(dev,
314 "Intel 82855GM (855GM GMCH) SVGA controller");
315 break;
316 case AGP_I852_GME:
317 device_set_desc(dev,
318 "Intel 82852GME (852GME GMCH) SVGA controller");
319 break;
320 case AGP_I852_GM:
321 device_set_desc(dev,
322 "Intel 82852GM (852GM GMCH) SVGA controller");
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323 break;
324 default:
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325 device_set_desc(dev,
326 "Intel 8285xM (85xGM GMCH) SVGA controller");
327 break;
984263bc 328 }
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329 } else {
330 device_set_desc(dev, match->name);
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331 }
332
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333 return BUS_PROBE_DEFAULT;
334}
335
336static void
337agp_i810_dump_regs(device_t dev)
338{
339 struct agp_i810_softc *sc = device_get_softc(dev);
340
341 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
342 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
343
344 switch (sc->chiptype) {
345 case CHIP_I810:
346 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
347 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
348 break;
349 case CHIP_I830:
350 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
351 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
352 break;
353 case CHIP_I855:
354 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
355 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
356 break;
357 case CHIP_I915:
358 case CHIP_I965:
359 case CHIP_G33:
9cac2c04 360 case CHIP_IGD:
a1a3872c 361 case CHIP_G4X:
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362 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
363 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
364 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
365 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
366 break;
367 }
368 device_printf(dev, "Aperture resource size: %d bytes\n",
369 AGP_GET_APERTURE(dev));
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370}
371
372static int
373agp_i810_attach(device_t dev)
374{
375 struct agp_i810_softc *sc = device_get_softc(dev);
376 struct agp_gatt *gatt;
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377 const struct agp_i810_match *match;
378 int error;
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379
380 sc->bdev = agp_i810_find_bridge(dev);
381 if (!sc->bdev)
382 return ENOENT;
383
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384 match = agp_i810_match(dev);
385 sc->chiptype = match->chiptype;
984263bc 386
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387 switch (sc->chiptype) {
388 case CHIP_I810:
389 case CHIP_I830:
390 case CHIP_I855:
391 sc->sc_res_spec = agp_i810_res_spec;
392 agp_set_aperture_resource(dev, AGP_APBASE);
984263bc 393 break;
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394 case CHIP_I915:
395 case CHIP_G33:
9cac2c04 396 case CHIP_IGD:
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397 sc->sc_res_spec = agp_i915_res_spec;
398 agp_set_aperture_resource(dev, AGP_I915_GMADR);
984263bc 399 break;
fdc3c5be 400 case CHIP_I965:
f16c0bab 401 case CHIP_G4X:
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402 sc->sc_res_spec = agp_i965_res_spec;
403 agp_set_aperture_resource(dev, AGP_I915_GMADR);
ab5a0ec8 404 break;
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HT
405 }
406
407 error = agp_generic_attach(dev);
408 if (error)
409 return error;
984263bc 410
fdc3c5be 411 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
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MD
412 sc->chiptype != CHIP_IGD && sc->chiptype != CHIP_G4X &&
413 ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
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HT
414 {
415 device_printf(dev, "agp_i810.c does not support physical "
416 "memory above 4GB.\n");
417 return ENOENT;
418 }
419
420 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
984263bc 421 agp_generic_detach(dev);
fdc3c5be 422 return ENODEV;
984263bc 423 }
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424
425 sc->initial_aperture = AGP_GET_APERTURE(dev);
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MD
426 if (sc->initial_aperture == 0) {
427 device_printf(dev, "bad initial aperture size, disabling\n");
428 return ENXIO;
429 }
984263bc 430
efda3bd0 431 gatt = kmalloc( sizeof(struct agp_gatt), M_AGP, M_INTWAIT);
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MD
432 sc->gatt = gatt;
433
434 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
435
436 if ( sc->chiptype == CHIP_I810 ) {
437 /* Some i810s have on-chip memory called dcache */
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HT
438 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
439 AGP_I810_DRT_POPULATED)
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440 sc->dcache_size = 4 * 1024 * 1024;
441 else
442 sc->dcache_size = 0;
443
444 /* According to the specs the gatt on the i810 must be 64k */
445 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
446 0, ~0, PAGE_SIZE, 0);
447 if (!gatt->ag_virtual) {
448 if (bootverbose)
449 device_printf(dev, "contiguous allocation failed\n");
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450 bus_release_resources(dev, sc->sc_res_spec,
451 sc->sc_res);
efda3bd0 452 kfree(gatt, M_AGP);
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453 agp_generic_detach(dev);
454 return ENOMEM;
455 }
456 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
457
458 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
459 agp_flush_cache();
460 /* Install the GATT. */
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461 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
462 gatt->ag_physical | 1);
463 } else if ( sc->chiptype == CHIP_I830 ) {
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464 /* The i830 automatically initializes the 128k gatt on boot. */
465 unsigned int gcc1, pgtblctl;
466
467 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
468 switch (gcc1 & AGP_I830_GCC1_GMS) {
469 case AGP_I830_GCC1_GMS_STOLEN_512:
470 sc->stolen = (512 - 132) * 1024 / 4096;
471 break;
472 case AGP_I830_GCC1_GMS_STOLEN_1024:
473 sc->stolen = (1024 - 132) * 1024 / 4096;
474 break;
475 case AGP_I830_GCC1_GMS_STOLEN_8192:
476 sc->stolen = (8192 - 132) * 1024 / 4096;
477 break;
478 default:
479 sc->stolen = 0;
480 device_printf(dev, "unknown memory configuration, disabling\n");
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481 bus_release_resources(dev, sc->sc_res_spec,
482 sc->sc_res);
483 kfree(gatt, M_AGP);
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484 agp_generic_detach(dev);
485 return EINVAL;
486 }
ab5a0ec8 487 if (sc->stolen > 0) {
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488 device_printf(dev, "detected %dk stolen memory\n",
489 sc->stolen * 4);
ab5a0ec8 490 }
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491 device_printf(dev, "aperture size is %dM\n",
492 sc->initial_aperture / 1024 / 1024);
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493
494 /* GATT address is already in there, make sure it's enabled */
fdc3c5be 495 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
984263bc 496 pgtblctl |= 1;
fdc3c5be 497 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
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498
499 gatt->ag_physical = pgtblctl & ~1;
fdc3c5be 500 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
f16c0bab 501 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
9cac2c04 502 sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
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503 unsigned int gcc1, pgtblctl, stolen, gtt_size;
504
505 /* Stolen memory is set up at the beginning of the aperture by
506 * the BIOS, consisting of the GATT followed by 4kb for the
507 * BIOS display.
508 */
509 switch (sc->chiptype) {
510 case CHIP_I855:
511 gtt_size = 128;
512 break;
513 case CHIP_I915:
514 gtt_size = 256;
515 break;
516 case CHIP_I965:
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517 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
518 AGP_I810_PGTBL_SIZE_MASK) {
519 case AGP_I810_PGTBL_SIZE_128KB:
520 gtt_size = 128;
521 break;
522 case AGP_I810_PGTBL_SIZE_256KB:
523 gtt_size = 256;
524 break;
525 case AGP_I810_PGTBL_SIZE_512KB:
526 gtt_size = 512;
527 break;
f16c0bab
HT
528 case AGP_I965_PGTBL_SIZE_1MB:
529 gtt_size = 1024;
530 break;
531 case AGP_I965_PGTBL_SIZE_2MB:
532 gtt_size = 2048;
533 break;
534 case AGP_I965_PGTBL_SIZE_1_5MB:
535 gtt_size = 1024 + 512;
536 break;
537 default:
538 device_printf(dev, "Bad PGTBL size\n");
539 bus_release_resources(dev, sc->sc_res_spec,
540 sc->sc_res);
541 kfree(gatt, M_AGP);
542 agp_generic_detach(dev);
543 return EINVAL;
544 }
545 break;
546 case CHIP_G33:
547 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
548 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
549 case AGP_G33_MGGC_GGMS_SIZE_1M:
550 gtt_size = 1024;
551 break;
552 case AGP_G33_MGGC_GGMS_SIZE_2M:
553 gtt_size = 2048;
554 break;
fdc3c5be
HT
555 default:
556 device_printf(dev, "Bad PGTBL size\n");
557 bus_release_resources(dev, sc->sc_res_spec,
558 sc->sc_res);
559 kfree(gatt, M_AGP);
560 agp_generic_detach(dev);
561 return EINVAL;
562 }
563 break;
9cac2c04 564 case CHIP_IGD:
f16c0bab
HT
565 case CHIP_G4X:
566 gtt_size = 0;
567 break;
fdc3c5be
HT
568 default:
569 device_printf(dev, "Bad chiptype\n");
570 bus_release_resources(dev, sc->sc_res_spec,
571 sc->sc_res);
572 kfree(gatt, M_AGP);
573 agp_generic_detach(dev);
574 return EINVAL;
575 }
984263bc 576
fdc3c5be 577 /* GCC1 is called MGGC on i915+ */
ab5a0ec8
MD
578 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
579 switch (gcc1 & AGP_I855_GCC1_GMS) {
580 case AGP_I855_GCC1_GMS_STOLEN_1M:
fdc3c5be 581 stolen = 1024;
ab5a0ec8
MD
582 break;
583 case AGP_I855_GCC1_GMS_STOLEN_4M:
f16c0bab 584 stolen = 4 * 1024;
ab5a0ec8
MD
585 break;
586 case AGP_I855_GCC1_GMS_STOLEN_8M:
f16c0bab 587 stolen = 8 * 1024;
ab5a0ec8
MD
588 break;
589 case AGP_I855_GCC1_GMS_STOLEN_16M:
f16c0bab 590 stolen = 16 * 1024;
ab5a0ec8
MD
591 break;
592 case AGP_I855_GCC1_GMS_STOLEN_32M:
f16c0bab 593 stolen = 32 * 1024;
fdc3c5be
HT
594 break;
595 case AGP_I915_GCC1_GMS_STOLEN_48M:
f16c0bab
HT
596 if (sc->chiptype == CHIP_I915 ||
597 sc->chiptype == CHIP_I965 ||
598 sc->chiptype == CHIP_G33 ||
9cac2c04 599 sc->chiptype == CHIP_IGD ||
f16c0bab
HT
600 sc->chiptype == CHIP_G4X) {
601 stolen = 48 * 1024;
602 } else {
603 stolen = 0;
604 }
fdc3c5be
HT
605 break;
606 case AGP_I915_GCC1_GMS_STOLEN_64M:
f16c0bab
HT
607 if (sc->chiptype == CHIP_I915 ||
608 sc->chiptype == CHIP_I965 ||
609 sc->chiptype == CHIP_G33 ||
9cac2c04 610 sc->chiptype == CHIP_IGD ||
f16c0bab
HT
611 sc->chiptype == CHIP_G4X) {
612 stolen = 64 * 1024;
613 } else {
614 stolen = 0;
615 }
fdc3c5be
HT
616 break;
617 case AGP_G33_GCC1_GMS_STOLEN_128M:
f16c0bab
HT
618 if (sc->chiptype == CHIP_I965 ||
619 sc->chiptype == CHIP_G33 ||
9cac2c04 620 sc->chiptype == CHIP_IGD ||
f16c0bab
HT
621 sc->chiptype == CHIP_G4X) {
622 stolen = 128 * 1024;
623 } else {
624 stolen = 0;
625 }
fdc3c5be
HT
626 break;
627 case AGP_G33_GCC1_GMS_STOLEN_256M:
f16c0bab
HT
628 if (sc->chiptype == CHIP_I965 ||
629 sc->chiptype == CHIP_G33 ||
9cac2c04 630 sc->chiptype == CHIP_IGD ||
f16c0bab
HT
631 sc->chiptype == CHIP_G4X) {
632 stolen = 256 * 1024;
633 } else {
634 stolen = 0;
635 }
636 break;
637 case AGP_G4X_GCC1_GMS_STOLEN_96M:
638 if (sc->chiptype == CHIP_I965 ||
639 sc->chiptype == CHIP_G4X) {
640 stolen = 96 * 1024;
641 } else {
642 stolen = 0;
643 }
644 break;
645 case AGP_G4X_GCC1_GMS_STOLEN_160M:
646 if (sc->chiptype == CHIP_I965 ||
647 sc->chiptype == CHIP_G4X) {
648 stolen = 160 * 1024;
649 } else {
650 stolen = 0;
651 }
652 break;
653 case AGP_G4X_GCC1_GMS_STOLEN_224M:
654 if (sc->chiptype == CHIP_I965 ||
655 sc->chiptype == CHIP_G4X) {
656 stolen = 224 * 1024;
657 } else {
658 stolen = 0;
659 }
660 break;
661 case AGP_G4X_GCC1_GMS_STOLEN_352M:
662 if (sc->chiptype == CHIP_I965 ||
663 sc->chiptype == CHIP_G4X) {
664 stolen = 352 * 1024;
665 } else {
666 stolen = 0;
667 }
ab5a0ec8
MD
668 break;
669 default:
fdc3c5be
HT
670 device_printf(dev, "unknown memory configuration, "
671 "disabling\n");
672 bus_release_resources(dev, sc->sc_res_spec,
673 sc->sc_res);
674 kfree(gatt, M_AGP);
ab5a0ec8
MD
675 agp_generic_detach(dev);
676 return EINVAL;
677 }
f16c0bab 678
a1a3872c 679 gtt_size += 4;
f16c0bab
HT
680
681 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
fdc3c5be
HT
682 if (sc->stolen > 0)
683 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
684 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
984263bc 685
ab5a0ec8 686 /* GATT address is already in there, make sure it's enabled */
fdc3c5be 687 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
ab5a0ec8 688 pgtblctl |= 1;
fdc3c5be 689 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
ab5a0ec8
MD
690
691 gatt->ag_physical = pgtblctl & ~1;
fdc3c5be
HT
692 }
693
694 if (0)
695 agp_i810_dump_regs(dev);
696
984263bc
MD
697 return 0;
698}
699
700static int
701agp_i810_detach(device_t dev)
702{
703 struct agp_i810_softc *sc = device_get_softc(dev);
984263bc 704
67e2dc5d 705 agp_free_cdev(dev);
984263bc
MD
706
707 /* Clear the GATT base. */
708 if ( sc->chiptype == CHIP_I810 ) {
fdc3c5be 709 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
984263bc
MD
710 } else {
711 unsigned int pgtblctl;
fdc3c5be 712 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
984263bc 713 pgtblctl &= ~1;
fdc3c5be 714 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
984263bc
MD
715 }
716
717 /* Put the aperture back the way it started. */
718 AGP_SET_APERTURE(dev, sc->initial_aperture);
719
720 if ( sc->chiptype == CHIP_I810 ) {
721 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
722 }
efda3bd0 723 kfree(sc->gatt, M_AGP);
984263bc 724
fdc3c5be 725 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
67e2dc5d 726 agp_free_res(dev);
984263bc
MD
727
728 return 0;
729}
730
2f1d30c1
HT
731static int
732agp_i810_resume(device_t dev)
733{
734 struct agp_i810_softc *sc;
735 sc = device_get_softc(dev);
736
737 AGP_SET_APERTURE(dev, sc->initial_aperture);
738
739 /* Install the GATT. */
740 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
741 sc->gatt->ag_physical | 1);
742
743 return (bus_generic_resume(dev));
744}
745
fdc3c5be
HT
746/**
747 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
748 * while returning failure on later chipsets when an actual change is
749 * requested.
750 *
751 * This whole function is likely bogus, as the kernel would probably need to
752 * reconfigure the placement of the AGP aperture if a larger size is requested,
753 * which doesn't happen currently.
754 */
984263bc
MD
755static int
756agp_i810_set_aperture(device_t dev, u_int32_t aperture)
757{
758 struct agp_i810_softc *sc = device_get_softc(dev);
fdc3c5be 759 u_int16_t miscc, gcc1;
984263bc 760
fdc3c5be
HT
761 switch (sc->chiptype) {
762 case CHIP_I810:
984263bc
MD
763 /*
764 * Double check for sanity.
765 */
766 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
767 device_printf(dev, "bad aperture size %d\n", aperture);
768 return EINVAL;
769 }
fdc3c5be 770
984263bc
MD
771 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
772 miscc &= ~AGP_I810_MISCC_WINSIZE;
773 if (aperture == 32 * 1024 * 1024)
774 miscc |= AGP_I810_MISCC_WINSIZE_32;
775 else
776 miscc |= AGP_I810_MISCC_WINSIZE_64;
777
778 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
fdc3c5be
HT
779 break;
780 case CHIP_I830:
781 if (aperture != 64 * 1024 * 1024 &&
782 aperture != 128 * 1024 * 1024) {
984263bc
MD
783 device_printf(dev, "bad aperture size %d\n", aperture);
784 return EINVAL;
785 }
786 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
787 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
788 if (aperture == 64 * 1024 * 1024)
789 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
790 else
791 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
792
793 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
fdc3c5be
HT
794 break;
795 case CHIP_I855:
796 case CHIP_I915:
797 case CHIP_I965:
798 case CHIP_G33:
9cac2c04 799 case CHIP_IGD:
a1a3872c 800 case CHIP_G4X:
fdc3c5be 801 return agp_generic_set_aperture(dev, aperture);
984263bc
MD
802 }
803
804 return 0;
805}
806
fdc3c5be
HT
807/**
808 * Writes a GTT entry mapping the page at the given offset from the beginning
809 * of the aperture to the given physical address.
810 */
811static void
812agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
813 int enabled)
814{
815 struct agp_i810_softc *sc = device_get_softc(dev);
816 u_int32_t pte;
817
818 pte = (u_int32_t)physical | 1;
a1a3872c 819 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
9cac2c04 820 sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
fdc3c5be
HT
821 pte |= (physical & 0x0000000f00000000ull) >> 28;
822 } else {
823 /* If we do actually have memory above 4GB on an older system,
824 * crash cleanly rather than scribble on system memory,
825 * so we know we need to fix it.
826 */
827 KASSERT((pte & 0x0000000f00000000ull) == 0,
828 (">4GB physical address in agp"));
829 }
830
831 switch (sc->chiptype) {
832 case CHIP_I810:
833 case CHIP_I830:
834 case CHIP_I855:
835 bus_write_4(sc->sc_res[0],
836 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
837 break;
838 case CHIP_I915:
839 case CHIP_G33:
9cac2c04 840 case CHIP_IGD:
fdc3c5be
HT
841 bus_write_4(sc->sc_res[1],
842 (offset >> AGP_PAGE_SHIFT) * 4, pte);
843 break;
844 case CHIP_I965:
845 bus_write_4(sc->sc_res[0],
846 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
847 break;
a1a3872c
HT
848 case CHIP_G4X:
849 bus_write_4(sc->sc_res[0],
850 (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
851 break;
fdc3c5be
HT
852 }
853}
854
984263bc
MD
855static int
856agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
857{
858 struct agp_i810_softc *sc = device_get_softc(dev);
859
860 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
861 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
862 return EINVAL;
863 }
864
fdc3c5be 865 if ( sc->chiptype != CHIP_I810 ) {
984263bc
MD
866 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
867 device_printf(dev, "trying to bind into stolen memory");
868 return EINVAL;
869 }
870 }
871
fdc3c5be
HT
872 agp_i810_write_gtt_entry(dev, offset, physical, 1);
873
984263bc
MD
874 return 0;
875}
876
877static int
878agp_i810_unbind_page(device_t dev, int offset)
879{
880 struct agp_i810_softc *sc = device_get_softc(dev);
881
882 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
883 return EINVAL;
884
fdc3c5be 885 if ( sc->chiptype != CHIP_I810 ) {
984263bc
MD
886 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
887 device_printf(dev, "trying to unbind from stolen memory");
888 return EINVAL;
889 }
890 }
891
fdc3c5be
HT
892 agp_i810_write_gtt_entry(dev, offset, 0, 0);
893
984263bc
MD
894 return 0;
895}
896
897/*
898 * Writing via memory mapped registers already flushes all TLBs.
899 */
900static void
901agp_i810_flush_tlb(device_t dev)
902{
903}
904
905static int
906agp_i810_enable(device_t dev, u_int32_t mode)
907{
908
909 return 0;
910}
911
912static struct agp_memory *
913agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
914{
915 struct agp_i810_softc *sc = device_get_softc(dev);
916 struct agp_memory *mem;
917
918 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
919 return 0;
920
921 if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
922 return 0;
923
924 if (type == 1) {
925 /*
926 * Mapping local DRAM into GATT.
927 */
fdc3c5be 928 if ( sc->chiptype != CHIP_I810 )
984263bc
MD
929 return 0;
930 if (size != sc->dcache_size)
931 return 0;
932 } else if (type == 2) {
933 /*
fdc3c5be
HT
934 * Type 2 is the contiguous physical memory type, that hands
935 * back a physical address. This is used for cursors on i810.
936 * Hand back as many single pages with physical as the user
937 * wants, but only allow one larger allocation (ARGB cursor)
938 * for simplicity.
984263bc 939 */
fdc3c5be
HT
940 if (size != AGP_PAGE_SIZE) {
941 if (sc->argb_cursor != NULL)
942 return 0;
943
944 /* Allocate memory for ARGB cursor, if we can. */
945 sc->argb_cursor = contigmalloc(size, M_AGP,
946 0, 0, ~0, PAGE_SIZE, 0);
947 if (sc->argb_cursor == NULL)
948 return 0;
949 }
984263bc
MD
950 }
951
efda3bd0 952 mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
984263bc
MD
953 mem->am_id = sc->agp.as_nextid++;
954 mem->am_size = size;
955 mem->am_type = type;
fdc3c5be 956 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
984263bc
MD
957 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
958 atop(round_page(size)));
959 else
960 mem->am_obj = 0;
961
962 if (type == 2) {
fdc3c5be
HT
963 if (size == AGP_PAGE_SIZE) {
964 /*
965 * Allocate and wire down the page now so that we can
966 * get its physical address.
967 */
968 vm_page_t m;
969
d2d8515b
MD
970 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NORMAL |
971 VM_ALLOC_ZERO |
972 VM_ALLOC_RETRY);
fdc3c5be
HT
973 vm_page_wire(m);
974 mem->am_physical = VM_PAGE_TO_PHYS(m);
975 vm_page_wakeup(m);
976 } else {
977 /* Our allocation is already nicely wired down for us.
978 * Just grab the physical address.
979 */
980 mem->am_physical = vtophys(sc->argb_cursor);
981 }
984263bc
MD
982 } else {
983 mem->am_physical = 0;
984 }
985
986 mem->am_offset = 0;
987 mem->am_is_bound = 0;
988 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
989 sc->agp.as_allocated += size;
990
991 return mem;
992}
993
994static int
995agp_i810_free_memory(device_t dev, struct agp_memory *mem)
996{
997 struct agp_i810_softc *sc = device_get_softc(dev);
998
999 if (mem->am_is_bound)
1000 return EBUSY;
1001
1002 if (mem->am_type == 2) {
fdc3c5be
HT
1003 if (mem->am_size == AGP_PAGE_SIZE) {
1004 /*
1005 * Unwire the page which we wired in alloc_memory.
1006 */
77912481 1007 vm_page_t m;
b12defdc
MD
1008
1009 vm_object_hold(mem->am_obj);
1010 m = vm_page_lookup_busy_wait(mem->am_obj, 0,
1011 FALSE, "agppg");
1012 vm_object_drop(mem->am_obj);
fdc3c5be 1013 vm_page_unwire(m, 0);
b12defdc 1014 vm_page_wakeup(m);
fdc3c5be
HT
1015 } else {
1016 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1017 sc->argb_cursor = NULL;
1018 }
984263bc
MD
1019 }
1020
1021 sc->agp.as_allocated -= mem->am_size;
1022 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1023 if (mem->am_obj)
1024 vm_object_deallocate(mem->am_obj);
efda3bd0 1025 kfree(mem, M_AGP);
984263bc
MD
1026 return 0;
1027}
1028
1029static int
1030agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1031 vm_offset_t offset)
1032{
1033 struct agp_i810_softc *sc = device_get_softc(dev);
1034 vm_offset_t i;
1035
fdc3c5be
HT
1036 /* Do some sanity checks first. */
1037 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1038 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1039 device_printf(dev, "binding memory at bad offset %#x\n",
1040 (int)offset);
1041 return EINVAL;
1042 }
1043
1044 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1045 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1046 if (mem->am_is_bound) {
1047 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1048 return EINVAL;
1049 }
1050 /* The memory's already wired down, just stick it in the GTT. */
1051 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1052 agp_i810_write_gtt_entry(dev, offset + i,
1053 mem->am_physical + i, 1);
1054 }
1055 agp_flush_cache();
1056 mem->am_offset = offset;
1057 mem->am_is_bound = 1;
1058 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1059 return 0;
1060 }
1061
984263bc
MD
1062 if (mem->am_type != 1)
1063 return agp_generic_bind_memory(dev, mem, offset);
1064
fdc3c5be 1065 if ( sc->chiptype != CHIP_I810 )
984263bc
MD
1066 return EINVAL;
1067
1068 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
fdc3c5be
HT
1069 bus_write_4(sc->sc_res[0],
1070 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
984263bc
MD
1071 }
1072
1073 return 0;
1074}
1075
1076static int
1077agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1078{
1079 struct agp_i810_softc *sc = device_get_softc(dev);
1080 vm_offset_t i;
1081
fdc3c5be
HT
1082 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1083 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1084 if (!mem->am_is_bound) {
1085 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1086 return EINVAL;
1087 }
1088
1089 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1090 agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1091 0, 0);
1092 }
1093 agp_flush_cache();
1094 mem->am_is_bound = 0;
1095 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1096 return 0;
1097 }
1098
984263bc
MD
1099 if (mem->am_type != 1)
1100 return agp_generic_unbind_memory(dev, mem);
1101
fdc3c5be 1102 if ( sc->chiptype != CHIP_I810 )
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1103 return EINVAL;
1104
fdc3c5be
HT
1105 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1106 bus_write_4(sc->sc_res[0],
1107 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1108 }
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1109
1110 return 0;
1111}
1112
1113static device_method_t agp_i810_methods[] = {
1114 /* Device interface */
fdc3c5be 1115 DEVMETHOD(device_identify, agp_i810_identify),
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1116 DEVMETHOD(device_probe, agp_i810_probe),
1117 DEVMETHOD(device_attach, agp_i810_attach),
1118 DEVMETHOD(device_detach, agp_i810_detach),
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1119 DEVMETHOD(device_suspend, bus_generic_suspend),
1120 DEVMETHOD(device_resume, agp_i810_resume),
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1121
1122 /* AGP interface */
fdc3c5be 1123 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
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1124 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
1125 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1126 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1127 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1128 DEVMETHOD(agp_enable, agp_i810_enable),
1129 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1130 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1131 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1132 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
1133
1134 { 0, 0 }
1135};
1136
1137static driver_t agp_i810_driver = {
1138 "agp",
1139 agp_i810_methods,
1140 sizeof(struct agp_i810_softc),
1141};
1142
1143static devclass_t agp_devclass;
1144
aa2b9d05 1145DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, NULL, NULL);
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1146MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1147MODULE_DEPEND(agp_i810, pci, 1, 1, 1);