Factor out re_free_rxchain()
[dragonfly.git] / sys / dev / agp / agp_i810.c
CommitLineData
ab5a0ec8 1/*
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2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
aa31142a 27 * $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.43 2007/11/12 21:51:36 jhb Exp $
2f1d30c1 28 * $DragonFly: src/sys/dev/agp/agp_i810.c,v 1.18 2008/08/22 07:08:13 hasso Exp $
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29 */
30
31/*
32 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
fdc3c5be 33 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
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34 */
35
36#include "opt_bus.h"
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37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/bus.h>
43#include <sys/lock.h>
1f7ab7c9 44#include <sys/rman.h>
984263bc 45
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46#include <bus/pci/pcivar.h>
47#include <bus/pci/pcireg.h>
48#include "agppriv.h"
49#include "agpreg.h"
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50
51#include <vm/vm.h>
52#include <vm/vm_object.h>
53#include <vm/vm_page.h>
54#include <vm/vm_pageout.h>
55#include <vm/pmap.h>
56
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57#include <machine/md_var.h>
58
59#define bus_read_1(r, o) \
60 bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
61#define bus_read_4(r, o) \
62 bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
63#define bus_write_4(r, o, v) \
64 bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
65
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66MALLOC_DECLARE(M_AGP);
67
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68enum {
69 CHIP_I810, /* i810/i815 */
70 CHIP_I830, /* 830M/845G */
71 CHIP_I855, /* 852GM/855GM/865G */
72 CHIP_I915, /* 915G/915GM */
73 CHIP_I965, /* G965 */
74 CHIP_G33, /* G33/Q33/Q35 */
75};
984263bc 76
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77/* The i810 through i855 have the registers at BAR 1, and the GATT gets
78 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
79 * start of the stolen memory, and should only be accessed by the OS through
80 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
81 * is registers, second 512KB is GATT.
82 */
83static struct resource_spec agp_i810_res_spec[] = {
84 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
85 { -1, 0 }
86};
87
88static struct resource_spec agp_i915_res_spec[] = {
89 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
90 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
91 { -1, 0 }
92};
93
94static struct resource_spec agp_i965_res_spec[] = {
95 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
96 { -1, 0 }
97};
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98
99struct agp_i810_softc {
100 struct agp_softc agp;
101 u_int32_t initial_aperture; /* aperture size at startup */
102 struct agp_gatt *gatt;
103 int chiptype; /* i810-like or i830 */
104 u_int32_t dcache_size; /* i810 only */
105 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
106 device_t bdev; /* bridge device */
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107
108 void *argb_cursor; /* contigmalloc area for ARGB cursor */
109
110 struct resource_spec * sc_res_spec;
111 struct resource *sc_res[2];
112};
113
114/* For adding new devices, devid is the id of the graphics controller
115 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
116 * second head should never be added. The bridge_offset is the offset to
117 * subtract from devid to get the id of the hostb that the device is on.
118 */
119static const struct agp_i810_match {
120 int devid;
121 int chiptype;
122 int bridge_offset;
123 char *name;
124} agp_i810_matches[] = {
125 {0x71218086, CHIP_I810, 0x00010000,
126 "Intel 82810 (i810 GMCH) SVGA controller"},
127 {0x71238086, CHIP_I810, 0x00010000,
128 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
129 {0x71258086, CHIP_I810, 0x00010000,
130 "Intel 82810E (i810E GMCH) SVGA controller"},
131 {0x11328086, CHIP_I810, 0x00020000,
132 "Intel 82815 (i815 GMCH) SVGA controller"},
133 {0x35778086, CHIP_I830, 0x00020000,
134 "Intel 82830M (830M GMCH) SVGA controller"},
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135 {0x25628086, CHIP_I830, 0x00020000,
136 "Intel 82845M (845M GMCH) SVGA controller"},
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137 {0x35828086, CHIP_I855, 0x00020000,
138 "Intel 82852/5"},
139 {0x25728086, CHIP_I855, 0x00020000,
140 "Intel 82865G (865G GMCH) SVGA controller"},
141 {0x25828086, CHIP_I915, 0x00020000,
142 "Intel 82915G (915G GMCH) SVGA controller"},
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143 {0x258A8086, CHIP_I915, 0x00020000,
144 "Intel E7221 SVGA controller"},
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145 {0x25928086, CHIP_I915, 0x00020000,
146 "Intel 82915GM (915GM GMCH) SVGA controller"},
147 {0x27728086, CHIP_I915, 0x00020000,
148 "Intel 82945G (945G GMCH) SVGA controller"},
149 {0x27A28086, CHIP_I915, 0x00020000,
150 "Intel 82945GM (945GM GMCH) SVGA controller"},
ca275521 151 {0x27AE8086, CHIP_I915, 0x00020000,
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152 "Intel 945GME SVGA controller"},
153 {0x29728086, CHIP_I965, 0x00020000,
154 "Intel 946GZ SVGA controller"},
155 {0x29828086, CHIP_I965, 0x00020000,
156 "Intel G965 SVGA controller"},
157 {0x29928086, CHIP_I965, 0x00020000,
158 "Intel Q965 SVGA controller"},
159 {0x29a28086, CHIP_I965, 0x00020000,
160 "Intel G965 SVGA controller"},
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161 {0x29b28086, CHIP_G33, 0x00020000,
162 "Intel Q35 SVGA controller"},
163 {0x29c28086, CHIP_G33, 0x00020000,
164 "Intel G33 SVGA controller"},
165 {0x29d28086, CHIP_G33, 0x00020000,
166 "Intel Q33 SVGA controller"},
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167 {0x2a028086, CHIP_I965, 0x00020000,
168 "Intel GM965 SVGA controller"},
169 {0x2a128086, CHIP_I965, 0x00020000,
170 "Intel GME965 SVGA controller"},
171 {0, 0, 0, NULL}
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172};
173
fdc3c5be 174static const struct agp_i810_match*
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175agp_i810_match(device_t dev)
176{
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177 int i, devid;
178
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179 if (pci_get_class(dev) != PCIC_DISPLAY
180 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
181 return NULL;
182
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183 devid = pci_get_devid(dev);
184 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
185 if (agp_i810_matches[i].devid == devid)
186 break;
187 }
188 if (agp_i810_matches[i].devid == 0)
189 return NULL;
190 else
191 return &agp_i810_matches[i];
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192}
193
194/*
195 * Find bridge device.
196 */
197static device_t
198agp_i810_find_bridge(device_t dev)
199{
200 device_t *children, child;
201 int nchildren, i;
202 u_int32_t devid;
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203 const struct agp_i810_match *match;
204
205 match = agp_i810_match(dev);
206 devid = match->devid - match->bridge_offset;
984263bc 207
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208 if (device_get_children(device_get_parent(dev), &children, &nchildren))
209 return 0;
210
211 for (i = 0; i < nchildren; i++) {
212 child = children[i];
213
214 if (pci_get_devid(child) == devid) {
efda3bd0 215 kfree(children, M_TEMP);
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216 return child;
217 }
218 }
efda3bd0 219 kfree(children, M_TEMP);
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220 return 0;
221}
222
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223static void
224agp_i810_identify(driver_t *driver, device_t parent)
225{
226
227 if (device_find_child(parent, "agp", -1) == NULL &&
228 agp_i810_match(parent))
229 device_add_child(parent, "agp", -1);
230}
231
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232static int
233agp_i810_probe(device_t dev)
234{
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235 device_t bdev;
236 const struct agp_i810_match *match;
237 u_int8_t smram;
238 int gcc1, deven;
239
240 if (resource_disabled("agp", device_get_unit(dev)))
241 return (ENXIO);
242 match = agp_i810_match(dev);
243 if (match == NULL)
244 return ENXIO;
984263bc 245
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246 bdev = agp_i810_find_bridge(dev);
247 if (!bdev) {
248 if (bootverbose)
249 kprintf("I810: can't find bridge device\n");
250 return ENXIO;
251 }
984263bc 252
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253 /*
254 * checking whether internal graphics device has been activated.
255 */
256 switch (match->chiptype) {
257 case CHIP_I810:
258 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
259 if ((smram & AGP_I810_SMRAM_GMS) ==
260 AGP_I810_SMRAM_GMS_DISABLED) {
984263bc 261 if (bootverbose)
fdc3c5be 262 kprintf("I810: disabled, not probing\n");
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263 return ENXIO;
264 }
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265 break;
266 case CHIP_I830:
267 case CHIP_I855:
268 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
269 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
270 AGP_I830_GCC1_DEV2_DISABLED) {
271 if (bootverbose)
272 kprintf("I830: disabled, not probing\n");
273 return ENXIO;
274 }
275 break;
276 case CHIP_I915:
277 case CHIP_I965:
278 case CHIP_G33:
279 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
280 if ((deven & AGP_I915_DEVEN_D2F0) ==
281 AGP_I915_DEVEN_D2F0_DISABLED) {
282 if (bootverbose)
283 kprintf("I915: disabled, not probing\n");
284 return ENXIO;
285 }
286 break;
287 }
984263bc 288
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289 device_verbose(dev);
290 if (match->devid == 0x35828086) {
291 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
292 case AGP_I855_GME:
293 device_set_desc(dev,
294 "Intel 82855GME (855GME GMCH) SVGA controller");
ab5a0ec8 295 break;
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296 case AGP_I855_GM:
297 device_set_desc(dev,
298 "Intel 82855GM (855GM GMCH) SVGA controller");
299 break;
300 case AGP_I852_GME:
301 device_set_desc(dev,
302 "Intel 82852GME (852GME GMCH) SVGA controller");
303 break;
304 case AGP_I852_GM:
305 device_set_desc(dev,
306 "Intel 82852GM (852GM GMCH) SVGA controller");
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307 break;
308 default:
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309 device_set_desc(dev,
310 "Intel 8285xM (85xGM GMCH) SVGA controller");
311 break;
984263bc 312 }
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313 } else {
314 device_set_desc(dev, match->name);
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315 }
316
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317 return BUS_PROBE_DEFAULT;
318}
319
320static void
321agp_i810_dump_regs(device_t dev)
322{
323 struct agp_i810_softc *sc = device_get_softc(dev);
324
325 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
326 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
327
328 switch (sc->chiptype) {
329 case CHIP_I810:
330 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
331 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
332 break;
333 case CHIP_I830:
334 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
335 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
336 break;
337 case CHIP_I855:
338 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
339 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
340 break;
341 case CHIP_I915:
342 case CHIP_I965:
343 case CHIP_G33:
344 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
345 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
346 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
347 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
348 break;
349 }
350 device_printf(dev, "Aperture resource size: %d bytes\n",
351 AGP_GET_APERTURE(dev));
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352}
353
354static int
355agp_i810_attach(device_t dev)
356{
357 struct agp_i810_softc *sc = device_get_softc(dev);
358 struct agp_gatt *gatt;
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359 const struct agp_i810_match *match;
360 int error;
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361
362 sc->bdev = agp_i810_find_bridge(dev);
363 if (!sc->bdev)
364 return ENOENT;
365
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366 match = agp_i810_match(dev);
367 sc->chiptype = match->chiptype;
984263bc 368
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369 switch (sc->chiptype) {
370 case CHIP_I810:
371 case CHIP_I830:
372 case CHIP_I855:
373 sc->sc_res_spec = agp_i810_res_spec;
374 agp_set_aperture_resource(dev, AGP_APBASE);
984263bc 375 break;
fdc3c5be
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376 case CHIP_I915:
377 case CHIP_G33:
378 sc->sc_res_spec = agp_i915_res_spec;
379 agp_set_aperture_resource(dev, AGP_I915_GMADR);
984263bc 380 break;
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381 case CHIP_I965:
382 sc->sc_res_spec = agp_i965_res_spec;
383 agp_set_aperture_resource(dev, AGP_I915_GMADR);
ab5a0ec8 384 break;
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385 }
386
387 error = agp_generic_attach(dev);
388 if (error)
389 return error;
984263bc 390
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391 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
392 ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
393 {
394 device_printf(dev, "agp_i810.c does not support physical "
395 "memory above 4GB.\n");
396 return ENOENT;
397 }
398
399 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
984263bc 400 agp_generic_detach(dev);
fdc3c5be 401 return ENODEV;
984263bc 402 }
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MD
403
404 sc->initial_aperture = AGP_GET_APERTURE(dev);
f7841f3c
MD
405 if (sc->initial_aperture == 0) {
406 device_printf(dev, "bad initial aperture size, disabling\n");
407 return ENXIO;
408 }
984263bc 409
efda3bd0 410 gatt = kmalloc( sizeof(struct agp_gatt), M_AGP, M_INTWAIT);
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MD
411 sc->gatt = gatt;
412
413 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
414
415 if ( sc->chiptype == CHIP_I810 ) {
416 /* Some i810s have on-chip memory called dcache */
fdc3c5be
HT
417 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
418 AGP_I810_DRT_POPULATED)
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419 sc->dcache_size = 4 * 1024 * 1024;
420 else
421 sc->dcache_size = 0;
422
423 /* According to the specs the gatt on the i810 must be 64k */
424 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
425 0, ~0, PAGE_SIZE, 0);
426 if (!gatt->ag_virtual) {
427 if (bootverbose)
428 device_printf(dev, "contiguous allocation failed\n");
fdc3c5be
HT
429 bus_release_resources(dev, sc->sc_res_spec,
430 sc->sc_res);
efda3bd0 431 kfree(gatt, M_AGP);
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432 agp_generic_detach(dev);
433 return ENOMEM;
434 }
435 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
436
437 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
438 agp_flush_cache();
439 /* Install the GATT. */
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HT
440 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
441 gatt->ag_physical | 1);
442 } else if ( sc->chiptype == CHIP_I830 ) {
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443 /* The i830 automatically initializes the 128k gatt on boot. */
444 unsigned int gcc1, pgtblctl;
445
446 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
447 switch (gcc1 & AGP_I830_GCC1_GMS) {
448 case AGP_I830_GCC1_GMS_STOLEN_512:
449 sc->stolen = (512 - 132) * 1024 / 4096;
450 break;
451 case AGP_I830_GCC1_GMS_STOLEN_1024:
452 sc->stolen = (1024 - 132) * 1024 / 4096;
453 break;
454 case AGP_I830_GCC1_GMS_STOLEN_8192:
455 sc->stolen = (8192 - 132) * 1024 / 4096;
456 break;
457 default:
458 sc->stolen = 0;
459 device_printf(dev, "unknown memory configuration, disabling\n");
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HT
460 bus_release_resources(dev, sc->sc_res_spec,
461 sc->sc_res);
462 kfree(gatt, M_AGP);
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463 agp_generic_detach(dev);
464 return EINVAL;
465 }
ab5a0ec8 466 if (sc->stolen > 0) {
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HT
467 device_printf(dev, "detected %dk stolen memory\n",
468 sc->stolen * 4);
ab5a0ec8 469 }
fdc3c5be
HT
470 device_printf(dev, "aperture size is %dM\n",
471 sc->initial_aperture / 1024 / 1024);
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MD
472
473 /* GATT address is already in there, make sure it's enabled */
fdc3c5be 474 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
984263bc 475 pgtblctl |= 1;
fdc3c5be 476 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
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477
478 gatt->ag_physical = pgtblctl & ~1;
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HT
479 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
480 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33) {
481 unsigned int gcc1, pgtblctl, stolen, gtt_size;
482
483 /* Stolen memory is set up at the beginning of the aperture by
484 * the BIOS, consisting of the GATT followed by 4kb for the
485 * BIOS display.
486 */
487 switch (sc->chiptype) {
488 case CHIP_I855:
489 gtt_size = 128;
490 break;
491 case CHIP_I915:
492 gtt_size = 256;
493 break;
494 case CHIP_I965:
495 case CHIP_G33:
496 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
497 AGP_I810_PGTBL_SIZE_MASK) {
498 case AGP_I810_PGTBL_SIZE_128KB:
499 gtt_size = 128;
500 break;
501 case AGP_I810_PGTBL_SIZE_256KB:
502 gtt_size = 256;
503 break;
504 case AGP_I810_PGTBL_SIZE_512KB:
505 gtt_size = 512;
506 break;
507 default:
508 device_printf(dev, "Bad PGTBL size\n");
509 bus_release_resources(dev, sc->sc_res_spec,
510 sc->sc_res);
511 kfree(gatt, M_AGP);
512 agp_generic_detach(dev);
513 return EINVAL;
514 }
515 break;
516 default:
517 device_printf(dev, "Bad chiptype\n");
518 bus_release_resources(dev, sc->sc_res_spec,
519 sc->sc_res);
520 kfree(gatt, M_AGP);
521 agp_generic_detach(dev);
522 return EINVAL;
523 }
984263bc 524
fdc3c5be 525 /* GCC1 is called MGGC on i915+ */
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MD
526 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
527 switch (gcc1 & AGP_I855_GCC1_GMS) {
528 case AGP_I855_GCC1_GMS_STOLEN_1M:
fdc3c5be 529 stolen = 1024;
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MD
530 break;
531 case AGP_I855_GCC1_GMS_STOLEN_4M:
fdc3c5be 532 stolen = 4096;
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MD
533 break;
534 case AGP_I855_GCC1_GMS_STOLEN_8M:
fdc3c5be 535 stolen = 8192;
ab5a0ec8
MD
536 break;
537 case AGP_I855_GCC1_GMS_STOLEN_16M:
fdc3c5be 538 stolen = 16384;
ab5a0ec8
MD
539 break;
540 case AGP_I855_GCC1_GMS_STOLEN_32M:
fdc3c5be
HT
541 stolen = 32768;
542 break;
543 case AGP_I915_GCC1_GMS_STOLEN_48M:
544 stolen = 49152;
545 break;
546 case AGP_I915_GCC1_GMS_STOLEN_64M:
547 stolen = 65536;
548 break;
549 case AGP_G33_GCC1_GMS_STOLEN_128M:
550 stolen = 128 * 1024;
551 break;
552 case AGP_G33_GCC1_GMS_STOLEN_256M:
553 stolen = 256 * 1024;
ab5a0ec8
MD
554 break;
555 default:
fdc3c5be
HT
556 device_printf(dev, "unknown memory configuration, "
557 "disabling\n");
558 bus_release_resources(dev, sc->sc_res_spec,
559 sc->sc_res);
560 kfree(gatt, M_AGP);
ab5a0ec8
MD
561 agp_generic_detach(dev);
562 return EINVAL;
563 }
fdc3c5be
HT
564 sc->stolen = (stolen - gtt_size - 4) * 1024 / 4096;
565 if (sc->stolen > 0)
566 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
567 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
984263bc 568
ab5a0ec8 569 /* GATT address is already in there, make sure it's enabled */
fdc3c5be 570 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
ab5a0ec8 571 pgtblctl |= 1;
fdc3c5be 572 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
ab5a0ec8
MD
573
574 gatt->ag_physical = pgtblctl & ~1;
fdc3c5be
HT
575 }
576
bd22570d
SS
577 /* Add a device for the drm to attach to */
578 /* XXX This will go away once we have vgapci */
579 if (!device_add_child(dev, "drmsub", -1))
580 device_printf(dev, "could not add drm subdevice\n");
581
fdc3c5be
HT
582 if (0)
583 agp_i810_dump_regs(dev);
584
984263bc
MD
585 return 0;
586}
587
588static int
589agp_i810_detach(device_t dev)
590{
591 struct agp_i810_softc *sc = device_get_softc(dev);
bd22570d 592 device_t child;
984263bc 593
67e2dc5d 594 agp_free_cdev(dev);
984263bc
MD
595
596 /* Clear the GATT base. */
597 if ( sc->chiptype == CHIP_I810 ) {
fdc3c5be 598 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
984263bc
MD
599 } else {
600 unsigned int pgtblctl;
fdc3c5be 601 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
984263bc 602 pgtblctl &= ~1;
fdc3c5be 603 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
984263bc
MD
604 }
605
606 /* Put the aperture back the way it started. */
607 AGP_SET_APERTURE(dev, sc->initial_aperture);
608
609 if ( sc->chiptype == CHIP_I810 ) {
610 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
611 }
efda3bd0 612 kfree(sc->gatt, M_AGP);
984263bc 613
fdc3c5be 614 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
67e2dc5d 615 agp_free_res(dev);
984263bc 616
bd22570d
SS
617 /* XXX This will go away once we have vgapci */
618 child = device_find_child(dev, "drmsub", 0);
619 if (child != NULL)
620 device_delete_child(dev, child);
621
984263bc
MD
622 return 0;
623}
624
2f1d30c1
HT
625static int
626agp_i810_resume(device_t dev)
627{
628 struct agp_i810_softc *sc;
629 sc = device_get_softc(dev);
630
631 AGP_SET_APERTURE(dev, sc->initial_aperture);
632
633 /* Install the GATT. */
634 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
635 sc->gatt->ag_physical | 1);
636
637 return (bus_generic_resume(dev));
638}
639
fdc3c5be
HT
640/**
641 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
642 * while returning failure on later chipsets when an actual change is
643 * requested.
644 *
645 * This whole function is likely bogus, as the kernel would probably need to
646 * reconfigure the placement of the AGP aperture if a larger size is requested,
647 * which doesn't happen currently.
648 */
984263bc
MD
649static int
650agp_i810_set_aperture(device_t dev, u_int32_t aperture)
651{
652 struct agp_i810_softc *sc = device_get_softc(dev);
fdc3c5be 653 u_int16_t miscc, gcc1;
984263bc 654
fdc3c5be
HT
655 switch (sc->chiptype) {
656 case CHIP_I810:
984263bc
MD
657 /*
658 * Double check for sanity.
659 */
660 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
661 device_printf(dev, "bad aperture size %d\n", aperture);
662 return EINVAL;
663 }
fdc3c5be 664
984263bc
MD
665 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
666 miscc &= ~AGP_I810_MISCC_WINSIZE;
667 if (aperture == 32 * 1024 * 1024)
668 miscc |= AGP_I810_MISCC_WINSIZE_32;
669 else
670 miscc |= AGP_I810_MISCC_WINSIZE_64;
671
672 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
fdc3c5be
HT
673 break;
674 case CHIP_I830:
675 if (aperture != 64 * 1024 * 1024 &&
676 aperture != 128 * 1024 * 1024) {
984263bc
MD
677 device_printf(dev, "bad aperture size %d\n", aperture);
678 return EINVAL;
679 }
680 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
681 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
682 if (aperture == 64 * 1024 * 1024)
683 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
684 else
685 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
686
687 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
fdc3c5be
HT
688 break;
689 case CHIP_I855:
690 case CHIP_I915:
691 case CHIP_I965:
692 case CHIP_G33:
693 return agp_generic_set_aperture(dev, aperture);
984263bc
MD
694 }
695
696 return 0;
697}
698
fdc3c5be
HT
699/**
700 * Writes a GTT entry mapping the page at the given offset from the beginning
701 * of the aperture to the given physical address.
702 */
703static void
704agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
705 int enabled)
706{
707 struct agp_i810_softc *sc = device_get_softc(dev);
708 u_int32_t pte;
709
710 pte = (u_int32_t)physical | 1;
711 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33) {
712 pte |= (physical & 0x0000000f00000000ull) >> 28;
713 } else {
714 /* If we do actually have memory above 4GB on an older system,
715 * crash cleanly rather than scribble on system memory,
716 * so we know we need to fix it.
717 */
718 KASSERT((pte & 0x0000000f00000000ull) == 0,
719 (">4GB physical address in agp"));
720 }
721
722 switch (sc->chiptype) {
723 case CHIP_I810:
724 case CHIP_I830:
725 case CHIP_I855:
726 bus_write_4(sc->sc_res[0],
727 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
728 break;
729 case CHIP_I915:
730 case CHIP_G33:
731 bus_write_4(sc->sc_res[1],
732 (offset >> AGP_PAGE_SHIFT) * 4, pte);
733 break;
734 case CHIP_I965:
735 bus_write_4(sc->sc_res[0],
736 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
737 break;
738 }
739}
740
984263bc
MD
741static int
742agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
743{
744 struct agp_i810_softc *sc = device_get_softc(dev);
745
746 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
747 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
748 return EINVAL;
749 }
750
fdc3c5be 751 if ( sc->chiptype != CHIP_I810 ) {
984263bc
MD
752 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
753 device_printf(dev, "trying to bind into stolen memory");
754 return EINVAL;
755 }
756 }
757
fdc3c5be
HT
758 agp_i810_write_gtt_entry(dev, offset, physical, 1);
759
984263bc
MD
760 return 0;
761}
762
763static int
764agp_i810_unbind_page(device_t dev, int offset)
765{
766 struct agp_i810_softc *sc = device_get_softc(dev);
767
768 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
769 return EINVAL;
770
fdc3c5be 771 if ( sc->chiptype != CHIP_I810 ) {
984263bc
MD
772 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
773 device_printf(dev, "trying to unbind from stolen memory");
774 return EINVAL;
775 }
776 }
777
fdc3c5be
HT
778 agp_i810_write_gtt_entry(dev, offset, 0, 0);
779
984263bc
MD
780 return 0;
781}
782
783/*
784 * Writing via memory mapped registers already flushes all TLBs.
785 */
786static void
787agp_i810_flush_tlb(device_t dev)
788{
789}
790
791static int
792agp_i810_enable(device_t dev, u_int32_t mode)
793{
794
795 return 0;
796}
797
798static struct agp_memory *
799agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
800{
801 struct agp_i810_softc *sc = device_get_softc(dev);
802 struct agp_memory *mem;
803
804 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
805 return 0;
806
807 if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
808 return 0;
809
810 if (type == 1) {
811 /*
812 * Mapping local DRAM into GATT.
813 */
fdc3c5be 814 if ( sc->chiptype != CHIP_I810 )
984263bc
MD
815 return 0;
816 if (size != sc->dcache_size)
817 return 0;
818 } else if (type == 2) {
819 /*
fdc3c5be
HT
820 * Type 2 is the contiguous physical memory type, that hands
821 * back a physical address. This is used for cursors on i810.
822 * Hand back as many single pages with physical as the user
823 * wants, but only allow one larger allocation (ARGB cursor)
824 * for simplicity.
984263bc 825 */
fdc3c5be
HT
826 if (size != AGP_PAGE_SIZE) {
827 if (sc->argb_cursor != NULL)
828 return 0;
829
830 /* Allocate memory for ARGB cursor, if we can. */
831 sc->argb_cursor = contigmalloc(size, M_AGP,
832 0, 0, ~0, PAGE_SIZE, 0);
833 if (sc->argb_cursor == NULL)
834 return 0;
835 }
984263bc
MD
836 }
837
efda3bd0 838 mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
984263bc
MD
839 mem->am_id = sc->agp.as_nextid++;
840 mem->am_size = size;
841 mem->am_type = type;
fdc3c5be 842 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
984263bc
MD
843 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
844 atop(round_page(size)));
845 else
846 mem->am_obj = 0;
847
848 if (type == 2) {
fdc3c5be
HT
849 if (size == AGP_PAGE_SIZE) {
850 /*
851 * Allocate and wire down the page now so that we can
852 * get its physical address.
853 */
854 vm_page_t m;
855
856 m = vm_page_grab(mem->am_obj, 0,
857 VM_ALLOC_NORMAL|VM_ALLOC_ZERO|VM_ALLOC_RETRY);
858 if ((m->flags & PG_ZERO) == 0)
859 vm_page_zero_fill(m);
860 vm_page_wire(m);
861 mem->am_physical = VM_PAGE_TO_PHYS(m);
862 vm_page_wakeup(m);
863 } else {
864 /* Our allocation is already nicely wired down for us.
865 * Just grab the physical address.
866 */
867 mem->am_physical = vtophys(sc->argb_cursor);
868 }
984263bc
MD
869 } else {
870 mem->am_physical = 0;
871 }
872
873 mem->am_offset = 0;
874 mem->am_is_bound = 0;
875 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
876 sc->agp.as_allocated += size;
877
878 return mem;
879}
880
881static int
882agp_i810_free_memory(device_t dev, struct agp_memory *mem)
883{
884 struct agp_i810_softc *sc = device_get_softc(dev);
885
886 if (mem->am_is_bound)
887 return EBUSY;
888
889 if (mem->am_type == 2) {
fdc3c5be
HT
890 if (mem->am_size == AGP_PAGE_SIZE) {
891 /*
892 * Unwire the page which we wired in alloc_memory.
893 */
894 vm_page_t m = vm_page_lookup(mem->am_obj, 0);
895 vm_page_unwire(m, 0);
896 } else {
897 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
898 sc->argb_cursor = NULL;
899 }
984263bc
MD
900 }
901
902 sc->agp.as_allocated -= mem->am_size;
903 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
904 if (mem->am_obj)
905 vm_object_deallocate(mem->am_obj);
efda3bd0 906 kfree(mem, M_AGP);
984263bc
MD
907 return 0;
908}
909
910static int
911agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
912 vm_offset_t offset)
913{
914 struct agp_i810_softc *sc = device_get_softc(dev);
915 vm_offset_t i;
916
fdc3c5be
HT
917 /* Do some sanity checks first. */
918 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
919 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
920 device_printf(dev, "binding memory at bad offset %#x\n",
921 (int)offset);
922 return EINVAL;
923 }
924
925 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
926 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
927 if (mem->am_is_bound) {
928 lockmgr(&sc->agp.as_lock, LK_RELEASE);
929 return EINVAL;
930 }
931 /* The memory's already wired down, just stick it in the GTT. */
932 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
933 agp_i810_write_gtt_entry(dev, offset + i,
934 mem->am_physical + i, 1);
935 }
936 agp_flush_cache();
937 mem->am_offset = offset;
938 mem->am_is_bound = 1;
939 lockmgr(&sc->agp.as_lock, LK_RELEASE);
940 return 0;
941 }
942
984263bc
MD
943 if (mem->am_type != 1)
944 return agp_generic_bind_memory(dev, mem, offset);
945
fdc3c5be 946 if ( sc->chiptype != CHIP_I810 )
984263bc
MD
947 return EINVAL;
948
949 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
fdc3c5be
HT
950 bus_write_4(sc->sc_res[0],
951 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
984263bc
MD
952 }
953
954 return 0;
955}
956
957static int
958agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
959{
960 struct agp_i810_softc *sc = device_get_softc(dev);
961 vm_offset_t i;
962
fdc3c5be
HT
963 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
964 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
965 if (!mem->am_is_bound) {
966 lockmgr(&sc->agp.as_lock, LK_RELEASE);
967 return EINVAL;
968 }
969
970 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
971 agp_i810_write_gtt_entry(dev, mem->am_offset + i,
972 0, 0);
973 }
974 agp_flush_cache();
975 mem->am_is_bound = 0;
976 lockmgr(&sc->agp.as_lock, LK_RELEASE);
977 return 0;
978 }
979
984263bc
MD
980 if (mem->am_type != 1)
981 return agp_generic_unbind_memory(dev, mem);
982
fdc3c5be 983 if ( sc->chiptype != CHIP_I810 )
984263bc
MD
984 return EINVAL;
985
fdc3c5be
HT
986 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
987 bus_write_4(sc->sc_res[0],
988 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
989 }
984263bc
MD
990
991 return 0;
992}
993
994static device_method_t agp_i810_methods[] = {
995 /* Device interface */
fdc3c5be 996 DEVMETHOD(device_identify, agp_i810_identify),
984263bc
MD
997 DEVMETHOD(device_probe, agp_i810_probe),
998 DEVMETHOD(device_attach, agp_i810_attach),
999 DEVMETHOD(device_detach, agp_i810_detach),
2f1d30c1
HT
1000 DEVMETHOD(device_suspend, bus_generic_suspend),
1001 DEVMETHOD(device_resume, agp_i810_resume),
984263bc
MD
1002
1003 /* AGP interface */
fdc3c5be 1004 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
984263bc
MD
1005 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
1006 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1007 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1008 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1009 DEVMETHOD(agp_enable, agp_i810_enable),
1010 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1011 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1012 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1013 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
1014
1015 { 0, 0 }
1016};
1017
1018static driver_t agp_i810_driver = {
1019 "agp",
1020 agp_i810_methods,
1021 sizeof(struct agp_i810_softc),
1022};
1023
1024static devclass_t agp_devclass;
1025
1026DRIVER_MODULE(agp_i810, pci, agp_i810_driver, agp_devclass, 0, 0);
f7841f3c
MD
1027MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1028MODULE_DEPEND(agp_i810, pci, 1, 1, 1);