1) Add support for NIC found in Sony FS570 laptops
[dragonfly.git] / sys / dev / netif / fxp / if_fxp.c
CommitLineData
984263bc
MD
1/*-
2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
654dbb2a 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.40 2005/12/17 09:09:21 sephe Exp $
984263bc
MD
30 */
31
32/*
33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
34 */
35
2b71c8f1
SZ
36#include "opt_polling.h"
37
984263bc
MD
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/mbuf.h>
41#include <sys/malloc.h>
984263bc
MD
42#include <sys/kernel.h>
43#include <sys/socket.h>
44#include <sys/sysctl.h>
37103068 45#include <sys/thread2.h>
984263bc
MD
46
47#include <net/if.h>
cb96d2fc 48#include <net/ifq_var.h>
984263bc
MD
49#include <net/if_dl.h>
50#include <net/if_media.h>
51
52#ifdef NS
53#include <netns/ns.h>
54#include <netns/ns_if.h>
55#endif
56
57#include <net/bpf.h>
58#include <sys/sockio.h>
59#include <sys/bus.h>
60#include <machine/bus.h>
61#include <sys/rman.h>
62#include <machine/resource.h>
63
64#include <net/ethernet.h>
65#include <net/if_arp.h>
66
67#include <vm/vm.h> /* for vtophys */
68#include <vm/pmap.h> /* for vtophys */
984263bc
MD
69
70#include <net/if_types.h>
1f2de5d4 71#include <net/vlan/if_vlan_var.h>
984263bc 72
1f2de5d4
MD
73#include <bus/pci/pcivar.h>
74#include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
984263bc 75
1f2de5d4
MD
76#include "../mii_layer/mii.h"
77#include "../mii_layer/miivar.h"
984263bc 78
1f2de5d4
MD
79#include "if_fxpreg.h"
80#include "if_fxpvar.h"
81#include "rcvbundl.h"
984263bc 82
984263bc
MD
83#include "miibus_if.h"
84
85/*
86 * NOTE! On the Alpha, we have an alignment constraint. The
87 * card DMAs the packet immediately following the RFA. However,
88 * the first thing in the packet is a 14-byte Ethernet header.
89 * This means that the packet is misaligned. To compensate,
90 * we actually offset the RFA 2 bytes into the cluster. This
91 * alignes the packet after the Ethernet header at a 32-bit
92 * boundary. HOWEVER! This means that the RFA is misaligned!
93 */
94#define RFA_ALIGNMENT_FUDGE 2
95
96/*
97 * Set initial transmit threshold at 64 (512 bytes). This is
98 * increased by 64 (512 bytes) at a time, to maximum of 192
99 * (1536 bytes), if an underrun occurs.
100 */
101static int tx_threshold = 64;
102
103/*
104 * The configuration byte map has several undefined fields which
105 * must be one or must be zero. Set up a template for these bits
106 * only, (assuming a 82557 chip) leaving the actual configuration
107 * to fxp_init.
108 *
109 * See struct fxp_cb_config for the bit definitions.
110 */
111static u_char fxp_cb_config_template[] = {
112 0x0, 0x0, /* cb_status */
113 0x0, 0x0, /* cb_command */
114 0x0, 0x0, 0x0, 0x0, /* link_addr */
115 0x0, /* 0 */
116 0x0, /* 1 */
117 0x0, /* 2 */
118 0x0, /* 3 */
119 0x0, /* 4 */
120 0x0, /* 5 */
121 0x32, /* 6 */
122 0x0, /* 7 */
123 0x0, /* 8 */
124 0x0, /* 9 */
125 0x6, /* 10 */
126 0x0, /* 11 */
127 0x0, /* 12 */
128 0x0, /* 13 */
129 0xf2, /* 14 */
130 0x48, /* 15 */
131 0x0, /* 16 */
132 0x40, /* 17 */
133 0xf0, /* 18 */
134 0x0, /* 19 */
135 0x3f, /* 20 */
136 0x5 /* 21 */
137};
138
139struct fxp_ident {
140 u_int16_t devid;
77bf5450 141 int16_t revid; /* -1 matches anything */
984263bc
MD
142 char *name;
143};
144
145/*
146 * Claim various Intel PCI device identifiers for this driver. The
147 * sub-vendor and sub-device field are extensively used to identify
148 * particular variants, but we don't currently differentiate between
149 * them.
150 */
151static struct fxp_ident fxp_ident_table[] = {
77bf5450
HP
152 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
153 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
154 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
155 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
156 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
157 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
158 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
159 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
160 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
161 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
162 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
163 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
164 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
165 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
166 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
167 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
168 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
f3f9ebbd 169 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
77bf5450 170 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
654dbb2a
SZ
171 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" },
172 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
173 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
77bf5450
HP
174 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
175 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
176 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
177 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
178 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
179 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
180 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
181 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
182 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
183 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
184 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
185 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
186 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
187 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
188 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
189 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
190 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
191 { 0, -1, NULL },
984263bc
MD
192};
193
194static int fxp_probe(device_t dev);
195static int fxp_attach(device_t dev);
196static int fxp_detach(device_t dev);
197static int fxp_shutdown(device_t dev);
198static int fxp_suspend(device_t dev);
199static int fxp_resume(device_t dev);
200
201static void fxp_intr(void *xsc);
202static void fxp_intr_body(struct fxp_softc *sc,
203 u_int8_t statack, int count);
204
205static void fxp_init(void *xsc);
206static void fxp_tick(void *xsc);
207static void fxp_powerstate_d0(device_t dev);
208static void fxp_start(struct ifnet *ifp);
209static void fxp_stop(struct fxp_softc *sc);
c81df1a6 210static void fxp_release(device_t dev);
984263bc 211static int fxp_ioctl(struct ifnet *ifp, u_long command,
bd4539cc 212 caddr_t data, struct ucred *);
984263bc
MD
213static void fxp_watchdog(struct ifnet *ifp);
214static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
215static int fxp_mc_addrs(struct fxp_softc *sc);
216static void fxp_mc_setup(struct fxp_softc *sc);
217static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
218 int autosize);
219static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
220 u_int16_t data);
221static void fxp_autosize_eeprom(struct fxp_softc *sc);
222static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
223 int offset, int words);
224static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
225 int offset, int words);
226static int fxp_ifmedia_upd(struct ifnet *ifp);
227static void fxp_ifmedia_sts(struct ifnet *ifp,
228 struct ifmediareq *ifmr);
229static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
230static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
231 struct ifmediareq *ifmr);
232static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
233static void fxp_miibus_writereg(device_t dev, int phy, int reg,
234 int value);
235static void fxp_load_ucode(struct fxp_softc *sc);
236static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
237 int low, int high);
238static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
239static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
9c095379
MD
240#ifdef DEVICE_POLLING
241static poll_handler_t fxp_poll;
242#endif
243
de1795b2 244static void fxp_lwcopy(volatile u_int32_t *src,
984263bc 245 volatile u_int32_t *dst);
de1795b2
JS
246static void fxp_scb_wait(struct fxp_softc *sc);
247static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
248static void fxp_dma_wait(volatile u_int16_t *status,
984263bc
MD
249 struct fxp_softc *sc);
250
251static device_method_t fxp_methods[] = {
252 /* Device interface */
253 DEVMETHOD(device_probe, fxp_probe),
254 DEVMETHOD(device_attach, fxp_attach),
255 DEVMETHOD(device_detach, fxp_detach),
256 DEVMETHOD(device_shutdown, fxp_shutdown),
257 DEVMETHOD(device_suspend, fxp_suspend),
258 DEVMETHOD(device_resume, fxp_resume),
259
260 /* MII interface */
261 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
262 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
263
264 { 0, 0 }
265};
266
267static driver_t fxp_driver = {
268 "fxp",
269 fxp_methods,
270 sizeof(struct fxp_softc),
271};
272
273static devclass_t fxp_devclass;
274
32832096
MD
275DECLARE_DUMMY_MODULE(if_fxp);
276MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
984263bc
MD
277DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
278DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
279DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
280
281static int fxp_rnr;
282SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
283
284/*
de1795b2 285 * Copy a 16-bit aligned 32-bit quantity.
984263bc 286 */
de1795b2 287static void
984263bc
MD
288fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
289{
290#ifdef __i386__
291 *dst = *src;
292#else
293 volatile u_int16_t *a = (volatile u_int16_t *)src;
294 volatile u_int16_t *b = (volatile u_int16_t *)dst;
295
296 b[0] = a[0];
297 b[1] = a[1];
298#endif
299}
300
301/*
302 * Wait for the previous command to be accepted (but not necessarily
303 * completed).
304 */
de1795b2 305static void
984263bc
MD
306fxp_scb_wait(struct fxp_softc *sc)
307{
308 int i = 10000;
309
310 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
311 DELAY(2);
c81df1a6
JS
312 if (i == 0) {
313 if_printf(&sc->arpcom.ac_if,
314 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
984263bc
MD
315 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
316 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
317 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
318 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
c81df1a6 319 }
984263bc
MD
320}
321
de1795b2 322static void
984263bc
MD
323fxp_scb_cmd(struct fxp_softc *sc, int cmd)
324{
325
326 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
327 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
328 fxp_scb_wait(sc);
329 }
330 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
331}
332
de1795b2 333static void
984263bc
MD
334fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
335{
336 int i = 10000;
337
338 while (!(*status & FXP_CB_STATUS_C) && --i)
339 DELAY(2);
340 if (i == 0)
c81df1a6 341 if_printf(&sc->arpcom.ac_if, "DMA timeout\n");
984263bc
MD
342}
343
344/*
345 * Return identification string if this is device is ours.
346 */
347static int
348fxp_probe(device_t dev)
349{
350 u_int16_t devid;
77bf5450 351 u_int8_t revid;
984263bc
MD
352 struct fxp_ident *ident;
353
354 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
355 devid = pci_get_device(dev);
77bf5450 356 revid = pci_get_revid(dev);
984263bc 357 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
77bf5450
HP
358 if (ident->devid == devid &&
359 (ident->revid == revid || ident->revid == -1)) {
984263bc
MD
360 device_set_desc(dev, ident->name);
361 return (0);
362 }
363 }
364 }
365 return (ENXIO);
366}
367
368static void
369fxp_powerstate_d0(device_t dev)
370{
984263bc
MD
371 u_int32_t iobase, membase, irq;
372
373 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
374 /* Save important PCI config data. */
375 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
376 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
377 irq = pci_read_config(dev, PCIR_INTLINE, 4);
378
379 /* Reset the power state. */
380 device_printf(dev, "chip is in D%d power mode "
381 "-- setting to D0\n", pci_get_powerstate(dev));
382
383 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
384
385 /* Restore PCI config data. */
386 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
387 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
388 pci_write_config(dev, PCIR_INTLINE, irq, 4);
389 }
984263bc
MD
390}
391
392static int
393fxp_attach(device_t dev)
394{
395 int error = 0;
396 struct fxp_softc *sc = device_get_softc(dev);
397 struct ifnet *ifp;
398 u_int32_t val;
399 u_int16_t data;
400 int i, rid, m1, m2, prefer_iomap;
984263bc 401
a1f4b801 402 callout_init(&sc->fxp_stat_timer);
984263bc 403 sysctl_ctx_init(&sc->sysctl_ctx);
984263bc 404
984263bc
MD
405 /*
406 * Enable bus mastering. Enable memory space too, in case
407 * BIOS/Prom forgot about it.
408 */
af340cf5
JS
409 pci_enable_busmaster(dev);
410 pci_enable_io(dev, SYS_RES_MEMORY);
984263bc
MD
411 val = pci_read_config(dev, PCIR_COMMAND, 2);
412
413 fxp_powerstate_d0(dev);
414
415 /*
416 * Figure out which we should try first - memory mapping or i/o mapping?
417 * We default to memory mapping. Then we accept an override from the
418 * command line. Then we check to see which one is enabled.
419 */
420 m1 = PCIM_CMD_MEMEN;
421 m2 = PCIM_CMD_PORTEN;
422 prefer_iomap = 0;
423 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
424 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
425 m1 = PCIM_CMD_PORTEN;
426 m2 = PCIM_CMD_MEMEN;
427 }
428
429 if (val & m1) {
430 sc->rtp =
431 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
432 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
4e6d744d
JS
433 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
434 RF_ACTIVE);
984263bc
MD
435 }
436 if (sc->mem == NULL && (val & m2)) {
437 sc->rtp =
438 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
439 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
4e6d744d
JS
440 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
441 RF_ACTIVE);
984263bc
MD
442 }
443
444 if (!sc->mem) {
445 device_printf(dev, "could not map device registers\n");
446 error = ENXIO;
447 goto fail;
448 }
449 if (bootverbose) {
450 device_printf(dev, "using %s space register mapping\n",
451 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
452 }
453
454 sc->sc_st = rman_get_bustag(sc->mem);
455 sc->sc_sh = rman_get_bushandle(sc->mem);
456
457 /*
458 * Allocate our interrupt.
459 */
460 rid = 0;
4e6d744d
JS
461 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
462 RF_SHAREABLE | RF_ACTIVE);
984263bc
MD
463 if (sc->irq == NULL) {
464 device_printf(dev, "could not map interrupt\n");
465 error = ENXIO;
466 goto fail;
467 }
468
984263bc
MD
469 /*
470 * Reset to a stable state.
471 */
472 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
473 DELAY(10);
474
475 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
c5541aee 476 M_DEVBUF, M_WAITOK | M_ZERO);
984263bc
MD
477
478 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
c5541aee 479 M_WAITOK | M_ZERO);
984263bc 480
c5541aee 481 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK);
984263bc
MD
482
483 /*
484 * Pre-allocate our receive buffers.
485 */
486 for (i = 0; i < FXP_NRFABUFS; i++) {
487 if (fxp_add_rfabuf(sc, NULL) != 0) {
488 goto failmem;
489 }
490 }
491
492 /*
493 * Find out how large of an SEEPROM we have.
494 */
495 fxp_autosize_eeprom(sc);
496
497 /*
498 * Determine whether we must use the 503 serial interface.
499 */
500 fxp_read_eeprom(sc, &data, 6, 1);
501 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
502 (data & FXP_PHY_SERIAL_ONLY))
503 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
504
505 /*
506 * Create the sysctl tree
507 */
508 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
509 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
510 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
511 if (sc->sysctl_tree == NULL)
512 goto fail;
513 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
514 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
515 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
516 "FXP driver receive interrupt microcode bundling delay");
517 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
518 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
519 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
520 "FXP driver receive interrupt microcode bundle size limit");
521
522 /*
523 * Pull in device tunables.
524 */
525 sc->tunable_int_delay = TUNABLE_INT_DELAY;
526 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
527 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
528 "int_delay", &sc->tunable_int_delay);
529 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
530 "bundle_max", &sc->tunable_bundle_max);
531
532 /*
533 * Find out the chip revision; lump all 82557 revs together.
534 */
535 fxp_read_eeprom(sc, &data, 5, 1);
536 if ((data >> 8) == 1)
537 sc->revision = FXP_REV_82557;
538 else
539 sc->revision = pci_get_revid(dev);
540
541 /*
542 * Enable workarounds for certain chip revision deficiencies.
543 *
544 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
545 * some systems based a normal 82559 design, have a defect where
546 * the chip can cause a PCI protocol violation if it receives
547 * a CU_RESUME command when it is entering the IDLE state. The
548 * workaround is to disable Dynamic Standby Mode, so the chip never
549 * deasserts CLKRUN#, and always remains in an active state.
550 *
551 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
552 */
553 i = pci_get_device(dev);
554 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
555 sc->revision >= FXP_REV_82559_A0) {
556 fxp_read_eeprom(sc, &data, 10, 1);
557 if (data & 0x02) { /* STB enable */
558 u_int16_t cksum;
559 int i;
560
561 device_printf(dev,
562 "Disabling dynamic standby mode in EEPROM\n");
563 data &= ~0x02;
564 fxp_write_eeprom(sc, &data, 10, 1);
565 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
566 cksum = 0;
567 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
568 fxp_read_eeprom(sc, &data, i, 1);
569 cksum += data;
570 }
571 i = (1 << sc->eeprom_size) - 1;
572 cksum = 0xBABA - cksum;
573 fxp_read_eeprom(sc, &data, i, 1);
574 fxp_write_eeprom(sc, &cksum, i, 1);
575 device_printf(dev,
576 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
577 i, data, cksum);
578#if 1
579 /*
580 * If the user elects to continue, try the software
581 * workaround, as it is better than nothing.
582 */
583 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
584#endif
585 }
586 }
587
588 /*
589 * If we are not a 82557 chip, we can enable extended features.
590 */
591 if (sc->revision != FXP_REV_82557) {
592 /*
593 * If MWI is enabled in the PCI configuration, and there
594 * is a valid cacheline size (8 or 16 dwords), then tell
595 * the board to turn on MWI.
596 */
597 if (val & PCIM_CMD_MWRICEN &&
598 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
599 sc->flags |= FXP_FLAG_MWI_ENABLE;
600
601 /* turn on the extended TxCB feature */
602 sc->flags |= FXP_FLAG_EXT_TXCB;
603
604 /* enable reception of long frames for VLAN */
605 sc->flags |= FXP_FLAG_LONG_PKT_EN;
606 }
607
608 /*
609 * Read MAC address.
610 */
611 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
267caeeb 612 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
c81df1a6 613 device_printf(dev, "10Mbps\n");
984263bc
MD
614 if (bootverbose) {
615 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
616 pci_get_vendor(dev), pci_get_device(dev),
617 pci_get_subvendor(dev), pci_get_subdevice(dev),
618 pci_get_revid(dev));
619 fxp_read_eeprom(sc, &data, 10, 1);
620 device_printf(dev, "Dynamic Standby mode is %s\n",
621 data & 0x02 ? "enabled" : "disabled");
622 }
623
624 /*
625 * If this is only a 10Mbps device, then there is no MII, and
626 * the PHY will use a serial interface instead.
627 *
628 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
629 * doesn't have a programming interface of any sort. The
630 * media is sensed automatically based on how the link partner
631 * is configured. This is, in essence, manual configuration.
632 */
633 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
634 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
635 fxp_serial_ifmedia_sts);
636 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
637 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
638 } else {
639 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
640 fxp_ifmedia_sts)) {
641 device_printf(dev, "MII without any PHY!\n");
642 error = ENXIO;
643 goto fail;
644 }
645 }
646
647 ifp = &sc->arpcom.ac_if;
af340cf5 648 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
649 ifp->if_baudrate = 100000000;
650 ifp->if_init = fxp_init;
651 ifp->if_softc = sc;
652 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
653 ifp->if_ioctl = fxp_ioctl;
654 ifp->if_start = fxp_start;
9c095379
MD
655#ifdef DEVICE_POLLING
656 ifp->if_poll = fxp_poll;
657#endif
984263bc
MD
658 ifp->if_watchdog = fxp_watchdog;
659
660 /*
661 * Attach the interface.
662 */
78195a76 663 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
984263bc
MD
664
665 /*
666 * Tell the upper layer(s) we support long frames.
667 */
668 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
669
670 /*
671 * Let the system queue as many packets as we have available
672 * TX descriptors.
673 */
cb96d2fc 674 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1);
4dbb2aca 675 ifq_set_ready(&ifp->if_snd);
984263bc 676
78195a76
MD
677 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE,
678 fxp_intr, sc, &sc->ih,
679 ifp->if_serializer);
37103068 680 if (error) {
a3e0c8f8 681 ether_ifdetach(ifp);
37103068
JS
682 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
683 ifmedia_removeall(&sc->sc_media);
684 device_printf(dev, "could not setup irq\n");
685 goto fail;
686 }
687
984263bc
MD
688 return (0);
689
690failmem:
691 device_printf(dev, "Failed to malloc memory\n");
692 error = ENOMEM;
693fail:
c81df1a6 694 fxp_release(dev);
984263bc
MD
695 return (error);
696}
697
698/*
699 * release all resources
700 */
701static void
c81df1a6 702fxp_release(device_t dev)
984263bc 703{
37103068 704 struct fxp_softc *sc = device_get_softc(dev);
984263bc 705
984263bc 706 if (sc->miibus)
c81df1a6 707 device_delete_child(dev, sc->miibus);
37103068 708 bus_generic_detach(dev);
984263bc
MD
709
710 if (sc->cbl_base)
711 free(sc->cbl_base, M_DEVBUF);
712 if (sc->fxp_stats)
713 free(sc->fxp_stats, M_DEVBUF);
714 if (sc->mcsp)
715 free(sc->mcsp, M_DEVBUF);
716 if (sc->rfa_headm)
717 m_freem(sc->rfa_headm);
718
984263bc 719 if (sc->irq)
c81df1a6 720 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
984263bc 721 if (sc->mem)
c81df1a6 722 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
984263bc
MD
723
724 sysctl_ctx_free(&sc->sysctl_ctx);
984263bc
MD
725}
726
727/*
728 * Detach interface.
729 */
730static int
731fxp_detach(device_t dev)
732{
733 struct fxp_softc *sc = device_get_softc(dev);
984263bc
MD
734
735 /* disable interrupts */
736 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
737
78195a76 738 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
984263bc
MD
739
740 /*
741 * Stop DMA and drop transmit queue.
742 */
743 fxp_stop(sc);
744
745 /*
746 * Close down routes etc.
747 */
0a8b5977 748 ether_ifdetach(&sc->arpcom.ac_if);
984263bc
MD
749
750 /*
751 * Free all media structures.
752 */
37103068
JS
753 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
754 ifmedia_removeall(&sc->sc_media);
984263bc 755
37103068
JS
756 if (sc->ih)
757 bus_teardown_intr(dev, sc->irq, sc->ih);
758
984263bc 759 /* Release our allocated resources. */
c81df1a6 760 fxp_release(dev);
78195a76 761 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
762
763 return (0);
764}
765
766/*
767 * Device shutdown routine. Called at system shutdown after sync. The
768 * main purpose of this routine is to shut off receiver DMA so that
769 * kernel memory doesn't get clobbered during warmboot.
770 */
771static int
772fxp_shutdown(device_t dev)
773{
774 /*
775 * Make sure that DMA is disabled prior to reboot. Not doing
776 * do could allow DMA to corrupt kernel memory during the
777 * reboot before the driver initializes.
778 */
779 fxp_stop((struct fxp_softc *) device_get_softc(dev));
780 return (0);
781}
782
783/*
784 * Device suspend routine. Stop the interface and save some PCI
785 * settings in case the BIOS doesn't restore them properly on
786 * resume.
787 */
788static int
789fxp_suspend(device_t dev)
790{
791 struct fxp_softc *sc = device_get_softc(dev);
37103068 792 int i;
984263bc 793
78195a76 794 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
984263bc
MD
795
796 fxp_stop(sc);
797
798 for (i = 0; i < 5; i++)
3dc849fa 799 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
984263bc
MD
800 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
801 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
802 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
803 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
804
805 sc->suspended = 1;
806
78195a76 807 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
808 return (0);
809}
810
811/*
812 * Device resume routine. Restore some PCI settings in case the BIOS
813 * doesn't, re-enable busmastering, and restart the interface if
814 * appropriate.
815 */
816static int
817fxp_resume(device_t dev)
818{
819 struct fxp_softc *sc = device_get_softc(dev);
3dc849fa 820 struct ifnet *ifp = &sc->arpcom.ac_if;
37103068 821 int i;
984263bc 822
78195a76 823 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
984263bc
MD
824
825 fxp_powerstate_d0(dev);
826
827 /* better way to do this? */
828 for (i = 0; i < 5; i++)
3dc849fa 829 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
984263bc
MD
830 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
831 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
832 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
833 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
834
af340cf5
JS
835 /* reenable busmastering and memory space */
836 pci_enable_busmaster(dev);
837 pci_enable_io(dev, SYS_RES_MEMORY);
984263bc
MD
838
839 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
840 DELAY(10);
841
842 /* reinitialize interface if necessary */
843 if (ifp->if_flags & IFF_UP)
844 fxp_init(sc);
845
846 sc->suspended = 0;
847
78195a76 848 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
849 return (0);
850}
851
852static void
853fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
854{
855 u_int16_t reg;
856 int x;
857
858 /*
859 * Shift in data.
860 */
861 for (x = 1 << (length - 1); x; x >>= 1) {
862 if (data & x)
863 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
864 else
865 reg = FXP_EEPROM_EECS;
866 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
867 DELAY(1);
868 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
869 DELAY(1);
870 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
871 DELAY(1);
872 }
873}
874
875/*
876 * Read from the serial EEPROM. Basically, you manually shift in
877 * the read opcode (one bit at a time) and then shift in the address,
878 * and then you shift out the data (all of this one bit at a time).
879 * The word size is 16 bits, so you have to provide the address for
880 * every 16 bits of data.
881 */
882static u_int16_t
883fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
884{
885 u_int16_t reg, data;
886 int x;
887
888 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
889 /*
890 * Shift in read opcode.
891 */
892 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
893 /*
894 * Shift in address.
895 */
896 data = 0;
897 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
898 if (offset & x)
899 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
900 else
901 reg = FXP_EEPROM_EECS;
902 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
903 DELAY(1);
904 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
905 DELAY(1);
906 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
907 DELAY(1);
908 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
909 data++;
910 if (autosize && reg == 0) {
911 sc->eeprom_size = data;
912 break;
913 }
914 }
915 /*
916 * Shift out data.
917 */
918 data = 0;
919 reg = FXP_EEPROM_EECS;
920 for (x = 1 << 15; x; x >>= 1) {
921 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
922 DELAY(1);
923 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
924 data |= x;
925 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
926 DELAY(1);
927 }
928 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
929 DELAY(1);
930
931 return (data);
932}
933
934static void
935fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
936{
937 int i;
938
939 /*
940 * Erase/write enable.
941 */
942 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
943 fxp_eeprom_shiftin(sc, 0x4, 3);
944 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
945 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
946 DELAY(1);
947 /*
948 * Shift in write opcode, address, data.
949 */
950 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
951 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
952 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
953 fxp_eeprom_shiftin(sc, data, 16);
954 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
955 DELAY(1);
956 /*
957 * Wait for EEPROM to finish up.
958 */
959 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
960 DELAY(1);
961 for (i = 0; i < 1000; i++) {
962 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
963 break;
964 DELAY(50);
965 }
966 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
967 DELAY(1);
968 /*
969 * Erase/write disable.
970 */
971 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
972 fxp_eeprom_shiftin(sc, 0x4, 3);
973 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
974 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
975 DELAY(1);
976}
977
978/*
979 * From NetBSD:
980 *
981 * Figure out EEPROM size.
982 *
983 * 559's can have either 64-word or 256-word EEPROMs, the 558
984 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
985 * talks about the existance of 16 to 256 word EEPROMs.
986 *
987 * The only known sizes are 64 and 256, where the 256 version is used
988 * by CardBus cards to store CIS information.
989 *
990 * The address is shifted in msb-to-lsb, and after the last
991 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
992 * after which follows the actual data. We try to detect this zero, by
993 * probing the data-out bit in the EEPROM control register just after
994 * having shifted in a bit. If the bit is zero, we assume we've
995 * shifted enough address bits. The data-out should be tri-state,
996 * before this, which should translate to a logical one.
997 */
998static void
999fxp_autosize_eeprom(struct fxp_softc *sc)
1000{
1001
1002 /* guess maximum size of 256 words */
1003 sc->eeprom_size = 8;
1004
1005 /* autosize */
1006 (void) fxp_eeprom_getword(sc, 0, 1);
1007}
1008
1009static void
1010fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1011{
1012 int i;
1013
1014 for (i = 0; i < words; i++)
1015 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1016}
1017
1018static void
1019fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1020{
1021 int i;
1022
1023 for (i = 0; i < words; i++)
1024 fxp_eeprom_putword(sc, offset + i, data[i]);
1025}
1026
1027/*
1028 * Start packet transmission on the interface.
1029 */
1030static void
1031fxp_start(struct ifnet *ifp)
1032{
1033 struct fxp_softc *sc = ifp->if_softc;
1034 struct fxp_cb_tx *txp;
1035
1036 /*
1037 * See if we need to suspend xmit until the multicast filter
1038 * has been reprogrammed (which can only be done at the head
1039 * of the command chain).
1040 */
1041 if (sc->need_mcsetup) {
1042 return;
1043 }
1044
1045 txp = NULL;
1046
1047 /*
1048 * We're finished if there is nothing more to add to the list or if
1049 * we're all filled up with buffers to transmit.
1050 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1051 * a NOP command when needed.
1052 */
cb96d2fc 1053 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) {
984263bc 1054 struct mbuf *m, *mb_head;
50503f0f 1055 int segment, ntries = 0;
984263bc
MD
1056
1057 /*
cb96d2fc
JS
1058 * Grab a packet to transmit. The packet is dequeued,
1059 * once we are sure that we have enough free descriptors.
984263bc 1060 */
cb96d2fc
JS
1061 mb_head = ifq_poll(&ifp->if_snd);
1062 if (mb_head == NULL)
1063 break;
984263bc
MD
1064
1065 /*
1066 * Get pointer to next available tx desc.
1067 */
1068 txp = sc->cbl_last->next;
1069
1070 /*
1071 * Go through each of the mbufs in the chain and initialize
1072 * the transmit buffer descriptors with the physical address
1073 * and size of the mbuf.
1074 */
1075tbdinit:
1076 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1077 if (m->m_len != 0) {
1078 if (segment == FXP_NTXSEG)
1079 break;
1080 txp->tbd[segment].tb_addr =
1081 vtophys(mtod(m, vm_offset_t));
1082 txp->tbd[segment].tb_size = m->m_len;
1083 segment++;
1084 }
1085 }
1086 if (m != NULL) {
1087 struct mbuf *mn;
1088
1089 /*
1090 * We ran out of segments. We have to recopy this
1091 * mbuf chain first. Bail out if we can't get the
1092 * new buffers.
1093 */
50503f0f
JH
1094 if (ntries > 0)
1095 break;
1096 mn = m_dup(mb_head, MB_DONTWAIT);
cb96d2fc 1097 if (mn == NULL)
984263bc 1098 break;
cb96d2fc 1099 /* We can transmit the packet, dequeue it. */
d2c71fa0 1100 ifq_dequeue(&ifp->if_snd, mb_head);
984263bc
MD
1101 m_freem(mb_head);
1102 mb_head = mn;
50503f0f 1103 ntries = 1;
984263bc 1104 goto tbdinit;
cb96d2fc
JS
1105 } else {
1106 /* Nothing to worry about, just dequeue. */
d2c71fa0 1107 ifq_dequeue(&ifp->if_snd, mb_head);
984263bc
MD
1108 }
1109
1110 txp->tbd_number = segment;
1111 txp->mb_head = mb_head;
1112 txp->cb_status = 0;
1113 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1114 txp->cb_command =
1115 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1116 FXP_CB_COMMAND_S;
1117 } else {
1118 txp->cb_command =
1119 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1120 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1121 /*
1122 * Set a 5 second timer just in case we don't hear
1123 * from the card again.
1124 */
1125 ifp->if_timer = 5;
1126 }
1127 txp->tx_threshold = tx_threshold;
1128
1129 /*
1130 * Advance the end of list forward.
1131 */
1132
984263bc 1133 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
984263bc
MD
1134 sc->cbl_last = txp;
1135
1136 /*
1137 * Advance the beginning of the list forward if there are
1138 * no other packets queued (when nothing is queued, cbl_first
1139 * sits on the last TxCB that was sent out).
1140 */
1141 if (sc->tx_queued == 0)
1142 sc->cbl_first = txp;
1143
1144 sc->tx_queued++;
1145
7600679e 1146 BPF_MTAP(ifp, mb_head);
984263bc
MD
1147 }
1148
1149 /*
1150 * We're finished. If we added to the list, issue a RESUME to get DMA
1151 * going again if suspended.
1152 */
1153 if (txp != NULL) {
1154 fxp_scb_wait(sc);
1155 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1156 }
1157}
1158
1159#ifdef DEVICE_POLLING
984263bc
MD
1160
1161static void
1162fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1163{
1164 struct fxp_softc *sc = ifp->if_softc;
1165 u_int8_t statack;
1166
9c095379
MD
1167 switch(cmd) {
1168 case POLL_REGISTER:
1169 /* disable interrupts */
1170 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1171 break;
1172 case POLL_DEREGISTER:
1173 /* enable interrupts */
984263bc 1174 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
9c095379
MD
1175 break;
1176 default:
1177 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1178 FXP_SCB_STATACK_FR;
1179 if (cmd == POLL_AND_CHECK_STATUS) {
1180 u_int8_t tmp;
1181
1182 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1183 if (tmp == 0xff || tmp == 0)
1184 return; /* nothing to do */
1185 tmp &= ~statack;
1186 /* ack what we can */
1187 if (tmp != 0)
1188 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1189 statack |= tmp;
1190 }
1191 fxp_intr_body(sc, statack, count);
1192 break;
984263bc 1193 }
984263bc 1194}
9c095379 1195
984263bc
MD
1196#endif /* DEVICE_POLLING */
1197
1198/*
1199 * Process interface interrupts.
1200 */
1201static void
1202fxp_intr(void *xsc)
1203{
1204 struct fxp_softc *sc = xsc;
1205 u_int8_t statack;
1206
984263bc
MD
1207 if (sc->suspended) {
1208 return;
1209 }
1210
1211 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1212 /*
1213 * It should not be possible to have all bits set; the
1214 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1215 * all bits are set, this may indicate that the card has
1216 * been physically ejected, so ignore it.
1217 */
1218 if (statack == 0xff)
1219 return;
1220
1221 /*
1222 * First ACK all the interrupts in this pass.
1223 */
1224 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1225 fxp_intr_body(sc, statack, -1);
1226 }
1227}
1228
1229static void
1230fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1231{
3dc849fa 1232 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
1233 struct mbuf *m;
1234 struct fxp_rfa *rfa;
1235 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1236
1237 if (rnr)
1238 fxp_rnr++;
1239#ifdef DEVICE_POLLING
1240 /* Pick up a deferred RNR condition if `count' ran out last time. */
1241 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1242 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1243 rnr = 1;
1244 }
1245#endif
1246
1247 /*
1248 * Free any finished transmit mbuf chains.
1249 *
1250 * Handle the CNA event likt a CXTNO event. It used to
1251 * be that this event (control unit not ready) was not
1252 * encountered, but it is now with the SMPng modifications.
1253 * The exact sequence of events that occur when the interface
1254 * is brought up are different now, and if this event
1255 * goes unhandled, the configuration/rxfilter setup sequence
1256 * can stall for several seconds. The result is that no
1257 * packets go out onto the wire for about 5 to 10 seconds
1258 * after the interface is ifconfig'ed for the first time.
1259 */
1260 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1261 struct fxp_cb_tx *txp;
1262
1263 for (txp = sc->cbl_first; sc->tx_queued &&
1264 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1265 txp = txp->next) {
acaaa437 1266 if ((m = txp->mb_head) != NULL) {
984263bc 1267 txp->mb_head = NULL;
acaaa437
MD
1268 sc->tx_queued--;
1269 m_freem(m);
1270 } else {
1271 sc->tx_queued--;
984263bc 1272 }
984263bc
MD
1273 }
1274 sc->cbl_first = txp;
1275 ifp->if_timer = 0;
1276 if (sc->tx_queued == 0) {
1277 if (sc->need_mcsetup)
1278 fxp_mc_setup(sc);
1279 }
1280 /*
1281 * Try to start more packets transmitting.
1282 */
cb96d2fc
JS
1283 if (!ifq_is_empty(&ifp->if_snd))
1284 (*ifp->if_start)(ifp);
984263bc
MD
1285 }
1286
1287 /*
1288 * Just return if nothing happened on the receive side.
1289 */
1290 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1291 return;
1292
1293 /*
1294 * Process receiver interrupts. If a no-resource (RNR)
1295 * condition exists, get whatever packets we can and
1296 * re-start the receiver.
1297 *
1298 * When using polling, we do not process the list to completion,
1299 * so when we get an RNR interrupt we must defer the restart
1300 * until we hit the last buffer with the C bit set.
1301 * If we run out of cycles and rfa_headm has the C bit set,
1302 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1303 * that the info will be used in the subsequent polling cycle.
1304 */
1305 for (;;) {
1306 m = sc->rfa_headm;
1307 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1308 RFA_ALIGNMENT_FUDGE);
1309
1310#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1311 if (count >= 0 && count-- == 0) {
1312 if (rnr) {
1313 /* Defer RNR processing until the next time. */
1314 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1315 rnr = 0;
1316 }
1317 break;
1318 }
1319#endif /* DEVICE_POLLING */
1320
1321 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1322 break;
1323
1324 /*
1325 * Remove first packet from the chain.
1326 */
1327 sc->rfa_headm = m->m_next;
1328 m->m_next = NULL;
1329
1330 /*
1331 * Add a new buffer to the receive chain.
1332 * If this fails, the old buffer is recycled
1333 * instead.
1334 */
1335 if (fxp_add_rfabuf(sc, m) == 0) {
1336 int total_len;
1337
1338 /*
1339 * Fetch packet length (the top 2 bits of
1340 * actual_size are flags set by the controller
1341 * upon completion), and drop the packet in case
1342 * of bogus length or CRC errors.
1343 */
1344 total_len = rfa->actual_size & 0x3fff;
1345 if (total_len < sizeof(struct ether_header) ||
1346 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1347 sizeof(struct fxp_rfa) ||
1348 rfa->rfa_status & FXP_RFA_STATUS_CRC) {
1349 m_freem(m);
1350 continue;
1351 }
1352 m->m_pkthdr.len = m->m_len = total_len;
78195a76 1353 ifp->if_input(ifp, m);
984263bc
MD
1354 }
1355 }
1356 if (rnr) {
1357 fxp_scb_wait(sc);
1358 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1359 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1360 RFA_ALIGNMENT_FUDGE);
1361 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1362 }
1363}
1364
1365/*
1366 * Update packet in/out/collision statistics. The i82557 doesn't
1367 * allow you to access these counters without doing a fairly
1368 * expensive DMA to get _all_ of the statistics it maintains, so
1369 * we do this operation here only once per second. The statistics
1370 * counters in the kernel are updated from the previous dump-stats
1371 * DMA and then a new dump-stats DMA is started. The on-chip
1372 * counters are zeroed when the DMA completes. If we can't start
1373 * the DMA immediately, we don't wait - we just prepare to read
1374 * them again next time.
1375 */
1376static void
1377fxp_tick(void *xsc)
1378{
1379 struct fxp_softc *sc = xsc;
3dc849fa 1380 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
1381 struct fxp_stats *sp = sc->fxp_stats;
1382 struct fxp_cb_tx *txp;
acaaa437 1383 struct mbuf *m;
984263bc 1384
78195a76
MD
1385 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1386
984263bc
MD
1387 ifp->if_opackets += sp->tx_good;
1388 ifp->if_collisions += sp->tx_total_collisions;
1389 if (sp->rx_good) {
1390 ifp->if_ipackets += sp->rx_good;
1391 sc->rx_idle_secs = 0;
1392 } else {
1393 /*
1394 * Receiver's been idle for another second.
1395 */
1396 sc->rx_idle_secs++;
1397 }
1398 ifp->if_ierrors +=
1399 sp->rx_crc_errors +
1400 sp->rx_alignment_errors +
1401 sp->rx_rnr_errors +
1402 sp->rx_overrun_errors;
1403 /*
1404 * If any transmit underruns occured, bump up the transmit
1405 * threshold by another 512 bytes (64 * 8).
1406 */
1407 if (sp->tx_underruns) {
1408 ifp->if_oerrors += sp->tx_underruns;
1409 if (tx_threshold < 192)
1410 tx_threshold += 64;
1411 }
37103068 1412
984263bc
MD
1413 /*
1414 * Release any xmit buffers that have completed DMA. This isn't
1415 * strictly necessary to do here, but it's advantagous for mbufs
1416 * with external storage to be released in a timely manner rather
1417 * than being defered for a potentially long time. This limits
1418 * the delay to a maximum of one second.
1419 */
1420 for (txp = sc->cbl_first; sc->tx_queued &&
1421 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1422 txp = txp->next) {
acaaa437 1423 if ((m = txp->mb_head) != NULL) {
984263bc 1424 txp->mb_head = NULL;
acaaa437
MD
1425 sc->tx_queued--;
1426 m_freem(m);
1427 } else {
1428 sc->tx_queued--;
984263bc 1429 }
984263bc
MD
1430 }
1431 sc->cbl_first = txp;
1432 /*
1433 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1434 * then assume the receiver has locked up and attempt to clear
1435 * the condition by reprogramming the multicast filter. This is
1436 * a work-around for a bug in the 82557 where the receiver locks
1437 * up if it gets certain types of garbage in the syncronization
1438 * bits prior to the packet header. This bug is supposed to only
1439 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1440 * mode as well (perhaps due to a 10/100 speed transition).
1441 */
1442 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1443 sc->rx_idle_secs = 0;
1444 fxp_mc_setup(sc);
1445 }
1446 /*
1447 * If there is no pending command, start another stats
1448 * dump. Otherwise punt for now.
1449 */
1450 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1451 /*
1452 * Start another stats dump.
1453 */
1454 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1455 } else {
1456 /*
1457 * A previous command is still waiting to be accepted.
1458 * Just zero our copy of the stats and wait for the
1459 * next timer event to update them.
1460 */
1461 sp->tx_good = 0;
1462 sp->tx_underruns = 0;
1463 sp->tx_total_collisions = 0;
1464
1465 sp->rx_good = 0;
1466 sp->rx_crc_errors = 0;
1467 sp->rx_alignment_errors = 0;
1468 sp->rx_rnr_errors = 0;
1469 sp->rx_overrun_errors = 0;
1470 }
1471 if (sc->miibus != NULL)
1472 mii_tick(device_get_softc(sc->miibus));
984263bc
MD
1473 /*
1474 * Schedule another timeout one second from now.
1475 */
a1f4b801 1476 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
37103068 1477
78195a76 1478 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
1479}
1480
1481/*
1482 * Stop the interface. Cancels the statistics updater and resets
1483 * the interface.
1484 */
1485static void
1486fxp_stop(struct fxp_softc *sc)
1487{
3dc849fa 1488 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
1489 struct fxp_cb_tx *txp;
1490 int i;
1491
1492 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1493 ifp->if_timer = 0;
1494
984263bc
MD
1495 /*
1496 * Cancel stats updater.
1497 */
a1f4b801 1498 callout_stop(&sc->fxp_stat_timer);
984263bc
MD
1499
1500 /*
1501 * Issue software reset, which also unloads the microcode.
1502 */
1503 sc->flags &= ~FXP_FLAG_UCODE;
1504 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1505 DELAY(50);
1506
1507 /*
1508 * Release any xmit buffers.
1509 */
1510 txp = sc->cbl_base;
1511 if (txp != NULL) {
1512 for (i = 0; i < FXP_NTXCB; i++) {
1513 if (txp[i].mb_head != NULL) {
1514 m_freem(txp[i].mb_head);
1515 txp[i].mb_head = NULL;
1516 }
1517 }
1518 }
1519 sc->tx_queued = 0;
1520
1521 /*
1522 * Free all the receive buffers then reallocate/reinitialize
1523 */
1524 if (sc->rfa_headm != NULL)
1525 m_freem(sc->rfa_headm);
1526 sc->rfa_headm = NULL;
1527 sc->rfa_tailm = NULL;
1528 for (i = 0; i < FXP_NRFABUFS; i++) {
1529 if (fxp_add_rfabuf(sc, NULL) != 0) {
1530 /*
1531 * This "can't happen" - we're at splimp()
1532 * and we just freed all the buffers we need
1533 * above.
1534 */
1535 panic("fxp_stop: no buffers!");
1536 }
1537 }
1538}
1539
1540/*
1541 * Watchdog/transmission transmit timeout handler. Called when a
1542 * transmission is started on the interface, but no interrupt is
1543 * received before the timeout. This usually indicates that the
1544 * card has wedged for some reason.
1545 */
1546static void
1547fxp_watchdog(struct ifnet *ifp)
1548{
af340cf5 1549 if_printf(ifp, "device timeout\n");
984263bc 1550 ifp->if_oerrors++;
af340cf5 1551 fxp_init(ifp->if_softc);
984263bc
MD
1552}
1553
1554static void
1555fxp_init(void *xsc)
1556{
1557 struct fxp_softc *sc = xsc;
3dc849fa 1558 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
1559 struct fxp_cb_config *cbp;
1560 struct fxp_cb_ias *cb_ias;
1561 struct fxp_cb_tx *txp;
1562 struct fxp_cb_mcs *mcsp;
37103068
JS
1563 int i, prm;
1564
984263bc
MD
1565 /*
1566 * Cancel any pending I/O
1567 */
1568 fxp_stop(sc);
1569
1570 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1571
1572 /*
1573 * Initialize base of CBL and RFA memory. Loading with zero
1574 * sets it up for regular linear addressing.
1575 */
1576 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1577 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1578
1579 fxp_scb_wait(sc);
1580 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1581
1582 /*
1583 * Initialize base of dump-stats buffer.
1584 */
1585 fxp_scb_wait(sc);
1586 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1587 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1588
1589 /*
1590 * Attempt to load microcode if requested.
1591 */
1592 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1593 fxp_load_ucode(sc);
1594
1595 /*
1596 * Initialize the multicast address list.
1597 */
1598 if (fxp_mc_addrs(sc)) {
1599 mcsp = sc->mcsp;
1600 mcsp->cb_status = 0;
1601 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1602 mcsp->link_addr = -1;
1603 /*
1604 * Start the multicast setup command.
1605 */
1606 fxp_scb_wait(sc);
1607 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1608 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1609 /* ...and wait for it to complete. */
1610 fxp_dma_wait(&mcsp->cb_status, sc);
1611 }
1612
1613 /*
1614 * We temporarily use memory that contains the TxCB list to
1615 * construct the config CB. The TxCB list memory is rebuilt
1616 * later.
1617 */
1618 cbp = (struct fxp_cb_config *) sc->cbl_base;
1619
1620 /*
1621 * This bcopy is kind of disgusting, but there are a bunch of must be
1622 * zero and must be one bits in this structure and this is the easiest
1623 * way to initialize them all to proper values.
1624 */
1625 bcopy(fxp_cb_config_template,
1626 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1627 sizeof(fxp_cb_config_template));
1628
1629 cbp->cb_status = 0;
1630 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1631 cbp->link_addr = -1; /* (no) next command */
1632 cbp->byte_count = 22; /* (22) bytes to config */
1633 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1634 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1635 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1636 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1637 cbp->type_enable = 0; /* actually reserved */
1638 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1639 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1640 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1641 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1642 cbp->dma_mbce = 0; /* (disable) dma max counters */
1643 cbp->late_scb = 0; /* (don't) defer SCB update */
1644 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1645 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1646 cbp->ci_int = 1; /* interrupt on CU idle */
1647 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1648 cbp->ext_stats_dis = 1; /* disable extended counters */
1649 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1650 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1651 cbp->disc_short_rx = !prm; /* discard short packets */
1652 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1653 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1654 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1655 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1656 cbp->csma_dis = 0; /* (don't) disable link */
1657 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1658 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1659 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1660 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1661 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1662 cbp->nsai = 1; /* (don't) disable source addr insert */
1663 cbp->preamble_length = 2; /* (7 byte) preamble */
1664 cbp->loopback = 0; /* (don't) loopback */
1665 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1666 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1667 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1668 cbp->promiscuous = prm; /* promiscuous mode */
1669 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1670 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1671 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1672 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1673 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1674
1675 cbp->stripping = !prm; /* truncate rx packet to byte count */
1676 cbp->padding = 1; /* (do) pad short tx packets */
1677 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1678 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1679 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1680 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1681 /* must set wake_en in PMCSR also */
1682 cbp->force_fdx = 0; /* (don't) force full duplex */
1683 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1684 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1685 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1686
1687 if (sc->revision == FXP_REV_82557) {
1688 /*
1689 * The 82557 has no hardware flow control, the values
1690 * below are the defaults for the chip.
1691 */
1692 cbp->fc_delay_lsb = 0;
1693 cbp->fc_delay_msb = 0x40;
1694 cbp->pri_fc_thresh = 3;
1695 cbp->tx_fc_dis = 0;
1696 cbp->rx_fc_restop = 0;
1697 cbp->rx_fc_restart = 0;
1698 cbp->fc_filter = 0;
1699 cbp->pri_fc_loc = 1;
1700 } else {
1701 cbp->fc_delay_lsb = 0x1f;
1702 cbp->fc_delay_msb = 0x01;
1703 cbp->pri_fc_thresh = 3;
1704 cbp->tx_fc_dis = 0; /* enable transmit FC */
1705 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1706 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1707 cbp->fc_filter = !prm; /* drop FC frames to host */
1708 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1709 }
1710
1711 /*
1712 * Start the config command/DMA.
1713 */
1714 fxp_scb_wait(sc);
1715 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1716 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1717 /* ...and wait for it to complete. */
1718 fxp_dma_wait(&cbp->cb_status, sc);
1719
1720 /*
1721 * Now initialize the station address. Temporarily use the TxCB
1722 * memory area like we did above for the config CB.
1723 */
1724 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1725 cb_ias->cb_status = 0;
1726 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1727 cb_ias->link_addr = -1;
1728 bcopy(sc->arpcom.ac_enaddr,
1729 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1730 sizeof(sc->arpcom.ac_enaddr));
1731
1732 /*
1733 * Start the IAS (Individual Address Setup) command/DMA.
1734 */
1735 fxp_scb_wait(sc);
1736 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1737 /* ...and wait for it to complete. */
1738 fxp_dma_wait(&cb_ias->cb_status, sc);
1739
1740 /*
1741 * Initialize transmit control block (TxCB) list.
1742 */
1743
1744 txp = sc->cbl_base;
1745 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1746 for (i = 0; i < FXP_NTXCB; i++) {
1747 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1748 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1749 txp[i].link_addr =
1750 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1751 if (sc->flags & FXP_FLAG_EXT_TXCB)
1752 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1753 else
1754 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1755 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1756 }
1757 /*
1758 * Set the suspend flag on the first TxCB and start the control
1759 * unit. It will execute the NOP and then suspend.
1760 */
1761 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1762 sc->cbl_first = sc->cbl_last = txp;
1763 sc->tx_queued = 1;
1764
1765 fxp_scb_wait(sc);
1766 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1767
1768 /*
1769 * Initialize receiver buffer area - RFA.
1770 */
1771 fxp_scb_wait(sc);
1772 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1773 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1774 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1775
1776 /*
1777 * Set current media.
1778 */
1779 if (sc->miibus != NULL)
1780 mii_mediachg(device_get_softc(sc->miibus));
1781
1782 ifp->if_flags |= IFF_RUNNING;
1783 ifp->if_flags &= ~IFF_OACTIVE;
1784
1785 /*
1786 * Enable interrupts.
1787 */
1788#ifdef DEVICE_POLLING
1789 /*
1790 * ... but only do that if we are not polling. And because (presumably)
1791 * the default is interrupts on, we need to disable them explicitly!
1792 */
46f25451 1793 if ( ifp->if_flags & IFF_POLLING )
984263bc
MD
1794 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1795 else
1796#endif /* DEVICE_POLLING */
1797 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
984263bc
MD
1798
1799 /*
1800 * Start stats updater.
1801 */
a1f4b801 1802 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
984263bc
MD
1803}
1804
1805static int
1806fxp_serial_ifmedia_upd(struct ifnet *ifp)
1807{
1808
1809 return (0);
1810}
1811
1812static void
1813fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1814{
1815
1816 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1817}
1818
1819/*
1820 * Change media according to request.
1821 */
1822static int
1823fxp_ifmedia_upd(struct ifnet *ifp)
1824{
1825 struct fxp_softc *sc = ifp->if_softc;
1826 struct mii_data *mii;
1827
1828 mii = device_get_softc(sc->miibus);
1829 mii_mediachg(mii);
1830 return (0);
1831}
1832
1833/*
1834 * Notify the world which media we're using.
1835 */
1836static void
1837fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1838{
1839 struct fxp_softc *sc = ifp->if_softc;
1840 struct mii_data *mii;
1841
1842 mii = device_get_softc(sc->miibus);
1843 mii_pollstat(mii);
1844 ifmr->ifm_active = mii->mii_media_active;
1845 ifmr->ifm_status = mii->mii_media_status;
1846
1847 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1848 sc->cu_resume_bug = 1;
1849 else
1850 sc->cu_resume_bug = 0;
1851}
1852
1853/*
1854 * Add a buffer to the end of the RFA buffer list.
1855 * Return 0 if successful, 1 for failure. A failure results in
1856 * adding the 'oldm' (if non-NULL) on to the end of the list -
1857 * tossing out its old contents and recycling it.
1858 * The RFA struct is stuck at the beginning of mbuf cluster and the
1859 * data pointer is fixed up to point just past it.
1860 */
1861static int
1862fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1863{
1864 u_int32_t v;
1865 struct mbuf *m;
1866 struct fxp_rfa *rfa, *p_rfa;
1867
74f1caca 1868 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc
MD
1869 if (m == NULL) { /* try to recycle the old mbuf instead */
1870 if (oldm == NULL)
1871 return 1;
1872 m = oldm;
1873 m->m_data = m->m_ext.ext_buf;
1874 }
1875
1876 /*
1877 * Move the data pointer up so that the incoming data packet
1878 * will be 32-bit aligned.
1879 */
1880 m->m_data += RFA_ALIGNMENT_FUDGE;
1881
1882 /*
1883 * Get a pointer to the base of the mbuf cluster and move
1884 * data start past it.
1885 */
1886 rfa = mtod(m, struct fxp_rfa *);
1887 m->m_data += sizeof(struct fxp_rfa);
1888 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1889
1890 /*
1891 * Initialize the rest of the RFA. Note that since the RFA
1892 * is misaligned, we cannot store values directly. Instead,
1893 * we use an optimized, inline copy.
1894 */
1895
1896 rfa->rfa_status = 0;
1897 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1898 rfa->actual_size = 0;
1899
1900 v = -1;
1901 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1902 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1903
1904 /*
1905 * If there are other buffers already on the list, attach this
1906 * one to the end by fixing up the tail to point to this one.
1907 */
1908 if (sc->rfa_headm != NULL) {
1909 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1910 RFA_ALIGNMENT_FUDGE);
1911 sc->rfa_tailm->m_next = m;
1912 v = vtophys(rfa);
1913 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1914 p_rfa->rfa_control = 0;
1915 } else {
1916 sc->rfa_headm = m;
1917 }
1918 sc->rfa_tailm = m;
1919
1920 return (m == oldm);
1921}
1922
1923static volatile int
1924fxp_miibus_readreg(device_t dev, int phy, int reg)
1925{
1926 struct fxp_softc *sc = device_get_softc(dev);
1927 int count = 10000;
1928 int value;
1929
1930 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1931 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1932
1933 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1934 && count--)
1935 DELAY(10);
1936
1937 if (count <= 0)
1938 device_printf(dev, "fxp_miibus_readreg: timed out\n");
1939
1940 return (value & 0xffff);
1941}
1942
1943static void
1944fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
1945{
1946 struct fxp_softc *sc = device_get_softc(dev);
1947 int count = 10000;
1948
1949 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1950 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1951 (value & 0xffff));
1952
1953 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1954 count--)
1955 DELAY(10);
1956
1957 if (count <= 0)
1958 device_printf(dev, "fxp_miibus_writereg: timed out\n");
1959}
1960
1961static int
bd4539cc 1962fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc
MD
1963{
1964 struct fxp_softc *sc = ifp->if_softc;
1965 struct ifreq *ifr = (struct ifreq *)data;
1966 struct mii_data *mii;
37103068 1967 int error = 0;
984263bc 1968
984263bc 1969 switch (command) {
984263bc
MD
1970
1971 case SIOCSIFFLAGS:
1972 if (ifp->if_flags & IFF_ALLMULTI)
1973 sc->flags |= FXP_FLAG_ALL_MCAST;
1974 else
1975 sc->flags &= ~FXP_FLAG_ALL_MCAST;
1976
1977 /*
1978 * If interface is marked up and not running, then start it.
1979 * If it is marked down and running, stop it.
1980 * XXX If it's up then re-initialize it. This is so flags
1981 * such as IFF_PROMISC are handled.
1982 */
1983 if (ifp->if_flags & IFF_UP) {
1984 fxp_init(sc);
1985 } else {
1986 if (ifp->if_flags & IFF_RUNNING)
1987 fxp_stop(sc);
1988 }
1989 break;
1990
1991 case SIOCADDMULTI:
1992 case SIOCDELMULTI:
1993 if (ifp->if_flags & IFF_ALLMULTI)
1994 sc->flags |= FXP_FLAG_ALL_MCAST;
1995 else
1996 sc->flags &= ~FXP_FLAG_ALL_MCAST;
1997 /*
1998 * Multicast list has changed; set the hardware filter
1999 * accordingly.
2000 */
2001 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2002 fxp_mc_setup(sc);
2003 /*
2004 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2005 * again rather than else {}.
2006 */
2007 if (sc->flags & FXP_FLAG_ALL_MCAST)
2008 fxp_init(sc);
2009 error = 0;
2010 break;
2011
2012 case SIOCSIFMEDIA:
2013 case SIOCGIFMEDIA:
2014 if (sc->miibus != NULL) {
2015 mii = device_get_softc(sc->miibus);
2016 error = ifmedia_ioctl(ifp, ifr,
2017 &mii->mii_media, command);
2018 } else {
2019 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2020 }
2021 break;
2022
2023 default:
20de928f
JS
2024 error = ether_ioctl(ifp, command, data);
2025 break;
984263bc 2026 }
984263bc
MD
2027 return (error);
2028}
2029
2030/*
2031 * Fill in the multicast address list and return number of entries.
2032 */
2033static int
2034fxp_mc_addrs(struct fxp_softc *sc)
2035{
2036 struct fxp_cb_mcs *mcsp = sc->mcsp;
3dc849fa 2037 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
2038 struct ifmultiaddr *ifma;
2039 int nmcasts;
2040
2041 nmcasts = 0;
2042 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
984263bc 2043 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
2044 if (ifma->ifma_addr->sa_family != AF_LINK)
2045 continue;
2046 if (nmcasts >= MAXMCADDR) {
2047 sc->flags |= FXP_FLAG_ALL_MCAST;
2048 nmcasts = 0;
2049 break;
2050 }
2051 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2052 (void *)(uintptr_t)(volatile void *)
2053 &sc->mcsp->mc_addr[nmcasts][0], 6);
2054 nmcasts++;
2055 }
2056 }
2057 mcsp->mc_cnt = nmcasts * 6;
2058 return (nmcasts);
2059}
2060
2061/*
2062 * Program the multicast filter.
2063 *
2064 * We have an artificial restriction that the multicast setup command
2065 * must be the first command in the chain, so we take steps to ensure
2066 * this. By requiring this, it allows us to keep up the performance of
2067 * the pre-initialized command ring (esp. link pointers) by not actually
2068 * inserting the mcsetup command in the ring - i.e. its link pointer
2069 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2070 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2071 * lead into the regular TxCB ring when it completes.
2072 *
2073 * This function must be called at splimp.
2074 */
2075static void
2076fxp_mc_setup(struct fxp_softc *sc)
2077{
2078 struct fxp_cb_mcs *mcsp = sc->mcsp;
3dc849fa 2079 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
2080 int count;
2081
2082 /*
2083 * If there are queued commands, we must wait until they are all
2084 * completed. If we are already waiting, then add a NOP command
2085 * with interrupt option so that we're notified when all commands
2086 * have been completed - fxp_start() ensures that no additional
2087 * TX commands will be added when need_mcsetup is true.
2088 */
2089 if (sc->tx_queued) {
2090 struct fxp_cb_tx *txp;
2091
2092 /*
2093 * need_mcsetup will be true if we are already waiting for the
2094 * NOP command to be completed (see below). In this case, bail.
2095 */
2096 if (sc->need_mcsetup)
2097 return;
2098 sc->need_mcsetup = 1;
2099
2100 /*
2101 * Add a NOP command with interrupt so that we are notified
2102 * when all TX commands have been processed.
2103 */
2104 txp = sc->cbl_last->next;
2105 txp->mb_head = NULL;
2106 txp->cb_status = 0;
2107 txp->cb_command = FXP_CB_COMMAND_NOP |
2108 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2109 /*
2110 * Advance the end of list forward.
2111 */
2112 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2113 sc->cbl_last = txp;
2114 sc->tx_queued++;
2115 /*
2116 * Issue a resume in case the CU has just suspended.
2117 */
2118 fxp_scb_wait(sc);
2119 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2120 /*
2121 * Set a 5 second timer just in case we don't hear from the
2122 * card again.
2123 */
2124 ifp->if_timer = 5;
2125
2126 return;
2127 }
2128 sc->need_mcsetup = 0;
2129
2130 /*
2131 * Initialize multicast setup descriptor.
2132 */
2133 mcsp->next = sc->cbl_base;
2134 mcsp->mb_head = NULL;
2135 mcsp->cb_status = 0;
2136 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2137 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2138 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2139 (void) fxp_mc_addrs(sc);
2140 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2141 sc->tx_queued = 1;
2142
2143 /*
2144 * Wait until command unit is not active. This should never
2145 * be the case when nothing is queued, but make sure anyway.
2146 */
2147 count = 100;
2148 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2149 FXP_SCB_CUS_ACTIVE && --count)
2150 DELAY(10);
2151 if (count == 0) {
c81df1a6 2152 if_printf(&sc->arpcom.ac_if, "command queue timeout\n");
984263bc
MD
2153 return;
2154 }
2155
2156 /*
2157 * Start the multicast setup command.
2158 */
2159 fxp_scb_wait(sc);
2160 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2161 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2162
2163 ifp->if_timer = 2;
2164 return;
2165}
2166
2167static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2168static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2169static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2170static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2171static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2172static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2173
2174#define UCODE(x) x, sizeof(x)
2175
2176struct ucode {
2177 u_int32_t revision;
2178 u_int32_t *ucode;
2179 int length;
2180 u_short int_delay_offset;
2181 u_short bundle_max_offset;
2182} ucode_table[] = {
2183 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2184 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2185 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2186 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2187 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2188 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2189 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2190 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2191 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2192 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2193 { 0, NULL, 0, 0, 0 }
2194};
2195
2196static void
2197fxp_load_ucode(struct fxp_softc *sc)
2198{
2199 struct ucode *uc;
2200 struct fxp_cb_ucode *cbp;
2201
2202 for (uc = ucode_table; uc->ucode != NULL; uc++)
2203 if (sc->revision == uc->revision)
2204 break;
2205 if (uc->ucode == NULL)
2206 return;
2207 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2208 cbp->cb_status = 0;
2209 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2210 cbp->link_addr = -1; /* (no) next command */
2211 memcpy(cbp->ucode, uc->ucode, uc->length);
2212 if (uc->int_delay_offset)
2213 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2214 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2215 if (uc->bundle_max_offset)
2216 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2217 sc->tunable_bundle_max;
2218 /*
2219 * Download the ucode to the chip.
2220 */
2221 fxp_scb_wait(sc);
2222 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2223 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2224 /* ...and wait for it to complete. */
2225 fxp_dma_wait(&cbp->cb_status, sc);
c81df1a6 2226 if_printf(&sc->arpcom.ac_if,
984263bc
MD
2227 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2228 sc->tunable_int_delay,
2229 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2230 sc->flags |= FXP_FLAG_UCODE;
2231}
2232
2233static int
2234sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2235{
2236 int error, value;
2237
2238 value = *(int *)arg1;
2239 error = sysctl_handle_int(oidp, &value, 0, req);
2240 if (error || !req->newptr)
2241 return (error);
2242 if (value < low || value > high)
2243 return (EINVAL);
2244 *(int *)arg1 = value;
2245 return (0);
2246}
2247
2248/*
2249 * Interrupt delay is expressed in microseconds, a multiplier is used
2250 * to convert this to the appropriate clock ticks before using.
2251 */
2252static int
2253sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2254{
2255 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2256}
2257
2258static int
2259sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2260{
2261 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
2262}