drm/i915: Update to Linux 3.9.11
[dragonfly.git] / sys / dev / drm / i915 / i915_suspend.c
CommitLineData
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1/*
2 *
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3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
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5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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25 */
26
18e26a6d 27#include <drm/drmP.h>
5c6c6f23 28#include <drm/i915_drm.h>
e3adcf8f 29#include "intel_drv.h"
e9243325 30#include "i915_reg.h"
b3705d71 31
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32static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
33{
34 struct drm_i915_private *dev_priv = dev->dev_private;
35
36 I915_WRITE8(index_port, reg);
37 return I915_READ8(data_port);
38}
39
40static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
41{
42 struct drm_i915_private *dev_priv = dev->dev_private;
43
44 I915_READ8(st01);
45 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
46 return I915_READ8(VGA_AR_DATA_READ);
47}
48
49static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
50{
51 struct drm_i915_private *dev_priv = dev->dev_private;
52
53 I915_READ8(st01);
54 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
55 I915_WRITE8(VGA_AR_DATA_WRITE, val);
56}
57
58static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
59{
60 struct drm_i915_private *dev_priv = dev->dev_private;
61
62 I915_WRITE8(index_port, reg);
63 I915_WRITE8(data_port, val);
64}
65
66static void i915_save_vga(struct drm_device *dev)
67{
68 struct drm_i915_private *dev_priv = dev->dev_private;
69 int i;
70 u16 cr_index, cr_data, st01;
71
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72 /* VGA state */
73 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
74 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
75 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
76 dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
77
b3705d71 78 /* VGA color palette registers */
e9243325 79 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
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80
81 /* MSR bits */
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82 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
83 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
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84 cr_index = VGA_CR_INDEX_CGA;
85 cr_data = VGA_CR_DATA_CGA;
86 st01 = VGA_ST01_CGA;
87 } else {
88 cr_index = VGA_CR_INDEX_MDA;
89 cr_data = VGA_CR_DATA_MDA;
90 st01 = VGA_ST01_MDA;
91 }
92
93 /* CRT controller regs */
94 i915_write_indexed(dev, cr_index, cr_data, 0x11,
95 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
96 (~0x80));
97 for (i = 0; i <= 0x24; i++)
e9243325 98 dev_priv->regfile.saveCR[i] =
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99 i915_read_indexed(dev, cr_index, cr_data, i);
100 /* Make sure we don't turn off CR group 0 writes */
e9243325 101 dev_priv->regfile.saveCR[0x11] &= ~0x80;
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102
103 /* Attribute controller registers */
104 I915_READ8(st01);
e9243325 105 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
b3705d71 106 for (i = 0; i <= 0x14; i++)
e9243325 107 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
b3705d71 108 I915_READ8(st01);
e9243325 109 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
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110 I915_READ8(st01);
111
112 /* Graphics controller registers */
113 for (i = 0; i < 9; i++)
e9243325 114 dev_priv->regfile.saveGR[i] =
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115 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
116
e9243325 117 dev_priv->regfile.saveGR[0x10] =
b3705d71 118 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
e9243325 119 dev_priv->regfile.saveGR[0x11] =
b3705d71 120 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
e9243325 121 dev_priv->regfile.saveGR[0x18] =
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122 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
123
124 /* Sequencer registers */
125 for (i = 0; i < 8; i++)
e9243325 126 dev_priv->regfile.saveSR[i] =
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127 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
128}
129
130static void i915_restore_vga(struct drm_device *dev)
131{
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 int i;
134 u16 cr_index, cr_data, st01;
135
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136 /* VGA state */
137 I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
138
139 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
140 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
141 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
142 POSTING_READ(VGA_PD);
143 udelay(150);
144
b3705d71 145 /* MSR bits */
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146 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
147 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
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148 cr_index = VGA_CR_INDEX_CGA;
149 cr_data = VGA_CR_DATA_CGA;
150 st01 = VGA_ST01_CGA;
151 } else {
152 cr_index = VGA_CR_INDEX_MDA;
153 cr_data = VGA_CR_DATA_MDA;
154 st01 = VGA_ST01_MDA;
155 }
156
157 /* Sequencer registers, don't write SR07 */
158 for (i = 0; i < 7; i++)
159 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
e9243325 160 dev_priv->regfile.saveSR[i]);
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161
162 /* CRT controller regs */
163 /* Enable CR group 0 writes */
e9243325 164 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
b3705d71 165 for (i = 0; i <= 0x24; i++)
e9243325 166 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
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167
168 /* Graphics controller regs */
169 for (i = 0; i < 9; i++)
170 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
e9243325 171 dev_priv->regfile.saveGR[i]);
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172
173 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
e9243325 174 dev_priv->regfile.saveGR[0x10]);
b3705d71 175 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
e9243325 176 dev_priv->regfile.saveGR[0x11]);
b3705d71 177 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
e9243325 178 dev_priv->regfile.saveGR[0x18]);
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179
180 /* Attribute controller registers */
181 I915_READ8(st01); /* switch back to index mode */
182 for (i = 0; i <= 0x14; i++)
e9243325 183 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
b3705d71 184 I915_READ8(st01); /* switch back to index mode */
e9243325 185 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
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186 I915_READ8(st01);
187
188 /* VGA color palette registers */
e9243325 189 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
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190}
191
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192static void i915_save_display(struct drm_device *dev)
193{
194 struct drm_i915_private *dev_priv = dev->dev_private;
195
196 /* Display arbitration control */
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197 if (INTEL_INFO(dev)->gen <= 4)
198 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
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199
200 /* This is only meaningful in non-KMS mode */
e9243325 201 /* Don't regfile.save them in KMS mode */
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202 if (!drm_core_check_feature(dev, DRIVER_MODESET))
203 i915_save_display_reg(dev);
b3705d71 204
b3705d71 205 /* LVDS state */
e3adcf8f 206 if (HAS_PCH_SPLIT(dev)) {
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207 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
208 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
209 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
210 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
211 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
212 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
e3adcf8f 213 } else {
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214 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
215 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
216 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
217 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
e3adcf8f 218 if (INTEL_INFO(dev)->gen >= 4)
e9243325 219 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
e3adcf8f 220 if (IS_MOBILE(dev) && !IS_I830(dev))
e9243325 221 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
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222 }
223
224 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
e9243325 225 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
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226
227 if (HAS_PCH_SPLIT(dev)) {
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228 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
229 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
230 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
e3adcf8f 231 } else {
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232 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
233 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
234 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
235 }
236
e9243325 237 /* Only regfile.save FBC state on the platform that supports FBC */
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238 if (I915_HAS_FBC(dev)) {
239 if (HAS_PCH_SPLIT(dev)) {
e9243325 240 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
e3adcf8f 241 } else if (IS_GM45(dev)) {
e9243325 242 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
e3adcf8f 243 } else {
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244 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
245 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
246 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
247 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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248 }
249 }
250
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251 if (!drm_core_check_feature(dev, DRIVER_MODESET))
252 i915_save_vga(dev);
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253}
254
255static void i915_restore_display(struct drm_device *dev)
256{
257 struct drm_i915_private *dev_priv = dev->dev_private;
258
259 /* Display arbitration */
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260 if (INTEL_INFO(dev)->gen <= 4)
261 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
e9243325 262
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263 if (!drm_core_check_feature(dev, DRIVER_MODESET))
264 i915_restore_display_reg(dev);
e3adcf8f 265
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266 /* LVDS state */
267 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
e9243325 268 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
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269
270 if (HAS_PCH_SPLIT(dev)) {
e9243325 271 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS);
e3adcf8f 272 } else if (IS_MOBILE(dev) && !IS_I830(dev))
e9243325 273 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS);
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274
275 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
e9243325 276 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
b3705d71 277
e3adcf8f 278 if (HAS_PCH_SPLIT(dev)) {
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279 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
280 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
281 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
282 * otherwise we get blank eDP screen after S3 on some machines
283 */
284 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
285 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
286 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
287 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
288 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
289 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
e3adcf8f 290 I915_WRITE(RSTDBYCTL,
e9243325 291 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
e3adcf8f 292 } else {
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293 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
294 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
295 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
296 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
297 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
298 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
299 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
300 }
301
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302 /* only restore FBC info on the platform that supports FBC*/
303 intel_disable_fbc(dev);
304 if (I915_HAS_FBC(dev)) {
305 if (HAS_PCH_SPLIT(dev)) {
e9243325 306 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
e3adcf8f 307 } else if (IS_GM45(dev)) {
e9243325 308 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
e3adcf8f 309 } else {
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310 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
311 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
312 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
313 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
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314 }
315 }
e3adcf8f 316
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317 if (!drm_core_check_feature(dev, DRIVER_MODESET))
318 i915_restore_vga(dev);
319 else
320 i915_redisable_vga(dev);
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FT
321}
322
323int i915_save_state(struct drm_device *dev)
324{
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 int i;
327
f0d07c12 328 pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
e3adcf8f 329
a2fdbec6 330 mutex_lock(&dev->struct_mutex);
283d6ace 331
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332 i915_save_display(dev);
333
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334 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
335 /* Interrupt state */
336 if (HAS_PCH_SPLIT(dev)) {
337 dev_priv->regfile.saveDEIER = I915_READ(DEIER);
338 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
339 dev_priv->regfile.saveGTIER = I915_READ(GTIER);
340 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
341 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
342 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
343 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
344 I915_READ(RSTDBYCTL);
345 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
346 } else {
347 dev_priv->regfile.saveIER = I915_READ(IER);
348 dev_priv->regfile.saveIMR = I915_READ(IMR);
349 }
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350 }
351
e9243325 352 intel_disable_gt_powersave(dev);
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353
354 /* Cache mode state */
e9243325 355 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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356
357 /* Memory Arbitration state */
e9243325 358 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
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359
360 /* Scratch space */
361 for (i = 0; i < 16; i++) {
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362 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
363 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
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FT
364 }
365 for (i = 0; i < 3; i++)
e9243325 366 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
e3adcf8f 367
a2fdbec6 368 mutex_unlock(&dev->struct_mutex);
283d6ace 369
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370 return 0;
371}
372
373int i915_restore_state(struct drm_device *dev)
374{
375 struct drm_i915_private *dev_priv = dev->dev_private;
376 int i;
377
f0d07c12 378 pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
e3adcf8f 379
a2fdbec6 380 mutex_lock(&dev->struct_mutex);
283d6ace 381
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382 i915_restore_display(dev);
383
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384 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
385 /* Interrupt state */
386 if (HAS_PCH_SPLIT(dev)) {
387 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
388 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
389 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
390 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
391 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
392 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
393 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
394 } else {
395 I915_WRITE(IER, dev_priv->regfile.saveIER);
396 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
397 }
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398 }
399
e3adcf8f 400 /* Cache mode state */
e9243325 401 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
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402
403 /* Memory arbitration state */
e9243325 404 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
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405
406 for (i = 0; i < 16; i++) {
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FT
407 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
408 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
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409 }
410 for (i = 0; i < 3; i++)
e9243325 411 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
b3705d71 412
a2fdbec6 413 mutex_unlock(&dev->struct_mutex);
283d6ace 414
3f2f609d 415 intel_i2c_reset(dev);
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416
417 return 0;
418}