drm/i915: Update to Linux 3.9.11
[dragonfly.git] / sys / dev / drm / i915 / intel_ddi.c
CommitLineData
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1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include <drm/drmP.h>
29#include <drm/i915_drm.h>
30#include "i915_drv.h"
31#include "intel_drv.h"
32
33/* HDMI/DVI modes ignore everything but the last 2 items. So we share
34 * them for both DP and FDI transports, allowing those ports to
35 * automatically adapt to HDMI connections as well
36 */
37static const u32 hsw_ddi_translations_dp[] = {
38 0x00FFFFFF, 0x0006000E, /* DP parameters */
39 0x00D75FFF, 0x0005000A,
40 0x00C30FFF, 0x00040006,
41 0x80AAAFFF, 0x000B0000,
42 0x00FFFFFF, 0x0005000A,
43 0x00D75FFF, 0x000C0004,
44 0x80C30FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006,
46 0x80D75FFF, 0x000B0000,
47 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48};
49
50static const u32 hsw_ddi_translations_fdi[] = {
51 0x00FFFFFF, 0x0007000E, /* FDI parameters */
52 0x00D75FFF, 0x000F000A,
53 0x00C30FFF, 0x00060006,
54 0x00AAAFFF, 0x001E0000,
55 0x00FFFFFF, 0x000F000A,
56 0x00D75FFF, 0x00160004,
57 0x00C30FFF, 0x001E0000,
58 0x00FFFFFF, 0x00060006,
59 0x00D75FFF, 0x001E0000,
60 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61};
62
63static enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
64{
65 struct drm_encoder *encoder = &intel_encoder->base;
66 int type = intel_encoder->type;
67
68 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
69 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
70 struct intel_digital_port *intel_dig_port =
71 enc_to_dig_port(encoder);
72 return intel_dig_port->port;
73
74 } else if (type == INTEL_OUTPUT_ANALOG) {
75 return PORT_E;
76
77 } else {
78 DRM_ERROR("Invalid DDI encoder type %d\n", type);
79 BUG();
80 }
81}
82
83/* On Haswell, DDI port buffers must be programmed with correct values
84 * in advance. The buffer values are different for FDI and DP modes,
85 * but the HDMI/DVI fields are shared among those. So we program the DDI
86 * in either FDI or DP modes only, as HDMI connections will work with both
87 * of those
88 */
89static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, bool use_fdi_mode)
90{
91 struct drm_i915_private *dev_priv = dev->dev_private;
92 u32 reg;
93 int i;
94 const u32 *ddi_translations = ((use_fdi_mode) ?
95 hsw_ddi_translations_fdi :
96 hsw_ddi_translations_dp);
97
98 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
99 port_name(port),
100 use_fdi_mode ? "FDI" : "DP");
101
102 WARN((use_fdi_mode && (port != PORT_E)),
103 "Programming port %c in FDI mode, this probably will not work.\n",
104 port_name(port));
105
106 for (i=0, reg=DDI_BUF_TRANS(port); i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
107 I915_WRITE(reg, ddi_translations[i]);
108 reg += 4;
109 }
110}
111
112/* Program DDI buffers translations for DP. By default, program ports A-D in DP
113 * mode and port E for FDI.
114 */
115void intel_prepare_ddi(struct drm_device *dev)
116{
117 int port;
118
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119 if (!HAS_DDI(dev))
120 return;
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122 for (port = PORT_A; port < PORT_E; port++)
123 intel_prepare_ddi_buffers(dev, port, false);
124
125 /* DDI E is the suggested one to work in FDI mode, so program is as such
126 * by default. It will have to be re-programmed in case a digital DP
127 * output will be detected on it
128 */
129 intel_prepare_ddi_buffers(dev, PORT_E, true);
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130}
131
132static const long hsw_ddi_buf_ctl_values[] = {
133 DDI_BUF_EMP_400MV_0DB_HSW,
134 DDI_BUF_EMP_400MV_3_5DB_HSW,
135 DDI_BUF_EMP_400MV_6DB_HSW,
136 DDI_BUF_EMP_400MV_9_5DB_HSW,
137 DDI_BUF_EMP_600MV_0DB_HSW,
138 DDI_BUF_EMP_600MV_3_5DB_HSW,
139 DDI_BUF_EMP_600MV_6DB_HSW,
140 DDI_BUF_EMP_800MV_0DB_HSW,
141 DDI_BUF_EMP_800MV_3_5DB_HSW
142};
143
144static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
145 enum port port)
146{
147 uint32_t reg = DDI_BUF_CTL(port);
148 int i;
149
150 for (i = 0; i < 8; i++) {
151 udelay(1);
152 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
153 return;
154 }
155 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
156}
157
158/* Starting with Haswell, different DDI ports can work in FDI mode for
159 * connection to the PCH-located connectors. For this, it is necessary to train
160 * both the DDI port and PCH receiver for the desired DDI buffer settings.
161 *
162 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
163 * please note that when FDI mode is active on DDI E, it shares 2 lines with
164 * DDI A (which is used for eDP)
165 */
166
167void hsw_fdi_link_train(struct drm_crtc *crtc)
168{
169 struct drm_device *dev = crtc->dev;
170 struct drm_i915_private *dev_priv = dev->dev_private;
171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
172 u32 temp, i, rx_ctl_val;
173
174 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
175 * mode set "sequence for CRT port" document:
176 * - TP1 to TP2 time with the default value
177 * - FDI delay to 90h
178 */
179 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
180 FDI_RX_PWRDN_LANE0_VAL(2) |
181 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
182
183 /* Enable the PCH Receiver FDI PLL */
184 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
185 FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19);
186 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
187 POSTING_READ(_FDI_RXA_CTL);
188 udelay(220);
189
190 /* Switch from Rawclk to PCDclk */
191 rx_ctl_val |= FDI_PCDCLK;
192 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
193
194 /* Configure Port Clock Select */
195 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
196
197 /* Start the training iterating through available voltages and emphasis,
198 * testing each value twice. */
199 for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
200 /* Configure DP_TP_CTL with auto-training */
201 I915_WRITE(DP_TP_CTL(PORT_E),
202 DP_TP_CTL_FDI_AUTOTRAIN |
203 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
204 DP_TP_CTL_LINK_TRAIN_PAT1 |
205 DP_TP_CTL_ENABLE);
206
207 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
208 * DDI E does not support port reversal, the functionality is
209 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
210 * port reversal bit */
211 I915_WRITE(DDI_BUF_CTL(PORT_E),
212 DDI_BUF_CTL_ENABLE |
213 ((intel_crtc->fdi_lanes - 1) << 1) |
214 hsw_ddi_buf_ctl_values[i / 2]);
215 POSTING_READ(DDI_BUF_CTL(PORT_E));
216
217 udelay(600);
218
219 /* Program PCH FDI Receiver TU */
220 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
221
222 /* Enable PCH FDI Receiver with auto-training */
223 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
224 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
225 POSTING_READ(_FDI_RXA_CTL);
226
227 /* Wait for FDI receiver lane calibration */
228 udelay(30);
229
230 /* Unset FDI_RX_MISC pwrdn lanes */
231 temp = I915_READ(_FDI_RXA_MISC);
232 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
233 I915_WRITE(_FDI_RXA_MISC, temp);
234 POSTING_READ(_FDI_RXA_MISC);
235
236 /* Wait for FDI auto training time */
237 udelay(5);
238
239 temp = I915_READ(DP_TP_STATUS(PORT_E));
240 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
241 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
242
243 /* Enable normal pixel sending for FDI */
244 I915_WRITE(DP_TP_CTL(PORT_E),
245 DP_TP_CTL_FDI_AUTOTRAIN |
246 DP_TP_CTL_LINK_TRAIN_NORMAL |
247 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
248 DP_TP_CTL_ENABLE);
249
250 return;
251 }
252
253 temp = I915_READ(DDI_BUF_CTL(PORT_E));
254 temp &= ~DDI_BUF_CTL_ENABLE;
255 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
256 POSTING_READ(DDI_BUF_CTL(PORT_E));
257
258 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
259 temp = I915_READ(DP_TP_CTL(PORT_E));
260 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
261 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
262 I915_WRITE(DP_TP_CTL(PORT_E), temp);
263 POSTING_READ(DP_TP_CTL(PORT_E));
264
265 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
266
267 rx_ctl_val &= ~FDI_RX_ENABLE;
268 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
269 POSTING_READ(_FDI_RXA_CTL);
270
271 /* Reset FDI_RX_MISC pwrdn lanes */
272 temp = I915_READ(_FDI_RXA_MISC);
273 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
274 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
275 I915_WRITE(_FDI_RXA_MISC, temp);
276 POSTING_READ(_FDI_RXA_MISC);
277 }
278
279 DRM_ERROR("FDI link training failed!\n");
280}
281
282/* WRPLL clock dividers */
283struct wrpll_tmds_clock {
284 u32 clock;
285 u16 p; /* Post divider */
286 u16 n2; /* Feedback divider */
287 u16 r2; /* Reference divider */
288};
289
290/* Table of matching values for WRPLL clocks programming for each frequency.
291 * The code assumes this table is sorted. */
292static const struct wrpll_tmds_clock wrpll_tmds_clock_table[] = {
293 {19750, 38, 25, 18},
294 {20000, 48, 32, 18},
295 {21000, 36, 21, 15},
296 {21912, 42, 29, 17},
297 {22000, 36, 22, 15},
298 {23000, 36, 23, 15},
299 {23500, 40, 40, 23},
300 {23750, 26, 16, 14},
301 {24000, 36, 24, 15},
302 {25000, 36, 25, 15},
303 {25175, 26, 40, 33},
304 {25200, 30, 21, 15},
305 {26000, 36, 26, 15},
306 {27000, 30, 21, 14},
307 {27027, 18, 100, 111},
308 {27500, 30, 29, 19},
309 {28000, 34, 30, 17},
310 {28320, 26, 30, 22},
311 {28322, 32, 42, 25},
312 {28750, 24, 23, 18},
313 {29000, 30, 29, 18},
314 {29750, 32, 30, 17},
315 {30000, 30, 25, 15},
316 {30750, 30, 41, 24},
317 {31000, 30, 31, 18},
318 {31500, 30, 28, 16},
319 {32000, 30, 32, 18},
320 {32500, 28, 32, 19},
321 {33000, 24, 22, 15},
322 {34000, 28, 30, 17},
323 {35000, 26, 32, 19},
324 {35500, 24, 30, 19},
325 {36000, 26, 26, 15},
326 {36750, 26, 46, 26},
327 {37000, 24, 23, 14},
328 {37762, 22, 40, 26},
329 {37800, 20, 21, 15},
330 {38000, 24, 27, 16},
331 {38250, 24, 34, 20},
332 {39000, 24, 26, 15},
333 {40000, 24, 32, 18},
334 {40500, 20, 21, 14},
335 {40541, 22, 147, 89},
336 {40750, 18, 19, 14},
337 {41000, 16, 17, 14},
338 {41500, 22, 44, 26},
339 {41540, 22, 44, 26},
340 {42000, 18, 21, 15},
341 {42500, 22, 45, 26},
342 {43000, 20, 43, 27},
343 {43163, 20, 24, 15},
344 {44000, 18, 22, 15},
345 {44900, 20, 108, 65},
346 {45000, 20, 25, 15},
347 {45250, 20, 52, 31},
348 {46000, 18, 23, 15},
349 {46750, 20, 45, 26},
350 {47000, 20, 40, 23},
351 {48000, 18, 24, 15},
352 {49000, 18, 49, 30},
353 {49500, 16, 22, 15},
354 {50000, 18, 25, 15},
355 {50500, 18, 32, 19},
356 {51000, 18, 34, 20},
357 {52000, 18, 26, 15},
358 {52406, 14, 34, 25},
359 {53000, 16, 22, 14},
360 {54000, 16, 24, 15},
361 {54054, 16, 173, 108},
362 {54500, 14, 24, 17},
363 {55000, 12, 22, 18},
364 {56000, 14, 45, 31},
365 {56250, 16, 25, 15},
366 {56750, 14, 25, 17},
367 {57000, 16, 27, 16},
368 {58000, 16, 43, 25},
369 {58250, 16, 38, 22},
370 {58750, 16, 40, 23},
371 {59000, 14, 26, 17},
372 {59341, 14, 40, 26},
373 {59400, 16, 44, 25},
374 {60000, 16, 32, 18},
375 {60500, 12, 39, 29},
376 {61000, 14, 49, 31},
377 {62000, 14, 37, 23},
378 {62250, 14, 42, 26},
379 {63000, 12, 21, 15},
380 {63500, 14, 28, 17},
381 {64000, 12, 27, 19},
382 {65000, 14, 32, 19},
383 {65250, 12, 29, 20},
384 {65500, 12, 32, 22},
385 {66000, 12, 22, 15},
386 {66667, 14, 38, 22},
387 {66750, 10, 21, 17},
388 {67000, 14, 33, 19},
389 {67750, 14, 58, 33},
390 {68000, 14, 30, 17},
391 {68179, 14, 46, 26},
392 {68250, 14, 46, 26},
393 {69000, 12, 23, 15},
394 {70000, 12, 28, 18},
395 {71000, 12, 30, 19},
396 {72000, 12, 24, 15},
397 {73000, 10, 23, 17},
398 {74000, 12, 23, 14},
399 {74176, 8, 100, 91},
400 {74250, 10, 22, 16},
401 {74481, 12, 43, 26},
402 {74500, 10, 29, 21},
403 {75000, 12, 25, 15},
404 {75250, 10, 39, 28},
405 {76000, 12, 27, 16},
406 {77000, 12, 53, 31},
407 {78000, 12, 26, 15},
408 {78750, 12, 28, 16},
409 {79000, 10, 38, 26},
410 {79500, 10, 28, 19},
411 {80000, 12, 32, 18},
412 {81000, 10, 21, 14},
413 {81081, 6, 100, 111},
414 {81624, 8, 29, 24},
415 {82000, 8, 17, 14},
416 {83000, 10, 40, 26},
417 {83950, 10, 28, 18},
418 {84000, 10, 28, 18},
419 {84750, 6, 16, 17},
420 {85000, 6, 17, 18},
421 {85250, 10, 30, 19},
422 {85750, 10, 27, 17},
423 {86000, 10, 43, 27},
424 {87000, 10, 29, 18},
425 {88000, 10, 44, 27},
426 {88500, 10, 41, 25},
427 {89000, 10, 28, 17},
428 {89012, 6, 90, 91},
429 {89100, 10, 33, 20},
430 {90000, 10, 25, 15},
431 {91000, 10, 32, 19},
432 {92000, 10, 46, 27},
433 {93000, 10, 31, 18},
434 {94000, 10, 40, 23},
435 {94500, 10, 28, 16},
436 {95000, 10, 44, 25},
437 {95654, 10, 39, 22},
438 {95750, 10, 39, 22},
439 {96000, 10, 32, 18},
440 {97000, 8, 23, 16},
441 {97750, 8, 42, 29},
442 {98000, 8, 45, 31},
443 {99000, 8, 22, 15},
444 {99750, 8, 34, 23},
445 {100000, 6, 20, 18},
446 {100500, 6, 19, 17},
447 {101000, 6, 37, 33},
448 {101250, 8, 21, 14},
449 {102000, 6, 17, 15},
450 {102250, 6, 25, 22},
451 {103000, 8, 29, 19},
452 {104000, 8, 37, 24},
453 {105000, 8, 28, 18},
454 {106000, 8, 22, 14},
455 {107000, 8, 46, 29},
456 {107214, 8, 27, 17},
457 {108000, 8, 24, 15},
458 {108108, 8, 173, 108},
459 {109000, 6, 23, 19},
460 {110000, 6, 22, 18},
461 {110013, 6, 22, 18},
462 {110250, 8, 49, 30},
463 {110500, 8, 36, 22},
464 {111000, 8, 23, 14},
465 {111264, 8, 150, 91},
466 {111375, 8, 33, 20},
467 {112000, 8, 63, 38},
468 {112500, 8, 25, 15},
469 {113100, 8, 57, 34},
470 {113309, 8, 42, 25},
471 {114000, 8, 27, 16},
472 {115000, 6, 23, 18},
473 {116000, 8, 43, 25},
474 {117000, 8, 26, 15},
475 {117500, 8, 40, 23},
476 {118000, 6, 38, 29},
477 {119000, 8, 30, 17},
478 {119500, 8, 46, 26},
479 {119651, 8, 39, 22},
480 {120000, 8, 32, 18},
481 {121000, 6, 39, 29},
482 {121250, 6, 31, 23},
483 {121750, 6, 23, 17},
484 {122000, 6, 42, 31},
485 {122614, 6, 30, 22},
486 {123000, 6, 41, 30},
487 {123379, 6, 37, 27},
488 {124000, 6, 51, 37},
489 {125000, 6, 25, 18},
490 {125250, 4, 13, 14},
491 {125750, 4, 27, 29},
492 {126000, 6, 21, 15},
493 {127000, 6, 24, 17},
494 {127250, 6, 41, 29},
495 {128000, 6, 27, 19},
496 {129000, 6, 43, 30},
497 {129859, 4, 25, 26},
498 {130000, 6, 26, 18},
499 {130250, 6, 42, 29},
500 {131000, 6, 32, 22},
501 {131500, 6, 38, 26},
502 {131850, 6, 41, 28},
503 {132000, 6, 22, 15},
504 {132750, 6, 28, 19},
505 {133000, 6, 34, 23},
506 {133330, 6, 37, 25},
507 {134000, 6, 61, 41},
508 {135000, 6, 21, 14},
509 {135250, 6, 167, 111},
510 {136000, 6, 62, 41},
511 {137000, 6, 35, 23},
512 {138000, 6, 23, 15},
513 {138500, 6, 40, 26},
514 {138750, 6, 37, 24},
515 {139000, 6, 34, 22},
516 {139050, 6, 34, 22},
517 {139054, 6, 34, 22},
518 {140000, 6, 28, 18},
519 {141000, 6, 36, 23},
520 {141500, 6, 22, 14},
521 {142000, 6, 30, 19},
522 {143000, 6, 27, 17},
523 {143472, 4, 17, 16},
524 {144000, 6, 24, 15},
525 {145000, 6, 29, 18},
526 {146000, 6, 47, 29},
527 {146250, 6, 26, 16},
528 {147000, 6, 49, 30},
529 {147891, 6, 23, 14},
530 {148000, 6, 23, 14},
531 {148250, 6, 28, 17},
532 {148352, 4, 100, 91},
533 {148500, 6, 33, 20},
534 {149000, 6, 48, 29},
535 {150000, 6, 25, 15},
536 {151000, 4, 19, 17},
537 {152000, 6, 27, 16},
538 {152280, 6, 44, 26},
539 {153000, 6, 34, 20},
540 {154000, 6, 53, 31},
541 {155000, 6, 31, 18},
542 {155250, 6, 50, 29},
543 {155750, 6, 45, 26},
544 {156000, 6, 26, 15},
545 {157000, 6, 61, 35},
546 {157500, 6, 28, 16},
547 {158000, 6, 65, 37},
548 {158250, 6, 44, 25},
549 {159000, 6, 53, 30},
550 {159500, 6, 39, 22},
551 {160000, 6, 32, 18},
552 {161000, 4, 31, 26},
553 {162000, 4, 18, 15},
554 {162162, 4, 131, 109},
555 {162500, 4, 53, 44},
556 {163000, 4, 29, 24},
557 {164000, 4, 17, 14},
558 {165000, 4, 22, 18},
559 {166000, 4, 32, 26},
560 {167000, 4, 26, 21},
561 {168000, 4, 46, 37},
562 {169000, 4, 104, 83},
563 {169128, 4, 64, 51},
564 {169500, 4, 39, 31},
565 {170000, 4, 34, 27},
566 {171000, 4, 19, 15},
567 {172000, 4, 51, 40},
568 {172750, 4, 32, 25},
569 {172800, 4, 32, 25},
570 {173000, 4, 41, 32},
571 {174000, 4, 49, 38},
572 {174787, 4, 22, 17},
573 {175000, 4, 35, 27},
574 {176000, 4, 30, 23},
575 {177000, 4, 38, 29},
576 {178000, 4, 29, 22},
577 {178500, 4, 37, 28},
578 {179000, 4, 53, 40},
579 {179500, 4, 73, 55},
580 {180000, 4, 20, 15},
581 {181000, 4, 55, 41},
582 {182000, 4, 31, 23},
583 {183000, 4, 42, 31},
584 {184000, 4, 30, 22},
585 {184750, 4, 26, 19},
586 {185000, 4, 37, 27},
587 {186000, 4, 51, 37},
588 {187000, 4, 36, 26},
589 {188000, 4, 32, 23},
590 {189000, 4, 21, 15},
591 {190000, 4, 38, 27},
592 {190960, 4, 41, 29},
593 {191000, 4, 41, 29},
594 {192000, 4, 27, 19},
595 {192250, 4, 37, 26},
596 {193000, 4, 20, 14},
597 {193250, 4, 53, 37},
598 {194000, 4, 23, 16},
599 {194208, 4, 23, 16},
600 {195000, 4, 26, 18},
601 {196000, 4, 45, 31},
602 {197000, 4, 35, 24},
603 {197750, 4, 41, 28},
604 {198000, 4, 22, 15},
605 {198500, 4, 25, 17},
606 {199000, 4, 28, 19},
607 {200000, 4, 37, 25},
608 {201000, 4, 61, 41},
609 {202000, 4, 112, 75},
610 {202500, 4, 21, 14},
611 {203000, 4, 146, 97},
612 {204000, 4, 62, 41},
613 {204750, 4, 44, 29},
614 {205000, 4, 38, 25},
615 {206000, 4, 29, 19},
616 {207000, 4, 23, 15},
617 {207500, 4, 40, 26},
618 {208000, 4, 37, 24},
619 {208900, 4, 48, 31},
620 {209000, 4, 48, 31},
621 {209250, 4, 31, 20},
622 {210000, 4, 28, 18},
623 {211000, 4, 25, 16},
624 {212000, 4, 22, 14},
625 {213000, 4, 30, 19},
626 {213750, 4, 38, 24},
627 {214000, 4, 46, 29},
628 {214750, 4, 35, 22},
629 {215000, 4, 43, 27},
630 {216000, 4, 24, 15},
631 {217000, 4, 37, 23},
632 {218000, 4, 42, 26},
633 {218250, 4, 42, 26},
634 {218750, 4, 34, 21},
635 {219000, 4, 47, 29},
636 {220000, 4, 44, 27},
637 {220640, 4, 49, 30},
638 {220750, 4, 36, 22},
639 {221000, 4, 36, 22},
640 {222000, 4, 23, 14},
641 {222525, 4, 28, 17},
642 {222750, 4, 33, 20},
643 {227000, 4, 37, 22},
644 {230250, 4, 29, 17},
645 {233500, 4, 38, 22},
646 {235000, 4, 40, 23},
647 {238000, 4, 30, 17},
648 {241500, 2, 17, 19},
649 {245250, 2, 20, 22},
650 {247750, 2, 22, 24},
651 {253250, 2, 15, 16},
652 {256250, 2, 18, 19},
653 {262500, 2, 31, 32},
654 {267250, 2, 66, 67},
655 {268500, 2, 94, 95},
656 {270000, 2, 14, 14},
657 {272500, 2, 77, 76},
658 {273750, 2, 57, 56},
659 {280750, 2, 24, 23},
660 {281250, 2, 23, 22},
661 {286000, 2, 17, 16},
662 {291750, 2, 26, 24},
663 {296703, 2, 56, 51},
664 {297000, 2, 22, 20},
665 {298000, 2, 21, 19},
666};
667
668static void intel_ddi_mode_set(struct drm_encoder *encoder,
669 struct drm_display_mode *mode,
670 struct drm_display_mode *adjusted_mode)
671{
672 struct drm_crtc *crtc = encoder->crtc;
673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
674 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
675 int port = intel_ddi_get_encoder_port(intel_encoder);
676 int pipe = intel_crtc->pipe;
677 int type = intel_encoder->type;
678
679 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
680 port_name(port), pipe_name(pipe));
681
a2fdbec6 682 intel_crtc->eld_vld = false;
19df918d
FT
683 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
684 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
685 struct intel_digital_port *intel_dig_port =
686 enc_to_dig_port(encoder);
687
688 intel_dp->DP = intel_dig_port->port_reversal |
689 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
690 switch (intel_dp->lane_count) {
691 case 1:
692 intel_dp->DP |= DDI_PORT_WIDTH_X1;
693 break;
694 case 2:
695 intel_dp->DP |= DDI_PORT_WIDTH_X2;
696 break;
697 case 4:
698 intel_dp->DP |= DDI_PORT_WIDTH_X4;
699 break;
700 default:
701 intel_dp->DP |= DDI_PORT_WIDTH_X4;
702 WARN(1, "Unexpected DP lane count %d\n",
703 intel_dp->lane_count);
704 break;
705 }
706
707 if (intel_dp->has_audio) {
708 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
709 pipe_name(intel_crtc->pipe));
710
711 /* write eld */
712 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
713 intel_write_eld(encoder, adjusted_mode);
714 }
715
716 intel_dp_init_link_config(intel_dp);
717
718 } else if (type == INTEL_OUTPUT_HDMI) {
719 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
720
721 if (intel_hdmi->has_audio) {
722 /* Proper support for digital audio needs a new logic
723 * and a new set of registers, so we leave it for future
724 * patch bombing.
725 */
726 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
727 pipe_name(intel_crtc->pipe));
728
729 /* write eld */
730 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
731 intel_write_eld(encoder, adjusted_mode);
732 }
733
734 intel_hdmi->set_infoframes(encoder, adjusted_mode);
735 }
736}
737
738static struct intel_encoder *
739intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
740{
741 struct drm_device *dev = crtc->dev;
742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
743 struct intel_encoder *intel_encoder, *ret = NULL;
744 int num_encoders = 0;
745
746 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
747 ret = intel_encoder;
748 num_encoders++;
749 }
750
751 if (num_encoders != 1)
752 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders,
753 intel_crtc->pipe);
754
755 BUG_ON(ret == NULL);
756 return ret;
757}
758
759void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
760{
761 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
762 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
764 uint32_t val;
765
766 switch (intel_crtc->ddi_pll_sel) {
767 case PORT_CLK_SEL_SPLL:
768 plls->spll_refcount--;
769 if (plls->spll_refcount == 0) {
770 DRM_DEBUG_KMS("Disabling SPLL\n");
771 val = I915_READ(SPLL_CTL);
772 WARN_ON(!(val & SPLL_PLL_ENABLE));
773 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
774 POSTING_READ(SPLL_CTL);
775 }
776 break;
777 case PORT_CLK_SEL_WRPLL1:
778 plls->wrpll1_refcount--;
779 if (plls->wrpll1_refcount == 0) {
780 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
781 val = I915_READ(WRPLL_CTL1);
782 WARN_ON(!(val & WRPLL_PLL_ENABLE));
783 I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
784 POSTING_READ(WRPLL_CTL1);
785 }
786 break;
787 case PORT_CLK_SEL_WRPLL2:
788 plls->wrpll2_refcount--;
789 if (plls->wrpll2_refcount == 0) {
790 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
791 val = I915_READ(WRPLL_CTL2);
792 WARN_ON(!(val & WRPLL_PLL_ENABLE));
793 I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
794 POSTING_READ(WRPLL_CTL2);
795 }
796 break;
797 }
798
799 WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
800 WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
801 WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
802
803 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
804}
805
806static void intel_ddi_calculate_wrpll(int clock, int *p, int *n2, int *r2)
807{
808 u32 i;
809
810 for (i = 0; i < ARRAY_SIZE(wrpll_tmds_clock_table); i++)
811 if (clock <= wrpll_tmds_clock_table[i].clock)
812 break;
813
814 if (i == ARRAY_SIZE(wrpll_tmds_clock_table))
815 i--;
816
817 *p = wrpll_tmds_clock_table[i].p;
818 *n2 = wrpll_tmds_clock_table[i].n2;
819 *r2 = wrpll_tmds_clock_table[i].r2;
820
821 if (wrpll_tmds_clock_table[i].clock != clock)
822 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
823 wrpll_tmds_clock_table[i].clock, clock);
824
825 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
826 clock, *p, *n2, *r2);
827}
828
829bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
830{
831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
832 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
833 struct drm_encoder *encoder = &intel_encoder->base;
834 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
835 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
836 int type = intel_encoder->type;
837 enum i915_pipe pipe = intel_crtc->pipe;
838 uint32_t reg, val;
839
840 /* TODO: reuse PLLs when possible (compare values) */
841
842 intel_ddi_put_crtc_pll(crtc);
843
844 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
845 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
846
847 switch (intel_dp->link_bw) {
848 case DP_LINK_BW_1_62:
849 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
850 break;
851 case DP_LINK_BW_2_7:
852 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
853 break;
854 case DP_LINK_BW_5_4:
855 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
856 break;
857 default:
858 DRM_ERROR("Link bandwidth %d unsupported\n",
859 intel_dp->link_bw);
860 return false;
861 }
862
863 /* We don't need to turn any PLL on because we'll use LCPLL. */
864 return true;
865
866 } else if (type == INTEL_OUTPUT_HDMI) {
867 int p, n2, r2;
868
869 if (plls->wrpll1_refcount == 0) {
870 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
871 pipe_name(pipe));
872 plls->wrpll1_refcount++;
873 reg = WRPLL_CTL1;
874 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
875 } else if (plls->wrpll2_refcount == 0) {
876 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
877 pipe_name(pipe));
878 plls->wrpll2_refcount++;
879 reg = WRPLL_CTL2;
880 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
881 } else {
882 DRM_ERROR("No WRPLLs available!\n");
883 return false;
884 }
885
886 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE,
887 "WRPLL already enabled\n");
888
889 intel_ddi_calculate_wrpll(clock, &p, &n2, &r2);
890
891 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
892 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
893 WRPLL_DIVIDER_POST(p);
894
895 } else if (type == INTEL_OUTPUT_ANALOG) {
896 if (plls->spll_refcount == 0) {
897 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
898 pipe_name(pipe));
899 plls->spll_refcount++;
900 reg = SPLL_CTL;
901 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
902 }
903
904 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
905 "SPLL already enabled\n");
906
907 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
908
909 } else {
910 WARN(1, "Invalid DDI encoder type %d\n", type);
911 return false;
912 }
913
914 I915_WRITE(reg, val);
915 udelay(20);
916
917 return true;
918}
919
920void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
921{
922 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
924 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
925 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
926 int type = intel_encoder->type;
927 uint32_t temp;
928
929 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
930
931 temp = TRANS_MSA_SYNC_CLK;
932 switch (intel_crtc->bpp) {
933 case 18:
934 temp |= TRANS_MSA_6_BPC;
935 break;
936 case 24:
937 temp |= TRANS_MSA_8_BPC;
938 break;
939 case 30:
940 temp |= TRANS_MSA_10_BPC;
941 break;
942 case 36:
943 temp |= TRANS_MSA_12_BPC;
944 break;
945 default:
946 temp |= TRANS_MSA_8_BPC;
947 WARN(1, "%d bpp unsupported by DDI function\n",
948 intel_crtc->bpp);
949 }
950 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
951 }
952}
953
954void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
955{
956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
957 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
958 struct drm_encoder *encoder = &intel_encoder->base;
959 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
960 enum i915_pipe pipe = intel_crtc->pipe;
961 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
962 enum port port = intel_ddi_get_encoder_port(intel_encoder);
963 int type = intel_encoder->type;
964 uint32_t temp;
965
966 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
967 temp = TRANS_DDI_FUNC_ENABLE;
968 temp |= TRANS_DDI_SELECT_PORT(port);
969
970 switch (intel_crtc->bpp) {
971 case 18:
972 temp |= TRANS_DDI_BPC_6;
973 break;
974 case 24:
975 temp |= TRANS_DDI_BPC_8;
976 break;
977 case 30:
978 temp |= TRANS_DDI_BPC_10;
979 break;
980 case 36:
981 temp |= TRANS_DDI_BPC_12;
982 break;
983 default:
984 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
985 intel_crtc->bpp);
986 }
987
988 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
989 temp |= TRANS_DDI_PVSYNC;
990 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
991 temp |= TRANS_DDI_PHSYNC;
992
993 if (cpu_transcoder == TRANSCODER_EDP) {
994 switch (pipe) {
995 case PIPE_A:
a2fdbec6
FT
996 /* Can only use the always-on power well for eDP when
997 * not using the panel fitter, and when not using motion
998 * blur mitigation (which we don't support). */
999 if (dev_priv->pch_pf_size)
1000 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1001 else
1002 temp |= TRANS_DDI_EDP_INPUT_A_ON;
19df918d
FT
1003 break;
1004 case PIPE_B:
1005 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1006 break;
1007 case PIPE_C:
1008 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1009 break;
1010 default:
1011 BUG();
1012 break;
1013 }
1014 }
1015
1016 if (type == INTEL_OUTPUT_HDMI) {
1017 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1018
1019 if (intel_hdmi->has_hdmi_sink)
1020 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1021 else
1022 temp |= TRANS_DDI_MODE_SELECT_DVI;
1023
1024 } else if (type == INTEL_OUTPUT_ANALOG) {
1025 temp |= TRANS_DDI_MODE_SELECT_FDI;
1026 temp |= (intel_crtc->fdi_lanes - 1) << 1;
1027
1028 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1029 type == INTEL_OUTPUT_EDP) {
1030 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1031
1032 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1033
1034 switch (intel_dp->lane_count) {
1035 case 1:
1036 temp |= TRANS_DDI_PORT_WIDTH_X1;
1037 break;
1038 case 2:
1039 temp |= TRANS_DDI_PORT_WIDTH_X2;
1040 break;
1041 case 4:
1042 temp |= TRANS_DDI_PORT_WIDTH_X4;
1043 break;
1044 default:
1045 temp |= TRANS_DDI_PORT_WIDTH_X4;
1046 WARN(1, "Unsupported lane count %d\n",
1047 intel_dp->lane_count);
1048 }
1049
1050 } else {
1051 WARN(1, "Invalid encoder type %d for pipe %d\n",
1052 intel_encoder->type, pipe);
1053 }
1054
1055 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1056}
1057
1058void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1059 enum transcoder cpu_transcoder)
1060{
1061 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1062 uint32_t val = I915_READ(reg);
1063
1064 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
1065 val |= TRANS_DDI_PORT_NONE;
1066 I915_WRITE(reg, val);
1067}
1068
1069bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1070{
1071 struct drm_device *dev = intel_connector->base.dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private;
1073 struct intel_encoder *intel_encoder = intel_connector->encoder;
1074 int type = intel_connector->base.connector_type;
1075 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1076 enum i915_pipe pipe = 0;
1077 enum transcoder cpu_transcoder;
1078 uint32_t tmp;
1079
1080 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1081 return false;
1082
1083 if (port == PORT_A)
1084 cpu_transcoder = TRANSCODER_EDP;
1085 else
a2fdbec6 1086 cpu_transcoder = (enum transcoder) pipe;
19df918d
FT
1087
1088 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1089
1090 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1091 case TRANS_DDI_MODE_SELECT_HDMI:
1092 case TRANS_DDI_MODE_SELECT_DVI:
1093 return (type == DRM_MODE_CONNECTOR_HDMIA);
1094
1095 case TRANS_DDI_MODE_SELECT_DP_SST:
1096 if (type == DRM_MODE_CONNECTOR_eDP)
1097 return true;
1098 case TRANS_DDI_MODE_SELECT_DP_MST:
1099 return (type == DRM_MODE_CONNECTOR_DisplayPort);
1100
1101 case TRANS_DDI_MODE_SELECT_FDI:
1102 return (type == DRM_MODE_CONNECTOR_VGA);
1103
1104 default:
1105 return false;
1106 }
1107}
1108
1109bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1110 enum i915_pipe *pipe)
1111{
1112 struct drm_device *dev = encoder->base.dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
1114 enum port port = intel_ddi_get_encoder_port(encoder);
1115 u32 tmp;
1116 int i;
1117
1118 tmp = I915_READ(DDI_BUF_CTL(port));
1119
1120 if (!(tmp & DDI_BUF_CTL_ENABLE))
1121 return false;
1122
1123 if (port == PORT_A) {
1124 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1125
1126 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1127 case TRANS_DDI_EDP_INPUT_A_ON:
1128 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1129 *pipe = PIPE_A;
1130 break;
1131 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1132 *pipe = PIPE_B;
1133 break;
1134 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1135 *pipe = PIPE_C;
1136 break;
1137 }
1138
1139 return true;
1140 } else {
1141 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1142 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1143
1144 if ((tmp & TRANS_DDI_PORT_MASK)
1145 == TRANS_DDI_SELECT_PORT(port)) {
1146 *pipe = i;
1147 return true;
1148 }
1149 }
1150 }
1151
1152 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port);
1153
1154 return true;
1155}
1156
1157static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1158 enum i915_pipe pipe)
1159{
1160 uint32_t temp, ret;
1161 enum port port = I915_MAX_PORTS;
1162 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1163 pipe);
1164 int i;
1165
1166 if (cpu_transcoder == TRANSCODER_EDP) {
1167 port = PORT_A;
1168 } else {
1169 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1170 temp &= TRANS_DDI_PORT_MASK;
1171
1172 for (i = PORT_B; i <= PORT_E; i++)
1173 if (temp == TRANS_DDI_SELECT_PORT(i))
1174 port = i;
1175 }
1176
1177 ret = I915_READ(PORT_CLK_SEL(port));
1178
1179 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1180 pipe_name(pipe), port_name(port), ret);
1181
1182 return ret;
1183}
1184
1185void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1186{
1187 struct drm_i915_private *dev_priv = dev->dev_private;
1188 enum i915_pipe pipe;
1189 struct intel_crtc *intel_crtc;
1190
1191 for_each_pipe(pipe) {
1192 intel_crtc =
1193 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1194
1195 if (!intel_crtc->active)
1196 continue;
1197
1198 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1199 pipe);
1200
1201 switch (intel_crtc->ddi_pll_sel) {
1202 case PORT_CLK_SEL_SPLL:
1203 dev_priv->ddi_plls.spll_refcount++;
1204 break;
1205 case PORT_CLK_SEL_WRPLL1:
1206 dev_priv->ddi_plls.wrpll1_refcount++;
1207 break;
1208 case PORT_CLK_SEL_WRPLL2:
1209 dev_priv->ddi_plls.wrpll2_refcount++;
1210 break;
1211 }
1212 }
1213}
1214
1215void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1216{
1217 struct drm_crtc *crtc = &intel_crtc->base;
1218 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1219 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1220 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1221 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1222
1223 if (cpu_transcoder != TRANSCODER_EDP)
1224 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1225 TRANS_CLK_SEL_PORT(port));
1226}
1227
1228void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1229{
1230 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1231 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1232
1233 if (cpu_transcoder != TRANSCODER_EDP)
1234 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1235 TRANS_CLK_SEL_DISABLED);
1236}
1237
1238static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1239{
1240 struct drm_encoder *encoder = &intel_encoder->base;
1241 struct drm_crtc *crtc = encoder->crtc;
1242 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1244 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1245 int type = intel_encoder->type;
1246
1247 if (type == INTEL_OUTPUT_EDP) {
1248 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1249 ironlake_edp_panel_vdd_on(intel_dp);
1250 ironlake_edp_panel_on(intel_dp);
1251 ironlake_edp_panel_vdd_off(intel_dp, true);
1252 }
1253
1254 WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1255 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1256
1257 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1258 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1259
1260 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1261 intel_dp_start_link_train(intel_dp);
1262 intel_dp_complete_link_train(intel_dp);
1263 }
1264}
1265
1266static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1267{
1268 struct drm_encoder *encoder = &intel_encoder->base;
1269 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1270 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1271 int type = intel_encoder->type;
1272 uint32_t val;
1273 bool wait = false;
1274
1275 val = I915_READ(DDI_BUF_CTL(port));
1276 if (val & DDI_BUF_CTL_ENABLE) {
1277 val &= ~DDI_BUF_CTL_ENABLE;
1278 I915_WRITE(DDI_BUF_CTL(port), val);
1279 wait = true;
1280 }
1281
1282 val = I915_READ(DP_TP_CTL(port));
1283 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1284 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1285 I915_WRITE(DP_TP_CTL(port), val);
1286
1287 if (wait)
1288 intel_wait_ddi_buf_idle(dev_priv, port);
1289
1290 if (type == INTEL_OUTPUT_EDP) {
1291 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1292 ironlake_edp_panel_vdd_on(intel_dp);
1293 ironlake_edp_panel_off(intel_dp);
1294 }
1295
1296 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1297}
1298
1299static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1300{
1301 struct drm_encoder *encoder = &intel_encoder->base;
a2fdbec6
FT
1302 struct drm_crtc *crtc = encoder->crtc;
1303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1304 int pipe = intel_crtc->pipe;
19df918d
FT
1305 struct drm_device *dev = encoder->dev;
1306 struct drm_i915_private *dev_priv = dev->dev_private;
1307 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1308 int type = intel_encoder->type;
a2fdbec6 1309 uint32_t tmp;
19df918d
FT
1310
1311 if (type == INTEL_OUTPUT_HDMI) {
1312 struct intel_digital_port *intel_dig_port =
1313 enc_to_dig_port(encoder);
1314
1315 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1316 * are ignored so nothing special needs to be done besides
1317 * enabling the port.
1318 */
1319 I915_WRITE(DDI_BUF_CTL(port),
1320 intel_dig_port->port_reversal | DDI_BUF_CTL_ENABLE);
1321 } else if (type == INTEL_OUTPUT_EDP) {
1322 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1323
1324 ironlake_edp_backlight_on(intel_dp);
1325 }
a2fdbec6
FT
1326
1327 if (intel_crtc->eld_vld) {
1328 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1329 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1330 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1331 }
19df918d
FT
1332}
1333
1334static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1335{
1336 struct drm_encoder *encoder = &intel_encoder->base;
a2fdbec6
FT
1337 struct drm_crtc *crtc = encoder->crtc;
1338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1339 int pipe = intel_crtc->pipe;
19df918d 1340 int type = intel_encoder->type;
a2fdbec6
FT
1341 struct drm_device *dev = encoder->dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 uint32_t tmp;
19df918d
FT
1344
1345 if (type == INTEL_OUTPUT_EDP) {
1346 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1347
1348 ironlake_edp_backlight_off(intel_dp);
1349 }
a2fdbec6
FT
1350
1351 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1352 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1353 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
19df918d
FT
1354}
1355
1356int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1357{
1358 if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
1359 return 450;
1360 else if ((I915_READ(LCPLL_CTL) & LCPLL_CLK_FREQ_MASK) ==
1361 LCPLL_CLK_FREQ_450)
1362 return 450;
1363 else if (IS_ULT(dev_priv->dev))
1364 return 338;
1365 else
1366 return 540;
1367}
1368
1369void intel_ddi_pll_init(struct drm_device *dev)
1370{
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 uint32_t val = I915_READ(LCPLL_CTL);
1373
1374 /* The LCPLL register should be turned on by the BIOS. For now let's
1375 * just check its state and print errors in case something is wrong.
1376 * Don't even try to turn it on.
1377 */
1378
1379 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1380 intel_ddi_get_cdclk_freq(dev_priv));
1381
1382 if (val & LCPLL_CD_SOURCE_FCLK)
1383 DRM_ERROR("CDCLK source is not LCPLL\n");
1384
1385 if (val & LCPLL_PLL_DISABLE)
1386 DRM_ERROR("LCPLL is disabled\n");
1387}
1388
1389void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1390{
1391 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1392 struct intel_dp *intel_dp = &intel_dig_port->dp;
1393 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1394 enum port port = intel_dig_port->port;
19df918d 1395 uint32_t val;
a2fdbec6 1396 bool wait = false;
19df918d
FT
1397
1398 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1399 val = I915_READ(DDI_BUF_CTL(port));
1400 if (val & DDI_BUF_CTL_ENABLE) {
1401 val &= ~DDI_BUF_CTL_ENABLE;
1402 I915_WRITE(DDI_BUF_CTL(port), val);
1403 wait = true;
1404 }
1405
1406 val = I915_READ(DP_TP_CTL(port));
1407 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1408 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1409 I915_WRITE(DP_TP_CTL(port), val);
1410 POSTING_READ(DP_TP_CTL(port));
1411
1412 if (wait)
1413 intel_wait_ddi_buf_idle(dev_priv, port);
1414 }
1415
1416 val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1417 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1418 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1419 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1420 I915_WRITE(DP_TP_CTL(port), val);
1421 POSTING_READ(DP_TP_CTL(port));
1422
1423 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1424 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1425 POSTING_READ(DDI_BUF_CTL(port));
1426
1427 udelay(600);
1428}
1429
1430void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1431{
1432 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1433 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1434 uint32_t val;
1435
1436 intel_ddi_post_disable(intel_encoder);
1437
1438 val = I915_READ(_FDI_RXA_CTL);
1439 val &= ~FDI_RX_ENABLE;
1440 I915_WRITE(_FDI_RXA_CTL, val);
1441
1442 val = I915_READ(_FDI_RXA_MISC);
1443 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1444 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1445 I915_WRITE(_FDI_RXA_MISC, val);
1446
1447 val = I915_READ(_FDI_RXA_CTL);
1448 val &= ~FDI_PCDCLK;
1449 I915_WRITE(_FDI_RXA_CTL, val);
1450
1451 val = I915_READ(_FDI_RXA_CTL);
1452 val &= ~FDI_RX_PLL_ENABLE;
1453 I915_WRITE(_FDI_RXA_CTL, val);
1454}
1455
1456static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1457{
1458 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1459 int type = intel_encoder->type;
1460
1461 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1462 intel_dp_check_link_status(intel_dp);
1463}
1464
1465static void intel_ddi_destroy(struct drm_encoder *encoder)
1466{
1467 /* HDMI has nothing special to destroy, so we can go with this. */
1468 intel_dp_encoder_destroy(encoder);
1469}
1470
1471static bool intel_ddi_mode_fixup(struct drm_encoder *encoder,
1472 const struct drm_display_mode *mode,
1473 struct drm_display_mode *adjusted_mode)
1474{
1475 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1476 int type = intel_encoder->type;
1477
1478 WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n");
1479
1480 if (type == INTEL_OUTPUT_HDMI)
1481 return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode);
1482 else
1483 return intel_dp_mode_fixup(encoder, mode, adjusted_mode);
1484}
1485
1486static const struct drm_encoder_funcs intel_ddi_funcs = {
1487 .destroy = intel_ddi_destroy,
1488};
1489
1490static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = {
1491 .mode_fixup = intel_ddi_mode_fixup,
1492 .mode_set = intel_ddi_mode_set,
1493 .disable = intel_encoder_noop,
1494};
1495
1496void intel_ddi_init(struct drm_device *dev, enum port port)
1497{
1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499 struct intel_digital_port *intel_dig_port;
1500 struct intel_encoder *intel_encoder;
1501 struct drm_encoder *encoder;
1502 struct intel_connector *hdmi_connector = NULL;
1503 struct intel_connector *dp_connector = NULL;
1504
1505 intel_dig_port = kmalloc(sizeof(struct intel_digital_port),
5a3b77d5 1506 M_DRM, M_WAITOK | M_ZERO);
19df918d
FT
1507 if (!intel_dig_port)
1508 return;
1509
1510 dp_connector = kmalloc(sizeof(struct intel_connector),
5a3b77d5 1511 M_DRM, M_WAITOK | M_ZERO);
19df918d 1512 if (!dp_connector) {
5a3b77d5 1513 kfree(intel_dig_port, M_DRM);
19df918d
FT
1514 return;
1515 }
1516
1517 if (port != PORT_A) {
1518 hdmi_connector = kmalloc(sizeof(struct intel_connector),
5a3b77d5 1519 M_DRM, M_WAITOK | M_ZERO);
19df918d 1520 if (!hdmi_connector) {
5a3b77d5
FT
1521 kfree(dp_connector, M_DRM);
1522 kfree(intel_dig_port, M_DRM);
19df918d
FT
1523 return;
1524 }
1525 }
1526
1527 intel_encoder = &intel_dig_port->base;
1528 encoder = &intel_encoder->base;
1529
1530 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1531 DRM_MODE_ENCODER_TMDS);
1532 drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs);
1533
1534 intel_encoder->enable = intel_enable_ddi;
1535 intel_encoder->pre_enable = intel_ddi_pre_enable;
1536 intel_encoder->disable = intel_disable_ddi;
1537 intel_encoder->post_disable = intel_ddi_post_disable;
1538 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1539
1540 intel_dig_port->port = port;
1541 intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) &
1542 DDI_BUF_PORT_REVERSAL;
1543 if (hdmi_connector)
1544 intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port);
1545 else
1546 intel_dig_port->hdmi.sdvox_reg = 0;
1547 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1548
1549 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1550 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1551 intel_encoder->cloneable = false;
1552 intel_encoder->hot_plug = intel_ddi_hot_plug;
1553
1554 if (hdmi_connector)
1555 intel_hdmi_init_connector(intel_dig_port, hdmi_connector);
1556 intel_dp_init_connector(intel_dig_port, dp_connector);
1557}