drm/i915: Update to Linux 3.9.11
[dragonfly.git] / sys / dev / drm / include / uapi_drm / drm.h
CommitLineData
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1/**
2 * \file drm.h
3 * Header for the Direct Rendering Manager
984263bc 4 *
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5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 *
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
9 */
10
ce3d36d7 11/*
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12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
15 *
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
22 *
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
25 * Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
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34 */
35
36#ifndef _DRM_H_
37#define _DRM_H_
38
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39#include <linux/types.h>
40typedef unsigned int drm_handle_t;
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41
42#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
43#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
44#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
45#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
984263bc 46
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47#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
48#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
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49#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
50#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
51#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
52
ce3d36d7 53typedef unsigned int drm_context_t;
7f3c3d6f 54typedef unsigned int drm_drawable_t;
ce3d36d7 55typedef unsigned int drm_magic_t;
984263bc 56
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57/**
58 * Cliprect.
59 *
ce3d36d7 60 * \warning: If you change this structure, make sure you change
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61 * XF86DRIClipRectRec in the server as well
62 *
63 * \note KW: Actually it's illegal to change either for
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64 * backwards-compatibility reasons.
65 */
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66struct drm_clip_rect {
67 unsigned short x1;
68 unsigned short y1;
69 unsigned short x2;
70 unsigned short y2;
71};
72
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73/**
74 * Drawable information.
75 */
76struct drm_drawable_info {
77 unsigned int num_rects;
78 struct drm_clip_rect *rects;
79};
80
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81/**
82 * Texture region,
83 */
84struct drm_tex_region {
85 unsigned char next;
86 unsigned char prev;
87 unsigned char in_use;
88 unsigned char padding;
89 unsigned int age;
90};
91
92/**
93 * Hardware lock.
94 *
95 * The lock structure is a simple cache-line aligned integer. To avoid
96 * processor bus contention on a multiprocessor system, there should not be any
97 * other data stored in the same cache line.
98 */
99struct drm_hw_lock {
100 __volatile__ unsigned int lock; /**< lock variable */
101 char padding[60]; /**< Pad to cache line */
102};
103
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104/**
105 * DRM_IOCTL_VERSION ioctl argument type.
106 *
107 * \sa drmGetVersion().
108 */
109struct drm_version {
110 int version_major; /**< Major version */
111 int version_minor; /**< Minor version */
112 int version_patchlevel; /**< Patch level */
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113 size_t name_len; /**< Length of name buffer */
114 char __user *name; /**< Name of driver */
115 size_t date_len; /**< Length of date buffer */
116 char __user *date; /**< User-space buffer to hold date */
117 size_t desc_len; /**< Length of desc buffer */
118 char __user *desc; /**< User-space buffer to hold desc */
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119};
120
121/**
122 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
123 *
124 * \sa drmGetBusid() and drmSetBusId().
125 */
126struct drm_unique {
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127 size_t unique_len; /**< Length of unique */
128 char __user *unique; /**< Unique name for driver instantiation */
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129};
130
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131struct drm_list {
132 int count; /**< Length of user-space structures */
133 struct drm_version __user *version;
134};
135
136struct drm_block {
137 int unused;
138};
984263bc 139
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140/**
141 * DRM_IOCTL_CONTROL ioctl argument type.
142 *
143 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
144 */
145struct drm_control {
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146 enum {
147 DRM_ADD_COMMAND,
148 DRM_RM_COMMAND,
149 DRM_INST_HANDLER,
150 DRM_UNINST_HANDLER
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151 } func;
152 int irq;
153};
984263bc 154
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155/**
156 * Type of memory to map.
157 */
158enum drm_map_type {
159 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
160 _DRM_REGISTERS = 1, /**< no caching, no core dump */
161 _DRM_SHM = 2, /**< shared, cached */
162 _DRM_AGP = 3, /**< AGP/GART */
163 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
164 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
ce3d36d7 165 _DRM_GEM = 6, /**< GEM object */
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166};
167
168/**
169 * Memory mapping flags.
170 */
171enum drm_map_flags {
172 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
173 _DRM_READ_ONLY = 0x02,
174 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
175 _DRM_KERNEL = 0x08, /**< kernel requires access */
176 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
177 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
178 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
179 _DRM_DRIVER = 0x80 /**< Managed by driver */
180};
181
182struct drm_ctx_priv_map {
183 unsigned int ctx_id; /**< Context requesting private mapping */
184 void *handle; /**< Handle of map */
185};
186
187/**
188 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
189 * argument type.
190 *
191 * \sa drmAddMap().
192 */
193struct drm_map {
194 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
195 unsigned long size; /**< Requested physical size (bytes) */
196 enum drm_map_type type; /**< Type of memory to map */
197 enum drm_map_flags flags; /**< Flags */
198 void *handle; /**< User-space: "Handle" to pass to mmap() */
199 /**< Kernel-space: kernel-virtual address */
200 int mtrr; /**< MTRR slot used */
201 /* Private data */
202};
203
204/**
205 * DRM_IOCTL_GET_CLIENT ioctl argument type.
206 */
207struct drm_client {
208 int idx; /**< Which client desired? */
209 int auth; /**< Is client authenticated? */
210 unsigned long pid; /**< Process ID */
211 unsigned long uid; /**< User ID */
212 unsigned long magic; /**< Magic */
213 unsigned long iocs; /**< Ioctl count */
214};
215
216enum drm_stat_type {
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217 _DRM_STAT_LOCK,
218 _DRM_STAT_OPENS,
219 _DRM_STAT_CLOSES,
220 _DRM_STAT_IOCTLS,
221 _DRM_STAT_LOCKS,
222 _DRM_STAT_UNLOCKS,
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223 _DRM_STAT_VALUE, /**< Generic value */
224 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
225 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
226
227 _DRM_STAT_IRQ, /**< IRQ */
228 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
229 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
230 _DRM_STAT_DMA, /**< DMA */
231 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
232 _DRM_STAT_MISSED /**< Missed DMA opportunity */
233 /* Add to the *END* of the list */
234};
984263bc 235
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236/**
237 * DRM_IOCTL_GET_STATS ioctl argument type.
238 */
239struct drm_stats {
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240 unsigned long count;
241 struct {
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242 unsigned long value;
243 enum drm_stat_type type;
984263bc 244 } data[15];
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245};
246
247/**
248 * Hardware locking flags.
249 */
250enum drm_lock_flags {
251 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
252 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
253 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
254 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
255 /* These *HALT* flags aren't supported yet
256 -- they will be used to support the
257 full-screen DGA-like mode. */
258 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
259 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
260};
261
262/**
263 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
264 *
265 * \sa drmGetLock() and drmUnlock().
266 */
267struct drm_lock {
268 int context;
269 enum drm_lock_flags flags;
270};
271
272/**
273 * DMA flags
274 *
275 * \warning
276 * These values \e must match xf86drm.h.
277 *
278 * \sa drm_dma.
279 */
280enum drm_dma_flags {
281 /* Flags for DMA buffer dispatch */
282 _DRM_DMA_BLOCK = 0x01, /**<
283 * Block until buffer dispatched.
284 *
285 * \note The buffer may not yet have
286 * been processed by the hardware --
287 * getting a hardware lock with the
288 * hardware quiescent will ensure
289 * that the buffer has been
290 * processed.
291 */
292 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
293 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
294
295 /* Flags for DMA buffer request */
296 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
297 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
298 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
299};
300
301/**
302 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
303 *
304 * \sa drmAddBufs().
305 */
306struct drm_buf_desc {
307 int count; /**< Number of buffers of this size */
308 int size; /**< Size in bytes */
309 int low_mark; /**< Low water mark */
310 int high_mark; /**< High water mark */
984263bc 311 enum {
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312 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
313 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
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314 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
315 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
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316 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
317 } flags;
318 unsigned long agp_start; /**<
319 * Start address of where the AGP buffers are
320 * in the AGP aperture
321 */
322};
984263bc 323
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324/**
325 * DRM_IOCTL_INFO_BUFS ioctl argument type.
326 */
327struct drm_buf_info {
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328 int count; /**< Entries in list */
329 struct drm_buf_desc __user *list;
7f3c3d6f 330};
984263bc 331
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332/**
333 * DRM_IOCTL_FREE_BUFS ioctl argument type.
334 */
335struct drm_buf_free {
336 int count;
337 int __user *list;
338};
984263bc 339
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340/**
341 * Buffer information
342 *
343 * \sa drm_buf_map.
344 */
345struct drm_buf_pub {
346 int idx; /**< Index into the master buffer list */
347 int total; /**< Buffer size */
348 int used; /**< Amount of buffer in use (for DMA) */
349 void __user *address; /**< Address of buffer */
350};
351
352/**
353 * DRM_IOCTL_MAP_BUFS ioctl argument type.
354 */
355struct drm_buf_map {
356 int count; /**< Length of the buffer list */
7f3c3d6f 357 void __user *virtual; /**< Mmap'd area in user-virtual */
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358 struct drm_buf_pub __user *list; /**< Buffer information */
359};
984263bc 360
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361/**
362 * DRM_IOCTL_DMA ioctl argument type.
363 *
364 * Indices here refer to the offset into the buffer list in drm_buf_get.
365 *
366 * \sa drmDMA().
367 */
368struct drm_dma {
369 int context; /**< Context handle */
370 int send_count; /**< Number of buffers to send */
371 int __user *send_indices; /**< List of handles to buffers */
372 int __user *send_sizes; /**< Lengths of data to send */
373 enum drm_dma_flags flags; /**< Flags */
374 int request_count; /**< Number of buffers requested */
375 int request_size; /**< Desired size for buffers */
ce3d36d7 376 int __user *request_indices; /**< Buffer information */
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377 int __user *request_sizes;
378 int granted_count; /**< Number of buffers granted */
379};
984263bc 380
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381enum drm_ctx_flags {
382 _DRM_CONTEXT_PRESERVED = 0x01,
383 _DRM_CONTEXT_2DONLY = 0x02
384};
984263bc 385
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386/**
387 * DRM_IOCTL_ADD_CTX ioctl argument type.
388 *
389 * \sa drmCreateContext() and drmDestroyContext().
390 */
391struct drm_ctx {
392 drm_context_t handle;
393 enum drm_ctx_flags flags;
394};
984263bc 395
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396/**
397 * DRM_IOCTL_RES_CTX ioctl argument type.
398 */
399struct drm_ctx_res {
400 int count;
401 struct drm_ctx __user *contexts;
402};
403
404/**
405 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
406 */
407struct drm_draw {
408 drm_drawable_t handle;
409};
410
411/**
412 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
413 */
984263bc 414typedef enum {
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415 DRM_DRAWABLE_CLIPRECTS,
416} drm_drawable_info_type_t;
417
418struct drm_update_draw {
419 drm_drawable_t handle;
420 unsigned int type;
421 unsigned int num;
422 unsigned long long data;
423};
424
425/**
426 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
427 */
428struct drm_auth {
429 drm_magic_t magic;
430};
431
432/**
433 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
434 *
435 * \sa drmGetInterruptFromBusID().
436 */
437struct drm_irq_busid {
438 int irq; /**< IRQ number */
439 int busnum; /**< bus number */
440 int devnum; /**< device number */
441 int funcnum; /**< function number */
442};
443
444enum drm_vblank_seq_type {
445 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
446 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
ce3d36d7 447 /* bits 1-6 are reserved for high crtcs */
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448 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
449 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
ce3d36d7 450 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
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451 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
452 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
ce3d36d7 453 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
7f3c3d6f 454};
5718399f 455#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
984263bc 456
7f3c3d6f 457#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
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458#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
459 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
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460
461struct drm_wait_vblank_request {
7f3c3d6f 462 enum drm_vblank_seq_type type;
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463 unsigned int sequence;
464 unsigned long signal;
465};
466
467struct drm_wait_vblank_reply {
7f3c3d6f 468 enum drm_vblank_seq_type type;
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469 unsigned int sequence;
470 long tval_sec;
471 long tval_usec;
472};
473
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474/**
475 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
476 *
477 * \sa drmWaitVBlank().
478 */
479union drm_wait_vblank {
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480 struct drm_wait_vblank_request request;
481 struct drm_wait_vblank_reply reply;
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482};
483
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484#define _DRM_PRE_MODESET 1
485#define _DRM_POST_MODESET 2
486
487/**
488 * DRM_IOCTL_MODESET_CTL ioctl argument type
489 *
490 * \sa drmModesetCtl().
491 */
492struct drm_modeset_ctl {
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493 __u32 crtc;
494 __u32 cmd;
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495};
496
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497/**
498 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
499 *
500 * \sa drmAgpEnable().
501 */
502struct drm_agp_mode {
503 unsigned long mode; /**< AGP mode */
504};
505
506/**
507 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
508 *
509 * \sa drmAgpAlloc() and drmAgpFree().
510 */
511struct drm_agp_buffer {
512 unsigned long size; /**< In bytes -- will round to page boundary */
513 unsigned long handle; /**< Used for binding / unbinding */
514 unsigned long type; /**< Type of memory to allocate */
515 unsigned long physical; /**< Physical used by i810 */
516};
517
518/**
519 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
520 *
521 * \sa drmAgpBind() and drmAgpUnbind().
522 */
523struct drm_agp_binding {
524 unsigned long handle; /**< From drm_agp_buffer */
525 unsigned long offset; /**< In bytes -- will round to page boundary */
526};
984263bc 527
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528/**
529 * DRM_IOCTL_AGP_INFO ioctl argument type.
530 *
531 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
532 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
533 * drmAgpVendorId() and drmAgpDeviceId().
534 */
535struct drm_agp_info {
536 int agp_version_major;
537 int agp_version_minor;
984263bc 538 unsigned long mode;
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539 unsigned long aperture_base; /* physical address */
540 unsigned long aperture_size; /* bytes */
541 unsigned long memory_allowed; /* bytes */
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542 unsigned long memory_used;
543
ce3d36d7 544 /* PCI information */
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545 unsigned short id_vendor;
546 unsigned short id_device;
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547};
548
549/**
550 * DRM_IOCTL_SG_ALLOC ioctl argument type.
551 */
552struct drm_scatter_gather {
553 unsigned long size; /**< In bytes -- will round to page boundary */
554 unsigned long handle; /**< Used for mapping / unmapping */
555};
556
557/**
558 * DRM_IOCTL_SET_VERSION ioctl argument type.
559 */
560struct drm_set_version {
561 int drm_di_major;
562 int drm_di_minor;
563 int drm_dd_major;
564 int drm_dd_minor;
565};
566
ce3d36d7 567/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
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568struct drm_gem_close {
569 /** Handle of the object to be closed. */
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570 __u32 handle;
571 __u32 pad;
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572};
573
ce3d36d7 574/** DRM_IOCTL_GEM_FLINK ioctl argument type */
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575struct drm_gem_flink {
576 /** Handle for the object being named */
ce3d36d7 577 __u32 handle;
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578
579 /** Returned global name */
ce3d36d7 580 __u32 name;
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581};
582
ce3d36d7 583/** DRM_IOCTL_GEM_OPEN ioctl argument type */
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584struct drm_gem_open {
585 /** Name of object being opened */
ce3d36d7 586 __u32 name;
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587
588 /** Returned handle for the object */
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589 __u32 handle;
590
b3705d71 591 /** Returned size of the object */
ce3d36d7 592 __u64 size;
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593};
594
ce3d36d7 595/** DRM_IOCTL_GET_CAP ioctl argument type */
5718399f 596struct drm_get_cap {
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597 __u64 capability;
598 __u64 value;
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599};
600
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601#define DRM_CLOEXEC O_CLOEXEC
602struct drm_prime_handle {
603 __u32 handle;
5718399f 604
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605 /** Flags.. only applicable for handle->fd */
606 __u32 flags;
5718399f 607
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608 /** Returned dmabuf file descriptor */
609 __s32 fd;
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610};
611
ce3d36d7 612#include <uapi_drm/drm_mode.h>
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613
614#define DRM_IOCTL_BASE 'd'
615#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
616#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
617#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
618#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
619
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620#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
621#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
622#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
623#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
624#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
625#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
626#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
627#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
ce3d36d7 628#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
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629#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
630#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
631#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
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632#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
633
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634#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
635#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
636#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
637#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
638#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
639#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
640#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
641#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
642#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
643#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
644#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
645
646#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
647
648#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
ce3d36d7 649#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
7f3c3d6f 650
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651#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
652#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
653
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654#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
655#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
656#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
657#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
658#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
659#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
660#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
661#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
662#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
663#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
664#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
665#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
666#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
984263bc 667
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668#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
669#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
5718399f 670
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671#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
672#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
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673#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
674#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
675#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
676#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
677#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
678#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
679
b3705d71 680#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
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681#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
682
683#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
684
ce3d36d7 685#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
7f3c3d6f 686
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687#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
688#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
689#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
690#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
691#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
692#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
693#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
694#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
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695#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
696#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
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697
698#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
699#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
700#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
701#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
702#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
703#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
704#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
705#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
706
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707#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
708#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
709#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
5718399f 710#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
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711#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
712#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
5718399f 713#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
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714#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
715#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
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716
717/**
718 * Device specific ioctls should only be in their respective headers
719 * The device specific ioctl range is from 0x40 to 0x99.
720 * Generic IOCTLS restart at 0xA0.
721 *
722 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
723 * drmCommandReadWrite().
724 */
984263bc 725#define DRM_COMMAND_BASE 0x40
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726#define DRM_COMMAND_END 0xA0
727
728/**
729 * Header for events written back to userspace on the drm fd. The
730 * type defines the type of event, the length specifies the total
731 * length of the event (including the header), and user_data is
732 * typically a 64 bit value passed with the ioctl that triggered the
733 * event. A read on the drm fd will always only return complete
734 * events, that is, if for example the read buffer is 100 bytes, and
735 * there are two 64 byte events pending, only one will be returned.
736 *
737 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
738 * up are chipset specific.
739 */
740struct drm_event {
741 __u32 type;
742 __u32 length;
743};
744
745#define DRM_EVENT_VBLANK 0x01
746#define DRM_EVENT_FLIP_COMPLETE 0x02
747
748struct drm_event_vblank {
749 struct drm_event base;
750 __u64 user_data;
751 __u32 tv_sec;
752 __u32 tv_usec;
753 __u32 sequence;
754 __u32 reserved;
755};
756
757#define DRM_CAP_DUMB_BUFFER 0x1
758#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
759#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
760#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
761#define DRM_CAP_PRIME 0x5
762#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
763
764#define DRM_PRIME_CAP_IMPORT 0x1
765#define DRM_PRIME_CAP_EXPORT 0x2
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766
767/* typedef area */
b3705d71 768#ifndef __KERNEL__
7f3c3d6f 769typedef struct drm_clip_rect drm_clip_rect_t;
ce3d36d7 770typedef struct drm_drawable_info drm_drawable_info_t;
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771typedef struct drm_tex_region drm_tex_region_t;
772typedef struct drm_hw_lock drm_hw_lock_t;
773typedef struct drm_version drm_version_t;
774typedef struct drm_unique drm_unique_t;
775typedef struct drm_list drm_list_t;
776typedef struct drm_block drm_block_t;
777typedef struct drm_control drm_control_t;
778typedef enum drm_map_type drm_map_type_t;
779typedef enum drm_map_flags drm_map_flags_t;
780typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
781typedef struct drm_map drm_map_t;
782typedef struct drm_client drm_client_t;
783typedef enum drm_stat_type drm_stat_type_t;
784typedef struct drm_stats drm_stats_t;
785typedef enum drm_lock_flags drm_lock_flags_t;
786typedef struct drm_lock drm_lock_t;
787typedef enum drm_dma_flags drm_dma_flags_t;
788typedef struct drm_buf_desc drm_buf_desc_t;
789typedef struct drm_buf_info drm_buf_info_t;
790typedef struct drm_buf_free drm_buf_free_t;
791typedef struct drm_buf_pub drm_buf_pub_t;
792typedef struct drm_buf_map drm_buf_map_t;
793typedef struct drm_dma drm_dma_t;
794typedef union drm_wait_vblank drm_wait_vblank_t;
795typedef struct drm_agp_mode drm_agp_mode_t;
796typedef enum drm_ctx_flags drm_ctx_flags_t;
797typedef struct drm_ctx drm_ctx_t;
798typedef struct drm_ctx_res drm_ctx_res_t;
799typedef struct drm_draw drm_draw_t;
800typedef struct drm_update_draw drm_update_draw_t;
801typedef struct drm_auth drm_auth_t;
802typedef struct drm_irq_busid drm_irq_busid_t;
803typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
ce3d36d7 804
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805typedef struct drm_agp_buffer drm_agp_buffer_t;
806typedef struct drm_agp_binding drm_agp_binding_t;
807typedef struct drm_agp_info drm_agp_info_t;
808typedef struct drm_scatter_gather drm_scatter_gather_t;
809typedef struct drm_set_version drm_set_version_t;
7f3c3d6f 810#endif
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811
812#endif