drm/i915: Update to Linux 3.9.11
[dragonfly.git] / sys / dev / drm / include / uapi_drm / drm_mode.h
CommitLineData
575ea5a0
FT
1/*
2 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
4 * Copyright (c) 2008 Red Hat Inc.
5 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
6 * Copyright (c) 2007-2008 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
575ea5a0
FT
25 */
26
27#ifndef _DRM_MODE_H
28#define _DRM_MODE_H
29
ce3d36d7
FT
30#include <linux/types.h>
31
575ea5a0
FT
32#define DRM_DISPLAY_INFO_LEN 32
33#define DRM_CONNECTOR_NAME_LEN 32
34#define DRM_DISPLAY_MODE_LEN 32
35#define DRM_PROP_NAME_LEN 32
36
37#define DRM_MODE_TYPE_BUILTIN (1<<0)
38#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
39#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
40#define DRM_MODE_TYPE_PREFERRED (1<<3)
41#define DRM_MODE_TYPE_DEFAULT (1<<4)
42#define DRM_MODE_TYPE_USERDEF (1<<5)
43#define DRM_MODE_TYPE_DRIVER (1<<6)
44
45/* Video mode flags */
46/* bit compatible with the xorg definitions. */
47#define DRM_MODE_FLAG_PHSYNC (1<<0)
48#define DRM_MODE_FLAG_NHSYNC (1<<1)
49#define DRM_MODE_FLAG_PVSYNC (1<<2)
50#define DRM_MODE_FLAG_NVSYNC (1<<3)
51#define DRM_MODE_FLAG_INTERLACE (1<<4)
52#define DRM_MODE_FLAG_DBLSCAN (1<<5)
53#define DRM_MODE_FLAG_CSYNC (1<<6)
54#define DRM_MODE_FLAG_PCSYNC (1<<7)
55#define DRM_MODE_FLAG_NCSYNC (1<<8)
56#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
57#define DRM_MODE_FLAG_BCAST (1<<10)
58#define DRM_MODE_FLAG_PIXMUX (1<<11)
59#define DRM_MODE_FLAG_DBLCLK (1<<12)
60#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
61
62/* DPMS flags */
63/* bit compatible with the xorg definitions. */
64#define DRM_MODE_DPMS_ON 0
65#define DRM_MODE_DPMS_STANDBY 1
66#define DRM_MODE_DPMS_SUSPEND 2
67#define DRM_MODE_DPMS_OFF 3
68
69/* Scaling mode options */
70#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
71 software can still scale) */
72#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
73#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
74#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
75
76/* Dithering mode options */
77#define DRM_MODE_DITHERING_OFF 0
78#define DRM_MODE_DITHERING_ON 1
79#define DRM_MODE_DITHERING_AUTO 2
80
81/* Dirty info options */
82#define DRM_MODE_DIRTY_OFF 0
83#define DRM_MODE_DIRTY_ON 1
84#define DRM_MODE_DIRTY_ANNOTATE 2
85
86struct drm_mode_modeinfo {
ce3d36d7
FT
87 __u32 clock;
88 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
89 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
575ea5a0 90
ce3d36d7 91 __u32 vrefresh;
575ea5a0 92
ce3d36d7
FT
93 __u32 flags;
94 __u32 type;
575ea5a0
FT
95 char name[DRM_DISPLAY_MODE_LEN];
96};
97
98struct drm_mode_card_res {
ce3d36d7
FT
99 __u64 fb_id_ptr;
100 __u64 crtc_id_ptr;
101 __u64 connector_id_ptr;
102 __u64 encoder_id_ptr;
103 __u32 count_fbs;
104 __u32 count_crtcs;
105 __u32 count_connectors;
106 __u32 count_encoders;
107 __u32 min_width, max_width;
108 __u32 min_height, max_height;
575ea5a0
FT
109};
110
111struct drm_mode_crtc {
ce3d36d7
FT
112 __u64 set_connectors_ptr;
113 __u32 count_connectors;
575ea5a0 114
ce3d36d7
FT
115 __u32 crtc_id; /**< Id */
116 __u32 fb_id; /**< Id of framebuffer */
575ea5a0 117
ce3d36d7 118 __u32 x, y; /**< Position on the frameuffer */
575ea5a0 119
ce3d36d7
FT
120 __u32 gamma_size;
121 __u32 mode_valid;
575ea5a0
FT
122 struct drm_mode_modeinfo mode;
123};
124
125#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
126#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
127
128/* Planes blend with or override other bits on the CRTC */
129struct drm_mode_set_plane {
ce3d36d7
FT
130 __u32 plane_id;
131 __u32 crtc_id;
132 __u32 fb_id; /* fb object contains surface format type */
133 __u32 flags; /* see above flags */
575ea5a0
FT
134
135 /* Signed dest location allows it to be partially off screen */
ce3d36d7
FT
136 __s32 crtc_x, crtc_y;
137 __u32 crtc_w, crtc_h;
575ea5a0
FT
138
139 /* Source values are 16.16 fixed point */
ce3d36d7
FT
140 __u32 src_x, src_y;
141 __u32 src_h, src_w;
575ea5a0
FT
142};
143
144struct drm_mode_get_plane {
ce3d36d7 145 __u32 plane_id;
575ea5a0 146
ce3d36d7
FT
147 __u32 crtc_id;
148 __u32 fb_id;
575ea5a0 149
ce3d36d7
FT
150 __u32 possible_crtcs;
151 __u32 gamma_size;
575ea5a0 152
ce3d36d7
FT
153 __u32 count_format_types;
154 __u64 format_type_ptr;
575ea5a0
FT
155};
156
157struct drm_mode_get_plane_res {
ce3d36d7
FT
158 __u64 plane_id_ptr;
159 __u32 count_planes;
575ea5a0
FT
160};
161
162#define DRM_MODE_ENCODER_NONE 0
163#define DRM_MODE_ENCODER_DAC 1
164#define DRM_MODE_ENCODER_TMDS 2
165#define DRM_MODE_ENCODER_LVDS 3
166#define DRM_MODE_ENCODER_TVDAC 4
ce3d36d7 167#define DRM_MODE_ENCODER_VIRTUAL 5
575ea5a0
FT
168
169struct drm_mode_get_encoder {
ce3d36d7
FT
170 __u32 encoder_id;
171 __u32 encoder_type;
575ea5a0 172
ce3d36d7 173 __u32 crtc_id; /**< Id of crtc */
575ea5a0 174
ce3d36d7
FT
175 __u32 possible_crtcs;
176 __u32 possible_clones;
575ea5a0
FT
177};
178
179/* This is for connectors with multiple signal types. */
180/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
181#define DRM_MODE_SUBCONNECTOR_Automatic 0
182#define DRM_MODE_SUBCONNECTOR_Unknown 0
183#define DRM_MODE_SUBCONNECTOR_DVID 3
184#define DRM_MODE_SUBCONNECTOR_DVIA 4
185#define DRM_MODE_SUBCONNECTOR_Composite 5
186#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
187#define DRM_MODE_SUBCONNECTOR_Component 8
188#define DRM_MODE_SUBCONNECTOR_SCART 9
189
190#define DRM_MODE_CONNECTOR_Unknown 0
191#define DRM_MODE_CONNECTOR_VGA 1
192#define DRM_MODE_CONNECTOR_DVII 2
193#define DRM_MODE_CONNECTOR_DVID 3
194#define DRM_MODE_CONNECTOR_DVIA 4
195#define DRM_MODE_CONNECTOR_Composite 5
196#define DRM_MODE_CONNECTOR_SVIDEO 6
197#define DRM_MODE_CONNECTOR_LVDS 7
198#define DRM_MODE_CONNECTOR_Component 8
199#define DRM_MODE_CONNECTOR_9PinDIN 9
200#define DRM_MODE_CONNECTOR_DisplayPort 10
201#define DRM_MODE_CONNECTOR_HDMIA 11
202#define DRM_MODE_CONNECTOR_HDMIB 12
203#define DRM_MODE_CONNECTOR_TV 13
204#define DRM_MODE_CONNECTOR_eDP 14
ce3d36d7 205#define DRM_MODE_CONNECTOR_VIRTUAL 15
575ea5a0
FT
206
207struct drm_mode_get_connector {
208
ce3d36d7
FT
209 __u64 encoders_ptr;
210 __u64 modes_ptr;
211 __u64 props_ptr;
212 __u64 prop_values_ptr;
575ea5a0 213
ce3d36d7
FT
214 __u32 count_modes;
215 __u32 count_props;
216 __u32 count_encoders;
575ea5a0 217
ce3d36d7
FT
218 __u32 encoder_id; /**< Current Encoder */
219 __u32 connector_id; /**< Id */
220 __u32 connector_type;
221 __u32 connector_type_id;
575ea5a0 222
ce3d36d7
FT
223 __u32 connection;
224 __u32 mm_width, mm_height; /**< HxW in millimeters */
225 __u32 subpixel;
a2fdbec6
FT
226
227 __u32 pad;
575ea5a0
FT
228};
229
230#define DRM_MODE_PROP_PENDING (1<<0)
231#define DRM_MODE_PROP_RANGE (1<<1)
232#define DRM_MODE_PROP_IMMUTABLE (1<<2)
233#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
234#define DRM_MODE_PROP_BLOB (1<<4)
ce3d36d7 235#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
575ea5a0
FT
236
237struct drm_mode_property_enum {
ce3d36d7 238 __u64 value;
575ea5a0
FT
239 char name[DRM_PROP_NAME_LEN];
240};
241
242struct drm_mode_get_property {
ce3d36d7
FT
243 __u64 values_ptr; /* values and blob lengths */
244 __u64 enum_blob_ptr; /* enum and blob id ptrs */
575ea5a0 245
ce3d36d7
FT
246 __u32 prop_id;
247 __u32 flags;
575ea5a0
FT
248 char name[DRM_PROP_NAME_LEN];
249
ce3d36d7
FT
250 __u32 count_values;
251 __u32 count_enum_blobs;
575ea5a0
FT
252};
253
254struct drm_mode_connector_set_property {
ce3d36d7
FT
255 __u64 value;
256 __u32 prop_id;
257 __u32 connector_id;
258};
259
260struct drm_mode_obj_get_properties {
261 __u64 props_ptr;
262 __u64 prop_values_ptr;
263 __u32 count_props;
264 __u32 obj_id;
265 __u32 obj_type;
266};
267
268struct drm_mode_obj_set_property {
269 __u64 value;
270 __u32 prop_id;
271 __u32 obj_id;
272 __u32 obj_type;
575ea5a0
FT
273};
274
275struct drm_mode_get_blob {
ce3d36d7
FT
276 __u32 blob_id;
277 __u32 length;
278 __u64 data;
575ea5a0
FT
279};
280
281struct drm_mode_fb_cmd {
ce3d36d7
FT
282 __u32 fb_id;
283 __u32 width, height;
284 __u32 pitch;
285 __u32 bpp;
286 __u32 depth;
575ea5a0 287 /* driver specific handle */
ce3d36d7 288 __u32 handle;
575ea5a0
FT
289};
290
ce3d36d7 291#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
575ea5a0
FT
292
293struct drm_mode_fb_cmd2 {
ce3d36d7
FT
294 __u32 fb_id;
295 __u32 width, height;
296 __u32 pixel_format; /* fourcc code from drm_fourcc.h */
297 __u32 flags; /* see above flags */
575ea5a0
FT
298
299 /*
300 * In case of planar formats, this ioctl allows up to 4
301 * buffer objects with offets and pitches per plane.
302 * The pitch and offset order is dictated by the fourcc,
303 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
304 *
305 * YUV 4:2:0 image with a plane of 8 bit Y samples
306 * followed by an interleaved U/V plane containing
307 * 8 bit 2x2 subsampled colour difference samples.
308 *
309 * So it would consist of Y as offset[0] and UV as
310 * offeset[1]. Note that offset[0] will generally
311 * be 0.
312 */
ce3d36d7
FT
313 __u32 handles[4];
314 __u32 pitches[4]; /* pitch for each plane */
315 __u32 offsets[4]; /* offset of each plane */
575ea5a0
FT
316};
317
318#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
319#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
320#define DRM_MODE_FB_DIRTY_FLAGS 0x03
321
322#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
323
324/*
325 * Mark a region of a framebuffer as dirty.
326 *
327 * Some hardware does not automatically update display contents
328 * as a hardware or software draw to a framebuffer. This ioctl
329 * allows userspace to tell the kernel and the hardware what
330 * regions of the framebuffer have changed.
331 *
332 * The kernel or hardware is free to update more then just the
333 * region specified by the clip rects. The kernel or hardware
334 * may also delay and/or coalesce several calls to dirty into a
335 * single update.
336 *
337 * Userspace may annotate the updates, the annotates are a
338 * promise made by the caller that the change is either a copy
339 * of pixels or a fill of a single color in the region specified.
340 *
341 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
342 * the number of updated regions are half of num_clips given,
343 * where the clip rects are paired in src and dst. The width and
344 * height of each one of the pairs must match.
345 *
346 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
347 * promises that the region specified of the clip rects is filled
348 * completely with a single color as given in the color argument.
349 */
350
351struct drm_mode_fb_dirty_cmd {
ce3d36d7
FT
352 __u32 fb_id;
353 __u32 flags;
354 __u32 color;
355 __u32 num_clips;
356 __u64 clips_ptr;
575ea5a0
FT
357};
358
359struct drm_mode_mode_cmd {
ce3d36d7 360 __u32 connector_id;
575ea5a0
FT
361 struct drm_mode_modeinfo mode;
362};
363
ce3d36d7
FT
364#define DRM_MODE_CURSOR_BO 0x01
365#define DRM_MODE_CURSOR_MOVE 0x02
366#define DRM_MODE_CURSOR_FLAGS 0x03
575ea5a0
FT
367
368/*
ce3d36d7 369 * depending on the value in flags different members are used.
575ea5a0
FT
370 *
371 * CURSOR_BO uses
a2fdbec6 372 * crtc_id
575ea5a0
FT
373 * width
374 * height
a2fdbec6 375 * handle - if 0 turns the cursor off
575ea5a0
FT
376 *
377 * CURSOR_MOVE uses
a2fdbec6 378 * crtc_id
575ea5a0
FT
379 * x
380 * y
381 */
382struct drm_mode_cursor {
ce3d36d7
FT
383 __u32 flags;
384 __u32 crtc_id;
385 __s32 x;
386 __s32 y;
387 __u32 width;
388 __u32 height;
575ea5a0 389 /* driver specific handle */
ce3d36d7 390 __u32 handle;
575ea5a0
FT
391};
392
393struct drm_mode_crtc_lut {
ce3d36d7
FT
394 __u32 crtc_id;
395 __u32 gamma_size;
575ea5a0
FT
396
397 /* pointers to arrays */
ce3d36d7
FT
398 __u64 red;
399 __u64 green;
400 __u64 blue;
575ea5a0
FT
401};
402
403#define DRM_MODE_PAGE_FLIP_EVENT 0x01
404#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
405
406/*
407 * Request a page flip on the specified crtc.
408 *
409 * This ioctl will ask KMS to schedule a page flip for the specified
410 * crtc. Once any pending rendering targeting the specified fb (as of
411 * ioctl time) has completed, the crtc will be reprogrammed to display
412 * that fb after the next vertical refresh. The ioctl returns
413 * immediately, but subsequent rendering to the current fb will block
414 * in the execbuffer ioctl until the page flip happens. If a page
415 * flip is already pending as the ioctl is called, EBUSY will be
416 * returned.
417 *
418 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
419 * request that drm sends back a vblank event (see drm.h: struct
420 * drm_event_vblank) when the page flip is done. The user_data field
421 * passed in with this ioctl will be returned as the user_data field
422 * in the vblank event struct.
423 *
424 * The reserved field must be zero until we figure out something
425 * clever to use it for.
426 */
427
428struct drm_mode_crtc_page_flip {
ce3d36d7
FT
429 __u32 crtc_id;
430 __u32 fb_id;
431 __u32 flags;
432 __u32 reserved;
433 __u64 user_data;
575ea5a0
FT
434};
435
436/* create a dumb scanout buffer */
437struct drm_mode_create_dumb {
438 uint32_t height;
439 uint32_t width;
440 uint32_t bpp;
441 uint32_t flags;
442 /* handle, pitch, size will be returned */
443 uint32_t handle;
444 uint32_t pitch;
445 uint64_t size;
446};
447
448/* set up for mmap of a dumb scanout buffer */
449struct drm_mode_map_dumb {
450 /** Handle for the object being mapped. */
ce3d36d7
FT
451 __u32 handle;
452 __u32 pad;
575ea5a0
FT
453 /**
454 * Fake offset to use for subsequent mmap call
455 *
456 * This is a fixed-size type for 32/64 compatibility.
457 */
ce3d36d7 458 __u64 offset;
575ea5a0
FT
459};
460
461struct drm_mode_destroy_dumb {
462 uint32_t handle;
463};
464
465#endif