kernel - Add PCI functionality
[dragonfly.git] / sys / dev / agp / agp_i810.c
CommitLineData
ab5a0ec8 1/*
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2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
a904aa53 4 * Copyright (c) 2011 The FreeBSD Foundation
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5 * All rights reserved.
6 *
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7 * Portions of this software were developed by Konstantin Belousov
8 * under sponsorship from the FreeBSD Foundation.
9 *
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10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
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30 */
31
32/*
33 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
fdc3c5be 34 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
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35 *
36 * This is generic Intel GTT handling code, morphed from the AGP
37 * bridge code.
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38 */
39
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40#if 0
41#define KTR_AGP_I810 KTR_DEV
42#else
43#define KTR_AGP_I810 0
44#endif
45
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46#include <sys/param.h>
47#include <sys/systm.h>
48#include <sys/malloc.h>
49#include <sys/kernel.h>
50#include <sys/bus.h>
51#include <sys/lock.h>
1f7ab7c9 52#include <sys/rman.h>
984263bc 53
dcb4b80d 54#include "pcidevs.h"
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55#include <bus/pci/pcivar.h>
56#include <bus/pci/pcireg.h>
57#include "agppriv.h"
58#include "agpreg.h"
b2776052 59#include <drm/intel-gtt.h>
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60
61#include <vm/vm.h>
62#include <vm/vm_object.h>
63#include <vm/vm_page.h>
64#include <vm/vm_pageout.h>
65#include <vm/pmap.h>
66
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67#include <machine/md_var.h>
68
69#define bus_read_1(r, o) \
70 bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
71#define bus_read_4(r, o) \
72 bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
73#define bus_write_4(r, o, v) \
74 bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
75
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76MALLOC_DECLARE(M_AGP);
77
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78struct agp_i810_match;
79
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80static int agp_i915_check_active(device_t bridge_dev);
81static int agp_sb_check_active(device_t bridge_dev);
82
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83static void agp_i810_set_desc(device_t dev, const struct agp_i810_match *match);
84
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85static void agp_i915_dump_regs(device_t dev);
86static void agp_i965_dump_regs(device_t dev);
87static void agp_sb_dump_regs(device_t dev);
88
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89static int agp_i915_get_stolen_size(device_t dev);
90static int agp_sb_get_stolen_size(device_t dev);
09d2c144 91static int agp_gen8_get_stolen_size(device_t dev);
a904aa53 92
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93static int agp_i915_get_gtt_mappable_entries(device_t dev);
94
95static int agp_i810_get_gtt_total_entries(device_t dev);
96static int agp_i965_get_gtt_total_entries(device_t dev);
97static int agp_gen5_get_gtt_total_entries(device_t dev);
98static int agp_sb_get_gtt_total_entries(device_t dev);
09d2c144 99static int agp_gen8_get_gtt_total_entries(device_t dev);
a904aa53 100
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101static int agp_i830_install_gatt(device_t dev);
102
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103static void agp_i830_deinstall_gatt(device_t dev);
104
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105static void agp_i915_install_gtt_pte(device_t dev, u_int index,
106 vm_offset_t physical, int flags);
107static void agp_i965_install_gtt_pte(device_t dev, u_int index,
108 vm_offset_t physical, int flags);
109static void agp_g4x_install_gtt_pte(device_t dev, u_int index,
110 vm_offset_t physical, int flags);
111static void agp_sb_install_gtt_pte(device_t dev, u_int index,
112 vm_offset_t physical, int flags);
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113static void agp_gen8_install_gtt_pte(device_t dev, u_int index,
114 vm_offset_t physical, int flags);
a904aa53 115
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116static void agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte);
117static void agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte);
118static void agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte);
119static void agp_sb_write_gtt(device_t dev, u_int index, uint32_t pte);
120
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121static void agp_i915_sync_gtt_pte(device_t dev, u_int index);
122static void agp_i965_sync_gtt_pte(device_t dev, u_int index);
123static void agp_g4x_sync_gtt_pte(device_t dev, u_int index);
a904aa53 124
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125static int agp_i915_set_aperture(device_t dev, u_int32_t aperture);
126
127static int agp_i810_chipset_flush_setup(device_t dev);
128static int agp_i915_chipset_flush_setup(device_t dev);
129static int agp_i965_chipset_flush_setup(device_t dev);
130
131static void agp_i810_chipset_flush_teardown(device_t dev);
132static void agp_i915_chipset_flush_teardown(device_t dev);
133static void agp_i965_chipset_flush_teardown(device_t dev);
134
135static void agp_i810_chipset_flush(device_t dev);
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136static void agp_i915_chipset_flush(device_t dev);
137
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138enum {
139 CHIP_I810, /* i810/i815 */
140 CHIP_I830, /* 830M/845G */
141 CHIP_I855, /* 852GM/855GM/865G */
142 CHIP_I915, /* 915G/915GM */
143 CHIP_I965, /* G965 */
144 CHIP_G33, /* G33/Q33/Q35 */
7f9ec87c 145 CHIP_IGD, /* Pineview */
f16c0bab 146 CHIP_G4X, /* G45/Q45 */
a904aa53 147 CHIP_SB, /* SandyBridge */
fdc3c5be 148};
984263bc 149
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150/* The i810 through i855 have the registers at BAR 1, and the GATT gets
151 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
152 * start of the stolen memory, and should only be accessed by the OS through
153 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
154 * is registers, second 512KB is GATT.
155 */
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156static struct resource_spec agp_i915_res_spec[] = {
157 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
158 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
159 { -1, 0 }
160};
161
162static struct resource_spec agp_i965_res_spec[] = {
163 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
164 { -1, 0 }
165};
984263bc 166
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167static struct resource_spec agp_g4x_res_spec[] = {
168 { SYS_RES_MEMORY, AGP_G4X_MMADR, RF_ACTIVE | RF_SHAREABLE },
169 { SYS_RES_MEMORY, AGP_G4X_GTTADR, RF_ACTIVE | RF_SHAREABLE },
170 { -1, 0 }
171};
172
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173struct agp_i810_softc {
174 struct agp_softc agp;
175 u_int32_t initial_aperture; /* aperture size at startup */
176 struct agp_gatt *gatt;
984263bc 177 u_int32_t dcache_size; /* i810 only */
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178 u_int32_t stolen; /* number of i830/845 gtt
179 entries for stolen memory */
180 u_int stolen_size; /* BIOS-reserved graphics memory */
181 u_int gtt_total_entries; /* Total number of gtt ptes */
182 u_int gtt_mappable_entries; /* Number of gtt ptes mappable by CPU */
984263bc 183 device_t bdev; /* bridge device */
fdc3c5be 184 void *argb_cursor; /* contigmalloc area for ARGB cursor */
fdc3c5be 185 struct resource *sc_res[2];
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186 const struct agp_i810_match *match;
187 int sc_flush_page_rid;
188 struct resource *sc_flush_page_res;
189 void *sc_flush_page_vaddr;
190 int sc_bios_allocated_flush_page;
191};
192
193static device_t intel_agp;
194
195struct agp_i810_driver {
196 int chiptype;
197 int gen;
198 int busdma_addr_mask_sz;
199 struct resource_spec *res_spec;
200 int (*check_active)(device_t);
201 void (*set_desc)(device_t, const struct agp_i810_match *);
202 void (*dump_regs)(device_t);
203 int (*get_stolen_size)(device_t);
204 int (*get_gtt_total_entries)(device_t);
205 int (*get_gtt_mappable_entries)(device_t);
206 int (*install_gatt)(device_t);
207 void (*deinstall_gatt)(device_t);
208 void (*write_gtt)(device_t, u_int, uint32_t);
209 void (*install_gtt_pte)(device_t, u_int, vm_offset_t, int);
09d2c144 210 void (*sync_gtt_pte)(device_t, u_int);
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211 int (*set_aperture)(device_t, u_int32_t);
212 int (*chipset_flush_setup)(device_t);
213 void (*chipset_flush_teardown)(device_t);
214 void (*chipset_flush)(device_t);
215};
216
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217static struct {
218 struct intel_gtt base;
219} intel_private;
220
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221static const struct agp_i810_driver agp_i810_i915_driver = {
222 .chiptype = CHIP_I915,
223 .gen = 3,
224 .busdma_addr_mask_sz = 32,
225 .res_spec = agp_i915_res_spec,
226 .check_active = agp_i915_check_active,
227 .set_desc = agp_i810_set_desc,
228 .dump_regs = agp_i915_dump_regs,
229 .get_stolen_size = agp_i915_get_stolen_size,
230 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
231 .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
232 .install_gatt = agp_i830_install_gatt,
233 .deinstall_gatt = agp_i830_deinstall_gatt,
234 .write_gtt = agp_i915_write_gtt,
235 .install_gtt_pte = agp_i915_install_gtt_pte,
09d2c144 236 .sync_gtt_pte = agp_i915_sync_gtt_pte,
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237 .set_aperture = agp_i915_set_aperture,
238 .chipset_flush_setup = agp_i915_chipset_flush_setup,
239 .chipset_flush_teardown = agp_i915_chipset_flush_teardown,
240 .chipset_flush = agp_i915_chipset_flush,
241};
242
243static const struct agp_i810_driver agp_i810_g965_driver = {
244 .chiptype = CHIP_I965,
245 .gen = 4,
246 .busdma_addr_mask_sz = 36,
247 .res_spec = agp_i965_res_spec,
248 .check_active = agp_i915_check_active,
249 .set_desc = agp_i810_set_desc,
250 .dump_regs = agp_i965_dump_regs,
251 .get_stolen_size = agp_i915_get_stolen_size,
252 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
253 .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
254 .install_gatt = agp_i830_install_gatt,
255 .deinstall_gatt = agp_i830_deinstall_gatt,
256 .write_gtt = agp_i965_write_gtt,
257 .install_gtt_pte = agp_i965_install_gtt_pte,
09d2c144 258 .sync_gtt_pte = agp_i965_sync_gtt_pte,
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259 .set_aperture = agp_i915_set_aperture,
260 .chipset_flush_setup = agp_i965_chipset_flush_setup,
261 .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
262 .chipset_flush = agp_i915_chipset_flush,
263};
264
265static const struct agp_i810_driver agp_i810_g33_driver = {
266 .chiptype = CHIP_G33,
267 .gen = 3,
268 .busdma_addr_mask_sz = 36,
269 .res_spec = agp_i915_res_spec,
270 .check_active = agp_i915_check_active,
271 .set_desc = agp_i810_set_desc,
272 .dump_regs = agp_i965_dump_regs,
273 .get_stolen_size = agp_i915_get_stolen_size,
274 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
275 .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
276 .install_gatt = agp_i830_install_gatt,
277 .deinstall_gatt = agp_i830_deinstall_gatt,
278 .write_gtt = agp_i915_write_gtt,
99e9e211 279 .install_gtt_pte = agp_i965_install_gtt_pte,
09d2c144 280 .sync_gtt_pte = agp_i915_sync_gtt_pte,
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281 .set_aperture = agp_i915_set_aperture,
282 .chipset_flush_setup = agp_i965_chipset_flush_setup,
283 .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
284 .chipset_flush = agp_i915_chipset_flush,
285};
286
99e9e211 287static const struct agp_i810_driver pineview_gtt_driver = {
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288 .chiptype = CHIP_IGD,
289 .gen = 3,
290 .busdma_addr_mask_sz = 36,
291 .res_spec = agp_i915_res_spec,
292 .check_active = agp_i915_check_active,
293 .set_desc = agp_i810_set_desc,
294 .dump_regs = agp_i915_dump_regs,
295 .get_stolen_size = agp_i915_get_stolen_size,
296 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
297 .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
298 .install_gatt = agp_i830_install_gatt,
299 .deinstall_gatt = agp_i830_deinstall_gatt,
300 .write_gtt = agp_i915_write_gtt,
99e9e211 301 .install_gtt_pte = agp_i965_install_gtt_pte,
09d2c144 302 .sync_gtt_pte = agp_i915_sync_gtt_pte,
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303 .set_aperture = agp_i915_set_aperture,
304 .chipset_flush_setup = agp_i965_chipset_flush_setup,
305 .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
306 .chipset_flush = agp_i915_chipset_flush,
307};
308
309static const struct agp_i810_driver agp_i810_g4x_driver = {
310 .chiptype = CHIP_G4X,
311 .gen = 5,
312 .busdma_addr_mask_sz = 36,
313 .res_spec = agp_i965_res_spec,
314 .check_active = agp_i915_check_active,
315 .set_desc = agp_i810_set_desc,
316 .dump_regs = agp_i965_dump_regs,
317 .get_stolen_size = agp_i915_get_stolen_size,
318 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
319 .get_gtt_total_entries = agp_gen5_get_gtt_total_entries,
320 .install_gatt = agp_i830_install_gatt,
321 .deinstall_gatt = agp_i830_deinstall_gatt,
322 .write_gtt = agp_g4x_write_gtt,
323 .install_gtt_pte = agp_g4x_install_gtt_pte,
09d2c144 324 .sync_gtt_pte = agp_g4x_sync_gtt_pte,
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325 .set_aperture = agp_i915_set_aperture,
326 .chipset_flush_setup = agp_i965_chipset_flush_setup,
327 .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
328 .chipset_flush = agp_i915_chipset_flush,
329};
330
331static const struct agp_i810_driver agp_i810_sb_driver = {
332 .chiptype = CHIP_SB,
333 .gen = 6,
334 .busdma_addr_mask_sz = 40,
335 .res_spec = agp_g4x_res_spec,
336 .check_active = agp_sb_check_active,
337 .set_desc = agp_i810_set_desc,
338 .dump_regs = agp_sb_dump_regs,
339 .get_stolen_size = agp_sb_get_stolen_size,
340 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
341 .get_gtt_total_entries = agp_sb_get_gtt_total_entries,
342 .install_gatt = agp_i830_install_gatt,
343 .deinstall_gatt = agp_i830_deinstall_gatt,
344 .write_gtt = agp_sb_write_gtt,
345 .install_gtt_pte = agp_sb_install_gtt_pte,
09d2c144 346 .sync_gtt_pte = agp_g4x_sync_gtt_pte,
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347 .set_aperture = agp_i915_set_aperture,
348 .chipset_flush_setup = agp_i810_chipset_flush_setup,
349 .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
350 .chipset_flush = agp_i810_chipset_flush,
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351};
352
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353static const struct agp_i810_driver valleyview_gtt_driver = {
354 .chiptype = CHIP_SB,
355 .gen = 7,
356 .busdma_addr_mask_sz = 40,
357 .res_spec = agp_g4x_res_spec,
358 .check_active = agp_sb_check_active,
359 .set_desc = agp_i810_set_desc,
360 .dump_regs = agp_sb_dump_regs,
361 .get_stolen_size = agp_sb_get_stolen_size,
362 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
363 .get_gtt_total_entries = agp_sb_get_gtt_total_entries,
364 .install_gatt = agp_i830_install_gatt,
365 .deinstall_gatt = agp_i830_deinstall_gatt,
366 .write_gtt = agp_sb_write_gtt,
367 .install_gtt_pte = agp_sb_install_gtt_pte,
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368 .sync_gtt_pte = agp_g4x_sync_gtt_pte,
369 .set_aperture = agp_i915_set_aperture,
370 .chipset_flush_setup = agp_i810_chipset_flush_setup,
371 .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
372 .chipset_flush = agp_i810_chipset_flush,
373};
374
375static const struct agp_i810_driver broadwell_gtt_driver = {
376 .chiptype = CHIP_SB,
377 .gen = 8,
378 .busdma_addr_mask_sz = 40,
379 .res_spec = agp_g4x_res_spec,
380 .check_active = agp_sb_check_active,
381 .set_desc = agp_i810_set_desc,
382 .dump_regs = agp_sb_dump_regs,
383 .get_stolen_size = agp_gen8_get_stolen_size,
384 .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
385 .get_gtt_total_entries = agp_gen8_get_gtt_total_entries,
386 .install_gatt = agp_i830_install_gatt,
387 .deinstall_gatt = agp_i830_deinstall_gatt,
388 .write_gtt = NULL,
389 .install_gtt_pte = agp_gen8_install_gtt_pte,
390 .sync_gtt_pte = agp_g4x_sync_gtt_pte,
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391 .set_aperture = agp_i915_set_aperture,
392 .chipset_flush_setup = agp_i810_chipset_flush_setup,
393 .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
394 .chipset_flush = agp_i810_chipset_flush,
395};
396
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397/* For adding new devices, devid is the id of the graphics controller
398 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
399 * second head should never be added. The bridge_offset is the offset to
400 * subtract from devid to get the id of the hostb that the device is on.
401 */
402static const struct agp_i810_match {
8d36a65a 403 uint16_t devid;
fdc3c5be 404 char *name;
a904aa53 405 const struct agp_i810_driver *driver;
fdc3c5be 406} agp_i810_matches[] = {
a904aa53 407 {
31d142df 408 .devid = 0x2582,
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409 .name = "Intel 82915G (915G GMCH) SVGA controller",
410 .driver = &agp_i810_i915_driver
411 },
412 {
31d142df 413 .devid = 0x258A,
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414 .name = "Intel E7221 SVGA controller",
415 .driver = &agp_i810_i915_driver
416 },
417 {
31d142df 418 .devid = 0x2592,
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419 .name = "Intel 82915GM (915GM GMCH) SVGA controller",
420 .driver = &agp_i810_i915_driver
421 },
422 {
31d142df 423 .devid = 0x2772,
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424 .name = "Intel 82945G (945G GMCH) SVGA controller",
425 .driver = &agp_i810_i915_driver
426 },
427 {
31d142df 428 .devid = 0x27A2,
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429 .name = "Intel 82945GM (945GM GMCH) SVGA controller",
430 .driver = &agp_i810_i915_driver
431 },
432 {
31d142df 433 .devid = 0x27AE,
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434 .name = "Intel 945GME SVGA controller",
435 .driver = &agp_i810_i915_driver
436 },
437 {
31d142df 438 .devid = 0x2972,
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439 .name = "Intel 946GZ SVGA controller",
440 .driver = &agp_i810_g965_driver
441 },
442 {
31d142df 443 .devid = 0x2982,
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FT
444 .name = "Intel G965 SVGA controller",
445 .driver = &agp_i810_g965_driver
446 },
447 {
31d142df 448 .devid = 0x2992,
a904aa53
FT
449 .name = "Intel Q965 SVGA controller",
450 .driver = &agp_i810_g965_driver
451 },
452 {
31d142df 453 .devid = 0x29A2,
a904aa53
FT
454 .name = "Intel G965 SVGA controller",
455 .driver = &agp_i810_g965_driver
456 },
457 {
31d142df 458 .devid = 0x29B2,
a904aa53
FT
459 .name = "Intel Q35 SVGA controller",
460 .driver = &agp_i810_g33_driver
461 },
462 {
31d142df 463 .devid = 0x29C2,
a904aa53
FT
464 .name = "Intel G33 SVGA controller",
465 .driver = &agp_i810_g33_driver
466 },
467 {
31d142df 468 .devid = 0x29D2,
a904aa53
FT
469 .name = "Intel Q33 SVGA controller",
470 .driver = &agp_i810_g33_driver
471 },
472 {
31d142df 473 .devid = 0xA001,
a904aa53 474 .name = "Intel Pineview SVGA controller",
99e9e211 475 .driver = &pineview_gtt_driver
a904aa53
FT
476 },
477 {
31d142df 478 .devid = 0xA011,
a904aa53 479 .name = "Intel Pineview (M) SVGA controller",
99e9e211 480 .driver = &pineview_gtt_driver
a904aa53
FT
481 },
482 {
31d142df 483 .devid = 0x2A02,
a904aa53
FT
484 .name = "Intel GM965 SVGA controller",
485 .driver = &agp_i810_g965_driver
486 },
487 {
31d142df 488 .devid = 0x2A12,
a904aa53
FT
489 .name = "Intel GME965 SVGA controller",
490 .driver = &agp_i810_g965_driver
491 },
492 {
31d142df 493 .devid = 0x2A42,
a904aa53
FT
494 .name = "Intel GM45 SVGA controller",
495 .driver = &agp_i810_g4x_driver
496 },
497 {
31d142df 498 .devid = 0x2E02,
a904aa53
FT
499 .name = "Intel Eaglelake SVGA controller",
500 .driver = &agp_i810_g4x_driver
501 },
502 {
31d142df 503 .devid = 0x2E12,
a904aa53
FT
504 .name = "Intel Q45 SVGA controller",
505 .driver = &agp_i810_g4x_driver
506 },
507 {
31d142df 508 .devid = 0x2E22,
a904aa53
FT
509 .name = "Intel G45 SVGA controller",
510 .driver = &agp_i810_g4x_driver
511 },
512 {
31d142df 513 .devid = 0x2E32,
a904aa53
FT
514 .name = "Intel G41 SVGA controller",
515 .driver = &agp_i810_g4x_driver
516 },
517 {
31d142df 518 .devid = 0x0042,
a904aa53
FT
519 .name = "Intel Ironlake (D) SVGA controller",
520 .driver = &agp_i810_g4x_driver
521 },
522 {
31d142df 523 .devid = 0x0046,
a904aa53
FT
524 .name = "Intel Ironlake (M) SVGA controller",
525 .driver = &agp_i810_g4x_driver
526 },
527 {
31d142df 528 .devid = 0x0102,
a904aa53
FT
529 .name = "SandyBridge desktop GT1 IG",
530 .driver = &agp_i810_sb_driver
531 },
532 {
31d142df 533 .devid = 0x0112,
a904aa53
FT
534 .name = "SandyBridge desktop GT2 IG",
535 .driver = &agp_i810_sb_driver
536 },
537 {
31d142df 538 .devid = 0x0122,
a904aa53
FT
539 .name = "SandyBridge desktop GT2+ IG",
540 .driver = &agp_i810_sb_driver
541 },
542 {
31d142df 543 .devid = 0x0106,
a904aa53
FT
544 .name = "SandyBridge mobile GT1 IG",
545 .driver = &agp_i810_sb_driver
546 },
547 {
31d142df 548 .devid = 0x0116,
a904aa53
FT
549 .name = "SandyBridge mobile GT2 IG",
550 .driver = &agp_i810_sb_driver
551 },
552 {
31d142df 553 .devid = 0x0126,
a904aa53
FT
554 .name = "SandyBridge mobile GT2+ IG",
555 .driver = &agp_i810_sb_driver
556 },
557 {
31d142df 558 .devid = 0x010a,
a904aa53
FT
559 .name = "SandyBridge server IG",
560 .driver = &agp_i810_sb_driver
561 },
562 {
31d142df 563 .devid = 0x0152,
a904aa53
FT
564 .name = "IvyBridge desktop GT1 IG",
565 .driver = &agp_i810_sb_driver
566 },
567 {
31d142df 568 .devid = 0x0162,
a904aa53
FT
569 .name = "IvyBridge desktop GT2 IG",
570 .driver = &agp_i810_sb_driver
571 },
572 {
31d142df 573 .devid = 0x0156,
a904aa53
FT
574 .name = "IvyBridge mobile GT1 IG",
575 .driver = &agp_i810_sb_driver
576 },
577 {
31d142df 578 .devid = 0x0166,
a904aa53
FT
579 .name = "IvyBridge mobile GT2 IG",
580 .driver = &agp_i810_sb_driver
581 },
582 {
31d142df 583 .devid = 0x015a,
a904aa53
FT
584 .name = "IvyBridge server GT1 IG",
585 .driver = &agp_i810_sb_driver
586 },
246f9ec5 587 {
31d142df 588 .devid = 0x016a,
246f9ec5
FT
589 .name = "IvyBridge server GT2 IG",
590 .driver = &agp_i810_sb_driver
591 },
8d36a65a
FT
592 {
593 .devid = 0x0f30,
594 .name = "ValleyView",
595 .driver = &valleyview_gtt_driver
596 },
597 {
598 .devid = 0x0402,
599 .name = "Haswell desktop GT1 IG",
600 .driver = &agp_i810_sb_driver
601 },
602 {
603 .devid = 0x0412,
604 .name = "Haswell desktop GT2 IG",
605 .driver = &agp_i810_sb_driver
606 },
bb66151c 607 { 0x041e, "Haswell", &agp_i810_sb_driver },
cf614546 608 { 0x0422, "Haswell", &agp_i810_sb_driver },
8d36a65a
FT
609 {
610 .devid = 0x0406,
611 .name = "Haswell mobile GT1 IG",
612 .driver = &agp_i810_sb_driver
613 },
614 {
615 .devid = 0x0416,
616 .name = "Haswell mobile GT2 IG",
617 .driver = &agp_i810_sb_driver
618 },
cf614546 619 { 0x0426, "Haswell", &agp_i810_sb_driver },
8d36a65a
FT
620 {
621 .devid = 0x040a,
622 .name = "Haswell server GT1 IG",
623 .driver = &agp_i810_sb_driver
624 },
625 {
626 .devid = 0x041a,
627 .name = "Haswell server GT2 IG",
628 .driver = &agp_i810_sb_driver
629 },
cf614546
FT
630 { 0x042a, "Haswell", &agp_i810_sb_driver },
631 { 0x0c02, "Haswell", &agp_i810_sb_driver },
632 { 0x0c12, "Haswell", &agp_i810_sb_driver },
633 { 0x0c22, "Haswell", &agp_i810_sb_driver },
634 { 0x0c06, "Haswell", &agp_i810_sb_driver },
8d36a65a
FT
635 {
636 .devid = 0x0c16,
637 .name = "Haswell SDV",
638 .driver = &agp_i810_sb_driver
639 },
cf614546
FT
640 { 0x0c26, "Haswell", &agp_i810_sb_driver },
641 { 0x0c0a, "Haswell", &agp_i810_sb_driver },
642 { 0x0c1a, "Haswell", &agp_i810_sb_driver },
643 { 0x0c2a, "Haswell", &agp_i810_sb_driver },
644 { 0x0a02, "Haswell", &agp_i810_sb_driver },
645 { 0x0a12, "Haswell", &agp_i810_sb_driver },
646 { 0x0a22, "Haswell", &agp_i810_sb_driver },
647 { 0x0a06, "Haswell", &agp_i810_sb_driver },
648 { 0x0a16, "Haswell", &agp_i810_sb_driver },
649 { 0x0a26, "Haswell", &agp_i810_sb_driver },
650 { 0x0a0a, "Haswell", &agp_i810_sb_driver },
651 { 0x0a1a, "Haswell", &agp_i810_sb_driver },
652 { 0x0a2a, "Haswell", &agp_i810_sb_driver },
653 { 0x0d12, "Haswell", &agp_i810_sb_driver },
654 { 0x0d22, "Haswell", &agp_i810_sb_driver },
655 { 0x0d32, "Haswell", &agp_i810_sb_driver },
656 { 0x0d16, "Haswell", &agp_i810_sb_driver },
657 { 0x0d26, "Haswell", &agp_i810_sb_driver },
658 { 0x0d36, "Haswell", &agp_i810_sb_driver },
659 { 0x0d1a, "Haswell", &agp_i810_sb_driver },
660 { 0x0d2a, "Haswell", &agp_i810_sb_driver },
661 { 0x0d3a, "Haswell", &agp_i810_sb_driver },
09d2c144
MD
662
663 { 0x1602, "Broadwell", &broadwell_gtt_driver }, /* m */
664 { 0x1606, "Broadwell", &broadwell_gtt_driver },
665 { 0x160B, "Broadwell", &broadwell_gtt_driver },
666 { 0x160E, "Broadwell", &broadwell_gtt_driver },
667 { 0x1616, "Broadwell", &broadwell_gtt_driver },
b12129b5 668 { 0x161E, "Broadwell", &broadwell_gtt_driver },
09d2c144
MD
669
670 { 0x160A, "Broadwell", &broadwell_gtt_driver }, /* d */
671 { 0x160D, "Broadwell", &broadwell_gtt_driver },
a904aa53
FT
672 {
673 .devid = 0,
674 }
984263bc
MD
675};
676
fdc3c5be 677static const struct agp_i810_match*
984263bc
MD
678agp_i810_match(device_t dev)
679{
fdc3c5be
HT
680 int i, devid;
681
31d142df 682 if (pci_get_vendor(dev) != PCI_VENDOR_INTEL)
a904aa53 683 return (NULL);
984263bc 684
26b66f28 685 devid = pci_get_device(dev);
fdc3c5be
HT
686 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
687 if (agp_i810_matches[i].devid == devid)
a904aa53 688 break;
fdc3c5be
HT
689 }
690 if (agp_i810_matches[i].devid == 0)
a904aa53 691 return (NULL);
fdc3c5be 692 else
a904aa53 693 return (&agp_i810_matches[i]);
984263bc
MD
694}
695
696/*
697 * Find bridge device.
698 */
699static device_t
700agp_i810_find_bridge(device_t dev)
701{
984263bc 702
a904aa53 703 return (pci_find_dbsf(0, 0, 0, 0));
984263bc
MD
704}
705
fdc3c5be
HT
706static void
707agp_i810_identify(driver_t *driver, device_t parent)
708{
709
710 if (device_find_child(parent, "agp", -1) == NULL &&
711 agp_i810_match(parent))
712 device_add_child(parent, "agp", -1);
713}
714
a904aa53
FT
715static int
716agp_i915_check_active(device_t bridge_dev)
717{
718 int deven;
719
720 deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4);
721 if ((deven & AGP_I915_DEVEN_D2F0) == AGP_I915_DEVEN_D2F0_DISABLED)
722 return (ENXIO);
723 return (0);
724}
725
726static int
727agp_sb_check_active(device_t bridge_dev)
728{
729 int deven;
730
731 deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4);
732 if ((deven & AGP_SB_DEVEN_D2EN) == AGP_SB_DEVEN_D2EN_DISABLED)
733 return (ENXIO);
734 return (0);
735}
736
a904aa53
FT
737static void
738agp_i810_set_desc(device_t dev, const struct agp_i810_match *match)
739{
740
741 device_set_desc(dev, match->name);
742}
743
984263bc
MD
744static int
745agp_i810_probe(device_t dev)
746{
fdc3c5be
HT
747 device_t bdev;
748 const struct agp_i810_match *match;
a904aa53 749 int err;
fdc3c5be
HT
750
751 if (resource_disabled("agp", device_get_unit(dev)))
752 return (ENXIO);
753 match = agp_i810_match(dev);
754 if (match == NULL)
a904aa53 755 return (ENXIO);
984263bc 756
fdc3c5be 757 bdev = agp_i810_find_bridge(dev);
a904aa53 758 if (bdev == NULL) {
fdc3c5be
HT
759 if (bootverbose)
760 kprintf("I810: can't find bridge device\n");
a904aa53 761 return (ENXIO);
fdc3c5be 762 }
984263bc 763
fdc3c5be
HT
764 /*
765 * checking whether internal graphics device has been activated.
766 */
a904aa53
FT
767 err = match->driver->check_active(bdev);
768 if (err != 0) {
769 if (bootverbose)
770 kprintf("i810: disabled, not probing\n");
771 return (err);
984263bc
MD
772 }
773
a904aa53
FT
774 match->driver->set_desc(dev, match);
775 return (BUS_PROBE_DEFAULT);
fdc3c5be
HT
776}
777
a904aa53
FT
778static void
779agp_i915_dump_regs(device_t dev)
780{
781 struct agp_i810_softc *sc = device_get_softc(dev);
984263bc 782
a904aa53
FT
783 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
784 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
785 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
786 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
787 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
788 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
789}
fdc3c5be 790
a904aa53
FT
791static void
792agp_i965_dump_regs(device_t dev)
793{
794 struct agp_i810_softc *sc = device_get_softc(dev);
984263bc 795
a904aa53
FT
796 device_printf(dev, "AGP_I965_PGTBL_CTL2: %08x\n",
797 bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2));
798 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
799 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
800 device_printf(dev, "AGP_I965_MSAC: 0x%02x\n",
801 pci_read_config(sc->bdev, AGP_I965_MSAC, 1));
802}
fdc3c5be 803
a904aa53
FT
804static void
805agp_sb_dump_regs(device_t dev)
806{
807 struct agp_i810_softc *sc = device_get_softc(dev);
984263bc 808
a904aa53
FT
809 device_printf(dev, "AGP_SNB_GFX_MODE: %08x\n",
810 bus_read_4(sc->sc_res[0], AGP_SNB_GFX_MODE));
811 device_printf(dev, "AGP_SNB_GCC1: 0x%04x\n",
812 pci_read_config(sc->bdev, AGP_SNB_GCC1, 2));
813}
814
a904aa53
FT
815static int
816agp_i915_get_stolen_size(device_t dev)
817{
818 struct agp_i810_softc *sc;
819 unsigned int gcc1, stolen, gtt_size;
984263bc 820
a904aa53 821 sc = device_get_softc(dev);
fdc3c5be 822
a904aa53
FT
823 /*
824 * Stolen memory is set up at the beginning of the aperture by
825 * the BIOS, consisting of the GATT followed by 4kb for the
826 * BIOS display.
827 */
828 switch (sc->match->driver->chiptype) {
829 case CHIP_I855:
830 gtt_size = 128;
831 break;
832 case CHIP_I915:
833 gtt_size = 256;
834 break;
835 case CHIP_I965:
836 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
837 AGP_I810_PGTBL_SIZE_MASK) {
838 case AGP_I810_PGTBL_SIZE_128KB:
fdc3c5be
HT
839 gtt_size = 128;
840 break;
a904aa53 841 case AGP_I810_PGTBL_SIZE_256KB:
fdc3c5be
HT
842 gtt_size = 256;
843 break;
a904aa53
FT
844 case AGP_I810_PGTBL_SIZE_512KB:
845 gtt_size = 512;
f16c0bab 846 break;
a904aa53
FT
847 case AGP_I965_PGTBL_SIZE_1MB:
848 gtt_size = 1024;
fdc3c5be 849 break;
a904aa53
FT
850 case AGP_I965_PGTBL_SIZE_2MB:
851 gtt_size = 2048;
852 break;
853 case AGP_I965_PGTBL_SIZE_1_5MB:
854 gtt_size = 1024 + 512;
f16c0bab 855 break;
fdc3c5be 856 default:
a904aa53
FT
857 device_printf(dev, "Bad PGTBL size\n");
858 return (EINVAL);
fdc3c5be 859 }
a904aa53
FT
860 break;
861 case CHIP_G33:
862 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
863 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
864 case AGP_G33_MGGC_GGMS_SIZE_1M:
865 gtt_size = 1024;
f16c0bab 866 break;
a904aa53
FT
867 case AGP_G33_MGGC_GGMS_SIZE_2M:
868 gtt_size = 2048;
ab5a0ec8
MD
869 break;
870 default:
a904aa53
FT
871 device_printf(dev, "Bad PGTBL size\n");
872 return (EINVAL);
ab5a0ec8 873 }
a904aa53
FT
874 break;
875 case CHIP_IGD:
876 case CHIP_G4X:
877 gtt_size = 0;
878 break;
879 default:
880 device_printf(dev, "Bad chiptype\n");
881 return (EINVAL);
882 }
f16c0bab 883
a904aa53
FT
884 /* GCC1 is called MGGC on i915+ */
885 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
886 switch (gcc1 & AGP_I855_GCC1_GMS) {
887 case AGP_I855_GCC1_GMS_STOLEN_1M:
888 stolen = 1024;
889 break;
890 case AGP_I855_GCC1_GMS_STOLEN_4M:
891 stolen = 4 * 1024;
892 break;
893 case AGP_I855_GCC1_GMS_STOLEN_8M:
894 stolen = 8 * 1024;
895 break;
896 case AGP_I855_GCC1_GMS_STOLEN_16M:
897 stolen = 16 * 1024;
898 break;
899 case AGP_I855_GCC1_GMS_STOLEN_32M:
900 stolen = 32 * 1024;
901 break;
902 case AGP_I915_GCC1_GMS_STOLEN_48M:
903 stolen = sc->match->driver->gen > 2 ? 48 * 1024 : 0;
904 break;
905 case AGP_I915_GCC1_GMS_STOLEN_64M:
906 stolen = sc->match->driver->gen > 2 ? 64 * 1024 : 0;
907 break;
908 case AGP_G33_GCC1_GMS_STOLEN_128M:
909 stolen = sc->match->driver->gen > 2 ? 128 * 1024 : 0;
910 break;
911 case AGP_G33_GCC1_GMS_STOLEN_256M:
912 stolen = sc->match->driver->gen > 2 ? 256 * 1024 : 0;
913 break;
914 case AGP_G4X_GCC1_GMS_STOLEN_96M:
915 if (sc->match->driver->chiptype == CHIP_I965 ||
916 sc->match->driver->chiptype == CHIP_G4X)
917 stolen = 96 * 1024;
918 else
919 stolen = 0;
920 break;
921 case AGP_G4X_GCC1_GMS_STOLEN_160M:
922 if (sc->match->driver->chiptype == CHIP_I965 ||
923 sc->match->driver->chiptype == CHIP_G4X)
924 stolen = 160 * 1024;
925 else
926 stolen = 0;
927 break;
928 case AGP_G4X_GCC1_GMS_STOLEN_224M:
929 if (sc->match->driver->chiptype == CHIP_I965 ||
930 sc->match->driver->chiptype == CHIP_G4X)
931 stolen = 224 * 1024;
932 else
933 stolen = 0;
934 break;
935 case AGP_G4X_GCC1_GMS_STOLEN_352M:
936 if (sc->match->driver->chiptype == CHIP_I965 ||
937 sc->match->driver->chiptype == CHIP_G4X)
938 stolen = 352 * 1024;
939 else
940 stolen = 0;
941 break;
942 default:
943 device_printf(dev,
944 "unknown memory configuration, disabling (GCC1 %x)\n",
945 gcc1);
946 return (EINVAL);
947 }
f16c0bab 948
a904aa53
FT
949 gtt_size += 4;
950 sc->stolen_size = stolen * 1024;
951 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
984263bc 952
a904aa53
FT
953 return (0);
954}
ab5a0ec8 955
a904aa53
FT
956static int
957agp_sb_get_stolen_size(device_t dev)
958{
959 struct agp_i810_softc *sc;
960 uint16_t gmch_ctl;
961
962 sc = device_get_softc(dev);
963 gmch_ctl = pci_read_config(sc->bdev, AGP_SNB_GCC1, 2);
964 switch (gmch_ctl & AGP_SNB_GMCH_GMS_STOLEN_MASK) {
965 case AGP_SNB_GMCH_GMS_STOLEN_32M:
966 sc->stolen_size = 32 * 1024 * 1024;
967 break;
968 case AGP_SNB_GMCH_GMS_STOLEN_64M:
969 sc->stolen_size = 64 * 1024 * 1024;
970 break;
971 case AGP_SNB_GMCH_GMS_STOLEN_96M:
972 sc->stolen_size = 96 * 1024 * 1024;
973 break;
974 case AGP_SNB_GMCH_GMS_STOLEN_128M:
975 sc->stolen_size = 128 * 1024 * 1024;
976 break;
977 case AGP_SNB_GMCH_GMS_STOLEN_160M:
978 sc->stolen_size = 160 * 1024 * 1024;
979 break;
980 case AGP_SNB_GMCH_GMS_STOLEN_192M:
981 sc->stolen_size = 192 * 1024 * 1024;
982 break;
983 case AGP_SNB_GMCH_GMS_STOLEN_224M:
984 sc->stolen_size = 224 * 1024 * 1024;
985 break;
986 case AGP_SNB_GMCH_GMS_STOLEN_256M:
987 sc->stolen_size = 256 * 1024 * 1024;
988 break;
989 case AGP_SNB_GMCH_GMS_STOLEN_288M:
990 sc->stolen_size = 288 * 1024 * 1024;
991 break;
992 case AGP_SNB_GMCH_GMS_STOLEN_320M:
993 sc->stolen_size = 320 * 1024 * 1024;
994 break;
995 case AGP_SNB_GMCH_GMS_STOLEN_352M:
996 sc->stolen_size = 352 * 1024 * 1024;
997 break;
998 case AGP_SNB_GMCH_GMS_STOLEN_384M:
999 sc->stolen_size = 384 * 1024 * 1024;
1000 break;
1001 case AGP_SNB_GMCH_GMS_STOLEN_416M:
1002 sc->stolen_size = 416 * 1024 * 1024;
1003 break;
1004 case AGP_SNB_GMCH_GMS_STOLEN_448M:
1005 sc->stolen_size = 448 * 1024 * 1024;
1006 break;
1007 case AGP_SNB_GMCH_GMS_STOLEN_480M:
1008 sc->stolen_size = 480 * 1024 * 1024;
1009 break;
1010 case AGP_SNB_GMCH_GMS_STOLEN_512M:
1011 sc->stolen_size = 512 * 1024 * 1024;
1012 break;
fdc3c5be 1013 }
a904aa53
FT
1014 sc->stolen = (sc->stolen_size - 4) / 4096;
1015 return (0);
1016}
1017
09d2c144
MD
1018static int
1019agp_gen8_get_stolen_size(device_t dev)
1020{
1021 struct agp_i810_softc *sc;
1022 uint16_t gcc1;
1023 int v;
1024
1025 sc = device_get_softc(dev);
1026 gcc1 = pci_read_config(sc->bdev, AGP_SNB_GCC1, 2);
1027 v = (gcc1 >> 8) & 0xFF;
1028 sc->stolen_size = v * (32L * 1024 * 1024); /* 32MB increments */
1029 kprintf("GTT STOLEN %ld\n", (long)sc->stolen_size);
1030
1031 return 0;
1032}
1033
a904aa53
FT
1034static int
1035agp_i915_get_gtt_mappable_entries(device_t dev)
1036{
1037 struct agp_i810_softc *sc;
1038 uint32_t ap;
1039
1040 sc = device_get_softc(dev);
1041 ap = AGP_GET_APERTURE(dev);
1042 sc->gtt_mappable_entries = ap >> AGP_PAGE_SHIFT;
1043 return (0);
1044}
1045
1046static int
1047agp_i810_get_gtt_total_entries(device_t dev)
1048{
1049 struct agp_i810_softc *sc;
1050
1051 sc = device_get_softc(dev);
1052 sc->gtt_total_entries = sc->gtt_mappable_entries;
1053 return (0);
1054}
fdc3c5be 1055
a904aa53
FT
1056static int
1057agp_i965_get_gtt_total_entries(device_t dev)
1058{
1059 struct agp_i810_softc *sc;
1060 uint32_t pgetbl_ctl;
1061 int error;
1062
1063 sc = device_get_softc(dev);
1064 error = 0;
1065 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1066 switch (pgetbl_ctl & AGP_I810_PGTBL_SIZE_MASK) {
1067 case AGP_I810_PGTBL_SIZE_128KB:
1068 sc->gtt_total_entries = 128 * 1024 / 4;
1069 break;
1070 case AGP_I810_PGTBL_SIZE_256KB:
1071 sc->gtt_total_entries = 256 * 1024 / 4;
1072 break;
1073 case AGP_I810_PGTBL_SIZE_512KB:
1074 sc->gtt_total_entries = 512 * 1024 / 4;
1075 break;
1076 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
1077 case AGP_I810_PGTBL_SIZE_1MB:
1078 sc->gtt_total_entries = 1024 * 1024 / 4;
1079 break;
1080 case AGP_I810_PGTBL_SIZE_2MB:
1081 sc->gtt_total_entries = 2 * 1024 * 1024 / 4;
1082 break;
1083 case AGP_I810_PGTBL_SIZE_1_5MB:
1084 sc->gtt_total_entries = (1024 + 512) * 1024 / 4;
1085 break;
1086 default:
1087 device_printf(dev, "Unknown page table size\n");
1088 error = ENXIO;
1089 }
1090 return (error);
1091}
1092
1093static void
1094agp_gen5_adjust_pgtbl_size(device_t dev, uint32_t sz)
1095{
1096 struct agp_i810_softc *sc;
1097 uint32_t pgetbl_ctl, pgetbl_ctl2;
1098
1099 sc = device_get_softc(dev);
1100
1101 /* Disable per-process page table. */
1102 pgetbl_ctl2 = bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2);
1103 pgetbl_ctl2 &= ~AGP_I810_PGTBL_ENABLED;
1104 bus_write_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2, pgetbl_ctl2);
1105
1106 /* Write the new ggtt size. */
1107 pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1108 pgetbl_ctl &= ~AGP_I810_PGTBL_SIZE_MASK;
1109 pgetbl_ctl |= sz;
1110 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgetbl_ctl);
1111}
1112
1113static int
1114agp_gen5_get_gtt_total_entries(device_t dev)
1115{
1116 struct agp_i810_softc *sc;
1117 uint16_t gcc1;
1118
1119 sc = device_get_softc(dev);
1120
1121 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1122 switch (gcc1 & AGP_G4x_GCC1_SIZE_MASK) {
1123 case AGP_G4x_GCC1_SIZE_1M:
1124 case AGP_G4x_GCC1_SIZE_VT_1M:
1125 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1MB);
1126 break;
1127 case AGP_G4x_GCC1_SIZE_VT_1_5M:
1128 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1_5MB);
1129 break;
1130 case AGP_G4x_GCC1_SIZE_2M:
1131 case AGP_G4x_GCC1_SIZE_VT_2M:
1132 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_2MB);
1133 break;
1134 default:
1135 device_printf(dev, "Unknown page table size\n");
1136 return (ENXIO);
1137 }
1138
1139 return (agp_i965_get_gtt_total_entries(dev));
1140}
1141
1142static int
1143agp_sb_get_gtt_total_entries(device_t dev)
1144{
1145 struct agp_i810_softc *sc;
1146 uint16_t gcc1;
1147
1148 sc = device_get_softc(dev);
1149
1150 gcc1 = pci_read_config(sc->bdev, AGP_SNB_GCC1, 2);
1151 switch (gcc1 & AGP_SNB_GTT_SIZE_MASK) {
1152 default:
1153 case AGP_SNB_GTT_SIZE_0M:
1154 kprintf("Bad GTT size mask: 0x%04x\n", gcc1);
1155 return (ENXIO);
1156 case AGP_SNB_GTT_SIZE_1M:
1157 sc->gtt_total_entries = 1024 * 1024 / 4;
1158 break;
1159 case AGP_SNB_GTT_SIZE_2M:
1160 sc->gtt_total_entries = 2 * 1024 * 1024 / 4;
1161 break;
1162 }
1163 return (0);
1164}
1165
09d2c144
MD
1166static int
1167agp_gen8_get_gtt_total_entries(device_t dev)
1168{
1169 struct agp_i810_softc *sc;
1170 uint16_t gcc1;
1171 int v;
1172
1173 sc = device_get_softc(dev);
1174
1175 gcc1 = pci_read_config(sc->bdev, AGP_SNB_GCC1, 2);
1176 v = (gcc1 >> 6) & 3;
1177 if (v)
1178 v = 1 << v;
1179 sc->gtt_total_entries = (v << 20) / 8;
1180
1181 /*
1182 * XXX limit to 2GB due to misc integer overflows calculated on
1183 * this field.
1184 */
1185 while ((long)sc->gtt_total_entries * PAGE_SIZE >= 4LL*1024*1024*1024)
1186 sc->gtt_total_entries >>= 1;
1187
1188 kprintf("GTT SIZE %ld representing %ldM vmap\n",
1189 (long)sc->gtt_total_entries * 8,
1190 (long)sc->gtt_total_entries * PAGE_SIZE);
1191
1192 return 0;
1193}
1194
a904aa53
FT
1195static int
1196agp_i830_install_gatt(device_t dev)
1197{
1198 struct agp_i810_softc *sc;
1199 uint32_t pgtblctl;
1200
1201 sc = device_get_softc(dev);
1202
1203 /*
1204 * The i830 automatically initializes the 128k gatt on boot.
1205 * GATT address is already in there, make sure it's enabled.
1206 */
1207 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1208 pgtblctl |= 1;
1209 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
1210
1211 sc->gatt->ag_physical = pgtblctl & ~1;
1212 return (0);
1213}
1214
1215static int
1216agp_i810_attach(device_t dev)
1217{
1218 struct agp_i810_softc *sc;
1219 int error;
1220
1221 sc = device_get_softc(dev);
1222 sc->bdev = agp_i810_find_bridge(dev);
1223 if (sc->bdev == NULL)
1224 return (ENOENT);
1225
1226 sc->match = agp_i810_match(dev);
1227
1228 agp_set_aperture_resource(dev, sc->match->driver->gen <= 2 ?
1229 AGP_APBASE : AGP_I915_GMADR);
1230 error = agp_generic_attach(dev);
1231 if (error)
1232 return (error);
1233
1234 if (ptoa((vm_paddr_t)Maxmem) >
1235 (1ULL << sc->match->driver->busdma_addr_mask_sz) - 1) {
1236 device_printf(dev, "agp_i810 does not support physical "
1237 "memory above %ju.\n", (uintmax_t)(1ULL <<
1238 sc->match->driver->busdma_addr_mask_sz) - 1);
1239 return (ENOENT);
1240 }
1241
1242 if (bus_alloc_resources(dev, sc->match->driver->res_spec, sc->sc_res)) {
1243 agp_generic_detach(dev);
1244 return (ENODEV);
1245 }
1246
1247 sc->initial_aperture = AGP_GET_APERTURE(dev);
1248 sc->gatt = kmalloc(sizeof(struct agp_gatt), M_AGP, M_WAITOK);
1249 sc->gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
1250
1251 if ((error = sc->match->driver->get_stolen_size(dev)) != 0 ||
1252 (error = sc->match->driver->install_gatt(dev)) != 0 ||
1253 (error = sc->match->driver->get_gtt_mappable_entries(dev)) != 0 ||
1254 (error = sc->match->driver->get_gtt_total_entries(dev)) != 0 ||
1255 (error = sc->match->driver->chipset_flush_setup(dev)) != 0) {
1256 bus_release_resources(dev, sc->match->driver->res_spec,
1257 sc->sc_res);
1258 kfree(sc->gatt, M_AGP);
1259 agp_generic_detach(dev);
1260 return (error);
1261 }
1262
1263 intel_agp = dev;
7f9ec87c
FT
1264 device_printf(dev, "aperture size is %dM",
1265 sc->initial_aperture / 1024 / 1024);
1266 if (sc->stolen > 0)
1267 kprintf(", detected %dk stolen memory\n", sc->stolen * 4);
1268 else
1269 kprintf("\n");
a904aa53
FT
1270 if (bootverbose) {
1271 sc->match->driver->dump_regs(dev);
1272 device_printf(dev, "Mappable GTT entries: %d\n",
1273 sc->gtt_mappable_entries);
1274 device_printf(dev, "Total GTT entries: %d\n",
1275 sc->gtt_total_entries);
1276 }
1277 return (0);
1278}
7f9ec87c 1279
a904aa53
FT
1280static void
1281agp_i830_deinstall_gatt(device_t dev)
1282{
1283 struct agp_i810_softc *sc;
1284 unsigned int pgtblctl;
1285
1286 sc = device_get_softc(dev);
1287 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1288 pgtblctl &= ~1;
1289 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
984263bc
MD
1290}
1291
1292static int
1293agp_i810_detach(device_t dev)
1294{
a904aa53 1295 struct agp_i810_softc *sc;
984263bc 1296
a904aa53 1297 sc = device_get_softc(dev);
67e2dc5d 1298 agp_free_cdev(dev);
984263bc
MD
1299
1300 /* Clear the GATT base. */
a904aa53
FT
1301 sc->match->driver->deinstall_gatt(dev);
1302
1303 sc->match->driver->chipset_flush_teardown(dev);
984263bc
MD
1304
1305 /* Put the aperture back the way it started. */
1306 AGP_SET_APERTURE(dev, sc->initial_aperture);
1307
efda3bd0 1308 kfree(sc->gatt, M_AGP);
a904aa53 1309 bus_release_resources(dev, sc->match->driver->res_spec, sc->sc_res);
67e2dc5d 1310 agp_free_res(dev);
984263bc 1311
a904aa53 1312 return (0);
984263bc
MD
1313}
1314
2f1d30c1
HT
1315static int
1316agp_i810_resume(device_t dev)
1317{
1318 struct agp_i810_softc *sc;
1319 sc = device_get_softc(dev);
1320
1321 AGP_SET_APERTURE(dev, sc->initial_aperture);
1322
1323 /* Install the GATT. */
1324 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
1325 sc->gatt->ag_physical | 1);
1326
1327 return (bus_generic_resume(dev));
1328}
1329
fdc3c5be
HT
1330/**
1331 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
1332 * while returning failure on later chipsets when an actual change is
1333 * requested.
1334 *
1335 * This whole function is likely bogus, as the kernel would probably need to
1336 * reconfigure the placement of the AGP aperture if a larger size is requested,
1337 * which doesn't happen currently.
1338 */
a904aa53
FT
1339
1340static int
1341agp_i915_set_aperture(device_t dev, u_int32_t aperture)
1342{
984263bc 1343
a904aa53
FT
1344 return (agp_generic_set_aperture(dev, aperture));
1345}
1346
1347static int
1348agp_i810_method_set_aperture(device_t dev, u_int32_t aperture)
1349{
1350 struct agp_i810_softc *sc;
1351
1352 sc = device_get_softc(dev);
1353 return (sc->match->driver->set_aperture(dev, aperture));
984263bc
MD
1354}
1355
fdc3c5be 1356/**
a904aa53
FT
1357 * Writes a GTT entry mapping the page at the given offset from the
1358 * beginning of the aperture to the given physical address. Setup the
1359 * caching mode according to flags.
1360 *
1361 * For gen 1, 2 and 3, GTT start is located at AGP_I810_GTT offset
1362 * from corresponding BAR start. For gen 4, offset is 512KB +
1363 * AGP_I810_GTT, for gen 5 and 6 it is 2MB + AGP_I810_GTT.
1364 *
1365 * Also, the bits of the physical page address above 4GB needs to be
1366 * placed into bits 40-32 of PTE.
fdc3c5be 1367 */
a904aa53
FT
1368static void
1369agp_i915_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1370 int flags)
1371{
1372 uint32_t pte;
1373
1374 pte = (u_int32_t)physical | I810_PTE_VALID;
1375 if (flags == AGP_USER_CACHED_MEMORY)
1376 pte |= I830_PTE_SYSTEM_CACHED;
99e9e211 1377
a904aa53
FT
1378 agp_i915_write_gtt(dev, index, pte);
1379}
1380
1381static void
1382agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte)
1383{
1384 struct agp_i810_softc *sc;
1385
1386 sc = device_get_softc(dev);
1387 bus_write_4(sc->sc_res[1], index * 4, pte);
1388}
1389
1390static void
1391agp_i965_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1392 int flags)
1393{
1394 uint32_t pte;
1395
1396 pte = (u_int32_t)physical | I810_PTE_VALID;
1397 if (flags == AGP_USER_CACHED_MEMORY)
1398 pte |= I830_PTE_SYSTEM_CACHED;
99e9e211
FT
1399
1400 pte |= (physical >> 28) & 0xf0;
a904aa53
FT
1401 agp_i965_write_gtt(dev, index, pte);
1402}
1403
1404static void
1405agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte)
1406{
1407 struct agp_i810_softc *sc;
1408
1409 sc = device_get_softc(dev);
1410 bus_write_4(sc->sc_res[0], index * 4 + (512 * 1024), pte);
1411}
1412
1413static void
1414agp_g4x_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1415 int flags)
1416{
1417 uint32_t pte;
1418
1419 pte = (u_int32_t)physical | I810_PTE_VALID;
1420 if (flags == AGP_USER_CACHED_MEMORY)
1421 pte |= I830_PTE_SYSTEM_CACHED;
99e9e211
FT
1422
1423 pte |= (physical >> 28) & 0xf0;
a904aa53
FT
1424 agp_g4x_write_gtt(dev, index, pte);
1425}
1426
1427static void
1428agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte)
1429{
1430 struct agp_i810_softc *sc;
1431
1432 sc = device_get_softc(dev);
1433 bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte);
1434}
1435
1436static void
09d2c144
MD
1437agp_sb_install_gtt_pte(device_t dev, u_int index,
1438 vm_offset_t physical, int flags)
a904aa53
FT
1439{
1440 int type_mask, gfdt;
1441 uint32_t pte;
1442
1443 pte = (u_int32_t)physical | I810_PTE_VALID;
1444 type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1445 gfdt = (flags & AGP_USER_CACHED_MEMORY_GFDT) != 0 ? GEN6_PTE_GFDT : 0;
1446
1447 if (type_mask == AGP_USER_MEMORY)
1448 pte |= GEN6_PTE_UNCACHED;
1449 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
1450 pte |= GEN6_PTE_LLC_MLC | gfdt;
1451 else
1452 pte |= GEN6_PTE_LLC | gfdt;
1453
1454 pte |= (physical & 0x000000ff00000000ull) >> 28;
1455 agp_sb_write_gtt(dev, index, pte);
1456}
1457
09d2c144
MD
1458static void
1459agp_gen8_install_gtt_pte(device_t dev, u_int index,
1460 vm_offset_t physical, int flags)
1461{
1462 struct agp_i810_softc *sc;
1463 int type_mask;
1464 uint64_t pte;
1465
1466 pte = (u_int64_t)physical | GEN8_PTE_PRESENT | GEN8_PTE_RW;
1467 type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1468
1469 if (type_mask == AGP_USER_MEMORY)
1470 pte |= GEN8_PTE_PWT; /* XXX */
1471 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC)
1472 pte |= GEN8_PTE_PWT; /* XXX */
1473 else
1474 pte |= GEN8_PTE_PWT; /* XXX */
1475
1476 sc = device_get_softc(dev);
1477 bus_write_4(sc->sc_res[0], index * 8 + (2 * 1024 * 1024),
1478 (uint32_t)pte);
1479 bus_write_4(sc->sc_res[0], index * 8 + (2 * 1024 * 1024) + 4,
1480 (uint32_t)(pte >> 32));
1481}
1482
a904aa53
FT
1483static void
1484agp_sb_write_gtt(device_t dev, u_int index, uint32_t pte)
1485{
1486 struct agp_i810_softc *sc;
1487
1488 sc = device_get_softc(dev);
1489 bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte);
1490}
1491
1492static int
1493agp_i810_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
fdc3c5be
HT
1494{
1495 struct agp_i810_softc *sc = device_get_softc(dev);
a904aa53 1496 u_int index;
fdc3c5be 1497
a904aa53
FT
1498 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
1499 device_printf(dev, "failed: offset is 0x%08jx, "
1500 "shift is %d, entries is %d\n", (intmax_t)offset,
1501 AGP_PAGE_SHIFT, sc->gatt->ag_entries);
1502 return (EINVAL);
1503 }
1504 index = offset >> AGP_PAGE_SHIFT;
1505 if (sc->stolen != 0 && index < sc->stolen) {
1506 device_printf(dev, "trying to bind into stolen memory\n");
1507 return (EINVAL);
fdc3c5be 1508 }
a904aa53
FT
1509 sc->match->driver->install_gtt_pte(dev, index, physical, 0);
1510 return (0);
1511}
fdc3c5be 1512
a904aa53
FT
1513static int
1514agp_i810_unbind_page(device_t dev, vm_offset_t offset)
1515{
1516 struct agp_i810_softc *sc;
1517 u_int index;
1518
1519 sc = device_get_softc(dev);
1520 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
1521 return (EINVAL);
1522 index = offset >> AGP_PAGE_SHIFT;
1523 if (sc->stolen != 0 && index < sc->stolen) {
1524 device_printf(dev, "trying to unbind from stolen memory\n");
1525 return (EINVAL);
fdc3c5be 1526 }
a904aa53
FT
1527 sc->match->driver->install_gtt_pte(dev, index, 0, 0);
1528 return (0);
1529}
1530
09d2c144
MD
1531static void
1532agp_i915_sync_gtt_pte(device_t dev, u_int index)
a904aa53
FT
1533{
1534 struct agp_i810_softc *sc;
fdc3c5be 1535
a904aa53 1536 sc = device_get_softc(dev);
09d2c144 1537 bus_read_4(sc->sc_res[1], index * 4);
984263bc
MD
1538}
1539
09d2c144
MD
1540static void
1541agp_i965_sync_gtt_pte(device_t dev, u_int index)
a904aa53
FT
1542{
1543 struct agp_i810_softc *sc;
984263bc 1544
a904aa53 1545 sc = device_get_softc(dev);
09d2c144 1546 bus_read_4(sc->sc_res[0], index * 4 + (512 * 1024));
a904aa53
FT
1547}
1548
09d2c144
MD
1549static void
1550agp_g4x_sync_gtt_pte(device_t dev, u_int index)
a904aa53
FT
1551{
1552 struct agp_i810_softc *sc;
fdc3c5be 1553
a904aa53 1554 sc = device_get_softc(dev);
09d2c144 1555 bus_read_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024));
984263bc
MD
1556}
1557
1558/*
1559 * Writing via memory mapped registers already flushes all TLBs.
1560 */
1561static void
1562agp_i810_flush_tlb(device_t dev)
1563{
1564}
1565
1566static int
1567agp_i810_enable(device_t dev, u_int32_t mode)
1568{
1569
a904aa53 1570 return (0);
984263bc
MD
1571}
1572
1573static struct agp_memory *
1574agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
1575{
a904aa53 1576 struct agp_i810_softc *sc;
984263bc 1577 struct agp_memory *mem;
a904aa53 1578 vm_page_t m;
984263bc 1579
a904aa53 1580 sc = device_get_softc(dev);
984263bc 1581
a904aa53
FT
1582 if ((size & (AGP_PAGE_SIZE - 1)) != 0 ||
1583 sc->agp.as_allocated + size > sc->agp.as_maxmem)
1584 return (0);
984263bc
MD
1585
1586 if (type == 1) {
1587 /*
1588 * Mapping local DRAM into GATT.
1589 */
a904aa53
FT
1590 if (sc->match->driver->chiptype != CHIP_I810)
1591 return (0);
984263bc 1592 if (size != sc->dcache_size)
a904aa53 1593 return (0);
984263bc
MD
1594 } else if (type == 2) {
1595 /*
fdc3c5be
HT
1596 * Type 2 is the contiguous physical memory type, that hands
1597 * back a physical address. This is used for cursors on i810.
1598 * Hand back as many single pages with physical as the user
1599 * wants, but only allow one larger allocation (ARGB cursor)
1600 * for simplicity.
984263bc 1601 */
fdc3c5be
HT
1602 if (size != AGP_PAGE_SIZE) {
1603 if (sc->argb_cursor != NULL)
a904aa53 1604 return (0);
fdc3c5be
HT
1605
1606 /* Allocate memory for ARGB cursor, if we can. */
1607 sc->argb_cursor = contigmalloc(size, M_AGP,
1608 0, 0, ~0, PAGE_SIZE, 0);
1609 if (sc->argb_cursor == NULL)
a904aa53 1610 return (0);
fdc3c5be 1611 }
984263bc
MD
1612 }
1613
efda3bd0 1614 mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
984263bc
MD
1615 mem->am_id = sc->agp.as_nextid++;
1616 mem->am_size = size;
1617 mem->am_type = type;
fdc3c5be 1618 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
984263bc 1619 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
a904aa53 1620 atop(round_page(size)));
984263bc
MD
1621 else
1622 mem->am_obj = 0;
1623
1624 if (type == 2) {
fdc3c5be
HT
1625 if (size == AGP_PAGE_SIZE) {
1626 /*
1627 * Allocate and wire down the page now so that we can
1628 * get its physical address.
1629 */
a904aa53 1630 VM_OBJECT_LOCK(mem->am_obj);
d2d8515b
MD
1631 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NORMAL |
1632 VM_ALLOC_ZERO |
1633 VM_ALLOC_RETRY);
fdc3c5be 1634 vm_page_wire(m);
a904aa53 1635 VM_OBJECT_UNLOCK(mem->am_obj);
fdc3c5be
HT
1636 mem->am_physical = VM_PAGE_TO_PHYS(m);
1637 vm_page_wakeup(m);
1638 } else {
1639 /* Our allocation is already nicely wired down for us.
1640 * Just grab the physical address.
1641 */
1642 mem->am_physical = vtophys(sc->argb_cursor);
1643 }
a904aa53 1644 } else
984263bc 1645 mem->am_physical = 0;
984263bc
MD
1646
1647 mem->am_offset = 0;
1648 mem->am_is_bound = 0;
1649 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
1650 sc->agp.as_allocated += size;
1651
a904aa53 1652 return (mem);
984263bc
MD
1653}
1654
1655static int
1656agp_i810_free_memory(device_t dev, struct agp_memory *mem)
1657{
a904aa53 1658 struct agp_i810_softc *sc;
984263bc
MD
1659
1660 if (mem->am_is_bound)
a904aa53
FT
1661 return (EBUSY);
1662
1663 sc = device_get_softc(dev);
984263bc
MD
1664
1665 if (mem->am_type == 2) {
fdc3c5be
HT
1666 if (mem->am_size == AGP_PAGE_SIZE) {
1667 /*
1668 * Unwire the page which we wired in alloc_memory.
1669 */
77912481 1670 vm_page_t m;
b12defdc
MD
1671
1672 vm_object_hold(mem->am_obj);
1673 m = vm_page_lookup_busy_wait(mem->am_obj, 0,
1674 FALSE, "agppg");
1675 vm_object_drop(mem->am_obj);
fdc3c5be 1676 vm_page_unwire(m, 0);
b12defdc 1677 vm_page_wakeup(m);
fdc3c5be
HT
1678 } else {
1679 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1680 sc->argb_cursor = NULL;
1681 }
984263bc
MD
1682 }
1683
1684 sc->agp.as_allocated -= mem->am_size;
1685 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1686 if (mem->am_obj)
1687 vm_object_deallocate(mem->am_obj);
efda3bd0 1688 kfree(mem, M_AGP);
a904aa53 1689 return (0);
984263bc
MD
1690}
1691
1692static int
a904aa53 1693agp_i810_bind_memory(device_t dev, struct agp_memory *mem, vm_offset_t offset)
984263bc 1694{
a904aa53 1695 struct agp_i810_softc *sc;
984263bc
MD
1696 vm_offset_t i;
1697
fdc3c5be 1698 /* Do some sanity checks first. */
7f9ec87c 1699 if ((offset & (AGP_PAGE_SIZE - 1)) != 0 ||
fdc3c5be
HT
1700 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1701 device_printf(dev, "binding memory at bad offset %#x\n",
1702 (int)offset);
a904aa53 1703 return (EINVAL);
fdc3c5be
HT
1704 }
1705
a904aa53 1706 sc = device_get_softc(dev);
fdc3c5be
HT
1707 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1708 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1709 if (mem->am_is_bound) {
1710 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1711 return EINVAL;
1712 }
1713 /* The memory's already wired down, just stick it in the GTT. */
1714 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
a904aa53
FT
1715 sc->match->driver->install_gtt_pte(dev, (offset + i) >>
1716 AGP_PAGE_SHIFT, mem->am_physical + i, 0);
fdc3c5be
HT
1717 }
1718 agp_flush_cache();
1719 mem->am_offset = offset;
1720 mem->am_is_bound = 1;
1721 lockmgr(&sc->agp.as_lock, LK_RELEASE);
a904aa53 1722 return (0);
fdc3c5be
HT
1723 }
1724
984263bc 1725 if (mem->am_type != 1)
a904aa53 1726 return (agp_generic_bind_memory(dev, mem, offset));
984263bc 1727
a904aa53
FT
1728 /*
1729 * Mapping local DRAM into GATT.
1730 */
1731 if (sc->match->driver->chiptype != CHIP_I810)
1732 return (EINVAL);
1733 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
fdc3c5be
HT
1734 bus_write_4(sc->sc_res[0],
1735 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
984263bc 1736
a904aa53 1737 return (0);
984263bc
MD
1738}
1739
1740static int
1741agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1742{
a904aa53 1743 struct agp_i810_softc *sc;
984263bc
MD
1744 vm_offset_t i;
1745
a904aa53
FT
1746 sc = device_get_softc(dev);
1747
fdc3c5be
HT
1748 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1749 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1750 if (!mem->am_is_bound) {
1751 lockmgr(&sc->agp.as_lock, LK_RELEASE);
a904aa53 1752 return (EINVAL);
fdc3c5be
HT
1753 }
1754
1755 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
a904aa53
FT
1756 sc->match->driver->install_gtt_pte(dev,
1757 (mem->am_offset + i) >> AGP_PAGE_SHIFT, 0, 0);
fdc3c5be
HT
1758 }
1759 agp_flush_cache();
1760 mem->am_is_bound = 0;
1761 lockmgr(&sc->agp.as_lock, LK_RELEASE);
a904aa53 1762 return (0);
fdc3c5be
HT
1763 }
1764
984263bc 1765 if (mem->am_type != 1)
a904aa53 1766 return (agp_generic_unbind_memory(dev, mem));
984263bc 1767
a904aa53
FT
1768 if (sc->match->driver->chiptype != CHIP_I810)
1769 return (EINVAL);
fdc3c5be 1770 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
a904aa53
FT
1771 sc->match->driver->install_gtt_pte(dev, i >> AGP_PAGE_SHIFT,
1772 0, 0);
fdc3c5be 1773 }
a904aa53 1774 return (0);
984263bc
MD
1775}
1776
1777static device_method_t agp_i810_methods[] = {
1778 /* Device interface */
fdc3c5be 1779 DEVMETHOD(device_identify, agp_i810_identify),
984263bc
MD
1780 DEVMETHOD(device_probe, agp_i810_probe),
1781 DEVMETHOD(device_attach, agp_i810_attach),
1782 DEVMETHOD(device_detach, agp_i810_detach),
2f1d30c1
HT
1783 DEVMETHOD(device_suspend, bus_generic_suspend),
1784 DEVMETHOD(device_resume, agp_i810_resume),
984263bc
MD
1785
1786 /* AGP interface */
fdc3c5be 1787 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
a904aa53 1788 DEVMETHOD(agp_set_aperture, agp_i810_method_set_aperture),
984263bc
MD
1789 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1790 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1791 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1792 DEVMETHOD(agp_enable, agp_i810_enable),
1793 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1794 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1795 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1796 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
a904aa53 1797 DEVMETHOD(agp_chipset_flush, agp_intel_gtt_chipset_flush),
984263bc 1798
d3c9c58e 1799 DEVMETHOD_END
984263bc
MD
1800};
1801
1802static driver_t agp_i810_driver = {
1803 "agp",
1804 agp_i810_methods,
1805 sizeof(struct agp_i810_softc),
1806};
1807
1808static devclass_t agp_devclass;
1809
aa2b9d05 1810DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, NULL, NULL);
f7841f3c
MD
1811MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1812MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
a904aa53
FT
1813
1814extern vm_page_t bogus_page;
1815
1816void
1817agp_intel_gtt_clear_range(device_t dev, u_int first_entry, u_int num_entries)
1818{
1819 struct agp_i810_softc *sc;
1820 u_int i;
1821
1822 sc = device_get_softc(dev);
1823 for (i = 0; i < num_entries; i++)
1824 sc->match->driver->install_gtt_pte(dev, first_entry + i,
1825 VM_PAGE_TO_PHYS(bogus_page), 0);
09d2c144 1826 sc->match->driver->sync_gtt_pte(dev, first_entry + num_entries - 1);
a904aa53
FT
1827}
1828
1829void
1830agp_intel_gtt_insert_pages(device_t dev, u_int first_entry, u_int num_entries,
1831 vm_page_t *pages, u_int flags)
1832{
1833 struct agp_i810_softc *sc;
1834 u_int i;
1835
1836 sc = device_get_softc(dev);
1837 for (i = 0; i < num_entries; i++) {
1838 KKASSERT(pages[i]->valid == VM_PAGE_BITS_ALL);
1839 KKASSERT(pages[i]->wire_count > 0);
1840 sc->match->driver->install_gtt_pte(dev, first_entry + i,
1841 VM_PAGE_TO_PHYS(pages[i]), flags);
1842 }
09d2c144 1843 sc->match->driver->sync_gtt_pte(dev, first_entry + num_entries - 1);
a904aa53
FT
1844}
1845
1846struct intel_gtt
1847agp_intel_gtt_get(device_t dev)
1848{
1849 struct agp_i810_softc *sc;
1850 struct intel_gtt res;
1851
1852 sc = device_get_softc(dev);
1853 res.stolen_size = sc->stolen_size;
1854 res.gtt_total_entries = sc->gtt_total_entries;
1855 res.gtt_mappable_entries = sc->gtt_mappable_entries;
1856 res.do_idle_maps = 0;
1857 res.scratch_page_dma = VM_PAGE_TO_PHYS(bogus_page);
1858 return (res);
1859}
1860
1861static int
1862agp_i810_chipset_flush_setup(device_t dev)
1863{
1864
1865 return (0);
1866}
1867
1868static void
1869agp_i810_chipset_flush_teardown(device_t dev)
1870{
1871
1872 /* Nothing to do. */
1873}
1874
1875static void
1876agp_i810_chipset_flush(device_t dev)
1877{
1878
1879 /* Nothing to do. */
1880}
1881
a904aa53
FT
1882static int
1883agp_i915_chipset_flush_alloc_page(device_t dev, uint64_t start, uint64_t end)
1884{
1885 struct agp_i810_softc *sc;
1886 device_t vga;
1887
1888 sc = device_get_softc(dev);
1889 vga = device_get_parent(dev);
1890 sc->sc_flush_page_rid = 100;
1891 sc->sc_flush_page_res = BUS_ALLOC_RESOURCE(device_get_parent(vga), dev,
1892 SYS_RES_MEMORY, &sc->sc_flush_page_rid, start, end, PAGE_SIZE,
1893 RF_ACTIVE, -1);
1894 if (sc->sc_flush_page_res == NULL) {
1895 device_printf(dev, "Failed to allocate flush page at 0x%jx\n",
1896 (uintmax_t)start);
1897 return (EINVAL);
1898 }
1899 sc->sc_flush_page_vaddr = rman_get_virtual(sc->sc_flush_page_res);
1900 if (bootverbose) {
1901 device_printf(dev, "Allocated flush page phys 0x%jx virt %p\n",
1902 (uintmax_t)rman_get_start(sc->sc_flush_page_res),
1903 sc->sc_flush_page_vaddr);
1904 }
1905 return (0);
1906}
1907
1908static void
1909agp_i915_chipset_flush_free_page(device_t dev)
1910{
1911 struct agp_i810_softc *sc;
1912 device_t vga;
1913
1914 sc = device_get_softc(dev);
1915 vga = device_get_parent(dev);
1916 if (sc->sc_flush_page_res == NULL)
1917 return;
1918 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY,
1919 sc->sc_flush_page_rid, sc->sc_flush_page_res);
1920 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY,
1921 sc->sc_flush_page_rid, sc->sc_flush_page_res);
1922}
1923
1924static int
1925agp_i915_chipset_flush_setup(device_t dev)
1926{
1927 struct agp_i810_softc *sc;
1928 uint32_t temp;
1929 int error;
1930
1931 sc = device_get_softc(dev);
1932 temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4);
1933 if ((temp & 1) != 0) {
1934 temp &= ~1;
1935 if (bootverbose)
1936 device_printf(dev,
1937 "Found already configured flush page at 0x%jx\n",
1938 (uintmax_t)temp);
1939 sc->sc_bios_allocated_flush_page = 1;
1940 /*
1941 * In the case BIOS initialized the flush pointer (?)
1942 * register, expect that BIOS also set up the resource
1943 * for the page.
1944 */
1945 error = agp_i915_chipset_flush_alloc_page(dev, temp,
1946 temp + PAGE_SIZE - 1);
1947 if (error != 0)
1948 return (error);
1949 } else {
1950 sc->sc_bios_allocated_flush_page = 0;
1951 error = agp_i915_chipset_flush_alloc_page(dev, 0, 0xffffffff);
1952 if (error != 0)
1953 return (error);
1954 temp = rman_get_start(sc->sc_flush_page_res);
1955 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp | 1, 4);
1956 }
1957 return (0);
1958}
1959
1960static void
1961agp_i915_chipset_flush_teardown(device_t dev)
1962{
1963 struct agp_i810_softc *sc;
1964 uint32_t temp;
1965
1966 sc = device_get_softc(dev);
1967 if (sc->sc_flush_page_res == NULL)
1968 return;
1969 if (!sc->sc_bios_allocated_flush_page) {
1970 temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4);
1971 temp &= ~1;
1972 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp, 4);
1973 }
1974 agp_i915_chipset_flush_free_page(dev);
1975}
1976
1977static int
1978agp_i965_chipset_flush_setup(device_t dev)
1979{
1980 struct agp_i810_softc *sc;
1981 uint64_t temp;
1982 uint32_t temp_hi, temp_lo;
1983 int error;
1984
1985 sc = device_get_softc(dev);
1986
1987 temp_hi = pci_read_config(sc->bdev, AGP_I965_IFPADDR + 4, 4);
1988 temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4);
1989
1990 if ((temp_lo & 1) != 0) {
1991 temp = ((uint64_t)temp_hi << 32) | (temp_lo & ~1);
1992 if (bootverbose)
1993 device_printf(dev,
1994 "Found already configured flush page at 0x%jx\n",
1995 (uintmax_t)temp);
1996 sc->sc_bios_allocated_flush_page = 1;
1997 /*
1998 * In the case BIOS initialized the flush pointer (?)
1999 * register, expect that BIOS also set up the resource
2000 * for the page.
2001 */
2002 error = agp_i915_chipset_flush_alloc_page(dev, temp,
2003 temp + PAGE_SIZE - 1);
2004 if (error != 0)
2005 return (error);
2006 } else {
2007 sc->sc_bios_allocated_flush_page = 0;
2008 error = agp_i915_chipset_flush_alloc_page(dev, 0, ~0);
2009 if (error != 0)
2010 return (error);
2011 temp = rman_get_start(sc->sc_flush_page_res);
2012 pci_write_config(sc->bdev, AGP_I965_IFPADDR + 4,
2013 (temp >> 32) & UINT32_MAX, 4);
2014 pci_write_config(sc->bdev, AGP_I965_IFPADDR,
2015 (temp & UINT32_MAX) | 1, 4);
2016 }
2017 return (0);
2018}
2019
2020static void
2021agp_i965_chipset_flush_teardown(device_t dev)
2022{
2023 struct agp_i810_softc *sc;
2024 uint32_t temp_lo;
2025
2026 sc = device_get_softc(dev);
2027 if (sc->sc_flush_page_res == NULL)
2028 return;
2029 if (!sc->sc_bios_allocated_flush_page) {
2030 temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4);
2031 temp_lo &= ~1;
2032 pci_write_config(sc->bdev, AGP_I965_IFPADDR, temp_lo, 4);
2033 }
2034 agp_i915_chipset_flush_free_page(dev);
2035}
2036
2037static void
2038agp_i915_chipset_flush(device_t dev)
2039{
2040 struct agp_i810_softc *sc;
2041
2042 sc = device_get_softc(dev);
2043 *(uint32_t *)sc->sc_flush_page_vaddr = 1;
2044}
2045
2046int
2047agp_intel_gtt_chipset_flush(device_t dev)
2048{
2049 struct agp_i810_softc *sc;
2050
2051 sc = device_get_softc(dev);
2052 sc->match->driver->chipset_flush(dev);
2053 return (0);
2054}
2055
2056void
2057agp_intel_gtt_unmap_memory(device_t dev, struct sglist *sg_list)
2058{
2059}
2060
2061int
2062agp_intel_gtt_map_memory(device_t dev, vm_page_t *pages, u_int num_entries,
2063 struct sglist **sg_list)
2064{
839fbabb 2065#if 0
a904aa53 2066 struct agp_i810_softc *sc;
839fbabb 2067#endif
a904aa53
FT
2068 struct sglist *sg;
2069 int i;
2070#if 0
2071 int error;
2072 bus_dma_tag_t dmat;
2073#endif
2074
2075 if (*sg_list != NULL)
2076 return (0);
839fbabb 2077#if 0
a904aa53 2078 sc = device_get_softc(dev);
839fbabb 2079#endif
a904aa53
FT
2080 sg = sglist_alloc(num_entries, M_WAITOK /* XXXKIB */);
2081 for (i = 0; i < num_entries; i++) {
2082 sg->sg_segs[i].ss_paddr = VM_PAGE_TO_PHYS(pages[i]);
2083 sg->sg_segs[i].ss_len = PAGE_SIZE;
2084 }
2085
2086#if 0
2087 error = bus_dma_tag_create(bus_get_dma_tag(dev),
2088 1 /* alignment */, 0 /* boundary */,
2089 1ULL << sc->match->busdma_addr_mask_sz /* lowaddr */,
2090 BUS_SPACE_MAXADDR /* highaddr */,
2091 NULL /* filtfunc */, NULL /* filtfuncarg */,
2092 BUS_SPACE_MAXADDR /* maxsize */,
2093 BUS_SPACE_UNRESTRICTED /* nsegments */,
2094 BUS_SPACE_MAXADDR /* maxsegsz */,
2095 0 /* flags */, NULL /* lockfunc */, NULL /* lockfuncarg */,
2096 &dmat);
2097 if (error != 0) {
2098 sglist_free(sg);
2099 return (error);
2100 }
2101 /* XXXKIB */
2102#endif
2103 *sg_list = sg;
2104 return (0);
2105}
2106
2107void
2108agp_intel_gtt_insert_sg_entries(device_t dev, struct sglist *sg_list,
2109 u_int first_entry, u_int flags)
2110{
2111 struct agp_i810_softc *sc;
2112 vm_paddr_t spaddr;
2113 size_t slen;
2114 u_int i, j;
2115
2116 sc = device_get_softc(dev);
2117 for (i = j = 0; j < sg_list->sg_nseg; j++) {
2118 spaddr = sg_list->sg_segs[i].ss_paddr;
2119 slen = sg_list->sg_segs[i].ss_len;
2120 for (; slen > 0; i++) {
2121 sc->match->driver->install_gtt_pte(dev, first_entry + i,
2122 spaddr, flags);
2123 spaddr += AGP_PAGE_SIZE;
2124 slen -= AGP_PAGE_SIZE;
2125 }
2126 }
09d2c144 2127 sc->match->driver->sync_gtt_pte(dev, first_entry + i - 1);
a904aa53
FT
2128}
2129
2130void
2131intel_gtt_clear_range(u_int first_entry, u_int num_entries)
2132{
2133
2134 agp_intel_gtt_clear_range(intel_agp, first_entry, num_entries);
2135}
2136
2137void
2138intel_gtt_insert_pages(u_int first_entry, u_int num_entries, vm_page_t *pages,
2139 u_int flags)
2140{
2141
2142 agp_intel_gtt_insert_pages(intel_agp, first_entry, num_entries,
2143 pages, flags);
2144}
2145
9edbd4a0
FT
2146void intel_gtt_get(size_t *gtt_total, size_t *stolen_size,
2147 phys_addr_t *mappable_base, unsigned long *mappable_end)
a904aa53 2148{
bc2fd6c1 2149 intel_private.base = agp_intel_gtt_get(intel_agp);
9edbd4a0
FT
2150
2151 *gtt_total = intel_private.base.gtt_total_entries << PAGE_SHIFT;
2152 *stolen_size = intel_private.base.stolen_size;
2153 *mappable_base = intel_private.base.gma_bus_addr;
2154 *mappable_end = intel_private.base.gtt_mappable_entries << PAGE_SHIFT;
a904aa53
FT
2155}
2156
2157int
2158intel_gtt_chipset_flush(void)
2159{
2160
2161 return (agp_intel_gtt_chipset_flush(intel_agp));
2162}
2163
2164void
2165intel_gtt_unmap_memory(struct sglist *sg_list)
2166{
2167
2168 agp_intel_gtt_unmap_memory(intel_agp, sg_list);
2169}
2170
2171int
2172intel_gtt_map_memory(vm_page_t *pages, u_int num_entries,
2173 struct sglist **sg_list)
2174{
2175
2176 return (agp_intel_gtt_map_memory(intel_agp, pages, num_entries,
2177 sg_list));
2178}
2179
2180void
2181intel_gtt_insert_sg_entries(struct sglist *sg_list, u_int first_entry,
2182 u_int flags)
2183{
2184
2185 agp_intel_gtt_insert_sg_entries(intel_agp, sg_list, first_entry, flags);
2186}
2187
09d2c144
MD
2188/*
2189 * Only used by gen6
2190 */
2191void
2192intel_gtt_sync_pte(u_int entry)
a904aa53
FT
2193{
2194 struct agp_i810_softc *sc;
2195
2196 sc = device_get_softc(intel_agp);
09d2c144 2197 sc->match->driver->sync_gtt_pte(intel_agp, entry);
a904aa53
FT
2198}
2199
09d2c144
MD
2200/*
2201 * Only used by gen6
2202 */
a904aa53
FT
2203void
2204intel_gtt_write(u_int entry, uint32_t val)
2205{
2206 struct agp_i810_softc *sc;
2207
2208 sc = device_get_softc(intel_agp);
d63cf994 2209 sc->match->driver->write_gtt(intel_agp, entry, val);
a904aa53 2210}