Merge branch 'vendor/GCC50'
[dragonfly.git] / contrib / binutils-2.24 / gas / doc / c-arm.texi
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1@c Copyright 1996-2013 Free Software Foundation, Inc.
2@c This is part of the GAS manual.
3@c For copying conditions, see the file as.texinfo.
4
5@ifset GENERIC
6@page
7@node ARM-Dependent
8@chapter ARM Dependent Features
9@end ifset
10
11@ifclear GENERIC
12@node Machine Dependencies
13@chapter ARM Dependent Features
14@end ifclear
15
16@cindex ARM support
17@cindex Thumb support
18@menu
19* ARM Options:: Options
20* ARM Syntax:: Syntax
21* ARM Floating Point:: Floating Point
22* ARM Directives:: ARM Machine Directives
23* ARM Opcodes:: Opcodes
24* ARM Mapping Symbols:: Mapping Symbols
25* ARM Unwinding Tutorial:: Unwinding
26@end menu
27
28@node ARM Options
29@section Options
30@cindex ARM options (none)
31@cindex options for ARM (none)
32
33@table @code
34
35@cindex @code{-mcpu=} command line option, ARM
36@item -mcpu=@var{processor}[+@var{extension}@dots{}]
37This option specifies the target processor. The assembler will issue an
38error message if an attempt is made to assemble an instruction which
39will not execute on the target processor. The following processor names are
40recognized:
41@code{arm1},
42@code{arm2},
43@code{arm250},
44@code{arm3},
45@code{arm6},
46@code{arm60},
47@code{arm600},
48@code{arm610},
49@code{arm620},
50@code{arm7},
51@code{arm7m},
52@code{arm7d},
53@code{arm7dm},
54@code{arm7di},
55@code{arm7dmi},
56@code{arm70},
57@code{arm700},
58@code{arm700i},
59@code{arm710},
60@code{arm710t},
61@code{arm720},
62@code{arm720t},
63@code{arm740t},
64@code{arm710c},
65@code{arm7100},
66@code{arm7500},
67@code{arm7500fe},
68@code{arm7t},
69@code{arm7tdmi},
70@code{arm7tdmi-s},
71@code{arm8},
72@code{arm810},
73@code{strongarm},
74@code{strongarm1},
75@code{strongarm110},
76@code{strongarm1100},
77@code{strongarm1110},
78@code{arm9},
79@code{arm920},
80@code{arm920t},
81@code{arm922t},
82@code{arm940t},
83@code{arm9tdmi},
84@code{fa526} (Faraday FA526 processor),
85@code{fa626} (Faraday FA626 processor),
86@code{arm9e},
87@code{arm926e},
88@code{arm926ej-s},
89@code{arm946e-r0},
90@code{arm946e},
91@code{arm946e-s},
92@code{arm966e-r0},
93@code{arm966e},
94@code{arm966e-s},
95@code{arm968e-s},
96@code{arm10t},
97@code{arm10tdmi},
98@code{arm10e},
99@code{arm1020},
100@code{arm1020t},
101@code{arm1020e},
102@code{arm1022e},
103@code{arm1026ej-s},
104@code{fa606te} (Faraday FA606TE processor),
105@code{fa616te} (Faraday FA616TE processor),
106@code{fa626te} (Faraday FA626TE processor),
107@code{fmp626} (Faraday FMP626 processor),
108@code{fa726te} (Faraday FA726TE processor),
109@code{arm1136j-s},
110@code{arm1136jf-s},
111@code{arm1156t2-s},
112@code{arm1156t2f-s},
113@code{arm1176jz-s},
114@code{arm1176jzf-s},
115@code{mpcore},
116@code{mpcorenovfp},
117@code{cortex-a5},
118@code{cortex-a7},
119@code{cortex-a8},
120@code{cortex-a9},
121@code{cortex-a15},
122@code{cortex-r4},
123@code{cortex-r4f},
124@code{cortex-r5},
125@code{cortex-r7},
126@code{cortex-m4},
127@code{cortex-m3},
128@code{cortex-m1},
129@code{cortex-m0},
130@code{cortex-m0plus},
131@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
132@code{i80200} (Intel XScale processor)
133@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
134and
135@code{xscale}.
136The special name @code{all} may be used to allow the
137assembler to accept instructions valid for any ARM processor.
138
139In addition to the basic instruction set, the assembler can be told to
140accept various extension mnemonics that extend the processor using the
141co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
142is equivalent to specifying @code{-mcpu=ep9312}.
143
144Multiple extensions may be specified, separated by a @code{+}. The
145extensions should be specified in ascending alphabetical order.
146
147Some extensions may be restricted to particular architectures; this is
148documented in the list of extensions below.
149
150Extension mnemonics may also be removed from those the assembler accepts.
151This is done be prepending @code{no} to the option that adds the extension.
152Extensions that are removed should be listed after all extensions which have
153been added, again in ascending alphabetical order. For example,
154@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
155
156
157The following extensions are currently supported:
158@code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
159@code{fp} (Floating Point Extensions for v8-A architecture),
160@code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
161@code{iwmmxt},
162@code{iwmmxt2},
163@code{maverick},
164@code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
165@code{os} (Operating System for v6M architecture),
166@code{sec} (Security Extensions for v6K and v7-A architectures),
167@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
168@code{virt} (Virtualization Extensions for v7-A architecture, implies
169@code{idiv}),
170and
171@code{xscale}.
172
173@cindex @code{-march=} command line option, ARM
174@item -march=@var{architecture}[+@var{extension}@dots{}]
175This option specifies the target architecture. The assembler will issue
176an error message if an attempt is made to assemble an instruction which
177will not execute on the target architecture. The following architecture
178names are recognized:
179@code{armv1},
180@code{armv2},
181@code{armv2a},
182@code{armv2s},
183@code{armv3},
184@code{armv3m},
185@code{armv4},
186@code{armv4xm},
187@code{armv4t},
188@code{armv4txm},
189@code{armv5},
190@code{armv5t},
191@code{armv5txm},
192@code{armv5te},
193@code{armv5texp},
194@code{armv6},
195@code{armv6j},
196@code{armv6k},
197@code{armv6z},
198@code{armv6zk},
199@code{armv6-m},
200@code{armv6s-m},
201@code{armv7},
202@code{armv7-a},
203@code{armv7ve},
204@code{armv7-r},
205@code{armv7-m},
206@code{armv7e-m},
207@code{armv8-a},
208@code{iwmmxt}
209and
210@code{xscale}.
211If both @code{-mcpu} and
212@code{-march} are specified, the assembler will use
213the setting for @code{-mcpu}.
214
215The architecture option can be extended with the same instruction set
216extension options as the @code{-mcpu} option.
217
218@cindex @code{-mfpu=} command line option, ARM
219@item -mfpu=@var{floating-point-format}
220
221This option specifies the floating point format to assemble for. The
222assembler will issue an error message if an attempt is made to assemble
223an instruction which will not execute on the target floating point unit.
224The following format options are recognized:
225@code{softfpa},
226@code{fpe},
227@code{fpe2},
228@code{fpe3},
229@code{fpa},
230@code{fpa10},
231@code{fpa11},
232@code{arm7500fe},
233@code{softvfp},
234@code{softvfp+vfp},
235@code{vfp},
236@code{vfp10},
237@code{vfp10-r0},
238@code{vfp9},
239@code{vfpxd},
240@code{vfpv2},
241@code{vfpv3},
242@code{vfpv3-fp16},
243@code{vfpv3-d16},
244@code{vfpv3-d16-fp16},
245@code{vfpv3xd},
246@code{vfpv3xd-d16},
247@code{vfpv4},
248@code{vfpv4-d16},
249@code{fpv4-sp-d16},
250@code{fp-armv8},
251@code{arm1020t},
252@code{arm1020e},
253@code{arm1136jf-s},
254@code{maverick},
255@code{neon},
256@code{neon-vfpv4},
257@code{neon-fp-armv8},
258and
259@code{crypto-neon-fp-armv8}.
260
261In addition to determining which instructions are assembled, this option
262also affects the way in which the @code{.double} assembler directive behaves
263when assembling little-endian code.
264
265The default is dependent on the processor selected. For Architecture 5 or
266later, the default is to assembler for VFP instructions; for earlier
267architectures the default is to assemble for FPA instructions.
268
269@cindex @code{-mthumb} command line option, ARM
270@item -mthumb
271This option specifies that the assembler should start assembling Thumb
272instructions; that is, it should behave as though the file starts with a
273@code{.code 16} directive.
274
275@cindex @code{-mthumb-interwork} command line option, ARM
276@item -mthumb-interwork
277This option specifies that the output generated by the assembler should
278be marked as supporting interworking.
279
280@cindex @code{-mimplicit-it} command line option, ARM
281@item -mimplicit-it=never
282@itemx -mimplicit-it=always
283@itemx -mimplicit-it=arm
284@itemx -mimplicit-it=thumb
285The @code{-mimplicit-it} option controls the behavior of the assembler when
286conditional instructions are not enclosed in IT blocks.
287There are four possible behaviors.
288If @code{never} is specified, such constructs cause a warning in ARM
289code and an error in Thumb-2 code.
290If @code{always} is specified, such constructs are accepted in both
291ARM and Thumb-2 code, where the IT instruction is added implicitly.
292If @code{arm} is specified, such constructs are accepted in ARM code
293and cause an error in Thumb-2 code.
294If @code{thumb} is specified, such constructs cause a warning in ARM
295code and are accepted in Thumb-2 code. If you omit this option, the
296behavior is equivalent to @code{-mimplicit-it=arm}.
297
298@cindex @code{-mapcs-26} command line option, ARM
299@cindex @code{-mapcs-32} command line option, ARM
300@item -mapcs-26
301@itemx -mapcs-32
302These options specify that the output generated by the assembler should
303be marked as supporting the indicated version of the Arm Procedure.
304Calling Standard.
305
306@cindex @code{-matpcs} command line option, ARM
307@item -matpcs
308This option specifies that the output generated by the assembler should
309be marked as supporting the Arm/Thumb Procedure Calling Standard. If
310enabled this option will cause the assembler to create an empty
311debugging section in the object file called .arm.atpcs. Debuggers can
312use this to determine the ABI being used by.
313
314@cindex @code{-mapcs-float} command line option, ARM
315@item -mapcs-float
316This indicates the floating point variant of the APCS should be
317used. In this variant floating point arguments are passed in FP
318registers rather than integer registers.
319
320@cindex @code{-mapcs-reentrant} command line option, ARM
321@item -mapcs-reentrant
322This indicates that the reentrant variant of the APCS should be used.
323This variant supports position independent code.
324
325@cindex @code{-mfloat-abi=} command line option, ARM
326@item -mfloat-abi=@var{abi}
327This option specifies that the output generated by the assembler should be
328marked as using specified floating point ABI.
329The following values are recognized:
330@code{soft},
331@code{softfp}
332and
333@code{hard}.
334
335@cindex @code{-eabi=} command line option, ARM
336@item -meabi=@var{ver}
337This option specifies which EABI version the produced object files should
338conform to.
339The following values are recognized:
340@code{gnu},
341@code{4}
342and
343@code{5}.
344
345@cindex @code{-EB} command line option, ARM
346@item -EB
347This option specifies that the output generated by the assembler should
348be marked as being encoded for a big-endian processor.
349
350@cindex @code{-EL} command line option, ARM
351@item -EL
352This option specifies that the output generated by the assembler should
353be marked as being encoded for a little-endian processor.
354
355@cindex @code{-k} command line option, ARM
356@cindex PIC code generation for ARM
357@item -k
358This option specifies that the output of the assembler should be marked
359as position-independent code (PIC).
360
361@cindex @code{--fix-v4bx} command line option, ARM
362@item --fix-v4bx
363Allow @code{BX} instructions in ARMv4 code. This is intended for use with
364the linker option of the same name.
365
366@cindex @code{-mwarn-deprecated} command line option, ARM
367@item -mwarn-deprecated
368@itemx -mno-warn-deprecated
369Enable or disable warnings about using deprecated options or
370features. The default is to warn.
371
372@end table
373
374
375@node ARM Syntax
376@section Syntax
377@menu
378* ARM-Instruction-Set:: Instruction Set
379* ARM-Chars:: Special Characters
380* ARM-Regs:: Register Names
381* ARM-Relocations:: Relocations
382* ARM-Neon-Alignment:: NEON Alignment Specifiers
383@end menu
384
385@node ARM-Instruction-Set
386@subsection Instruction Set Syntax
387Two slightly different syntaxes are support for ARM and THUMB
388instructions. The default, @code{divided}, uses the old style where
389ARM and THUMB instructions had their own, separate syntaxes. The new,
390@code{unified} syntax, which can be selected via the @code{.syntax}
391directive, and has the following main features:
392
393@itemize @bullet
394@item
395Immediate operands do not require a @code{#} prefix.
396
397@item
398The @code{IT} instruction may appear, and if it does it is validated
399against subsequent conditional affixes. In ARM mode it does not
400generate machine code, in THUMB mode it does.
401
402@item
403For ARM instructions the conditional affixes always appear at the end
404of the instruction. For THUMB instructions conditional affixes can be
405used, but only inside the scope of an @code{IT} instruction.
406
407@item
408All of the instructions new to the V6T2 architecture (and later) are
409available. (Only a few such instructions can be written in the
410@code{divided} syntax).
411
412@item
413The @code{.N} and @code{.W} suffixes are recognized and honored.
414
415@item
416All instructions set the flags if and only if they have an @code{s}
417affix.
418@end itemize
419
420@node ARM-Chars
421@subsection Special Characters
422
423@cindex line comment character, ARM
424@cindex ARM line comment character
425The presence of a @samp{@@} anywhere on a line indicates the start of
426a comment that extends to the end of that line.
427
428If a @samp{#} appears as the first character of a line then the whole
429line is treated as a comment, but in this case the line could also be
430a logical line number directive (@pxref{Comments}) or a preprocessor
431control command (@pxref{Preprocessing}).
432
433@cindex line separator, ARM
434@cindex statement separator, ARM
435@cindex ARM line separator
436The @samp{;} character can be used instead of a newline to separate
437statements.
438
439@cindex immediate character, ARM
440@cindex ARM immediate character
441Either @samp{#} or @samp{$} can be used to indicate immediate operands.
442
443@cindex identifiers, ARM
444@cindex ARM identifiers
445*TODO* Explain about /data modifier on symbols.
446
447@node ARM-Regs
448@subsection Register Names
449
450@cindex ARM register names
451@cindex register names, ARM
452*TODO* Explain about ARM register naming, and the predefined names.
453
454@node ARM-Relocations
455@subsection ARM relocation generation
456
457@cindex data relocations, ARM
458@cindex ARM data relocations
459Specific data relocations can be generated by putting the relocation name
460in parentheses after the symbol name. For example:
461
462@smallexample
463 .word foo(TARGET1)
464@end smallexample
465
466This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
467@var{foo}.
468The following relocations are supported:
469@code{GOT},
470@code{GOTOFF},
471@code{TARGET1},
472@code{TARGET2},
473@code{SBREL},
474@code{TLSGD},
475@code{TLSLDM},
476@code{TLSLDO},
477@code{TLSDESC},
478@code{TLSCALL},
479@code{GOTTPOFF},
480@code{GOT_PREL}
481and
482@code{TPOFF}.
483
484For compatibility with older toolchains the assembler also accepts
485@code{(PLT)} after branch targets. On legacy targets this will
486generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
487targets it will encode either the @samp{R_ARM_CALL} or
488@samp{R_ARM_JUMP24} relocation, as appropriate.
489
490@cindex MOVW and MOVT relocations, ARM
491Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
492by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
493respectively. For example to load the 32-bit address of foo into r0:
494
495@smallexample
496 MOVW r0, #:lower16:foo
497 MOVT r0, #:upper16:foo
498@end smallexample
499
500@node ARM-Neon-Alignment
501@subsection NEON Alignment Specifiers
502
503@cindex alignment for NEON instructions
504Some NEON load/store instructions allow an optional address
505alignment qualifier.
506The ARM documentation specifies that this is indicated by
507@samp{@@ @var{align}}. However GAS already interprets
508the @samp{@@} character as a "line comment" start,
509so @samp{: @var{align}} is used instead. For example:
510
511@smallexample
512 vld1.8 @{q0@}, [r0, :128]
513@end smallexample
514
515@node ARM Floating Point
516@section Floating Point
517
518@cindex floating point, ARM (@sc{ieee})
519@cindex ARM floating point (@sc{ieee})
520The ARM family uses @sc{ieee} floating-point numbers.
521
522@node ARM Directives
523@section ARM Machine Directives
524
525@cindex machine directives, ARM
526@cindex ARM machine directives
527@table @code
528
529@c AAAAAAAAAAAAAAAAAAAAAAAAA
530
531@cindex @code{.2byte} directive, ARM
532@cindex @code{.4byte} directive, ARM
533@cindex @code{.8byte} directive, ARM
534@item .2byte @var{expression} [, @var{expression}]*
535@itemx .4byte @var{expression} [, @var{expression}]*
536@itemx .8byte @var{expression} [, @var{expression}]*
537These directives write 2, 4 or 8 byte values to the output section.
538
539@cindex @code{.align} directive, ARM
540@item .align @var{expression} [, @var{expression}]
541This is the generic @var{.align} directive. For the ARM however if the
542first argument is zero (ie no alignment is needed) the assembler will
543behave as if the argument had been 2 (ie pad to the next four byte
544boundary). This is for compatibility with ARM's own assembler.
545
546@cindex @code{.arch} directive, ARM
547@item .arch @var{name}
548Select the target architecture. Valid values for @var{name} are the same as
549for the @option{-march} commandline option.
550
551Specifying @code{.arch} clears any previously selected architecture
552extensions.
553
554@cindex @code{.arch_extension} directive, ARM
555@item .arch_extension @var{name}
556Add or remove an architecture extension to the target architecture. Valid
557values for @var{name} are the same as those accepted as architectural
558extensions by the @option{-mcpu} commandline option.
559
560@code{.arch_extension} may be used multiple times to add or remove extensions
561incrementally to the architecture being compiled for.
562
563@cindex @code{.arm} directive, ARM
564@item .arm
565This performs the same action as @var{.code 32}.
566
567@anchor{arm_pad}
568@cindex @code{.pad} directive, ARM
569@item .pad #@var{count}
570Generate unwinder annotations for a stack adjustment of @var{count} bytes.
571A positive value indicates the function prologue allocated stack space by
572decrementing the stack pointer.
573
574@c BBBBBBBBBBBBBBBBBBBBBBBBBB
575
576@cindex @code{.bss} directive, ARM
577@item .bss
578This directive switches to the @code{.bss} section.
579
580@c CCCCCCCCCCCCCCCCCCCCCCCCCC
581
582@cindex @code{.cantunwind} directive, ARM
583@item .cantunwind
584Prevents unwinding through the current function. No personality routine
585or exception table data is required or permitted.
586
587@cindex @code{.code} directive, ARM
588@item .code @code{[16|32]}
589This directive selects the instruction set being generated. The value 16
590selects Thumb, with the value 32 selecting ARM.
591
592@cindex @code{.cpu} directive, ARM
593@item .cpu @var{name}
594Select the target processor. Valid values for @var{name} are the same as
595for the @option{-mcpu} commandline option.
596
597Specifying @code{.cpu} clears any previously selected architecture
598extensions.
599
600@c DDDDDDDDDDDDDDDDDDDDDDDDDD
601
602@cindex @code{.dn} and @code{.qn} directives, ARM
603@item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
604@itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
605
606The @code{dn} and @code{qn} directives are used to create typed
607and/or indexed register aliases for use in Advanced SIMD Extension
608(Neon) instructions. The former should be used to create aliases
609of double-precision registers, and the latter to create aliases of
610quad-precision registers.
611
612If these directives are used to create typed aliases, those aliases can
613be used in Neon instructions instead of writing types after the mnemonic
614or after each operand. For example:
615
616@smallexample
617 x .dn d2.f32
618 y .dn d3.f32
619 z .dn d4.f32[1]
620 vmul x,y,z
621@end smallexample
622
623This is equivalent to writing the following:
624
625@smallexample
626 vmul.f32 d2,d3,d4[1]
627@end smallexample
628
629Aliases created using @code{dn} or @code{qn} can be destroyed using
630@code{unreq}.
631
632@c EEEEEEEEEEEEEEEEEEEEEEEEEE
633
634@cindex @code{.eabi_attribute} directive, ARM
635@item .eabi_attribute @var{tag}, @var{value}
636Set the EABI object attribute @var{tag} to @var{value}.
637
638The @var{tag} is either an attribute number, or one of the following:
639@code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
640@code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
641@code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
642@code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
643@code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
644@code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
645@code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
646@code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
647@code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
648@code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
649@code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
650@code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
651@code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
652@code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
653@code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
654@code{Tag_MPextension_use}, @code{Tag_DIV_use},
655@code{Tag_nodefaults}, @code{Tag_also_compatible_with},
656@code{Tag_conformance}, @code{Tag_T2EE_use},
657@code{Tag_Virtualization_use}
658
659The @var{value} is either a @code{number}, @code{"string"}, or
660@code{number, "string"} depending on the tag.
661
662Note - the following legacy values are also accepted by @var{tag}:
663@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
664@code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
665
666@cindex @code{.even} directive, ARM
667@item .even
668This directive aligns to an even-numbered address.
669
670@cindex @code{.extend} directive, ARM
671@cindex @code{.ldouble} directive, ARM
672@item .extend @var{expression} [, @var{expression}]*
673@itemx .ldouble @var{expression} [, @var{expression}]*
674These directives write 12byte long double floating-point values to the
675output section. These are not compatible with current ARM processors
676or ABIs.
677
678@c FFFFFFFFFFFFFFFFFFFFFFFFFF
679
680@anchor{arm_fnend}
681@cindex @code{.fnend} directive, ARM
682@item .fnend
683Marks the end of a function with an unwind table entry. The unwind index
684table entry is created when this directive is processed.
685
686If no personality routine has been specified then standard personality
687routine 0 or 1 will be used, depending on the number of unwind opcodes
688required.
689
690@anchor{arm_fnstart}
691@cindex @code{.fnstart} directive, ARM
692@item .fnstart
693Marks the start of a function with an unwind table entry.
694
695@cindex @code{.force_thumb} directive, ARM
696@item .force_thumb
697This directive forces the selection of Thumb instructions, even if the
698target processor does not support those instructions
699
700@cindex @code{.fpu} directive, ARM
701@item .fpu @var{name}
702Select the floating-point unit to assemble for. Valid values for @var{name}
703are the same as for the @option{-mfpu} commandline option.
704
705@c GGGGGGGGGGGGGGGGGGGGGGGGGG
706@c HHHHHHHHHHHHHHHHHHHHHHHHHH
707
708@cindex @code{.handlerdata} directive, ARM
709@item .handlerdata
710Marks the end of the current function, and the start of the exception table
711entry for that function. Anything between this directive and the
712@code{.fnend} directive will be added to the exception table entry.
713
714Must be preceded by a @code{.personality} or @code{.personalityindex}
715directive.
716
717@c IIIIIIIIIIIIIIIIIIIIIIIIII
718
719@cindex @code{.inst} directive, ARM
720@item .inst @var{opcode} [ , @dots{} ]
721@itemx .inst.n @var{opcode} [ , @dots{} ]
722@itemx .inst.w @var{opcode} [ , @dots{} ]
723Generates the instruction corresponding to the numerical value @var{opcode}.
724@code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
725specified explicitly, overriding the normal encoding rules.
726
727@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
728@c KKKKKKKKKKKKKKKKKKKKKKKKKK
729@c LLLLLLLLLLLLLLLLLLLLLLLLLL
730
731@item .ldouble @var{expression} [, @var{expression}]*
732See @code{.extend}.
733
734@cindex @code{.ltorg} directive, ARM
735@item .ltorg
736This directive causes the current contents of the literal pool to be
737dumped into the current section (which is assumed to be the .text
738section) at the current location (aligned to a word boundary).
739@code{GAS} maintains a separate literal pool for each section and each
740sub-section. The @code{.ltorg} directive will only affect the literal
741pool of the current section and sub-section. At the end of assembly
742all remaining, un-empty literal pools will automatically be dumped.
743
744Note - older versions of @code{GAS} would dump the current literal
745pool any time a section change occurred. This is no longer done, since
746it prevents accurate control of the placement of literal pools.
747
748@c MMMMMMMMMMMMMMMMMMMMMMMMMM
749
750@cindex @code{.movsp} directive, ARM
751@item .movsp @var{reg} [, #@var{offset}]
752Tell the unwinder that @var{reg} contains an offset from the current
753stack pointer. If @var{offset} is not specified then it is assumed to be
754zero.
755
756@c NNNNNNNNNNNNNNNNNNNNNNNNNN
757@c OOOOOOOOOOOOOOOOOOOOOOOOOO
758
759@cindex @code{.object_arch} directive, ARM
760@item .object_arch @var{name}
761Override the architecture recorded in the EABI object attribute section.
762Valid values for @var{name} are the same as for the @code{.arch} directive.
763Typically this is useful when code uses runtime detection of CPU features.
764
765@c PPPPPPPPPPPPPPPPPPPPPPPPPP
766
767@cindex @code{.packed} directive, ARM
768@item .packed @var{expression} [, @var{expression}]*
769This directive writes 12-byte packed floating-point values to the
770output section. These are not compatible with current ARM processors
771or ABIs.
772
773@cindex @code{.pad} directive, ARM
774@item .pad #@var{count}
775Generate unwinder annotations for a stack adjustment of @var{count} bytes.
776A positive value indicates the function prologue allocated stack space by
777decrementing the stack pointer.
778
779@cindex @code{.personality} directive, ARM
780@item .personality @var{name}
781Sets the personality routine for the current function to @var{name}.
782
783@cindex @code{.personalityindex} directive, ARM
784@item .personalityindex @var{index}
785Sets the personality routine for the current function to the EABI standard
786routine number @var{index}
787
788@cindex @code{.pool} directive, ARM
789@item .pool
790This is a synonym for .ltorg.
791
792@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
793@c RRRRRRRRRRRRRRRRRRRRRRRRRR
794
795@cindex @code{.req} directive, ARM
796@item @var{name} .req @var{register name}
797This creates an alias for @var{register name} called @var{name}. For
798example:
799
800@smallexample
801 foo .req r0
802@end smallexample
803
804@c SSSSSSSSSSSSSSSSSSSSSSSSSS
805
806@anchor{arm_save}
807@cindex @code{.save} directive, ARM
808@item .save @var{reglist}
809Generate unwinder annotations to restore the registers in @var{reglist}.
810The format of @var{reglist} is the same as the corresponding store-multiple
811instruction.
812
813@smallexample
814@exdent @emph{core registers}
815 .save @{r4, r5, r6, lr@}
816 stmfd sp!, @{r4, r5, r6, lr@}
817@exdent @emph{FPA registers}
818 .save f4, 2
819 sfmfd f4, 2, [sp]!
820@exdent @emph{VFP registers}
821 .save @{d8, d9, d10@}
822 fstmdx sp!, @{d8, d9, d10@}
823@exdent @emph{iWMMXt registers}
824 .save @{wr10, wr11@}
825 wstrd wr11, [sp, #-8]!
826 wstrd wr10, [sp, #-8]!
827or
828 .save wr11
829 wstrd wr11, [sp, #-8]!
830 .save wr10
831 wstrd wr10, [sp, #-8]!
832@end smallexample
833
834@anchor{arm_setfp}
835@cindex @code{.setfp} directive, ARM
836@item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
837Make all unwinder annotations relative to a frame pointer. Without this
838the unwinder will use offsets from the stack pointer.
839
840The syntax of this directive is the same as the @code{add} or @code{mov}
841instruction used to set the frame pointer. @var{spreg} must be either
842@code{sp} or mentioned in a previous @code{.movsp} directive.
843
844@smallexample
845.movsp ip
846mov ip, sp
847@dots{}
848.setfp fp, ip, #4
849add fp, ip, #4
850@end smallexample
851
852@cindex @code{.secrel32} directive, ARM
853@item .secrel32 @var{expression} [, @var{expression}]*
854This directive emits relocations that evaluate to the section-relative
855offset of each expression's symbol. This directive is only supported
856for PE targets.
857
858@cindex @code{.syntax} directive, ARM
859@item .syntax [@code{unified} | @code{divided}]
860This directive sets the Instruction Set Syntax as described in the
861@ref{ARM-Instruction-Set} section.
862
863@c TTTTTTTTTTTTTTTTTTTTTTTTTT
864
865@cindex @code{.thumb} directive, ARM
866@item .thumb
867This performs the same action as @var{.code 16}.
868
869@cindex @code{.thumb_func} directive, ARM
870@item .thumb_func
871This directive specifies that the following symbol is the name of a
872Thumb encoded function. This information is necessary in order to allow
873the assembler and linker to generate correct code for interworking
874between Arm and Thumb instructions and should be used even if
875interworking is not going to be performed. The presence of this
876directive also implies @code{.thumb}
877
878This directive is not neccessary when generating EABI objects. On these
879targets the encoding is implicit when generating Thumb code.
880
881@cindex @code{.thumb_set} directive, ARM
882@item .thumb_set
883This performs the equivalent of a @code{.set} directive in that it
884creates a symbol which is an alias for another symbol (possibly not yet
885defined). This directive also has the added property in that it marks
886the aliased symbol as being a thumb function entry point, in the same
887way that the @code{.thumb_func} directive does.
888
889@cindex @code{.tlsdescseq} directive, ARM
890@item .tlsdescseq @var{tls-variable}
891This directive is used to annotate parts of an inlined TLS descriptor
892trampoline. Normally the trampoline is provided by the linker, and
893this directive is not needed.
894
895@c UUUUUUUUUUUUUUUUUUUUUUUUUU
896
897@cindex @code{.unreq} directive, ARM
898@item .unreq @var{alias-name}
899This undefines a register alias which was previously defined using the
900@code{req}, @code{dn} or @code{qn} directives. For example:
901
902@smallexample
903 foo .req r0
904 .unreq foo
905@end smallexample
906
907An error occurs if the name is undefined. Note - this pseudo op can
908be used to delete builtin in register name aliases (eg 'r0'). This
909should only be done if it is really necessary.
910
911@cindex @code{.unwind_raw} directive, ARM
912@item .unwind_raw @var{offset}, @var{byte1}, @dots{}
913Insert one of more arbitary unwind opcode bytes, which are known to adjust
914the stack pointer by @var{offset} bytes.
915
916For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
917@code{.save @{r0@}}
918
919@c VVVVVVVVVVVVVVVVVVVVVVVVVV
920
921@cindex @code{.vsave} directive, ARM
922@item .vsave @var{vfp-reglist}
923Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
924using FLDMD. Also works for VFPv3 registers
925that are to be restored using VLDM.
926The format of @var{vfp-reglist} is the same as the corresponding store-multiple
927instruction.
928
929@smallexample
930@exdent @emph{VFP registers}
931 .vsave @{d8, d9, d10@}
932 fstmdd sp!, @{d8, d9, d10@}
933@exdent @emph{VFPv3 registers}
934 .vsave @{d15, d16, d17@}
935 vstm sp!, @{d15, d16, d17@}
936@end smallexample
937
938Since FLDMX and FSTMX are now deprecated, this directive should be
939used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
940
941@c WWWWWWWWWWWWWWWWWWWWWWWWWW
942@c XXXXXXXXXXXXXXXXXXXXXXXXXX
943@c YYYYYYYYYYYYYYYYYYYYYYYYYY
944@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
945
946@end table
947
948@node ARM Opcodes
949@section Opcodes
950
951@cindex ARM opcodes
952@cindex opcodes for ARM
953@code{@value{AS}} implements all the standard ARM opcodes. It also
954implements several pseudo opcodes, including several synthetic load
955instructions.
956
957@table @code
958
959@cindex @code{NOP} pseudo op, ARM
960@item NOP
961@smallexample
962 nop
963@end smallexample
964
965This pseudo op will always evaluate to a legal ARM instruction that does
966nothing. Currently it will evaluate to MOV r0, r0.
967
968@cindex @code{LDR reg,=<label>} pseudo op, ARM
969@item LDR
970@smallexample
971 ldr <register> , = <expression>
972@end smallexample
973
974If expression evaluates to a numeric constant then a MOV or MVN
975instruction will be used in place of the LDR instruction, if the
976constant can be generated by either of these instructions. Otherwise
977the constant will be placed into the nearest literal pool (if it not
978already there) and a PC relative LDR instruction will be generated.
979
980@cindex @code{ADR reg,<label>} pseudo op, ARM
981@item ADR
982@smallexample
983 adr <register> <label>
984@end smallexample
985
986This instruction will load the address of @var{label} into the indicated
987register. The instruction will evaluate to a PC relative ADD or SUB
988instruction depending upon where the label is located. If the label is
989out of range, or if it is not defined in the same file (and section) as
990the ADR instruction, then an error will be generated. This instruction
991will not make use of the literal pool.
992
993@cindex @code{ADRL reg,<label>} pseudo op, ARM
994@item ADRL
995@smallexample
996 adrl <register> <label>
997@end smallexample
998
999This instruction will load the address of @var{label} into the indicated
1000register. The instruction will evaluate to one or two PC relative ADD
1001or SUB instructions depending upon where the label is located. If a
1002second instruction is not needed a NOP instruction will be generated in
1003its place, so that this instruction is always 8 bytes long.
1004
1005If the label is out of range, or if it is not defined in the same file
1006(and section) as the ADRL instruction, then an error will be generated.
1007This instruction will not make use of the literal pool.
1008
1009@end table
1010
1011For information on the ARM or Thumb instruction sets, see @cite{ARM
1012Software Development Toolkit Reference Manual}, Advanced RISC Machines
1013Ltd.
1014
1015@node ARM Mapping Symbols
1016@section Mapping Symbols
1017
1018The ARM ELF specification requires that special symbols be inserted
1019into object files to mark certain features:
1020
1021@table @code
1022
1023@cindex @code{$a}
1024@item $a
1025At the start of a region of code containing ARM instructions.
1026
1027@cindex @code{$t}
1028@item $t
1029At the start of a region of code containing THUMB instructions.
1030
1031@cindex @code{$d}
1032@item $d
1033At the start of a region of data.
1034
1035@end table
1036
1037The assembler will automatically insert these symbols for you - there
1038is no need to code them yourself. Support for tagging symbols ($b,
1039$f, $p and $m) which is also mentioned in the current ARM ELF
1040specification is not implemented. This is because they have been
1041dropped from the new EABI and so tools cannot rely upon their
1042presence.
1043
1044@node ARM Unwinding Tutorial
1045@section Unwinding
1046
1047The ABI for the ARM Architecture specifies a standard format for
1048exception unwind information. This information is used when an
1049exception is thrown to determine where control should be transferred.
1050In particular, the unwind information is used to determine which
1051function called the function that threw the exception, and which
1052function called that one, and so forth. This information is also used
1053to restore the values of callee-saved registers in the function
1054catching the exception.
1055
1056If you are writing functions in assembly code, and those functions
1057call other functions that throw exceptions, you must use assembly
1058pseudo ops to ensure that appropriate exception unwind information is
1059generated. Otherwise, if one of the functions called by your assembly
1060code throws an exception, the run-time library will be unable to
1061unwind the stack through your assembly code and your program will not
1062behave correctly.
1063
1064To illustrate the use of these pseudo ops, we will examine the code
1065that G++ generates for the following C++ input:
1066
1067@verbatim
1068void callee (int *);
1069
1070int
1071caller ()
1072{
1073 int i;
1074 callee (&i);
1075 return i;
1076}
1077@end verbatim
1078
1079This example does not show how to throw or catch an exception from
1080assembly code. That is a much more complex operation and should
1081always be done in a high-level language, such as C++, that directly
1082supports exceptions.
1083
1084The code generated by one particular version of G++ when compiling the
1085example above is:
1086
1087@verbatim
1088_Z6callerv:
1089 .fnstart
1090.LFB2:
1091 @ Function supports interworking.
1092 @ args = 0, pretend = 0, frame = 8
1093 @ frame_needed = 1, uses_anonymous_args = 0
1094 stmfd sp!, {fp, lr}
1095 .save {fp, lr}
1096.LCFI0:
1097 .setfp fp, sp, #4
1098 add fp, sp, #4
1099.LCFI1:
1100 .pad #8
1101 sub sp, sp, #8
1102.LCFI2:
1103 sub r3, fp, #8
1104 mov r0, r3
1105 bl _Z6calleePi
1106 ldr r3, [fp, #-8]
1107 mov r0, r3
1108 sub sp, fp, #4
1109 ldmfd sp!, {fp, lr}
1110 bx lr
1111.LFE2:
1112 .fnend
1113@end verbatim
1114
1115Of course, the sequence of instructions varies based on the options
1116you pass to GCC and on the version of GCC in use. The exact
1117instructions are not important since we are focusing on the pseudo ops
1118that are used to generate unwind information.
1119
1120An important assumption made by the unwinder is that the stack frame
1121does not change during the body of the function. In particular, since
1122we assume that the assembly code does not itself throw an exception,
1123the only point where an exception can be thrown is from a call, such
1124as the @code{bl} instruction above. At each call site, the same saved
1125registers (including @code{lr}, which indicates the return address)
1126must be located in the same locations relative to the frame pointer.
1127
1128The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1129op appears immediately before the first instruction of the function
1130while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1131op appears immediately after the last instruction of the function.
1132These pseudo ops specify the range of the function.
1133
1134Only the order of the other pseudos ops (e.g., @code{.setfp} or
1135@code{.pad}) matters; their exact locations are irrelevant. In the
1136example above, the compiler emits the pseudo ops with particular
1137instructions. That makes it easier to understand the code, but it is
1138not required for correctness. It would work just as well to emit all
1139of the pseudo ops other than @code{.fnend} in the same order, but
1140immediately after @code{.fnstart}.
1141
1142The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1143indicates registers that have been saved to the stack so that they can
1144be restored before the function returns. The argument to the
1145@code{.save} pseudo op is a list of registers to save. If a register
1146is ``callee-saved'' (as specified by the ABI) and is modified by the
1147function you are writing, then your code must save the value before it
1148is modified and restore the original value before the function
1149returns. If an exception is thrown, the run-time library restores the
1150values of these registers from their locations on the stack before
1151returning control to the exception handler. (Of course, if an
1152exception is not thrown, the function that contains the @code{.save}
1153pseudo op restores these registers in the function epilogue, as is
1154done with the @code{ldmfd} instruction above.)
1155
1156You do not have to save callee-saved registers at the very beginning
1157of the function and you do not need to use the @code{.save} pseudo op
1158immediately following the point at which the registers are saved.
1159However, if you modify a callee-saved register, you must save it on
1160the stack before modifying it and before calling any functions which
1161might throw an exception. And, you must use the @code{.save} pseudo
1162op to indicate that you have done so.
1163
1164The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1165modification of the stack pointer that does not save any registers.
1166The argument is the number of bytes (in decimal) that are subtracted
1167from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1168subtracting from the stack pointer increases the size of the stack.)
1169
1170The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1171indicates the register that contains the frame pointer. The first
1172argument is the register that is set, which is typically @code{fp}.
1173The second argument indicates the register from which the frame
1174pointer takes its value. The third argument, if present, is the value
1175(in decimal) added to the register specified by the second argument to
1176compute the value of the frame pointer. You should not modify the
1177frame pointer in the body of the function.
1178
1179If you do not use a frame pointer, then you should not use the
1180@code{.setfp} pseudo op. If you do not use a frame pointer, then you
1181should avoid modifying the stack pointer outside of the function
1182prologue. Otherwise, the run-time library will be unable to find
1183saved registers when it is unwinding the stack.
1184
1185The pseudo ops described above are sufficient for writing assembly
1186code that calls functions which may throw exceptions. If you need to
1187know more about the object-file format used to represent unwind
1188information, you may consult the @cite{Exception Handling ABI for the
1189ARM Architecture} available from @uref{http://infocenter.arm.com}.