Merge branch 'vendor/GCC50'
[dragonfly.git] / contrib / binutils-2.24 / gas / doc / c-sparc.texi
CommitLineData
f40e693d
JM
1@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002, 2008,
2@c 2011
3@c Free Software Foundation, Inc.
4@c This is part of the GAS manual.
5@c For copying conditions, see the file as.texinfo.
6@ifset GENERIC
7@page
8@node Sparc-Dependent
9@chapter SPARC Dependent Features
10@end ifset
11@ifclear GENERIC
12@node Machine Dependencies
13@chapter SPARC Dependent Features
14@end ifclear
15
16@cindex SPARC support
17@menu
18* Sparc-Opts:: Options
19* Sparc-Aligned-Data:: Option to enforce aligned data
20* Sparc-Syntax:: Syntax
21* Sparc-Float:: Floating Point
22* Sparc-Directives:: Sparc Machine Directives
23@end menu
24
25@node Sparc-Opts
26@section Options
27
28@cindex options for SPARC
29@cindex SPARC options
30@cindex architectures, SPARC
31@cindex SPARC architectures
32The SPARC chip family includes several successive versions, using the same
33core instruction set, but including a few additional instructions at
34each version. There are exceptions to this however. For details on what
35instructions each variant supports, please see the chip's architecture
36reference manual.
37
38By default, @code{@value{AS}} assumes the core instruction set (SPARC
39v6), but ``bumps'' the architecture level as needed: it switches to
40successively higher architectures as it encounters instructions that
41only exist in the higher levels.
42
43If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
44past sparclite by default, an option must be passed to enable the
45v9 instructions.
46
47GAS treats sparclite as being compatible with v8, unless an architecture
48is explicitly requested. SPARC v9 is always incompatible with sparclite.
49
50@c The order here is the same as the order of enum sparc_opcode_arch_val
51@c to give the user a sense of the order of the "bumping".
52
53@table @code
54@kindex -Av6
55@kindex -Av7
56@kindex -Av8
57@kindex -Aleon
58@kindex -Asparclet
59@kindex -Asparclite
60@kindex -Av9
61@kindex -Av9a
62@kindex -Av9b
63@kindex -Av9c
64@kindex -Av9d
65@kindex -Av9v
66@kindex -Asparc
67@kindex -Asparcvis
68@kindex -Asparcvis2
69@kindex -Asparcfmaf
70@kindex -Asparcima
71@kindex -Asparcvis3
72@kindex -Asparcvis3r
73@item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
74@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
75@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
76@itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
77@itemx -Asparcvis3 | -Asparcvis3r
78Use one of the @samp{-A} options to select one of the SPARC
79architectures explicitly. If you select an architecture explicitly,
80@code{@value{AS}} reports a fatal error if it encounters an instruction
81or feature requiring an incompatible or higher level.
82
83@samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
84@samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
85
86@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and
87@samp{-Av9v} select a 64 bit environment and are not available unless GAS
88is explicitly configured with 64 bit environment support.
89
90@samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
91UltraSPARC VIS 1.0 extensions.
92
93@samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions,
94as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}.
95
96@samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions,
97as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
98
99@samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused
100multiply-add, VIS 3.0, and HPC extension instructions, as well as the
101instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
102
103@samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional
104memory, floating point unfused multiply-add, integer multiply-add, and
105cache sparing store instructions, as well as the instructions enabled
106by @samp{-Av8plusd} and @samp{-Av9d}.
107
108@samp{-Asparc} specifies a v9 environment. It is equivalent to
109@samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
110
111@samp{-Asparcvis} specifies a v9a environment. It is equivalent to
112@samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise.
113
114@samp{-Asparcvis2} specifies a v9b environment. It is equivalent to
115@samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise.
116
117@samp{-Asparcfmaf} specifies a v9b environment with the floating point
118fused multiply-add instructions enabled.
119
120@samp{-Asparcima} specifies a v9b environment with the integer
121multiply-add instructions enabled.
122
123@samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
124HPC , and floating point fused multiply-add instructions enabled.
125
126@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0,
127HPC, transactional memory, random, and floating point unfused multiply-add
128instructions enabled.
129
130@item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
131@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
132@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v
133@itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
134@itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
135@itemx -xarch=sparcvis3r
136For compatibility with the SunOS v9 assembler. These options are
137equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
138-Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis,
139-Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r,
140respectively.
141
142@item -bump
143Warn whenever it is necessary to switch to another level.
144If an architecture level is explicitly requested, GAS will not issue
145warnings until that level is reached, and will then bump the level
146as required (except between incompatible levels).
147
148@item -32 | -64
149Select the word size, either 32 bits or 64 bits.
150These options are only available with the ELF object file format,
151and require that the necessary BFD support has been included.
152@end table
153
154@node Sparc-Aligned-Data
155@section Enforcing aligned data
156
157@cindex data alignment on SPARC
158@cindex SPARC data alignment
159SPARC GAS normally permits data to be misaligned. For example, it
160permits the @code{.long} pseudo-op to be used on a byte boundary.
161However, the native SunOS assemblers issue an error when they see
162misaligned data.
163
164@kindex --enforce-aligned-data
165You can use the @code{--enforce-aligned-data} option to make SPARC GAS
166also issue an error about misaligned data, just as the SunOS
167assemblers do.
168
169The @code{--enforce-aligned-data} option is not the default because gcc
170issues misaligned data pseudo-ops when it initializes certain packed
171data structures (structures defined using the @code{packed} attribute).
172You may have to assemble with GAS in order to initialize packed data
173structures in your own code.
174
175@cindex SPARC syntax
176@cindex syntax, SPARC
177@node Sparc-Syntax
178@section Sparc Syntax
179The assembler syntax closely follows The Sparc Architecture Manual,
180versions 8 and 9, as well as most extensions defined by Sun
181for their UltraSPARC and Niagara line of processors.
182
183@menu
184* Sparc-Chars:: Special Characters
185* Sparc-Regs:: Register Names
186* Sparc-Constants:: Constant Names
187* Sparc-Relocs:: Relocations
188* Sparc-Size-Translations:: Size Translations
189@end menu
190
191@node Sparc-Chars
192@subsection Special Characters
193
194@cindex line comment character, Sparc
195@cindex Sparc line comment character
196A @samp{!} character appearing anywhere on a line indicates the start
197of a comment that extends to the end of that line.
198
199If a @samp{#} appears as the first character of a line then the whole
200line is treated as a comment, but in this case the line could also be
201a logical line number directive (@pxref{Comments}) or a preprocessor
202control command (@pxref{Preprocessing}).
203
204@cindex line separator, Sparc
205@cindex statement separator, Sparc
206@cindex Sparc line separator
207@samp{;} can be used instead of a newline to separate statements.
208
209@node Sparc-Regs
210@subsection Register Names
211@cindex Sparc registers
212@cindex register names, Sparc
213
214The Sparc integer register file is broken down into global,
215outgoing, local, and incoming.
216
217@itemize @bullet
218@item
219The 8 global registers are referred to as @samp{%g@var{n}}.
220
221@item
222The 8 outgoing registers are referred to as @samp{%o@var{n}}.
223
224@item
225The 8 local registers are referred to as @samp{%l@var{n}}.
226
227@item
228The 8 incoming registers are referred to as @samp{%i@var{n}}.
229
230@item
231The frame pointer register @samp{%i6} can be referenced using
232the alias @samp{%fp}.
233
234@item
235The stack pointer register @samp{%o6} can be referenced using
236the alias @samp{%sp}.
237@end itemize
238
239Floating point registers are simply referred to as @samp{%f@var{n}}.
240When assembling for pre-V9, only 32 floating point registers
241are available. For V9 and later there are 64, but there are
242restrictions when referencing the upper 32 registers. They
243can only be accessed as double or quad, and thus only even
244or quad numbered accesses are allowed. For example, @samp{%f34}
245is a legal floating point register, but @samp{%f35} is not.
246
247Certain V9 instructions allow access to ancillary state registers.
248Most simply they can be referred to as @samp{%asr@var{n}} where
249@var{n} can be from 16 to 31. However, there are some aliases
250defined to reference ASR registers defined for various UltraSPARC
251processors:
252
253@itemize @bullet
254@item
255The tick compare register is referred to as @samp{%tick_cmpr}.
256
257@item
258The system tick register is referred to as @samp{%stick}. An alias,
259@samp{%sys_tick}, exists but is deprecated and should not be used
260by new software.
261
262@item
263The system tick compare register is referred to as @samp{%stick_cmpr}.
264An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should
265not be used by new software.
266
267@item
268The software interrupt register is referred to as @samp{%softint}.
269
270@item
271The set software interrupt register is referred to as @samp{%set_softint}.
272The mnemonic @samp{%softint_set} is provided as an alias.
273
274@item
275The clear software interrupt register is referred to as
276@samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
277as an alias.
278
279@item
280The performance instrumentation counters register is referred to as
281@samp{%pic}.
282
283@item
284The performance control register is referred to as @samp{%pcr}.
285
286@item
287The graphics status register is referred to as @samp{%gsr}.
288
289@item
290The V9 dispatch control register is referred to as @samp{%dcr}.
291@end itemize
292
293Various V9 branch and conditional move instructions allow
294specification of which set of integer condition codes to
295test. These are referred to as @samp{%xcc} and @samp{%icc}.
296
297In V9, there are 4 sets of floating point condition codes
298which are referred to as @samp{%fcc@var{n}}.
299
300Several special privileged and non-privileged registers
301exist:
302
303@itemize @bullet
304@item
305The V9 address space identifier register is referred to as @samp{%asi}.
306
307@item
308The V9 restorable windows register is referred to as @samp{%canrestore}.
309
310@item
311The V9 savable windows register is referred to as @samp{%cansave}.
312
313@item
314The V9 clean windows register is referred to as @samp{%cleanwin}.
315
316@item
317The V9 current window pointer register is referred to as @samp{%cwp}.
318
319@item
320The floating-point queue register is referred to as @samp{%fq}.
321
322@item
323The V8 co-processor queue register is referred to as @samp{%cq}.
324
325@item
326The floating point status register is referred to as @samp{%fsr}.
327
328@item
329The other windows register is referred to as @samp{%otherwin}.
330
331@item
332The V9 program counter register is referred to as @samp{%pc}.
333
334@item
335The V9 next program counter register is referred to as @samp{%npc}.
336
337@item
338The V9 processor interrupt level register is referred to as @samp{%pil}.
339
340@item
341The V9 processor state register is referred to as @samp{%pstate}.
342
343@item
344The trap base address register is referred to as @samp{%tba}.
345
346@item
347The V9 tick register is referred to as @samp{%tick}.
348
349@item
350The V9 trap level is referred to as @samp{%tl}.
351
352@item
353The V9 trap program counter is referred to as @samp{%tpc}.
354
355@item
356The V9 trap next program counter is referred to as @samp{%tnpc}.
357
358@item
359The V9 trap state is referred to as @samp{%tstate}.
360
361@item
362The V9 trap type is referred to as @samp{%tt}.
363
364@item
365The V9 condition codes is referred to as @samp{%ccr}.
366
367@item
368The V9 floating-point registers state is referred to as @samp{%fprs}.
369
370@item
371The V9 version register is referred to as @samp{%ver}.
372
373@item
374The V9 window state register is referred to as @samp{%wstate}.
375
376@item
377The Y register is referred to as @samp{%y}.
378
379@item
380The V8 window invalid mask register is referred to as @samp{%wim}.
381
382@item
383The V8 processor state register is referred to as @samp{%psr}.
384
385@item
386The V9 global register level register is referred to as @samp{%gl}.
387@end itemize
388
389Several special register names exist for hypervisor mode code:
390
391@itemize @bullet
392@item
393The hyperprivileged processor state register is referred to as
394@samp{%hpstate}.
395
396@item
397The hyperprivileged trap state register is referred to as @samp{%htstate}.
398
399@item
400The hyperprivileged interrupt pending register is referred to as
401@samp{%hintp}.
402
403@item
404The hyperprivileged trap base address register is referred to as
405@samp{%htba}.
406
407@item
408The hyperprivileged implementation version register is referred
409to as @samp{%hver}.
410
411@item
412The hyperprivileged system tick compare register is referred
413to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick}
414register, the normal @samp{%stick} is used.
415@end itemize
416
417@node Sparc-Constants
418@subsection Constants
419@cindex Sparc constants
420@cindex constants, Sparc
421
422Several Sparc instructions take an immediate operand field for
423which mnemonic names exist. Two such examples are @samp{membar}
424and @samp{prefetch}. Another example are the set of V9
425memory access instruction that allow specification of an
426address space identifier.
427
428The @samp{membar} instruction specifies a memory barrier that is
429the defined by the operand which is a bitmask. The supported
430mask mnemonics are:
431
432@itemize @bullet
433@item
434@samp{#Sync} requests that all operations (including nonmemory
435reference operations) appearing prior to the @code{membar} must have
436been performed and the effects of any exceptions become visible before
437any instructions after the @code{membar} may be initiated. This
438corresponds to @code{membar} cmask field bit 2.
439
440@item
441@samp{#MemIssue} requests that all memory reference operations
442appearing prior to the @code{membar} must have been performed before
443any memory operation after the @code{membar} may be initiated. This
444corresponds to @code{membar} cmask field bit 1.
445
446@item
447@samp{#Lookaside} requests that a store appearing prior to the
448@code{membar} must complete before any load following the
449@code{membar} referencing the same address can be initiated. This
450corresponds to @code{membar} cmask field bit 0.
451
452@item
453@samp{#StoreStore} defines that the effects of all stores appearing
454prior to the @code{membar} instruction must be visible to all
455processors before the effect of any stores following the
456@code{membar}. Equivalent to the deprecated @code{stbar} instruction.
457This corresponds to @code{membar} mmask field bit 3.
458
459@item
460@samp{#LoadStore} defines all loads appearing prior to the
461@code{membar} instruction must have been performed before the effect
462of any stores following the @code{membar} is visible to any other
463processor. This corresponds to @code{membar} mmask field bit 2.
464
465@item
466@samp{#StoreLoad} defines that the effects of all stores appearing
467prior to the @code{membar} instruction must be visible to all
468processors before loads following the @code{membar} may be performed.
469This corresponds to @code{membar} mmask field bit 1.
470
471@item
472@samp{#LoadLoad} defines that all loads appearing prior to the
473@code{membar} instruction must have been performed before any loads
474following the @code{membar} may be performed. This corresponds to
475@code{membar} mmask field bit 0.
476
477@end itemize
478
479These values can be ored together, for example:
480
481@example
482membar #Sync
483membar #StoreLoad | #LoadLoad
484membar #StoreLoad | #StoreStore
485@end example
486
487The @code{prefetch} and @code{prefetcha} instructions take a prefetch
488function code. The following prefetch function code constant
489mnemonics are available:
490
491@itemize @bullet
492@item
493@samp{#n_reads} requests a prefetch for several reads, and corresponds
494to a prefetch function code of 0.
495
496@samp{#one_read} requests a prefetch for one read, and corresponds
497to a prefetch function code of 1.
498
499@samp{#n_writes} requests a prefetch for several writes (and possibly
500reads), and corresponds to a prefetch function code of 2.
501
502@samp{#one_write} requests a prefetch for one write, and corresponds
503to a prefetch function code of 3.
504
505@samp{#page} requests a prefetch page, and corresponds to a prefetch
506function code of 4.
507
508@samp{#invalidate} requests a prefetch invalidate, and corresponds to
509a prefetch function code of 16.
510
511@samp{#unified} requests a prefetch to the nearest unified cache, and
512corresponds to a prefetch function code of 17.
513
514@samp{#n_reads_strong} requests a strong prefetch for several reads,
515and corresponds to a prefetch function code of 20.
516
517@samp{#one_read_strong} requests a strong prefetch for one read,
518and corresponds to a prefetch function code of 21.
519
520@samp{#n_writes_strong} requests a strong prefetch for several writes,
521and corresponds to a prefetch function code of 22.
522
523@samp{#one_write_strong} requests a strong prefetch for one write,
524and corresponds to a prefetch function code of 23.
525
526Onle one prefetch code may be specified. Here are some examples:
527
528@example
529prefetch [%l0 + %l2], #one_read
530prefetch [%g2 + 8], #n_writes
531prefetcha [%g1] 0x8, #unified
532prefetcha [%o0 + 0x10] %asi, #n_reads
533@end example
534
535The actual behavior of a given prefetch function code is processor
536specific. If a processor does not implement a given prefetch
537function code, it will treat the prefetch instruction as a nop.
538
539For instructions that accept an immediate address space identifier,
540@code{@value{AS}} provides many mnemonics corresponding to
541V9 defined as well as UltraSPARC and Niagara extended values.
542For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}.
543See the V9 and processor specific manuals for details.
544
545@end itemize
546
547@node Sparc-Relocs
548@subsection Relocations
549@cindex Sparc relocations
550@cindex relocations, Sparc
551
552ELF relocations are available as defined in the 32-bit and 64-bit
553Sparc ELF specifications.
554
555@code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10}
556is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is
557obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained
558using @samp{%lox}. For example:
559
560@example
561sethi %hi(symbol), %g1
562or %g1, %lo(symbol), %g1
563
564sethi %hix(symbol), %g1
565xor %g1, %lox(symbol), %g1
566@end example
567
568These ``high'' mnemonics extract bits 31:10 of their operand,
569and the ``low'' mnemonics extract bits 9:0 of their operand.
570
571V9 code model relocations can be requested as follows:
572
573@itemize @bullet
574@item
575@code{R_SPARC_HH22} is requested using @samp{%hh}. It can
576also be generated using @samp{%uhi}.
577@item
578@code{R_SPARC_HM10} is requested using @samp{%hm}. It can
579also be generated using @samp{%ulo}.
580@item
581@code{R_SPARC_LM22} is requested using @samp{%lm}.
582
583@item
584@code{R_SPARC_H44} is requested using @samp{%h44}.
585@item
586@code{R_SPARC_M44} is requested using @samp{%m44}.
587@item
588@code{R_SPARC_L44} is requested using @samp{%l44} or @samp{%l34}.
589@item
590@code{R_SPARC_H34} is requested using @samp{%h34}.
591@end itemize
592
593The @samp{%l34} generates a @code{R_SPARC_L44} relocation because it
594calculates the necessary value, and therefore no explicit
595@code{R_SPARC_L34} relocation needed to be created for this purpose.
596
597The @samp{%h34} and @samp{%l34} relocations are used for the abs34 code
598model. Here is an example abs34 address generation sequence:
599
600@example
601sethi %h34(symbol), %g1
602sllx %g1, 2, %g1
603or %g1, %l34(symbol), %g1
604@end example
605
606The PC relative relocation @code{R_SPARC_PC22} can be obtained by
607enclosing an operand inside of @samp{%pc22}. Likewise, the
608@code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
609These are mostly used when assembling PIC code. For example, the
610standard PIC sequence on Sparc to get the base of the global offset
611table, PC relative, into a register, can be performed as:
612
613@example
614sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
615add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
616@end example
617
618Several relocations exist to allow the link editor to potentially
619optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22}
620relocation can obtained by enclosing an operand inside of
621@samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10}
622relocation can obtained by enclosing an operand inside of
623@samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be
624obtained by enclosing an operand inside of @samp{%gdop}.
625For example, assuming the GOT base is in register @code{%l7}:
626
627@example
628sethi %gdop_hix22(symbol), %l1
629xor %l1, %gdop_lox10(symbol), %l1
630ld [%l7 + %l1], %l2, %gdop(symbol)
631@end example
632
633There are many relocations that can be requested for access to
634thread local storage variables. All of the Sparc TLS mnemonics
635are supported:
636
637@itemize @bullet
638@item
639@code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}.
640@item
641@code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}.
642@item
643@code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}.
644@item
645@code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}.
646
647@item
648@code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}.
649@item
650@code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}.
651@item
652@code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}.
653@item
654@code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}.
655
656@item
657@code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}.
658@item
659@code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}.
660@item
661@code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}.
662
663@item
664@code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}.
665@item
666@code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}.
667@item
668@code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}.
669@item
670@code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}.
671@item
672@code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}.
673
674@item
675@code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}.
676@item
677@code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}.
678@end itemize
679
680Here are some example TLS model sequences.
681
682First, General Dynamic:
683
684@example
685sethi %tgd_hi22(symbol), %l1
686add %l1, %tgd_lo10(symbol), %l1
687add %l7, %l1, %o0, %tgd_add(symbol)
688call __tls_get_addr, %tgd_call(symbol)
689nop
690@end example
691
692Local Dynamic:
693
694@example
695sethi %tldm_hi22(symbol), %l1
696add %l1, %tldm_lo10(symbol), %l1
697add %l7, %l1, %o0, %tldm_add(symbol)
698call __tls_get_addr, %tldm_call(symbol)
699nop
700
701sethi %tldo_hix22(symbol), %l1
702xor %l1, %tldo_lox10(symbol), %l1
703add %o0, %l1, %l1, %tldo_add(symbol)
704@end example
705
706Initial Exec:
707
708@example
709sethi %tie_hi22(symbol), %l1
710add %l1, %tie_lo10(symbol), %l1
711ld [%l7 + %l1], %o0, %tie_ld(symbol)
712add %g7, %o0, %o0, %tie_add(symbol)
713
714sethi %tie_hi22(symbol), %l1
715add %l1, %tie_lo10(symbol), %l1
716ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
717add %g7, %o0, %o0, %tie_add(symbol)
718@end example
719
720And finally, Local Exec:
721
722@example
723sethi %tle_hix22(symbol), %l1
724add %l1, %tle_lox10(symbol), %l1
725add %g7, %l1, %l1
726@end example
727
728When assembling for 64-bit, and a secondary constant addend is
729specified in an address expression that would normally generate
730an @code{R_SPARC_LO10} relocation, the assembler will emit an
731@code{R_SPARC_OLO10} instead.
732
733@node Sparc-Size-Translations
734@subsection Size Translations
735@cindex Sparc size translations
736@cindex size, translations, Sparc
737
738Often it is desirable to write code in an operand size agnostic
739manner. @code{@value{AS}} provides support for this via
740operand size opcode translations. Translations are supported
741for loads, stores, shifts, compare-and-swap atomics, and the
742@samp{clr} synthetic instruction.
743
744If generating 32-bit code, @code{@value{AS}} will generate the
74532-bit opcode. Whereas if 64-bit code is being generated,
746the 64-bit opcode will be emitted. For example @code{ldn}
747will be transformed into @code{ld} for 32-bit code and
748@code{ldx} for 64-bit code.
749
750Here is an example meant to demonstrate all the supported
751opcode translations:
752
753@example
754ldn [%o0], %o1
755ldna [%o0] %asi, %o2
756stn %o1, [%o0]
757stna %o2, [%o0] %asi
758slln %o3, 3, %o3
759srln %o4, 8, %o4
760sran %o5, 12, %o5
761casn [%o0], %o1, %o2
762casna [%o0] %asi, %o1, %o2
763clrn %g1
764@end example
765
766In 32-bit mode @code{@value{AS}} will emit:
767
768@example
769ld [%o0], %o1
770lda [%o0] %asi, %o2
771st %o1, [%o0]
772sta %o2, [%o0] %asi
773sll %o3, 3, %o3
774srl %o4, 8, %o4
775sra %o5, 12, %o5
776cas [%o0], %o1, %o2
777casa [%o0] %asi, %o1, %o2
778clr %g1
779@end example
780
781And in 64-bit mode @code{@value{AS}} will emit:
782
783@example
784ldx [%o0], %o1
785ldxa [%o0] %asi, %o2
786stx %o1, [%o0]
787stxa %o2, [%o0] %asi
788sllx %o3, 3, %o3
789srlx %o4, 8, %o4
790srax %o5, 12, %o5
791casx [%o0], %o1, %o2
792casxa [%o0] %asi, %o1, %o2
793clrx %g1
794@end example
795
796Finally, the @samp{.nword} translating directive is supported
797as well. It is documented in the section on Sparc machine
798directives.
799
800@node Sparc-Float
801@section Floating Point
802
803@cindex floating point, SPARC (@sc{ieee})
804@cindex SPARC floating point (@sc{ieee})
805The Sparc uses @sc{ieee} floating-point numbers.
806
807@node Sparc-Directives
808@section Sparc Machine Directives
809
810@cindex SPARC machine directives
811@cindex machine directives, SPARC
812The Sparc version of @code{@value{AS}} supports the following additional
813machine directives:
814
815@table @code
816@cindex @code{align} directive, SPARC
817@item .align
818This must be followed by the desired alignment in bytes.
819
820@cindex @code{common} directive, SPARC
821@item .common
822This must be followed by a symbol name, a positive number, and
823@code{"bss"}. This behaves somewhat like @code{.comm}, but the
824syntax is different.
825
826@cindex @code{half} directive, SPARC
827@item .half
828This is functionally identical to @code{.short}.
829
830@cindex @code{nword} directive, SPARC
831@item .nword
832On the Sparc, the @code{.nword} directive produces native word sized value,
833ie. if assembling with -32 it is equivalent to @code{.word}, if assembling
834with -64 it is equivalent to @code{.xword}.
835
836@cindex @code{proc} directive, SPARC
837@item .proc
838This directive is ignored. Any text following it on the same
839line is also ignored.
840
841@cindex @code{register} directive, SPARC
842@item .register
843This directive declares use of a global application or system register.
844It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
845the symbol name for that register. If symbol name is @code{#scratch},
846it is a scratch register, if it is @code{#ignore}, it just suppresses any
847errors about using undeclared global register, but does not emit any
848information about it into the object file. This can be useful e.g. if you
849save the register before use and restore it after.
850
851@cindex @code{reserve} directive, SPARC
852@item .reserve
853This must be followed by a symbol name, a positive number, and
854@code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
855syntax is different.
856
857@cindex @code{seg} directive, SPARC
858@item .seg
859This must be followed by @code{"text"}, @code{"data"}, or
860@code{"data1"}. It behaves like @code{.text}, @code{.data}, or
861@code{.data 1}.
862
863@cindex @code{skip} directive, SPARC
864@item .skip
865This is functionally identical to the @code{.space} directive.
866
867@cindex @code{word} directive, SPARC
868@item .word
869On the Sparc, the @code{.word} directive produces 32 bit values,
870instead of the 16 bit values it produces on many other machines.
871
872@cindex @code{xword} directive, SPARC
873@item .xword
874On the Sparc V9 processor, the @code{.xword} directive produces
87564 bit values.
876@end table