Upgrade GDB from 7.4.1 to 7.6.1 on the vendor branch
[dragonfly.git] / contrib / gdb-7 / gdb / i387-tdep.c
CommitLineData
5796c8dc
SS
1/* Intel 387 floating point stuff.
2
ef5ccd6c 3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5796c8dc
SS
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20#include "defs.h"
21#include "doublest.h"
22#include "floatformat.h"
23#include "frame.h"
24#include "gdbcore.h"
25#include "inferior.h"
26#include "language.h"
27#include "regcache.h"
28#include "value.h"
29
30#include "gdb_assert.h"
31#include "gdb_string.h"
32
33#include "i386-tdep.h"
34#include "i387-tdep.h"
cf7f2e2d 35#include "i386-xstate.h"
5796c8dc
SS
36
37/* Print the floating point number specified by RAW. */
38
39static void
40print_i387_value (struct gdbarch *gdbarch,
41 const gdb_byte *raw, struct ui_file *file)
42{
43 DOUBLEST value;
44
45 /* Using extract_typed_floating here might affect the representation
46 of certain numbers such as NaNs, even if GDB is running natively.
47 This is fine since our caller already detects such special
48 numbers and we print the hexadecimal representation anyway. */
49 value = extract_typed_floating (raw, i387_ext_type (gdbarch));
50
51 /* We try to print 19 digits. The last digit may or may not contain
52 garbage, but we'd better print one too many. We need enough room
53 to print the value, 1 position for the sign, 1 for the decimal
54 point, 19 for the digits and 6 for the exponent adds up to 27. */
55#ifdef PRINTF_HAS_LONG_DOUBLE
56 fprintf_filtered (file, " %-+27.19Lg", (long double) value);
57#else
58 fprintf_filtered (file, " %-+27.19g", (double) value);
59#endif
60}
61
62/* Print the classification for the register contents RAW. */
63
64static void
65print_i387_ext (struct gdbarch *gdbarch,
66 const gdb_byte *raw, struct ui_file *file)
67{
68 int sign;
69 int integer;
70 unsigned int exponent;
71 unsigned long fraction[2];
72
73 sign = raw[9] & 0x80;
74 integer = raw[7] & 0x80;
75 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
76 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
77 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
78 | (raw[5] << 8) | raw[4]);
79
80 if (exponent == 0x7fff && integer)
81 {
82 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000)
83 /* Infinity. */
84 fprintf_filtered (file, " %cInf", (sign ? '-' : '+'));
85 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000)
86 /* Real Indefinite (QNaN). */
87 fputs_unfiltered (" Real Indefinite (QNaN)", file);
88 else if (fraction[1] & 0x40000000)
89 /* QNaN. */
90 fputs_filtered (" QNaN", file);
91 else
92 /* SNaN. */
93 fputs_filtered (" SNaN", file);
94 }
95 else if (exponent < 0x7fff && exponent > 0x0000 && integer)
96 /* Normal. */
97 print_i387_value (gdbarch, raw, file);
98 else if (exponent == 0x0000)
99 {
100 /* Denormal or zero. */
101 print_i387_value (gdbarch, raw, file);
102
103 if (integer)
104 /* Pseudo-denormal. */
105 fputs_filtered (" Pseudo-denormal", file);
106 else if (fraction[0] || fraction[1])
107 /* Denormal. */
108 fputs_filtered (" Denormal", file);
109 }
110 else
111 /* Unsupported. */
112 fputs_filtered (" Unsupported", file);
113}
114
ef5ccd6c
JM
115/* Print the status word STATUS. If STATUS_P is false, then STATUS
116 was unavailable. */
5796c8dc
SS
117
118static void
ef5ccd6c
JM
119print_i387_status_word (int status_p,
120 unsigned int status, struct ui_file *file)
5796c8dc 121{
ef5ccd6c
JM
122 fprintf_filtered (file, "Status Word: ");
123 if (!status_p)
124 {
125 fprintf_filtered (file, "%s\n", _("<unavailable>"));
126 return;
127 }
128
129 fprintf_filtered (file, "%s", hex_string_custom (status, 4));
5796c8dc
SS
130 fputs_filtered (" ", file);
131 fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " ");
132 fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " ");
133 fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " ");
134 fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " ");
135 fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " ");
136 fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " ");
137 fputs_filtered (" ", file);
138 fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " ");
139 fputs_filtered (" ", file);
140 fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " ");
141 fputs_filtered (" ", file);
142 fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " ");
143 fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " ");
144 fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " ");
145 fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " ");
146
147 fputs_filtered ("\n", file);
148
149 fprintf_filtered (file,
150 " TOP: %d\n", ((status >> 11) & 7));
151}
152
ef5ccd6c
JM
153/* Print the control word CONTROL. If CONTROL_P is false, then
154 CONTROL was unavailable. */
5796c8dc
SS
155
156static void
ef5ccd6c
JM
157print_i387_control_word (int control_p,
158 unsigned int control, struct ui_file *file)
5796c8dc 159{
ef5ccd6c
JM
160 fprintf_filtered (file, "Control Word: ");
161 if (!control_p)
162 {
163 fprintf_filtered (file, "%s\n", _("<unavailable>"));
164 return;
165 }
166
167 fprintf_filtered (file, "%s", hex_string_custom (control, 4));
5796c8dc
SS
168 fputs_filtered (" ", file);
169 fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " ");
170 fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " ");
171 fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " ");
172 fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " ");
173 fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " ");
174 fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " ");
175
176 fputs_filtered ("\n", file);
177
178 fputs_filtered (" PC: ", file);
179 switch ((control >> 8) & 3)
180 {
181 case 0:
182 fputs_filtered ("Single Precision (24-bits)\n", file);
183 break;
184 case 1:
185 fputs_filtered ("Reserved\n", file);
186 break;
187 case 2:
188 fputs_filtered ("Double Precision (53-bits)\n", file);
189 break;
190 case 3:
191 fputs_filtered ("Extended Precision (64-bits)\n", file);
192 break;
193 }
194
195 fputs_filtered (" RC: ", file);
196 switch ((control >> 10) & 3)
197 {
198 case 0:
199 fputs_filtered ("Round to nearest\n", file);
200 break;
201 case 1:
202 fputs_filtered ("Round down\n", file);
203 break;
204 case 2:
205 fputs_filtered ("Round up\n", file);
206 break;
207 case 3:
208 fputs_filtered ("Round toward zero\n", file);
209 break;
210 }
211}
212
213/* Print out the i387 floating point state. Note that we ignore FRAME
214 in the code below. That's OK since floating-point registers are
215 never saved on the stack. */
216
217void
218i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
219 struct frame_info *frame, const char *args)
220{
221 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
5796c8dc 222 ULONGEST fctrl;
ef5ccd6c 223 int fctrl_p;
5796c8dc 224 ULONGEST fstat;
ef5ccd6c 225 int fstat_p;
5796c8dc 226 ULONGEST ftag;
ef5ccd6c 227 int ftag_p;
5796c8dc 228 ULONGEST fiseg;
ef5ccd6c 229 int fiseg_p;
5796c8dc 230 ULONGEST fioff;
ef5ccd6c 231 int fioff_p;
5796c8dc 232 ULONGEST foseg;
ef5ccd6c 233 int foseg_p;
5796c8dc 234 ULONGEST fooff;
ef5ccd6c 235 int fooff_p;
5796c8dc 236 ULONGEST fop;
ef5ccd6c 237 int fop_p;
5796c8dc
SS
238 int fpreg;
239 int top;
240
241 gdb_assert (gdbarch == get_frame_arch (frame));
242
ef5ccd6c
JM
243 fctrl_p = read_frame_register_unsigned (frame,
244 I387_FCTRL_REGNUM (tdep), &fctrl);
245 fstat_p = read_frame_register_unsigned (frame,
246 I387_FSTAT_REGNUM (tdep), &fstat);
247 ftag_p = read_frame_register_unsigned (frame,
248 I387_FTAG_REGNUM (tdep), &ftag);
249 fiseg_p = read_frame_register_unsigned (frame,
250 I387_FISEG_REGNUM (tdep), &fiseg);
251 fioff_p = read_frame_register_unsigned (frame,
252 I387_FIOFF_REGNUM (tdep), &fioff);
253 foseg_p = read_frame_register_unsigned (frame,
254 I387_FOSEG_REGNUM (tdep), &foseg);
255 fooff_p = read_frame_register_unsigned (frame,
256 I387_FOOFF_REGNUM (tdep), &fooff);
257 fop_p = read_frame_register_unsigned (frame,
258 I387_FOP_REGNUM (tdep), &fop);
259
260 if (fstat_p)
261 {
262 top = ((fstat >> 11) & 7);
5796c8dc 263
ef5ccd6c
JM
264 for (fpreg = 7; fpreg >= 0; fpreg--)
265 {
266 struct value *regval;
267 int regnum;
268 int i;
269 int tag = -1;
5796c8dc 270
ef5ccd6c 271 fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg);
5796c8dc 272
ef5ccd6c
JM
273 if (ftag_p)
274 {
275 tag = (ftag >> (fpreg * 2)) & 3;
276
277 switch (tag)
278 {
279 case 0:
280 fputs_filtered ("Valid ", file);
281 break;
282 case 1:
283 fputs_filtered ("Zero ", file);
284 break;
285 case 2:
286 fputs_filtered ("Special ", file);
287 break;
288 case 3:
289 fputs_filtered ("Empty ", file);
290 break;
291 }
292 }
293 else
294 fputs_filtered ("Unknown ", file);
5796c8dc 295
ef5ccd6c
JM
296 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep);
297 regval = get_frame_register_value (frame, regnum);
5796c8dc 298
ef5ccd6c
JM
299 if (value_entirely_available (regval))
300 {
301 const gdb_byte *raw = value_contents (regval);
5796c8dc 302
ef5ccd6c
JM
303 fputs_filtered ("0x", file);
304 for (i = 9; i >= 0; i--)
305 fprintf_filtered (file, "%02x", raw[i]);
5796c8dc 306
ef5ccd6c
JM
307 if (tag != -1 && tag != 3)
308 print_i387_ext (gdbarch, raw, file);
309 }
310 else
311 fprintf_filtered (file, "%s", _("<unavailable>"));
5796c8dc 312
ef5ccd6c
JM
313 fputs_filtered ("\n", file);
314 }
5796c8dc
SS
315 }
316
317 fputs_filtered ("\n", file);
ef5ccd6c
JM
318 print_i387_status_word (fstat_p, fstat, file);
319 print_i387_control_word (fctrl_p, fctrl, file);
5796c8dc 320 fprintf_filtered (file, "Tag Word: %s\n",
ef5ccd6c 321 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>"));
5796c8dc 322 fprintf_filtered (file, "Instruction Pointer: %s:",
ef5ccd6c
JM
323 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>"));
324 fprintf_filtered (file, "%s\n",
325 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>"));
5796c8dc 326 fprintf_filtered (file, "Operand Pointer: %s:",
ef5ccd6c
JM
327 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>"));
328 fprintf_filtered (file, "%s\n",
329 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>"));
5796c8dc 330 fprintf_filtered (file, "Opcode: %s\n",
ef5ccd6c
JM
331 fop_p
332 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4))
333 : _("<unavailable>"));
5796c8dc
SS
334}
335\f
336
337/* Return nonzero if a value of type TYPE stored in register REGNUM
338 needs any special handling. */
339
340int
c50c785c
JM
341i387_convert_register_p (struct gdbarch *gdbarch, int regnum,
342 struct type *type)
5796c8dc
SS
343{
344 if (i386_fp_regnum_p (gdbarch, regnum))
345 {
346 /* Floating point registers must be converted unless we are
347 accessing them in their hardware type. */
348 if (type == i387_ext_type (gdbarch))
349 return 0;
350 else
351 return 1;
352 }
353
354 return 0;
355}
356
357/* Read a value of type TYPE from register REGNUM in frame FRAME, and
358 return its contents in TO. */
359
c50c785c 360int
5796c8dc 361i387_register_to_value (struct frame_info *frame, int regnum,
c50c785c
JM
362 struct type *type, gdb_byte *to,
363 int *optimizedp, int *unavailablep)
5796c8dc
SS
364{
365 struct gdbarch *gdbarch = get_frame_arch (frame);
366 gdb_byte from[I386_MAX_REGISTER_SIZE];
367
368 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
369
370 /* We only support floating-point values. */
371 if (TYPE_CODE (type) != TYPE_CODE_FLT)
372 {
373 warning (_("Cannot convert floating-point register value "
374 "to non-floating-point type."));
c50c785c
JM
375 *optimizedp = *unavailablep = 0;
376 return 0;
5796c8dc
SS
377 }
378
379 /* Convert to TYPE. */
c50c785c
JM
380 if (!get_frame_register_bytes (frame, regnum, 0, TYPE_LENGTH (type),
381 from, optimizedp, unavailablep))
382 return 0;
383
5796c8dc 384 convert_typed_floating (from, i387_ext_type (gdbarch), to, type);
c50c785c
JM
385 *optimizedp = *unavailablep = 0;
386 return 1;
5796c8dc
SS
387}
388
389/* Write the contents FROM of a value of type TYPE into register
390 REGNUM in frame FRAME. */
391
392void
393i387_value_to_register (struct frame_info *frame, int regnum,
394 struct type *type, const gdb_byte *from)
395{
396 struct gdbarch *gdbarch = get_frame_arch (frame);
397 gdb_byte to[I386_MAX_REGISTER_SIZE];
398
399 gdb_assert (i386_fp_regnum_p (gdbarch, regnum));
400
401 /* We only support floating-point values. */
402 if (TYPE_CODE (type) != TYPE_CODE_FLT)
403 {
404 warning (_("Cannot convert non-floating-point type "
405 "to floating-point register value."));
406 return;
407 }
408
409 /* Convert from TYPE. */
410 convert_typed_floating (from, type, to, i387_ext_type (gdbarch));
411 put_frame_register (frame, regnum, to);
412}
413\f
414
415/* Handle FSAVE and FXSAVE formats. */
416
417/* At fsave_offset[REGNUM] you'll find the offset to the location in
418 the data structure used by the "fsave" instruction where GDB
419 register REGNUM is stored. */
420
421static int fsave_offset[] =
422{
423 28 + 0 * 10, /* %st(0) ... */
424 28 + 1 * 10,
425 28 + 2 * 10,
426 28 + 3 * 10,
427 28 + 4 * 10,
428 28 + 5 * 10,
429 28 + 6 * 10,
430 28 + 7 * 10, /* ... %st(7). */
431 0, /* `fctrl' (16 bits). */
432 4, /* `fstat' (16 bits). */
433 8, /* `ftag' (16 bits). */
434 16, /* `fiseg' (16 bits). */
435 12, /* `fioff'. */
436 24, /* `foseg' (16 bits). */
437 20, /* `fooff'. */
438 18 /* `fop' (bottom 11 bits). */
439};
440
441#define FSAVE_ADDR(tdep, fsave, regnum) \
442 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)])
443\f
444
445/* Fill register REGNUM in REGCACHE with the appropriate value from
446 *FSAVE. This function masks off any of the reserved bits in
447 *FSAVE. */
448
449void
450i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave)
451{
452 struct gdbarch *gdbarch = get_regcache_arch (regcache);
453 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
454 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
455 const gdb_byte *regs = fsave;
456 int i;
457
458 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
459
460 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
461 if (regnum == -1 || regnum == i)
462 {
463 if (fsave == NULL)
464 {
465 regcache_raw_supply (regcache, i, NULL);
466 continue;
467 }
468
469 /* Most of the FPU control registers occupy only 16 bits in the
470 fsave area. Give those a special treatment. */
471 if (i >= I387_FCTRL_REGNUM (tdep)
472 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
473 {
474 gdb_byte val[4];
475
476 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2);
477 val[2] = val[3] = 0;
478 if (i == I387_FOP_REGNUM (tdep))
479 val[1] &= ((1 << 3) - 1);
480 regcache_raw_supply (regcache, i, val);
481 }
482 else
483 regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i));
484 }
485
486 /* Provide dummy values for the SSE registers. */
487 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
488 if (regnum == -1 || regnum == i)
489 regcache_raw_supply (regcache, i, NULL);
490 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep))
491 {
492 gdb_byte buf[4];
493
494 store_unsigned_integer (buf, 4, byte_order, 0x1f80);
495 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf);
496 }
497}
498
499/* Fill register REGNUM (if it is a floating-point register) in *FSAVE
500 with the value from REGCACHE. If REGNUM is -1, do this for all
501 registers. This function doesn't touch any of the reserved bits in
502 *FSAVE. */
503
504void
505i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave)
506{
507 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
508 gdb_byte *regs = fsave;
509 int i;
510
511 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
512
513 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
514 if (regnum == -1 || regnum == i)
515 {
516 /* Most of the FPU control registers occupy only 16 bits in
517 the fsave area. Give those a special treatment. */
518 if (i >= I387_FCTRL_REGNUM (tdep)
519 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
520 {
521 gdb_byte buf[4];
522
523 regcache_raw_collect (regcache, i, buf);
524
525 if (i == I387_FOP_REGNUM (tdep))
526 {
527 /* The opcode occupies only 11 bits. Make sure we
528 don't touch the other bits. */
529 buf[1] &= ((1 << 3) - 1);
530 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
531 }
532 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2);
533 }
534 else
535 regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i));
536 }
537}
538\f
539
540/* At fxsave_offset[REGNUM] you'll find the offset to the location in
541 the data structure used by the "fxsave" instruction where GDB
542 register REGNUM is stored. */
543
544static int fxsave_offset[] =
545{
546 32, /* %st(0) through ... */
547 48,
548 64,
549 80,
550 96,
551 112,
552 128,
553 144, /* ... %st(7) (80 bits each). */
554 0, /* `fctrl' (16 bits). */
555 2, /* `fstat' (16 bits). */
556 4, /* `ftag' (16 bits). */
557 12, /* `fiseg' (16 bits). */
558 8, /* `fioff'. */
559 20, /* `foseg' (16 bits). */
560 16, /* `fooff'. */
561 6, /* `fop' (bottom 11 bits). */
562 160 + 0 * 16, /* %xmm0 through ... */
563 160 + 1 * 16,
564 160 + 2 * 16,
565 160 + 3 * 16,
566 160 + 4 * 16,
567 160 + 5 * 16,
568 160 + 6 * 16,
569 160 + 7 * 16,
570 160 + 8 * 16,
571 160 + 9 * 16,
572 160 + 10 * 16,
573 160 + 11 * 16,
574 160 + 12 * 16,
575 160 + 13 * 16,
576 160 + 14 * 16,
577 160 + 15 * 16, /* ... %xmm15 (128 bits each). */
578};
579
580#define FXSAVE_ADDR(tdep, fxsave, regnum) \
581 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)])
582
583/* We made an unfortunate choice in putting %mxcsr after the SSE
584 registers %xmm0-%xmm7 instead of before, since it makes supporting
585 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we
586 don't include the offset for %mxcsr here above. */
587
588#define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24)
589
590static int i387_tag (const gdb_byte *raw);
591\f
592
593/* Fill register REGNUM in REGCACHE with the appropriate
594 floating-point or SSE register value from *FXSAVE. This function
595 masks off any of the reserved bits in *FXSAVE. */
596
597void
598i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave)
599{
600 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
601 const gdb_byte *regs = fxsave;
602 int i;
603
604 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
605 gdb_assert (tdep->num_xmm_regs > 0);
606
607 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
608 if (regnum == -1 || regnum == i)
609 {
610 if (regs == NULL)
611 {
612 regcache_raw_supply (regcache, i, NULL);
613 continue;
614 }
615
616 /* Most of the FPU control registers occupy only 16 bits in
617 the fxsave area. Give those a special treatment. */
618 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
619 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
620 {
621 gdb_byte val[4];
622
623 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
624 val[2] = val[3] = 0;
625 if (i == I387_FOP_REGNUM (tdep))
626 val[1] &= ((1 << 3) - 1);
627 else if (i== I387_FTAG_REGNUM (tdep))
628 {
629 /* The fxsave area contains a simplified version of
630 the tag word. We have to look at the actual 80-bit
631 FP data to recreate the traditional i387 tag word. */
632
633 unsigned long ftag = 0;
634 int fpreg;
635 int top;
636
637 top = ((FXSAVE_ADDR (tdep, regs,
638 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
639 top &= 0x7;
640
641 for (fpreg = 7; fpreg >= 0; fpreg--)
642 {
643 int tag;
644
645 if (val[0] & (1 << fpreg))
646 {
c50c785c
JM
647 int thisreg = (fpreg + 8 - top) % 8
648 + I387_ST0_REGNUM (tdep);
649 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
5796c8dc
SS
650 }
651 else
652 tag = 3; /* Empty */
653
654 ftag |= tag << (2 * fpreg);
655 }
656 val[0] = ftag & 0xff;
657 val[1] = (ftag >> 8) & 0xff;
658 }
659 regcache_raw_supply (regcache, i, val);
660 }
661 else
662 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
663 }
664
665 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
666 {
667 if (regs == NULL)
668 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL);
669 else
670 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
671 FXSAVE_MXCSR_ADDR (regs));
672 }
673}
674
675/* Fill register REGNUM (if it is a floating-point or SSE register) in
676 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
677 all registers. This function doesn't touch any of the reserved
678 bits in *FXSAVE. */
679
680void
681i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave)
682{
683 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
684 gdb_byte *regs = fxsave;
685 int i;
686
687 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
688 gdb_assert (tdep->num_xmm_regs > 0);
689
690 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++)
691 if (regnum == -1 || regnum == i)
692 {
693 /* Most of the FPU control registers occupy only 16 bits in
694 the fxsave area. Give those a special treatment. */
695 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep)
696 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep))
697 {
698 gdb_byte buf[4];
699
700 regcache_raw_collect (regcache, i, buf);
701
702 if (i == I387_FOP_REGNUM (tdep))
703 {
704 /* The opcode occupies only 11 bits. Make sure we
705 don't touch the other bits. */
706 buf[1] &= ((1 << 3) - 1);
707 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
708 }
709 else if (i == I387_FTAG_REGNUM (tdep))
710 {
711 /* Converting back is much easier. */
712
713 unsigned short ftag;
714 int fpreg;
715
716 ftag = (buf[1] << 8) | buf[0];
717 buf[0] = 0;
718 buf[1] = 0;
719
cf7f2e2d
JM
720 for (fpreg = 7; fpreg >= 0; fpreg--)
721 {
722 int tag = (ftag >> (fpreg * 2)) & 3;
723
724 if (tag != 3)
725 buf[0] |= (1 << fpreg);
726 }
727 }
728 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
729 }
730 else
731 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
732 }
733
734 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
735 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
736 FXSAVE_MXCSR_ADDR (regs));
737}
738
739/* `xstate_bv' is at byte offset 512. */
740#define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512)
741
742/* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in
743 the upper 128bit of AVX register data structure used by the "xsave"
744 instruction where GDB register REGNUM is stored. */
745
746static int xsave_avxh_offset[] =
747{
748 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */
749 576 + 1 * 16,
750 576 + 2 * 16,
751 576 + 3 * 16,
752 576 + 4 * 16,
753 576 + 5 * 16,
754 576 + 6 * 16,
755 576 + 7 * 16,
756 576 + 8 * 16,
757 576 + 9 * 16,
758 576 + 10 * 16,
759 576 + 11 * 16,
760 576 + 12 * 16,
761 576 + 13 * 16,
762 576 + 14 * 16,
763 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */
764};
765
766#define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \
767 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)])
768
769/* Similar to i387_supply_fxsave, but use XSAVE extended state. */
770
771void
772i387_supply_xsave (struct regcache *regcache, int regnum,
773 const void *xsave)
774{
775 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
776 const gdb_byte *regs = xsave;
777 int i;
778 unsigned int clear_bv;
a45ae5f8 779 static const gdb_byte zero[MAX_REGISTER_SIZE] = { 0 };
cf7f2e2d
JM
780 enum
781 {
782 none = 0x0,
783 x87 = 0x1,
784 sse = 0x2,
785 avxh = 0x4,
786 all = x87 | sse | avxh
787 } regclass;
788
ef5ccd6c 789 gdb_assert (regs != NULL);
cf7f2e2d
JM
790 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
791 gdb_assert (tdep->num_xmm_regs > 0);
792
793 if (regnum == -1)
794 regclass = all;
795 else if (regnum >= I387_YMM0H_REGNUM (tdep)
796 && regnum < I387_YMMENDH_REGNUM (tdep))
797 regclass = avxh;
798 else if (regnum >= I387_XMM0_REGNUM(tdep)
799 && regnum < I387_MXCSR_REGNUM (tdep))
800 regclass = sse;
801 else if (regnum >= I387_ST0_REGNUM (tdep)
802 && regnum < I387_FCTRL_REGNUM (tdep))
803 regclass = x87;
804 else
805 regclass = none;
806
ef5ccd6c 807 if (regclass != none)
cf7f2e2d
JM
808 {
809 /* Get `xstat_bv'. */
810 const gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
811
812 /* The supported bits in `xstat_bv' are 1 byte. Clear part in
813 vector registers if its bit in xstat_bv is zero. */
814 clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
815 }
816 else
817 clear_bv = I386_XSTATE_AVX_MASK;
818
a45ae5f8
JM
819 /* With the delayed xsave mechanism, in between the program
820 starting, and the program accessing the vector registers for the
821 first time, the register's values are invalid. The kernel
822 initializes register states to zero when they are set the first
823 time in a program. This means that from the user-space programs'
824 perspective, it's the same as if the registers have always been
825 zero from the start of the program. Therefore, the debugger
ef5ccd6c 826 should provide the same illusion to the user. */
a45ae5f8 827
cf7f2e2d
JM
828 switch (regclass)
829 {
830 case none:
831 break;
832
833 case avxh:
834 if ((clear_bv & I386_XSTATE_AVX))
ef5ccd6c 835 regcache_raw_supply (regcache, regnum, zero);
cf7f2e2d 836 else
a45ae5f8
JM
837 regcache_raw_supply (regcache, regnum,
838 XSAVE_AVXH_ADDR (tdep, regs, regnum));
cf7f2e2d
JM
839 return;
840
841 case sse:
842 if ((clear_bv & I386_XSTATE_SSE))
ef5ccd6c 843 regcache_raw_supply (regcache, regnum, zero);
cf7f2e2d 844 else
a45ae5f8
JM
845 regcache_raw_supply (regcache, regnum,
846 FXSAVE_ADDR (tdep, regs, regnum));
cf7f2e2d
JM
847 return;
848
849 case x87:
850 if ((clear_bv & I386_XSTATE_X87))
ef5ccd6c 851 regcache_raw_supply (regcache, regnum, zero);
cf7f2e2d 852 else
a45ae5f8
JM
853 regcache_raw_supply (regcache, regnum,
854 FXSAVE_ADDR (tdep, regs, regnum));
cf7f2e2d
JM
855 return;
856
857 case all:
a45ae5f8 858 /* Handle the upper YMM registers. */
cf7f2e2d
JM
859 if ((tdep->xcr0 & I386_XSTATE_AVX))
860 {
861 if ((clear_bv & I386_XSTATE_AVX))
a45ae5f8
JM
862 {
863 for (i = I387_YMM0H_REGNUM (tdep);
864 i < I387_YMMENDH_REGNUM (tdep);
865 i++)
ef5ccd6c 866 regcache_raw_supply (regcache, i, zero);
a45ae5f8 867 }
cf7f2e2d 868 else
cf7f2e2d 869 {
a45ae5f8
JM
870 for (i = I387_YMM0H_REGNUM (tdep);
871 i < I387_YMMENDH_REGNUM (tdep);
872 i++)
873 regcache_raw_supply (regcache, i,
874 XSAVE_AVXH_ADDR (tdep, regs, i));
cf7f2e2d
JM
875 }
876 }
877
878 /* Handle the XMM registers. */
879 if ((tdep->xcr0 & I386_XSTATE_SSE))
880 {
881 if ((clear_bv & I386_XSTATE_SSE))
a45ae5f8
JM
882 {
883 for (i = I387_XMM0_REGNUM (tdep);
884 i < I387_MXCSR_REGNUM (tdep);
885 i++)
ef5ccd6c 886 regcache_raw_supply (regcache, i, zero);
a45ae5f8 887 }
cf7f2e2d 888 else
cf7f2e2d 889 {
a45ae5f8
JM
890 for (i = I387_XMM0_REGNUM (tdep);
891 i < I387_MXCSR_REGNUM (tdep); i++)
892 regcache_raw_supply (regcache, i,
893 FXSAVE_ADDR (tdep, regs, i));
cf7f2e2d
JM
894 }
895 }
896
897 /* Handle the x87 registers. */
898 if ((tdep->xcr0 & I386_XSTATE_X87))
899 {
900 if ((clear_bv & I386_XSTATE_X87))
a45ae5f8
JM
901 {
902 for (i = I387_ST0_REGNUM (tdep);
903 i < I387_FCTRL_REGNUM (tdep);
904 i++)
ef5ccd6c 905 regcache_raw_supply (regcache, i, zero);
a45ae5f8 906 }
cf7f2e2d 907 else
cf7f2e2d 908 {
a45ae5f8
JM
909 for (i = I387_ST0_REGNUM (tdep);
910 i < I387_FCTRL_REGNUM (tdep);
911 i++)
912 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
cf7f2e2d
JM
913 }
914 }
915 break;
916 }
917
918 /* Only handle x87 control registers. */
919 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
920 if (regnum == -1 || regnum == i)
921 {
cf7f2e2d
JM
922 /* Most of the FPU control registers occupy only 16 bits in
923 the xsave extended state. Give those a special treatment. */
924 if (i != I387_FIOFF_REGNUM (tdep)
925 && i != I387_FOOFF_REGNUM (tdep))
926 {
927 gdb_byte val[4];
928
929 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2);
930 val[2] = val[3] = 0;
931 if (i == I387_FOP_REGNUM (tdep))
932 val[1] &= ((1 << 3) - 1);
933 else if (i== I387_FTAG_REGNUM (tdep))
934 {
935 /* The fxsave area contains a simplified version of
936 the tag word. We have to look at the actual 80-bit
937 FP data to recreate the traditional i387 tag word. */
938
939 unsigned long ftag = 0;
940 int fpreg;
941 int top;
942
943 top = ((FXSAVE_ADDR (tdep, regs,
944 I387_FSTAT_REGNUM (tdep)))[1] >> 3);
945 top &= 0x7;
946
947 for (fpreg = 7; fpreg >= 0; fpreg--)
948 {
949 int tag;
950
951 if (val[0] & (1 << fpreg))
952 {
c50c785c 953 int thisreg = (fpreg + 8 - top) % 8
cf7f2e2d 954 + I387_ST0_REGNUM (tdep);
c50c785c 955 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg));
cf7f2e2d
JM
956 }
957 else
958 tag = 3; /* Empty */
959
960 ftag |= tag << (2 * fpreg);
961 }
962 val[0] = ftag & 0xff;
963 val[1] = (ftag >> 8) & 0xff;
964 }
965 regcache_raw_supply (regcache, i, val);
966 }
967 else
968 regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i));
969 }
970
971 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
ef5ccd6c
JM
972 regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep),
973 FXSAVE_MXCSR_ADDR (regs));
cf7f2e2d
JM
974}
975
976/* Similar to i387_collect_fxsave, but use XSAVE extended state. */
977
978void
979i387_collect_xsave (const struct regcache *regcache, int regnum,
980 void *xsave, int gcore)
981{
982 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
983 gdb_byte *regs = xsave;
984 int i;
985 enum
986 {
987 none = 0x0,
988 check = 0x1,
989 x87 = 0x2 | check,
990 sse = 0x4 | check,
991 avxh = 0x8 | check,
992 all = x87 | sse | avxh
993 } regclass;
994
995 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM);
996 gdb_assert (tdep->num_xmm_regs > 0);
997
998 if (regnum == -1)
999 regclass = all;
1000 else if (regnum >= I387_YMM0H_REGNUM (tdep)
1001 && regnum < I387_YMMENDH_REGNUM (tdep))
1002 regclass = avxh;
1003 else if (regnum >= I387_XMM0_REGNUM(tdep)
1004 && regnum < I387_MXCSR_REGNUM (tdep))
1005 regclass = sse;
1006 else if (regnum >= I387_ST0_REGNUM (tdep)
1007 && regnum < I387_FCTRL_REGNUM (tdep))
1008 regclass = x87;
1009 else
1010 regclass = none;
1011
1012 if (gcore)
1013 {
1014 /* Clear XSAVE extended state. */
1015 memset (regs, 0, I386_XSTATE_SIZE (tdep->xcr0));
1016
1017 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */
1018 if (tdep->xsave_xcr0_offset != -1)
1019 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8);
1020 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8);
1021 }
1022
1023 if ((regclass & check))
1024 {
1025 gdb_byte raw[I386_MAX_REGISTER_SIZE];
1026 gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs);
1027 unsigned int xstate_bv = 0;
c50c785c 1028 /* The supported bits in `xstat_bv' are 1 byte. */
cf7f2e2d
JM
1029 unsigned int clear_bv = (~(*xstate_bv_p)) & tdep->xcr0;
1030 gdb_byte *p;
1031
1032 /* Clear register set if its bit in xstat_bv is zero. */
1033 if (clear_bv)
1034 {
1035 if ((clear_bv & I386_XSTATE_AVX))
1036 for (i = I387_YMM0H_REGNUM (tdep);
1037 i < I387_YMMENDH_REGNUM (tdep); i++)
1038 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16);
1039
1040 if ((clear_bv & I386_XSTATE_SSE))
1041 for (i = I387_XMM0_REGNUM (tdep);
1042 i < I387_MXCSR_REGNUM (tdep); i++)
1043 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16);
1044
1045 if ((clear_bv & I386_XSTATE_X87))
1046 for (i = I387_ST0_REGNUM (tdep);
1047 i < I387_FCTRL_REGNUM (tdep); i++)
1048 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10);
1049 }
1050
1051 if (regclass == all)
1052 {
1053 /* Check if any upper YMM registers are changed. */
1054 if ((tdep->xcr0 & I386_XSTATE_AVX))
1055 for (i = I387_YMM0H_REGNUM (tdep);
1056 i < I387_YMMENDH_REGNUM (tdep); i++)
1057 {
1058 regcache_raw_collect (regcache, i, raw);
1059 p = XSAVE_AVXH_ADDR (tdep, regs, i);
1060 if (memcmp (raw, p, 16))
1061 {
1062 xstate_bv |= I386_XSTATE_AVX;
1063 memcpy (p, raw, 16);
1064 }
1065 }
1066
1067 /* Check if any SSE registers are changed. */
1068 if ((tdep->xcr0 & I386_XSTATE_SSE))
1069 for (i = I387_XMM0_REGNUM (tdep);
1070 i < I387_MXCSR_REGNUM (tdep); i++)
1071 {
1072 regcache_raw_collect (regcache, i, raw);
1073 p = FXSAVE_ADDR (tdep, regs, i);
1074 if (memcmp (raw, p, 16))
1075 {
1076 xstate_bv |= I386_XSTATE_SSE;
1077 memcpy (p, raw, 16);
1078 }
1079 }
1080
1081 /* Check if any X87 registers are changed. */
1082 if ((tdep->xcr0 & I386_XSTATE_X87))
1083 for (i = I387_ST0_REGNUM (tdep);
1084 i < I387_FCTRL_REGNUM (tdep); i++)
1085 {
1086 regcache_raw_collect (regcache, i, raw);
1087 p = FXSAVE_ADDR (tdep, regs, i);
1088 if (memcmp (raw, p, 10))
1089 {
1090 xstate_bv |= I386_XSTATE_X87;
1091 memcpy (p, raw, 10);
1092 }
1093 }
1094 }
1095 else
1096 {
1097 /* Check if REGNUM is changed. */
1098 regcache_raw_collect (regcache, regnum, raw);
1099
1100 switch (regclass)
1101 {
1102 default:
1103 internal_error (__FILE__, __LINE__,
1104 _("invalid i387 regclass"));
1105
1106 case avxh:
1107 /* This is an upper YMM register. */
1108 p = XSAVE_AVXH_ADDR (tdep, regs, regnum);
1109 if (memcmp (raw, p, 16))
1110 {
1111 xstate_bv |= I386_XSTATE_AVX;
1112 memcpy (p, raw, 16);
1113 }
1114 break;
1115
1116 case sse:
1117 /* This is an SSE register. */
1118 p = FXSAVE_ADDR (tdep, regs, regnum);
1119 if (memcmp (raw, p, 16))
1120 {
1121 xstate_bv |= I386_XSTATE_SSE;
1122 memcpy (p, raw, 16);
1123 }
1124 break;
1125
1126 case x87:
1127 /* This is an x87 register. */
1128 p = FXSAVE_ADDR (tdep, regs, regnum);
1129 if (memcmp (raw, p, 10))
1130 {
1131 xstate_bv |= I386_XSTATE_X87;
1132 memcpy (p, raw, 10);
1133 }
1134 break;
1135 }
1136 }
1137
1138 /* Update the corresponding bits in `xstate_bv' if any SSE/AVX
1139 registers are changed. */
1140 if (xstate_bv)
1141 {
1142 /* The supported bits in `xstat_bv' are 1 byte. */
1143 *xstate_bv_p |= (gdb_byte) xstate_bv;
1144
1145 switch (regclass)
1146 {
1147 default:
1148 internal_error (__FILE__, __LINE__,
1149 _("invalid i387 regclass"));
1150
1151 case all:
1152 break;
1153
1154 case x87:
1155 case sse:
1156 case avxh:
1157 /* Register REGNUM has been updated. Return. */
1158 return;
1159 }
1160 }
1161 else
1162 {
1163 /* Return if REGNUM isn't changed. */
1164 if (regclass != all)
1165 return;
1166 }
1167 }
1168
1169 /* Only handle x87 control registers. */
1170 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++)
1171 if (regnum == -1 || regnum == i)
1172 {
1173 /* Most of the FPU control registers occupy only 16 bits in
1174 the xsave extended state. Give those a special treatment. */
1175 if (i != I387_FIOFF_REGNUM (tdep)
1176 && i != I387_FOOFF_REGNUM (tdep))
1177 {
1178 gdb_byte buf[4];
1179
1180 regcache_raw_collect (regcache, i, buf);
1181
1182 if (i == I387_FOP_REGNUM (tdep))
1183 {
1184 /* The opcode occupies only 11 bits. Make sure we
1185 don't touch the other bits. */
1186 buf[1] &= ((1 << 3) - 1);
1187 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1));
1188 }
1189 else if (i == I387_FTAG_REGNUM (tdep))
1190 {
1191 /* Converting back is much easier. */
1192
1193 unsigned short ftag;
1194 int fpreg;
1195
1196 ftag = (buf[1] << 8) | buf[0];
1197 buf[0] = 0;
1198 buf[1] = 0;
1199
5796c8dc
SS
1200 for (fpreg = 7; fpreg >= 0; fpreg--)
1201 {
1202 int tag = (ftag >> (fpreg * 2)) & 3;
1203
1204 if (tag != 3)
1205 buf[0] |= (1 << fpreg);
1206 }
1207 }
1208 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2);
1209 }
1210 else
1211 regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i));
1212 }
1213
1214 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1)
1215 regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep),
1216 FXSAVE_MXCSR_ADDR (regs));
1217}
1218
1219/* Recreate the FTW (tag word) valid bits from the 80-bit FP data in
1220 *RAW. */
1221
1222static int
1223i387_tag (const gdb_byte *raw)
1224{
1225 int integer;
1226 unsigned int exponent;
1227 unsigned long fraction[2];
1228
1229 integer = raw[7] & 0x80;
1230 exponent = (((raw[9] & 0x7f) << 8) | raw[8]);
1231 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]);
1232 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16)
1233 | (raw[5] << 8) | raw[4]);
1234
1235 if (exponent == 0x7fff)
1236 {
1237 /* Special. */
1238 return (2);
1239 }
1240 else if (exponent == 0x0000)
1241 {
1242 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer)
1243 {
1244 /* Zero. */
1245 return (1);
1246 }
1247 else
1248 {
1249 /* Special. */
1250 return (2);
1251 }
1252 }
1253 else
1254 {
1255 if (integer)
1256 {
1257 /* Valid. */
1258 return (0);
1259 }
1260 else
1261 {
1262 /* Special. */
1263 return (2);
1264 }
1265 }
1266}
1267
1268/* Prepare the FPU stack in REGCACHE for a function return. */
1269
1270void
1271i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache)
1272{
1273 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1274 ULONGEST fstat;
1275
1276 /* Set the top of the floating-point register stack to 7. The
1277 actual value doesn't really matter, but 7 is what a normal
1278 function return would end up with if the program started out with
1279 a freshly initialized FPU. */
1280 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
1281 fstat |= (7 << 11);
1282 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
1283
1284 /* Mark %st(1) through %st(7) as empty. Since we set the top of the
1285 floating-point register stack to 7, the appropriate value for the
1286 tag word is 0x3fff. */
1287 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
1288
1289}