Upgrade GDB from 7.4.1 to 7.6.1 on the vendor branch
[dragonfly.git] / contrib / gdb-7 / opcodes / i386-dis.c
CommitLineData
5796c8dc
SS
1/* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
ef5ccd6c 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
5796c8dc
SS
4 Free Software Foundation, Inc.
5
6 This file is part of the GNU opcodes library.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
22
23
24/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
25 July 1988
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
29
30/* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
36
37#include "sysdep.h"
38#include "dis-asm.h"
39#include "opintl.h"
40#include "opcode/i386.h"
41#include "libiberty.h"
42
43#include <setjmp.h>
44
5796c8dc
SS
45static int print_insn (bfd_vma, disassemble_info *);
46static void dofloat (int);
47static void OP_ST (int, int);
48static void OP_STi (int, int);
49static int putop (const char *, int);
50static void oappend (const char *);
51static void append_seg (void);
52static void OP_indirE (int, int);
53static void print_operand_value (char *, int, bfd_vma);
54static void OP_E_register (int, int);
55static void OP_E_memory (int, int);
5796c8dc
SS
56static void print_displacement (char *, bfd_vma);
57static void OP_E (int, int);
58static void OP_G (int, int);
59static bfd_vma get64 (void);
60static bfd_signed_vma get32 (void);
61static bfd_signed_vma get32s (void);
62static int get16 (void);
63static void set_op (bfd_vma, int);
64static void OP_Skip_MODRM (int, int);
65static void OP_REG (int, int);
66static void OP_IMREG (int, int);
67static void OP_I (int, int);
68static void OP_I64 (int, int);
69static void OP_sI (int, int);
70static void OP_J (int, int);
71static void OP_SEG (int, int);
72static void OP_DIR (int, int);
73static void OP_OFF (int, int);
74static void OP_OFF64 (int, int);
75static void ptr_reg (int, int);
76static void OP_ESreg (int, int);
77static void OP_DSreg (int, int);
78static void OP_C (int, int);
79static void OP_D (int, int);
80static void OP_T (int, int);
81static void OP_R (int, int);
82static void OP_MMX (int, int);
83static void OP_XMM (int, int);
84static void OP_EM (int, int);
85static void OP_EX (int, int);
86static void OP_EMC (int,int);
87static void OP_MXC (int,int);
88static void OP_MS (int, int);
89static void OP_XS (int, int);
90static void OP_M (int, int);
91static void OP_VEX (int, int);
5796c8dc
SS
92static void OP_EX_Vex (int, int);
93static void OP_EX_VexW (int, int);
cf7f2e2d 94static void OP_EX_VexImmW (int, int);
5796c8dc
SS
95static void OP_XMM_Vex (int, int);
96static void OP_XMM_VexW (int, int);
97static void OP_REG_VexI4 (int, int);
98static void PCLMUL_Fixup (int, int);
99static void VEXI4_Fixup (int, int);
100static void VZERO_Fixup (int, int);
101static void VCMP_Fixup (int, int);
102static void OP_0f07 (int, int);
103static void OP_Monitor (int, int);
104static void OP_Mwait (int, int);
105static void NOP_Fixup1 (int, int);
106static void NOP_Fixup2 (int, int);
107static void OP_3DNowSuffix (int, int);
108static void CMP_Fixup (int, int);
109static void BadOp (void);
110static void REP_Fixup (int, int);
ef5ccd6c
JM
111static void HLE_Fixup1 (int, int);
112static void HLE_Fixup2 (int, int);
113static void HLE_Fixup3 (int, int);
5796c8dc
SS
114static void CMPXCHG8B_Fixup (int, int);
115static void XMM_Fixup (int, int);
116static void CRC32_Fixup (int, int);
cf7f2e2d
JM
117static void FXSAVE_Fixup (int, int);
118static void OP_LWPCB_E (int, int);
119static void OP_LWP_E (int, int);
120static void OP_Vex_2src_1 (int, int);
121static void OP_Vex_2src_2 (int, int);
5796c8dc
SS
122
123static void MOVBE_Fixup (int, int);
124
125struct dis_private {
126 /* Points to first byte not fetched. */
127 bfd_byte *max_fetched;
128 bfd_byte the_buffer[MAX_MNEM_SIZE];
129 bfd_vma insn_start;
130 int orig_sizeflag;
131 jmp_buf bailout;
132};
133
134enum address_mode
135{
136 mode_16bit,
137 mode_32bit,
138 mode_64bit
139};
140
141enum address_mode address_mode;
142
143/* Flags for the prefixes for the current instruction. See below. */
144static int prefixes;
145
146/* REX prefix the current instruction. See below. */
147static int rex;
148/* Bits of REX we've already used. */
149static int rex_used;
cf7f2e2d 150/* REX bits in original REX prefix ignored. */
5796c8dc
SS
151static int rex_ignored;
152/* Mark parts used in the REX prefix. When we are testing for
153 empty prefix (for 8bit register REX extension), just mask it
154 out. Otherwise test for REX bit is excuse for existence of REX
155 only in case value is nonzero. */
156#define USED_REX(value) \
157 { \
158 if (value) \
159 { \
160 if ((rex & value)) \
161 rex_used |= (value) | REX_OPCODE; \
162 } \
163 else \
164 rex_used |= REX_OPCODE; \
165 }
166
167/* Flags for prefixes which we somehow handled when printing the
168 current instruction. */
169static int used_prefixes;
170
171/* Flags stored in PREFIXES. */
172#define PREFIX_REPZ 1
173#define PREFIX_REPNZ 2
174#define PREFIX_LOCK 4
175#define PREFIX_CS 8
176#define PREFIX_SS 0x10
177#define PREFIX_DS 0x20
178#define PREFIX_ES 0x40
179#define PREFIX_FS 0x80
180#define PREFIX_GS 0x100
181#define PREFIX_DATA 0x200
182#define PREFIX_ADDR 0x400
183#define PREFIX_FWAIT 0x800
184
185/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
186 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
187 on error. */
188#define FETCH_DATA(info, addr) \
189 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
190 ? 1 : fetch_data ((info), (addr)))
191
192static int
193fetch_data (struct disassemble_info *info, bfd_byte *addr)
194{
195 int status;
196 struct dis_private *priv = (struct dis_private *) info->private_data;
197 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
198
199 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
200 status = (*info->read_memory_func) (start,
201 priv->max_fetched,
202 addr - priv->max_fetched,
203 info);
204 else
205 status = -1;
206 if (status != 0)
207 {
208 /* If we did manage to read at least one byte, then
209 print_insn_i386 will do something sensible. Otherwise, print
210 an error. We do that here because this is where we know
211 STATUS. */
212 if (priv->max_fetched == priv->the_buffer)
213 (*info->memory_error_func) (status, start, info);
214 longjmp (priv->bailout, 1);
215 }
216 else
217 priv->max_fetched = addr;
218 return 1;
219}
220
221#define XX { NULL, 0 }
cf7f2e2d 222#define Bad_Opcode NULL, { { NULL, 0 } }
5796c8dc
SS
223
224#define Eb { OP_E, b_mode }
225#define EbS { OP_E, b_swap_mode }
226#define Ev { OP_E, v_mode }
227#define EvS { OP_E, v_swap_mode }
228#define Ed { OP_E, d_mode }
229#define Edq { OP_E, dq_mode }
230#define Edqw { OP_E, dqw_mode }
231#define Edqb { OP_E, dqb_mode }
232#define Edqd { OP_E, dqd_mode }
233#define Eq { OP_E, q_mode }
234#define indirEv { OP_indirE, stack_v_mode }
235#define indirEp { OP_indirE, f_mode }
236#define stackEv { OP_E, stack_v_mode }
237#define Em { OP_E, m_mode }
238#define Ew { OP_E, w_mode }
239#define M { OP_M, 0 } /* lea, lgdt, etc. */
240#define Ma { OP_M, a_mode }
241#define Mb { OP_M, b_mode }
242#define Md { OP_M, d_mode }
243#define Mo { OP_M, o_mode }
244#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
245#define Mq { OP_M, q_mode }
246#define Mx { OP_M, x_mode }
247#define Mxmm { OP_M, xmm_mode }
248#define Gb { OP_G, b_mode }
249#define Gv { OP_G, v_mode }
250#define Gd { OP_G, d_mode }
251#define Gdq { OP_G, dq_mode }
252#define Gm { OP_G, m_mode }
253#define Gw { OP_G, w_mode }
254#define Rd { OP_R, d_mode }
255#define Rm { OP_R, m_mode }
256#define Ib { OP_I, b_mode }
257#define sIb { OP_sI, b_mode } /* sign extened byte */
c50c785c 258#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
5796c8dc 259#define Iv { OP_I, v_mode }
ef5ccd6c 260#define sIv { OP_sI, v_mode }
5796c8dc
SS
261#define Iq { OP_I, q_mode }
262#define Iv64 { OP_I64, v_mode }
263#define Iw { OP_I, w_mode }
264#define I1 { OP_I, const_1_mode }
265#define Jb { OP_J, b_mode }
266#define Jv { OP_J, v_mode }
267#define Cm { OP_C, m_mode }
268#define Dm { OP_D, m_mode }
269#define Td { OP_T, d_mode }
270#define Skip_MODRM { OP_Skip_MODRM, 0 }
271
272#define RMeAX { OP_REG, eAX_reg }
273#define RMeBX { OP_REG, eBX_reg }
274#define RMeCX { OP_REG, eCX_reg }
275#define RMeDX { OP_REG, eDX_reg }
276#define RMeSP { OP_REG, eSP_reg }
277#define RMeBP { OP_REG, eBP_reg }
278#define RMeSI { OP_REG, eSI_reg }
279#define RMeDI { OP_REG, eDI_reg }
280#define RMrAX { OP_REG, rAX_reg }
281#define RMrBX { OP_REG, rBX_reg }
282#define RMrCX { OP_REG, rCX_reg }
283#define RMrDX { OP_REG, rDX_reg }
284#define RMrSP { OP_REG, rSP_reg }
285#define RMrBP { OP_REG, rBP_reg }
286#define RMrSI { OP_REG, rSI_reg }
287#define RMrDI { OP_REG, rDI_reg }
288#define RMAL { OP_REG, al_reg }
5796c8dc
SS
289#define RMCL { OP_REG, cl_reg }
290#define RMDL { OP_REG, dl_reg }
291#define RMBL { OP_REG, bl_reg }
292#define RMAH { OP_REG, ah_reg }
293#define RMCH { OP_REG, ch_reg }
294#define RMDH { OP_REG, dh_reg }
295#define RMBH { OP_REG, bh_reg }
296#define RMAX { OP_REG, ax_reg }
297#define RMDX { OP_REG, dx_reg }
298
299#define eAX { OP_IMREG, eAX_reg }
300#define eBX { OP_IMREG, eBX_reg }
301#define eCX { OP_IMREG, eCX_reg }
302#define eDX { OP_IMREG, eDX_reg }
303#define eSP { OP_IMREG, eSP_reg }
304#define eBP { OP_IMREG, eBP_reg }
305#define eSI { OP_IMREG, eSI_reg }
306#define eDI { OP_IMREG, eDI_reg }
307#define AL { OP_IMREG, al_reg }
308#define CL { OP_IMREG, cl_reg }
309#define DL { OP_IMREG, dl_reg }
310#define BL { OP_IMREG, bl_reg }
311#define AH { OP_IMREG, ah_reg }
312#define CH { OP_IMREG, ch_reg }
313#define DH { OP_IMREG, dh_reg }
314#define BH { OP_IMREG, bh_reg }
315#define AX { OP_IMREG, ax_reg }
316#define DX { OP_IMREG, dx_reg }
317#define zAX { OP_IMREG, z_mode_ax_reg }
318#define indirDX { OP_IMREG, indir_dx_reg }
319
320#define Sw { OP_SEG, w_mode }
321#define Sv { OP_SEG, v_mode }
322#define Ap { OP_DIR, 0 }
323#define Ob { OP_OFF64, b_mode }
324#define Ov { OP_OFF64, v_mode }
325#define Xb { OP_DSreg, eSI_reg }
326#define Xv { OP_DSreg, eSI_reg }
327#define Xz { OP_DSreg, eSI_reg }
328#define Yb { OP_ESreg, eDI_reg }
329#define Yv { OP_ESreg, eDI_reg }
330#define DSBX { OP_DSreg, eBX_reg }
331
332#define es { OP_REG, es_reg }
333#define ss { OP_REG, ss_reg }
334#define cs { OP_REG, cs_reg }
335#define ds { OP_REG, ds_reg }
336#define fs { OP_REG, fs_reg }
337#define gs { OP_REG, gs_reg }
338
339#define MX { OP_MMX, 0 }
340#define XM { OP_XMM, 0 }
cf7f2e2d 341#define XMScalar { OP_XMM, scalar_mode }
a45ae5f8 342#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
5796c8dc
SS
343#define XMM { OP_XMM, xmm_mode }
344#define EM { OP_EM, v_mode }
345#define EMS { OP_EM, v_swap_mode }
346#define EMd { OP_EM, d_mode }
347#define EMx { OP_EM, x_mode }
348#define EXw { OP_EX, w_mode }
349#define EXd { OP_EX, d_mode }
cf7f2e2d 350#define EXdScalar { OP_EX, d_scalar_mode }
5796c8dc
SS
351#define EXdS { OP_EX, d_swap_mode }
352#define EXq { OP_EX, q_mode }
cf7f2e2d
JM
353#define EXqScalar { OP_EX, q_scalar_mode }
354#define EXqScalarS { OP_EX, q_scalar_swap_mode }
5796c8dc
SS
355#define EXqS { OP_EX, q_swap_mode }
356#define EXx { OP_EX, x_mode }
357#define EXxS { OP_EX, x_swap_mode }
358#define EXxmm { OP_EX, xmm_mode }
359#define EXxmmq { OP_EX, xmmq_mode }
a45ae5f8
JM
360#define EXxmm_mb { OP_EX, xmm_mb_mode }
361#define EXxmm_mw { OP_EX, xmm_mw_mode }
362#define EXxmm_md { OP_EX, xmm_md_mode }
363#define EXxmm_mq { OP_EX, xmm_mq_mode }
364#define EXxmmdw { OP_EX, xmmdw_mode }
365#define EXxmmqd { OP_EX, xmmqd_mode }
5796c8dc
SS
366#define EXymmq { OP_EX, ymmq_mode }
367#define EXVexWdq { OP_EX, vex_w_dq_mode }
cf7f2e2d 368#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
5796c8dc
SS
369#define MS { OP_MS, v_mode }
370#define XS { OP_XS, v_mode }
371#define EMCq { OP_EMC, q_mode }
372#define MXC { OP_MXC, 0 }
373#define OPSUF { OP_3DNowSuffix, 0 }
374#define CMP { CMP_Fixup, 0 }
375#define XMM0 { XMM_Fixup, 0 }
cf7f2e2d
JM
376#define FXSAVE { FXSAVE_Fixup, 0 }
377#define Vex_2src_1 { OP_Vex_2src_1, 0 }
378#define Vex_2src_2 { OP_Vex_2src_2, 0 }
5796c8dc
SS
379
380#define Vex { OP_VEX, vex_mode }
cf7f2e2d 381#define VexScalar { OP_VEX, vex_scalar_mode }
a45ae5f8 382#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
5796c8dc
SS
383#define Vex128 { OP_VEX, vex128_mode }
384#define Vex256 { OP_VEX, vex256_mode }
c50c785c 385#define VexGdq { OP_VEX, dq_mode }
5796c8dc 386#define VexI4 { VEXI4_Fixup, 0}
5796c8dc
SS
387#define EXdVex { OP_EX_Vex, d_mode }
388#define EXdVexS { OP_EX_Vex, d_swap_mode }
cf7f2e2d 389#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
5796c8dc
SS
390#define EXqVex { OP_EX_Vex, q_mode }
391#define EXqVexS { OP_EX_Vex, q_swap_mode }
cf7f2e2d 392#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
5796c8dc
SS
393#define EXVexW { OP_EX_VexW, x_mode }
394#define EXdVexW { OP_EX_VexW, d_mode }
395#define EXqVexW { OP_EX_VexW, q_mode }
cf7f2e2d 396#define EXVexImmW { OP_EX_VexImmW, x_mode }
5796c8dc 397#define XMVex { OP_XMM_Vex, 0 }
cf7f2e2d 398#define XMVexScalar { OP_XMM_Vex, scalar_mode }
5796c8dc
SS
399#define XMVexW { OP_XMM_VexW, 0 }
400#define XMVexI4 { OP_REG_VexI4, x_mode }
401#define PCLMUL { PCLMUL_Fixup, 0 }
402#define VZERO { VZERO_Fixup, 0 }
403#define VCMP { VCMP_Fixup, 0 }
404
a45ae5f8
JM
405#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
406#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
407
5796c8dc
SS
408/* Used handle "rep" prefix for string instructions. */
409#define Xbr { REP_Fixup, eSI_reg }
410#define Xvr { REP_Fixup, eSI_reg }
411#define Ybr { REP_Fixup, eDI_reg }
412#define Yvr { REP_Fixup, eDI_reg }
413#define Yzr { REP_Fixup, eDI_reg }
414#define indirDXr { REP_Fixup, indir_dx_reg }
415#define ALr { REP_Fixup, al_reg }
416#define eAXr { REP_Fixup, eAX_reg }
417
ef5ccd6c
JM
418/* Used handle HLE prefix for lockable instructions. */
419#define Ebh1 { HLE_Fixup1, b_mode }
420#define Evh1 { HLE_Fixup1, v_mode }
421#define Ebh2 { HLE_Fixup2, b_mode }
422#define Evh2 { HLE_Fixup2, v_mode }
423#define Ebh3 { HLE_Fixup3, b_mode }
424#define Evh3 { HLE_Fixup3, v_mode }
425
5796c8dc
SS
426#define cond_jump_flag { NULL, cond_jump_mode }
427#define loop_jcxz_flag { NULL, loop_jcxz_mode }
428
429/* bits in sizeflag */
430#define SUFFIX_ALWAYS 4
431#define AFLAG 2
432#define DFLAG 1
433
cf7f2e2d
JM
434enum
435{
436 /* byte operand */
437 b_mode = 1,
438 /* byte operand with operand swapped */
439 b_swap_mode,
c50c785c
JM
440 /* byte operand, sign extend like 'T' suffix */
441 b_T_mode,
cf7f2e2d
JM
442 /* operand size depends on prefixes */
443 v_mode,
444 /* operand size depends on prefixes with operand swapped */
445 v_swap_mode,
446 /* word operand */
447 w_mode,
448 /* double word operand */
449 d_mode,
450 /* double word operand with operand swapped */
451 d_swap_mode,
452 /* quad word operand */
453 q_mode,
454 /* quad word operand with operand swapped */
455 q_swap_mode,
456 /* ten-byte operand */
457 t_mode,
458 /* 16-byte XMM or 32-byte YMM operand */
459 x_mode,
460 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
461 x_swap_mode,
462 /* 16-byte XMM operand */
463 xmm_mode,
464 /* 16-byte XMM or quad word operand */
465 xmmq_mode,
a45ae5f8
JM
466 /* XMM register or byte memory operand */
467 xmm_mb_mode,
468 /* XMM register or word memory operand */
469 xmm_mw_mode,
470 /* XMM register or double word memory operand */
471 xmm_md_mode,
472 /* XMM register or quad word memory operand */
473 xmm_mq_mode,
474 /* 16-byte XMM, word or double word operand */
475 xmmdw_mode,
476 /* 16-byte XMM, double word or quad word operand */
477 xmmqd_mode,
cf7f2e2d
JM
478 /* 32-byte YMM or quad word operand */
479 ymmq_mode,
a45ae5f8
JM
480 /* 32-byte YMM or 16-byte word operand */
481 ymmxmm_mode,
cf7f2e2d
JM
482 /* d_mode in 32bit, q_mode in 64bit mode. */
483 m_mode,
484 /* pair of v_mode operands */
485 a_mode,
486 cond_jump_mode,
487 loop_jcxz_mode,
488 /* operand size depends on REX prefixes. */
489 dq_mode,
490 /* registers like dq_mode, memory like w_mode. */
491 dqw_mode,
492 /* 4- or 6-byte pointer operand */
493 f_mode,
494 const_1_mode,
495 /* v_mode for stack-related opcodes. */
496 stack_v_mode,
497 /* non-quad operand size depends on prefixes */
498 z_mode,
499 /* 16-byte operand */
500 o_mode,
501 /* registers like dq_mode, memory like b_mode. */
502 dqb_mode,
503 /* registers like dq_mode, memory like d_mode. */
504 dqd_mode,
505 /* normal vex mode */
506 vex_mode,
507 /* 128bit vex mode */
508 vex128_mode,
509 /* 256bit vex mode */
510 vex256_mode,
511 /* operand size depends on the VEX.W bit. */
512 vex_w_dq_mode,
513
a45ae5f8
JM
514 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
515 vex_vsib_d_w_dq_mode,
516 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
517 vex_vsib_q_w_dq_mode,
518
cf7f2e2d
JM
519 /* scalar, ignore vector length. */
520 scalar_mode,
521 /* like d_mode, ignore vector length. */
522 d_scalar_mode,
523 /* like d_swap_mode, ignore vector length. */
524 d_scalar_swap_mode,
525 /* like q_mode, ignore vector length. */
526 q_scalar_mode,
527 /* like q_swap_mode, ignore vector length. */
528 q_scalar_swap_mode,
529 /* like vex_mode, ignore vector length. */
530 vex_scalar_mode,
531 /* like vex_w_dq_mode, ignore vector length. */
532 vex_scalar_w_dq_mode,
533
534 es_reg,
535 cs_reg,
536 ss_reg,
537 ds_reg,
538 fs_reg,
539 gs_reg,
540
541 eAX_reg,
542 eCX_reg,
543 eDX_reg,
544 eBX_reg,
545 eSP_reg,
546 eBP_reg,
547 eSI_reg,
548 eDI_reg,
549
550 al_reg,
551 cl_reg,
552 dl_reg,
553 bl_reg,
554 ah_reg,
555 ch_reg,
556 dh_reg,
557 bh_reg,
558
559 ax_reg,
560 cx_reg,
561 dx_reg,
562 bx_reg,
563 sp_reg,
564 bp_reg,
565 si_reg,
566 di_reg,
567
568 rAX_reg,
569 rCX_reg,
570 rDX_reg,
571 rBX_reg,
572 rSP_reg,
573 rBP_reg,
574 rSI_reg,
575 rDI_reg,
576
577 z_mode_ax_reg,
578 indir_dx_reg
579};
580
581enum
582{
583 FLOATCODE = 1,
584 USE_REG_TABLE,
585 USE_MOD_TABLE,
586 USE_RM_TABLE,
587 USE_PREFIX_TABLE,
588 USE_X86_64_TABLE,
589 USE_3BYTE_TABLE,
590 USE_XOP_8F_TABLE,
591 USE_VEX_C4_TABLE,
592 USE_VEX_C5_TABLE,
593 USE_VEX_LEN_TABLE,
594 USE_VEX_W_TABLE
595};
5796c8dc
SS
596
597#define FLOAT NULL, { { NULL, FLOATCODE } }
598
599#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
600#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
601#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
602#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
603#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
604#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
605#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
cf7f2e2d 606#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
5796c8dc
SS
607#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
608#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
609#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
cf7f2e2d
JM
610#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
611
612enum
613{
614 REG_80 = 0,
615 REG_81,
616 REG_82,
617 REG_8F,
618 REG_C0,
619 REG_C1,
620 REG_C6,
621 REG_C7,
622 REG_D0,
623 REG_D1,
624 REG_D2,
625 REG_D3,
626 REG_F6,
627 REG_F7,
628 REG_FE,
629 REG_FF,
630 REG_0F00,
631 REG_0F01,
632 REG_0F0D,
633 REG_0F18,
634 REG_0F71,
635 REG_0F72,
636 REG_0F73,
637 REG_0FA6,
638 REG_0FA7,
639 REG_0FAE,
640 REG_0FBA,
641 REG_0FC7,
c50c785c
JM
642 REG_VEX_0F71,
643 REG_VEX_0F72,
644 REG_VEX_0F73,
645 REG_VEX_0FAE,
646 REG_VEX_0F38F3,
cf7f2e2d 647 REG_XOP_LWPCB,
c50c785c
JM
648 REG_XOP_LWP,
649 REG_XOP_TBM_01,
650 REG_XOP_TBM_02
cf7f2e2d
JM
651};
652
653enum
654{
655 MOD_8D = 0,
ef5ccd6c
JM
656 MOD_C6_REG_7,
657 MOD_C7_REG_7,
cf7f2e2d
JM
658 MOD_0F01_REG_0,
659 MOD_0F01_REG_1,
660 MOD_0F01_REG_2,
661 MOD_0F01_REG_3,
662 MOD_0F01_REG_7,
663 MOD_0F12_PREFIX_0,
664 MOD_0F13,
665 MOD_0F16_PREFIX_0,
666 MOD_0F17,
667 MOD_0F18_REG_0,
668 MOD_0F18_REG_1,
669 MOD_0F18_REG_2,
670 MOD_0F18_REG_3,
ef5ccd6c
JM
671 MOD_0F18_REG_4,
672 MOD_0F18_REG_5,
673 MOD_0F18_REG_6,
674 MOD_0F18_REG_7,
cf7f2e2d
JM
675 MOD_0F20,
676 MOD_0F21,
677 MOD_0F22,
678 MOD_0F23,
679 MOD_0F24,
680 MOD_0F26,
681 MOD_0F2B_PREFIX_0,
682 MOD_0F2B_PREFIX_1,
683 MOD_0F2B_PREFIX_2,
684 MOD_0F2B_PREFIX_3,
685 MOD_0F51,
686 MOD_0F71_REG_2,
687 MOD_0F71_REG_4,
688 MOD_0F71_REG_6,
689 MOD_0F72_REG_2,
690 MOD_0F72_REG_4,
691 MOD_0F72_REG_6,
692 MOD_0F73_REG_2,
693 MOD_0F73_REG_3,
694 MOD_0F73_REG_6,
695 MOD_0F73_REG_7,
696 MOD_0FAE_REG_0,
697 MOD_0FAE_REG_1,
698 MOD_0FAE_REG_2,
699 MOD_0FAE_REG_3,
700 MOD_0FAE_REG_4,
701 MOD_0FAE_REG_5,
702 MOD_0FAE_REG_6,
703 MOD_0FAE_REG_7,
704 MOD_0FB2,
705 MOD_0FB4,
706 MOD_0FB5,
707 MOD_0FC7_REG_6,
708 MOD_0FC7_REG_7,
709 MOD_0FD7,
710 MOD_0FE7_PREFIX_2,
711 MOD_0FF0_PREFIX_3,
712 MOD_0F382A_PREFIX_2,
713 MOD_62_32BIT,
714 MOD_C4_32BIT,
715 MOD_C5_32BIT,
c50c785c
JM
716 MOD_VEX_0F12_PREFIX_0,
717 MOD_VEX_0F13,
718 MOD_VEX_0F16_PREFIX_0,
719 MOD_VEX_0F17,
720 MOD_VEX_0F2B,
721 MOD_VEX_0F50,
722 MOD_VEX_0F71_REG_2,
723 MOD_VEX_0F71_REG_4,
724 MOD_VEX_0F71_REG_6,
725 MOD_VEX_0F72_REG_2,
726 MOD_VEX_0F72_REG_4,
727 MOD_VEX_0F72_REG_6,
728 MOD_VEX_0F73_REG_2,
729 MOD_VEX_0F73_REG_3,
730 MOD_VEX_0F73_REG_6,
731 MOD_VEX_0F73_REG_7,
732 MOD_VEX_0FAE_REG_2,
733 MOD_VEX_0FAE_REG_3,
734 MOD_VEX_0FD7_PREFIX_2,
735 MOD_VEX_0FE7_PREFIX_2,
736 MOD_VEX_0FF0_PREFIX_3,
c50c785c
JM
737 MOD_VEX_0F381A_PREFIX_2,
738 MOD_VEX_0F382A_PREFIX_2,
739 MOD_VEX_0F382C_PREFIX_2,
740 MOD_VEX_0F382D_PREFIX_2,
741 MOD_VEX_0F382E_PREFIX_2,
a45ae5f8
JM
742 MOD_VEX_0F382F_PREFIX_2,
743 MOD_VEX_0F385A_PREFIX_2,
744 MOD_VEX_0F388C_PREFIX_2,
745 MOD_VEX_0F388E_PREFIX_2,
cf7f2e2d
JM
746};
747
748enum
749{
ef5ccd6c
JM
750 RM_C6_REG_7 = 0,
751 RM_C7_REG_7,
752 RM_0F01_REG_0,
cf7f2e2d
JM
753 RM_0F01_REG_1,
754 RM_0F01_REG_2,
755 RM_0F01_REG_3,
756 RM_0F01_REG_7,
757 RM_0FAE_REG_5,
758 RM_0FAE_REG_6,
759 RM_0FAE_REG_7
760};
761
762enum
763{
764 PREFIX_90 = 0,
765 PREFIX_0F10,
766 PREFIX_0F11,
767 PREFIX_0F12,
768 PREFIX_0F16,
769 PREFIX_0F2A,
770 PREFIX_0F2B,
771 PREFIX_0F2C,
772 PREFIX_0F2D,
773 PREFIX_0F2E,
774 PREFIX_0F2F,
775 PREFIX_0F51,
776 PREFIX_0F52,
777 PREFIX_0F53,
778 PREFIX_0F58,
779 PREFIX_0F59,
780 PREFIX_0F5A,
781 PREFIX_0F5B,
782 PREFIX_0F5C,
783 PREFIX_0F5D,
784 PREFIX_0F5E,
785 PREFIX_0F5F,
786 PREFIX_0F60,
787 PREFIX_0F61,
788 PREFIX_0F62,
789 PREFIX_0F6C,
790 PREFIX_0F6D,
791 PREFIX_0F6F,
792 PREFIX_0F70,
793 PREFIX_0F73_REG_3,
794 PREFIX_0F73_REG_7,
795 PREFIX_0F78,
796 PREFIX_0F79,
797 PREFIX_0F7C,
798 PREFIX_0F7D,
799 PREFIX_0F7E,
800 PREFIX_0F7F,
801 PREFIX_0FAE_REG_0,
802 PREFIX_0FAE_REG_1,
803 PREFIX_0FAE_REG_2,
804 PREFIX_0FAE_REG_3,
805 PREFIX_0FB8,
c50c785c 806 PREFIX_0FBC,
cf7f2e2d
JM
807 PREFIX_0FBD,
808 PREFIX_0FC2,
809 PREFIX_0FC3,
810 PREFIX_0FC7_REG_6,
811 PREFIX_0FD0,
812 PREFIX_0FD6,
813 PREFIX_0FE6,
814 PREFIX_0FE7,
815 PREFIX_0FF0,
816 PREFIX_0FF7,
817 PREFIX_0F3810,
818 PREFIX_0F3814,
819 PREFIX_0F3815,
820 PREFIX_0F3817,
821 PREFIX_0F3820,
822 PREFIX_0F3821,
823 PREFIX_0F3822,
824 PREFIX_0F3823,
825 PREFIX_0F3824,
826 PREFIX_0F3825,
827 PREFIX_0F3828,
828 PREFIX_0F3829,
829 PREFIX_0F382A,
830 PREFIX_0F382B,
831 PREFIX_0F3830,
832 PREFIX_0F3831,
833 PREFIX_0F3832,
834 PREFIX_0F3833,
835 PREFIX_0F3834,
836 PREFIX_0F3835,
837 PREFIX_0F3837,
838 PREFIX_0F3838,
839 PREFIX_0F3839,
840 PREFIX_0F383A,
841 PREFIX_0F383B,
842 PREFIX_0F383C,
843 PREFIX_0F383D,
844 PREFIX_0F383E,
845 PREFIX_0F383F,
846 PREFIX_0F3840,
847 PREFIX_0F3841,
848 PREFIX_0F3880,
849 PREFIX_0F3881,
a45ae5f8 850 PREFIX_0F3882,
cf7f2e2d
JM
851 PREFIX_0F38DB,
852 PREFIX_0F38DC,
853 PREFIX_0F38DD,
854 PREFIX_0F38DE,
855 PREFIX_0F38DF,
856 PREFIX_0F38F0,
857 PREFIX_0F38F1,
ef5ccd6c 858 PREFIX_0F38F6,
cf7f2e2d
JM
859 PREFIX_0F3A08,
860 PREFIX_0F3A09,
861 PREFIX_0F3A0A,
862 PREFIX_0F3A0B,
863 PREFIX_0F3A0C,
864 PREFIX_0F3A0D,
865 PREFIX_0F3A0E,
866 PREFIX_0F3A14,
867 PREFIX_0F3A15,
868 PREFIX_0F3A16,
869 PREFIX_0F3A17,
870 PREFIX_0F3A20,
871 PREFIX_0F3A21,
872 PREFIX_0F3A22,
873 PREFIX_0F3A40,
874 PREFIX_0F3A41,
875 PREFIX_0F3A42,
876 PREFIX_0F3A44,
877 PREFIX_0F3A60,
878 PREFIX_0F3A61,
879 PREFIX_0F3A62,
880 PREFIX_0F3A63,
881 PREFIX_0F3ADF,
c50c785c
JM
882 PREFIX_VEX_0F10,
883 PREFIX_VEX_0F11,
884 PREFIX_VEX_0F12,
885 PREFIX_VEX_0F16,
886 PREFIX_VEX_0F2A,
887 PREFIX_VEX_0F2C,
888 PREFIX_VEX_0F2D,
889 PREFIX_VEX_0F2E,
890 PREFIX_VEX_0F2F,
891 PREFIX_VEX_0F51,
892 PREFIX_VEX_0F52,
893 PREFIX_VEX_0F53,
894 PREFIX_VEX_0F58,
895 PREFIX_VEX_0F59,
896 PREFIX_VEX_0F5A,
897 PREFIX_VEX_0F5B,
898 PREFIX_VEX_0F5C,
899 PREFIX_VEX_0F5D,
900 PREFIX_VEX_0F5E,
901 PREFIX_VEX_0F5F,
902 PREFIX_VEX_0F60,
903 PREFIX_VEX_0F61,
904 PREFIX_VEX_0F62,
905 PREFIX_VEX_0F63,
906 PREFIX_VEX_0F64,
907 PREFIX_VEX_0F65,
908 PREFIX_VEX_0F66,
909 PREFIX_VEX_0F67,
910 PREFIX_VEX_0F68,
911 PREFIX_VEX_0F69,
912 PREFIX_VEX_0F6A,
913 PREFIX_VEX_0F6B,
914 PREFIX_VEX_0F6C,
915 PREFIX_VEX_0F6D,
916 PREFIX_VEX_0F6E,
917 PREFIX_VEX_0F6F,
918 PREFIX_VEX_0F70,
919 PREFIX_VEX_0F71_REG_2,
920 PREFIX_VEX_0F71_REG_4,
921 PREFIX_VEX_0F71_REG_6,
922 PREFIX_VEX_0F72_REG_2,
923 PREFIX_VEX_0F72_REG_4,
924 PREFIX_VEX_0F72_REG_6,
925 PREFIX_VEX_0F73_REG_2,
926 PREFIX_VEX_0F73_REG_3,
927 PREFIX_VEX_0F73_REG_6,
928 PREFIX_VEX_0F73_REG_7,
929 PREFIX_VEX_0F74,
930 PREFIX_VEX_0F75,
931 PREFIX_VEX_0F76,
932 PREFIX_VEX_0F77,
933 PREFIX_VEX_0F7C,
934 PREFIX_VEX_0F7D,
935 PREFIX_VEX_0F7E,
936 PREFIX_VEX_0F7F,
937 PREFIX_VEX_0FC2,
938 PREFIX_VEX_0FC4,
939 PREFIX_VEX_0FC5,
940 PREFIX_VEX_0FD0,
941 PREFIX_VEX_0FD1,
942 PREFIX_VEX_0FD2,
943 PREFIX_VEX_0FD3,
944 PREFIX_VEX_0FD4,
945 PREFIX_VEX_0FD5,
946 PREFIX_VEX_0FD6,
947 PREFIX_VEX_0FD7,
948 PREFIX_VEX_0FD8,
949 PREFIX_VEX_0FD9,
950 PREFIX_VEX_0FDA,
951 PREFIX_VEX_0FDB,
952 PREFIX_VEX_0FDC,
953 PREFIX_VEX_0FDD,
954 PREFIX_VEX_0FDE,
955 PREFIX_VEX_0FDF,
956 PREFIX_VEX_0FE0,
957 PREFIX_VEX_0FE1,
958 PREFIX_VEX_0FE2,
959 PREFIX_VEX_0FE3,
960 PREFIX_VEX_0FE4,
961 PREFIX_VEX_0FE5,
962 PREFIX_VEX_0FE6,
963 PREFIX_VEX_0FE7,
964 PREFIX_VEX_0FE8,
965 PREFIX_VEX_0FE9,
966 PREFIX_VEX_0FEA,
967 PREFIX_VEX_0FEB,
968 PREFIX_VEX_0FEC,
969 PREFIX_VEX_0FED,
970 PREFIX_VEX_0FEE,
971 PREFIX_VEX_0FEF,
972 PREFIX_VEX_0FF0,
973 PREFIX_VEX_0FF1,
974 PREFIX_VEX_0FF2,
975 PREFIX_VEX_0FF3,
976 PREFIX_VEX_0FF4,
977 PREFIX_VEX_0FF5,
978 PREFIX_VEX_0FF6,
979 PREFIX_VEX_0FF7,
980 PREFIX_VEX_0FF8,
981 PREFIX_VEX_0FF9,
982 PREFIX_VEX_0FFA,
983 PREFIX_VEX_0FFB,
984 PREFIX_VEX_0FFC,
985 PREFIX_VEX_0FFD,
986 PREFIX_VEX_0FFE,
987 PREFIX_VEX_0F3800,
988 PREFIX_VEX_0F3801,
989 PREFIX_VEX_0F3802,
990 PREFIX_VEX_0F3803,
991 PREFIX_VEX_0F3804,
992 PREFIX_VEX_0F3805,
993 PREFIX_VEX_0F3806,
994 PREFIX_VEX_0F3807,
995 PREFIX_VEX_0F3808,
996 PREFIX_VEX_0F3809,
997 PREFIX_VEX_0F380A,
998 PREFIX_VEX_0F380B,
999 PREFIX_VEX_0F380C,
1000 PREFIX_VEX_0F380D,
1001 PREFIX_VEX_0F380E,
1002 PREFIX_VEX_0F380F,
1003 PREFIX_VEX_0F3813,
a45ae5f8 1004 PREFIX_VEX_0F3816,
c50c785c
JM
1005 PREFIX_VEX_0F3817,
1006 PREFIX_VEX_0F3818,
1007 PREFIX_VEX_0F3819,
1008 PREFIX_VEX_0F381A,
1009 PREFIX_VEX_0F381C,
1010 PREFIX_VEX_0F381D,
1011 PREFIX_VEX_0F381E,
1012 PREFIX_VEX_0F3820,
1013 PREFIX_VEX_0F3821,
1014 PREFIX_VEX_0F3822,
1015 PREFIX_VEX_0F3823,
1016 PREFIX_VEX_0F3824,
1017 PREFIX_VEX_0F3825,
1018 PREFIX_VEX_0F3828,
1019 PREFIX_VEX_0F3829,
1020 PREFIX_VEX_0F382A,
1021 PREFIX_VEX_0F382B,
1022 PREFIX_VEX_0F382C,
1023 PREFIX_VEX_0F382D,
1024 PREFIX_VEX_0F382E,
1025 PREFIX_VEX_0F382F,
1026 PREFIX_VEX_0F3830,
1027 PREFIX_VEX_0F3831,
1028 PREFIX_VEX_0F3832,
1029 PREFIX_VEX_0F3833,
1030 PREFIX_VEX_0F3834,
1031 PREFIX_VEX_0F3835,
a45ae5f8 1032 PREFIX_VEX_0F3836,
c50c785c
JM
1033 PREFIX_VEX_0F3837,
1034 PREFIX_VEX_0F3838,
1035 PREFIX_VEX_0F3839,
1036 PREFIX_VEX_0F383A,
1037 PREFIX_VEX_0F383B,
1038 PREFIX_VEX_0F383C,
1039 PREFIX_VEX_0F383D,
1040 PREFIX_VEX_0F383E,
1041 PREFIX_VEX_0F383F,
1042 PREFIX_VEX_0F3840,
1043 PREFIX_VEX_0F3841,
a45ae5f8
JM
1044 PREFIX_VEX_0F3845,
1045 PREFIX_VEX_0F3846,
1046 PREFIX_VEX_0F3847,
1047 PREFIX_VEX_0F3858,
1048 PREFIX_VEX_0F3859,
1049 PREFIX_VEX_0F385A,
1050 PREFIX_VEX_0F3878,
1051 PREFIX_VEX_0F3879,
1052 PREFIX_VEX_0F388C,
1053 PREFIX_VEX_0F388E,
1054 PREFIX_VEX_0F3890,
1055 PREFIX_VEX_0F3891,
1056 PREFIX_VEX_0F3892,
1057 PREFIX_VEX_0F3893,
c50c785c
JM
1058 PREFIX_VEX_0F3896,
1059 PREFIX_VEX_0F3897,
1060 PREFIX_VEX_0F3898,
1061 PREFIX_VEX_0F3899,
1062 PREFIX_VEX_0F389A,
1063 PREFIX_VEX_0F389B,
1064 PREFIX_VEX_0F389C,
1065 PREFIX_VEX_0F389D,
1066 PREFIX_VEX_0F389E,
1067 PREFIX_VEX_0F389F,
1068 PREFIX_VEX_0F38A6,
1069 PREFIX_VEX_0F38A7,
1070 PREFIX_VEX_0F38A8,
1071 PREFIX_VEX_0F38A9,
1072 PREFIX_VEX_0F38AA,
1073 PREFIX_VEX_0F38AB,
1074 PREFIX_VEX_0F38AC,
1075 PREFIX_VEX_0F38AD,
1076 PREFIX_VEX_0F38AE,
1077 PREFIX_VEX_0F38AF,
1078 PREFIX_VEX_0F38B6,
1079 PREFIX_VEX_0F38B7,
1080 PREFIX_VEX_0F38B8,
1081 PREFIX_VEX_0F38B9,
1082 PREFIX_VEX_0F38BA,
1083 PREFIX_VEX_0F38BB,
1084 PREFIX_VEX_0F38BC,
1085 PREFIX_VEX_0F38BD,
1086 PREFIX_VEX_0F38BE,
1087 PREFIX_VEX_0F38BF,
1088 PREFIX_VEX_0F38DB,
1089 PREFIX_VEX_0F38DC,
1090 PREFIX_VEX_0F38DD,
1091 PREFIX_VEX_0F38DE,
1092 PREFIX_VEX_0F38DF,
1093 PREFIX_VEX_0F38F2,
1094 PREFIX_VEX_0F38F3_REG_1,
1095 PREFIX_VEX_0F38F3_REG_2,
1096 PREFIX_VEX_0F38F3_REG_3,
a45ae5f8
JM
1097 PREFIX_VEX_0F38F5,
1098 PREFIX_VEX_0F38F6,
c50c785c 1099 PREFIX_VEX_0F38F7,
a45ae5f8
JM
1100 PREFIX_VEX_0F3A00,
1101 PREFIX_VEX_0F3A01,
1102 PREFIX_VEX_0F3A02,
c50c785c
JM
1103 PREFIX_VEX_0F3A04,
1104 PREFIX_VEX_0F3A05,
1105 PREFIX_VEX_0F3A06,
1106 PREFIX_VEX_0F3A08,
1107 PREFIX_VEX_0F3A09,
1108 PREFIX_VEX_0F3A0A,
1109 PREFIX_VEX_0F3A0B,
1110 PREFIX_VEX_0F3A0C,
1111 PREFIX_VEX_0F3A0D,
1112 PREFIX_VEX_0F3A0E,
1113 PREFIX_VEX_0F3A0F,
1114 PREFIX_VEX_0F3A14,
1115 PREFIX_VEX_0F3A15,
1116 PREFIX_VEX_0F3A16,
1117 PREFIX_VEX_0F3A17,
1118 PREFIX_VEX_0F3A18,
1119 PREFIX_VEX_0F3A19,
1120 PREFIX_VEX_0F3A1D,
1121 PREFIX_VEX_0F3A20,
1122 PREFIX_VEX_0F3A21,
1123 PREFIX_VEX_0F3A22,
a45ae5f8
JM
1124 PREFIX_VEX_0F3A38,
1125 PREFIX_VEX_0F3A39,
c50c785c
JM
1126 PREFIX_VEX_0F3A40,
1127 PREFIX_VEX_0F3A41,
1128 PREFIX_VEX_0F3A42,
1129 PREFIX_VEX_0F3A44,
a45ae5f8 1130 PREFIX_VEX_0F3A46,
c50c785c
JM
1131 PREFIX_VEX_0F3A48,
1132 PREFIX_VEX_0F3A49,
1133 PREFIX_VEX_0F3A4A,
1134 PREFIX_VEX_0F3A4B,
1135 PREFIX_VEX_0F3A4C,
1136 PREFIX_VEX_0F3A5C,
1137 PREFIX_VEX_0F3A5D,
1138 PREFIX_VEX_0F3A5E,
1139 PREFIX_VEX_0F3A5F,
1140 PREFIX_VEX_0F3A60,
1141 PREFIX_VEX_0F3A61,
1142 PREFIX_VEX_0F3A62,
1143 PREFIX_VEX_0F3A63,
1144 PREFIX_VEX_0F3A68,
1145 PREFIX_VEX_0F3A69,
1146 PREFIX_VEX_0F3A6A,
1147 PREFIX_VEX_0F3A6B,
1148 PREFIX_VEX_0F3A6C,
1149 PREFIX_VEX_0F3A6D,
1150 PREFIX_VEX_0F3A6E,
1151 PREFIX_VEX_0F3A6F,
1152 PREFIX_VEX_0F3A78,
1153 PREFIX_VEX_0F3A79,
1154 PREFIX_VEX_0F3A7A,
1155 PREFIX_VEX_0F3A7B,
1156 PREFIX_VEX_0F3A7C,
1157 PREFIX_VEX_0F3A7D,
1158 PREFIX_VEX_0F3A7E,
1159 PREFIX_VEX_0F3A7F,
a45ae5f8
JM
1160 PREFIX_VEX_0F3ADF,
1161 PREFIX_VEX_0F3AF0
cf7f2e2d
JM
1162};
1163
1164enum
1165{
1166 X86_64_06 = 0,
1167 X86_64_07,
1168 X86_64_0D,
1169 X86_64_16,
1170 X86_64_17,
1171 X86_64_1E,
1172 X86_64_1F,
1173 X86_64_27,
1174 X86_64_2F,
1175 X86_64_37,
1176 X86_64_3F,
1177 X86_64_60,
1178 X86_64_61,
1179 X86_64_62,
1180 X86_64_63,
1181 X86_64_6D,
1182 X86_64_6F,
1183 X86_64_9A,
1184 X86_64_C4,
1185 X86_64_C5,
1186 X86_64_CE,
1187 X86_64_D4,
1188 X86_64_D5,
1189 X86_64_EA,
1190 X86_64_0F01_REG_0,
1191 X86_64_0F01_REG_1,
1192 X86_64_0F01_REG_2,
1193 X86_64_0F01_REG_3
1194};
1195
1196enum
1197{
1198 THREE_BYTE_0F38 = 0,
1199 THREE_BYTE_0F3A,
1200 THREE_BYTE_0F7A
1201};
1202
1203enum
1204{
1205 XOP_08 = 0,
1206 XOP_09,
1207 XOP_0A
1208};
1209
1210enum
1211{
1212 VEX_0F = 0,
1213 VEX_0F38,
1214 VEX_0F3A
1215};
1216
1217enum
1218{
c50c785c
JM
1219 VEX_LEN_0F10_P_1 = 0,
1220 VEX_LEN_0F10_P_3,
1221 VEX_LEN_0F11_P_1,
1222 VEX_LEN_0F11_P_3,
1223 VEX_LEN_0F12_P_0_M_0,
1224 VEX_LEN_0F12_P_0_M_1,
1225 VEX_LEN_0F12_P_2,
1226 VEX_LEN_0F13_M_0,
1227 VEX_LEN_0F16_P_0_M_0,
1228 VEX_LEN_0F16_P_0_M_1,
1229 VEX_LEN_0F16_P_2,
1230 VEX_LEN_0F17_M_0,
1231 VEX_LEN_0F2A_P_1,
1232 VEX_LEN_0F2A_P_3,
1233 VEX_LEN_0F2C_P_1,
1234 VEX_LEN_0F2C_P_3,
1235 VEX_LEN_0F2D_P_1,
1236 VEX_LEN_0F2D_P_3,
1237 VEX_LEN_0F2E_P_0,
1238 VEX_LEN_0F2E_P_2,
1239 VEX_LEN_0F2F_P_0,
1240 VEX_LEN_0F2F_P_2,
1241 VEX_LEN_0F51_P_1,
1242 VEX_LEN_0F51_P_3,
1243 VEX_LEN_0F52_P_1,
1244 VEX_LEN_0F53_P_1,
1245 VEX_LEN_0F58_P_1,
1246 VEX_LEN_0F58_P_3,
1247 VEX_LEN_0F59_P_1,
1248 VEX_LEN_0F59_P_3,
1249 VEX_LEN_0F5A_P_1,
1250 VEX_LEN_0F5A_P_3,
1251 VEX_LEN_0F5C_P_1,
1252 VEX_LEN_0F5C_P_3,
1253 VEX_LEN_0F5D_P_1,
1254 VEX_LEN_0F5D_P_3,
1255 VEX_LEN_0F5E_P_1,
1256 VEX_LEN_0F5E_P_3,
1257 VEX_LEN_0F5F_P_1,
1258 VEX_LEN_0F5F_P_3,
c50c785c 1259 VEX_LEN_0F6E_P_2,
c50c785c
JM
1260 VEX_LEN_0F7E_P_1,
1261 VEX_LEN_0F7E_P_2,
1262 VEX_LEN_0FAE_R_2_M_0,
1263 VEX_LEN_0FAE_R_3_M_0,
1264 VEX_LEN_0FC2_P_1,
1265 VEX_LEN_0FC2_P_3,
1266 VEX_LEN_0FC4_P_2,
1267 VEX_LEN_0FC5_P_2,
c50c785c 1268 VEX_LEN_0FD6_P_2,
c50c785c 1269 VEX_LEN_0FF7_P_2,
a45ae5f8
JM
1270 VEX_LEN_0F3816_P_2,
1271 VEX_LEN_0F3819_P_2,
c50c785c 1272 VEX_LEN_0F381A_P_2_M_0,
a45ae5f8 1273 VEX_LEN_0F3836_P_2,
c50c785c 1274 VEX_LEN_0F3841_P_2,
a45ae5f8 1275 VEX_LEN_0F385A_P_2_M_0,
c50c785c
JM
1276 VEX_LEN_0F38DB_P_2,
1277 VEX_LEN_0F38DC_P_2,
1278 VEX_LEN_0F38DD_P_2,
1279 VEX_LEN_0F38DE_P_2,
1280 VEX_LEN_0F38DF_P_2,
1281 VEX_LEN_0F38F2_P_0,
1282 VEX_LEN_0F38F3_R_1_P_0,
1283 VEX_LEN_0F38F3_R_2_P_0,
1284 VEX_LEN_0F38F3_R_3_P_0,
a45ae5f8
JM
1285 VEX_LEN_0F38F5_P_0,
1286 VEX_LEN_0F38F5_P_1,
1287 VEX_LEN_0F38F5_P_3,
1288 VEX_LEN_0F38F6_P_3,
c50c785c 1289 VEX_LEN_0F38F7_P_0,
a45ae5f8
JM
1290 VEX_LEN_0F38F7_P_1,
1291 VEX_LEN_0F38F7_P_2,
1292 VEX_LEN_0F38F7_P_3,
1293 VEX_LEN_0F3A00_P_2,
1294 VEX_LEN_0F3A01_P_2,
c50c785c
JM
1295 VEX_LEN_0F3A06_P_2,
1296 VEX_LEN_0F3A0A_P_2,
1297 VEX_LEN_0F3A0B_P_2,
c50c785c
JM
1298 VEX_LEN_0F3A14_P_2,
1299 VEX_LEN_0F3A15_P_2,
1300 VEX_LEN_0F3A16_P_2,
1301 VEX_LEN_0F3A17_P_2,
1302 VEX_LEN_0F3A18_P_2,
1303 VEX_LEN_0F3A19_P_2,
1304 VEX_LEN_0F3A20_P_2,
1305 VEX_LEN_0F3A21_P_2,
1306 VEX_LEN_0F3A22_P_2,
a45ae5f8
JM
1307 VEX_LEN_0F3A38_P_2,
1308 VEX_LEN_0F3A39_P_2,
c50c785c 1309 VEX_LEN_0F3A41_P_2,
c50c785c 1310 VEX_LEN_0F3A44_P_2,
a45ae5f8 1311 VEX_LEN_0F3A46_P_2,
c50c785c
JM
1312 VEX_LEN_0F3A60_P_2,
1313 VEX_LEN_0F3A61_P_2,
1314 VEX_LEN_0F3A62_P_2,
1315 VEX_LEN_0F3A63_P_2,
1316 VEX_LEN_0F3A6A_P_2,
1317 VEX_LEN_0F3A6B_P_2,
1318 VEX_LEN_0F3A6E_P_2,
1319 VEX_LEN_0F3A6F_P_2,
1320 VEX_LEN_0F3A7A_P_2,
1321 VEX_LEN_0F3A7B_P_2,
1322 VEX_LEN_0F3A7E_P_2,
1323 VEX_LEN_0F3A7F_P_2,
1324 VEX_LEN_0F3ADF_P_2,
a45ae5f8 1325 VEX_LEN_0F3AF0_P_3,
ef5ccd6c
JM
1326 VEX_LEN_0FXOP_08_CC,
1327 VEX_LEN_0FXOP_08_CD,
1328 VEX_LEN_0FXOP_08_CE,
1329 VEX_LEN_0FXOP_08_CF,
1330 VEX_LEN_0FXOP_08_EC,
1331 VEX_LEN_0FXOP_08_ED,
1332 VEX_LEN_0FXOP_08_EE,
1333 VEX_LEN_0FXOP_08_EF,
c50c785c
JM
1334 VEX_LEN_0FXOP_09_80,
1335 VEX_LEN_0FXOP_09_81
cf7f2e2d 1336};
5796c8dc 1337
cf7f2e2d
JM
1338enum
1339{
c50c785c
JM
1340 VEX_W_0F10_P_0 = 0,
1341 VEX_W_0F10_P_1,
1342 VEX_W_0F10_P_2,
1343 VEX_W_0F10_P_3,
1344 VEX_W_0F11_P_0,
1345 VEX_W_0F11_P_1,
1346 VEX_W_0F11_P_2,
1347 VEX_W_0F11_P_3,
1348 VEX_W_0F12_P_0_M_0,
1349 VEX_W_0F12_P_0_M_1,
1350 VEX_W_0F12_P_1,
1351 VEX_W_0F12_P_2,
1352 VEX_W_0F12_P_3,
1353 VEX_W_0F13_M_0,
1354 VEX_W_0F14,
1355 VEX_W_0F15,
1356 VEX_W_0F16_P_0_M_0,
1357 VEX_W_0F16_P_0_M_1,
1358 VEX_W_0F16_P_1,
1359 VEX_W_0F16_P_2,
1360 VEX_W_0F17_M_0,
1361 VEX_W_0F28,
1362 VEX_W_0F29,
1363 VEX_W_0F2B_M_0,
1364 VEX_W_0F2E_P_0,
1365 VEX_W_0F2E_P_2,
1366 VEX_W_0F2F_P_0,
1367 VEX_W_0F2F_P_2,
1368 VEX_W_0F50_M_0,
1369 VEX_W_0F51_P_0,
1370 VEX_W_0F51_P_1,
1371 VEX_W_0F51_P_2,
1372 VEX_W_0F51_P_3,
1373 VEX_W_0F52_P_0,
1374 VEX_W_0F52_P_1,
1375 VEX_W_0F53_P_0,
1376 VEX_W_0F53_P_1,
1377 VEX_W_0F58_P_0,
1378 VEX_W_0F58_P_1,
1379 VEX_W_0F58_P_2,
1380 VEX_W_0F58_P_3,
1381 VEX_W_0F59_P_0,
1382 VEX_W_0F59_P_1,
1383 VEX_W_0F59_P_2,
1384 VEX_W_0F59_P_3,
1385 VEX_W_0F5A_P_0,
1386 VEX_W_0F5A_P_1,
1387 VEX_W_0F5A_P_3,
1388 VEX_W_0F5B_P_0,
1389 VEX_W_0F5B_P_1,
1390 VEX_W_0F5B_P_2,
1391 VEX_W_0F5C_P_0,
1392 VEX_W_0F5C_P_1,
1393 VEX_W_0F5C_P_2,
1394 VEX_W_0F5C_P_3,
1395 VEX_W_0F5D_P_0,
1396 VEX_W_0F5D_P_1,
1397 VEX_W_0F5D_P_2,
1398 VEX_W_0F5D_P_3,
1399 VEX_W_0F5E_P_0,
1400 VEX_W_0F5E_P_1,
1401 VEX_W_0F5E_P_2,
1402 VEX_W_0F5E_P_3,
1403 VEX_W_0F5F_P_0,
1404 VEX_W_0F5F_P_1,
1405 VEX_W_0F5F_P_2,
1406 VEX_W_0F5F_P_3,
1407 VEX_W_0F60_P_2,
1408 VEX_W_0F61_P_2,
1409 VEX_W_0F62_P_2,
1410 VEX_W_0F63_P_2,
1411 VEX_W_0F64_P_2,
1412 VEX_W_0F65_P_2,
1413 VEX_W_0F66_P_2,
1414 VEX_W_0F67_P_2,
1415 VEX_W_0F68_P_2,
1416 VEX_W_0F69_P_2,
1417 VEX_W_0F6A_P_2,
1418 VEX_W_0F6B_P_2,
1419 VEX_W_0F6C_P_2,
1420 VEX_W_0F6D_P_2,
1421 VEX_W_0F6F_P_1,
1422 VEX_W_0F6F_P_2,
1423 VEX_W_0F70_P_1,
1424 VEX_W_0F70_P_2,
1425 VEX_W_0F70_P_3,
1426 VEX_W_0F71_R_2_P_2,
1427 VEX_W_0F71_R_4_P_2,
1428 VEX_W_0F71_R_6_P_2,
1429 VEX_W_0F72_R_2_P_2,
1430 VEX_W_0F72_R_4_P_2,
1431 VEX_W_0F72_R_6_P_2,
1432 VEX_W_0F73_R_2_P_2,
1433 VEX_W_0F73_R_3_P_2,
1434 VEX_W_0F73_R_6_P_2,
1435 VEX_W_0F73_R_7_P_2,
1436 VEX_W_0F74_P_2,
1437 VEX_W_0F75_P_2,
1438 VEX_W_0F76_P_2,
1439 VEX_W_0F77_P_0,
1440 VEX_W_0F7C_P_2,
1441 VEX_W_0F7C_P_3,
1442 VEX_W_0F7D_P_2,
1443 VEX_W_0F7D_P_3,
1444 VEX_W_0F7E_P_1,
1445 VEX_W_0F7F_P_1,
1446 VEX_W_0F7F_P_2,
1447 VEX_W_0FAE_R_2_M_0,
1448 VEX_W_0FAE_R_3_M_0,
1449 VEX_W_0FC2_P_0,
1450 VEX_W_0FC2_P_1,
1451 VEX_W_0FC2_P_2,
1452 VEX_W_0FC2_P_3,
1453 VEX_W_0FC4_P_2,
1454 VEX_W_0FC5_P_2,
1455 VEX_W_0FD0_P_2,
1456 VEX_W_0FD0_P_3,
1457 VEX_W_0FD1_P_2,
1458 VEX_W_0FD2_P_2,
1459 VEX_W_0FD3_P_2,
1460 VEX_W_0FD4_P_2,
1461 VEX_W_0FD5_P_2,
1462 VEX_W_0FD6_P_2,
1463 VEX_W_0FD7_P_2_M_1,
1464 VEX_W_0FD8_P_2,
1465 VEX_W_0FD9_P_2,
1466 VEX_W_0FDA_P_2,
1467 VEX_W_0FDB_P_2,
1468 VEX_W_0FDC_P_2,
1469 VEX_W_0FDD_P_2,
1470 VEX_W_0FDE_P_2,
1471 VEX_W_0FDF_P_2,
1472 VEX_W_0FE0_P_2,
1473 VEX_W_0FE1_P_2,
1474 VEX_W_0FE2_P_2,
1475 VEX_W_0FE3_P_2,
1476 VEX_W_0FE4_P_2,
1477 VEX_W_0FE5_P_2,
1478 VEX_W_0FE6_P_1,
1479 VEX_W_0FE6_P_2,
1480 VEX_W_0FE6_P_3,
1481 VEX_W_0FE7_P_2_M_0,
1482 VEX_W_0FE8_P_2,
1483 VEX_W_0FE9_P_2,
1484 VEX_W_0FEA_P_2,
1485 VEX_W_0FEB_P_2,
1486 VEX_W_0FEC_P_2,
1487 VEX_W_0FED_P_2,
1488 VEX_W_0FEE_P_2,
1489 VEX_W_0FEF_P_2,
1490 VEX_W_0FF0_P_3_M_0,
1491 VEX_W_0FF1_P_2,
1492 VEX_W_0FF2_P_2,
1493 VEX_W_0FF3_P_2,
1494 VEX_W_0FF4_P_2,
1495 VEX_W_0FF5_P_2,
1496 VEX_W_0FF6_P_2,
1497 VEX_W_0FF7_P_2,
1498 VEX_W_0FF8_P_2,
1499 VEX_W_0FF9_P_2,
1500 VEX_W_0FFA_P_2,
1501 VEX_W_0FFB_P_2,
1502 VEX_W_0FFC_P_2,
1503 VEX_W_0FFD_P_2,
1504 VEX_W_0FFE_P_2,
1505 VEX_W_0F3800_P_2,
1506 VEX_W_0F3801_P_2,
1507 VEX_W_0F3802_P_2,
1508 VEX_W_0F3803_P_2,
1509 VEX_W_0F3804_P_2,
1510 VEX_W_0F3805_P_2,
1511 VEX_W_0F3806_P_2,
1512 VEX_W_0F3807_P_2,
1513 VEX_W_0F3808_P_2,
1514 VEX_W_0F3809_P_2,
1515 VEX_W_0F380A_P_2,
1516 VEX_W_0F380B_P_2,
1517 VEX_W_0F380C_P_2,
1518 VEX_W_0F380D_P_2,
1519 VEX_W_0F380E_P_2,
1520 VEX_W_0F380F_P_2,
a45ae5f8 1521 VEX_W_0F3816_P_2,
c50c785c 1522 VEX_W_0F3817_P_2,
a45ae5f8
JM
1523 VEX_W_0F3818_P_2,
1524 VEX_W_0F3819_P_2,
c50c785c
JM
1525 VEX_W_0F381A_P_2_M_0,
1526 VEX_W_0F381C_P_2,
1527 VEX_W_0F381D_P_2,
1528 VEX_W_0F381E_P_2,
1529 VEX_W_0F3820_P_2,
1530 VEX_W_0F3821_P_2,
1531 VEX_W_0F3822_P_2,
1532 VEX_W_0F3823_P_2,
1533 VEX_W_0F3824_P_2,
1534 VEX_W_0F3825_P_2,
1535 VEX_W_0F3828_P_2,
1536 VEX_W_0F3829_P_2,
1537 VEX_W_0F382A_P_2_M_0,
1538 VEX_W_0F382B_P_2,
1539 VEX_W_0F382C_P_2_M_0,
1540 VEX_W_0F382D_P_2_M_0,
1541 VEX_W_0F382E_P_2_M_0,
1542 VEX_W_0F382F_P_2_M_0,
1543 VEX_W_0F3830_P_2,
1544 VEX_W_0F3831_P_2,
1545 VEX_W_0F3832_P_2,
1546 VEX_W_0F3833_P_2,
1547 VEX_W_0F3834_P_2,
1548 VEX_W_0F3835_P_2,
a45ae5f8 1549 VEX_W_0F3836_P_2,
c50c785c
JM
1550 VEX_W_0F3837_P_2,
1551 VEX_W_0F3838_P_2,
1552 VEX_W_0F3839_P_2,
1553 VEX_W_0F383A_P_2,
1554 VEX_W_0F383B_P_2,
1555 VEX_W_0F383C_P_2,
1556 VEX_W_0F383D_P_2,
1557 VEX_W_0F383E_P_2,
1558 VEX_W_0F383F_P_2,
1559 VEX_W_0F3840_P_2,
1560 VEX_W_0F3841_P_2,
a45ae5f8
JM
1561 VEX_W_0F3846_P_2,
1562 VEX_W_0F3858_P_2,
1563 VEX_W_0F3859_P_2,
1564 VEX_W_0F385A_P_2_M_0,
1565 VEX_W_0F3878_P_2,
1566 VEX_W_0F3879_P_2,
c50c785c
JM
1567 VEX_W_0F38DB_P_2,
1568 VEX_W_0F38DC_P_2,
1569 VEX_W_0F38DD_P_2,
1570 VEX_W_0F38DE_P_2,
1571 VEX_W_0F38DF_P_2,
a45ae5f8
JM
1572 VEX_W_0F3A00_P_2,
1573 VEX_W_0F3A01_P_2,
1574 VEX_W_0F3A02_P_2,
c50c785c
JM
1575 VEX_W_0F3A04_P_2,
1576 VEX_W_0F3A05_P_2,
1577 VEX_W_0F3A06_P_2,
1578 VEX_W_0F3A08_P_2,
1579 VEX_W_0F3A09_P_2,
1580 VEX_W_0F3A0A_P_2,
1581 VEX_W_0F3A0B_P_2,
1582 VEX_W_0F3A0C_P_2,
1583 VEX_W_0F3A0D_P_2,
1584 VEX_W_0F3A0E_P_2,
1585 VEX_W_0F3A0F_P_2,
1586 VEX_W_0F3A14_P_2,
1587 VEX_W_0F3A15_P_2,
1588 VEX_W_0F3A18_P_2,
1589 VEX_W_0F3A19_P_2,
1590 VEX_W_0F3A20_P_2,
1591 VEX_W_0F3A21_P_2,
a45ae5f8
JM
1592 VEX_W_0F3A38_P_2,
1593 VEX_W_0F3A39_P_2,
c50c785c
JM
1594 VEX_W_0F3A40_P_2,
1595 VEX_W_0F3A41_P_2,
1596 VEX_W_0F3A42_P_2,
1597 VEX_W_0F3A44_P_2,
a45ae5f8 1598 VEX_W_0F3A46_P_2,
c50c785c
JM
1599 VEX_W_0F3A48_P_2,
1600 VEX_W_0F3A49_P_2,
1601 VEX_W_0F3A4A_P_2,
1602 VEX_W_0F3A4B_P_2,
1603 VEX_W_0F3A4C_P_2,
1604 VEX_W_0F3A60_P_2,
1605 VEX_W_0F3A61_P_2,
1606 VEX_W_0F3A62_P_2,
1607 VEX_W_0F3A63_P_2,
1608 VEX_W_0F3ADF_P_2
cf7f2e2d 1609};
5796c8dc
SS
1610
1611typedef void (*op_rtn) (int bytemode, int sizeflag);
1612
1613struct dis386 {
1614 const char *name;
1615 struct
1616 {
1617 op_rtn rtn;
1618 int bytemode;
1619 } op[MAX_OPERANDS];
1620};
1621
1622/* Upper case letters in the instruction names here are macros.
1623 'A' => print 'b' if no register operands or suffix_always is true
1624 'B' => print 'b' if suffix_always is true
1625 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1626 size prefix
1627 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1628 suffix_always is true
1629 'E' => print 'e' if 32-bit form of jcxz
1630 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1631 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1632 'H' => print ",pt" or ",pn" branch hint
1633 'I' => honor following macro letter even in Intel mode (implemented only
1634 for some of the macro letters)
1635 'J' => print 'l'
1636 'K' => print 'd' or 'q' if rex prefix is present.
1637 'L' => print 'l' if suffix_always is true
1638 'M' => print 'r' if intel_mnemonic is false.
1639 'N' => print 'n' if instruction has no wait "prefix"
1640 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1641 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1642 or suffix_always is true. print 'q' if rex prefix is present.
1643 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1644 is true
1645 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1646 'S' => print 'w', 'l' or 'q' if suffix_always is true
1647 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1648 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1649 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1650 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1651 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1652 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1653 suffix_always is true.
1654 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1655 '!' => change condition from true to false or from false to true.
1656 '%' => add 1 upper case letter to the macro.
1657
1658 2 upper case letter macros:
1659 "XY" => print 'x' or 'y' if no register operands or suffix_always
1660 is true.
cf7f2e2d
JM
1661 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1662 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
5796c8dc 1663 or suffix_always is true
cf7f2e2d
JM
1664 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1665 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1666 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
a45ae5f8 1667 "LW" => print 'd', 'q' depending on the VEX.W bit
5796c8dc
SS
1668
1669 Many of the above letters print nothing in Intel mode. See "putop"
1670 for the details.
1671
1672 Braces '{' and '}', and vertical bars '|', indicate alternative
1673 mnemonic strings for AT&T and Intel. */
1674
1675static const struct dis386 dis386[] = {
1676 /* 00 */
ef5ccd6c
JM
1677 { "addB", { Ebh1, Gb } },
1678 { "addS", { Evh1, Gv } },
5796c8dc
SS
1679 { "addB", { Gb, EbS } },
1680 { "addS", { Gv, EvS } },
1681 { "addB", { AL, Ib } },
1682 { "addS", { eAX, Iv } },
1683 { X86_64_TABLE (X86_64_06) },
1684 { X86_64_TABLE (X86_64_07) },
1685 /* 08 */
ef5ccd6c
JM
1686 { "orB", { Ebh1, Gb } },
1687 { "orS", { Evh1, Gv } },
5796c8dc
SS
1688 { "orB", { Gb, EbS } },
1689 { "orS", { Gv, EvS } },
1690 { "orB", { AL, Ib } },
1691 { "orS", { eAX, Iv } },
1692 { X86_64_TABLE (X86_64_0D) },
cf7f2e2d 1693 { Bad_Opcode }, /* 0x0f extended opcode escape */
5796c8dc 1694 /* 10 */
ef5ccd6c
JM
1695 { "adcB", { Ebh1, Gb } },
1696 { "adcS", { Evh1, Gv } },
5796c8dc
SS
1697 { "adcB", { Gb, EbS } },
1698 { "adcS", { Gv, EvS } },
1699 { "adcB", { AL, Ib } },
1700 { "adcS", { eAX, Iv } },
1701 { X86_64_TABLE (X86_64_16) },
1702 { X86_64_TABLE (X86_64_17) },
1703 /* 18 */
ef5ccd6c
JM
1704 { "sbbB", { Ebh1, Gb } },
1705 { "sbbS", { Evh1, Gv } },
5796c8dc
SS
1706 { "sbbB", { Gb, EbS } },
1707 { "sbbS", { Gv, EvS } },
1708 { "sbbB", { AL, Ib } },
1709 { "sbbS", { eAX, Iv } },
1710 { X86_64_TABLE (X86_64_1E) },
1711 { X86_64_TABLE (X86_64_1F) },
1712 /* 20 */
ef5ccd6c
JM
1713 { "andB", { Ebh1, Gb } },
1714 { "andS", { Evh1, Gv } },
5796c8dc
SS
1715 { "andB", { Gb, EbS } },
1716 { "andS", { Gv, EvS } },
1717 { "andB", { AL, Ib } },
1718 { "andS", { eAX, Iv } },
cf7f2e2d 1719 { Bad_Opcode }, /* SEG ES prefix */
5796c8dc
SS
1720 { X86_64_TABLE (X86_64_27) },
1721 /* 28 */
ef5ccd6c
JM
1722 { "subB", { Ebh1, Gb } },
1723 { "subS", { Evh1, Gv } },
5796c8dc
SS
1724 { "subB", { Gb, EbS } },
1725 { "subS", { Gv, EvS } },
1726 { "subB", { AL, Ib } },
1727 { "subS", { eAX, Iv } },
cf7f2e2d 1728 { Bad_Opcode }, /* SEG CS prefix */
5796c8dc
SS
1729 { X86_64_TABLE (X86_64_2F) },
1730 /* 30 */
ef5ccd6c
JM
1731 { "xorB", { Ebh1, Gb } },
1732 { "xorS", { Evh1, Gv } },
5796c8dc
SS
1733 { "xorB", { Gb, EbS } },
1734 { "xorS", { Gv, EvS } },
1735 { "xorB", { AL, Ib } },
1736 { "xorS", { eAX, Iv } },
cf7f2e2d 1737 { Bad_Opcode }, /* SEG SS prefix */
5796c8dc
SS
1738 { X86_64_TABLE (X86_64_37) },
1739 /* 38 */
1740 { "cmpB", { Eb, Gb } },
1741 { "cmpS", { Ev, Gv } },
1742 { "cmpB", { Gb, EbS } },
1743 { "cmpS", { Gv, EvS } },
1744 { "cmpB", { AL, Ib } },
1745 { "cmpS", { eAX, Iv } },
cf7f2e2d 1746 { Bad_Opcode }, /* SEG DS prefix */
5796c8dc
SS
1747 { X86_64_TABLE (X86_64_3F) },
1748 /* 40 */
1749 { "inc{S|}", { RMeAX } },
1750 { "inc{S|}", { RMeCX } },
1751 { "inc{S|}", { RMeDX } },
1752 { "inc{S|}", { RMeBX } },
1753 { "inc{S|}", { RMeSP } },
1754 { "inc{S|}", { RMeBP } },
1755 { "inc{S|}", { RMeSI } },
1756 { "inc{S|}", { RMeDI } },
1757 /* 48 */
1758 { "dec{S|}", { RMeAX } },
1759 { "dec{S|}", { RMeCX } },
1760 { "dec{S|}", { RMeDX } },
1761 { "dec{S|}", { RMeBX } },
1762 { "dec{S|}", { RMeSP } },
1763 { "dec{S|}", { RMeBP } },
1764 { "dec{S|}", { RMeSI } },
1765 { "dec{S|}", { RMeDI } },
1766 /* 50 */
1767 { "pushV", { RMrAX } },
1768 { "pushV", { RMrCX } },
1769 { "pushV", { RMrDX } },
1770 { "pushV", { RMrBX } },
1771 { "pushV", { RMrSP } },
1772 { "pushV", { RMrBP } },
1773 { "pushV", { RMrSI } },
1774 { "pushV", { RMrDI } },
1775 /* 58 */
1776 { "popV", { RMrAX } },
1777 { "popV", { RMrCX } },
1778 { "popV", { RMrDX } },
1779 { "popV", { RMrBX } },
1780 { "popV", { RMrSP } },
1781 { "popV", { RMrBP } },
1782 { "popV", { RMrSI } },
1783 { "popV", { RMrDI } },
1784 /* 60 */
1785 { X86_64_TABLE (X86_64_60) },
1786 { X86_64_TABLE (X86_64_61) },
1787 { X86_64_TABLE (X86_64_62) },
1788 { X86_64_TABLE (X86_64_63) },
cf7f2e2d
JM
1789 { Bad_Opcode }, /* seg fs */
1790 { Bad_Opcode }, /* seg gs */
1791 { Bad_Opcode }, /* op size prefix */
1792 { Bad_Opcode }, /* adr size prefix */
5796c8dc 1793 /* 68 */
c50c785c 1794 { "pushT", { sIv } },
5796c8dc 1795 { "imulS", { Gv, Ev, Iv } },
c50c785c 1796 { "pushT", { sIbT } },
5796c8dc
SS
1797 { "imulS", { Gv, Ev, sIb } },
1798 { "ins{b|}", { Ybr, indirDX } },
1799 { X86_64_TABLE (X86_64_6D) },
1800 { "outs{b|}", { indirDXr, Xb } },
1801 { X86_64_TABLE (X86_64_6F) },
1802 /* 70 */
1803 { "joH", { Jb, XX, cond_jump_flag } },
1804 { "jnoH", { Jb, XX, cond_jump_flag } },
1805 { "jbH", { Jb, XX, cond_jump_flag } },
1806 { "jaeH", { Jb, XX, cond_jump_flag } },
1807 { "jeH", { Jb, XX, cond_jump_flag } },
1808 { "jneH", { Jb, XX, cond_jump_flag } },
1809 { "jbeH", { Jb, XX, cond_jump_flag } },
1810 { "jaH", { Jb, XX, cond_jump_flag } },
1811 /* 78 */
1812 { "jsH", { Jb, XX, cond_jump_flag } },
1813 { "jnsH", { Jb, XX, cond_jump_flag } },
1814 { "jpH", { Jb, XX, cond_jump_flag } },
1815 { "jnpH", { Jb, XX, cond_jump_flag } },
1816 { "jlH", { Jb, XX, cond_jump_flag } },
1817 { "jgeH", { Jb, XX, cond_jump_flag } },
1818 { "jleH", { Jb, XX, cond_jump_flag } },
1819 { "jgH", { Jb, XX, cond_jump_flag } },
1820 /* 80 */
1821 { REG_TABLE (REG_80) },
1822 { REG_TABLE (REG_81) },
cf7f2e2d 1823 { Bad_Opcode },
5796c8dc
SS
1824 { REG_TABLE (REG_82) },
1825 { "testB", { Eb, Gb } },
1826 { "testS", { Ev, Gv } },
ef5ccd6c
JM
1827 { "xchgB", { Ebh2, Gb } },
1828 { "xchgS", { Evh2, Gv } },
5796c8dc 1829 /* 88 */
ef5ccd6c
JM
1830 { "movB", { Ebh3, Gb } },
1831 { "movS", { Evh3, Gv } },
5796c8dc
SS
1832 { "movB", { Gb, EbS } },
1833 { "movS", { Gv, EvS } },
1834 { "movD", { Sv, Sw } },
1835 { MOD_TABLE (MOD_8D) },
1836 { "movD", { Sw, Sv } },
1837 { REG_TABLE (REG_8F) },
1838 /* 90 */
1839 { PREFIX_TABLE (PREFIX_90) },
1840 { "xchgS", { RMeCX, eAX } },
1841 { "xchgS", { RMeDX, eAX } },
1842 { "xchgS", { RMeBX, eAX } },
1843 { "xchgS", { RMeSP, eAX } },
1844 { "xchgS", { RMeBP, eAX } },
1845 { "xchgS", { RMeSI, eAX } },
1846 { "xchgS", { RMeDI, eAX } },
1847 /* 98 */
1848 { "cW{t|}R", { XX } },
1849 { "cR{t|}O", { XX } },
1850 { X86_64_TABLE (X86_64_9A) },
cf7f2e2d 1851 { Bad_Opcode }, /* fwait */
5796c8dc
SS
1852 { "pushfT", { XX } },
1853 { "popfT", { XX } },
1854 { "sahf", { XX } },
1855 { "lahf", { XX } },
1856 /* a0 */
cf7f2e2d
JM
1857 { "mov%LB", { AL, Ob } },
1858 { "mov%LS", { eAX, Ov } },
1859 { "mov%LB", { Ob, AL } },
1860 { "mov%LS", { Ov, eAX } },
5796c8dc
SS
1861 { "movs{b|}", { Ybr, Xb } },
1862 { "movs{R|}", { Yvr, Xv } },
1863 { "cmps{b|}", { Xb, Yb } },
1864 { "cmps{R|}", { Xv, Yv } },
1865 /* a8 */
1866 { "testB", { AL, Ib } },
1867 { "testS", { eAX, Iv } },
1868 { "stosB", { Ybr, AL } },
1869 { "stosS", { Yvr, eAX } },
1870 { "lodsB", { ALr, Xb } },
1871 { "lodsS", { eAXr, Xv } },
1872 { "scasB", { AL, Yb } },
1873 { "scasS", { eAX, Yv } },
1874 /* b0 */
1875 { "movB", { RMAL, Ib } },
1876 { "movB", { RMCL, Ib } },
1877 { "movB", { RMDL, Ib } },
1878 { "movB", { RMBL, Ib } },
1879 { "movB", { RMAH, Ib } },
1880 { "movB", { RMCH, Ib } },
1881 { "movB", { RMDH, Ib } },
1882 { "movB", { RMBH, Ib } },
1883 /* b8 */
cf7f2e2d
JM
1884 { "mov%LV", { RMeAX, Iv64 } },
1885 { "mov%LV", { RMeCX, Iv64 } },
1886 { "mov%LV", { RMeDX, Iv64 } },
1887 { "mov%LV", { RMeBX, Iv64 } },
1888 { "mov%LV", { RMeSP, Iv64 } },
1889 { "mov%LV", { RMeBP, Iv64 } },
1890 { "mov%LV", { RMeSI, Iv64 } },
1891 { "mov%LV", { RMeDI, Iv64 } },
5796c8dc
SS
1892 /* c0 */
1893 { REG_TABLE (REG_C0) },
1894 { REG_TABLE (REG_C1) },
1895 { "retT", { Iw } },
1896 { "retT", { XX } },
1897 { X86_64_TABLE (X86_64_C4) },
1898 { X86_64_TABLE (X86_64_C5) },
1899 { REG_TABLE (REG_C6) },
1900 { REG_TABLE (REG_C7) },
1901 /* c8 */
1902 { "enterT", { Iw, Ib } },
1903 { "leaveT", { XX } },
1904 { "Jret{|f}P", { Iw } },
1905 { "Jret{|f}P", { XX } },
1906 { "int3", { XX } },
1907 { "int", { Ib } },
1908 { X86_64_TABLE (X86_64_CE) },
1909 { "iretP", { XX } },
1910 /* d0 */
1911 { REG_TABLE (REG_D0) },
1912 { REG_TABLE (REG_D1) },
1913 { REG_TABLE (REG_D2) },
1914 { REG_TABLE (REG_D3) },
1915 { X86_64_TABLE (X86_64_D4) },
1916 { X86_64_TABLE (X86_64_D5) },
cf7f2e2d 1917 { Bad_Opcode },
5796c8dc
SS
1918 { "xlat", { DSBX } },
1919 /* d8 */
1920 { FLOAT },
1921 { FLOAT },
1922 { FLOAT },
1923 { FLOAT },
1924 { FLOAT },
1925 { FLOAT },
1926 { FLOAT },
1927 { FLOAT },
1928 /* e0 */
1929 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1930 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1931 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1932 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1933 { "inB", { AL, Ib } },
1934 { "inG", { zAX, Ib } },
1935 { "outB", { Ib, AL } },
1936 { "outG", { Ib, zAX } },
1937 /* e8 */
1938 { "callT", { Jv } },
1939 { "jmpT", { Jv } },
1940 { X86_64_TABLE (X86_64_EA) },
1941 { "jmp", { Jb } },
1942 { "inB", { AL, indirDX } },
1943 { "inG", { zAX, indirDX } },
1944 { "outB", { indirDX, AL } },
1945 { "outG", { indirDX, zAX } },
1946 /* f0 */
cf7f2e2d 1947 { Bad_Opcode }, /* lock prefix */
5796c8dc 1948 { "icebp", { XX } },
cf7f2e2d
JM
1949 { Bad_Opcode }, /* repne */
1950 { Bad_Opcode }, /* repz */
5796c8dc
SS
1951 { "hlt", { XX } },
1952 { "cmc", { XX } },
1953 { REG_TABLE (REG_F6) },
1954 { REG_TABLE (REG_F7) },
1955 /* f8 */
1956 { "clc", { XX } },
1957 { "stc", { XX } },
1958 { "cli", { XX } },
1959 { "sti", { XX } },
1960 { "cld", { XX } },
1961 { "std", { XX } },
1962 { REG_TABLE (REG_FE) },
1963 { REG_TABLE (REG_FF) },
1964};
1965
1966static const struct dis386 dis386_twobyte[] = {
1967 /* 00 */
1968 { REG_TABLE (REG_0F00 ) },
1969 { REG_TABLE (REG_0F01 ) },
1970 { "larS", { Gv, Ew } },
1971 { "lslS", { Gv, Ew } },
cf7f2e2d 1972 { Bad_Opcode },
5796c8dc
SS
1973 { "syscall", { XX } },
1974 { "clts", { XX } },
1975 { "sysretP", { XX } },
1976 /* 08 */
1977 { "invd", { XX } },
1978 { "wbinvd", { XX } },
cf7f2e2d 1979 { Bad_Opcode },
c50c785c 1980 { "ud2", { XX } },
cf7f2e2d 1981 { Bad_Opcode },
5796c8dc
SS
1982 { REG_TABLE (REG_0F0D) },
1983 { "femms", { XX } },
1984 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1985 /* 10 */
1986 { PREFIX_TABLE (PREFIX_0F10) },
1987 { PREFIX_TABLE (PREFIX_0F11) },
1988 { PREFIX_TABLE (PREFIX_0F12) },
1989 { MOD_TABLE (MOD_0F13) },
1990 { "unpcklpX", { XM, EXx } },
1991 { "unpckhpX", { XM, EXx } },
1992 { PREFIX_TABLE (PREFIX_0F16) },
1993 { MOD_TABLE (MOD_0F17) },
1994 /* 18 */
1995 { REG_TABLE (REG_0F18) },
1996 { "nopQ", { Ev } },
1997 { "nopQ", { Ev } },
1998 { "nopQ", { Ev } },
1999 { "nopQ", { Ev } },
2000 { "nopQ", { Ev } },
2001 { "nopQ", { Ev } },
2002 { "nopQ", { Ev } },
2003 /* 20 */
2004 { MOD_TABLE (MOD_0F20) },
2005 { MOD_TABLE (MOD_0F21) },
2006 { MOD_TABLE (MOD_0F22) },
2007 { MOD_TABLE (MOD_0F23) },
2008 { MOD_TABLE (MOD_0F24) },
cf7f2e2d 2009 { Bad_Opcode },
5796c8dc 2010 { MOD_TABLE (MOD_0F26) },
cf7f2e2d 2011 { Bad_Opcode },
5796c8dc
SS
2012 /* 28 */
2013 { "movapX", { XM, EXx } },
2014 { "movapX", { EXxS, XM } },
2015 { PREFIX_TABLE (PREFIX_0F2A) },
2016 { PREFIX_TABLE (PREFIX_0F2B) },
2017 { PREFIX_TABLE (PREFIX_0F2C) },
2018 { PREFIX_TABLE (PREFIX_0F2D) },
2019 { PREFIX_TABLE (PREFIX_0F2E) },
2020 { PREFIX_TABLE (PREFIX_0F2F) },
2021 /* 30 */
2022 { "wrmsr", { XX } },
2023 { "rdtsc", { XX } },
2024 { "rdmsr", { XX } },
2025 { "rdpmc", { XX } },
2026 { "sysenter", { XX } },
2027 { "sysexit", { XX } },
cf7f2e2d 2028 { Bad_Opcode },
5796c8dc
SS
2029 { "getsec", { XX } },
2030 /* 38 */
2031 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
cf7f2e2d 2032 { Bad_Opcode },
5796c8dc 2033 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
cf7f2e2d
JM
2034 { Bad_Opcode },
2035 { Bad_Opcode },
2036 { Bad_Opcode },
2037 { Bad_Opcode },
2038 { Bad_Opcode },
5796c8dc
SS
2039 /* 40 */
2040 { "cmovoS", { Gv, Ev } },
2041 { "cmovnoS", { Gv, Ev } },
2042 { "cmovbS", { Gv, Ev } },
2043 { "cmovaeS", { Gv, Ev } },
2044 { "cmoveS", { Gv, Ev } },
2045 { "cmovneS", { Gv, Ev } },
2046 { "cmovbeS", { Gv, Ev } },
2047 { "cmovaS", { Gv, Ev } },
2048 /* 48 */
2049 { "cmovsS", { Gv, Ev } },
2050 { "cmovnsS", { Gv, Ev } },
2051 { "cmovpS", { Gv, Ev } },
2052 { "cmovnpS", { Gv, Ev } },
2053 { "cmovlS", { Gv, Ev } },
2054 { "cmovgeS", { Gv, Ev } },
2055 { "cmovleS", { Gv, Ev } },
2056 { "cmovgS", { Gv, Ev } },
2057 /* 50 */
2058 { MOD_TABLE (MOD_0F51) },
2059 { PREFIX_TABLE (PREFIX_0F51) },
2060 { PREFIX_TABLE (PREFIX_0F52) },
2061 { PREFIX_TABLE (PREFIX_0F53) },
2062 { "andpX", { XM, EXx } },
2063 { "andnpX", { XM, EXx } },
2064 { "orpX", { XM, EXx } },
2065 { "xorpX", { XM, EXx } },
2066 /* 58 */
2067 { PREFIX_TABLE (PREFIX_0F58) },
2068 { PREFIX_TABLE (PREFIX_0F59) },
2069 { PREFIX_TABLE (PREFIX_0F5A) },
2070 { PREFIX_TABLE (PREFIX_0F5B) },
2071 { PREFIX_TABLE (PREFIX_0F5C) },
2072 { PREFIX_TABLE (PREFIX_0F5D) },
2073 { PREFIX_TABLE (PREFIX_0F5E) },
2074 { PREFIX_TABLE (PREFIX_0F5F) },
2075 /* 60 */
2076 { PREFIX_TABLE (PREFIX_0F60) },
2077 { PREFIX_TABLE (PREFIX_0F61) },
2078 { PREFIX_TABLE (PREFIX_0F62) },
2079 { "packsswb", { MX, EM } },
2080 { "pcmpgtb", { MX, EM } },
2081 { "pcmpgtw", { MX, EM } },
2082 { "pcmpgtd", { MX, EM } },
2083 { "packuswb", { MX, EM } },
2084 /* 68 */
2085 { "punpckhbw", { MX, EM } },
2086 { "punpckhwd", { MX, EM } },
2087 { "punpckhdq", { MX, EM } },
2088 { "packssdw", { MX, EM } },
2089 { PREFIX_TABLE (PREFIX_0F6C) },
2090 { PREFIX_TABLE (PREFIX_0F6D) },
2091 { "movK", { MX, Edq } },
2092 { PREFIX_TABLE (PREFIX_0F6F) },
2093 /* 70 */
2094 { PREFIX_TABLE (PREFIX_0F70) },
2095 { REG_TABLE (REG_0F71) },
2096 { REG_TABLE (REG_0F72) },
2097 { REG_TABLE (REG_0F73) },
2098 { "pcmpeqb", { MX, EM } },
2099 { "pcmpeqw", { MX, EM } },
2100 { "pcmpeqd", { MX, EM } },
2101 { "emms", { XX } },
2102 /* 78 */
2103 { PREFIX_TABLE (PREFIX_0F78) },
2104 { PREFIX_TABLE (PREFIX_0F79) },
2105 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
cf7f2e2d 2106 { Bad_Opcode },
5796c8dc
SS
2107 { PREFIX_TABLE (PREFIX_0F7C) },
2108 { PREFIX_TABLE (PREFIX_0F7D) },
2109 { PREFIX_TABLE (PREFIX_0F7E) },
2110 { PREFIX_TABLE (PREFIX_0F7F) },
2111 /* 80 */
2112 { "joH", { Jv, XX, cond_jump_flag } },
2113 { "jnoH", { Jv, XX, cond_jump_flag } },
2114 { "jbH", { Jv, XX, cond_jump_flag } },
2115 { "jaeH", { Jv, XX, cond_jump_flag } },
2116 { "jeH", { Jv, XX, cond_jump_flag } },
2117 { "jneH", { Jv, XX, cond_jump_flag } },
2118 { "jbeH", { Jv, XX, cond_jump_flag } },
2119 { "jaH", { Jv, XX, cond_jump_flag } },
2120 /* 88 */
2121 { "jsH", { Jv, XX, cond_jump_flag } },
2122 { "jnsH", { Jv, XX, cond_jump_flag } },
2123 { "jpH", { Jv, XX, cond_jump_flag } },
2124 { "jnpH", { Jv, XX, cond_jump_flag } },
2125 { "jlH", { Jv, XX, cond_jump_flag } },
2126 { "jgeH", { Jv, XX, cond_jump_flag } },
2127 { "jleH", { Jv, XX, cond_jump_flag } },
2128 { "jgH", { Jv, XX, cond_jump_flag } },
2129 /* 90 */
2130 { "seto", { Eb } },
2131 { "setno", { Eb } },
2132 { "setb", { Eb } },
2133 { "setae", { Eb } },
2134 { "sete", { Eb } },
2135 { "setne", { Eb } },
2136 { "setbe", { Eb } },
2137 { "seta", { Eb } },
2138 /* 98 */
2139 { "sets", { Eb } },
2140 { "setns", { Eb } },
2141 { "setp", { Eb } },
2142 { "setnp", { Eb } },
2143 { "setl", { Eb } },
2144 { "setge", { Eb } },
2145 { "setle", { Eb } },
2146 { "setg", { Eb } },
2147 /* a0 */
2148 { "pushT", { fs } },
2149 { "popT", { fs } },
2150 { "cpuid", { XX } },
2151 { "btS", { Ev, Gv } },
2152 { "shldS", { Ev, Gv, Ib } },
2153 { "shldS", { Ev, Gv, CL } },
2154 { REG_TABLE (REG_0FA6) },
2155 { REG_TABLE (REG_0FA7) },
2156 /* a8 */
2157 { "pushT", { gs } },
2158 { "popT", { gs } },
2159 { "rsm", { XX } },
ef5ccd6c 2160 { "btsS", { Evh1, Gv } },
5796c8dc
SS
2161 { "shrdS", { Ev, Gv, Ib } },
2162 { "shrdS", { Ev, Gv, CL } },
2163 { REG_TABLE (REG_0FAE) },
2164 { "imulS", { Gv, Ev } },
2165 /* b0 */
ef5ccd6c
JM
2166 { "cmpxchgB", { Ebh1, Gb } },
2167 { "cmpxchgS", { Evh1, Gv } },
5796c8dc 2168 { MOD_TABLE (MOD_0FB2) },
ef5ccd6c 2169 { "btrS", { Evh1, Gv } },
5796c8dc
SS
2170 { MOD_TABLE (MOD_0FB4) },
2171 { MOD_TABLE (MOD_0FB5) },
2172 { "movz{bR|x}", { Gv, Eb } },
2173 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2174 /* b8 */
2175 { PREFIX_TABLE (PREFIX_0FB8) },
c50c785c 2176 { "ud1", { XX } },
5796c8dc 2177 { REG_TABLE (REG_0FBA) },
ef5ccd6c 2178 { "btcS", { Evh1, Gv } },
c50c785c 2179 { PREFIX_TABLE (PREFIX_0FBC) },
5796c8dc
SS
2180 { PREFIX_TABLE (PREFIX_0FBD) },
2181 { "movs{bR|x}", { Gv, Eb } },
2182 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2183 /* c0 */
ef5ccd6c
JM
2184 { "xaddB", { Ebh1, Gb } },
2185 { "xaddS", { Evh1, Gv } },
5796c8dc
SS
2186 { PREFIX_TABLE (PREFIX_0FC2) },
2187 { PREFIX_TABLE (PREFIX_0FC3) },
2188 { "pinsrw", { MX, Edqw, Ib } },
2189 { "pextrw", { Gdq, MS, Ib } },
2190 { "shufpX", { XM, EXx, Ib } },
2191 { REG_TABLE (REG_0FC7) },
2192 /* c8 */
2193 { "bswap", { RMeAX } },
2194 { "bswap", { RMeCX } },
2195 { "bswap", { RMeDX } },
2196 { "bswap", { RMeBX } },
2197 { "bswap", { RMeSP } },
2198 { "bswap", { RMeBP } },
2199 { "bswap", { RMeSI } },
2200 { "bswap", { RMeDI } },
2201 /* d0 */
2202 { PREFIX_TABLE (PREFIX_0FD0) },
2203 { "psrlw", { MX, EM } },
2204 { "psrld", { MX, EM } },
2205 { "psrlq", { MX, EM } },
2206 { "paddq", { MX, EM } },
2207 { "pmullw", { MX, EM } },
2208 { PREFIX_TABLE (PREFIX_0FD6) },
2209 { MOD_TABLE (MOD_0FD7) },
2210 /* d8 */
2211 { "psubusb", { MX, EM } },
2212 { "psubusw", { MX, EM } },
2213 { "pminub", { MX, EM } },
2214 { "pand", { MX, EM } },
2215 { "paddusb", { MX, EM } },
2216 { "paddusw", { MX, EM } },
2217 { "pmaxub", { MX, EM } },
2218 { "pandn", { MX, EM } },
2219 /* e0 */
2220 { "pavgb", { MX, EM } },
2221 { "psraw", { MX, EM } },
2222 { "psrad", { MX, EM } },
2223 { "pavgw", { MX, EM } },
2224 { "pmulhuw", { MX, EM } },
2225 { "pmulhw", { MX, EM } },
2226 { PREFIX_TABLE (PREFIX_0FE6) },
2227 { PREFIX_TABLE (PREFIX_0FE7) },
2228 /* e8 */
2229 { "psubsb", { MX, EM } },
2230 { "psubsw", { MX, EM } },
2231 { "pminsw", { MX, EM } },
2232 { "por", { MX, EM } },
2233 { "paddsb", { MX, EM } },
2234 { "paddsw", { MX, EM } },
2235 { "pmaxsw", { MX, EM } },
2236 { "pxor", { MX, EM } },
2237 /* f0 */
2238 { PREFIX_TABLE (PREFIX_0FF0) },
2239 { "psllw", { MX, EM } },
2240 { "pslld", { MX, EM } },
2241 { "psllq", { MX, EM } },
2242 { "pmuludq", { MX, EM } },
2243 { "pmaddwd", { MX, EM } },
2244 { "psadbw", { MX, EM } },
2245 { PREFIX_TABLE (PREFIX_0FF7) },
2246 /* f8 */
2247 { "psubb", { MX, EM } },
2248 { "psubw", { MX, EM } },
2249 { "psubd", { MX, EM } },
2250 { "psubq", { MX, EM } },
2251 { "paddb", { MX, EM } },
2252 { "paddw", { MX, EM } },
2253 { "paddd", { MX, EM } },
cf7f2e2d 2254 { Bad_Opcode },
5796c8dc
SS
2255};
2256
2257static const unsigned char onebyte_has_modrm[256] = {
2258 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2259 /* ------------------------------- */
2260 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2261 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2262 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2263 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2264 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2265 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2266 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2267 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2268 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2269 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2270 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2271 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2272 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2273 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2274 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2275 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2276 /* ------------------------------- */
2277 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2278};
2279
2280static const unsigned char twobyte_has_modrm[256] = {
2281 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2282 /* ------------------------------- */
2283 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2284 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2285 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2286 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2287 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2288 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2289 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2290 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2291 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2292 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2293 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2294 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2295 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2296 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2297 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2298 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2299 /* ------------------------------- */
2300 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2301};
2302
2303static char obuf[100];
2304static char *obufp;
2305static char *mnemonicendp;
2306static char scratchbuf[100];
2307static unsigned char *start_codep;
2308static unsigned char *insn_codep;
2309static unsigned char *codep;
cf7f2e2d
JM
2310static int last_lock_prefix;
2311static int last_repz_prefix;
2312static int last_repnz_prefix;
2313static int last_data_prefix;
2314static int last_addr_prefix;
2315static int last_rex_prefix;
2316static int last_seg_prefix;
2317#define MAX_CODE_LENGTH 15
2318/* We can up to 14 prefixes since the maximum instruction length is
2319 15bytes. */
2320static int all_prefixes[MAX_CODE_LENGTH - 1];
5796c8dc
SS
2321static disassemble_info *the_info;
2322static struct
2323 {
2324 int mod;
2325 int reg;
2326 int rm;
2327 }
2328modrm;
2329static unsigned char need_modrm;
cf7f2e2d
JM
2330static struct
2331 {
2332 int scale;
2333 int index;
2334 int base;
2335 }
2336sib;
5796c8dc
SS
2337static struct
2338 {
2339 int register_specifier;
2340 int length;
2341 int prefix;
2342 int w;
2343 }
2344vex;
2345static unsigned char need_vex;
2346static unsigned char need_vex_reg;
2347static unsigned char vex_w_done;
2348
2349struct op
2350 {
2351 const char *name;
2352 unsigned int len;
2353 };
2354
2355/* If we are accessing mod/rm/reg without need_modrm set, then the
2356 values are stale. Hitting this abort likely indicates that you
2357 need to update onebyte_has_modrm or twobyte_has_modrm. */
2358#define MODRM_CHECK if (!need_modrm) abort ()
2359
2360static const char **names64;
2361static const char **names32;
2362static const char **names16;
2363static const char **names8;
2364static const char **names8rex;
2365static const char **names_seg;
2366static const char *index64;
2367static const char *index32;
2368static const char **index16;
2369
2370static const char *intel_names64[] = {
2371 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2372 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2373};
2374static const char *intel_names32[] = {
2375 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2376 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2377};
2378static const char *intel_names16[] = {
2379 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2380 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2381};
2382static const char *intel_names8[] = {
2383 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2384};
2385static const char *intel_names8rex[] = {
2386 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2387 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2388};
2389static const char *intel_names_seg[] = {
2390 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2391};
2392static const char *intel_index64 = "riz";
2393static const char *intel_index32 = "eiz";
2394static const char *intel_index16[] = {
2395 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2396};
2397
2398static const char *att_names64[] = {
2399 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2400 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2401};
2402static const char *att_names32[] = {
2403 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2404 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2405};
2406static const char *att_names16[] = {
2407 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2408 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2409};
2410static const char *att_names8[] = {
2411 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2412};
2413static const char *att_names8rex[] = {
2414 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2415 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2416};
2417static const char *att_names_seg[] = {
2418 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2419};
2420static const char *att_index64 = "%riz";
2421static const char *att_index32 = "%eiz";
2422static const char *att_index16[] = {
2423 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2424};
2425
cf7f2e2d
JM
2426static const char **names_mm;
2427static const char *intel_names_mm[] = {
2428 "mm0", "mm1", "mm2", "mm3",
2429 "mm4", "mm5", "mm6", "mm7"
2430};
2431static const char *att_names_mm[] = {
2432 "%mm0", "%mm1", "%mm2", "%mm3",
2433 "%mm4", "%mm5", "%mm6", "%mm7"
2434};
2435
2436static const char **names_xmm;
2437static const char *intel_names_xmm[] = {
2438 "xmm0", "xmm1", "xmm2", "xmm3",
2439 "xmm4", "xmm5", "xmm6", "xmm7",
2440 "xmm8", "xmm9", "xmm10", "xmm11",
2441 "xmm12", "xmm13", "xmm14", "xmm15"
2442};
2443static const char *att_names_xmm[] = {
2444 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2445 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2446 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2447 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2448};
2449
2450static const char **names_ymm;
2451static const char *intel_names_ymm[] = {
2452 "ymm0", "ymm1", "ymm2", "ymm3",
2453 "ymm4", "ymm5", "ymm6", "ymm7",
2454 "ymm8", "ymm9", "ymm10", "ymm11",
2455 "ymm12", "ymm13", "ymm14", "ymm15"
2456};
2457static const char *att_names_ymm[] = {
2458 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2459 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2460 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2461 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2462};
2463
5796c8dc
SS
2464static const struct dis386 reg_table[][8] = {
2465 /* REG_80 */
2466 {
ef5ccd6c
JM
2467 { "addA", { Ebh1, Ib } },
2468 { "orA", { Ebh1, Ib } },
2469 { "adcA", { Ebh1, Ib } },
2470 { "sbbA", { Ebh1, Ib } },
2471 { "andA", { Ebh1, Ib } },
2472 { "subA", { Ebh1, Ib } },
2473 { "xorA", { Ebh1, Ib } },
5796c8dc
SS
2474 { "cmpA", { Eb, Ib } },
2475 },
2476 /* REG_81 */
2477 {
ef5ccd6c
JM
2478 { "addQ", { Evh1, Iv } },
2479 { "orQ", { Evh1, Iv } },
2480 { "adcQ", { Evh1, Iv } },
2481 { "sbbQ", { Evh1, Iv } },
2482 { "andQ", { Evh1, Iv } },
2483 { "subQ", { Evh1, Iv } },
2484 { "xorQ", { Evh1, Iv } },
5796c8dc
SS
2485 { "cmpQ", { Ev, Iv } },
2486 },
2487 /* REG_82 */
2488 {
ef5ccd6c
JM
2489 { "addQ", { Evh1, sIb } },
2490 { "orQ", { Evh1, sIb } },
2491 { "adcQ", { Evh1, sIb } },
2492 { "sbbQ", { Evh1, sIb } },
2493 { "andQ", { Evh1, sIb } },
2494 { "subQ", { Evh1, sIb } },
2495 { "xorQ", { Evh1, sIb } },
5796c8dc
SS
2496 { "cmpQ", { Ev, sIb } },
2497 },
2498 /* REG_8F */
2499 {
2500 { "popU", { stackEv } },
cf7f2e2d
JM
2501 { XOP_8F_TABLE (XOP_09) },
2502 { Bad_Opcode },
2503 { Bad_Opcode },
2504 { Bad_Opcode },
2505 { XOP_8F_TABLE (XOP_09) },
5796c8dc
SS
2506 },
2507 /* REG_C0 */
2508 {
2509 { "rolA", { Eb, Ib } },
2510 { "rorA", { Eb, Ib } },
2511 { "rclA", { Eb, Ib } },
2512 { "rcrA", { Eb, Ib } },
2513 { "shlA", { Eb, Ib } },
2514 { "shrA", { Eb, Ib } },
cf7f2e2d 2515 { Bad_Opcode },
5796c8dc
SS
2516 { "sarA", { Eb, Ib } },
2517 },
2518 /* REG_C1 */
2519 {
2520 { "rolQ", { Ev, Ib } },
2521 { "rorQ", { Ev, Ib } },
2522 { "rclQ", { Ev, Ib } },
2523 { "rcrQ", { Ev, Ib } },
2524 { "shlQ", { Ev, Ib } },
2525 { "shrQ", { Ev, Ib } },
cf7f2e2d 2526 { Bad_Opcode },
5796c8dc
SS
2527 { "sarQ", { Ev, Ib } },
2528 },
2529 /* REG_C6 */
2530 {
ef5ccd6c
JM
2531 { "movA", { Ebh3, Ib } },
2532 { Bad_Opcode },
2533 { Bad_Opcode },
2534 { Bad_Opcode },
2535 { Bad_Opcode },
2536 { Bad_Opcode },
2537 { Bad_Opcode },
2538 { MOD_TABLE (MOD_C6_REG_7) },
5796c8dc
SS
2539 },
2540 /* REG_C7 */
2541 {
ef5ccd6c
JM
2542 { "movQ", { Evh3, Iv } },
2543 { Bad_Opcode },
2544 { Bad_Opcode },
2545 { Bad_Opcode },
2546 { Bad_Opcode },
2547 { Bad_Opcode },
2548 { Bad_Opcode },
2549 { MOD_TABLE (MOD_C7_REG_7) },
5796c8dc
SS
2550 },
2551 /* REG_D0 */
2552 {
2553 { "rolA", { Eb, I1 } },
2554 { "rorA", { Eb, I1 } },
2555 { "rclA", { Eb, I1 } },
2556 { "rcrA", { Eb, I1 } },
2557 { "shlA", { Eb, I1 } },
2558 { "shrA", { Eb, I1 } },
cf7f2e2d 2559 { Bad_Opcode },
5796c8dc
SS
2560 { "sarA", { Eb, I1 } },
2561 },
2562 /* REG_D1 */
2563 {
2564 { "rolQ", { Ev, I1 } },
2565 { "rorQ", { Ev, I1 } },
2566 { "rclQ", { Ev, I1 } },
2567 { "rcrQ", { Ev, I1 } },
2568 { "shlQ", { Ev, I1 } },
2569 { "shrQ", { Ev, I1 } },
cf7f2e2d 2570 { Bad_Opcode },
5796c8dc
SS
2571 { "sarQ", { Ev, I1 } },
2572 },
2573 /* REG_D2 */
2574 {
2575 { "rolA", { Eb, CL } },
2576 { "rorA", { Eb, CL } },
2577 { "rclA", { Eb, CL } },
2578 { "rcrA", { Eb, CL } },
2579 { "shlA", { Eb, CL } },
2580 { "shrA", { Eb, CL } },
cf7f2e2d 2581 { Bad_Opcode },
5796c8dc
SS
2582 { "sarA", { Eb, CL } },
2583 },
2584 /* REG_D3 */
2585 {
2586 { "rolQ", { Ev, CL } },
2587 { "rorQ", { Ev, CL } },
2588 { "rclQ", { Ev, CL } },
2589 { "rcrQ", { Ev, CL } },
2590 { "shlQ", { Ev, CL } },
2591 { "shrQ", { Ev, CL } },
cf7f2e2d 2592 { Bad_Opcode },
5796c8dc
SS
2593 { "sarQ", { Ev, CL } },
2594 },
2595 /* REG_F6 */
2596 {
2597 { "testA", { Eb, Ib } },
cf7f2e2d 2598 { Bad_Opcode },
ef5ccd6c
JM
2599 { "notA", { Ebh1 } },
2600 { "negA", { Ebh1 } },
5796c8dc
SS
2601 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2602 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2603 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2604 { "idivA", { Eb } }, /* and idiv for consistency. */
2605 },
2606 /* REG_F7 */
2607 {
2608 { "testQ", { Ev, Iv } },
cf7f2e2d 2609 { Bad_Opcode },
ef5ccd6c
JM
2610 { "notQ", { Evh1 } },
2611 { "negQ", { Evh1 } },
5796c8dc
SS
2612 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2613 { "imulQ", { Ev } },
2614 { "divQ", { Ev } },
2615 { "idivQ", { Ev } },
2616 },
2617 /* REG_FE */
2618 {
ef5ccd6c
JM
2619 { "incA", { Ebh1 } },
2620 { "decA", { Ebh1 } },
5796c8dc
SS
2621 },
2622 /* REG_FF */
2623 {
ef5ccd6c
JM
2624 { "incQ", { Evh1 } },
2625 { "decQ", { Evh1 } },
c50c785c
JM
2626 { "call{T|}", { indirEv } },
2627 { "Jcall{T|}", { indirEp } },
2628 { "jmp{T|}", { indirEv } },
2629 { "Jjmp{T|}", { indirEp } },
5796c8dc 2630 { "pushU", { stackEv } },
cf7f2e2d 2631 { Bad_Opcode },
5796c8dc
SS
2632 },
2633 /* REG_0F00 */
2634 {
2635 { "sldtD", { Sv } },
2636 { "strD", { Sv } },
2637 { "lldt", { Ew } },
2638 { "ltr", { Ew } },
2639 { "verr", { Ew } },
2640 { "verw", { Ew } },
cf7f2e2d
JM
2641 { Bad_Opcode },
2642 { Bad_Opcode },
5796c8dc
SS
2643 },
2644 /* REG_0F01 */
2645 {
2646 { MOD_TABLE (MOD_0F01_REG_0) },
2647 { MOD_TABLE (MOD_0F01_REG_1) },
2648 { MOD_TABLE (MOD_0F01_REG_2) },
2649 { MOD_TABLE (MOD_0F01_REG_3) },
2650 { "smswD", { Sv } },
cf7f2e2d 2651 { Bad_Opcode },
5796c8dc
SS
2652 { "lmsw", { Ew } },
2653 { MOD_TABLE (MOD_0F01_REG_7) },
2654 },
2655 /* REG_0F0D */
2656 {
c50c785c
JM
2657 { "prefetch", { Mb } },
2658 { "prefetchw", { Mb } },
ef5ccd6c
JM
2659 { "prefetch", { Mb } },
2660 { "prefetch", { Mb } },
2661 { "prefetch", { Mb } },
2662 { "prefetch", { Mb } },
2663 { "prefetch", { Mb } },
2664 { "prefetch", { Mb } },
5796c8dc
SS
2665 },
2666 /* REG_0F18 */
2667 {
2668 { MOD_TABLE (MOD_0F18_REG_0) },
2669 { MOD_TABLE (MOD_0F18_REG_1) },
2670 { MOD_TABLE (MOD_0F18_REG_2) },
2671 { MOD_TABLE (MOD_0F18_REG_3) },
ef5ccd6c
JM
2672 { MOD_TABLE (MOD_0F18_REG_4) },
2673 { MOD_TABLE (MOD_0F18_REG_5) },
2674 { MOD_TABLE (MOD_0F18_REG_6) },
2675 { MOD_TABLE (MOD_0F18_REG_7) },
5796c8dc
SS
2676 },
2677 /* REG_0F71 */
2678 {
cf7f2e2d
JM
2679 { Bad_Opcode },
2680 { Bad_Opcode },
5796c8dc 2681 { MOD_TABLE (MOD_0F71_REG_2) },
cf7f2e2d 2682 { Bad_Opcode },
5796c8dc 2683 { MOD_TABLE (MOD_0F71_REG_4) },
cf7f2e2d 2684 { Bad_Opcode },
5796c8dc 2685 { MOD_TABLE (MOD_0F71_REG_6) },
5796c8dc
SS
2686 },
2687 /* REG_0F72 */
2688 {
cf7f2e2d
JM
2689 { Bad_Opcode },
2690 { Bad_Opcode },
5796c8dc 2691 { MOD_TABLE (MOD_0F72_REG_2) },
cf7f2e2d 2692 { Bad_Opcode },
5796c8dc 2693 { MOD_TABLE (MOD_0F72_REG_4) },
cf7f2e2d 2694 { Bad_Opcode },
5796c8dc 2695 { MOD_TABLE (MOD_0F72_REG_6) },
5796c8dc
SS
2696 },
2697 /* REG_0F73 */
2698 {
cf7f2e2d
JM
2699 { Bad_Opcode },
2700 { Bad_Opcode },
5796c8dc
SS
2701 { MOD_TABLE (MOD_0F73_REG_2) },
2702 { MOD_TABLE (MOD_0F73_REG_3) },
cf7f2e2d
JM
2703 { Bad_Opcode },
2704 { Bad_Opcode },
5796c8dc
SS
2705 { MOD_TABLE (MOD_0F73_REG_6) },
2706 { MOD_TABLE (MOD_0F73_REG_7) },
2707 },
2708 /* REG_0FA6 */
2709 {
2710 { "montmul", { { OP_0f07, 0 } } },
2711 { "xsha1", { { OP_0f07, 0 } } },
2712 { "xsha256", { { OP_0f07, 0 } } },
5796c8dc
SS
2713 },
2714 /* REG_0FA7 */
2715 {
2716 { "xstore-rng", { { OP_0f07, 0 } } },
2717 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2718 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2719 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2720 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2721 { "xcrypt-ofb", { { OP_0f07, 0 } } },
5796c8dc
SS
2722 },
2723 /* REG_0FAE */
2724 {
2725 { MOD_TABLE (MOD_0FAE_REG_0) },
2726 { MOD_TABLE (MOD_0FAE_REG_1) },
2727 { MOD_TABLE (MOD_0FAE_REG_2) },
2728 { MOD_TABLE (MOD_0FAE_REG_3) },
2729 { MOD_TABLE (MOD_0FAE_REG_4) },
2730 { MOD_TABLE (MOD_0FAE_REG_5) },
2731 { MOD_TABLE (MOD_0FAE_REG_6) },
2732 { MOD_TABLE (MOD_0FAE_REG_7) },
2733 },
2734 /* REG_0FBA */
2735 {
cf7f2e2d
JM
2736 { Bad_Opcode },
2737 { Bad_Opcode },
2738 { Bad_Opcode },
2739 { Bad_Opcode },
5796c8dc 2740 { "btQ", { Ev, Ib } },
ef5ccd6c
JM
2741 { "btsQ", { Evh1, Ib } },
2742 { "btrQ", { Evh1, Ib } },
2743 { "btcQ", { Evh1, Ib } },
5796c8dc
SS
2744 },
2745 /* REG_0FC7 */
2746 {
cf7f2e2d 2747 { Bad_Opcode },
5796c8dc 2748 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
cf7f2e2d
JM
2749 { Bad_Opcode },
2750 { Bad_Opcode },
2751 { Bad_Opcode },
2752 { Bad_Opcode },
5796c8dc
SS
2753 { MOD_TABLE (MOD_0FC7_REG_6) },
2754 { MOD_TABLE (MOD_0FC7_REG_7) },
2755 },
c50c785c 2756 /* REG_VEX_0F71 */
5796c8dc 2757 {
cf7f2e2d
JM
2758 { Bad_Opcode },
2759 { Bad_Opcode },
c50c785c 2760 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
cf7f2e2d 2761 { Bad_Opcode },
c50c785c 2762 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
cf7f2e2d 2763 { Bad_Opcode },
c50c785c 2764 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
5796c8dc 2765 },
c50c785c 2766 /* REG_VEX_0F72 */
5796c8dc 2767 {
cf7f2e2d
JM
2768 { Bad_Opcode },
2769 { Bad_Opcode },
c50c785c 2770 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
cf7f2e2d 2771 { Bad_Opcode },
c50c785c 2772 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
cf7f2e2d 2773 { Bad_Opcode },
c50c785c 2774 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
5796c8dc 2775 },
c50c785c 2776 /* REG_VEX_0F73 */
5796c8dc 2777 {
cf7f2e2d
JM
2778 { Bad_Opcode },
2779 { Bad_Opcode },
c50c785c
JM
2780 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2781 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
cf7f2e2d
JM
2782 { Bad_Opcode },
2783 { Bad_Opcode },
c50c785c
JM
2784 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2785 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
5796c8dc 2786 },
c50c785c 2787 /* REG_VEX_0FAE */
5796c8dc 2788 {
cf7f2e2d
JM
2789 { Bad_Opcode },
2790 { Bad_Opcode },
c50c785c
JM
2791 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2792 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2793 },
2794 /* REG_VEX_0F38F3 */
2795 {
2796 { Bad_Opcode },
2797 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2798 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2799 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
cf7f2e2d
JM
2800 },
2801 /* REG_XOP_LWPCB */
2802 {
2803 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2804 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2805 },
2806 /* REG_XOP_LWP */
2807 {
2808 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2809 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
5796c8dc 2810 },
c50c785c
JM
2811 /* REG_XOP_TBM_01 */
2812 {
2813 { Bad_Opcode },
2814 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
2815 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
2816 { "blcs", { { OP_LWP_E, 0 }, Ev } },
2817 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
2818 { "blcic", { { OP_LWP_E, 0 }, Ev } },
2819 { "blsic", { { OP_LWP_E, 0 }, Ev } },
2820 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2821 },
2822 /* REG_XOP_TBM_02 */
2823 {
2824 { Bad_Opcode },
2825 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2826 { Bad_Opcode },
2827 { Bad_Opcode },
2828 { Bad_Opcode },
2829 { Bad_Opcode },
2830 { "blci", { { OP_LWP_E, 0 }, Ev } },
2831 },
5796c8dc
SS
2832};
2833
2834static const struct dis386 prefix_table[][4] = {
2835 /* PREFIX_90 */
2836 {
2837 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2838 { "pause", { XX } },
2839 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
5796c8dc
SS
2840 },
2841
2842 /* PREFIX_0F10 */
2843 {
2844 { "movups", { XM, EXx } },
2845 { "movss", { XM, EXd } },
2846 { "movupd", { XM, EXx } },
2847 { "movsd", { XM, EXq } },
2848 },
2849
2850 /* PREFIX_0F11 */
2851 {
2852 { "movups", { EXxS, XM } },
2853 { "movss", { EXdS, XM } },
2854 { "movupd", { EXxS, XM } },
2855 { "movsd", { EXqS, XM } },
2856 },
2857
2858 /* PREFIX_0F12 */
2859 {
2860 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2861 { "movsldup", { XM, EXx } },
2862 { "movlpd", { XM, EXq } },
2863 { "movddup", { XM, EXq } },
2864 },
2865
2866 /* PREFIX_0F16 */
2867 {
2868 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2869 { "movshdup", { XM, EXx } },
2870 { "movhpd", { XM, EXq } },
5796c8dc
SS
2871 },
2872
2873 /* PREFIX_0F2A */
2874 {
2875 { "cvtpi2ps", { XM, EMCq } },
2876 { "cvtsi2ss%LQ", { XM, Ev } },
2877 { "cvtpi2pd", { XM, EMCq } },
2878 { "cvtsi2sd%LQ", { XM, Ev } },
2879 },
2880
2881 /* PREFIX_0F2B */
2882 {
2883 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2884 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2885 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2886 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2887 },
2888
2889 /* PREFIX_0F2C */
2890 {
2891 { "cvttps2pi", { MXC, EXq } },
2892 { "cvttss2siY", { Gv, EXd } },
2893 { "cvttpd2pi", { MXC, EXx } },
2894 { "cvttsd2siY", { Gv, EXq } },
2895 },
2896
2897 /* PREFIX_0F2D */
2898 {
2899 { "cvtps2pi", { MXC, EXq } },
2900 { "cvtss2siY", { Gv, EXd } },
2901 { "cvtpd2pi", { MXC, EXx } },
2902 { "cvtsd2siY", { Gv, EXq } },
2903 },
2904
2905 /* PREFIX_0F2E */
2906 {
ef5ccd6c 2907 { "ucomiss",{ XM, EXd } },
cf7f2e2d 2908 { Bad_Opcode },
ef5ccd6c 2909 { "ucomisd",{ XM, EXq } },
5796c8dc
SS
2910 },
2911
2912 /* PREFIX_0F2F */
2913 {
2914 { "comiss", { XM, EXd } },
cf7f2e2d 2915 { Bad_Opcode },
5796c8dc 2916 { "comisd", { XM, EXq } },
5796c8dc
SS
2917 },
2918
2919 /* PREFIX_0F51 */
2920 {
2921 { "sqrtps", { XM, EXx } },
2922 { "sqrtss", { XM, EXd } },
2923 { "sqrtpd", { XM, EXx } },
2924 { "sqrtsd", { XM, EXq } },
2925 },
2926
2927 /* PREFIX_0F52 */
2928 {
2929 { "rsqrtps",{ XM, EXx } },
2930 { "rsqrtss",{ XM, EXd } },
5796c8dc
SS
2931 },
2932
2933 /* PREFIX_0F53 */
2934 {
2935 { "rcpps", { XM, EXx } },
2936 { "rcpss", { XM, EXd } },
5796c8dc
SS
2937 },
2938
2939 /* PREFIX_0F58 */
2940 {
2941 { "addps", { XM, EXx } },
2942 { "addss", { XM, EXd } },
2943 { "addpd", { XM, EXx } },
2944 { "addsd", { XM, EXq } },
2945 },
2946
2947 /* PREFIX_0F59 */
2948 {
2949 { "mulps", { XM, EXx } },
2950 { "mulss", { XM, EXd } },
2951 { "mulpd", { XM, EXx } },
2952 { "mulsd", { XM, EXq } },
2953 },
2954
2955 /* PREFIX_0F5A */
2956 {
2957 { "cvtps2pd", { XM, EXq } },
2958 { "cvtss2sd", { XM, EXd } },
2959 { "cvtpd2ps", { XM, EXx } },
2960 { "cvtsd2ss", { XM, EXq } },
2961 },
2962
2963 /* PREFIX_0F5B */
2964 {
2965 { "cvtdq2ps", { XM, EXx } },
2966 { "cvttps2dq", { XM, EXx } },
2967 { "cvtps2dq", { XM, EXx } },
5796c8dc
SS
2968 },
2969
2970 /* PREFIX_0F5C */
2971 {
2972 { "subps", { XM, EXx } },
2973 { "subss", { XM, EXd } },
2974 { "subpd", { XM, EXx } },
2975 { "subsd", { XM, EXq } },
2976 },
2977
2978 /* PREFIX_0F5D */
2979 {
2980 { "minps", { XM, EXx } },
2981 { "minss", { XM, EXd } },
2982 { "minpd", { XM, EXx } },
2983 { "minsd", { XM, EXq } },
2984 },
2985
2986 /* PREFIX_0F5E */
2987 {
2988 { "divps", { XM, EXx } },
2989 { "divss", { XM, EXd } },
2990 { "divpd", { XM, EXx } },
2991 { "divsd", { XM, EXq } },
2992 },
2993
2994 /* PREFIX_0F5F */
2995 {
2996 { "maxps", { XM, EXx } },
2997 { "maxss", { XM, EXd } },
2998 { "maxpd", { XM, EXx } },
2999 { "maxsd", { XM, EXq } },
3000 },
3001
3002 /* PREFIX_0F60 */
3003 {
3004 { "punpcklbw",{ MX, EMd } },
cf7f2e2d 3005 { Bad_Opcode },
5796c8dc 3006 { "punpcklbw",{ MX, EMx } },
5796c8dc
SS
3007 },
3008
3009 /* PREFIX_0F61 */
3010 {
3011 { "punpcklwd",{ MX, EMd } },
cf7f2e2d 3012 { Bad_Opcode },
5796c8dc 3013 { "punpcklwd",{ MX, EMx } },
5796c8dc
SS
3014 },
3015
3016 /* PREFIX_0F62 */
3017 {
3018 { "punpckldq",{ MX, EMd } },
cf7f2e2d 3019 { Bad_Opcode },
5796c8dc 3020 { "punpckldq",{ MX, EMx } },
5796c8dc
SS
3021 },
3022
3023 /* PREFIX_0F6C */
3024 {
cf7f2e2d
JM
3025 { Bad_Opcode },
3026 { Bad_Opcode },
5796c8dc 3027 { "punpcklqdq", { XM, EXx } },
5796c8dc
SS
3028 },
3029
3030 /* PREFIX_0F6D */
3031 {
cf7f2e2d
JM
3032 { Bad_Opcode },
3033 { Bad_Opcode },
5796c8dc 3034 { "punpckhqdq", { XM, EXx } },
5796c8dc
SS
3035 },
3036
3037 /* PREFIX_0F6F */
3038 {
3039 { "movq", { MX, EM } },
3040 { "movdqu", { XM, EXx } },
3041 { "movdqa", { XM, EXx } },
5796c8dc
SS
3042 },
3043
3044 /* PREFIX_0F70 */
3045 {
3046 { "pshufw", { MX, EM, Ib } },
3047 { "pshufhw",{ XM, EXx, Ib } },
3048 { "pshufd", { XM, EXx, Ib } },
3049 { "pshuflw",{ XM, EXx, Ib } },
3050 },
3051
3052 /* PREFIX_0F73_REG_3 */
3053 {
cf7f2e2d
JM
3054 { Bad_Opcode },
3055 { Bad_Opcode },
5796c8dc 3056 { "psrldq", { XS, Ib } },
5796c8dc
SS
3057 },
3058
3059 /* PREFIX_0F73_REG_7 */
3060 {
cf7f2e2d
JM
3061 { Bad_Opcode },
3062 { Bad_Opcode },
5796c8dc 3063 { "pslldq", { XS, Ib } },
5796c8dc
SS
3064 },
3065
3066 /* PREFIX_0F78 */
3067 {
3068 {"vmread", { Em, Gm } },
cf7f2e2d 3069 { Bad_Opcode },
5796c8dc
SS
3070 {"extrq", { XS, Ib, Ib } },
3071 {"insertq", { XM, XS, Ib, Ib } },
3072 },
3073
3074 /* PREFIX_0F79 */
3075 {
3076 {"vmwrite", { Gm, Em } },
cf7f2e2d 3077 { Bad_Opcode },
5796c8dc
SS
3078 {"extrq", { XM, XS } },
3079 {"insertq", { XM, XS } },
3080 },
3081
3082 /* PREFIX_0F7C */
3083 {
cf7f2e2d
JM
3084 { Bad_Opcode },
3085 { Bad_Opcode },
5796c8dc
SS
3086 { "haddpd", { XM, EXx } },
3087 { "haddps", { XM, EXx } },
3088 },
3089
3090 /* PREFIX_0F7D */
3091 {
cf7f2e2d
JM
3092 { Bad_Opcode },
3093 { Bad_Opcode },
5796c8dc
SS
3094 { "hsubpd", { XM, EXx } },
3095 { "hsubps", { XM, EXx } },
3096 },
3097
3098 /* PREFIX_0F7E */
3099 {
3100 { "movK", { Edq, MX } },
3101 { "movq", { XM, EXq } },
3102 { "movK", { Edq, XM } },
5796c8dc
SS
3103 },
3104
3105 /* PREFIX_0F7F */
3106 {
3107 { "movq", { EMS, MX } },
3108 { "movdqu", { EXxS, XM } },
3109 { "movdqa", { EXxS, XM } },
cf7f2e2d
JM
3110 },
3111
3112 /* PREFIX_0FAE_REG_0 */
3113 {
3114 { Bad_Opcode },
3115 { "rdfsbase", { Ev } },
3116 },
3117
3118 /* PREFIX_0FAE_REG_1 */
3119 {
3120 { Bad_Opcode },
3121 { "rdgsbase", { Ev } },
3122 },
3123
3124 /* PREFIX_0FAE_REG_2 */
3125 {
3126 { Bad_Opcode },
3127 { "wrfsbase", { Ev } },
3128 },
3129
3130 /* PREFIX_0FAE_REG_3 */
3131 {
3132 { Bad_Opcode },
3133 { "wrgsbase", { Ev } },
5796c8dc
SS
3134 },
3135
3136 /* PREFIX_0FB8 */
3137 {
cf7f2e2d 3138 { Bad_Opcode },
5796c8dc 3139 { "popcntS", { Gv, Ev } },
5796c8dc
SS
3140 },
3141
c50c785c
JM
3142 /* PREFIX_0FBC */
3143 {
3144 { "bsfS", { Gv, Ev } },
3145 { "tzcntS", { Gv, Ev } },
3146 { "bsfS", { Gv, Ev } },
3147 },
3148
5796c8dc
SS
3149 /* PREFIX_0FBD */
3150 {
3151 { "bsrS", { Gv, Ev } },
3152 { "lzcntS", { Gv, Ev } },
3153 { "bsrS", { Gv, Ev } },
5796c8dc
SS
3154 },
3155
3156 /* PREFIX_0FC2 */
3157 {
3158 { "cmpps", { XM, EXx, CMP } },
3159 { "cmpss", { XM, EXd, CMP } },
3160 { "cmppd", { XM, EXx, CMP } },
3161 { "cmpsd", { XM, EXq, CMP } },
3162 },
3163
3164 /* PREFIX_0FC3 */
3165 {
3166 { "movntiS", { Ma, Gv } },
5796c8dc
SS
3167 },
3168
3169 /* PREFIX_0FC7_REG_6 */
3170 {
3171 { "vmptrld",{ Mq } },
3172 { "vmxon", { Mq } },
3173 { "vmclear",{ Mq } },
5796c8dc
SS
3174 },
3175
3176 /* PREFIX_0FD0 */
3177 {
cf7f2e2d
JM
3178 { Bad_Opcode },
3179 { Bad_Opcode },
5796c8dc
SS
3180 { "addsubpd", { XM, EXx } },
3181 { "addsubps", { XM, EXx } },
3182 },
3183
3184 /* PREFIX_0FD6 */
3185 {
cf7f2e2d 3186 { Bad_Opcode },
5796c8dc
SS
3187 { "movq2dq",{ XM, MS } },
3188 { "movq", { EXqS, XM } },
3189 { "movdq2q",{ MX, XS } },
3190 },
3191
3192 /* PREFIX_0FE6 */
3193 {
cf7f2e2d 3194 { Bad_Opcode },
5796c8dc
SS
3195 { "cvtdq2pd", { XM, EXq } },
3196 { "cvttpd2dq", { XM, EXx } },
3197 { "cvtpd2dq", { XM, EXx } },
3198 },
3199
3200 /* PREFIX_0FE7 */
3201 {
3202 { "movntq", { Mq, MX } },
cf7f2e2d 3203 { Bad_Opcode },
5796c8dc 3204 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
5796c8dc
SS
3205 },
3206
3207 /* PREFIX_0FF0 */
3208 {
cf7f2e2d
JM
3209 { Bad_Opcode },
3210 { Bad_Opcode },
3211 { Bad_Opcode },
5796c8dc
SS
3212 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3213 },
3214
3215 /* PREFIX_0FF7 */
3216 {
3217 { "maskmovq", { MX, MS } },
cf7f2e2d 3218 { Bad_Opcode },
5796c8dc 3219 { "maskmovdqu", { XM, XS } },
5796c8dc
SS
3220 },
3221
3222 /* PREFIX_0F3810 */
3223 {
cf7f2e2d
JM
3224 { Bad_Opcode },
3225 { Bad_Opcode },
5796c8dc 3226 { "pblendvb", { XM, EXx, XMM0 } },
5796c8dc
SS
3227 },
3228
3229 /* PREFIX_0F3814 */
3230 {
cf7f2e2d
JM
3231 { Bad_Opcode },
3232 { Bad_Opcode },
5796c8dc 3233 { "blendvps", { XM, EXx, XMM0 } },
5796c8dc
SS
3234 },
3235
3236 /* PREFIX_0F3815 */
3237 {
cf7f2e2d
JM
3238 { Bad_Opcode },
3239 { Bad_Opcode },
5796c8dc 3240 { "blendvpd", { XM, EXx, XMM0 } },
5796c8dc
SS
3241 },
3242
3243 /* PREFIX_0F3817 */
3244 {
cf7f2e2d
JM
3245 { Bad_Opcode },
3246 { Bad_Opcode },
5796c8dc 3247 { "ptest", { XM, EXx } },
5796c8dc
SS
3248 },
3249
3250 /* PREFIX_0F3820 */
3251 {
cf7f2e2d
JM
3252 { Bad_Opcode },
3253 { Bad_Opcode },
5796c8dc 3254 { "pmovsxbw", { XM, EXq } },
5796c8dc
SS
3255 },
3256
3257 /* PREFIX_0F3821 */
3258 {
cf7f2e2d
JM
3259 { Bad_Opcode },
3260 { Bad_Opcode },
5796c8dc 3261 { "pmovsxbd", { XM, EXd } },
5796c8dc
SS
3262 },
3263
3264 /* PREFIX_0F3822 */
3265 {
cf7f2e2d
JM
3266 { Bad_Opcode },
3267 { Bad_Opcode },
5796c8dc 3268 { "pmovsxbq", { XM, EXw } },
5796c8dc
SS
3269 },
3270
3271 /* PREFIX_0F3823 */
3272 {
cf7f2e2d
JM
3273 { Bad_Opcode },
3274 { Bad_Opcode },
5796c8dc 3275 { "pmovsxwd", { XM, EXq } },
5796c8dc
SS
3276 },
3277
3278 /* PREFIX_0F3824 */
3279 {
cf7f2e2d
JM
3280 { Bad_Opcode },
3281 { Bad_Opcode },
5796c8dc 3282 { "pmovsxwq", { XM, EXd } },
5796c8dc
SS
3283 },
3284
3285 /* PREFIX_0F3825 */
3286 {
cf7f2e2d
JM
3287 { Bad_Opcode },
3288 { Bad_Opcode },
5796c8dc 3289 { "pmovsxdq", { XM, EXq } },
5796c8dc
SS
3290 },
3291
3292 /* PREFIX_0F3828 */
3293 {
cf7f2e2d
JM
3294 { Bad_Opcode },
3295 { Bad_Opcode },
5796c8dc 3296 { "pmuldq", { XM, EXx } },
5796c8dc
SS
3297 },
3298
3299 /* PREFIX_0F3829 */
3300 {
cf7f2e2d
JM
3301 { Bad_Opcode },
3302 { Bad_Opcode },
5796c8dc 3303 { "pcmpeqq", { XM, EXx } },
5796c8dc
SS
3304 },
3305
3306 /* PREFIX_0F382A */
3307 {
cf7f2e2d
JM
3308 { Bad_Opcode },
3309 { Bad_Opcode },
5796c8dc 3310 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
5796c8dc
SS
3311 },
3312
3313 /* PREFIX_0F382B */
3314 {
cf7f2e2d
JM
3315 { Bad_Opcode },
3316 { Bad_Opcode },
5796c8dc 3317 { "packusdw", { XM, EXx } },
5796c8dc
SS
3318 },
3319
3320 /* PREFIX_0F3830 */
3321 {
cf7f2e2d
JM
3322 { Bad_Opcode },
3323 { Bad_Opcode },
5796c8dc 3324 { "pmovzxbw", { XM, EXq } },
5796c8dc
SS
3325 },
3326
3327 /* PREFIX_0F3831 */
3328 {
cf7f2e2d
JM
3329 { Bad_Opcode },
3330 { Bad_Opcode },
5796c8dc 3331 { "pmovzxbd", { XM, EXd } },
5796c8dc
SS
3332 },
3333
3334 /* PREFIX_0F3832 */
3335 {
cf7f2e2d
JM
3336 { Bad_Opcode },
3337 { Bad_Opcode },
5796c8dc 3338 { "pmovzxbq", { XM, EXw } },
5796c8dc
SS
3339 },
3340
3341 /* PREFIX_0F3833 */
3342 {
cf7f2e2d
JM
3343 { Bad_Opcode },
3344 { Bad_Opcode },
5796c8dc 3345 { "pmovzxwd", { XM, EXq } },
5796c8dc
SS
3346 },
3347
3348 /* PREFIX_0F3834 */
3349 {
cf7f2e2d
JM
3350 { Bad_Opcode },
3351 { Bad_Opcode },
5796c8dc 3352 { "pmovzxwq", { XM, EXd } },
5796c8dc
SS
3353 },
3354
3355 /* PREFIX_0F3835 */
3356 {
cf7f2e2d
JM
3357 { Bad_Opcode },
3358 { Bad_Opcode },
5796c8dc 3359 { "pmovzxdq", { XM, EXq } },
5796c8dc
SS
3360 },
3361
3362 /* PREFIX_0F3837 */
3363 {
cf7f2e2d
JM
3364 { Bad_Opcode },
3365 { Bad_Opcode },
5796c8dc 3366 { "pcmpgtq", { XM, EXx } },
5796c8dc
SS
3367 },
3368
3369 /* PREFIX_0F3838 */
3370 {
cf7f2e2d
JM
3371 { Bad_Opcode },
3372 { Bad_Opcode },
5796c8dc 3373 { "pminsb", { XM, EXx } },
5796c8dc
SS
3374 },
3375
3376 /* PREFIX_0F3839 */
3377 {
cf7f2e2d
JM
3378 { Bad_Opcode },
3379 { Bad_Opcode },
5796c8dc 3380 { "pminsd", { XM, EXx } },
5796c8dc
SS
3381 },
3382
3383 /* PREFIX_0F383A */
3384 {
cf7f2e2d
JM
3385 { Bad_Opcode },
3386 { Bad_Opcode },
5796c8dc 3387 { "pminuw", { XM, EXx } },
5796c8dc
SS
3388 },
3389
3390 /* PREFIX_0F383B */
3391 {
cf7f2e2d
JM
3392 { Bad_Opcode },
3393 { Bad_Opcode },
5796c8dc 3394 { "pminud", { XM, EXx } },
5796c8dc
SS
3395 },
3396
3397 /* PREFIX_0F383C */
3398 {
cf7f2e2d
JM
3399 { Bad_Opcode },
3400 { Bad_Opcode },
5796c8dc 3401 { "pmaxsb", { XM, EXx } },
5796c8dc
SS
3402 },
3403
3404 /* PREFIX_0F383D */
3405 {
cf7f2e2d
JM
3406 { Bad_Opcode },
3407 { Bad_Opcode },
5796c8dc 3408 { "pmaxsd", { XM, EXx } },
5796c8dc
SS
3409 },
3410
3411 /* PREFIX_0F383E */
3412 {
cf7f2e2d
JM
3413 { Bad_Opcode },
3414 { Bad_Opcode },
5796c8dc 3415 { "pmaxuw", { XM, EXx } },
5796c8dc
SS
3416 },
3417
3418 /* PREFIX_0F383F */
3419 {
cf7f2e2d
JM
3420 { Bad_Opcode },
3421 { Bad_Opcode },
5796c8dc 3422 { "pmaxud", { XM, EXx } },
5796c8dc
SS
3423 },
3424
3425 /* PREFIX_0F3840 */
3426 {
cf7f2e2d
JM
3427 { Bad_Opcode },
3428 { Bad_Opcode },
5796c8dc 3429 { "pmulld", { XM, EXx } },
5796c8dc
SS
3430 },
3431
3432 /* PREFIX_0F3841 */
3433 {
cf7f2e2d
JM
3434 { Bad_Opcode },
3435 { Bad_Opcode },
5796c8dc 3436 { "phminposuw", { XM, EXx } },
5796c8dc
SS
3437 },
3438
3439 /* PREFIX_0F3880 */
3440 {
cf7f2e2d
JM
3441 { Bad_Opcode },
3442 { Bad_Opcode },
5796c8dc 3443 { "invept", { Gm, Mo } },
5796c8dc
SS
3444 },
3445
3446 /* PREFIX_0F3881 */
3447 {
cf7f2e2d
JM
3448 { Bad_Opcode },
3449 { Bad_Opcode },
5796c8dc 3450 { "invvpid", { Gm, Mo } },
5796c8dc
SS
3451 },
3452
a45ae5f8
JM
3453 /* PREFIX_0F3882 */
3454 {
3455 { Bad_Opcode },
3456 { Bad_Opcode },
3457 { "invpcid", { Gm, M } },
3458 },
3459
5796c8dc
SS
3460 /* PREFIX_0F38DB */
3461 {
cf7f2e2d
JM
3462 { Bad_Opcode },
3463 { Bad_Opcode },
5796c8dc 3464 { "aesimc", { XM, EXx } },
5796c8dc
SS
3465 },
3466
3467 /* PREFIX_0F38DC */
3468 {
cf7f2e2d
JM
3469 { Bad_Opcode },
3470 { Bad_Opcode },
5796c8dc 3471 { "aesenc", { XM, EXx } },
5796c8dc
SS
3472 },
3473
3474 /* PREFIX_0F38DD */
3475 {
cf7f2e2d
JM
3476 { Bad_Opcode },
3477 { Bad_Opcode },
5796c8dc 3478 { "aesenclast", { XM, EXx } },
5796c8dc
SS
3479 },
3480
3481 /* PREFIX_0F38DE */
3482 {
cf7f2e2d
JM
3483 { Bad_Opcode },
3484 { Bad_Opcode },
5796c8dc 3485 { "aesdec", { XM, EXx } },
5796c8dc
SS
3486 },
3487
3488 /* PREFIX_0F38DF */
3489 {
cf7f2e2d
JM
3490 { Bad_Opcode },
3491 { Bad_Opcode },
5796c8dc 3492 { "aesdeclast", { XM, EXx } },
5796c8dc
SS
3493 },
3494
3495 /* PREFIX_0F38F0 */
3496 {
3497 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
cf7f2e2d 3498 { Bad_Opcode },
5796c8dc 3499 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
ef5ccd6c 3500 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
5796c8dc
SS
3501 },
3502
3503 /* PREFIX_0F38F1 */
3504 {
3505 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
cf7f2e2d 3506 { Bad_Opcode },
5796c8dc 3507 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
ef5ccd6c
JM
3508 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3509 },
3510
3511 /* PREFIX_0F38F6 */
3512 {
3513 { Bad_Opcode },
3514 { "adoxS", { Gdq, Edq} },
3515 { "adcxS", { Gdq, Edq} },
3516 { Bad_Opcode },
5796c8dc
SS
3517 },
3518
3519 /* PREFIX_0F3A08 */
3520 {
cf7f2e2d
JM
3521 { Bad_Opcode },
3522 { Bad_Opcode },
5796c8dc 3523 { "roundps", { XM, EXx, Ib } },
5796c8dc
SS
3524 },
3525
3526 /* PREFIX_0F3A09 */
3527 {
cf7f2e2d
JM
3528 { Bad_Opcode },
3529 { Bad_Opcode },
5796c8dc 3530 { "roundpd", { XM, EXx, Ib } },
5796c8dc
SS
3531 },
3532
3533 /* PREFIX_0F3A0A */
3534 {
cf7f2e2d
JM
3535 { Bad_Opcode },
3536 { Bad_Opcode },
5796c8dc 3537 { "roundss", { XM, EXd, Ib } },
5796c8dc
SS
3538 },
3539
3540 /* PREFIX_0F3A0B */
3541 {
cf7f2e2d
JM
3542 { Bad_Opcode },
3543 { Bad_Opcode },
5796c8dc 3544 { "roundsd", { XM, EXq, Ib } },
5796c8dc
SS
3545 },
3546
3547 /* PREFIX_0F3A0C */
3548 {
cf7f2e2d
JM
3549 { Bad_Opcode },
3550 { Bad_Opcode },
5796c8dc 3551 { "blendps", { XM, EXx, Ib } },
5796c8dc
SS
3552 },
3553
3554 /* PREFIX_0F3A0D */
3555 {
cf7f2e2d
JM
3556 { Bad_Opcode },
3557 { Bad_Opcode },
5796c8dc 3558 { "blendpd", { XM, EXx, Ib } },
5796c8dc
SS
3559 },
3560
3561 /* PREFIX_0F3A0E */
3562 {
cf7f2e2d
JM
3563 { Bad_Opcode },
3564 { Bad_Opcode },
5796c8dc 3565 { "pblendw", { XM, EXx, Ib } },
5796c8dc
SS
3566 },
3567
3568 /* PREFIX_0F3A14 */
3569 {
cf7f2e2d
JM
3570 { Bad_Opcode },
3571 { Bad_Opcode },
5796c8dc 3572 { "pextrb", { Edqb, XM, Ib } },
5796c8dc
SS
3573 },
3574
3575 /* PREFIX_0F3A15 */
3576 {
cf7f2e2d
JM
3577 { Bad_Opcode },
3578 { Bad_Opcode },
5796c8dc 3579 { "pextrw", { Edqw, XM, Ib } },
5796c8dc
SS
3580 },
3581
3582 /* PREFIX_0F3A16 */
3583 {
cf7f2e2d
JM
3584 { Bad_Opcode },
3585 { Bad_Opcode },
5796c8dc 3586 { "pextrK", { Edq, XM, Ib } },
5796c8dc
SS
3587 },
3588
3589 /* PREFIX_0F3A17 */
3590 {
cf7f2e2d
JM
3591 { Bad_Opcode },
3592 { Bad_Opcode },
5796c8dc 3593 { "extractps", { Edqd, XM, Ib } },
5796c8dc
SS
3594 },
3595
3596 /* PREFIX_0F3A20 */
3597 {
cf7f2e2d
JM
3598 { Bad_Opcode },
3599 { Bad_Opcode },
5796c8dc 3600 { "pinsrb", { XM, Edqb, Ib } },