Commit | Line | Data |
---|---|---|
19df918d FT |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
19df918d FT |
28 | #include "i915_drv.h" |
29 | #include "intel_drv.h" | |
1b13d190 FT |
30 | #include <asm/int-ll64.h> |
31 | ||
32 | struct ddi_buf_trans { | |
33 | u32 trans1; /* balance leg enable, de-emph level */ | |
34 | u32 trans2; /* vref sel, vswing */ | |
35 | }; | |
19df918d FT |
36 | |
37 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
38 | * them for both DP and FDI transports, allowing those ports to | |
39 | * automatically adapt to HDMI connections as well | |
40 | */ | |
1b13d190 FT |
41 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
42 | { 0x00FFFFFF, 0x0006000E }, | |
43 | { 0x00D75FFF, 0x0005000A }, | |
44 | { 0x00C30FFF, 0x00040006 }, | |
45 | { 0x80AAAFFF, 0x000B0000 }, | |
46 | { 0x00FFFFFF, 0x0005000A }, | |
47 | { 0x00D75FFF, 0x000C0004 }, | |
48 | { 0x80C30FFF, 0x000B0000 }, | |
49 | { 0x00FFFFFF, 0x00040006 }, | |
50 | { 0x80D75FFF, 0x000B0000 }, | |
51 | }; | |
52 | ||
53 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { | |
54 | { 0x00FFFFFF, 0x0007000E }, | |
55 | { 0x00D75FFF, 0x000F000A }, | |
56 | { 0x00C30FFF, 0x00060006 }, | |
57 | { 0x00AAAFFF, 0x001E0000 }, | |
58 | { 0x00FFFFFF, 0x000F000A }, | |
59 | { 0x00D75FFF, 0x00160004 }, | |
60 | { 0x00C30FFF, 0x001E0000 }, | |
61 | { 0x00FFFFFF, 0x00060006 }, | |
62 | { 0x00D75FFF, 0x001E0000 }, | |
19df918d FT |
63 | }; |
64 | ||
1b13d190 FT |
65 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
66 | /* Idx NT mV d T mV d db */ | |
67 | { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */ | |
68 | { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */ | |
69 | { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */ | |
70 | { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */ | |
71 | { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */ | |
72 | { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */ | |
73 | { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */ | |
74 | { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */ | |
75 | { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */ | |
76 | { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */ | |
77 | { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */ | |
78 | { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */ | |
19df918d FT |
79 | }; |
80 | ||
1b13d190 FT |
81 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
82 | { 0x00FFFFFF, 0x00000012 }, | |
83 | { 0x00EBAFFF, 0x00020011 }, | |
84 | { 0x00C71FFF, 0x0006000F }, | |
85 | { 0x00AAAFFF, 0x000E000A }, | |
86 | { 0x00FFFFFF, 0x00020011 }, | |
87 | { 0x00DB6FFF, 0x0005000F }, | |
88 | { 0x00BEEFFF, 0x000A000C }, | |
89 | { 0x00FFFFFF, 0x0005000F }, | |
90 | { 0x00DB6FFF, 0x000A000C }, | |
9edbd4a0 FT |
91 | }; |
92 | ||
1b13d190 FT |
93 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
94 | { 0x00FFFFFF, 0x0007000E }, | |
95 | { 0x00D75FFF, 0x000E000A }, | |
96 | { 0x00BEFFFF, 0x00140006 }, | |
97 | { 0x80B2CFFF, 0x001B0002 }, | |
98 | { 0x00FFFFFF, 0x000E000A }, | |
99 | { 0x00D75FFF, 0x00180004 }, | |
100 | { 0x80CB2FFF, 0x001B0002 }, | |
101 | { 0x00F7DFFF, 0x00180004 }, | |
102 | { 0x80D75FFF, 0x001B0002 }, | |
9edbd4a0 FT |
103 | }; |
104 | ||
1b13d190 FT |
105 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
106 | { 0x00FFFFFF, 0x0001000E }, | |
107 | { 0x00D75FFF, 0x0004000A }, | |
108 | { 0x00C30FFF, 0x00070006 }, | |
109 | { 0x00AAAFFF, 0x000C0000 }, | |
110 | { 0x00FFFFFF, 0x0004000A }, | |
111 | { 0x00D75FFF, 0x00090004 }, | |
112 | { 0x00C30FFF, 0x000C0000 }, | |
113 | { 0x00FFFFFF, 0x00070006 }, | |
114 | { 0x00D75FFF, 0x000C0000 }, | |
9edbd4a0 FT |
115 | }; |
116 | ||
1b13d190 FT |
117 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
118 | /* Idx NT mV d T mV df db */ | |
119 | { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */ | |
120 | { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */ | |
121 | { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */ | |
122 | { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */ | |
123 | { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */ | |
124 | { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */ | |
125 | { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */ | |
126 | { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */ | |
127 | { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */ | |
128 | { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */ | |
9edbd4a0 FT |
129 | }; |
130 | ||
131 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) | |
19df918d FT |
132 | { |
133 | struct drm_encoder *encoder = &intel_encoder->base; | |
134 | int type = intel_encoder->type; | |
135 | ||
136 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || | |
137 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { | |
138 | struct intel_digital_port *intel_dig_port = | |
139 | enc_to_dig_port(encoder); | |
140 | return intel_dig_port->port; | |
141 | ||
142 | } else if (type == INTEL_OUTPUT_ANALOG) { | |
143 | return PORT_E; | |
144 | ||
145 | } else { | |
146 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
147 | BUG(); | |
148 | } | |
149 | } | |
150 | ||
9edbd4a0 FT |
151 | /* |
152 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
153 | * values in advance. The buffer values are different for FDI and DP modes, | |
19df918d FT |
154 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
155 | * in either FDI or DP modes only, as HDMI connections will work with both | |
156 | * of those | |
157 | */ | |
9edbd4a0 | 158 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
19df918d FT |
159 | { |
160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
161 | u32 reg; | |
1b13d190 | 162 | int i, n_hdmi_entries, hdmi_800mV_0dB; |
9edbd4a0 | 163 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
1b13d190 FT |
164 | const struct ddi_buf_trans *ddi_translations_fdi; |
165 | const struct ddi_buf_trans *ddi_translations_dp; | |
166 | const struct ddi_buf_trans *ddi_translations_edp; | |
167 | const struct ddi_buf_trans *ddi_translations_hdmi; | |
168 | const struct ddi_buf_trans *ddi_translations; | |
9edbd4a0 FT |
169 | |
170 | if (IS_BROADWELL(dev)) { | |
171 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
172 | ddi_translations_dp = bdw_ddi_translations_dp; | |
173 | ddi_translations_edp = bdw_ddi_translations_edp; | |
1b13d190 FT |
174 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
175 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
176 | hdmi_800mV_0dB = 7; | |
9edbd4a0 FT |
177 | } else if (IS_HASWELL(dev)) { |
178 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
179 | ddi_translations_dp = hsw_ddi_translations_dp; | |
180 | ddi_translations_edp = hsw_ddi_translations_dp; | |
1b13d190 FT |
181 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
182 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); | |
183 | hdmi_800mV_0dB = 6; | |
9edbd4a0 FT |
184 | } else { |
185 | WARN(1, "ddi translation table missing\n"); | |
186 | ddi_translations_edp = bdw_ddi_translations_dp; | |
187 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
188 | ddi_translations_dp = bdw_ddi_translations_dp; | |
1b13d190 FT |
189 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
190 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); | |
191 | hdmi_800mV_0dB = 7; | |
9edbd4a0 | 192 | } |
19df918d | 193 | |
9edbd4a0 FT |
194 | switch (port) { |
195 | case PORT_A: | |
196 | ddi_translations = ddi_translations_edp; | |
197 | break; | |
198 | case PORT_B: | |
199 | case PORT_C: | |
200 | ddi_translations = ddi_translations_dp; | |
201 | break; | |
202 | case PORT_D: | |
203 | if (intel_dp_is_edp(dev, PORT_D)) | |
204 | ddi_translations = ddi_translations_edp; | |
205 | else | |
206 | ddi_translations = ddi_translations_dp; | |
207 | break; | |
208 | case PORT_E: | |
209 | ddi_translations = ddi_translations_fdi; | |
210 | break; | |
211 | default: | |
212 | BUG(); | |
213 | } | |
19df918d | 214 | |
9edbd4a0 FT |
215 | for (i = 0, reg = DDI_BUF_TRANS(port); |
216 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
1b13d190 | 217 | I915_WRITE(reg, ddi_translations[i].trans1); |
19df918d | 218 | reg += 4; |
1b13d190 | 219 | I915_WRITE(reg, ddi_translations[i].trans2); |
9edbd4a0 FT |
220 | reg += 4; |
221 | } | |
1b13d190 FT |
222 | |
223 | /* Choose a good default if VBT is badly populated */ | |
224 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || | |
225 | hdmi_level >= n_hdmi_entries) | |
226 | hdmi_level = hdmi_800mV_0dB; | |
227 | ||
228 | /* Entry 9 is for HDMI: */ | |
229 | I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1); | |
230 | reg += 4; | |
231 | I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2); | |
232 | reg += 4; | |
19df918d FT |
233 | } |
234 | ||
235 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
236 | * mode and port E for FDI. | |
237 | */ | |
238 | void intel_prepare_ddi(struct drm_device *dev) | |
239 | { | |
240 | int port; | |
241 | ||
a2fdbec6 FT |
242 | if (!HAS_DDI(dev)) |
243 | return; | |
19df918d | 244 | |
9edbd4a0 FT |
245 | for (port = PORT_A; port <= PORT_E; port++) |
246 | intel_prepare_ddi_buffers(dev, port); | |
19df918d FT |
247 | } |
248 | ||
19df918d FT |
249 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
250 | enum port port) | |
251 | { | |
252 | uint32_t reg = DDI_BUF_CTL(port); | |
253 | int i; | |
254 | ||
255 | for (i = 0; i < 8; i++) { | |
256 | udelay(1); | |
257 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
258 | return; | |
259 | } | |
260 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
261 | } | |
262 | ||
263 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
264 | * connection to the PCH-located connectors. For this, it is necessary to train | |
265 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
266 | * | |
267 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
268 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
269 | * DDI A (which is used for eDP) | |
270 | */ | |
271 | ||
272 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
273 | { | |
274 | struct drm_device *dev = crtc->dev; | |
275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
276 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
277 | u32 temp, i, rx_ctl_val; | |
278 | ||
279 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the | |
280 | * mode set "sequence for CRT port" document: | |
281 | * - TP1 to TP2 time with the default value | |
282 | * - FDI delay to 90h | |
5d0b1887 FT |
283 | * |
284 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
19df918d FT |
285 | */ |
286 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
287 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
288 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
289 | ||
290 | /* Enable the PCH Receiver FDI PLL */ | |
291 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | | |
5d0b1887 FT |
292 | FDI_RX_PLL_ENABLE | |
293 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
19df918d FT |
294 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
295 | POSTING_READ(_FDI_RXA_CTL); | |
296 | udelay(220); | |
297 | ||
298 | /* Switch from Rawclk to PCDclk */ | |
299 | rx_ctl_val |= FDI_PCDCLK; | |
300 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
301 | ||
302 | /* Configure Port Clock Select */ | |
24edb884 FT |
303 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); |
304 | WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
19df918d FT |
305 | |
306 | /* Start the training iterating through available voltages and emphasis, | |
307 | * testing each value twice. */ | |
1b13d190 | 308 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
19df918d FT |
309 | /* Configure DP_TP_CTL with auto-training */ |
310 | I915_WRITE(DP_TP_CTL(PORT_E), | |
311 | DP_TP_CTL_FDI_AUTOTRAIN | | |
312 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
313 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
314 | DP_TP_CTL_ENABLE); | |
315 | ||
316 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. | |
317 | * DDI E does not support port reversal, the functionality is | |
318 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
319 | * port reversal bit */ | |
320 | I915_WRITE(DDI_BUF_CTL(PORT_E), | |
321 | DDI_BUF_CTL_ENABLE | | |
5d0b1887 | 322 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
1b13d190 | 323 | DDI_BUF_TRANS_SELECT(i / 2)); |
19df918d FT |
324 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
325 | ||
326 | udelay(600); | |
327 | ||
328 | /* Program PCH FDI Receiver TU */ | |
329 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
330 | ||
331 | /* Enable PCH FDI Receiver with auto-training */ | |
332 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
333 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
334 | POSTING_READ(_FDI_RXA_CTL); | |
335 | ||
336 | /* Wait for FDI receiver lane calibration */ | |
337 | udelay(30); | |
338 | ||
339 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
340 | temp = I915_READ(_FDI_RXA_MISC); | |
341 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
342 | I915_WRITE(_FDI_RXA_MISC, temp); | |
343 | POSTING_READ(_FDI_RXA_MISC); | |
344 | ||
345 | /* Wait for FDI auto training time */ | |
346 | udelay(5); | |
347 | ||
348 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
349 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
350 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); | |
351 | ||
352 | /* Enable normal pixel sending for FDI */ | |
353 | I915_WRITE(DP_TP_CTL(PORT_E), | |
354 | DP_TP_CTL_FDI_AUTOTRAIN | | |
355 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
356 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
357 | DP_TP_CTL_ENABLE); | |
358 | ||
359 | return; | |
360 | } | |
361 | ||
362 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); | |
363 | temp &= ~DDI_BUF_CTL_ENABLE; | |
364 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
365 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
366 | ||
367 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ | |
368 | temp = I915_READ(DP_TP_CTL(PORT_E)); | |
369 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
370 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
371 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
372 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
373 | ||
374 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
375 | ||
376 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
377 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
378 | POSTING_READ(_FDI_RXA_CTL); | |
379 | ||
380 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
381 | temp = I915_READ(_FDI_RXA_MISC); | |
382 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
383 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
384 | I915_WRITE(_FDI_RXA_MISC, temp); | |
385 | POSTING_READ(_FDI_RXA_MISC); | |
386 | } | |
387 | ||
388 | DRM_ERROR("FDI link training failed!\n"); | |
389 | } | |
390 | ||
1b13d190 FT |
391 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
392 | { | |
393 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
394 | struct intel_digital_port *intel_dig_port = | |
395 | enc_to_dig_port(&encoder->base); | |
396 | ||
397 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
398 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); | |
399 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); | |
400 | ||
401 | } | |
402 | ||
19df918d FT |
403 | static struct intel_encoder * |
404 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
405 | { | |
406 | struct drm_device *dev = crtc->dev; | |
407 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
408 | struct intel_encoder *intel_encoder, *ret = NULL; | |
409 | int num_encoders = 0; | |
410 | ||
411 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
412 | ret = intel_encoder; | |
413 | num_encoders++; | |
414 | } | |
415 | ||
416 | if (num_encoders != 1) | |
5d0b1887 FT |
417 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
418 | pipe_name(intel_crtc->pipe)); | |
19df918d FT |
419 | |
420 | BUG_ON(ret == NULL); | |
421 | return ret; | |
422 | } | |
423 | ||
5d0b1887 | 424 | #define LC_FREQ 2700 |
1b13d190 | 425 | #define LC_FREQ_2K U64_C(LC_FREQ * 2000) |
5d0b1887 FT |
426 | |
427 | #define P_MIN 2 | |
428 | #define P_MAX 64 | |
429 | #define P_INC 2 | |
430 | ||
431 | /* Constraints for PLL good behavior */ | |
432 | #define REF_MIN 48 | |
433 | #define REF_MAX 400 | |
434 | #define VCO_MIN 2400 | |
435 | #define VCO_MAX 4800 | |
436 | ||
1b13d190 FT |
437 | #define abs_diff(a, b) ({ \ |
438 | typeof(a) __a = (a); \ | |
439 | typeof(b) __b = (b); \ | |
440 | (void) (&__a == &__b); \ | |
441 | __a > __b ? (__a - __b) : (__b - __a); }) | |
5d0b1887 FT |
442 | |
443 | struct wrpll_rnp { | |
444 | unsigned p, n2, r2; | |
445 | }; | |
446 | ||
447 | static unsigned wrpll_get_budget_for_freq(int clock) | |
448 | { | |
449 | unsigned budget; | |
450 | ||
451 | switch (clock) { | |
452 | case 25175000: | |
453 | case 25200000: | |
454 | case 27000000: | |
455 | case 27027000: | |
456 | case 37762500: | |
457 | case 37800000: | |
458 | case 40500000: | |
459 | case 40541000: | |
460 | case 54000000: | |
461 | case 54054000: | |
462 | case 59341000: | |
463 | case 59400000: | |
464 | case 72000000: | |
465 | case 74176000: | |
466 | case 74250000: | |
467 | case 81000000: | |
468 | case 81081000: | |
469 | case 89012000: | |
470 | case 89100000: | |
471 | case 108000000: | |
472 | case 108108000: | |
473 | case 111264000: | |
474 | case 111375000: | |
475 | case 148352000: | |
476 | case 148500000: | |
477 | case 162000000: | |
478 | case 162162000: | |
479 | case 222525000: | |
480 | case 222750000: | |
481 | case 296703000: | |
482 | case 297000000: | |
483 | budget = 0; | |
484 | break; | |
485 | case 233500000: | |
486 | case 245250000: | |
487 | case 247750000: | |
488 | case 253250000: | |
489 | case 298000000: | |
490 | budget = 1500; | |
491 | break; | |
492 | case 169128000: | |
493 | case 169500000: | |
494 | case 179500000: | |
495 | case 202000000: | |
496 | budget = 2000; | |
497 | break; | |
498 | case 256250000: | |
499 | case 262500000: | |
500 | case 270000000: | |
501 | case 272500000: | |
502 | case 273750000: | |
503 | case 280750000: | |
504 | case 281250000: | |
505 | case 286000000: | |
506 | case 291750000: | |
507 | budget = 4000; | |
508 | break; | |
509 | case 267250000: | |
510 | case 268500000: | |
511 | budget = 5000; | |
512 | break; | |
513 | default: | |
514 | budget = 1000; | |
515 | break; | |
516 | } | |
517 | ||
518 | return budget; | |
519 | } | |
520 | ||
521 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
522 | unsigned r2, unsigned n2, unsigned p, | |
523 | struct wrpll_rnp *best) | |
19df918d | 524 | { |
5d0b1887 | 525 | uint64_t a, b, c, d, diff, diff_best; |
19df918d | 526 | |
5d0b1887 FT |
527 | /* No best (r,n,p) yet */ |
528 | if (best->p == 0) { | |
529 | best->p = p; | |
530 | best->n2 = n2; | |
531 | best->r2 = r2; | |
532 | return; | |
533 | } | |
534 | ||
535 | /* | |
536 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
537 | * freq2k. | |
538 | * | |
539 | * delta = 1e6 * | |
540 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
541 | * freq2k; | |
542 | * | |
543 | * and we would like delta <= budget. | |
544 | * | |
545 | * If the discrepancy is above the PPM-based budget, always prefer to | |
546 | * improve upon the previous solution. However, if you're within the | |
547 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
548 | */ | |
549 | a = freq2k * budget * p * r2; | |
550 | b = freq2k * budget * best->p * best->r2; | |
1b13d190 FT |
551 | diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); |
552 | diff_best = abs_diff(freq2k * best->p * best->r2, | |
553 | LC_FREQ_2K * best->n2); | |
5d0b1887 FT |
554 | c = 1000000 * diff; |
555 | d = 1000000 * diff_best; | |
556 | ||
557 | if (a < c && b < d) { | |
558 | /* If both are above the budget, pick the closer */ | |
559 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
560 | best->p = p; | |
561 | best->n2 = n2; | |
562 | best->r2 = r2; | |
563 | } | |
564 | } else if (a >= c && b < d) { | |
565 | /* If A is below the threshold but B is above it? Update. */ | |
566 | best->p = p; | |
567 | best->n2 = n2; | |
568 | best->r2 = r2; | |
569 | } else if (a >= c && b >= d) { | |
570 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
571 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
572 | best->p = p; | |
573 | best->n2 = n2; | |
574 | best->r2 = r2; | |
575 | } | |
576 | } | |
577 | /* Otherwise a < c && b >= d, do nothing */ | |
578 | } | |
579 | ||
ba55f2f5 FT |
580 | static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
581 | int reg) | |
582 | { | |
583 | int refclk = LC_FREQ; | |
584 | int n, p, r; | |
585 | u32 wrpll; | |
586 | ||
587 | wrpll = I915_READ(reg); | |
24edb884 FT |
588 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
589 | case WRPLL_PLL_SSC: | |
590 | case WRPLL_PLL_NON_SSC: | |
ba55f2f5 FT |
591 | /* |
592 | * We could calculate spread here, but our checking | |
593 | * code only cares about 5% accuracy, and spread is a max of | |
594 | * 0.5% downspread. | |
595 | */ | |
596 | refclk = 135; | |
597 | break; | |
24edb884 | 598 | case WRPLL_PLL_LCPLL: |
ba55f2f5 FT |
599 | refclk = LC_FREQ; |
600 | break; | |
601 | default: | |
602 | WARN(1, "bad wrpll refclk\n"); | |
603 | return 0; | |
604 | } | |
605 | ||
606 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
607 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
608 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
609 | ||
610 | /* Convert to KHz, p & r have a fixed point portion */ | |
611 | return (refclk * n * 100) / (p * r); | |
612 | } | |
613 | ||
1b13d190 FT |
614 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
615 | struct intel_crtc_config *pipe_config) | |
ba55f2f5 FT |
616 | { |
617 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
ba55f2f5 FT |
618 | int link_clock = 0; |
619 | u32 val, pll; | |
620 | ||
24edb884 | 621 | val = pipe_config->ddi_pll_sel; |
ba55f2f5 FT |
622 | switch (val & PORT_CLK_SEL_MASK) { |
623 | case PORT_CLK_SEL_LCPLL_810: | |
624 | link_clock = 81000; | |
625 | break; | |
626 | case PORT_CLK_SEL_LCPLL_1350: | |
627 | link_clock = 135000; | |
628 | break; | |
629 | case PORT_CLK_SEL_LCPLL_2700: | |
630 | link_clock = 270000; | |
631 | break; | |
632 | case PORT_CLK_SEL_WRPLL1: | |
633 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); | |
634 | break; | |
635 | case PORT_CLK_SEL_WRPLL2: | |
636 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); | |
637 | break; | |
638 | case PORT_CLK_SEL_SPLL: | |
639 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
640 | if (pll == SPLL_PLL_FREQ_810MHz) | |
641 | link_clock = 81000; | |
642 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
643 | link_clock = 135000; | |
644 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
645 | link_clock = 270000; | |
646 | else { | |
647 | WARN(1, "bad spll freq\n"); | |
648 | return; | |
649 | } | |
650 | break; | |
651 | default: | |
652 | WARN(1, "bad port clock sel\n"); | |
653 | return; | |
654 | } | |
655 | ||
656 | pipe_config->port_clock = link_clock * 2; | |
657 | ||
658 | if (pipe_config->has_pch_encoder) | |
659 | pipe_config->adjusted_mode.crtc_clock = | |
660 | intel_dotclock_calculate(pipe_config->port_clock, | |
661 | &pipe_config->fdi_m_n); | |
662 | else if (pipe_config->has_dp_encoder) | |
663 | pipe_config->adjusted_mode.crtc_clock = | |
664 | intel_dotclock_calculate(pipe_config->port_clock, | |
665 | &pipe_config->dp_m_n); | |
666 | else | |
667 | pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; | |
668 | } | |
669 | ||
1b13d190 FT |
670 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
671 | struct intel_crtc_config *pipe_config) | |
672 | { | |
673 | hsw_ddi_clock_get(encoder, pipe_config); | |
674 | } | |
675 | ||
5d0b1887 | 676 | static void |
1b13d190 FT |
677 | hsw_ddi_calculate_wrpll(int clock /* in Hz */, |
678 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
5d0b1887 FT |
679 | { |
680 | uint64_t freq2k; | |
681 | unsigned p, n2, r2; | |
682 | struct wrpll_rnp best = { 0, 0, 0 }; | |
683 | unsigned budget; | |
19df918d | 684 | |
5d0b1887 | 685 | freq2k = clock / 100; |
19df918d | 686 | |
5d0b1887 | 687 | budget = wrpll_get_budget_for_freq(clock); |
19df918d | 688 | |
5d0b1887 FT |
689 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely |
690 | * and directly pass the LC PLL to it. */ | |
691 | if (freq2k == 5400000) { | |
692 | *n2_out = 2; | |
693 | *p_out = 1; | |
694 | *r2_out = 2; | |
695 | return; | |
696 | } | |
697 | ||
698 | /* | |
699 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
700 | * the WR PLL. | |
701 | * | |
702 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
703 | * Injecting R2 = 2 * R gives: | |
704 | * REF_MAX * r2 > LC_FREQ * 2 and | |
705 | * REF_MIN * r2 < LC_FREQ * 2 | |
706 | * | |
707 | * Which means the desired boundaries for r2 are: | |
708 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
709 | * | |
710 | */ | |
711 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
712 | r2 <= LC_FREQ * 2 / REF_MIN; | |
713 | r2++) { | |
714 | ||
715 | /* | |
716 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
717 | * | |
718 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
719 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
720 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
721 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
722 | * | |
723 | * Which means the desired boundaries for n2 are: | |
724 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
725 | */ | |
726 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
727 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
728 | n2++) { | |
19df918d | 729 | |
5d0b1887 FT |
730 | for (p = P_MIN; p <= P_MAX; p += P_INC) |
731 | wrpll_update_rnp(freq2k, budget, | |
732 | r2, n2, p, &best); | |
733 | } | |
734 | } | |
735 | ||
736 | *n2_out = best.n2; | |
737 | *p_out = best.p; | |
738 | *r2_out = best.r2; | |
19df918d FT |
739 | } |
740 | ||
1b13d190 FT |
741 | static bool |
742 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, | |
743 | struct intel_encoder *intel_encoder, | |
744 | int clock) | |
19df918d | 745 | { |
1b13d190 | 746 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
24edb884 FT |
747 | struct intel_shared_dpll *pll; |
748 | uint32_t val; | |
5d0b1887 | 749 | unsigned p, n2, r2; |
19df918d | 750 | |
1b13d190 | 751 | hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
9edbd4a0 | 752 | |
24edb884 | 753 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
9edbd4a0 FT |
754 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
755 | WRPLL_DIVIDER_POST(p); | |
756 | ||
24edb884 | 757 | intel_crtc->config.dpll_hw_state.wrpll = val; |
19df918d | 758 | |
24edb884 FT |
759 | pll = intel_get_shared_dpll(intel_crtc); |
760 | if (pll == NULL) { | |
761 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
762 | pipe_name(intel_crtc->pipe)); | |
8e26cdf6 | 763 | return false; |
19df918d FT |
764 | } |
765 | ||
24edb884 | 766 | intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
19df918d FT |
767 | } |
768 | ||
19df918d FT |
769 | return true; |
770 | } | |
771 | ||
1b13d190 FT |
772 | |
773 | /* | |
774 | * Tries to find a *shared* PLL for the CRTC and store it in | |
775 | * intel_crtc->ddi_pll_sel. | |
776 | * | |
777 | * For private DPLLs, compute_config() should do the selection for us. This | |
778 | * function should be folded into compute_config() eventually. | |
779 | */ | |
780 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc) | |
781 | { | |
782 | struct drm_crtc *crtc = &intel_crtc->base; | |
783 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
784 | int clock = intel_crtc->config.port_clock; | |
785 | ||
786 | intel_put_shared_dpll(intel_crtc); | |
787 | ||
788 | return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock); | |
789 | } | |
790 | ||
19df918d FT |
791 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
792 | { | |
793 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
794 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
795 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
8e26cdf6 | 796 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
19df918d FT |
797 | int type = intel_encoder->type; |
798 | uint32_t temp; | |
799 | ||
800 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
801 | ||
802 | temp = TRANS_MSA_SYNC_CLK; | |
8e26cdf6 | 803 | switch (intel_crtc->config.pipe_bpp) { |
19df918d FT |
804 | case 18: |
805 | temp |= TRANS_MSA_6_BPC; | |
806 | break; | |
807 | case 24: | |
808 | temp |= TRANS_MSA_8_BPC; | |
809 | break; | |
810 | case 30: | |
811 | temp |= TRANS_MSA_10_BPC; | |
812 | break; | |
813 | case 36: | |
814 | temp |= TRANS_MSA_12_BPC; | |
815 | break; | |
816 | default: | |
8e26cdf6 | 817 | BUG(); |
19df918d FT |
818 | } |
819 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); | |
820 | } | |
821 | } | |
822 | ||
1b13d190 FT |
823 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
824 | { | |
825 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
826 | struct drm_device *dev = crtc->dev; | |
827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
828 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
829 | uint32_t temp; | |
830 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
831 | if (state == true) | |
832 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
833 | else | |
834 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
835 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
836 | } | |
837 | ||
8e26cdf6 | 838 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
19df918d FT |
839 | { |
840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
841 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
842 | struct drm_encoder *encoder = &intel_encoder->base; | |
9edbd4a0 FT |
843 | struct drm_device *dev = crtc->dev; |
844 | struct drm_i915_private *dev_priv = dev->dev_private; | |
19df918d | 845 | enum i915_pipe pipe = intel_crtc->pipe; |
8e26cdf6 | 846 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
19df918d FT |
847 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
848 | int type = intel_encoder->type; | |
849 | uint32_t temp; | |
850 | ||
851 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ | |
852 | temp = TRANS_DDI_FUNC_ENABLE; | |
853 | temp |= TRANS_DDI_SELECT_PORT(port); | |
854 | ||
8e26cdf6 | 855 | switch (intel_crtc->config.pipe_bpp) { |
19df918d FT |
856 | case 18: |
857 | temp |= TRANS_DDI_BPC_6; | |
858 | break; | |
859 | case 24: | |
860 | temp |= TRANS_DDI_BPC_8; | |
861 | break; | |
862 | case 30: | |
863 | temp |= TRANS_DDI_BPC_10; | |
864 | break; | |
865 | case 36: | |
866 | temp |= TRANS_DDI_BPC_12; | |
867 | break; | |
868 | default: | |
8e26cdf6 | 869 | BUG(); |
19df918d FT |
870 | } |
871 | ||
9edbd4a0 | 872 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
19df918d | 873 | temp |= TRANS_DDI_PVSYNC; |
9edbd4a0 | 874 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
19df918d FT |
875 | temp |= TRANS_DDI_PHSYNC; |
876 | ||
877 | if (cpu_transcoder == TRANSCODER_EDP) { | |
878 | switch (pipe) { | |
879 | case PIPE_A: | |
9edbd4a0 FT |
880 | /* On Haswell, can only use the always-on power well for |
881 | * eDP when not using the panel fitter, and when not | |
882 | * using motion blur mitigation (which we don't | |
883 | * support). */ | |
24edb884 FT |
884 | if (IS_HASWELL(dev) && |
885 | (intel_crtc->config.pch_pfit.enabled || | |
886 | intel_crtc->config.pch_pfit.force_thru)) | |
a2fdbec6 FT |
887 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
888 | else | |
889 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
19df918d FT |
890 | break; |
891 | case PIPE_B: | |
892 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
893 | break; | |
894 | case PIPE_C: | |
895 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
896 | break; | |
897 | default: | |
898 | BUG(); | |
899 | break; | |
900 | } | |
901 | } | |
902 | ||
903 | if (type == INTEL_OUTPUT_HDMI) { | |
ba55f2f5 | 904 | if (intel_crtc->config.has_hdmi_sink) |
19df918d FT |
905 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
906 | else | |
907 | temp |= TRANS_DDI_MODE_SELECT_DVI; | |
908 | ||
909 | } else if (type == INTEL_OUTPUT_ANALOG) { | |
910 | temp |= TRANS_DDI_MODE_SELECT_FDI; | |
5d0b1887 | 911 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
19df918d FT |
912 | |
913 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
914 | type == INTEL_OUTPUT_EDP) { | |
915 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
916 | ||
917 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
918 | ||
5d0b1887 | 919 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
19df918d | 920 | } else { |
5d0b1887 FT |
921 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
922 | intel_encoder->type, pipe_name(pipe)); | |
19df918d FT |
923 | } |
924 | ||
925 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
926 | } | |
927 | ||
928 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
929 | enum transcoder cpu_transcoder) | |
930 | { | |
931 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); | |
932 | uint32_t val = I915_READ(reg); | |
933 | ||
934 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); | |
935 | val |= TRANS_DDI_PORT_NONE; | |
936 | I915_WRITE(reg, val); | |
937 | } | |
938 | ||
939 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) | |
940 | { | |
941 | struct drm_device *dev = intel_connector->base.dev; | |
942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
943 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
944 | int type = intel_connector->base.connector_type; | |
945 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
946 | enum i915_pipe pipe = 0; | |
947 | enum transcoder cpu_transcoder; | |
ba55f2f5 | 948 | enum intel_display_power_domain power_domain; |
19df918d FT |
949 | uint32_t tmp; |
950 | ||
ba55f2f5 FT |
951 | power_domain = intel_display_port_power_domain(intel_encoder); |
952 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
953 | return false; | |
954 | ||
19df918d FT |
955 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
956 | return false; | |
957 | ||
958 | if (port == PORT_A) | |
959 | cpu_transcoder = TRANSCODER_EDP; | |
960 | else | |
a2fdbec6 | 961 | cpu_transcoder = (enum transcoder) pipe; |
19df918d FT |
962 | |
963 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
964 | ||
965 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
966 | case TRANS_DDI_MODE_SELECT_HDMI: | |
967 | case TRANS_DDI_MODE_SELECT_DVI: | |
968 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
969 | ||
970 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
971 | if (type == DRM_MODE_CONNECTOR_eDP) | |
972 | return true; | |
973 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
974 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
975 | ||
976 | case TRANS_DDI_MODE_SELECT_FDI: | |
977 | return (type == DRM_MODE_CONNECTOR_VGA); | |
978 | ||
979 | default: | |
980 | return false; | |
981 | } | |
982 | } | |
983 | ||
984 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, | |
985 | enum i915_pipe *pipe) | |
986 | { | |
987 | struct drm_device *dev = encoder->base.dev; | |
988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
989 | enum port port = intel_ddi_get_encoder_port(encoder); | |
ba55f2f5 | 990 | enum intel_display_power_domain power_domain; |
19df918d FT |
991 | u32 tmp; |
992 | int i; | |
993 | ||
ba55f2f5 FT |
994 | power_domain = intel_display_port_power_domain(encoder); |
995 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
996 | return false; | |
997 | ||
19df918d FT |
998 | tmp = I915_READ(DDI_BUF_CTL(port)); |
999 | ||
1000 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
1001 | return false; | |
1002 | ||
1003 | if (port == PORT_A) { | |
1004 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
1005 | ||
1006 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
1007 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1008 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1009 | *pipe = PIPE_A; | |
1010 | break; | |
1011 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1012 | *pipe = PIPE_B; | |
1013 | break; | |
1014 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1015 | *pipe = PIPE_C; | |
1016 | break; | |
1017 | } | |
1018 | ||
1019 | return true; | |
1020 | } else { | |
1021 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
1022 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1023 | ||
1024 | if ((tmp & TRANS_DDI_PORT_MASK) | |
1025 | == TRANS_DDI_SELECT_PORT(port)) { | |
1026 | *pipe = i; | |
1027 | return true; | |
1028 | } | |
1029 | } | |
1030 | } | |
1031 | ||
5d0b1887 | 1032 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
19df918d | 1033 | |
8e26cdf6 | 1034 | return false; |
19df918d FT |
1035 | } |
1036 | ||
19df918d FT |
1037 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1038 | { | |
1039 | struct drm_crtc *crtc = &intel_crtc->base; | |
1040 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1041 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1042 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
8e26cdf6 | 1043 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
19df918d FT |
1044 | |
1045 | if (cpu_transcoder != TRANSCODER_EDP) | |
1046 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1047 | TRANS_CLK_SEL_PORT(port)); | |
1048 | } | |
1049 | ||
1050 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1051 | { | |
1052 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
8e26cdf6 | 1053 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
19df918d FT |
1054 | |
1055 | if (cpu_transcoder != TRANSCODER_EDP) | |
1056 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1057 | TRANS_CLK_SEL_DISABLED); | |
1058 | } | |
1059 | ||
1060 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) | |
1061 | { | |
1062 | struct drm_encoder *encoder = &intel_encoder->base; | |
19df918d | 1063 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
ba55f2f5 | 1064 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
19df918d FT |
1065 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1066 | int type = intel_encoder->type; | |
1067 | ||
ba55f2f5 FT |
1068 | if (crtc->config.has_audio) { |
1069 | DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n", | |
1070 | pipe_name(crtc->pipe)); | |
1071 | ||
1072 | /* write eld */ | |
1073 | DRM_DEBUG_DRIVER("DDI audio: write eld information\n"); | |
1074 | intel_write_eld(encoder, &crtc->config.adjusted_mode); | |
1075 | } | |
1076 | ||
19df918d FT |
1077 | if (type == INTEL_OUTPUT_EDP) { |
1078 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
ba55f2f5 | 1079 | intel_edp_panel_on(intel_dp); |
19df918d FT |
1080 | } |
1081 | ||
24edb884 FT |
1082 | WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE); |
1083 | I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel); | |
19df918d FT |
1084 | |
1085 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
1086 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
ba55f2f5 | 1087 | |
1b13d190 | 1088 | intel_ddi_init_dp_buf_reg(intel_encoder); |
19df918d FT |
1089 | |
1090 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1091 | intel_dp_start_link_train(intel_dp); | |
1092 | intel_dp_complete_link_train(intel_dp); | |
8e26cdf6 FT |
1093 | if (port != PORT_A) |
1094 | intel_dp_stop_link_train(intel_dp); | |
ba55f2f5 FT |
1095 | } else if (type == INTEL_OUTPUT_HDMI) { |
1096 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1097 | ||
1098 | intel_hdmi->set_infoframes(encoder, | |
1099 | crtc->config.has_hdmi_sink, | |
1100 | &crtc->config.adjusted_mode); | |
19df918d FT |
1101 | } |
1102 | } | |
1103 | ||
1104 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) | |
1105 | { | |
1106 | struct drm_encoder *encoder = &intel_encoder->base; | |
1107 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1108 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1109 | int type = intel_encoder->type; | |
1110 | uint32_t val; | |
1111 | bool wait = false; | |
1112 | ||
1113 | val = I915_READ(DDI_BUF_CTL(port)); | |
1114 | if (val & DDI_BUF_CTL_ENABLE) { | |
1115 | val &= ~DDI_BUF_CTL_ENABLE; | |
1116 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1117 | wait = true; | |
1118 | } | |
1119 | ||
1120 | val = I915_READ(DP_TP_CTL(port)); | |
1121 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1122 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1123 | I915_WRITE(DP_TP_CTL(port), val); | |
1124 | ||
1125 | if (wait) | |
1126 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1127 | ||
9edbd4a0 | 1128 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
19df918d | 1129 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
9edbd4a0 | 1130 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
ba55f2f5 FT |
1131 | intel_edp_panel_vdd_on(intel_dp); |
1132 | intel_edp_panel_off(intel_dp); | |
19df918d FT |
1133 | } |
1134 | ||
1135 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); | |
1136 | } | |
1137 | ||
1138 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) | |
1139 | { | |
1140 | struct drm_encoder *encoder = &intel_encoder->base; | |
a2fdbec6 FT |
1141 | struct drm_crtc *crtc = encoder->crtc; |
1142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1143 | int pipe = intel_crtc->pipe; | |
19df918d FT |
1144 | struct drm_device *dev = encoder->dev; |
1145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1146 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1147 | int type = intel_encoder->type; | |
a2fdbec6 | 1148 | uint32_t tmp; |
19df918d FT |
1149 | |
1150 | if (type == INTEL_OUTPUT_HDMI) { | |
1151 | struct intel_digital_port *intel_dig_port = | |
1152 | enc_to_dig_port(encoder); | |
1153 | ||
1154 | /* In HDMI/DVI mode, the port width, and swing/emphasis values | |
1155 | * are ignored so nothing special needs to be done besides | |
1156 | * enabling the port. | |
1157 | */ | |
1158 | I915_WRITE(DDI_BUF_CTL(port), | |
5d0b1887 FT |
1159 | intel_dig_port->saved_port_bits | |
1160 | DDI_BUF_CTL_ENABLE); | |
19df918d FT |
1161 | } else if (type == INTEL_OUTPUT_EDP) { |
1162 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1163 | ||
8e26cdf6 FT |
1164 | if (port == PORT_A) |
1165 | intel_dp_stop_link_train(intel_dp); | |
1166 | ||
ba55f2f5 | 1167 | intel_edp_backlight_on(intel_dp); |
9edbd4a0 | 1168 | intel_edp_psr_enable(intel_dp); |
19df918d | 1169 | } |
a2fdbec6 | 1170 | |
ba55f2f5 FT |
1171 | if (intel_crtc->config.has_audio) { |
1172 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); | |
a2fdbec6 FT |
1173 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1174 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1175 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1176 | } | |
19df918d FT |
1177 | } |
1178 | ||
1179 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) | |
1180 | { | |
1181 | struct drm_encoder *encoder = &intel_encoder->base; | |
a2fdbec6 FT |
1182 | struct drm_crtc *crtc = encoder->crtc; |
1183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1184 | int pipe = intel_crtc->pipe; | |
19df918d | 1185 | int type = intel_encoder->type; |
a2fdbec6 FT |
1186 | struct drm_device *dev = encoder->dev; |
1187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1188 | uint32_t tmp; | |
19df918d | 1189 | |
ba55f2f5 FT |
1190 | /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this |
1191 | * register is part of the power well on Haswell. */ | |
1192 | if (intel_crtc->config.has_audio) { | |
5d0b1887 FT |
1193 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1194 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1195 | (pipe * 4)); | |
1196 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
ba55f2f5 | 1197 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
5d0b1887 | 1198 | } |
8e26cdf6 | 1199 | |
19df918d FT |
1200 | if (type == INTEL_OUTPUT_EDP) { |
1201 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1202 | ||
9edbd4a0 | 1203 | intel_edp_psr_disable(intel_dp); |
ba55f2f5 | 1204 | intel_edp_backlight_off(intel_dp); |
19df918d FT |
1205 | } |
1206 | } | |
1207 | ||
1b13d190 FT |
1208 | static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv) |
1209 | { | |
1210 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
1211 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
1212 | ||
1213 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
1214 | return 800000; | |
1215 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
1216 | return 450000; | |
1217 | else if (freq == LCPLL_CLK_FREQ_450) | |
1218 | return 450000; | |
1219 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
1220 | return 540000; | |
1221 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
1222 | return 337500; | |
1223 | else | |
1224 | return 675000; | |
1225 | } | |
1226 | ||
1227 | static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv) | |
19df918d | 1228 | { |
9edbd4a0 FT |
1229 | struct drm_device *dev = dev_priv->dev; |
1230 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
1231 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
1232 | ||
1b13d190 | 1233 | if (lcpll & LCPLL_CD_SOURCE_FCLK) |
9edbd4a0 | 1234 | return 800000; |
1b13d190 | 1235 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) |
5d0b1887 | 1236 | return 450000; |
1b13d190 | 1237 | else if (freq == LCPLL_CLK_FREQ_450) |
5d0b1887 | 1238 | return 450000; |
1b13d190 FT |
1239 | else if (IS_ULT(dev)) |
1240 | return 337500; | |
1241 | else | |
1242 | return 540000; | |
1243 | } | |
1244 | ||
1245 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) | |
1246 | { | |
1247 | struct drm_device *dev = dev_priv->dev; | |
1248 | ||
1249 | if (IS_BROADWELL(dev)) | |
1250 | return bdw_get_cdclk_freq(dev_priv); | |
1251 | ||
1252 | /* Haswell */ | |
1253 | return hsw_get_cdclk_freq(dev_priv); | |
19df918d FT |
1254 | } |
1255 | ||
24edb884 FT |
1256 | static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, |
1257 | struct intel_shared_dpll *pll) | |
1258 | { | |
1259 | I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll); | |
1260 | POSTING_READ(WRPLL_CTL(pll->id)); | |
1261 | udelay(20); | |
1262 | } | |
1263 | ||
1264 | static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, | |
1265 | struct intel_shared_dpll *pll) | |
1266 | { | |
1267 | uint32_t val; | |
1268 | ||
1269 | val = I915_READ(WRPLL_CTL(pll->id)); | |
1270 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); | |
1271 | POSTING_READ(WRPLL_CTL(pll->id)); | |
1272 | } | |
1273 | ||
1274 | static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, | |
1275 | struct intel_shared_dpll *pll, | |
1276 | struct intel_dpll_hw_state *hw_state) | |
1277 | { | |
1278 | uint32_t val; | |
1279 | ||
1280 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
1281 | return false; | |
1282 | ||
1283 | val = I915_READ(WRPLL_CTL(pll->id)); | |
1284 | hw_state->wrpll = val; | |
1285 | ||
1286 | return val & WRPLL_PLL_ENABLE; | |
1287 | } | |
1288 | ||
1289 | static const char * const hsw_ddi_pll_names[] = { | |
1290 | "WRPLL 1", | |
1291 | "WRPLL 2", | |
1292 | }; | |
1293 | ||
1b13d190 | 1294 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
19df918d | 1295 | { |
24edb884 FT |
1296 | int i; |
1297 | ||
1298 | dev_priv->num_shared_dpll = 2; | |
1299 | ||
1300 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
1301 | dev_priv->shared_dplls[i].id = i; | |
1302 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; | |
1303 | dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; | |
1304 | dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; | |
1305 | dev_priv->shared_dplls[i].get_hw_state = | |
1306 | hsw_ddi_pll_get_hw_state; | |
1307 | } | |
1b13d190 FT |
1308 | } |
1309 | ||
1310 | void intel_ddi_pll_init(struct drm_device *dev) | |
1311 | { | |
1312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1313 | uint32_t val = I915_READ(LCPLL_CTL); | |
1314 | ||
1315 | hsw_shared_dplls_init(dev_priv); | |
19df918d FT |
1316 | |
1317 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1318 | * just check its state and print errors in case something is wrong. | |
1319 | * Don't even try to turn it on. | |
1320 | */ | |
1321 | ||
5d0b1887 | 1322 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
19df918d FT |
1323 | intel_ddi_get_cdclk_freq(dev_priv)); |
1324 | ||
1325 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1326 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1327 | ||
1328 | if (val & LCPLL_PLL_DISABLE) | |
1329 | DRM_ERROR("LCPLL is disabled\n"); | |
1330 | } | |
1331 | ||
1332 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1333 | { | |
1334 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); | |
1335 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1336 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1337 | enum port port = intel_dig_port->port; | |
19df918d | 1338 | uint32_t val; |
a2fdbec6 | 1339 | bool wait = false; |
19df918d FT |
1340 | |
1341 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1342 | val = I915_READ(DDI_BUF_CTL(port)); | |
1343 | if (val & DDI_BUF_CTL_ENABLE) { | |
1344 | val &= ~DDI_BUF_CTL_ENABLE; | |
1345 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1346 | wait = true; | |
1347 | } | |
1348 | ||
1349 | val = I915_READ(DP_TP_CTL(port)); | |
1350 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1351 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1352 | I915_WRITE(DP_TP_CTL(port), val); | |
1353 | POSTING_READ(DP_TP_CTL(port)); | |
1354 | ||
1355 | if (wait) | |
1356 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1357 | } | |
1358 | ||
1359 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1360 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
9edbd4a0 | 1361 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
19df918d FT |
1362 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
1363 | I915_WRITE(DP_TP_CTL(port), val); | |
1364 | POSTING_READ(DP_TP_CTL(port)); | |
1365 | ||
1366 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1367 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1368 | POSTING_READ(DDI_BUF_CTL(port)); | |
1369 | ||
1370 | udelay(600); | |
1371 | } | |
1372 | ||
1373 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) | |
1374 | { | |
1375 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1376 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1377 | uint32_t val; | |
1378 | ||
1379 | intel_ddi_post_disable(intel_encoder); | |
1380 | ||
1381 | val = I915_READ(_FDI_RXA_CTL); | |
1382 | val &= ~FDI_RX_ENABLE; | |
1383 | I915_WRITE(_FDI_RXA_CTL, val); | |
1384 | ||
1385 | val = I915_READ(_FDI_RXA_MISC); | |
1386 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1387 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1388 | I915_WRITE(_FDI_RXA_MISC, val); | |
1389 | ||
1390 | val = I915_READ(_FDI_RXA_CTL); | |
1391 | val &= ~FDI_PCDCLK; | |
1392 | I915_WRITE(_FDI_RXA_CTL, val); | |
1393 | ||
1394 | val = I915_READ(_FDI_RXA_CTL); | |
1395 | val &= ~FDI_RX_PLL_ENABLE; | |
1396 | I915_WRITE(_FDI_RXA_CTL, val); | |
1397 | } | |
1398 | ||
1399 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) | |
1400 | { | |
1401 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
1402 | int type = intel_encoder->type; | |
1403 | ||
1404 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) | |
1405 | intel_dp_check_link_status(intel_dp); | |
1406 | } | |
1407 | ||
9edbd4a0 FT |
1408 | void intel_ddi_get_config(struct intel_encoder *encoder, |
1409 | struct intel_crtc_config *pipe_config) | |
5d0b1887 FT |
1410 | { |
1411 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1412 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1413 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1414 | u32 temp, flags = 0; | |
1415 | ||
1416 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1417 | if (temp & TRANS_DDI_PHSYNC) | |
1418 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1419 | else | |
1420 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1421 | if (temp & TRANS_DDI_PVSYNC) | |
1422 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1423 | else | |
1424 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1425 | ||
1426 | pipe_config->adjusted_mode.flags |= flags; | |
9edbd4a0 FT |
1427 | |
1428 | switch (temp & TRANS_DDI_BPC_MASK) { | |
1429 | case TRANS_DDI_BPC_6: | |
1430 | pipe_config->pipe_bpp = 18; | |
1431 | break; | |
1432 | case TRANS_DDI_BPC_8: | |
1433 | pipe_config->pipe_bpp = 24; | |
1434 | break; | |
1435 | case TRANS_DDI_BPC_10: | |
1436 | pipe_config->pipe_bpp = 30; | |
1437 | break; | |
1438 | case TRANS_DDI_BPC_12: | |
1439 | pipe_config->pipe_bpp = 36; | |
1440 | break; | |
1441 | default: | |
1442 | break; | |
1443 | } | |
1444 | ||
1445 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
1446 | case TRANS_DDI_MODE_SELECT_HDMI: | |
ba55f2f5 | 1447 | pipe_config->has_hdmi_sink = true; |
9edbd4a0 FT |
1448 | case TRANS_DDI_MODE_SELECT_DVI: |
1449 | case TRANS_DDI_MODE_SELECT_FDI: | |
1450 | break; | |
1451 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1452 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1453 | pipe_config->has_dp_encoder = true; | |
1454 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
1455 | break; | |
1456 | default: | |
1457 | break; | |
1458 | } | |
1459 | ||
ba55f2f5 FT |
1460 | if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
1461 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1462 | if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4))) | |
1463 | pipe_config->has_audio = true; | |
1464 | } | |
1465 | ||
9edbd4a0 FT |
1466 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
1467 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1468 | /* | |
1469 | * This is a big fat ugly hack. | |
1470 | * | |
1471 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1472 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1473 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1474 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1475 | * max, not what it tells us to use. | |
1476 | * | |
1477 | * Note: This will still be broken if the eDP panel is not lit | |
1478 | * up by the BIOS, and thus we can't get the mode at module | |
1479 | * load. | |
1480 | */ | |
1481 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1482 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1483 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1484 | } | |
ba55f2f5 | 1485 | |
1b13d190 | 1486 | hsw_ddi_clock_get(encoder, pipe_config); |
5d0b1887 FT |
1487 | } |
1488 | ||
19df918d FT |
1489 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1490 | { | |
1491 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1492 | intel_dp_encoder_destroy(encoder); | |
1493 | } | |
1494 | ||
8e26cdf6 FT |
1495 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1496 | struct intel_crtc_config *pipe_config) | |
19df918d | 1497 | { |
8e26cdf6 | 1498 | int type = encoder->type; |
5d0b1887 | 1499 | int port = intel_ddi_get_encoder_port(encoder); |
19df918d | 1500 | |
8e26cdf6 | 1501 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
19df918d | 1502 | |
5d0b1887 FT |
1503 | if (port == PORT_A) |
1504 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1505 | ||
19df918d | 1506 | if (type == INTEL_OUTPUT_HDMI) |
8e26cdf6 | 1507 | return intel_hdmi_compute_config(encoder, pipe_config); |
19df918d | 1508 | else |
8e26cdf6 | 1509 | return intel_dp_compute_config(encoder, pipe_config); |
19df918d FT |
1510 | } |
1511 | ||
1512 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1513 | .destroy = intel_ddi_destroy, | |
1514 | }; | |
1515 | ||
9edbd4a0 FT |
1516 | static struct intel_connector * |
1517 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
1518 | { | |
1519 | struct intel_connector *connector; | |
1520 | enum port port = intel_dig_port->port; | |
1521 | ||
1522 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1523 | if (!connector) | |
1524 | return NULL; | |
1525 | ||
1526 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
1527 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
1528 | kfree(connector); | |
1529 | return NULL; | |
1530 | } | |
1531 | ||
1532 | return connector; | |
1533 | } | |
1534 | ||
1535 | static struct intel_connector * | |
1536 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
1537 | { | |
1538 | struct intel_connector *connector; | |
1539 | enum port port = intel_dig_port->port; | |
1540 | ||
1541 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1542 | if (!connector) | |
1543 | return NULL; | |
1544 | ||
1545 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1546 | intel_hdmi_init_connector(intel_dig_port, connector); | |
1547 | ||
1548 | return connector; | |
1549 | } | |
19df918d FT |
1550 | |
1551 | void intel_ddi_init(struct drm_device *dev, enum port port) | |
1552 | { | |
1553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1554 | struct intel_digital_port *intel_dig_port; | |
1555 | struct intel_encoder *intel_encoder; | |
1556 | struct drm_encoder *encoder; | |
9edbd4a0 FT |
1557 | bool init_hdmi, init_dp; |
1558 | ||
1559 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
1560 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
1561 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
1562 | if (!init_dp && !init_hdmi) { | |
24edb884 | 1563 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", |
9edbd4a0 FT |
1564 | port_name(port)); |
1565 | init_hdmi = true; | |
1566 | init_dp = true; | |
1567 | } | |
19df918d | 1568 | |
9edbd4a0 | 1569 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
19df918d FT |
1570 | if (!intel_dig_port) |
1571 | return; | |
1572 | ||
19df918d FT |
1573 | intel_encoder = &intel_dig_port->base; |
1574 | encoder = &intel_encoder->base; | |
1575 | ||
1576 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1577 | DRM_MODE_ENCODER_TMDS); | |
19df918d | 1578 | |
8e26cdf6 | 1579 | intel_encoder->compute_config = intel_ddi_compute_config; |
19df918d FT |
1580 | intel_encoder->enable = intel_enable_ddi; |
1581 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1582 | intel_encoder->disable = intel_disable_ddi; | |
1583 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1584 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
5d0b1887 | 1585 | intel_encoder->get_config = intel_ddi_get_config; |
19df918d FT |
1586 | |
1587 | intel_dig_port->port = port; | |
5d0b1887 FT |
1588 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1589 | (DDI_BUF_PORT_REVERSAL | | |
1590 | DDI_A_4_LANES); | |
19df918d FT |
1591 | |
1592 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
24edb884 | 1593 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
ba55f2f5 | 1594 | intel_encoder->cloneable = 0; |
19df918d FT |
1595 | intel_encoder->hot_plug = intel_ddi_hot_plug; |
1596 | ||
24edb884 FT |
1597 | if (init_dp) { |
1598 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
1599 | goto err; | |
1600 | ||
1601 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; | |
1602 | dev_priv->hpd_irq_port[port] = intel_dig_port; | |
1603 | } | |
5d0b1887 | 1604 | |
9edbd4a0 FT |
1605 | /* In theory we don't need the encoder->type check, but leave it just in |
1606 | * case we have some really bad VBTs... */ | |
24edb884 FT |
1607 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
1608 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
1609 | goto err; | |
5d0b1887 | 1610 | } |
24edb884 FT |
1611 | |
1612 | return; | |
1613 | ||
1614 | err: | |
1615 | drm_encoder_cleanup(encoder); | |
1616 | kfree(intel_dig_port); | |
19df918d | 1617 | } |