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| 32 | .tr \(*W- |
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| 37 | . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch |
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| 56 | .\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index |
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| 58 | .\" output yourself in some meaningful fashion. |
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| 60 | . de IX |
| 61 | . tm Index:\\$1\t\\n%\t"\\$2" |
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| 102 | . ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' |
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| 110 | .ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' |
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| 120 | \{\ |
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| 130 | .\} |
| 131 | .rm #[ #] #H #V #F C |
| 132 | .\" ======================================================================== |
| 133 | .\" |
| 134 | .IX Title "GCC 1" |
| 135 | .TH GCC 1 "2014-06-12" "gcc-4.7.4" "GNU" |
| 136 | .\" For nroff, turn off justification. Always turn off hyphenation; it makes |
| 137 | .\" way too many mistakes in technical documents. |
| 138 | .if n .ad l |
| 139 | .nh |
| 140 | .SH "NAME" |
| 141 | gcc \- GNU project C and C++ compiler |
| 142 | .SH "SYNOPSIS" |
| 143 | .IX Header "SYNOPSIS" |
| 144 | gcc [\fB\-c\fR|\fB\-S\fR|\fB\-E\fR] [\fB\-std=\fR\fIstandard\fR] |
| 145 | [\fB\-g\fR] [\fB\-pg\fR] [\fB\-O\fR\fIlevel\fR] |
| 146 | [\fB\-W\fR\fIwarn\fR...] [\fB\-pedantic\fR] |
| 147 | [\fB\-I\fR\fIdir\fR...] [\fB\-L\fR\fIdir\fR...] |
| 148 | [\fB\-D\fR\fImacro\fR[=\fIdefn\fR]...] [\fB\-U\fR\fImacro\fR] |
| 149 | [\fB\-f\fR\fIoption\fR...] [\fB\-m\fR\fImachine-option\fR...] |
| 150 | [\fB\-o\fR \fIoutfile\fR] [@\fIfile\fR] \fIinfile\fR... |
| 151 | .PP |
| 152 | Only the most useful options are listed here; see below for the |
| 153 | remainder. \fBg++\fR accepts mostly the same options as \fBgcc\fR. |
| 154 | .SH "DESCRIPTION" |
| 155 | .IX Header "DESCRIPTION" |
| 156 | When you invoke \s-1GCC\s0, it normally does preprocessing, compilation, |
| 157 | assembly and linking. The \*(L"overall options\*(R" allow you to stop this |
| 158 | process at an intermediate stage. For example, the \fB\-c\fR option |
| 159 | says not to run the linker. Then the output consists of object files |
| 160 | output by the assembler. |
| 161 | .PP |
| 162 | Other options are passed on to one stage of processing. Some options |
| 163 | control the preprocessor and others the compiler itself. Yet other |
| 164 | options control the assembler and linker; most of these are not |
| 165 | documented here, since you rarely need to use any of them. |
| 166 | .PP |
| 167 | Most of the command-line options that you can use with \s-1GCC\s0 are useful |
| 168 | for C programs; when an option is only useful with another language |
| 169 | (usually \*(C+), the explanation says so explicitly. If the description |
| 170 | for a particular option does not mention a source language, you can use |
| 171 | that option with all supported languages. |
| 172 | .PP |
| 173 | The \fBgcc\fR program accepts options and file names as operands. Many |
| 174 | options have multi-letter names; therefore multiple single-letter options |
| 175 | may \fInot\fR be grouped: \fB\-dv\fR is very different from \fB\-d\ \-v\fR. |
| 176 | .PP |
| 177 | You can mix options and other arguments. For the most part, the order |
| 178 | you use doesn't matter. Order does matter when you use several |
| 179 | options of the same kind; for example, if you specify \fB\-L\fR more |
| 180 | than once, the directories are searched in the order specified. Also, |
| 181 | the placement of the \fB\-l\fR option is significant. |
| 182 | .PP |
| 183 | Many options have long names starting with \fB\-f\fR or with |
| 184 | \&\fB\-W\fR\-\-\-for example, |
| 185 | \&\fB\-fmove\-loop\-invariants\fR, \fB\-Wformat\fR and so on. Most of |
| 186 | these have both positive and negative forms; the negative form of |
| 187 | \&\fB\-ffoo\fR would be \fB\-fno\-foo\fR. This manual documents |
| 188 | only one of these two forms, whichever one is not the default. |
| 189 | .SH "OPTIONS" |
| 190 | .IX Header "OPTIONS" |
| 191 | .Sh "Option Summary" |
| 192 | .IX Subsection "Option Summary" |
| 193 | Here is a summary of all the options, grouped by type. Explanations are |
| 194 | in the following sections. |
| 195 | .IP "\fIOverall Options\fR" 4 |
| 196 | .IX Item "Overall Options" |
| 197 | \&\fB\-c \-S \-E \-o\fR \fIfile\fR \fB\-no\-canonical\-prefixes |
| 198 | \&\-pipe \-pass\-exit\-codes |
| 199 | \&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help |
| 200 | \&\-\-version \-wrapper @\fR\fIfile\fR \fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR |
| 201 | \&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fdump\-go\-spec=\fR\fIfile\fR |
| 202 | .IP "\fIC Language Options\fR" 4 |
| 203 | .IX Item "C Language Options" |
| 204 | \&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline |
| 205 | \&\-aux\-info\fR \fIfilename\fR \fB\-fallow\-parameterless\-variadic\-functions |
| 206 | \&\-fno\-asm \-fno\-builtin \-fno\-builtin\-\fR\fIfunction\fR |
| 207 | \&\fB\-fhosted \-ffreestanding \-fopenmp \-fms\-extensions \-fplan9\-extensions |
| 208 | \&\-trigraphs \-no\-integrated\-cpp \-traditional \-traditional\-cpp |
| 209 | \&\-fallow\-single\-precision \-fcond\-mismatch \-flax\-vector\-conversions |
| 210 | \&\-fsigned\-bitfields \-fsigned\-char |
| 211 | \&\-funsigned\-bitfields \-funsigned\-char\fR |
| 212 | .IP "\fI\*(C+ Language Options\fR" 4 |
| 213 | .IX Item " Language Options" |
| 214 | \&\fB\-fabi\-version=\fR\fIn\fR \fB\-fno\-access\-control \-fcheck\-new |
| 215 | \&\-fconserve\-space \-fconstexpr\-depth=\fR\fIn\fR \fB\-ffriend\-injection |
| 216 | \&\-fno\-elide\-constructors |
| 217 | \&\-fno\-enforce\-eh\-specs |
| 218 | \&\-ffor\-scope \-fno\-for\-scope \-fno\-gnu\-keywords |
| 219 | \&\-fno\-implicit\-templates |
| 220 | \&\-fno\-implicit\-inline\-templates |
| 221 | \&\-fno\-implement\-inlines \-fms\-extensions |
| 222 | \&\-fno\-nonansi\-builtins \-fnothrow\-opt \-fno\-operator\-names |
| 223 | \&\-fno\-optional\-diags \-fpermissive |
| 224 | \&\-fno\-pretty\-templates |
| 225 | \&\-frepo \-fno\-rtti \-fstats \-ftemplate\-depth=\fR\fIn\fR |
| 226 | \&\fB\-fno\-threadsafe\-statics \-fuse\-cxa\-atexit \-fno\-weak \-nostdinc++ |
| 227 | \&\-fno\-default\-inline \-fvisibility\-inlines\-hidden |
| 228 | \&\-fvisibility\-ms\-compat |
| 229 | \&\-Wabi \-Wconversion\-null \-Wctor\-dtor\-privacy |
| 230 | \&\-Wdelete\-non\-virtual\-dtor \-Wnarrowing \-Wnoexcept |
| 231 | \&\-Wnon\-virtual\-dtor \-Wreorder |
| 232 | \&\-Weffc++ \-Wstrict\-null\-sentinel |
| 233 | \&\-Wno\-non\-template\-friend \-Wold\-style\-cast |
| 234 | \&\-Woverloaded\-virtual \-Wno\-pmf\-conversions |
| 235 | \&\-Wsign\-promo\fR |
| 236 | .IP "\fIObjective-C and Objective\-\*(C+ Language Options\fR" 4 |
| 237 | .IX Item "Objective-C and Objective- Language Options" |
| 238 | \&\fB\-fconstant\-string\-class=\fR\fIclass-name\fR |
| 239 | \&\fB\-fgnu\-runtime \-fnext\-runtime |
| 240 | \&\-fno\-nil\-receivers |
| 241 | \&\-fobjc\-abi\-version=\fR\fIn\fR |
| 242 | \&\fB\-fobjc\-call\-cxx\-cdtors |
| 243 | \&\-fobjc\-direct\-dispatch |
| 244 | \&\-fobjc\-exceptions |
| 245 | \&\-fobjc\-gc |
| 246 | \&\-fobjc\-nilcheck |
| 247 | \&\-fobjc\-std=objc1 |
| 248 | \&\-freplace\-objc\-classes |
| 249 | \&\-fzero\-link |
| 250 | \&\-gen\-decls |
| 251 | \&\-Wassign\-intercept |
| 252 | \&\-Wno\-protocol \-Wselector |
| 253 | \&\-Wstrict\-selector\-match |
| 254 | \&\-Wundeclared\-selector\fR |
| 255 | .IP "\fILanguage Independent Options\fR" 4 |
| 256 | .IX Item "Language Independent Options" |
| 257 | \&\fB\-fmessage\-length=\fR\fIn\fR |
| 258 | \&\fB\-fdiagnostics\-show\-location=\fR[\fBonce\fR|\fBevery-line\fR] |
| 259 | \&\fB\-fno\-diagnostics\-show\-option\fR |
| 260 | .IP "\fIWarning Options\fR" 4 |
| 261 | .IX Item "Warning Options" |
| 262 | \&\fB\-fsyntax\-only \-fmax\-errors=\fR\fIn\fR \fB\-pedantic |
| 263 | \&\-pedantic\-errors |
| 264 | \&\-w \-Wextra \-Wall \-Waddress \-Waggregate\-return \-Warray\-bounds |
| 265 | \&\-Wno\-attributes \-Wno\-builtin\-macro\-redefined |
| 266 | \&\-Wc++\-compat \-Wc++11\-compat \-Wcast\-align \-Wcast\-qual |
| 267 | \&\-Wchar\-subscripts \-Wclobbered \-Wcomment |
| 268 | \&\-Wconversion \-Wcoverage\-mismatch \-Wno\-cpp \-Wno\-deprecated |
| 269 | \&\-Wno\-deprecated\-declarations \-Wdisabled\-optimization |
| 270 | \&\-Wno\-div\-by\-zero \-Wdouble\-promotion \-Wempty\-body \-Wenum\-compare |
| 271 | \&\-Wno\-endif\-labels \-Werror \-Werror=* |
| 272 | \&\-Wfatal\-errors \-Wfloat\-equal \-Wformat \-Wformat=2 |
| 273 | \&\-Wno\-format\-contains\-nul \-Wno\-format\-extra\-args \-Wformat\-nonliteral |
| 274 | \&\-Wformat\-security \-Wformat\-y2k |
| 275 | \&\-Wframe\-larger\-than=\fR\fIlen\fR \fB\-Wno\-free\-nonheap\-object \-Wjump\-misses\-init |
| 276 | \&\-Wignored\-qualifiers |
| 277 | \&\-Wimplicit \-Wimplicit\-function\-declaration \-Wimplicit\-int |
| 278 | \&\-Winit\-self \-Winline \-Wmaybe\-uninitialized |
| 279 | \&\-Wno\-int\-to\-pointer\-cast \-Wno\-invalid\-offsetof |
| 280 | \&\-Winvalid\-pch \-Wlarger\-than=\fR\fIlen\fR \fB\-Wunsafe\-loop\-optimizations |
| 281 | \&\-Wlogical\-op \-Wlong\-long |
| 282 | \&\-Wmain \-Wmaybe\-uninitialized \-Wmissing\-braces \-Wmissing\-field\-initializers |
| 283 | \&\-Wmissing\-format\-attribute \-Wmissing\-include\-dirs |
| 284 | \&\-Wno\-mudflap |
| 285 | \&\-Wno\-multichar \-Wnonnull \-Wno\-overflow |
| 286 | \&\-Woverlength\-strings \-Wpacked \-Wpacked\-bitfield\-compat \-Wpadded |
| 287 | \&\-Wparentheses \-Wpedantic\-ms\-format \-Wno\-pedantic\-ms\-format |
| 288 | \&\-Wpointer\-arith \-Wno\-pointer\-to\-int\-cast |
| 289 | \&\-Wredundant\-decls |
| 290 | \&\-Wreturn\-type \-Wsequence\-point \-Wshadow |
| 291 | \&\-Wsign\-compare \-Wsign\-conversion \-Wstack\-protector |
| 292 | \&\-Wstack\-usage=\fR\fIlen\fR \fB\-Wstrict\-aliasing \-Wstrict\-aliasing=n |
| 293 | \&\-Wstrict\-overflow \-Wstrict\-overflow=\fR\fIn\fR |
| 294 | \&\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR] |
| 295 | \&\fB\-Wswitch \-Wswitch\-default \-Wswitch\-enum \-Wsync\-nand |
| 296 | \&\-Wsystem\-headers \-Wtrampolines \-Wtrigraphs \-Wtype\-limits \-Wundef |
| 297 | \&\-Wuninitialized \-Wunknown\-pragmas \-Wno\-pragmas |
| 298 | \&\-Wunsuffixed\-float\-constants \-Wunused \-Wunused\-function |
| 299 | \&\-Wunused\-label \-Wunused\-local\-typedefs \-Wunused\-parameter |
| 300 | \&\-Wno\-unused\-result \-Wunused\-value \-Wunused\-variable |
| 301 | \&\-Wunused\-but\-set\-parameter \-Wunused\-but\-set\-variable |
| 302 | \&\-Wvariadic\-macros \-Wvector\-operation\-performance \-Wvla |
| 303 | \&\-Wvolatile\-register\-var \-Wwrite\-strings \-Wzero\-as\-null\-pointer\-constant\fR |
| 304 | .IP "\fIC and Objective-C-only Warning Options\fR" 4 |
| 305 | .IX Item "C and Objective-C-only Warning Options" |
| 306 | \&\fB\-Wbad\-function\-cast \-Wmissing\-declarations |
| 307 | \&\-Wmissing\-parameter\-type \-Wmissing\-prototypes \-Wnested\-externs |
| 308 | \&\-Wold\-style\-declaration \-Wold\-style\-definition |
| 309 | \&\-Wstrict\-prototypes \-Wtraditional \-Wtraditional\-conversion |
| 310 | \&\-Wdeclaration\-after\-statement \-Wpointer\-sign\fR |
| 311 | .IP "\fIDebugging Options\fR" 4 |
| 312 | .IX Item "Debugging Options" |
| 313 | \&\fB\-d\fR\fIletters\fR \fB\-dumpspecs \-dumpmachine \-dumpversion |
| 314 | \&\-fdbg\-cnt\-list \-fdbg\-cnt=\fR\fIcounter-value-list\fR |
| 315 | \&\fB\-fdisable\-ipa\-\fR\fIpass_name\fR |
| 316 | \&\fB\-fdisable\-rtl\-\fR\fIpass_name\fR |
| 317 | \&\fB\-fdisable\-rtl\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR |
| 318 | \&\fB\-fdisable\-tree\-\fR\fIpass_name\fR |
| 319 | \&\fB\-fdisable\-tree\-\fR\fIpass-name\fR\fB=\fR\fIrange-list\fR |
| 320 | \&\fB\-fdump\-noaddr \-fdump\-unnumbered \-fdump\-unnumbered\-links |
| 321 | \&\-fdump\-translation\-unit\fR[\fB\-\fR\fIn\fR] |
| 322 | \&\fB\-fdump\-class\-hierarchy\fR[\fB\-\fR\fIn\fR] |
| 323 | \&\fB\-fdump\-ipa\-all \-fdump\-ipa\-cgraph \-fdump\-ipa\-inline |
| 324 | \&\-fdump\-passes |
| 325 | \&\-fdump\-statistics |
| 326 | \&\-fdump\-tree\-all |
| 327 | \&\-fdump\-tree\-original\fR[\fB\-\fR\fIn\fR] |
| 328 | \&\fB\-fdump\-tree\-optimized\fR[\fB\-\fR\fIn\fR] |
| 329 | \&\fB\-fdump\-tree\-cfg \-fdump\-tree\-vcg \-fdump\-tree\-alias |
| 330 | \&\-fdump\-tree\-ch |
| 331 | \&\-fdump\-tree\-ssa\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-pre\fR[\fB\-\fR\fIn\fR] |
| 332 | \&\fB\-fdump\-tree\-ccp\fR[\fB\-\fR\fIn\fR] \fB\-fdump\-tree\-dce\fR[\fB\-\fR\fIn\fR] |
| 333 | \&\fB\-fdump\-tree\-gimple\fR[\fB\-raw\fR] \fB\-fdump\-tree\-mudflap\fR[\fB\-\fR\fIn\fR] |
| 334 | \&\fB\-fdump\-tree\-dom\fR[\fB\-\fR\fIn\fR] |
| 335 | \&\fB\-fdump\-tree\-dse\fR[\fB\-\fR\fIn\fR] |
| 336 | \&\fB\-fdump\-tree\-phiprop\fR[\fB\-\fR\fIn\fR] |
| 337 | \&\fB\-fdump\-tree\-phiopt\fR[\fB\-\fR\fIn\fR] |
| 338 | \&\fB\-fdump\-tree\-forwprop\fR[\fB\-\fR\fIn\fR] |
| 339 | \&\fB\-fdump\-tree\-copyrename\fR[\fB\-\fR\fIn\fR] |
| 340 | \&\fB\-fdump\-tree\-nrv \-fdump\-tree\-vect |
| 341 | \&\-fdump\-tree\-sink |
| 342 | \&\-fdump\-tree\-sra\fR[\fB\-\fR\fIn\fR] |
| 343 | \&\fB\-fdump\-tree\-forwprop\fR[\fB\-\fR\fIn\fR] |
| 344 | \&\fB\-fdump\-tree\-fre\fR[\fB\-\fR\fIn\fR] |
| 345 | \&\fB\-fdump\-tree\-vrp\fR[\fB\-\fR\fIn\fR] |
| 346 | \&\fB\-ftree\-vectorizer\-verbose=\fR\fIn\fR |
| 347 | \&\fB\-fdump\-tree\-storeccp\fR[\fB\-\fR\fIn\fR] |
| 348 | \&\fB\-fdump\-final\-insns=\fR\fIfile\fR |
| 349 | \&\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR] \fB\-fcompare\-debug\-second |
| 350 | \&\-feliminate\-dwarf2\-dups \-feliminate\-unused\-debug\-types |
| 351 | \&\-feliminate\-unused\-debug\-symbols \-femit\-class\-debug\-always |
| 352 | \&\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR |
| 353 | \&\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR |
| 354 | \&\fB\-fdebug\-types\-section |
| 355 | \&\-fmem\-report \-fpre\-ipa\-mem\-report \-fpost\-ipa\-mem\-report \-fprofile\-arcs |
| 356 | \&\-frandom\-seed=\fR\fIstring\fR \fB\-fsched\-verbose=\fR\fIn\fR |
| 357 | \&\fB\-fsel\-sched\-verbose \-fsel\-sched\-dump\-cfg \-fsel\-sched\-pipelining\-verbose |
| 358 | \&\-fstack\-usage \-ftest\-coverage \-ftime\-report \-fvar\-tracking |
| 359 | \&\-fvar\-tracking\-assignments \-fvar\-tracking\-assignments\-toggle |
| 360 | \&\-g \-g\fR\fIlevel\fR \fB\-gtoggle \-gcoff \-gdwarf\-\fR\fIversion\fR |
| 361 | \&\fB\-ggdb \-grecord\-gcc\-switches \-gno\-record\-gcc\-switches |
| 362 | \&\-gstabs \-gstabs+ \-gstrict\-dwarf \-gno\-strict\-dwarf |
| 363 | \&\-gvms \-gxcoff \-gxcoff+ |
| 364 | \&\-fno\-merge\-debug\-strings \-fno\-dwarf2\-cfi\-asm |
| 365 | \&\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR |
| 366 | \&\fB\-femit\-struct\-debug\-baseonly \-femit\-struct\-debug\-reduced |
| 367 | \&\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR] |
| 368 | \&\fB\-p \-pg \-print\-file\-name=\fR\fIlibrary\fR \fB\-print\-libgcc\-file\-name |
| 369 | \&\-print\-multi\-directory \-print\-multi\-lib \-print\-multi\-os\-directory |
| 370 | \&\-print\-prog\-name=\fR\fIprogram\fR \fB\-print\-search\-dirs \-Q |
| 371 | \&\-print\-sysroot \-print\-sysroot\-headers\-suffix |
| 372 | \&\-save\-temps \-save\-temps=cwd \-save\-temps=obj \-time\fR[\fB=\fR\fIfile\fR] |
| 373 | .IP "\fIOptimization Options\fR" 4 |
| 374 | .IX Item "Optimization Options" |
| 375 | \&\fB\-falign\-functions[=\fR\fIn\fR\fB] \-falign\-jumps[=\fR\fIn\fR\fB] |
| 376 | \&\-falign\-labels[=\fR\fIn\fR\fB] \-falign\-loops[=\fR\fIn\fR\fB] \-fassociative\-math |
| 377 | \&\-fauto\-inc\-dec \-fbranch\-probabilities \-fbranch\-target\-load\-optimize |
| 378 | \&\-fbranch\-target\-load\-optimize2 \-fbtr\-bb\-exclusive \-fcaller\-saves |
| 379 | \&\-fcheck\-data\-deps \-fcombine\-stack\-adjustments \-fconserve\-stack |
| 380 | \&\-fcompare\-elim \-fcprop\-registers \-fcrossjumping |
| 381 | \&\-fcse\-follow\-jumps \-fcse\-skip\-blocks \-fcx\-fortran\-rules |
| 382 | \&\-fcx\-limited\-range |
| 383 | \&\-fdata\-sections \-fdce \-fdelayed\-branch |
| 384 | \&\-fdelete\-null\-pointer\-checks \-fdevirtualize \-fdse |
| 385 | \&\-fearly\-inlining \-fipa\-sra \-fexpensive\-optimizations \-ffat\-lto\-objects |
| 386 | \&\-ffast\-math \-ffinite\-math\-only \-ffloat\-store \-fexcess\-precision=\fR\fIstyle\fR |
| 387 | \&\fB\-fforward\-propagate \-ffp\-contract=\fR\fIstyle\fR \fB\-ffunction\-sections |
| 388 | \&\-fgcse \-fgcse\-after\-reload \-fgcse\-las \-fgcse\-lm \-fgraphite\-identity |
| 389 | \&\-fgcse\-sm \-fif\-conversion \-fif\-conversion2 \-findirect\-inlining |
| 390 | \&\-finline\-functions \-finline\-functions\-called\-once \-finline\-limit=\fR\fIn\fR |
| 391 | \&\fB\-finline\-small\-functions \-fipa\-cp \-fipa\-cp\-clone \-fipa\-matrix\-reorg |
| 392 | \&\-fipa\-pta \-fipa\-profile \-fipa\-pure\-const \-fipa\-reference |
| 393 | \&\-fira\-algorithm=\fR\fIalgorithm\fR |
| 394 | \&\fB\-fira\-region=\fR\fIregion\fR |
| 395 | \&\fB\-fira\-loop\-pressure \-fno\-ira\-share\-save\-slots |
| 396 | \&\-fno\-ira\-share\-spill\-slots \-fira\-verbose=\fR\fIn\fR |
| 397 | \&\fB\-fivopts \-fkeep\-inline\-functions \-fkeep\-static\-consts |
| 398 | \&\-floop\-block \-floop\-flatten \-floop\-interchange \-floop\-strip\-mine |
| 399 | \&\-floop\-parallelize\-all \-flto \-flto\-compression\-level |
| 400 | \&\-flto\-partition=\fR\fIalg\fR \fB\-flto\-report \-fmerge\-all\-constants |
| 401 | \&\-fmerge\-constants \-fmodulo\-sched \-fmodulo\-sched\-allow\-regmoves |
| 402 | \&\-fmove\-loop\-invariants fmudflap \-fmudflapir \-fmudflapth \-fno\-branch\-count\-reg |
| 403 | \&\-fno\-default\-inline |
| 404 | \&\-fno\-defer\-pop \-fno\-function\-cse \-fno\-guess\-branch\-probability |
| 405 | \&\-fno\-inline \-fno\-math\-errno \-fno\-peephole \-fno\-peephole2 |
| 406 | \&\-fno\-sched\-interblock \-fno\-sched\-spec \-fno\-signed\-zeros |
| 407 | \&\-fno\-toplevel\-reorder \-fno\-trapping\-math \-fno\-zero\-initialized\-in\-bss |
| 408 | \&\-fomit\-frame\-pointer \-foptimize\-register\-move \-foptimize\-sibling\-calls |
| 409 | \&\-fpartial\-inlining \-fpeel\-loops \-fpredictive\-commoning |
| 410 | \&\-fprefetch\-loop\-arrays |
| 411 | \&\-fprofile\-correction \-fprofile\-dir=\fR\fIpath\fR \fB\-fprofile\-generate |
| 412 | \&\-fprofile\-generate=\fR\fIpath\fR |
| 413 | \&\fB\-fprofile\-use \-fprofile\-use=\fR\fIpath\fR \fB\-fprofile\-values |
| 414 | \&\-freciprocal\-math \-free \-fregmove \-frename\-registers \-freorder\-blocks |
| 415 | \&\-freorder\-blocks\-and\-partition \-freorder\-functions |
| 416 | \&\-frerun\-cse\-after\-loop \-freschedule\-modulo\-scheduled\-loops |
| 417 | \&\-frounding\-math \-fsched2\-use\-superblocks \-fsched\-pressure |
| 418 | \&\-fsched\-spec\-load \-fsched\-spec\-load\-dangerous |
| 419 | \&\-fsched\-stalled\-insns\-dep[=\fR\fIn\fR\fB] \-fsched\-stalled\-insns[=\fR\fIn\fR\fB] |
| 420 | \&\-fsched\-group\-heuristic \-fsched\-critical\-path\-heuristic |
| 421 | \&\-fsched\-spec\-insn\-heuristic \-fsched\-rank\-heuristic |
| 422 | \&\-fsched\-last\-insn\-heuristic \-fsched\-dep\-count\-heuristic |
| 423 | \&\-fschedule\-insns \-fschedule\-insns2 \-fsection\-anchors |
| 424 | \&\-fselective\-scheduling \-fselective\-scheduling2 |
| 425 | \&\-fsel\-sched\-pipelining \-fsel\-sched\-pipelining\-outer\-loops |
| 426 | \&\-fshrink\-wrap \-fsignaling\-nans \-fsingle\-precision\-constant |
| 427 | \&\-fsplit\-ivs\-in\-unroller \-fsplit\-wide\-types \-fstack\-protector |
| 428 | \&\-fstack\-protector\-all \-fstrict\-aliasing \-fstrict\-overflow |
| 429 | \&\-fthread\-jumps \-ftracer \-ftree\-bit\-ccp |
| 430 | \&\-ftree\-builtin\-call\-dce \-ftree\-ccp \-ftree\-ch \-ftree\-copy\-prop |
| 431 | \&\-ftree\-copyrename \-ftree\-dce \-ftree\-dominator\-opts \-ftree\-dse |
| 432 | \&\-ftree\-forwprop \-ftree\-fre \-ftree\-loop\-if\-convert |
| 433 | \&\-ftree\-loop\-if\-convert\-stores \-ftree\-loop\-im |
| 434 | \&\-ftree\-phiprop \-ftree\-loop\-distribution \-ftree\-loop\-distribute\-patterns |
| 435 | \&\-ftree\-loop\-ivcanon \-ftree\-loop\-linear \-ftree\-loop\-optimize |
| 436 | \&\-ftree\-parallelize\-loops=\fR\fIn\fR \fB\-ftree\-pre \-ftree\-pta \-ftree\-reassoc |
| 437 | \&\-ftree\-sink \-ftree\-sra \-ftree\-switch\-conversion \-ftree\-tail\-merge |
| 438 | \&\-ftree\-ter \-ftree\-vect\-loop\-version \-ftree\-vectorize \-ftree\-vrp |
| 439 | \&\-funit\-at\-a\-time \-funroll\-all\-loops \-funroll\-loops |
| 440 | \&\-funsafe\-loop\-optimizations \-funsafe\-math\-optimizations \-funswitch\-loops |
| 441 | \&\-fvariable\-expansion\-in\-unroller \-fvect\-cost\-model \-fvpt \-fweb |
| 442 | \&\-fwhole\-program \-fwpa \-fuse\-linker\-plugin |
| 443 | \&\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR |
| 444 | \&\fB\-O \-O0 \-O1 \-O2 \-O3 \-Os \-Ofast\fR |
| 445 | .IP "\fIPreprocessor Options\fR" 4 |
| 446 | .IX Item "Preprocessor Options" |
| 447 | \&\fB\-A\fR\fIquestion\fR\fB=\fR\fIanswer\fR |
| 448 | \&\fB\-A\-\fR\fIquestion\fR[\fB=\fR\fIanswer\fR] |
| 449 | \&\fB\-C \-dD \-dI \-dM \-dN |
| 450 | \&\-D\fR\fImacro\fR[\fB=\fR\fIdefn\fR] \fB\-E \-H |
| 451 | \&\-idirafter\fR \fIdir\fR |
| 452 | \&\fB\-include\fR \fIfile\fR \fB\-imacros\fR \fIfile\fR |
| 453 | \&\fB\-iprefix\fR \fIfile\fR \fB\-iwithprefix\fR \fIdir\fR |
| 454 | \&\fB\-iwithprefixbefore\fR \fIdir\fR \fB\-isystem\fR \fIdir\fR |
| 455 | \&\fB\-imultilib\fR \fIdir\fR \fB\-isysroot\fR \fIdir\fR |
| 456 | \&\fB\-M \-MM \-MF \-MG \-MP \-MQ \-MT \-nostdinc |
| 457 | \&\-P \-fdebug\-cpp \-ftrack\-macro\-expansion \-fworking\-directory |
| 458 | \&\-remap \-trigraphs \-undef \-U\fR\fImacro\fR |
| 459 | \&\fB\-Wp,\fR\fIoption\fR \fB\-Xpreprocessor\fR \fIoption\fR |
| 460 | .IP "\fIAssembler Option\fR" 4 |
| 461 | .IX Item "Assembler Option" |
| 462 | \&\fB\-Wa,\fR\fIoption\fR \fB\-Xassembler\fR \fIoption\fR |
| 463 | .IP "\fILinker Options\fR" 4 |
| 464 | .IX Item "Linker Options" |
| 465 | \&\fIobject-file-name\fR \fB\-l\fR\fIlibrary\fR |
| 466 | \&\fB\-nostartfiles \-nodefaultlibs \-nostdlib \-pie \-rdynamic |
| 467 | \&\-s \-static \-static\-libgcc \-static\-libstdc++ \-shared |
| 468 | \&\-shared\-libgcc \-symbolic |
| 469 | \&\-T\fR \fIscript\fR \fB\-Wl,\fR\fIoption\fR \fB\-Xlinker\fR \fIoption\fR |
| 470 | \&\fB\-u\fR \fIsymbol\fR |
| 471 | .IP "\fIDirectory Options\fR" 4 |
| 472 | .IX Item "Directory Options" |
| 473 | \&\fB\-B\fR\fIprefix\fR \fB\-I\fR\fIdir\fR \fB\-iplugindir=\fR\fIdir\fR |
| 474 | \&\fB\-iquote\fR\fIdir\fR \fB\-L\fR\fIdir\fR \fB\-specs=\fR\fIfile\fR \fB\-I\- |
| 475 | \&\-\-sysroot=\fR\fIdir\fR |
| 476 | .IP "\fIMachine Dependent Options\fR" 4 |
| 477 | .IX Item "Machine Dependent Options" |
| 478 | \&\fIAdapteva Epiphany Options\fR |
| 479 | \&\fB\-mhalf\-reg\-file \-mprefer\-short\-insn\-regs |
| 480 | \&\-mbranch\-cost=\fR\fInum\fR \fB\-mcmove \-mnops=\fR\fInum\fR \fB\-msoft\-cmpsf |
| 481 | \&\-msplit\-lohi \-mpost\-inc \-mpost\-modify \-mstack\-offset=\fR\fInum\fR |
| 482 | \&\fB\-mround\-nearest \-mlong\-calls \-mshort\-calls \-msmall16 |
| 483 | \&\-mfp\-mode=\fR\fImode\fR \fB\-mvect\-double \-max\-vect\-align=\fR\fInum\fR |
| 484 | \&\fB\-msplit\-vecmove\-early \-m1reg\-\fR\fIreg\fR |
| 485 | .Sp |
| 486 | \&\fI\s-1ARM\s0 Options\fR |
| 487 | \&\fB\-mapcs\-frame \-mno\-apcs\-frame |
| 488 | \&\-mabi=\fR\fIname\fR |
| 489 | \&\fB\-mapcs\-stack\-check \-mno\-apcs\-stack\-check |
| 490 | \&\-mapcs\-float \-mno\-apcs\-float |
| 491 | \&\-mapcs\-reentrant \-mno\-apcs\-reentrant |
| 492 | \&\-msched\-prolog \-mno\-sched\-prolog |
| 493 | \&\-mlittle\-endian \-mbig\-endian \-mwords\-little\-endian |
| 494 | \&\-mfloat\-abi=\fR\fIname\fR \fB\-mfpe |
| 495 | \&\-mfp16\-format=\fR\fIname\fR |
| 496 | \&\fB\-mthumb\-interwork \-mno\-thumb\-interwork |
| 497 | \&\-mcpu=\fR\fIname\fR \fB\-march=\fR\fIname\fR \fB\-mfpu=\fR\fIname\fR |
| 498 | \&\fB\-mstructure\-size\-boundary=\fR\fIn\fR |
| 499 | \&\fB\-mabort\-on\-noreturn |
| 500 | \&\-mlong\-calls \-mno\-long\-calls |
| 501 | \&\-msingle\-pic\-base \-mno\-single\-pic\-base |
| 502 | \&\-mpic\-register=\fR\fIreg\fR |
| 503 | \&\fB\-mnop\-fun\-dllimport |
| 504 | \&\-mcirrus\-fix\-invalid\-insns \-mno\-cirrus\-fix\-invalid\-insns |
| 505 | \&\-mpoke\-function\-name |
| 506 | \&\-mthumb \-marm |
| 507 | \&\-mtpcs\-frame \-mtpcs\-leaf\-frame |
| 508 | \&\-mcaller\-super\-interworking \-mcallee\-super\-interworking |
| 509 | \&\-mtp=\fR\fIname\fR \fB\-mtls\-dialect=\fR\fIdialect\fR |
| 510 | \&\fB\-mword\-relocations |
| 511 | \&\-mfix\-cortex\-m3\-ldrd |
| 512 | \&\-munaligned\-access\fR |
| 513 | .Sp |
| 514 | \&\fI\s-1AVR\s0 Options\fR |
| 515 | \&\fB\-mmcu=\fR\fImcu\fR \fB\-maccumulate\-args \-mbranch\-cost=\fR\fIcost\fR |
| 516 | \&\fB\-mcall\-prologues \-mint8 \-mno\-interrupts \-mrelax \-mshort\-calls |
| 517 | \&\-mstrict\-X \-mtiny\-stack\fR |
| 518 | .Sp |
| 519 | \&\fIBlackfin Options\fR |
| 520 | \&\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR] |
| 521 | \&\fB\-msim \-momit\-leaf\-frame\-pointer \-mno\-omit\-leaf\-frame\-pointer |
| 522 | \&\-mspecld\-anomaly \-mno\-specld\-anomaly \-mcsync\-anomaly \-mno\-csync\-anomaly |
| 523 | \&\-mlow\-64k \-mno\-low64k \-mstack\-check\-l1 \-mid\-shared\-library |
| 524 | \&\-mno\-id\-shared\-library \-mshared\-library\-id=\fR\fIn\fR |
| 525 | \&\fB\-mleaf\-id\-shared\-library \-mno\-leaf\-id\-shared\-library |
| 526 | \&\-msep\-data \-mno\-sep\-data \-mlong\-calls \-mno\-long\-calls |
| 527 | \&\-mfast\-fp \-minline\-plt \-mmulticore \-mcorea \-mcoreb \-msdram |
| 528 | \&\-micplb\fR |
| 529 | .Sp |
| 530 | \&\fIC6X Options\fR |
| 531 | \&\fB\-mbig\-endian \-mlittle\-endian \-march=\fR\fIcpu\fR |
| 532 | \&\fB\-msim \-msdata=\fR\fIsdata-type\fR |
| 533 | .Sp |
| 534 | \&\fI\s-1CRIS\s0 Options\fR |
| 535 | \&\fB\-mcpu=\fR\fIcpu\fR \fB\-march=\fR\fIcpu\fR \fB\-mtune=\fR\fIcpu\fR |
| 536 | \&\fB\-mmax\-stack\-frame=\fR\fIn\fR \fB\-melinux\-stacksize=\fR\fIn\fR |
| 537 | \&\fB\-metrax4 \-metrax100 \-mpdebug \-mcc\-init \-mno\-side\-effects |
| 538 | \&\-mstack\-align \-mdata\-align \-mconst\-align |
| 539 | \&\-m32\-bit \-m16\-bit \-m8\-bit \-mno\-prologue\-epilogue \-mno\-gotplt |
| 540 | \&\-melf \-maout \-melinux \-mlinux \-sim \-sim2 |
| 541 | \&\-mmul\-bug\-workaround \-mno\-mul\-bug\-workaround\fR |
| 542 | .Sp |
| 543 | \&\fI\s-1CR16\s0 Options\fR |
| 544 | \&\fB\-mmac |
| 545 | \&\-mcr16cplus \-mcr16c |
| 546 | \&\-msim \-mint32 \-mbit\-ops |
| 547 | \&\-mdata\-model=\fR\fImodel\fR |
| 548 | .Sp |
| 549 | \&\fIDarwin Options\fR |
| 550 | \&\fB\-all_load \-allowable_client \-arch \-arch_errors_fatal |
| 551 | \&\-arch_only \-bind_at_load \-bundle \-bundle_loader |
| 552 | \&\-client_name \-compatibility_version \-current_version |
| 553 | \&\-dead_strip |
| 554 | \&\-dependency\-file \-dylib_file \-dylinker_install_name |
| 555 | \&\-dynamic \-dynamiclib \-exported_symbols_list |
| 556 | \&\-filelist \-flat_namespace \-force_cpusubtype_ALL |
| 557 | \&\-force_flat_namespace \-headerpad_max_install_names |
| 558 | \&\-iframework |
| 559 | \&\-image_base \-init \-install_name \-keep_private_externs |
| 560 | \&\-multi_module \-multiply_defined \-multiply_defined_unused |
| 561 | \&\-noall_load \-no_dead_strip_inits_and_terms |
| 562 | \&\-nofixprebinding \-nomultidefs \-noprebind \-noseglinkedit |
| 563 | \&\-pagezero_size \-prebind \-prebind_all_twolevel_modules |
| 564 | \&\-private_bundle \-read_only_relocs \-sectalign |
| 565 | \&\-sectobjectsymbols \-whyload \-seg1addr |
| 566 | \&\-sectcreate \-sectobjectsymbols \-sectorder |
| 567 | \&\-segaddr \-segs_read_only_addr \-segs_read_write_addr |
| 568 | \&\-seg_addr_table \-seg_addr_table_filename \-seglinkedit |
| 569 | \&\-segprot \-segs_read_only_addr \-segs_read_write_addr |
| 570 | \&\-single_module \-static \-sub_library \-sub_umbrella |
| 571 | \&\-twolevel_namespace \-umbrella \-undefined |
| 572 | \&\-unexported_symbols_list \-weak_reference_mismatches |
| 573 | \&\-whatsloaded \-F \-gused \-gfull \-mmacosx\-version\-min=\fR\fIversion\fR |
| 574 | \&\fB\-mkernel \-mone\-byte\-bool\fR |
| 575 | .Sp |
| 576 | \&\fI\s-1DEC\s0 Alpha Options\fR |
| 577 | \&\fB\-mno\-fp\-regs \-msoft\-float \-malpha\-as \-mgas |
| 578 | \&\-mieee \-mieee\-with\-inexact \-mieee\-conformant |
| 579 | \&\-mfp\-trap\-mode=\fR\fImode\fR \fB\-mfp\-rounding\-mode=\fR\fImode\fR |
| 580 | \&\fB\-mtrap\-precision=\fR\fImode\fR \fB\-mbuild\-constants |
| 581 | \&\-mcpu=\fR\fIcpu-type\fR \fB\-mtune=\fR\fIcpu-type\fR |
| 582 | \&\fB\-mbwx \-mmax \-mfix \-mcix |
| 583 | \&\-mfloat\-vax \-mfloat\-ieee |
| 584 | \&\-mexplicit\-relocs \-msmall\-data \-mlarge\-data |
| 585 | \&\-msmall\-text \-mlarge\-text |
| 586 | \&\-mmemory\-latency=\fR\fItime\fR |
| 587 | .Sp |
| 588 | \&\fI\s-1DEC\s0 Alpha/VMS Options\fR |
| 589 | \&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64\fR |
| 590 | .Sp |
| 591 | \&\fI\s-1FR30\s0 Options\fR |
| 592 | \&\fB\-msmall\-model \-mno\-lsim\fR |
| 593 | .Sp |
| 594 | \&\fI\s-1FRV\s0 Options\fR |
| 595 | \&\fB\-mgpr\-32 \-mgpr\-64 \-mfpr\-32 \-mfpr\-64 |
| 596 | \&\-mhard\-float \-msoft\-float |
| 597 | \&\-malloc\-cc \-mfixed\-cc \-mdword \-mno\-dword |
| 598 | \&\-mdouble \-mno\-double |
| 599 | \&\-mmedia \-mno\-media \-mmuladd \-mno\-muladd |
| 600 | \&\-mfdpic \-minline\-plt \-mgprel\-ro \-multilib\-library\-pic |
| 601 | \&\-mlinked\-fp \-mlong\-calls \-malign\-labels |
| 602 | \&\-mlibrary\-pic \-macc\-4 \-macc\-8 |
| 603 | \&\-mpack \-mno\-pack \-mno\-eflags \-mcond\-move \-mno\-cond\-move |
| 604 | \&\-moptimize\-membar \-mno\-optimize\-membar |
| 605 | \&\-mscc \-mno\-scc \-mcond\-exec \-mno\-cond\-exec |
| 606 | \&\-mvliw\-branch \-mno\-vliw\-branch |
| 607 | \&\-mmulti\-cond\-exec \-mno\-multi\-cond\-exec \-mnested\-cond\-exec |
| 608 | \&\-mno\-nested\-cond\-exec \-mtomcat\-stats |
| 609 | \&\-mTLS \-mtls |
| 610 | \&\-mcpu=\fR\fIcpu\fR |
| 611 | .Sp |
| 612 | \&\fIGNU/Linux Options\fR |
| 613 | \&\fB\-mglibc \-muclibc \-mbionic \-mandroid |
| 614 | \&\-tno\-android\-cc \-tno\-android\-ld\fR |
| 615 | .Sp |
| 616 | \&\fIH8/300 Options\fR |
| 617 | \&\fB\-mrelax \-mh \-ms \-mn \-mint32 \-malign\-300\fR |
| 618 | .Sp |
| 619 | \&\fI\s-1HPPA\s0 Options\fR |
| 620 | \&\fB\-march=\fR\fIarchitecture-type\fR |
| 621 | \&\fB\-mbig\-switch \-mdisable\-fpregs \-mdisable\-indexing |
| 622 | \&\-mfast\-indirect\-calls \-mgas \-mgnu\-ld \-mhp\-ld |
| 623 | \&\-mfixed\-range=\fR\fIregister-range\fR |
| 624 | \&\fB\-mjump\-in\-delay \-mlinker\-opt \-mlong\-calls |
| 625 | \&\-mlong\-load\-store \-mno\-big\-switch \-mno\-disable\-fpregs |
| 626 | \&\-mno\-disable\-indexing \-mno\-fast\-indirect\-calls \-mno\-gas |
| 627 | \&\-mno\-jump\-in\-delay \-mno\-long\-load\-store |
| 628 | \&\-mno\-portable\-runtime \-mno\-soft\-float |
| 629 | \&\-mno\-space\-regs \-msoft\-float \-mpa\-risc\-1\-0 |
| 630 | \&\-mpa\-risc\-1\-1 \-mpa\-risc\-2\-0 \-mportable\-runtime |
| 631 | \&\-mschedule=\fR\fIcpu-type\fR \fB\-mspace\-regs \-msio \-mwsio |
| 632 | \&\-munix=\fR\fIunix-std\fR \fB\-nolibdld \-static \-threads\fR |
| 633 | .Sp |
| 634 | \&\fIi386 and x86\-64 Options\fR |
| 635 | \&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR |
| 636 | \&\fB\-mfpmath=\fR\fIunit\fR |
| 637 | \&\fB\-masm=\fR\fIdialect\fR \fB\-mno\-fancy\-math\-387 |
| 638 | \&\-mno\-fp\-ret\-in\-387 \-msoft\-float |
| 639 | \&\-mno\-wide\-multiply \-mrtd \-malign\-double |
| 640 | \&\-mpreferred\-stack\-boundary=\fR\fInum\fR |
| 641 | \&\fB\-mincoming\-stack\-boundary=\fR\fInum\fR |
| 642 | \&\fB\-mcld \-mcx16 \-msahf \-mmovbe \-mcrc32 |
| 643 | \&\-mrecip \-mrecip=\fR\fIopt\fR |
| 644 | \&\fB\-mvzeroupper \-mprefer\-avx128 |
| 645 | \&\-mmmx \-msse \-msse2 \-msse3 \-mssse3 \-msse4.1 \-msse4.2 \-msse4 \-mavx |
| 646 | \&\-mavx2 \-maes \-mpclmul \-mfsgsbase \-mrdrnd \-mf16c \-mfma |
| 647 | \&\-msse4a \-m3dnow \-mpopcnt \-mabm \-mbmi \-mtbm \-mfma4 \-mxop \-mlzcnt |
| 648 | \&\-mbmi2 \-mlwp \-mthreads \-mno\-align\-stringops \-minline\-all\-stringops |
| 649 | \&\-minline\-stringops\-dynamically \-mstringop\-strategy=\fR\fIalg\fR |
| 650 | \&\fB\-mpush\-args \-maccumulate\-outgoing\-args \-m128bit\-long\-double |
| 651 | \&\-m96bit\-long\-double \-mregparm=\fR\fInum\fR \fB\-msseregparm |
| 652 | \&\-mveclibabi=\fR\fItype\fR \fB\-mvect8\-ret\-in\-mem |
| 653 | \&\-mpc32 \-mpc64 \-mpc80 \-mstackrealign |
| 654 | \&\-momit\-leaf\-frame\-pointer \-mno\-red\-zone \-mno\-tls\-direct\-seg\-refs |
| 655 | \&\-mcmodel=\fR\fIcode-model\fR \fB\-mabi=\fR\fIname\fR |
| 656 | \&\fB\-m32 \-m64 \-mx32 \-mlarge\-data\-threshold=\fR\fInum\fR |
| 657 | \&\fB\-msse2avx \-mfentry \-m8bit\-idiv |
| 658 | \&\-mavx256\-split\-unaligned\-load \-mavx256\-split\-unaligned\-store\fR |
| 659 | .Sp |
| 660 | \&\fIi386 and x86\-64 Windows Options\fR |
| 661 | \&\fB\-mconsole \-mcygwin \-mno\-cygwin \-mdll |
| 662 | \&\-mnop\-fun\-dllimport \-mthread |
| 663 | \&\-municode \-mwin32 \-mwindows \-fno\-set\-stack\-executable\fR |
| 664 | .Sp |
| 665 | \&\fI\s-1IA\-64\s0 Options\fR |
| 666 | \&\fB\-mbig\-endian \-mlittle\-endian \-mgnu\-as \-mgnu\-ld \-mno\-pic |
| 667 | \&\-mvolatile\-asm\-stop \-mregister\-names \-msdata \-mno\-sdata |
| 668 | \&\-mconstant\-gp \-mauto\-pic \-mfused\-madd |
| 669 | \&\-minline\-float\-divide\-min\-latency |
| 670 | \&\-minline\-float\-divide\-max\-throughput |
| 671 | \&\-mno\-inline\-float\-divide |
| 672 | \&\-minline\-int\-divide\-min\-latency |
| 673 | \&\-minline\-int\-divide\-max\-throughput |
| 674 | \&\-mno\-inline\-int\-divide |
| 675 | \&\-minline\-sqrt\-min\-latency \-minline\-sqrt\-max\-throughput |
| 676 | \&\-mno\-inline\-sqrt |
| 677 | \&\-mdwarf2\-asm \-mearly\-stop\-bits |
| 678 | \&\-mfixed\-range=\fR\fIregister-range\fR \fB\-mtls\-size=\fR\fItls-size\fR |
| 679 | \&\fB\-mtune=\fR\fIcpu-type\fR \fB\-milp32 \-mlp64 |
| 680 | \&\-msched\-br\-data\-spec \-msched\-ar\-data\-spec \-msched\-control\-spec |
| 681 | \&\-msched\-br\-in\-data\-spec \-msched\-ar\-in\-data\-spec \-msched\-in\-control\-spec |
| 682 | \&\-msched\-spec\-ldc \-msched\-spec\-control\-ldc |
| 683 | \&\-msched\-prefer\-non\-data\-spec\-insns \-msched\-prefer\-non\-control\-spec\-insns |
| 684 | \&\-msched\-stop\-bits\-after\-every\-cycle \-msched\-count\-spec\-in\-critical\-path |
| 685 | \&\-msel\-sched\-dont\-check\-control\-spec \-msched\-fp\-mem\-deps\-zero\-cost |
| 686 | \&\-msched\-max\-memory\-insns\-hard\-limit \-msched\-max\-memory\-insns=\fR\fImax-insns\fR |
| 687 | .Sp |
| 688 | \&\fI\s-1IA\-64/VMS\s0 Options\fR |
| 689 | \&\fB\-mvms\-return\-codes \-mdebug\-main=\fR\fIprefix\fR \fB\-mmalloc64\fR |
| 690 | .Sp |
| 691 | \&\fI\s-1LM32\s0 Options\fR |
| 692 | \&\fB\-mbarrel\-shift\-enabled \-mdivide\-enabled \-mmultiply\-enabled |
| 693 | \&\-msign\-extend\-enabled \-muser\-enabled\fR |
| 694 | .Sp |
| 695 | \&\fIM32R/D Options\fR |
| 696 | \&\fB\-m32r2 \-m32rx \-m32r |
| 697 | \&\-mdebug |
| 698 | \&\-malign\-loops \-mno\-align\-loops |
| 699 | \&\-missue\-rate=\fR\fInumber\fR |
| 700 | \&\fB\-mbranch\-cost=\fR\fInumber\fR |
| 701 | \&\fB\-mmodel=\fR\fIcode-size-model-type\fR |
| 702 | \&\fB\-msdata=\fR\fIsdata-type\fR |
| 703 | \&\fB\-mno\-flush\-func \-mflush\-func=\fR\fIname\fR |
| 704 | \&\fB\-mno\-flush\-trap \-mflush\-trap=\fR\fInumber\fR |
| 705 | \&\fB\-G\fR \fInum\fR |
| 706 | .Sp |
| 707 | \&\fIM32C Options\fR |
| 708 | \&\fB\-mcpu=\fR\fIcpu\fR \fB\-msim \-memregs=\fR\fInumber\fR |
| 709 | .Sp |
| 710 | \&\fIM680x0 Options\fR |
| 711 | \&\fB\-march=\fR\fIarch\fR \fB\-mcpu=\fR\fIcpu\fR \fB\-mtune=\fR\fItune\fR |
| 712 | \&\fB\-m68000 \-m68020 \-m68020\-40 \-m68020\-60 \-m68030 \-m68040 |
| 713 | \&\-m68060 \-mcpu32 \-m5200 \-m5206e \-m528x \-m5307 \-m5407 |
| 714 | \&\-mcfv4e \-mbitfield \-mno\-bitfield \-mc68000 \-mc68020 |
| 715 | \&\-mnobitfield \-mrtd \-mno\-rtd \-mdiv \-mno\-div \-mshort |
| 716 | \&\-mno\-short \-mhard\-float \-m68881 \-msoft\-float \-mpcrel |
| 717 | \&\-malign\-int \-mstrict\-align \-msep\-data \-mno\-sep\-data |
| 718 | \&\-mshared\-library\-id=n \-mid\-shared\-library \-mno\-id\-shared\-library |
| 719 | \&\-mxgot \-mno\-xgot\fR |
| 720 | .Sp |
| 721 | \&\fIMCore Options\fR |
| 722 | \&\fB\-mhardlit \-mno\-hardlit \-mdiv \-mno\-div \-mrelax\-immediates |
| 723 | \&\-mno\-relax\-immediates \-mwide\-bitfields \-mno\-wide\-bitfields |
| 724 | \&\-m4byte\-functions \-mno\-4byte\-functions \-mcallgraph\-data |
| 725 | \&\-mno\-callgraph\-data \-mslow\-bytes \-mno\-slow\-bytes \-mno\-lsim |
| 726 | \&\-mlittle\-endian \-mbig\-endian \-m210 \-m340 \-mstack\-increment\fR |
| 727 | .Sp |
| 728 | \&\fIMeP Options\fR |
| 729 | \&\fB\-mabsdiff \-mall\-opts \-maverage \-mbased=\fR\fIn\fR \fB\-mbitops |
| 730 | \&\-mc=\fR\fIn\fR \fB\-mclip \-mconfig=\fR\fIname\fR \fB\-mcop \-mcop32 \-mcop64 \-mivc2 |
| 731 | \&\-mdc \-mdiv \-meb \-mel \-mio\-volatile \-ml \-mleadz \-mm \-mminmax |
| 732 | \&\-mmult \-mno\-opts \-mrepeat \-ms \-msatur \-msdram \-msim \-msimnovec \-mtf |
| 733 | \&\-mtiny=\fR\fIn\fR |
| 734 | .Sp |
| 735 | \&\fIMicroBlaze Options\fR |
| 736 | \&\fB\-msoft\-float \-mhard\-float \-msmall\-divides \-mcpu=\fR\fIcpu\fR |
| 737 | \&\fB\-mmemcpy \-mxl\-soft\-mul \-mxl\-soft\-div \-mxl\-barrel\-shift |
| 738 | \&\-mxl\-pattern\-compare \-mxl\-stack\-check \-mxl\-gp\-opt \-mno\-clearbss |
| 739 | \&\-mxl\-multiply\-high \-mxl\-float\-convert \-mxl\-float\-sqrt |
| 740 | \&\-mxl\-mode\-\fR\fIapp-model\fR |
| 741 | .Sp |
| 742 | \&\fI\s-1MIPS\s0 Options\fR |
| 743 | \&\fB\-EL \-EB \-march=\fR\fIarch\fR \fB\-mtune=\fR\fIarch\fR |
| 744 | \&\fB\-mips1 \-mips2 \-mips3 \-mips4 \-mips32 \-mips32r2 |
| 745 | \&\-mips64 \-mips64r2 |
| 746 | \&\-mips16 \-mno\-mips16 \-mflip\-mips16 |
| 747 | \&\-minterlink\-mips16 \-mno\-interlink\-mips16 |
| 748 | \&\-mabi=\fR\fIabi\fR \fB\-mabicalls \-mno\-abicalls |
| 749 | \&\-mshared \-mno\-shared \-mplt \-mno\-plt \-mxgot \-mno\-xgot |
| 750 | \&\-mgp32 \-mgp64 \-mfp32 \-mfp64 \-mhard\-float \-msoft\-float |
| 751 | \&\-msingle\-float \-mdouble\-float \-mdsp \-mno\-dsp \-mdspr2 \-mno\-dspr2 |
| 752 | \&\-mfpu=\fR\fIfpu-type\fR |
| 753 | \&\fB\-msmartmips \-mno\-smartmips |
| 754 | \&\-mpaired\-single \-mno\-paired\-single \-mdmx \-mno\-mdmx |
| 755 | \&\-mips3d \-mno\-mips3d \-mmt \-mno\-mt \-mllsc \-mno\-llsc |
| 756 | \&\-mlong64 \-mlong32 \-msym32 \-mno\-sym32 |
| 757 | \&\-G\fR\fInum\fR \fB\-mlocal\-sdata \-mno\-local\-sdata |
| 758 | \&\-mextern\-sdata \-mno\-extern\-sdata \-mgpopt \-mno\-gopt |
| 759 | \&\-membedded\-data \-mno\-embedded\-data |
| 760 | \&\-muninit\-const\-in\-rodata \-mno\-uninit\-const\-in\-rodata |
| 761 | \&\-mcode\-readable=\fR\fIsetting\fR |
| 762 | \&\fB\-msplit\-addresses \-mno\-split\-addresses |
| 763 | \&\-mexplicit\-relocs \-mno\-explicit\-relocs |
| 764 | \&\-mcheck\-zero\-division \-mno\-check\-zero\-division |
| 765 | \&\-mdivide\-traps \-mdivide\-breaks |
| 766 | \&\-mmemcpy \-mno\-memcpy \-mlong\-calls \-mno\-long\-calls |
| 767 | \&\-mmad \-mno\-mad \-mfused\-madd \-mno\-fused\-madd \-nocpp |
| 768 | \&\-mfix\-24k \-mno\-fix\-24k |
| 769 | \&\-mfix\-r4000 \-mno\-fix\-r4000 \-mfix\-r4400 \-mno\-fix\-r4400 |
| 770 | \&\-mfix\-r10000 \-mno\-fix\-r10000 \-mfix\-vr4120 \-mno\-fix\-vr4120 |
| 771 | \&\-mfix\-vr4130 \-mno\-fix\-vr4130 \-mfix\-sb1 \-mno\-fix\-sb1 |
| 772 | \&\-mflush\-func=\fR\fIfunc\fR \fB\-mno\-flush\-func |
| 773 | \&\-mbranch\-cost=\fR\fInum\fR \fB\-mbranch\-likely \-mno\-branch\-likely |
| 774 | \&\-mfp\-exceptions \-mno\-fp\-exceptions |
| 775 | \&\-mvr4130\-align \-mno\-vr4130\-align \-msynci \-mno\-synci |
| 776 | \&\-mrelax\-pic\-calls \-mno\-relax\-pic\-calls \-mmcount\-ra\-address\fR |
| 777 | .Sp |
| 778 | \&\fI\s-1MMIX\s0 Options\fR |
| 779 | \&\fB\-mlibfuncs \-mno\-libfuncs \-mepsilon \-mno\-epsilon \-mabi=gnu |
| 780 | \&\-mabi=mmixware \-mzero\-extend \-mknuthdiv \-mtoplevel\-symbols |
| 781 | \&\-melf \-mbranch\-predict \-mno\-branch\-predict \-mbase\-addresses |
| 782 | \&\-mno\-base\-addresses \-msingle\-exit \-mno\-single\-exit\fR |
| 783 | .Sp |
| 784 | \&\fI\s-1MN10300\s0 Options\fR |
| 785 | \&\fB\-mmult\-bug \-mno\-mult\-bug |
| 786 | \&\-mno\-am33 \-mam33 \-mam33\-2 \-mam34 |
| 787 | \&\-mtune=\fR\fIcpu-type\fR |
| 788 | \&\fB\-mreturn\-pointer\-on\-d0 |
| 789 | \&\-mno\-crt0 \-mrelax \-mliw \-msetlb\fR |
| 790 | .Sp |
| 791 | \&\fI\s-1PDP\-11\s0 Options\fR |
| 792 | \&\fB\-mfpu \-msoft\-float \-mac0 \-mno\-ac0 \-m40 \-m45 \-m10 |
| 793 | \&\-mbcopy \-mbcopy\-builtin \-mint32 \-mno\-int16 |
| 794 | \&\-mint16 \-mno\-int32 \-mfloat32 \-mno\-float64 |
| 795 | \&\-mfloat64 \-mno\-float32 \-mabshi \-mno\-abshi |
| 796 | \&\-mbranch\-expensive \-mbranch\-cheap |
| 797 | \&\-munix\-asm \-mdec\-asm\fR |
| 798 | .Sp |
| 799 | \&\fIpicoChip Options\fR |
| 800 | \&\fB\-mae=\fR\fIae_type\fR \fB\-mvliw\-lookahead=\fR\fIN\fR |
| 801 | \&\fB\-msymbol\-as\-address \-mno\-inefficient\-warnings\fR |
| 802 | .Sp |
| 803 | \&\fIPowerPC Options\fR |
| 804 | See \s-1RS/6000\s0 and PowerPC Options. |
| 805 | .Sp |
| 806 | \&\fI\s-1RL78\s0 Options\fR |
| 807 | \&\fB\-msim \-mmul=none \-mmul=g13 \-mmul=rl78\fR |
| 808 | .Sp |
| 809 | \&\fI\s-1RS/6000\s0 and PowerPC Options\fR |
| 810 | \&\fB\-mcpu=\fR\fIcpu-type\fR |
| 811 | \&\fB\-mtune=\fR\fIcpu-type\fR |
| 812 | \&\fB\-mcmodel=\fR\fIcode-model\fR |
| 813 | \&\fB\-mpower \-mno\-power \-mpower2 \-mno\-power2 |
| 814 | \&\-mpowerpc \-mpowerpc64 \-mno\-powerpc |
| 815 | \&\-maltivec \-mno\-altivec |
| 816 | \&\-mpowerpc\-gpopt \-mno\-powerpc\-gpopt |
| 817 | \&\-mpowerpc\-gfxopt \-mno\-powerpc\-gfxopt |
| 818 | \&\-mmfcrf \-mno\-mfcrf \-mpopcntb \-mno\-popcntb \-mpopcntd \-mno\-popcntd |
| 819 | \&\-mfprnd \-mno\-fprnd |
| 820 | \&\-mcmpb \-mno\-cmpb \-mmfpgpr \-mno\-mfpgpr \-mhard\-dfp \-mno\-hard\-dfp |
| 821 | \&\-mnew\-mnemonics \-mold\-mnemonics |
| 822 | \&\-mfull\-toc \-mminimal\-toc \-mno\-fp\-in\-toc \-mno\-sum\-in\-toc |
| 823 | \&\-m64 \-m32 \-mxl\-compat \-mno\-xl\-compat \-mpe |
| 824 | \&\-malign\-power \-malign\-natural |
| 825 | \&\-msoft\-float \-mhard\-float \-mmultiple \-mno\-multiple |
| 826 | \&\-msingle\-float \-mdouble\-float \-msimple\-fpu |
| 827 | \&\-mstring \-mno\-string \-mupdate \-mno\-update |
| 828 | \&\-mavoid\-indexed\-addresses \-mno\-avoid\-indexed\-addresses |
| 829 | \&\-mfused\-madd \-mno\-fused\-madd \-mbit\-align \-mno\-bit\-align |
| 830 | \&\-mstrict\-align \-mno\-strict\-align \-mrelocatable |
| 831 | \&\-mno\-relocatable \-mrelocatable\-lib \-mno\-relocatable\-lib |
| 832 | \&\-mtoc \-mno\-toc \-mlittle \-mlittle\-endian \-mbig \-mbig\-endian |
| 833 | \&\-mdynamic\-no\-pic \-maltivec \-mswdiv \-msingle\-pic\-base |
| 834 | \&\-mprioritize\-restricted\-insns=\fR\fIpriority\fR |
| 835 | \&\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR |
| 836 | \&\fB\-minsert\-sched\-nops=\fR\fIscheme\fR |
| 837 | \&\fB\-mcall\-sysv \-mcall\-netbsd |
| 838 | \&\-maix\-struct\-return \-msvr4\-struct\-return |
| 839 | \&\-mabi=\fR\fIabi-type\fR \fB\-msecure\-plt \-mbss\-plt |
| 840 | \&\-mblock\-move\-inline\-limit=\fR\fInum\fR |
| 841 | \&\fB\-misel \-mno\-isel |
| 842 | \&\-misel=yes \-misel=no |
| 843 | \&\-mspe \-mno\-spe |
| 844 | \&\-mspe=yes \-mspe=no |
| 845 | \&\-mpaired |
| 846 | \&\-mgen\-cell\-microcode \-mwarn\-cell\-microcode |
| 847 | \&\-mvrsave \-mno\-vrsave |
| 848 | \&\-mmulhw \-mno\-mulhw |
| 849 | \&\-mdlmzb \-mno\-dlmzb |
| 850 | \&\-mfloat\-gprs=yes \-mfloat\-gprs=no \-mfloat\-gprs=single \-mfloat\-gprs=double |
| 851 | \&\-mprototype \-mno\-prototype |
| 852 | \&\-msim \-mmvme \-mads \-myellowknife \-memb \-msdata |
| 853 | \&\-msdata=\fR\fIopt\fR \fB\-mvxworks \-G\fR \fInum\fR \fB\-pthread |
| 854 | \&\-mrecip \-mrecip=\fR\fIopt\fR \fB\-mno\-recip \-mrecip\-precision |
| 855 | \&\-mno\-recip\-precision |
| 856 | \&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz |
| 857 | \&\-mpointers\-to\-nested\-functions \-mno\-pointers\-to\-nested\-functions |
| 858 | \&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect\fR |
| 859 | .Sp |
| 860 | \&\fI\s-1RX\s0 Options\fR |
| 861 | \&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu |
| 862 | \&\-mcpu= |
| 863 | \&\-mbig\-endian\-data \-mlittle\-endian\-data |
| 864 | \&\-msmall\-data |
| 865 | \&\-msim \-mno\-sim |
| 866 | \&\-mas100\-syntax \-mno\-as100\-syntax |
| 867 | \&\-mrelax |
| 868 | \&\-mmax\-constant\-size= |
| 869 | \&\-mint\-register= |
| 870 | \&\-mpid |
| 871 | \&\-msave\-acc\-in\-interrupts\fR |
| 872 | .Sp |
| 873 | \&\fIS/390 and zSeries Options\fR |
| 874 | \&\fB\-mtune=\fR\fIcpu-type\fR \fB\-march=\fR\fIcpu-type\fR |
| 875 | \&\fB\-mhard\-float \-msoft\-float \-mhard\-dfp \-mno\-hard\-dfp |
| 876 | \&\-mlong\-double\-64 \-mlong\-double\-128 |
| 877 | \&\-mbackchain \-mno\-backchain \-mpacked\-stack \-mno\-packed\-stack |
| 878 | \&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle |
| 879 | \&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch |
| 880 | \&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd |
| 881 | \&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard\fR |
| 882 | .Sp |
| 883 | \&\fIScore Options\fR |
| 884 | \&\fB\-meb \-mel |
| 885 | \&\-mnhwloop |
| 886 | \&\-muls |
| 887 | \&\-mmac |
| 888 | \&\-mscore5 \-mscore5u \-mscore7 \-mscore7d\fR |
| 889 | .Sp |
| 890 | \&\fI\s-1SH\s0 Options\fR |
| 891 | \&\fB\-m1 \-m2 \-m2e |
| 892 | \&\-m2a\-nofpu \-m2a\-single\-only \-m2a\-single \-m2a |
| 893 | \&\-m3 \-m3e |
| 894 | \&\-m4\-nofpu \-m4\-single\-only \-m4\-single \-m4 |
| 895 | \&\-m4a\-nofpu \-m4a\-single\-only \-m4a\-single \-m4a \-m4al |
| 896 | \&\-m5\-64media \-m5\-64media\-nofpu |
| 897 | \&\-m5\-32media \-m5\-32media\-nofpu |
| 898 | \&\-m5\-compact \-m5\-compact\-nofpu |
| 899 | \&\-mb \-ml \-mdalign \-mrelax |
| 900 | \&\-mbigtable \-mfmovd \-mhitachi \-mrenesas \-mno\-renesas \-mnomacsave |
| 901 | \&\-mieee \-mno\-ieee \-mbitops \-misize \-minline\-ic_invalidate \-mpadstruct |
| 902 | \&\-mspace \-mprefergot \-musermode \-multcost=\fR\fInumber\fR \fB\-mdiv=\fR\fIstrategy\fR |
| 903 | \&\fB\-mdivsi3_libfunc=\fR\fIname\fR \fB\-mfixed\-range=\fR\fIregister-range\fR |
| 904 | \&\fB\-madjust\-unroll \-mindexed\-addressing \-mgettrcost=\fR\fInumber\fR \fB\-mpt\-fixed |
| 905 | \&\-maccumulate\-outgoing\-args \-minvalid\-symbols \-msoft\-atomic |
| 906 | \&\-mbranch\-cost=\fR\fInum\fR \fB\-mcbranchdi \-mcmpeqdi \-mfused\-madd \-mpretend\-cmove\fR |
| 907 | .Sp |
| 908 | \&\fISolaris 2 Options\fR |
| 909 | \&\fB\-mimpure\-text \-mno\-impure\-text |
| 910 | \&\-pthreads \-pthread\fR |
| 911 | .Sp |
| 912 | \&\fI\s-1SPARC\s0 Options\fR |
| 913 | \&\fB\-mcpu=\fR\fIcpu-type\fR |
| 914 | \&\fB\-mtune=\fR\fIcpu-type\fR |
| 915 | \&\fB\-mcmodel=\fR\fIcode-model\fR |
| 916 | \&\fB\-mmemory\-model=\fR\fImem-model\fR |
| 917 | \&\fB\-m32 \-m64 \-mapp\-regs \-mno\-app\-regs |
| 918 | \&\-mfaster\-structs \-mno\-faster\-structs \-mflat \-mno\-flat |
| 919 | \&\-mfpu \-mno\-fpu \-mhard\-float \-msoft\-float |
| 920 | \&\-mhard\-quad\-float \-msoft\-quad\-float |
| 921 | \&\-mstack\-bias \-mno\-stack\-bias |
| 922 | \&\-munaligned\-doubles \-mno\-unaligned\-doubles |
| 923 | \&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis |
| 924 | \&\-mvis2 \-mno\-vis2 \-mvis3 \-mno\-vis3 |
| 925 | \&\-mfmaf \-mno\-fmaf \-mpopc \-mno\-popc |
| 926 | \&\-mfix\-at697f\fR |
| 927 | .Sp |
| 928 | \&\fI\s-1SPU\s0 Options\fR |
| 929 | \&\fB\-mwarn\-reloc \-merror\-reloc |
| 930 | \&\-msafe\-dma \-munsafe\-dma |
| 931 | \&\-mbranch\-hints |
| 932 | \&\-msmall\-mem \-mlarge\-mem \-mstdmain |
| 933 | \&\-mfixed\-range=\fR\fIregister-range\fR |
| 934 | \&\fB\-mea32 \-mea64 |
| 935 | \&\-maddress\-space\-conversion \-mno\-address\-space\-conversion |
| 936 | \&\-mcache\-size=\fR\fIcache-size\fR |
| 937 | \&\fB\-matomic\-updates \-mno\-atomic\-updates\fR |
| 938 | .Sp |
| 939 | \&\fISystem V Options\fR |
| 940 | \&\fB\-Qy \-Qn \-YP,\fR\fIpaths\fR \fB\-Ym,\fR\fIdir\fR |
| 941 | .Sp |
| 942 | \&\fITILE-Gx Options\fR |
| 943 | \&\fB\-mcpu=\fR\fIcpu\fR \fB\-m32 \-m64\fR |
| 944 | .Sp |
| 945 | \&\fITILEPro Options\fR |
| 946 | \&\fB\-mcpu=\fR\fIcpu\fR \fB\-m32\fR |
| 947 | .Sp |
| 948 | \&\fIV850 Options\fR |
| 949 | \&\fB\-mlong\-calls \-mno\-long\-calls \-mep \-mno\-ep |
| 950 | \&\-mprolog\-function \-mno\-prolog\-function \-mspace |
| 951 | \&\-mtda=\fR\fIn\fR \fB\-msda=\fR\fIn\fR \fB\-mzda=\fR\fIn\fR |
| 952 | \&\fB\-mapp\-regs \-mno\-app\-regs |
| 953 | \&\-mdisable\-callt \-mno\-disable\-callt |
| 954 | \&\-mv850e2v3 |
| 955 | \&\-mv850e2 |
| 956 | \&\-mv850e1 \-mv850es |
| 957 | \&\-mv850e |
| 958 | \&\-mv850 \-mbig\-switch\fR |
| 959 | .Sp |
| 960 | \&\fI\s-1VAX\s0 Options\fR |
| 961 | \&\fB\-mg \-mgnu \-munix\fR |
| 962 | .Sp |
| 963 | \&\fIVxWorks Options\fR |
| 964 | \&\fB\-mrtp \-non\-static \-Bstatic \-Bdynamic |
| 965 | \&\-Xbind\-lazy \-Xbind\-now\fR |
| 966 | .Sp |
| 967 | \&\fIx86\-64 Options\fR |
| 968 | See i386 and x86\-64 Options. |
| 969 | .Sp |
| 970 | \&\fIXstormy16 Options\fR |
| 971 | \&\fB\-msim\fR |
| 972 | .Sp |
| 973 | \&\fIXtensa Options\fR |
| 974 | \&\fB\-mconst16 \-mno\-const16 |
| 975 | \&\-mfused\-madd \-mno\-fused\-madd |
| 976 | \&\-mforce\-no\-pic |
| 977 | \&\-mserialize\-volatile \-mno\-serialize\-volatile |
| 978 | \&\-mtext\-section\-literals \-mno\-text\-section\-literals |
| 979 | \&\-mtarget\-align \-mno\-target\-align |
| 980 | \&\-mlongcalls \-mno\-longcalls\fR |
| 981 | .Sp |
| 982 | \&\fIzSeries Options\fR |
| 983 | See S/390 and zSeries Options. |
| 984 | .IP "\fICode Generation Options\fR" 4 |
| 985 | .IX Item "Code Generation Options" |
| 986 | \&\fB\-fcall\-saved\-\fR\fIreg\fR \fB\-fcall\-used\-\fR\fIreg\fR |
| 987 | \&\fB\-ffixed\-\fR\fIreg\fR \fB\-fexceptions |
| 988 | \&\-fnon\-call\-exceptions \-funwind\-tables |
| 989 | \&\-fasynchronous\-unwind\-tables |
| 990 | \&\-finhibit\-size\-directive \-finstrument\-functions |
| 991 | \&\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,... |
| 992 | \&\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,... |
| 993 | \&\-fno\-common \-fno\-ident |
| 994 | \&\-fpcc\-struct\-return \-fpic \-fPIC \-fpie \-fPIE |
| 995 | \&\-fno\-jump\-tables |
| 996 | \&\-frecord\-gcc\-switches |
| 997 | \&\-freg\-struct\-return \-fshort\-enums |
| 998 | \&\-fshort\-double \-fshort\-wchar |
| 999 | \&\-fverbose\-asm \-fpack\-struct[=\fR\fIn\fR\fB] \-fstack\-check |
| 1000 | \&\-fstack\-limit\-register=\fR\fIreg\fR \fB\-fstack\-limit\-symbol=\fR\fIsym\fR |
| 1001 | \&\fB\-fno\-stack\-limit \-fsplit\-stack |
| 1002 | \&\-fleading\-underscore \-ftls\-model=\fR\fImodel\fR |
| 1003 | \&\fB\-ftrapv \-fwrapv \-fbounds\-check |
| 1004 | \&\-fvisibility \-fstrict\-volatile\-bitfields\fR |
| 1005 | .Sh "Options Controlling the Kind of Output" |
| 1006 | .IX Subsection "Options Controlling the Kind of Output" |
| 1007 | Compilation can involve up to four stages: preprocessing, compilation |
| 1008 | proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of |
| 1009 | preprocessing and compiling several files either into several |
| 1010 | assembler input files, or into one assembler input file; then each |
| 1011 | assembler input file produces an object file, and linking combines all |
| 1012 | the object files (those newly compiled, and those specified as input) |
| 1013 | into an executable file. |
| 1014 | .PP |
| 1015 | For any given input file, the file name suffix determines what kind of |
| 1016 | compilation is done: |
| 1017 | .IP "\fIfile\fR\fB.c\fR" 4 |
| 1018 | .IX Item "file.c" |
| 1019 | C source code that must be preprocessed. |
| 1020 | .IP "\fIfile\fR\fB.i\fR" 4 |
| 1021 | .IX Item "file.i" |
| 1022 | C source code that should not be preprocessed. |
| 1023 | .IP "\fIfile\fR\fB.ii\fR" 4 |
| 1024 | .IX Item "file.ii" |
| 1025 | \&\*(C+ source code that should not be preprocessed. |
| 1026 | .IP "\fIfile\fR\fB.m\fR" 4 |
| 1027 | .IX Item "file.m" |
| 1028 | Objective-C source code. Note that you must link with the \fIlibobjc\fR |
| 1029 | library to make an Objective-C program work. |
| 1030 | .IP "\fIfile\fR\fB.mi\fR" 4 |
| 1031 | .IX Item "file.mi" |
| 1032 | Objective-C source code that should not be preprocessed. |
| 1033 | .IP "\fIfile\fR\fB.mm\fR" 4 |
| 1034 | .IX Item "file.mm" |
| 1035 | .PD 0 |
| 1036 | .IP "\fIfile\fR\fB.M\fR" 4 |
| 1037 | .IX Item "file.M" |
| 1038 | .PD |
| 1039 | Objective\-\*(C+ source code. Note that you must link with the \fIlibobjc\fR |
| 1040 | library to make an Objective\-\*(C+ program work. Note that \fB.M\fR refers |
| 1041 | to a literal capital M. |
| 1042 | .IP "\fIfile\fR\fB.mii\fR" 4 |
| 1043 | .IX Item "file.mii" |
| 1044 | Objective\-\*(C+ source code that should not be preprocessed. |
| 1045 | .IP "\fIfile\fR\fB.h\fR" 4 |
| 1046 | .IX Item "file.h" |
| 1047 | C, \*(C+, Objective-C or Objective\-\*(C+ header file to be turned into a |
| 1048 | precompiled header (default), or C, \*(C+ header file to be turned into an |
| 1049 | Ada spec (via the \fB\-fdump\-ada\-spec\fR switch). |
| 1050 | .IP "\fIfile\fR\fB.cc\fR" 4 |
| 1051 | .IX Item "file.cc" |
| 1052 | .PD 0 |
| 1053 | .IP "\fIfile\fR\fB.cp\fR" 4 |
| 1054 | .IX Item "file.cp" |
| 1055 | .IP "\fIfile\fR\fB.cxx\fR" 4 |
| 1056 | .IX Item "file.cxx" |
| 1057 | .IP "\fIfile\fR\fB.cpp\fR" 4 |
| 1058 | .IX Item "file.cpp" |
| 1059 | .IP "\fIfile\fR\fB.CPP\fR" 4 |
| 1060 | .IX Item "file.CPP" |
| 1061 | .IP "\fIfile\fR\fB.c++\fR" 4 |
| 1062 | .IX Item "file.c++" |
| 1063 | .IP "\fIfile\fR\fB.C\fR" 4 |
| 1064 | .IX Item "file.C" |
| 1065 | .PD |
| 1066 | \&\*(C+ source code that must be preprocessed. Note that in \fB.cxx\fR, |
| 1067 | the last two letters must both be literally \fBx\fR. Likewise, |
| 1068 | \&\fB.C\fR refers to a literal capital C. |
| 1069 | .IP "\fIfile\fR\fB.mm\fR" 4 |
| 1070 | .IX Item "file.mm" |
| 1071 | .PD 0 |
| 1072 | .IP "\fIfile\fR\fB.M\fR" 4 |
| 1073 | .IX Item "file.M" |
| 1074 | .PD |
| 1075 | Objective\-\*(C+ source code that must be preprocessed. |
| 1076 | .IP "\fIfile\fR\fB.mii\fR" 4 |
| 1077 | .IX Item "file.mii" |
| 1078 | Objective\-\*(C+ source code that should not be preprocessed. |
| 1079 | .IP "\fIfile\fR\fB.hh\fR" 4 |
| 1080 | .IX Item "file.hh" |
| 1081 | .PD 0 |
| 1082 | .IP "\fIfile\fR\fB.H\fR" 4 |
| 1083 | .IX Item "file.H" |
| 1084 | .IP "\fIfile\fR\fB.hp\fR" 4 |
| 1085 | .IX Item "file.hp" |
| 1086 | .IP "\fIfile\fR\fB.hxx\fR" 4 |
| 1087 | .IX Item "file.hxx" |
| 1088 | .IP "\fIfile\fR\fB.hpp\fR" 4 |
| 1089 | .IX Item "file.hpp" |
| 1090 | .IP "\fIfile\fR\fB.HPP\fR" 4 |
| 1091 | .IX Item "file.HPP" |
| 1092 | .IP "\fIfile\fR\fB.h++\fR" 4 |
| 1093 | .IX Item "file.h++" |
| 1094 | .IP "\fIfile\fR\fB.tcc\fR" 4 |
| 1095 | .IX Item "file.tcc" |
| 1096 | .PD |
| 1097 | \&\*(C+ header file to be turned into a precompiled header or Ada spec. |
| 1098 | .IP "\fIfile\fR\fB.f\fR" 4 |
| 1099 | .IX Item "file.f" |
| 1100 | .PD 0 |
| 1101 | .IP "\fIfile\fR\fB.for\fR" 4 |
| 1102 | .IX Item "file.for" |
| 1103 | .IP "\fIfile\fR\fB.ftn\fR" 4 |
| 1104 | .IX Item "file.ftn" |
| 1105 | .PD |
| 1106 | Fixed form Fortran source code that should not be preprocessed. |
| 1107 | .IP "\fIfile\fR\fB.F\fR" 4 |
| 1108 | .IX Item "file.F" |
| 1109 | .PD 0 |
| 1110 | .IP "\fIfile\fR\fB.FOR\fR" 4 |
| 1111 | .IX Item "file.FOR" |
| 1112 | .IP "\fIfile\fR\fB.fpp\fR" 4 |
| 1113 | .IX Item "file.fpp" |
| 1114 | .IP "\fIfile\fR\fB.FPP\fR" 4 |
| 1115 | .IX Item "file.FPP" |
| 1116 | .IP "\fIfile\fR\fB.FTN\fR" 4 |
| 1117 | .IX Item "file.FTN" |
| 1118 | .PD |
| 1119 | Fixed form Fortran source code that must be preprocessed (with the traditional |
| 1120 | preprocessor). |
| 1121 | .IP "\fIfile\fR\fB.f90\fR" 4 |
| 1122 | .IX Item "file.f90" |
| 1123 | .PD 0 |
| 1124 | .IP "\fIfile\fR\fB.f95\fR" 4 |
| 1125 | .IX Item "file.f95" |
| 1126 | .IP "\fIfile\fR\fB.f03\fR" 4 |
| 1127 | .IX Item "file.f03" |
| 1128 | .IP "\fIfile\fR\fB.f08\fR" 4 |
| 1129 | .IX Item "file.f08" |
| 1130 | .PD |
| 1131 | Free form Fortran source code that should not be preprocessed. |
| 1132 | .IP "\fIfile\fR\fB.F90\fR" 4 |
| 1133 | .IX Item "file.F90" |
| 1134 | .PD 0 |
| 1135 | .IP "\fIfile\fR\fB.F95\fR" 4 |
| 1136 | .IX Item "file.F95" |
| 1137 | .IP "\fIfile\fR\fB.F03\fR" 4 |
| 1138 | .IX Item "file.F03" |
| 1139 | .IP "\fIfile\fR\fB.F08\fR" 4 |
| 1140 | .IX Item "file.F08" |
| 1141 | .PD |
| 1142 | Free form Fortran source code that must be preprocessed (with the |
| 1143 | traditional preprocessor). |
| 1144 | .IP "\fIfile\fR\fB.go\fR" 4 |
| 1145 | .IX Item "file.go" |
| 1146 | Go source code. |
| 1147 | .IP "\fIfile\fR\fB.ads\fR" 4 |
| 1148 | .IX Item "file.ads" |
| 1149 | Ada source code file that contains a library unit declaration (a |
| 1150 | declaration of a package, subprogram, or generic, or a generic |
| 1151 | instantiation), or a library unit renaming declaration (a package, |
| 1152 | generic, or subprogram renaming declaration). Such files are also |
| 1153 | called \fIspecs\fR. |
| 1154 | .IP "\fIfile\fR\fB.adb\fR" 4 |
| 1155 | .IX Item "file.adb" |
| 1156 | Ada source code file containing a library unit body (a subprogram or |
| 1157 | package body). Such files are also called \fIbodies\fR. |
| 1158 | .IP "\fIfile\fR\fB.s\fR" 4 |
| 1159 | .IX Item "file.s" |
| 1160 | Assembler code. |
| 1161 | .IP "\fIfile\fR\fB.S\fR" 4 |
| 1162 | .IX Item "file.S" |
| 1163 | .PD 0 |
| 1164 | .IP "\fIfile\fR\fB.sx\fR" 4 |
| 1165 | .IX Item "file.sx" |
| 1166 | .PD |
| 1167 | Assembler code that must be preprocessed. |
| 1168 | .IP "\fIother\fR" 4 |
| 1169 | .IX Item "other" |
| 1170 | An object file to be fed straight into linking. |
| 1171 | Any file name with no recognized suffix is treated this way. |
| 1172 | .PP |
| 1173 | You can specify the input language explicitly with the \fB\-x\fR option: |
| 1174 | .IP "\fB\-x\fR \fIlanguage\fR" 4 |
| 1175 | .IX Item "-x language" |
| 1176 | Specify explicitly the \fIlanguage\fR for the following input files |
| 1177 | (rather than letting the compiler choose a default based on the file |
| 1178 | name suffix). This option applies to all following input files until |
| 1179 | the next \fB\-x\fR option. Possible values for \fIlanguage\fR are: |
| 1180 | .Sp |
| 1181 | .Vb 9 |
| 1182 | \& c c\-header cpp\-output |
| 1183 | \& c++ c++\-header c++\-cpp\-output |
| 1184 | \& objective\-c objective\-c\-header objective\-c\-cpp\-output |
| 1185 | \& objective\-c++ objective\-c++\-header objective\-c++\-cpp\-output |
| 1186 | \& assembler assembler\-with\-cpp |
| 1187 | \& ada |
| 1188 | \& f77 f77\-cpp\-input f95 f95\-cpp\-input |
| 1189 | \& go |
| 1190 | \& java |
| 1191 | .Ve |
| 1192 | .IP "\fB\-x none\fR" 4 |
| 1193 | .IX Item "-x none" |
| 1194 | Turn off any specification of a language, so that subsequent files are |
| 1195 | handled according to their file name suffixes (as they are if \fB\-x\fR |
| 1196 | has not been used at all). |
| 1197 | .IP "\fB\-pass\-exit\-codes\fR" 4 |
| 1198 | .IX Item "-pass-exit-codes" |
| 1199 | Normally the \fBgcc\fR program will exit with the code of 1 if any |
| 1200 | phase of the compiler returns a non-success return code. If you specify |
| 1201 | \&\fB\-pass\-exit\-codes\fR, the \fBgcc\fR program will instead return with |
| 1202 | numerically highest error produced by any phase that returned an error |
| 1203 | indication. The C, \*(C+, and Fortran frontends return 4, if an internal |
| 1204 | compiler error is encountered. |
| 1205 | .PP |
| 1206 | If you only want some of the stages of compilation, you can use |
| 1207 | \&\fB\-x\fR (or filename suffixes) to tell \fBgcc\fR where to start, and |
| 1208 | one of the options \fB\-c\fR, \fB\-S\fR, or \fB\-E\fR to say where |
| 1209 | \&\fBgcc\fR is to stop. Note that some combinations (for example, |
| 1210 | \&\fB\-x cpp-output \-E\fR) instruct \fBgcc\fR to do nothing at all. |
| 1211 | .IP "\fB\-c\fR" 4 |
| 1212 | .IX Item "-c" |
| 1213 | Compile or assemble the source files, but do not link. The linking |
| 1214 | stage simply is not done. The ultimate output is in the form of an |
| 1215 | object file for each source file. |
| 1216 | .Sp |
| 1217 | By default, the object file name for a source file is made by replacing |
| 1218 | the suffix \fB.c\fR, \fB.i\fR, \fB.s\fR, etc., with \fB.o\fR. |
| 1219 | .Sp |
| 1220 | Unrecognized input files, not requiring compilation or assembly, are |
| 1221 | ignored. |
| 1222 | .IP "\fB\-S\fR" 4 |
| 1223 | .IX Item "-S" |
| 1224 | Stop after the stage of compilation proper; do not assemble. The output |
| 1225 | is in the form of an assembler code file for each non-assembler input |
| 1226 | file specified. |
| 1227 | .Sp |
| 1228 | By default, the assembler file name for a source file is made by |
| 1229 | replacing the suffix \fB.c\fR, \fB.i\fR, etc., with \fB.s\fR. |
| 1230 | .Sp |
| 1231 | Input files that don't require compilation are ignored. |
| 1232 | .IP "\fB\-E\fR" 4 |
| 1233 | .IX Item "-E" |
| 1234 | Stop after the preprocessing stage; do not run the compiler proper. The |
| 1235 | output is in the form of preprocessed source code, which is sent to the |
| 1236 | standard output. |
| 1237 | .Sp |
| 1238 | Input files that don't require preprocessing are ignored. |
| 1239 | .IP "\fB\-o\fR \fIfile\fR" 4 |
| 1240 | .IX Item "-o file" |
| 1241 | Place output in file \fIfile\fR. This applies regardless to whatever |
| 1242 | sort of output is being produced, whether it be an executable file, |
| 1243 | an object file, an assembler file or preprocessed C code. |
| 1244 | .Sp |
| 1245 | If \fB\-o\fR is not specified, the default is to put an executable |
| 1246 | file in \fIa.out\fR, the object file for |
| 1247 | \&\fI\fIsource\fI.\fIsuffix\fI\fR in \fI\fIsource\fI.o\fR, its |
| 1248 | assembler file in \fI\fIsource\fI.s\fR, a precompiled header file in |
| 1249 | \&\fI\fIsource\fI.\fIsuffix\fI.gch\fR, and all preprocessed C source on |
| 1250 | standard output. |
| 1251 | .IP "\fB\-v\fR" 4 |
| 1252 | .IX Item "-v" |
| 1253 | Print (on standard error output) the commands executed to run the stages |
| 1254 | of compilation. Also print the version number of the compiler driver |
| 1255 | program and of the preprocessor and the compiler proper. |
| 1256 | .IP "\fB\-###\fR" 4 |
| 1257 | .IX Item "-###" |
| 1258 | Like \fB\-v\fR except the commands are not executed and arguments |
| 1259 | are quoted unless they contain only alphanumeric characters or \f(CW\*(C`./\-_\*(C'\fR. |
| 1260 | This is useful for shell scripts to capture the driver-generated command lines. |
| 1261 | .IP "\fB\-pipe\fR" 4 |
| 1262 | .IX Item "-pipe" |
| 1263 | Use pipes rather than temporary files for communication between the |
| 1264 | various stages of compilation. This fails to work on some systems where |
| 1265 | the assembler is unable to read from a pipe; but the \s-1GNU\s0 assembler has |
| 1266 | no trouble. |
| 1267 | .IP "\fB\-\-help\fR" 4 |
| 1268 | .IX Item "--help" |
| 1269 | Print (on the standard output) a description of the command-line options |
| 1270 | understood by \fBgcc\fR. If the \fB\-v\fR option is also specified |
| 1271 | then \fB\-\-help\fR will also be passed on to the various processes |
| 1272 | invoked by \fBgcc\fR, so that they can display the command-line options |
| 1273 | they accept. If the \fB\-Wextra\fR option has also been specified |
| 1274 | (prior to the \fB\-\-help\fR option), then command-line options that |
| 1275 | have no documentation associated with them will also be displayed. |
| 1276 | .IP "\fB\-\-target\-help\fR" 4 |
| 1277 | .IX Item "--target-help" |
| 1278 | Print (on the standard output) a description of target-specific command-line |
| 1279 | options for each tool. For some targets extra target-specific |
| 1280 | information may also be printed. |
| 1281 | .IP "\fB\-\-help={\fR\fIclass\fR|[\fB^\fR]\fIqualifier\fR\fB}\fR[\fB,...\fR]" 4 |
| 1282 | .IX Item "--help={class|[^]qualifier}[,...]" |
| 1283 | Print (on the standard output) a description of the command-line |
| 1284 | options understood by the compiler that fit into all specified classes |
| 1285 | and qualifiers. These are the supported classes: |
| 1286 | .RS 4 |
| 1287 | .IP "\fBoptimizers\fR" 4 |
| 1288 | .IX Item "optimizers" |
| 1289 | This will display all of the optimization options supported by the |
| 1290 | compiler. |
| 1291 | .IP "\fBwarnings\fR" 4 |
| 1292 | .IX Item "warnings" |
| 1293 | This will display all of the options controlling warning messages |
| 1294 | produced by the compiler. |
| 1295 | .IP "\fBtarget\fR" 4 |
| 1296 | .IX Item "target" |
| 1297 | This will display target-specific options. Unlike the |
| 1298 | \&\fB\-\-target\-help\fR option however, target-specific options of the |
| 1299 | linker and assembler will not be displayed. This is because those |
| 1300 | tools do not currently support the extended \fB\-\-help=\fR syntax. |
| 1301 | .IP "\fBparams\fR" 4 |
| 1302 | .IX Item "params" |
| 1303 | This will display the values recognized by the \fB\-\-param\fR |
| 1304 | option. |
| 1305 | .IP "\fIlanguage\fR" 4 |
| 1306 | .IX Item "language" |
| 1307 | This will display the options supported for \fIlanguage\fR, where |
| 1308 | \&\fIlanguage\fR is the name of one of the languages supported in this |
| 1309 | version of \s-1GCC\s0. |
| 1310 | .IP "\fBcommon\fR" 4 |
| 1311 | .IX Item "common" |
| 1312 | This will display the options that are common to all languages. |
| 1313 | .RE |
| 1314 | .RS 4 |
| 1315 | .Sp |
| 1316 | These are the supported qualifiers: |
| 1317 | .IP "\fBundocumented\fR" 4 |
| 1318 | .IX Item "undocumented" |
| 1319 | Display only those options that are undocumented. |
| 1320 | .IP "\fBjoined\fR" 4 |
| 1321 | .IX Item "joined" |
| 1322 | Display options taking an argument that appears after an equal |
| 1323 | sign in the same continuous piece of text, such as: |
| 1324 | \&\fB\-\-help=target\fR. |
| 1325 | .IP "\fBseparate\fR" 4 |
| 1326 | .IX Item "separate" |
| 1327 | Display options taking an argument that appears as a separate word |
| 1328 | following the original option, such as: \fB\-o output-file\fR. |
| 1329 | .RE |
| 1330 | .RS 4 |
| 1331 | .Sp |
| 1332 | Thus for example to display all the undocumented target-specific |
| 1333 | switches supported by the compiler the following can be used: |
| 1334 | .Sp |
| 1335 | .Vb 1 |
| 1336 | \& \-\-help=target,undocumented |
| 1337 | .Ve |
| 1338 | .Sp |
| 1339 | The sense of a qualifier can be inverted by prefixing it with the |
| 1340 | \&\fB^\fR character, so for example to display all binary warning |
| 1341 | options (i.e., ones that are either on or off and that do not take an |
| 1342 | argument) that have a description, use: |
| 1343 | .Sp |
| 1344 | .Vb 1 |
| 1345 | \& \-\-help=warnings,^joined,^undocumented |
| 1346 | .Ve |
| 1347 | .Sp |
| 1348 | The argument to \fB\-\-help=\fR should not consist solely of inverted |
| 1349 | qualifiers. |
| 1350 | .Sp |
| 1351 | Combining several classes is possible, although this usually |
| 1352 | restricts the output by so much that there is nothing to display. One |
| 1353 | case where it does work however is when one of the classes is |
| 1354 | \&\fItarget\fR. So for example to display all the target-specific |
| 1355 | optimization options the following can be used: |
| 1356 | .Sp |
| 1357 | .Vb 1 |
| 1358 | \& \-\-help=target,optimizers |
| 1359 | .Ve |
| 1360 | .Sp |
| 1361 | The \fB\-\-help=\fR option can be repeated on the command line. Each |
| 1362 | successive use will display its requested class of options, skipping |
| 1363 | those that have already been displayed. |
| 1364 | .Sp |
| 1365 | If the \fB\-Q\fR option appears on the command line before the |
| 1366 | \&\fB\-\-help=\fR option, then the descriptive text displayed by |
| 1367 | \&\fB\-\-help=\fR is changed. Instead of describing the displayed |
| 1368 | options, an indication is given as to whether the option is enabled, |
| 1369 | disabled or set to a specific value (assuming that the compiler |
| 1370 | knows this at the point where the \fB\-\-help=\fR option is used). |
| 1371 | .Sp |
| 1372 | Here is a truncated example from the \s-1ARM\s0 port of \fBgcc\fR: |
| 1373 | .Sp |
| 1374 | .Vb 5 |
| 1375 | \& % gcc \-Q \-mabi=2 \-\-help=target \-c |
| 1376 | \& The following options are target specific: |
| 1377 | \& \-mabi= 2 |
| 1378 | \& \-mabort\-on\-noreturn [disabled] |
| 1379 | \& \-mapcs [disabled] |
| 1380 | .Ve |
| 1381 | .Sp |
| 1382 | The output is sensitive to the effects of previous command-line |
| 1383 | options, so for example it is possible to find out which optimizations |
| 1384 | are enabled at \fB\-O2\fR by using: |
| 1385 | .Sp |
| 1386 | .Vb 1 |
| 1387 | \& \-Q \-O2 \-\-help=optimizers |
| 1388 | .Ve |
| 1389 | .Sp |
| 1390 | Alternatively you can discover which binary optimizations are enabled |
| 1391 | by \fB\-O3\fR by using: |
| 1392 | .Sp |
| 1393 | .Vb 3 |
| 1394 | \& gcc \-c \-Q \-O3 \-\-help=optimizers > /tmp/O3\-opts |
| 1395 | \& gcc \-c \-Q \-O2 \-\-help=optimizers > /tmp/O2\-opts |
| 1396 | \& diff /tmp/O2\-opts /tmp/O3\-opts | grep enabled |
| 1397 | .Ve |
| 1398 | .RE |
| 1399 | .IP "\fB\-no\-canonical\-prefixes\fR" 4 |
| 1400 | .IX Item "-no-canonical-prefixes" |
| 1401 | Do not expand any symbolic links, resolve references to \fB/../\fR |
| 1402 | or \fB/./\fR, or make the path absolute when generating a relative |
| 1403 | prefix. |
| 1404 | .IP "\fB\-\-version\fR" 4 |
| 1405 | .IX Item "--version" |
| 1406 | Display the version number and copyrights of the invoked \s-1GCC\s0. |
| 1407 | .IP "\fB\-wrapper\fR" 4 |
| 1408 | .IX Item "-wrapper" |
| 1409 | Invoke all subcommands under a wrapper program. The name of the |
| 1410 | wrapper program and its parameters are passed as a comma separated |
| 1411 | list. |
| 1412 | .Sp |
| 1413 | .Vb 1 |
| 1414 | \& gcc \-c t.c \-wrapper gdb,\-\-args |
| 1415 | .Ve |
| 1416 | .Sp |
| 1417 | This will invoke all subprograms of \fBgcc\fR under |
| 1418 | \&\fBgdb \-\-args\fR, thus the invocation of \fBcc1\fR will be |
| 1419 | \&\fBgdb \-\-args cc1 ...\fR. |
| 1420 | .IP "\fB\-fplugin=\fR\fIname\fR\fB.so\fR" 4 |
| 1421 | .IX Item "-fplugin=name.so" |
| 1422 | Load the plugin code in file \fIname\fR.so, assumed to be a |
| 1423 | shared object to be dlopen'd by the compiler. The base name of |
| 1424 | the shared object file is used to identify the plugin for the |
| 1425 | purposes of argument parsing (See |
| 1426 | \&\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR below). |
| 1427 | Each plugin should define the callback functions specified in the |
| 1428 | Plugins \s-1API\s0. |
| 1429 | .IP "\fB\-fplugin\-arg\-\fR\fIname\fR\fB\-\fR\fIkey\fR\fB=\fR\fIvalue\fR" 4 |
| 1430 | .IX Item "-fplugin-arg-name-key=value" |
| 1431 | Define an argument called \fIkey\fR with a value of \fIvalue\fR |
| 1432 | for the plugin called \fIname\fR. |
| 1433 | .IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 |
| 1434 | .IX Item "-fdump-ada-spec[-slim]" |
| 1435 | For C and \*(C+ source and include files, generate corresponding Ada specs. |
| 1436 | .IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 |
| 1437 | .IX Item "-fdump-go-spec=file" |
| 1438 | For input files in any language, generate corresponding Go |
| 1439 | declarations in \fIfile\fR. This generates Go \f(CW\*(C`const\*(C'\fR, |
| 1440 | \&\f(CW\*(C`type\*(C'\fR, \f(CW\*(C`var\*(C'\fR, and \f(CW\*(C`func\*(C'\fR declarations which may be a |
| 1441 | useful way to start writing a Go interface to code written in some |
| 1442 | other language. |
| 1443 | .IP "\fB@\fR\fIfile\fR" 4 |
| 1444 | .IX Item "@file" |
| 1445 | Read command-line options from \fIfile\fR. The options read are |
| 1446 | inserted in place of the original @\fIfile\fR option. If \fIfile\fR |
| 1447 | does not exist, or cannot be read, then the option will be treated |
| 1448 | literally, and not removed. |
| 1449 | .Sp |
| 1450 | Options in \fIfile\fR are separated by whitespace. A whitespace |
| 1451 | character may be included in an option by surrounding the entire |
| 1452 | option in either single or double quotes. Any character (including a |
| 1453 | backslash) may be included by prefixing the character to be included |
| 1454 | with a backslash. The \fIfile\fR may itself contain additional |
| 1455 | @\fIfile\fR options; any such options will be processed recursively. |
| 1456 | .Sh "Compiling \*(C+ Programs" |
| 1457 | .IX Subsection "Compiling Programs" |
| 1458 | \&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, |
| 1459 | \&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or |
| 1460 | \&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, |
| 1461 | \&\fB.H\fR, or (for shared template code) \fB.tcc\fR; and |
| 1462 | preprocessed \*(C+ files use the suffix \fB.ii\fR. \s-1GCC\s0 recognizes |
| 1463 | files with these names and compiles them as \*(C+ programs even if you |
| 1464 | call the compiler the same way as for compiling C programs (usually |
| 1465 | with the name \fBgcc\fR). |
| 1466 | .PP |
| 1467 | However, the use of \fBgcc\fR does not add the \*(C+ library. |
| 1468 | \&\fBg++\fR is a program that calls \s-1GCC\s0 and treats \fB.c\fR, |
| 1469 | \&\fB.h\fR and \fB.i\fR files as \*(C+ source files instead of C source |
| 1470 | files unless \fB\-x\fR is used, and automatically specifies linking |
| 1471 | against the \*(C+ library. This program is also useful when |
| 1472 | precompiling a C header file with a \fB.h\fR extension for use in \*(C+ |
| 1473 | compilations. On many systems, \fBg++\fR is also installed with |
| 1474 | the name \fBc++\fR. |
| 1475 | .PP |
| 1476 | When you compile \*(C+ programs, you may specify many of the same |
| 1477 | command-line options that you use for compiling programs in any |
| 1478 | language; or command-line options meaningful for C and related |
| 1479 | languages; or options that are meaningful only for \*(C+ programs. |
| 1480 | .Sh "Options Controlling C Dialect" |
| 1481 | .IX Subsection "Options Controlling C Dialect" |
| 1482 | The following options control the dialect of C (or languages derived |
| 1483 | from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler |
| 1484 | accepts: |
| 1485 | .IP "\fB\-ansi\fR" 4 |
| 1486 | .IX Item "-ansi" |
| 1487 | In C mode, this is equivalent to \fB\-std=c90\fR. In \*(C+ mode, it is |
| 1488 | equivalent to \fB\-std=c++98\fR. |
| 1489 | .Sp |
| 1490 | This turns off certain features of \s-1GCC\s0 that are incompatible with \s-1ISO\s0 |
| 1491 | C90 (when compiling C code), or of standard \*(C+ (when compiling \*(C+ code), |
| 1492 | such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, and |
| 1493 | predefined macros such as \f(CW\*(C`unix\*(C'\fR and \f(CW\*(C`vax\*(C'\fR that identify the |
| 1494 | type of system you are using. It also enables the undesirable and |
| 1495 | rarely used \s-1ISO\s0 trigraph feature. For the C compiler, |
| 1496 | it disables recognition of \*(C+ style \fB//\fR comments as well as |
| 1497 | the \f(CW\*(C`inline\*(C'\fR keyword. |
| 1498 | .Sp |
| 1499 | The alternate keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_extension_\|_\*(C'\fR, |
| 1500 | \&\f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR continue to work despite |
| 1501 | \&\fB\-ansi\fR. You would not want to use them in an \s-1ISO\s0 C program, of |
| 1502 | course, but it is useful to put them in header files that might be included |
| 1503 | in compilations done with \fB\-ansi\fR. Alternate predefined macros |
| 1504 | such as \f(CW\*(C`_\|_unix_\|_\*(C'\fR and \f(CW\*(C`_\|_vax_\|_\*(C'\fR are also available, with or |
| 1505 | without \fB\-ansi\fR. |
| 1506 | .Sp |
| 1507 | The \fB\-ansi\fR option does not cause non-ISO programs to be |
| 1508 | rejected gratuitously. For that, \fB\-pedantic\fR is required in |
| 1509 | addition to \fB\-ansi\fR. |
| 1510 | .Sp |
| 1511 | The macro \f(CW\*(C`_\|_STRICT_ANSI_\|_\*(C'\fR is predefined when the \fB\-ansi\fR |
| 1512 | option is used. Some header files may notice this macro and refrain |
| 1513 | from declaring certain functions or defining certain macros that the |
| 1514 | \&\s-1ISO\s0 standard doesn't call for; this is to avoid interfering with any |
| 1515 | programs that might use these names for other things. |
| 1516 | .Sp |
| 1517 | Functions that would normally be built in but do not have semantics |
| 1518 | defined by \s-1ISO\s0 C (such as \f(CW\*(C`alloca\*(C'\fR and \f(CW\*(C`ffs\*(C'\fR) are not built-in |
| 1519 | functions when \fB\-ansi\fR is used. |
| 1520 | .IP "\fB\-std=\fR" 4 |
| 1521 | .IX Item "-std=" |
| 1522 | Determine the language standard. This option |
| 1523 | is currently only supported when compiling C or \*(C+. |
| 1524 | .Sp |
| 1525 | The compiler can accept several base standards, such as \fBc90\fR or |
| 1526 | \&\fBc++98\fR, and \s-1GNU\s0 dialects of those standards, such as |
| 1527 | \&\fBgnu90\fR or \fBgnu++98\fR. By specifying a base standard, the |
| 1528 | compiler will accept all programs following that standard and those |
| 1529 | using \s-1GNU\s0 extensions that do not contradict it. For example, |
| 1530 | \&\fB\-std=c90\fR turns off certain features of \s-1GCC\s0 that are |
| 1531 | incompatible with \s-1ISO\s0 C90, such as the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR |
| 1532 | keywords, but not other \s-1GNU\s0 extensions that do not have a meaning in |
| 1533 | \&\s-1ISO\s0 C90, such as omitting the middle term of a \f(CW\*(C`?:\*(C'\fR |
| 1534 | expression. On the other hand, by specifying a \s-1GNU\s0 dialect of a |
| 1535 | standard, all features the compiler support are enabled, even when |
| 1536 | those features change the meaning of the base standard and some |
| 1537 | strict-conforming programs may be rejected. The particular standard |
| 1538 | is used by \fB\-pedantic\fR to identify which features are \s-1GNU\s0 |
| 1539 | extensions given that version of the standard. For example |
| 1540 | \&\fB\-std=gnu90 \-pedantic\fR would warn about \*(C+ style \fB//\fR |
| 1541 | comments, while \fB\-std=gnu99 \-pedantic\fR would not. |
| 1542 | .Sp |
| 1543 | A value for this option must be provided; possible values are |
| 1544 | .RS 4 |
| 1545 | .IP "\fBc90\fR" 4 |
| 1546 | .IX Item "c90" |
| 1547 | .PD 0 |
| 1548 | .IP "\fBc89\fR" 4 |
| 1549 | .IX Item "c89" |
| 1550 | .IP "\fBiso9899:1990\fR" 4 |
| 1551 | .IX Item "iso9899:1990" |
| 1552 | .PD |
| 1553 | Support all \s-1ISO\s0 C90 programs (certain \s-1GNU\s0 extensions that conflict |
| 1554 | with \s-1ISO\s0 C90 are disabled). Same as \fB\-ansi\fR for C code. |
| 1555 | .IP "\fBiso9899:199409\fR" 4 |
| 1556 | .IX Item "iso9899:199409" |
| 1557 | \&\s-1ISO\s0 C90 as modified in amendment 1. |
| 1558 | .IP "\fBc99\fR" 4 |
| 1559 | .IX Item "c99" |
| 1560 | .PD 0 |
| 1561 | .IP "\fBc9x\fR" 4 |
| 1562 | .IX Item "c9x" |
| 1563 | .IP "\fBiso9899:1999\fR" 4 |
| 1564 | .IX Item "iso9899:1999" |
| 1565 | .IP "\fBiso9899:199x\fR" 4 |
| 1566 | .IX Item "iso9899:199x" |
| 1567 | .PD |
| 1568 | \&\s-1ISO\s0 C99. Note that this standard is not yet fully supported; see |
| 1569 | <\fBhttp://gcc.gnu.org/gcc\-4.7/c99status.html\fR> for more information. The |
| 1570 | names \fBc9x\fR and \fBiso9899:199x\fR are deprecated. |
| 1571 | .IP "\fBc11\fR" 4 |
| 1572 | .IX Item "c11" |
| 1573 | .PD 0 |
| 1574 | .IP "\fBc1x\fR" 4 |
| 1575 | .IX Item "c1x" |
| 1576 | .IP "\fBiso9899:2011\fR" 4 |
| 1577 | .IX Item "iso9899:2011" |
| 1578 | .PD |
| 1579 | \&\s-1ISO\s0 C11, the 2011 revision of the \s-1ISO\s0 C standard. |
| 1580 | Support is incomplete and experimental. The name \fBc1x\fR is |
| 1581 | deprecated. |
| 1582 | .IP "\fBgnu90\fR" 4 |
| 1583 | .IX Item "gnu90" |
| 1584 | .PD 0 |
| 1585 | .IP "\fBgnu89\fR" 4 |
| 1586 | .IX Item "gnu89" |
| 1587 | .PD |
| 1588 | \&\s-1GNU\s0 dialect of \s-1ISO\s0 C90 (including some C99 features). This |
| 1589 | is the default for C code. |
| 1590 | .IP "\fBgnu99\fR" 4 |
| 1591 | .IX Item "gnu99" |
| 1592 | .PD 0 |
| 1593 | .IP "\fBgnu9x\fR" 4 |
| 1594 | .IX Item "gnu9x" |
| 1595 | .PD |
| 1596 | \&\s-1GNU\s0 dialect of \s-1ISO\s0 C99. When \s-1ISO\s0 C99 is fully implemented in \s-1GCC\s0, |
| 1597 | this will become the default. The name \fBgnu9x\fR is deprecated. |
| 1598 | .IP "\fBgnu11\fR" 4 |
| 1599 | .IX Item "gnu11" |
| 1600 | .PD 0 |
| 1601 | .IP "\fBgnu1x\fR" 4 |
| 1602 | .IX Item "gnu1x" |
| 1603 | .PD |
| 1604 | \&\s-1GNU\s0 dialect of \s-1ISO\s0 C11. Support is incomplete and experimental. The |
| 1605 | name \fBgnu1x\fR is deprecated. |
| 1606 | .IP "\fBc++98\fR" 4 |
| 1607 | .IX Item "c++98" |
| 1608 | The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. Same as \fB\-ansi\fR for |
| 1609 | \&\*(C+ code. |
| 1610 | .IP "\fBgnu++98\fR" 4 |
| 1611 | .IX Item "gnu++98" |
| 1612 | \&\s-1GNU\s0 dialect of \fB\-std=c++98\fR. This is the default for |
| 1613 | \&\*(C+ code. |
| 1614 | .IP "\fBc++11\fR" 4 |
| 1615 | .IX Item "c++11" |
| 1616 | The 2011 \s-1ISO\s0 \*(C+ standard plus amendments. Support for \*(C+11 is still |
| 1617 | experimental, and may change in incompatible ways in future releases. |
| 1618 | .IP "\fBgnu++11\fR" 4 |
| 1619 | .IX Item "gnu++11" |
| 1620 | \&\s-1GNU\s0 dialect of \fB\-std=c++11\fR. Support for \*(C+11 is still |
| 1621 | experimental, and may change in incompatible ways in future releases. |
| 1622 | .RE |
| 1623 | .RS 4 |
| 1624 | .RE |
| 1625 | .IP "\fB\-fgnu89\-inline\fR" 4 |
| 1626 | .IX Item "-fgnu89-inline" |
| 1627 | The option \fB\-fgnu89\-inline\fR tells \s-1GCC\s0 to use the traditional |
| 1628 | \&\s-1GNU\s0 semantics for \f(CW\*(C`inline\*(C'\fR functions when in C99 mode. |
| 1629 | This option |
| 1630 | is accepted and ignored by \s-1GCC\s0 versions 4.1.3 up to but not including |
| 1631 | 4.3. In \s-1GCC\s0 versions 4.3 and later it changes the behavior of \s-1GCC\s0 in |
| 1632 | C99 mode. Using this option is roughly equivalent to adding the |
| 1633 | \&\f(CW\*(C`gnu_inline\*(C'\fR function attribute to all inline functions. |
| 1634 | .Sp |
| 1635 | The option \fB\-fno\-gnu89\-inline\fR explicitly tells \s-1GCC\s0 to use the |
| 1636 | C99 semantics for \f(CW\*(C`inline\*(C'\fR when in C99 or gnu99 mode (i.e., it |
| 1637 | specifies the default behavior). This option was first supported in |
| 1638 | \&\s-1GCC\s0 4.3. This option is not supported in \fB\-std=c90\fR or |
| 1639 | \&\fB\-std=gnu90\fR mode. |
| 1640 | .Sp |
| 1641 | The preprocessor macros \f(CW\*(C`_\|_GNUC_GNU_INLINE_\|_\*(C'\fR and |
| 1642 | \&\f(CW\*(C`_\|_GNUC_STDC_INLINE_\|_\*(C'\fR may be used to check which semantics are |
| 1643 | in effect for \f(CW\*(C`inline\*(C'\fR functions. |
| 1644 | .IP "\fB\-aux\-info\fR \fIfilename\fR" 4 |
| 1645 | .IX Item "-aux-info filename" |
| 1646 | Output to the given filename prototyped declarations for all functions |
| 1647 | declared and/or defined in a translation unit, including those in header |
| 1648 | files. This option is silently ignored in any language other than C. |
| 1649 | .Sp |
| 1650 | Besides declarations, the file indicates, in comments, the origin of |
| 1651 | each declaration (source file and line), whether the declaration was |
| 1652 | implicit, prototyped or unprototyped (\fBI\fR, \fBN\fR for new or |
| 1653 | \&\fBO\fR for old, respectively, in the first character after the line |
| 1654 | number and the colon), and whether it came from a declaration or a |
| 1655 | definition (\fBC\fR or \fBF\fR, respectively, in the following |
| 1656 | character). In the case of function definitions, a K&R\-style list of |
| 1657 | arguments followed by their declarations is also provided, inside |
| 1658 | comments, after the declaration. |
| 1659 | .IP "\fB\-fallow\-parameterless\-variadic\-functions\fR" 4 |
| 1660 | .IX Item "-fallow-parameterless-variadic-functions" |
| 1661 | Accept variadic functions without named parameters. |
| 1662 | .Sp |
| 1663 | Although it is possible to define such a function, this is not very |
| 1664 | useful as it is not possible to read the arguments. This is only |
| 1665 | supported for C as this construct is allowed by \*(C+. |
| 1666 | .IP "\fB\-fno\-asm\fR" 4 |
| 1667 | .IX Item "-fno-asm" |
| 1668 | Do not recognize \f(CW\*(C`asm\*(C'\fR, \f(CW\*(C`inline\*(C'\fR or \f(CW\*(C`typeof\*(C'\fR as a |
| 1669 | keyword, so that code can use these words as identifiers. You can use |
| 1670 | the keywords \f(CW\*(C`_\|_asm_\|_\*(C'\fR, \f(CW\*(C`_\|_inline_\|_\*(C'\fR and \f(CW\*(C`_\|_typeof_\|_\*(C'\fR |
| 1671 | instead. \fB\-ansi\fR implies \fB\-fno\-asm\fR. |
| 1672 | .Sp |
| 1673 | In \*(C+, this switch only affects the \f(CW\*(C`typeof\*(C'\fR keyword, since |
| 1674 | \&\f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`inline\*(C'\fR are standard keywords. You may want to |
| 1675 | use the \fB\-fno\-gnu\-keywords\fR flag instead, which has the same |
| 1676 | effect. In C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this |
| 1677 | switch only affects the \f(CW\*(C`asm\*(C'\fR and \f(CW\*(C`typeof\*(C'\fR keywords, since |
| 1678 | \&\f(CW\*(C`inline\*(C'\fR is a standard keyword in \s-1ISO\s0 C99. |
| 1679 | .IP "\fB\-fno\-builtin\fR" 4 |
| 1680 | .IX Item "-fno-builtin" |
| 1681 | .PD 0 |
| 1682 | .IP "\fB\-fno\-builtin\-\fR\fIfunction\fR" 4 |
| 1683 | .IX Item "-fno-builtin-function" |
| 1684 | .PD |
| 1685 | Don't recognize built-in functions that do not begin with |
| 1686 | \&\fB_\|_builtin_\fR as prefix. |
| 1687 | .Sp |
| 1688 | \&\s-1GCC\s0 normally generates special code to handle certain built-in functions |
| 1689 | more efficiently; for instance, calls to \f(CW\*(C`alloca\*(C'\fR may become single |
| 1690 | instructions which adjust the stack directly, and calls to \f(CW\*(C`memcpy\*(C'\fR |
| 1691 | may become inline copy loops. The resulting code is often both smaller |
| 1692 | and faster, but since the function calls no longer appear as such, you |
| 1693 | cannot set a breakpoint on those calls, nor can you change the behavior |
| 1694 | of the functions by linking with a different library. In addition, |
| 1695 | when a function is recognized as a built-in function, \s-1GCC\s0 may use |
| 1696 | information about that function to warn about problems with calls to |
| 1697 | that function, or to generate more efficient code, even if the |
| 1698 | resulting code still contains calls to that function. For example, |
| 1699 | warnings are given with \fB\-Wformat\fR for bad calls to |
| 1700 | \&\f(CW\*(C`printf\*(C'\fR, when \f(CW\*(C`printf\*(C'\fR is built in, and \f(CW\*(C`strlen\*(C'\fR is |
| 1701 | known not to modify global memory. |
| 1702 | .Sp |
| 1703 | With the \fB\-fno\-builtin\-\fR\fIfunction\fR option |
| 1704 | only the built-in function \fIfunction\fR is |
| 1705 | disabled. \fIfunction\fR must not begin with \fB_\|_builtin_\fR. If a |
| 1706 | function is named that is not built-in in this version of \s-1GCC\s0, this |
| 1707 | option is ignored. There is no corresponding |
| 1708 | \&\fB\-fbuiltin\-\fR\fIfunction\fR option; if you wish to enable |
| 1709 | built-in functions selectively when using \fB\-fno\-builtin\fR or |
| 1710 | \&\fB\-ffreestanding\fR, you may define macros such as: |
| 1711 | .Sp |
| 1712 | .Vb 2 |
| 1713 | \& #define abs(n) _\|_builtin_abs ((n)) |
| 1714 | \& #define strcpy(d, s) _\|_builtin_strcpy ((d), (s)) |
| 1715 | .Ve |
| 1716 | .IP "\fB\-fhosted\fR" 4 |
| 1717 | .IX Item "-fhosted" |
| 1718 | Assert that compilation takes place in a hosted environment. This implies |
| 1719 | \&\fB\-fbuiltin\fR. A hosted environment is one in which the |
| 1720 | entire standard library is available, and in which \f(CW\*(C`main\*(C'\fR has a return |
| 1721 | type of \f(CW\*(C`int\*(C'\fR. Examples are nearly everything except a kernel. |
| 1722 | This is equivalent to \fB\-fno\-freestanding\fR. |
| 1723 | .IP "\fB\-ffreestanding\fR" 4 |
| 1724 | .IX Item "-ffreestanding" |
| 1725 | Assert that compilation takes place in a freestanding environment. This |
| 1726 | implies \fB\-fno\-builtin\fR. A freestanding environment |
| 1727 | is one in which the standard library may not exist, and program startup may |
| 1728 | not necessarily be at \f(CW\*(C`main\*(C'\fR. The most obvious example is an \s-1OS\s0 kernel. |
| 1729 | This is equivalent to \fB\-fno\-hosted\fR. |
| 1730 | .IP "\fB\-fopenmp\fR" 4 |
| 1731 | .IX Item "-fopenmp" |
| 1732 | Enable handling of OpenMP directives \f(CW\*(C`#pragma omp\*(C'\fR in C/\*(C+ and |
| 1733 | \&\f(CW\*(C`!$omp\*(C'\fR in Fortran. When \fB\-fopenmp\fR is specified, the |
| 1734 | compiler generates parallel code according to the OpenMP Application |
| 1735 | Program Interface v3.0 <\fBhttp://www.openmp.org/\fR>. This option |
| 1736 | implies \fB\-pthread\fR, and thus is only supported on targets that |
| 1737 | have support for \fB\-pthread\fR. |
| 1738 | .IP "\fB\-fgnu\-tm\fR" 4 |
| 1739 | .IX Item "-fgnu-tm" |
| 1740 | When the option \fB\-fgnu\-tm\fR is specified, the compiler will |
| 1741 | generate code for the Linux variant of Intel's current Transactional |
| 1742 | Memory \s-1ABI\s0 specification document (Revision 1.1, May 6 2009). This is |
| 1743 | an experimental feature whose interface may change in future versions |
| 1744 | of \s-1GCC\s0, as the official specification changes. Please note that not |
| 1745 | all architectures are supported for this feature. |
| 1746 | .Sp |
| 1747 | For more information on \s-1GCC\s0's support for transactional memory, |
| 1748 | .Sp |
| 1749 | Note that the transactional memory feature is not supported with |
| 1750 | non-call exceptions (\fB\-fnon\-call\-exceptions\fR). |
| 1751 | .IP "\fB\-fms\-extensions\fR" 4 |
| 1752 | .IX Item "-fms-extensions" |
| 1753 | Accept some non-standard constructs used in Microsoft header files. |
| 1754 | .Sp |
| 1755 | In \*(C+ code, this allows member names in structures to be similar |
| 1756 | to previous types declarations. |
| 1757 | .Sp |
| 1758 | .Vb 4 |
| 1759 | \& typedef int UOW; |
| 1760 | \& struct ABC { |
| 1761 | \& UOW UOW; |
| 1762 | \& }; |
| 1763 | .Ve |
| 1764 | .Sp |
| 1765 | Some cases of unnamed fields in structures and unions are only |
| 1766 | accepted with this option. |
| 1767 | .IP "\fB\-fplan9\-extensions\fR" 4 |
| 1768 | .IX Item "-fplan9-extensions" |
| 1769 | Accept some non-standard constructs used in Plan 9 code. |
| 1770 | .Sp |
| 1771 | This enables \fB\-fms\-extensions\fR, permits passing pointers to |
| 1772 | structures with anonymous fields to functions that expect pointers to |
| 1773 | elements of the type of the field, and permits referring to anonymous |
| 1774 | fields declared using a typedef. This is only |
| 1775 | supported for C, not \*(C+. |
| 1776 | .IP "\fB\-trigraphs\fR" 4 |
| 1777 | .IX Item "-trigraphs" |
| 1778 | Support \s-1ISO\s0 C trigraphs. The \fB\-ansi\fR option (and \fB\-std\fR |
| 1779 | options for strict \s-1ISO\s0 C conformance) implies \fB\-trigraphs\fR. |
| 1780 | .IP "\fB\-no\-integrated\-cpp\fR" 4 |
| 1781 | .IX Item "-no-integrated-cpp" |
| 1782 | Performs a compilation in two passes: preprocessing and compiling. This |
| 1783 | option allows a user supplied \*(L"cc1\*(R", \*(L"cc1plus\*(R", or \*(L"cc1obj\*(R" via the |
| 1784 | \&\fB\-B\fR option. The user supplied compilation step can then add in |
| 1785 | an additional preprocessing step after normal preprocessing but before |
| 1786 | compiling. The default is to use the integrated cpp (internal cpp) |
| 1787 | .Sp |
| 1788 | The semantics of this option will change if \*(L"cc1\*(R", \*(L"cc1plus\*(R", and |
| 1789 | \&\*(L"cc1obj\*(R" are merged. |
| 1790 | .IP "\fB\-traditional\fR" 4 |
| 1791 | .IX Item "-traditional" |
| 1792 | .PD 0 |
| 1793 | .IP "\fB\-traditional\-cpp\fR" 4 |
| 1794 | .IX Item "-traditional-cpp" |
| 1795 | .PD |
| 1796 | Formerly, these options caused \s-1GCC\s0 to attempt to emulate a pre-standard |
| 1797 | C compiler. They are now only supported with the \fB\-E\fR switch. |
| 1798 | The preprocessor continues to support a pre-standard mode. See the \s-1GNU\s0 |
| 1799 | \&\s-1CPP\s0 manual for details. |
| 1800 | .IP "\fB\-fcond\-mismatch\fR" 4 |
| 1801 | .IX Item "-fcond-mismatch" |
| 1802 | Allow conditional expressions with mismatched types in the second and |
| 1803 | third arguments. The value of such an expression is void. This option |
| 1804 | is not supported for \*(C+. |
| 1805 | .IP "\fB\-flax\-vector\-conversions\fR" 4 |
| 1806 | .IX Item "-flax-vector-conversions" |
| 1807 | Allow implicit conversions between vectors with differing numbers of |
| 1808 | elements and/or incompatible element types. This option should not be |
| 1809 | used for new code. |
| 1810 | .IP "\fB\-funsigned\-char\fR" 4 |
| 1811 | .IX Item "-funsigned-char" |
| 1812 | Let the type \f(CW\*(C`char\*(C'\fR be unsigned, like \f(CW\*(C`unsigned char\*(C'\fR. |
| 1813 | .Sp |
| 1814 | Each kind of machine has a default for what \f(CW\*(C`char\*(C'\fR should |
| 1815 | be. It is either like \f(CW\*(C`unsigned char\*(C'\fR by default or like |
| 1816 | \&\f(CW\*(C`signed char\*(C'\fR by default. |
| 1817 | .Sp |
| 1818 | Ideally, a portable program should always use \f(CW\*(C`signed char\*(C'\fR or |
| 1819 | \&\f(CW\*(C`unsigned char\*(C'\fR when it depends on the signedness of an object. |
| 1820 | But many programs have been written to use plain \f(CW\*(C`char\*(C'\fR and |
| 1821 | expect it to be signed, or expect it to be unsigned, depending on the |
| 1822 | machines they were written for. This option, and its inverse, let you |
| 1823 | make such a program work with the opposite default. |
| 1824 | .Sp |
| 1825 | The type \f(CW\*(C`char\*(C'\fR is always a distinct type from each of |
| 1826 | \&\f(CW\*(C`signed char\*(C'\fR or \f(CW\*(C`unsigned char\*(C'\fR, even though its behavior |
| 1827 | is always just like one of those two. |
| 1828 | .IP "\fB\-fsigned\-char\fR" 4 |
| 1829 | .IX Item "-fsigned-char" |
| 1830 | Let the type \f(CW\*(C`char\*(C'\fR be signed, like \f(CW\*(C`signed char\*(C'\fR. |
| 1831 | .Sp |
| 1832 | Note that this is equivalent to \fB\-fno\-unsigned\-char\fR, which is |
| 1833 | the negative form of \fB\-funsigned\-char\fR. Likewise, the option |
| 1834 | \&\fB\-fno\-signed\-char\fR is equivalent to \fB\-funsigned\-char\fR. |
| 1835 | .IP "\fB\-fsigned\-bitfields\fR" 4 |
| 1836 | .IX Item "-fsigned-bitfields" |
| 1837 | .PD 0 |
| 1838 | .IP "\fB\-funsigned\-bitfields\fR" 4 |
| 1839 | .IX Item "-funsigned-bitfields" |
| 1840 | .IP "\fB\-fno\-signed\-bitfields\fR" 4 |
| 1841 | .IX Item "-fno-signed-bitfields" |
| 1842 | .IP "\fB\-fno\-unsigned\-bitfields\fR" 4 |
| 1843 | .IX Item "-fno-unsigned-bitfields" |
| 1844 | .PD |
| 1845 | These options control whether a bit-field is signed or unsigned, when the |
| 1846 | declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By |
| 1847 | default, such a bit-field is signed, because this is consistent: the |
| 1848 | basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. |
| 1849 | .Sh "Options Controlling \*(C+ Dialect" |
| 1850 | .IX Subsection "Options Controlling Dialect" |
| 1851 | This section describes the command-line options that are only meaningful |
| 1852 | for \*(C+ programs; but you can also use most of the \s-1GNU\s0 compiler options |
| 1853 | regardless of what language your program is in. For example, you |
| 1854 | might compile a file \f(CW\*(C`firstClass.C\*(C'\fR like this: |
| 1855 | .PP |
| 1856 | .Vb 1 |
| 1857 | \& g++ \-g \-frepo \-O \-c firstClass.C |
| 1858 | .Ve |
| 1859 | .PP |
| 1860 | In this example, only \fB\-frepo\fR is an option meant |
| 1861 | only for \*(C+ programs; you can use the other options with any |
| 1862 | language supported by \s-1GCC\s0. |
| 1863 | .PP |
| 1864 | Here is a list of options that are \fIonly\fR for compiling \*(C+ programs: |
| 1865 | .IP "\fB\-fabi\-version=\fR\fIn\fR" 4 |
| 1866 | .IX Item "-fabi-version=n" |
| 1867 | Use version \fIn\fR of the \*(C+ \s-1ABI\s0. Version 2 is the version of the |
| 1868 | \&\*(C+ \s-1ABI\s0 that first appeared in G++ 3.4. Version 1 is the version of |
| 1869 | the \*(C+ \s-1ABI\s0 that first appeared in G++ 3.2. Version 0 will always be |
| 1870 | the version that conforms most closely to the \*(C+ \s-1ABI\s0 specification. |
| 1871 | Therefore, the \s-1ABI\s0 obtained using version 0 will change as \s-1ABI\s0 bugs |
| 1872 | are fixed. |
| 1873 | .Sp |
| 1874 | The default is version 2. |
| 1875 | .Sp |
| 1876 | Version 3 corrects an error in mangling a constant address as a |
| 1877 | template argument. |
| 1878 | .Sp |
| 1879 | Version 4, which first appeared in G++ 4.5, implements a standard |
| 1880 | mangling for vector types. |
| 1881 | .Sp |
| 1882 | Version 5, which first appeared in G++ 4.6, corrects the mangling of |
| 1883 | attribute const/volatile on function pointer types, decltype of a |
| 1884 | plain decl, and use of a function parameter in the declaration of |
| 1885 | another parameter. |
| 1886 | .Sp |
| 1887 | Version 6, which first appeared in G++ 4.7, corrects the promotion |
| 1888 | behavior of \*(C+11 scoped enums and the mangling of template argument |
| 1889 | packs, const/static_cast, prefix ++ and \-\-, and a class scope function |
| 1890 | used as a template argument. |
| 1891 | .Sp |
| 1892 | See also \fB\-Wabi\fR. |
| 1893 | .IP "\fB\-fno\-access\-control\fR" 4 |
| 1894 | .IX Item "-fno-access-control" |
| 1895 | Turn off all access checking. This switch is mainly useful for working |
| 1896 | around bugs in the access control code. |
| 1897 | .IP "\fB\-fcheck\-new\fR" 4 |
| 1898 | .IX Item "-fcheck-new" |
| 1899 | Check that the pointer returned by \f(CW\*(C`operator new\*(C'\fR is non-null |
| 1900 | before attempting to modify the storage allocated. This check is |
| 1901 | normally unnecessary because the \*(C+ standard specifies that |
| 1902 | \&\f(CW\*(C`operator new\*(C'\fR will only return \f(CW0\fR if it is declared |
| 1903 | \&\fB\f(BIthrow()\fB\fR, in which case the compiler will always check the |
| 1904 | return value even without this option. In all other cases, when |
| 1905 | \&\f(CW\*(C`operator new\*(C'\fR has a non-empty exception specification, memory |
| 1906 | exhaustion is signalled by throwing \f(CW\*(C`std::bad_alloc\*(C'\fR. See also |
| 1907 | \&\fBnew (nothrow)\fR. |
| 1908 | .IP "\fB\-fconserve\-space\fR" 4 |
| 1909 | .IX Item "-fconserve-space" |
| 1910 | Put uninitialized or run-time-initialized global variables into the |
| 1911 | common segment, as C does. This saves space in the executable at the |
| 1912 | cost of not diagnosing duplicate definitions. If you compile with this |
| 1913 | flag and your program mysteriously crashes after \f(CW\*(C`main()\*(C'\fR has |
| 1914 | completed, you may have an object that is being destroyed twice because |
| 1915 | two definitions were merged. |
| 1916 | .Sp |
| 1917 | This option is no longer useful on most targets, now that support has |
| 1918 | been added for putting variables into \s-1BSS\s0 without making them common. |
| 1919 | .IP "\fB\-fconstexpr\-depth=\fR\fIn\fR" 4 |
| 1920 | .IX Item "-fconstexpr-depth=n" |
| 1921 | Set the maximum nested evaluation depth for \*(C+11 constexpr functions |
| 1922 | to \fIn\fR. A limit is needed to detect endless recursion during |
| 1923 | constant expression evaluation. The minimum specified by the standard |
| 1924 | is 512. |
| 1925 | .IP "\fB\-fdeduce\-init\-list\fR" 4 |
| 1926 | .IX Item "-fdeduce-init-list" |
| 1927 | Enable deduction of a template type parameter as |
| 1928 | std::initializer_list from a brace-enclosed initializer list, i.e. |
| 1929 | .Sp |
| 1930 | .Vb 4 |
| 1931 | \& template <class T> auto forward(T t) \-> decltype (realfn (t)) |
| 1932 | \& { |
| 1933 | \& return realfn (t); |
| 1934 | \& } |
| 1935 | \& |
| 1936 | \& void f() |
| 1937 | \& { |
| 1938 | \& forward({1,2}); // call forward<std::initializer_list<int>> |
| 1939 | \& } |
| 1940 | .Ve |
| 1941 | .Sp |
| 1942 | This deduction was implemented as a possible extension to the |
| 1943 | originally proposed semantics for the \*(C+11 standard, but was not part |
| 1944 | of the final standard, so it is disabled by default. This option is |
| 1945 | deprecated, and may be removed in a future version of G++. |
| 1946 | .IP "\fB\-ffriend\-injection\fR" 4 |
| 1947 | .IX Item "-ffriend-injection" |
| 1948 | Inject friend functions into the enclosing namespace, so that they are |
| 1949 | visible outside the scope of the class in which they are declared. |
| 1950 | Friend functions were documented to work this way in the old Annotated |
| 1951 | \&\*(C+ Reference Manual, and versions of G++ before 4.1 always worked |
| 1952 | that way. However, in \s-1ISO\s0 \*(C+ a friend function that is not declared |
| 1953 | in an enclosing scope can only be found using argument dependent |
| 1954 | lookup. This option causes friends to be injected as they were in |
| 1955 | earlier releases. |
| 1956 | .Sp |
| 1957 | This option is for compatibility, and may be removed in a future |
| 1958 | release of G++. |
| 1959 | .IP "\fB\-fno\-elide\-constructors\fR" 4 |
| 1960 | .IX Item "-fno-elide-constructors" |
| 1961 | The \*(C+ standard allows an implementation to omit creating a temporary |
| 1962 | that is only used to initialize another object of the same type. |
| 1963 | Specifying this option disables that optimization, and forces G++ to |
| 1964 | call the copy constructor in all cases. |
| 1965 | .IP "\fB\-fno\-enforce\-eh\-specs\fR" 4 |
| 1966 | .IX Item "-fno-enforce-eh-specs" |
| 1967 | Don't generate code to check for violation of exception specifications |
| 1968 | at run time. This option violates the \*(C+ standard, but may be useful |
| 1969 | for reducing code size in production builds, much like defining |
| 1970 | \&\fB\s-1NDEBUG\s0\fR. This does not give user code permission to throw |
| 1971 | exceptions in violation of the exception specifications; the compiler |
| 1972 | will still optimize based on the specifications, so throwing an |
| 1973 | unexpected exception will result in undefined behavior. |
| 1974 | .IP "\fB\-ffor\-scope\fR" 4 |
| 1975 | .IX Item "-ffor-scope" |
| 1976 | .PD 0 |
| 1977 | .IP "\fB\-fno\-for\-scope\fR" 4 |
| 1978 | .IX Item "-fno-for-scope" |
| 1979 | .PD |
| 1980 | If \fB\-ffor\-scope\fR is specified, the scope of variables declared in |
| 1981 | a \fIfor-init-statement\fR is limited to the \fBfor\fR loop itself, |
| 1982 | as specified by the \*(C+ standard. |
| 1983 | If \fB\-fno\-for\-scope\fR is specified, the scope of variables declared in |
| 1984 | a \fIfor-init-statement\fR extends to the end of the enclosing scope, |
| 1985 | as was the case in old versions of G++, and other (traditional) |
| 1986 | implementations of \*(C+. |
| 1987 | .Sp |
| 1988 | The default if neither flag is given to follow the standard, |
| 1989 | but to allow and give a warning for old-style code that would |
| 1990 | otherwise be invalid, or have different behavior. |
| 1991 | .IP "\fB\-fno\-gnu\-keywords\fR" 4 |
| 1992 | .IX Item "-fno-gnu-keywords" |
| 1993 | Do not recognize \f(CW\*(C`typeof\*(C'\fR as a keyword, so that code can use this |
| 1994 | word as an identifier. You can use the keyword \f(CW\*(C`_\|_typeof_\|_\*(C'\fR instead. |
| 1995 | \&\fB\-ansi\fR implies \fB\-fno\-gnu\-keywords\fR. |
| 1996 | .IP "\fB\-fno\-implicit\-templates\fR" 4 |
| 1997 | .IX Item "-fno-implicit-templates" |
| 1998 | Never emit code for non-inline templates that are instantiated |
| 1999 | implicitly (i.e. by use); only emit code for explicit instantiations. |
| 2000 | .IP "\fB\-fno\-implicit\-inline\-templates\fR" 4 |
| 2001 | .IX Item "-fno-implicit-inline-templates" |
| 2002 | Don't emit code for implicit instantiations of inline templates, either. |
| 2003 | The default is to handle inlines differently so that compiles with and |
| 2004 | without optimization will need the same set of explicit instantiations. |
| 2005 | .IP "\fB\-fno\-implement\-inlines\fR" 4 |
| 2006 | .IX Item "-fno-implement-inlines" |
| 2007 | To save space, do not emit out-of-line copies of inline functions |
| 2008 | controlled by \fB#pragma implementation\fR. This will cause linker |
| 2009 | errors if these functions are not inlined everywhere they are called. |
| 2010 | .IP "\fB\-fms\-extensions\fR" 4 |
| 2011 | .IX Item "-fms-extensions" |
| 2012 | Disable pedantic warnings about constructs used in \s-1MFC\s0, such as implicit |
| 2013 | int and getting a pointer to member function via non-standard syntax. |
| 2014 | .IP "\fB\-fno\-nonansi\-builtins\fR" 4 |
| 2015 | .IX Item "-fno-nonansi-builtins" |
| 2016 | Disable built-in declarations of functions that are not mandated by |
| 2017 | \&\s-1ANSI/ISO\s0 C. These include \f(CW\*(C`ffs\*(C'\fR, \f(CW\*(C`alloca\*(C'\fR, \f(CW\*(C`_exit\*(C'\fR, |
| 2018 | \&\f(CW\*(C`index\*(C'\fR, \f(CW\*(C`bzero\*(C'\fR, \f(CW\*(C`conjf\*(C'\fR, and other related functions. |
| 2019 | .IP "\fB\-fnothrow\-opt\fR" 4 |
| 2020 | .IX Item "-fnothrow-opt" |
| 2021 | Treat a \f(CW\*(C`throw()\*(C'\fR exception specification as though it were a |
| 2022 | \&\f(CW\*(C`noexcept\*(C'\fR specification to reduce or eliminate the text size |
| 2023 | overhead relative to a function with no exception specification. If |
| 2024 | the function has local variables of types with non-trivial |
| 2025 | destructors, the exception specification will actually make the |
| 2026 | function smaller because the \s-1EH\s0 cleanups for those variables can be |
| 2027 | optimized away. The semantic effect is that an exception thrown out of |
| 2028 | a function with such an exception specification will result in a call |
| 2029 | to \f(CW\*(C`terminate\*(C'\fR rather than \f(CW\*(C`unexpected\*(C'\fR. |
| 2030 | .IP "\fB\-fno\-operator\-names\fR" 4 |
| 2031 | .IX Item "-fno-operator-names" |
| 2032 | Do not treat the operator name keywords \f(CW\*(C`and\*(C'\fR, \f(CW\*(C`bitand\*(C'\fR, |
| 2033 | \&\f(CW\*(C`bitor\*(C'\fR, \f(CW\*(C`compl\*(C'\fR, \f(CW\*(C`not\*(C'\fR, \f(CW\*(C`or\*(C'\fR and \f(CW\*(C`xor\*(C'\fR as |
| 2034 | synonyms as keywords. |
| 2035 | .IP "\fB\-fno\-optional\-diags\fR" 4 |
| 2036 | .IX Item "-fno-optional-diags" |
| 2037 | Disable diagnostics that the standard says a compiler does not need to |
| 2038 | issue. Currently, the only such diagnostic issued by G++ is the one for |
| 2039 | a name having multiple meanings within a class. |
| 2040 | .IP "\fB\-fpermissive\fR" 4 |
| 2041 | .IX Item "-fpermissive" |
| 2042 | Downgrade some diagnostics about nonconformant code from errors to |
| 2043 | warnings. Thus, using \fB\-fpermissive\fR will allow some |
| 2044 | nonconforming code to compile. |
| 2045 | .IP "\fB\-fno\-pretty\-templates\fR" 4 |
| 2046 | .IX Item "-fno-pretty-templates" |
| 2047 | When an error message refers to a specialization of a function |
| 2048 | template, the compiler will normally print the signature of the |
| 2049 | template followed by the template arguments and any typedefs or |
| 2050 | typenames in the signature (e.g. \f(CW\*(C`void f(T) [with T = int]\*(C'\fR |
| 2051 | rather than \f(CW\*(C`void f(int)\*(C'\fR) so that it's clear which template is |
| 2052 | involved. When an error message refers to a specialization of a class |
| 2053 | template, the compiler will omit any template arguments that match |
| 2054 | the default template arguments for that template. If either of these |
| 2055 | behaviors make it harder to understand the error message rather than |
| 2056 | easier, using \fB\-fno\-pretty\-templates\fR will disable them. |
| 2057 | .IP "\fB\-frepo\fR" 4 |
| 2058 | .IX Item "-frepo" |
| 2059 | Enable automatic template instantiation at link time. This option also |
| 2060 | implies \fB\-fno\-implicit\-templates\fR. |
| 2061 | .IP "\fB\-fno\-rtti\fR" 4 |
| 2062 | .IX Item "-fno-rtti" |
| 2063 | Disable generation of information about every class with virtual |
| 2064 | functions for use by the \*(C+ run-time type identification features |
| 2065 | (\fBdynamic_cast\fR and \fBtypeid\fR). If you don't use those parts |
| 2066 | of the language, you can save some space by using this flag. Note that |
| 2067 | exception handling uses the same information, but it will generate it as |
| 2068 | needed. The \fBdynamic_cast\fR operator can still be used for casts that |
| 2069 | do not require run-time type information, i.e. casts to \f(CW\*(C`void *\*(C'\fR or to |
| 2070 | unambiguous base classes. |
| 2071 | .IP "\fB\-fstats\fR" 4 |
| 2072 | .IX Item "-fstats" |
| 2073 | Emit statistics about front-end processing at the end of the compilation. |
| 2074 | This information is generally only useful to the G++ development team. |
| 2075 | .IP "\fB\-fstrict\-enums\fR" 4 |
| 2076 | .IX Item "-fstrict-enums" |
| 2077 | Allow the compiler to optimize using the assumption that a value of |
| 2078 | enumerated type can only be one of the values of the enumeration (as |
| 2079 | defined in the \*(C+ standard; basically, a value that can be |
| 2080 | represented in the minimum number of bits needed to represent all the |
| 2081 | enumerators). This assumption may not be valid if the program uses a |
| 2082 | cast to convert an arbitrary integer value to the enumerated type. |
| 2083 | .IP "\fB\-ftemplate\-depth=\fR\fIn\fR" 4 |
| 2084 | .IX Item "-ftemplate-depth=n" |
| 2085 | Set the maximum instantiation depth for template classes to \fIn\fR. |
| 2086 | A limit on the template instantiation depth is needed to detect |
| 2087 | endless recursions during template class instantiation. \s-1ANSI/ISO\s0 \*(C+ |
| 2088 | conforming programs must not rely on a maximum depth greater than 17 |
| 2089 | (changed to 1024 in \*(C+11). The default value is 900, as the compiler |
| 2090 | can run out of stack space before hitting 1024 in some situations. |
| 2091 | .IP "\fB\-fno\-threadsafe\-statics\fR" 4 |
| 2092 | .IX Item "-fno-threadsafe-statics" |
| 2093 | Do not emit the extra code to use the routines specified in the \*(C+ |
| 2094 | \&\s-1ABI\s0 for thread-safe initialization of local statics. You can use this |
| 2095 | option to reduce code size slightly in code that doesn't need to be |
| 2096 | thread-safe. |
| 2097 | .IP "\fB\-fuse\-cxa\-atexit\fR" 4 |
| 2098 | .IX Item "-fuse-cxa-atexit" |
| 2099 | Register destructors for objects with static storage duration with the |
| 2100 | \&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR function rather than the \f(CW\*(C`atexit\*(C'\fR function. |
| 2101 | This option is required for fully standards-compliant handling of static |
| 2102 | destructors, but will only work if your C library supports |
| 2103 | \&\f(CW\*(C`_\|_cxa_atexit\*(C'\fR. |
| 2104 | .IP "\fB\-fno\-use\-cxa\-get\-exception\-ptr\fR" 4 |
| 2105 | .IX Item "-fno-use-cxa-get-exception-ptr" |
| 2106 | Don't use the \f(CW\*(C`_\|_cxa_get_exception_ptr\*(C'\fR runtime routine. This |
| 2107 | will cause \f(CW\*(C`std::uncaught_exception\*(C'\fR to be incorrect, but is necessary |
| 2108 | if the runtime routine is not available. |
| 2109 | .IP "\fB\-fvisibility\-inlines\-hidden\fR" 4 |
| 2110 | .IX Item "-fvisibility-inlines-hidden" |
| 2111 | This switch declares that the user does not attempt to compare |
| 2112 | pointers to inline functions or methods where the addresses of the two functions |
| 2113 | were taken in different shared objects. |
| 2114 | .Sp |
| 2115 | The effect of this is that \s-1GCC\s0 may, effectively, mark inline methods with |
| 2116 | \&\f(CW\*(C`_\|_attribute_\|_ ((visibility ("hidden")))\*(C'\fR so that they do not |
| 2117 | appear in the export table of a \s-1DSO\s0 and do not require a \s-1PLT\s0 indirection |
| 2118 | when used within the \s-1DSO\s0. Enabling this option can have a dramatic effect |
| 2119 | on load and link times of a \s-1DSO\s0 as it massively reduces the size of the |
| 2120 | dynamic export table when the library makes heavy use of templates. |
| 2121 | .Sp |
| 2122 | The behavior of this switch is not quite the same as marking the |
| 2123 | methods as hidden directly, because it does not affect static variables |
| 2124 | local to the function or cause the compiler to deduce that |
| 2125 | the function is defined in only one shared object. |
| 2126 | .Sp |
| 2127 | You may mark a method as having a visibility explicitly to negate the |
| 2128 | effect of the switch for that method. For example, if you do want to |
| 2129 | compare pointers to a particular inline method, you might mark it as |
| 2130 | having default visibility. Marking the enclosing class with explicit |
| 2131 | visibility will have no effect. |
| 2132 | .Sp |
| 2133 | Explicitly instantiated inline methods are unaffected by this option |
| 2134 | as their linkage might otherwise cross a shared library boundary. |
| 2135 | .IP "\fB\-fvisibility\-ms\-compat\fR" 4 |
| 2136 | .IX Item "-fvisibility-ms-compat" |
| 2137 | This flag attempts to use visibility settings to make \s-1GCC\s0's \*(C+ |
| 2138 | linkage model compatible with that of Microsoft Visual Studio. |
| 2139 | .Sp |
| 2140 | The flag makes these changes to \s-1GCC\s0's linkage model: |
| 2141 | .RS 4 |
| 2142 | .IP "1." 4 |
| 2143 | It sets the default visibility to \f(CW\*(C`hidden\*(C'\fR, like |
| 2144 | \&\fB\-fvisibility=hidden\fR. |
| 2145 | .IP "2." 4 |
| 2146 | Types, but not their members, are not hidden by default. |
| 2147 | .IP "3." 4 |
| 2148 | The One Definition Rule is relaxed for types without explicit |
| 2149 | visibility specifications that are defined in more than one different |
| 2150 | shared object: those declarations are permitted if they would have |
| 2151 | been permitted when this option was not used. |
| 2152 | .RE |
| 2153 | .RS 4 |
| 2154 | .Sp |
| 2155 | In new code it is better to use \fB\-fvisibility=hidden\fR and |
| 2156 | export those classes that are intended to be externally visible. |
| 2157 | Unfortunately it is possible for code to rely, perhaps accidentally, |
| 2158 | on the Visual Studio behavior. |
| 2159 | .Sp |
| 2160 | Among the consequences of these changes are that static data members |
| 2161 | of the same type with the same name but defined in different shared |
| 2162 | objects will be different, so changing one will not change the other; |
| 2163 | and that pointers to function members defined in different shared |
| 2164 | objects may not compare equal. When this flag is given, it is a |
| 2165 | violation of the \s-1ODR\s0 to define types with the same name differently. |
| 2166 | .RE |
| 2167 | .IP "\fB\-fno\-weak\fR" 4 |
| 2168 | .IX Item "-fno-weak" |
| 2169 | Do not use weak symbol support, even if it is provided by the linker. |
| 2170 | By default, G++ will use weak symbols if they are available. This |
| 2171 | option exists only for testing, and should not be used by end-users; |
| 2172 | it will result in inferior code and has no benefits. This option may |
| 2173 | be removed in a future release of G++. |
| 2174 | .IP "\fB\-nostdinc++\fR" 4 |
| 2175 | .IX Item "-nostdinc++" |
| 2176 | Do not search for header files in the standard directories specific to |
| 2177 | \&\*(C+, but do still search the other standard directories. (This option |
| 2178 | is used when building the \*(C+ library.) |
| 2179 | .PP |
| 2180 | In addition, these optimization, warning, and code generation options |
| 2181 | have meanings only for \*(C+ programs: |
| 2182 | .IP "\fB\-fno\-default\-inline\fR" 4 |
| 2183 | .IX Item "-fno-default-inline" |
| 2184 | Do not assume \fBinline\fR for functions defined inside a class scope. |
| 2185 | Note that these |
| 2186 | functions will have linkage like inline functions; they just won't be |
| 2187 | inlined by default. |
| 2188 | .IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 |
| 2189 | .IX Item "-Wabi (C, Objective-C, and Objective- only)" |
| 2190 | Warn when G++ generates code that is probably not compatible with the |
| 2191 | vendor-neutral \*(C+ \s-1ABI\s0. Although an effort has been made to warn about |
| 2192 | all such cases, there are probably some cases that are not warned about, |
| 2193 | even though G++ is generating incompatible code. There may also be |
| 2194 | cases where warnings are emitted even though the code that is generated |
| 2195 | will be compatible. |
| 2196 | .Sp |
| 2197 | You should rewrite your code to avoid these warnings if you are |
| 2198 | concerned about the fact that code generated by G++ may not be binary |
| 2199 | compatible with code generated by other compilers. |
| 2200 | .Sp |
| 2201 | The known incompatibilities in \fB\-fabi\-version=2\fR (the default) include: |
| 2202 | .RS 4 |
| 2203 | .IP "\(bu" 4 |
| 2204 | A template with a non-type template parameter of reference type is |
| 2205 | mangled incorrectly: |
| 2206 | .Sp |
| 2207 | .Vb 3 |
| 2208 | \& extern int N; |
| 2209 | \& template <int &> struct S {}; |
| 2210 | \& void n (S<N>) {2} |
| 2211 | .Ve |
| 2212 | .Sp |
| 2213 | This is fixed in \fB\-fabi\-version=3\fR. |
| 2214 | .IP "\(bu" 4 |
| 2215 | \&\s-1SIMD\s0 vector types declared using \f(CW\*(C`_\|_attribute ((vector_size))\*(C'\fR are |
| 2216 | mangled in a non-standard way that does not allow for overloading of |
| 2217 | functions taking vectors of different sizes. |
| 2218 | .Sp |
| 2219 | The mangling is changed in \fB\-fabi\-version=4\fR. |
| 2220 | .RE |
| 2221 | .RS 4 |
| 2222 | .Sp |
| 2223 | The known incompatibilities in \fB\-fabi\-version=1\fR include: |
| 2224 | .IP "\(bu" 4 |
| 2225 | Incorrect handling of tail-padding for bit-fields. G++ may attempt to |
| 2226 | pack data into the same byte as a base class. For example: |
| 2227 | .Sp |
| 2228 | .Vb 2 |
| 2229 | \& struct A { virtual void f(); int f1 : 1; }; |
| 2230 | \& struct B : public A { int f2 : 1; }; |
| 2231 | .Ve |
| 2232 | .Sp |
| 2233 | In this case, G++ will place \f(CW\*(C`B::f2\*(C'\fR into the same byte |
| 2234 | as\f(CW\*(C`A::f1\*(C'\fR; other compilers will not. You can avoid this problem |
| 2235 | by explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of the |
| 2236 | byte size on your platform; that will cause G++ and other compilers to |
| 2237 | layout \f(CW\*(C`B\*(C'\fR identically. |
| 2238 | .IP "\(bu" 4 |
| 2239 | Incorrect handling of tail-padding for virtual bases. G++ does not use |
| 2240 | tail padding when laying out virtual bases. For example: |
| 2241 | .Sp |
| 2242 | .Vb 3 |
| 2243 | \& struct A { virtual void f(); char c1; }; |
| 2244 | \& struct B { B(); char c2; }; |
| 2245 | \& struct C : public A, public virtual B {}; |
| 2246 | .Ve |
| 2247 | .Sp |
| 2248 | In this case, G++ will not place \f(CW\*(C`B\*(C'\fR into the tail-padding for |
| 2249 | \&\f(CW\*(C`A\*(C'\fR; other compilers will. You can avoid this problem by |
| 2250 | explicitly padding \f(CW\*(C`A\*(C'\fR so that its size is a multiple of its |
| 2251 | alignment (ignoring virtual base classes); that will cause G++ and other |
| 2252 | compilers to layout \f(CW\*(C`C\*(C'\fR identically. |
| 2253 | .IP "\(bu" 4 |
| 2254 | Incorrect handling of bit-fields with declared widths greater than that |
| 2255 | of their underlying types, when the bit-fields appear in a union. For |
| 2256 | example: |
| 2257 | .Sp |
| 2258 | .Vb 1 |
| 2259 | \& union U { int i : 4096; }; |
| 2260 | .Ve |
| 2261 | .Sp |
| 2262 | Assuming that an \f(CW\*(C`int\*(C'\fR does not have 4096 bits, G++ will make the |
| 2263 | union too small by the number of bits in an \f(CW\*(C`int\*(C'\fR. |
| 2264 | .IP "\(bu" 4 |
| 2265 | Empty classes can be placed at incorrect offsets. For example: |
| 2266 | .Sp |
| 2267 | .Vb 1 |
| 2268 | \& struct A {}; |
| 2269 | \& |
| 2270 | \& struct B { |
| 2271 | \& A a; |
| 2272 | \& virtual void f (); |
| 2273 | \& }; |
| 2274 | \& |
| 2275 | \& struct C : public B, public A {}; |
| 2276 | .Ve |
| 2277 | .Sp |
| 2278 | G++ will place the \f(CW\*(C`A\*(C'\fR base class of \f(CW\*(C`C\*(C'\fR at a nonzero offset; |
| 2279 | it should be placed at offset zero. G++ mistakenly believes that the |
| 2280 | \&\f(CW\*(C`A\*(C'\fR data member of \f(CW\*(C`B\*(C'\fR is already at offset zero. |
| 2281 | .IP "\(bu" 4 |
| 2282 | Names of template functions whose types involve \f(CW\*(C`typename\*(C'\fR or |
| 2283 | template template parameters can be mangled incorrectly. |
| 2284 | .Sp |
| 2285 | .Vb 2 |
| 2286 | \& template <typename Q> |
| 2287 | \& void f(typename Q::X) {} |
| 2288 | \& |
| 2289 | \& template <template <typename> class Q> |
| 2290 | \& void f(typename Q<int>::X) {} |
| 2291 | .Ve |
| 2292 | .Sp |
| 2293 | Instantiations of these templates may be mangled incorrectly. |
| 2294 | .RE |
| 2295 | .RS 4 |
| 2296 | .Sp |
| 2297 | It also warns psABI related changes. The known psABI changes at this |
| 2298 | point include: |
| 2299 | .IP "\(bu" 4 |
| 2300 | For SYSV/x86\-64, when passing union with long double, it is changed to |
| 2301 | pass in memory as specified in psABI. For example: |
| 2302 | .Sp |
| 2303 | .Vb 4 |
| 2304 | \& union U { |
| 2305 | \& long double ld; |
| 2306 | \& int i; |
| 2307 | \& }; |
| 2308 | .Ve |
| 2309 | .Sp |
| 2310 | \&\f(CW\*(C`union U\*(C'\fR will always be passed in memory. |
| 2311 | .RE |
| 2312 | .RS 4 |
| 2313 | .RE |
| 2314 | .IP "\fB\-Wctor\-dtor\-privacy\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2315 | .IX Item "-Wctor-dtor-privacy ( and Objective- only)" |
| 2316 | Warn when a class seems unusable because all the constructors or |
| 2317 | destructors in that class are private, and it has neither friends nor |
| 2318 | public static member functions. |
| 2319 | .IP "\fB\-Wdelete\-non\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2320 | .IX Item "-Wdelete-non-virtual-dtor ( and Objective- only)" |
| 2321 | Warn when \fBdelete\fR is used to destroy an instance of a class that |
| 2322 | has virtual functions and non-virtual destructor. It is unsafe to delete |
| 2323 | an instance of a derived class through a pointer to a base class if the |
| 2324 | base class does not have a virtual destructor. This warning is enabled |
| 2325 | by \fB\-Wall\fR. |
| 2326 | .IP "\fB\-Wnarrowing\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2327 | .IX Item "-Wnarrowing ( and Objective- only)" |
| 2328 | Warn when a narrowing conversion prohibited by \*(C+11 occurs within |
| 2329 | \&\fB{ }\fR, e.g. |
| 2330 | .Sp |
| 2331 | .Vb 1 |
| 2332 | \& int i = { 2.2 }; // error: narrowing from double to int |
| 2333 | .Ve |
| 2334 | .Sp |
| 2335 | This flag is included in \fB\-Wall\fR and \fB\-Wc++11\-compat\fR. |
| 2336 | .Sp |
| 2337 | With \-std=c++11, \fB\-Wno\-narrowing\fR suppresses the diagnostic |
| 2338 | required by the standard. Note that this does not affect the meaning |
| 2339 | of well-formed code; narrowing conversions are still considered |
| 2340 | ill-formed in \s-1SFINAE\s0 context. |
| 2341 | .IP "\fB\-Wnoexcept\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2342 | .IX Item "-Wnoexcept ( and Objective- only)" |
| 2343 | Warn when a noexcept-expression evaluates to false because of a call |
| 2344 | to a function that does not have a non-throwing exception |
| 2345 | specification (i.e. \fB\f(BIthrow()\fB\fR or \fBnoexcept\fR) but is known by |
| 2346 | the compiler to never throw an exception. |
| 2347 | .IP "\fB\-Wnon\-virtual\-dtor\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2348 | .IX Item "-Wnon-virtual-dtor ( and Objective- only)" |
| 2349 | Warn when a class has virtual functions and accessible non-virtual |
| 2350 | destructor, in which case it would be possible but unsafe to delete |
| 2351 | an instance of a derived class through a pointer to the base class. |
| 2352 | This warning is also enabled if \fB\-Weffc++\fR is specified. |
| 2353 | .IP "\fB\-Wreorder\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2354 | .IX Item "-Wreorder ( and Objective- only)" |
| 2355 | Warn when the order of member initializers given in the code does not |
| 2356 | match the order in which they must be executed. For instance: |
| 2357 | .Sp |
| 2358 | .Vb 5 |
| 2359 | \& struct A { |
| 2360 | \& int i; |
| 2361 | \& int j; |
| 2362 | \& A(): j (0), i (1) { } |
| 2363 | \& }; |
| 2364 | .Ve |
| 2365 | .Sp |
| 2366 | The compiler will rearrange the member initializers for \fBi\fR |
| 2367 | and \fBj\fR to match the declaration order of the members, emitting |
| 2368 | a warning to that effect. This warning is enabled by \fB\-Wall\fR. |
| 2369 | .PP |
| 2370 | The following \fB\-W...\fR options are not affected by \fB\-Wall\fR. |
| 2371 | .IP "\fB\-Weffc++\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2372 | .IX Item "-Weffc++ ( and Objective- only)" |
| 2373 | Warn about violations of the following style guidelines from Scott Meyers' |
| 2374 | \&\fIEffective \*(C+, Second Edition\fR book: |
| 2375 | .RS 4 |
| 2376 | .IP "\(bu" 4 |
| 2377 | Item 11: Define a copy constructor and an assignment operator for classes |
| 2378 | with dynamically allocated memory. |
| 2379 | .IP "\(bu" 4 |
| 2380 | Item 12: Prefer initialization to assignment in constructors. |
| 2381 | .IP "\(bu" 4 |
| 2382 | Item 14: Make destructors virtual in base classes. |
| 2383 | .IP "\(bu" 4 |
| 2384 | Item 15: Have \f(CW\*(C`operator=\*(C'\fR return a reference to \f(CW*this\fR. |
| 2385 | .IP "\(bu" 4 |
| 2386 | Item 23: Don't try to return a reference when you must return an object. |
| 2387 | .RE |
| 2388 | .RS 4 |
| 2389 | .Sp |
| 2390 | Also warn about violations of the following style guidelines from |
| 2391 | Scott Meyers' \fIMore Effective \*(C+\fR book: |
| 2392 | .IP "\(bu" 4 |
| 2393 | Item 6: Distinguish between prefix and postfix forms of increment and |
| 2394 | decrement operators. |
| 2395 | .IP "\(bu" 4 |
| 2396 | Item 7: Never overload \f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, or \f(CW\*(C`,\*(C'\fR. |
| 2397 | .RE |
| 2398 | .RS 4 |
| 2399 | .Sp |
| 2400 | When selecting this option, be aware that the standard library |
| 2401 | headers do not obey all of these guidelines; use \fBgrep \-v\fR |
| 2402 | to filter out those warnings. |
| 2403 | .RE |
| 2404 | .IP "\fB\-Wstrict\-null\-sentinel\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2405 | .IX Item "-Wstrict-null-sentinel ( and Objective- only)" |
| 2406 | Warn also about the use of an uncasted \f(CW\*(C`NULL\*(C'\fR as sentinel. When |
| 2407 | compiling only with \s-1GCC\s0 this is a valid sentinel, as \f(CW\*(C`NULL\*(C'\fR is defined |
| 2408 | to \f(CW\*(C`_\|_null\*(C'\fR. Although it is a null pointer constant not a null pointer, |
| 2409 | it is guaranteed to be of the same size as a pointer. But this use is |
| 2410 | not portable across different compilers. |
| 2411 | .IP "\fB\-Wno\-non\-template\-friend\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2412 | .IX Item "-Wno-non-template-friend ( and Objective- only)" |
| 2413 | Disable warnings when non-templatized friend functions are declared |
| 2414 | within a template. Since the advent of explicit template specification |
| 2415 | support in G++, if the name of the friend is an unqualified-id (i.e., |
| 2416 | \&\fBfriend foo(int)\fR), the \*(C+ language specification demands that the |
| 2417 | friend declare or define an ordinary, nontemplate function. (Section |
| 2418 | 14.5.3). Before G++ implemented explicit specification, unqualified-ids |
| 2419 | could be interpreted as a particular specialization of a templatized |
| 2420 | function. Because this non-conforming behavior is no longer the default |
| 2421 | behavior for G++, \fB\-Wnon\-template\-friend\fR allows the compiler to |
| 2422 | check existing code for potential trouble spots and is on by default. |
| 2423 | This new compiler behavior can be turned off with |
| 2424 | \&\fB\-Wno\-non\-template\-friend\fR, which keeps the conformant compiler code |
| 2425 | but disables the helpful warning. |
| 2426 | .IP "\fB\-Wold\-style\-cast\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2427 | .IX Item "-Wold-style-cast ( and Objective- only)" |
| 2428 | Warn if an old-style (C\-style) cast to a non-void type is used within |
| 2429 | a \*(C+ program. The new-style casts (\fBdynamic_cast\fR, |
| 2430 | \&\fBstatic_cast\fR, \fBreinterpret_cast\fR, and \fBconst_cast\fR) are |
| 2431 | less vulnerable to unintended effects and much easier to search for. |
| 2432 | .IP "\fB\-Woverloaded\-virtual\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2433 | .IX Item "-Woverloaded-virtual ( and Objective- only)" |
| 2434 | Warn when a function declaration hides virtual functions from a |
| 2435 | base class. For example, in: |
| 2436 | .Sp |
| 2437 | .Vb 3 |
| 2438 | \& struct A { |
| 2439 | \& virtual void f(); |
| 2440 | \& }; |
| 2441 | \& |
| 2442 | \& struct B: public A { |
| 2443 | \& void f(int); |
| 2444 | \& }; |
| 2445 | .Ve |
| 2446 | .Sp |
| 2447 | the \f(CW\*(C`A\*(C'\fR class version of \f(CW\*(C`f\*(C'\fR is hidden in \f(CW\*(C`B\*(C'\fR, and code |
| 2448 | like: |
| 2449 | .Sp |
| 2450 | .Vb 2 |
| 2451 | \& B* b; |
| 2452 | \& b\->f(); |
| 2453 | .Ve |
| 2454 | .Sp |
| 2455 | will fail to compile. |
| 2456 | .IP "\fB\-Wno\-pmf\-conversions\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2457 | .IX Item "-Wno-pmf-conversions ( and Objective- only)" |
| 2458 | Disable the diagnostic for converting a bound pointer to member function |
| 2459 | to a plain pointer. |
| 2460 | .IP "\fB\-Wsign\-promo\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 2461 | .IX Item "-Wsign-promo ( and Objective- only)" |
| 2462 | Warn when overload resolution chooses a promotion from unsigned or |
| 2463 | enumerated type to a signed type, over a conversion to an unsigned type of |
| 2464 | the same size. Previous versions of G++ would try to preserve |
| 2465 | unsignedness, but the standard mandates the current behavior. |
| 2466 | .Sp |
| 2467 | .Vb 4 |
| 2468 | \& struct A { |
| 2469 | \& operator int (); |
| 2470 | \& A& operator = (int); |
| 2471 | \& }; |
| 2472 | \& |
| 2473 | \& main () |
| 2474 | \& { |
| 2475 | \& A a,b; |
| 2476 | \& a = b; |
| 2477 | \& } |
| 2478 | .Ve |
| 2479 | .Sp |
| 2480 | In this example, G++ will synthesize a default \fBA& operator = |
| 2481 | (const A&);\fR, while cfront will use the user-defined \fBoperator =\fR. |
| 2482 | .Sh "Options Controlling Objective-C and Objective\-\*(C+ Dialects" |
| 2483 | .IX Subsection "Options Controlling Objective-C and Objective- Dialects" |
| 2484 | (\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ |
| 2485 | languages themselves. |
| 2486 | .PP |
| 2487 | This section describes the command-line options that are only meaningful |
| 2488 | for Objective-C and Objective\-\*(C+ programs, but you can also use most of |
| 2489 | the language-independent \s-1GNU\s0 compiler options. |
| 2490 | For example, you might compile a file \f(CW\*(C`some_class.m\*(C'\fR like this: |
| 2491 | .PP |
| 2492 | .Vb 1 |
| 2493 | \& gcc \-g \-fgnu\-runtime \-O \-c some_class.m |
| 2494 | .Ve |
| 2495 | .PP |
| 2496 | In this example, \fB\-fgnu\-runtime\fR is an option meant only for |
| 2497 | Objective-C and Objective\-\*(C+ programs; you can use the other options with |
| 2498 | any language supported by \s-1GCC\s0. |
| 2499 | .PP |
| 2500 | Note that since Objective-C is an extension of the C language, Objective-C |
| 2501 | compilations may also use options specific to the C front-end (e.g., |
| 2502 | \&\fB\-Wtraditional\fR). Similarly, Objective\-\*(C+ compilations may use |
| 2503 | \&\*(C+\-specific options (e.g., \fB\-Wabi\fR). |
| 2504 | .PP |
| 2505 | Here is a list of options that are \fIonly\fR for compiling Objective-C |
| 2506 | and Objective\-\*(C+ programs: |
| 2507 | .IP "\fB\-fconstant\-string\-class=\fR\fIclass-name\fR" 4 |
| 2508 | .IX Item "-fconstant-string-class=class-name" |
| 2509 | Use \fIclass-name\fR as the name of the class to instantiate for each |
| 2510 | literal string specified with the syntax \f(CW\*(C`@"..."\*(C'\fR. The default |
| 2511 | class name is \f(CW\*(C`NXConstantString\*(C'\fR if the \s-1GNU\s0 runtime is being used, and |
| 2512 | \&\f(CW\*(C`NSConstantString\*(C'\fR if the NeXT runtime is being used (see below). The |
| 2513 | \&\fB\-fconstant\-cfstrings\fR option, if also present, will override the |
| 2514 | \&\fB\-fconstant\-string\-class\fR setting and cause \f(CW\*(C`@"..."\*(C'\fR literals |
| 2515 | to be laid out as constant CoreFoundation strings. |
| 2516 | .IP "\fB\-fgnu\-runtime\fR" 4 |
| 2517 | .IX Item "-fgnu-runtime" |
| 2518 | Generate object code compatible with the standard \s-1GNU\s0 Objective-C |
| 2519 | runtime. This is the default for most types of systems. |
| 2520 | .IP "\fB\-fnext\-runtime\fR" 4 |
| 2521 | .IX Item "-fnext-runtime" |
| 2522 | Generate output compatible with the NeXT runtime. This is the default |
| 2523 | for NeXT-based systems, including Darwin and Mac \s-1OS\s0 X. The macro |
| 2524 | \&\f(CW\*(C`_\|_NEXT_RUNTIME_\|_\*(C'\fR is predefined if (and only if) this option is |
| 2525 | used. |
| 2526 | .IP "\fB\-fno\-nil\-receivers\fR" 4 |
| 2527 | .IX Item "-fno-nil-receivers" |
| 2528 | Assume that all Objective-C message dispatches (\f(CW\*(C`[receiver |
| 2529 | message:arg]\*(C'\fR) in this translation unit ensure that the receiver is |
| 2530 | not \f(CW\*(C`nil\*(C'\fR. This allows for more efficient entry points in the |
| 2531 | runtime to be used. This option is only available in conjunction with |
| 2532 | the NeXT runtime and \s-1ABI\s0 version 0 or 1. |
| 2533 | .IP "\fB\-fobjc\-abi\-version=\fR\fIn\fR" 4 |
| 2534 | .IX Item "-fobjc-abi-version=n" |
| 2535 | Use version \fIn\fR of the Objective-C \s-1ABI\s0 for the selected runtime. |
| 2536 | This option is currently supported only for the NeXT runtime. In that |
| 2537 | case, Version 0 is the traditional (32\-bit) \s-1ABI\s0 without support for |
| 2538 | properties and other Objective-C 2.0 additions. Version 1 is the |
| 2539 | traditional (32\-bit) \s-1ABI\s0 with support for properties and other |
| 2540 | Objective-C 2.0 additions. Version 2 is the modern (64\-bit) \s-1ABI\s0. If |
| 2541 | nothing is specified, the default is Version 0 on 32\-bit target |
| 2542 | machines, and Version 2 on 64\-bit target machines. |
| 2543 | .IP "\fB\-fobjc\-call\-cxx\-cdtors\fR" 4 |
| 2544 | .IX Item "-fobjc-call-cxx-cdtors" |
| 2545 | For each Objective-C class, check if any of its instance variables is a |
| 2546 | \&\*(C+ object with a non-trivial default constructor. If so, synthesize a |
| 2547 | special \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR instance method which will run |
| 2548 | non-trivial default constructors on any such instance variables, in order, |
| 2549 | and then return \f(CW\*(C`self\*(C'\fR. Similarly, check if any instance variable |
| 2550 | is a \*(C+ object with a non-trivial destructor, and if so, synthesize a |
| 2551 | special \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR method which will run |
| 2552 | all such default destructors, in reverse order. |
| 2553 | .Sp |
| 2554 | The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR |
| 2555 | methods thusly generated will only operate on instance variables |
| 2556 | declared in the current Objective-C class, and not those inherited |
| 2557 | from superclasses. It is the responsibility of the Objective-C |
| 2558 | runtime to invoke all such methods in an object's inheritance |
| 2559 | hierarchy. The \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR methods will be invoked |
| 2560 | by the runtime immediately after a new object instance is allocated; |
| 2561 | the \f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods will be invoked immediately |
| 2562 | before the runtime deallocates an object instance. |
| 2563 | .Sp |
| 2564 | As of this writing, only the NeXT runtime on Mac \s-1OS\s0 X 10.4 and later has |
| 2565 | support for invoking the \f(CW\*(C`\- (id) .cxx_construct\*(C'\fR and |
| 2566 | \&\f(CW\*(C`\- (void) .cxx_destruct\*(C'\fR methods. |
| 2567 | .IP "\fB\-fobjc\-direct\-dispatch\fR" 4 |
| 2568 | .IX Item "-fobjc-direct-dispatch" |
| 2569 | Allow fast jumps to the message dispatcher. On Darwin this is |
| 2570 | accomplished via the comm page. |
| 2571 | .IP "\fB\-fobjc\-exceptions\fR" 4 |
| 2572 | .IX Item "-fobjc-exceptions" |
| 2573 | Enable syntactic support for structured exception handling in |
| 2574 | Objective-C, similar to what is offered by \*(C+ and Java. This option |
| 2575 | is required to use the Objective-C keywords \f(CW@try\fR, |
| 2576 | \&\f(CW@throw\fR, \f(CW@catch\fR, \f(CW@finally\fR and |
| 2577 | \&\f(CW@synchronized\fR. This option is available with both the \s-1GNU\s0 |
| 2578 | runtime and the NeXT runtime (but not available in conjunction with |
| 2579 | the NeXT runtime on Mac \s-1OS\s0 X 10.2 and earlier). |
| 2580 | .IP "\fB\-fobjc\-gc\fR" 4 |
| 2581 | .IX Item "-fobjc-gc" |
| 2582 | Enable garbage collection (\s-1GC\s0) in Objective-C and Objective\-\*(C+ |
| 2583 | programs. This option is only available with the NeXT runtime; the |
| 2584 | \&\s-1GNU\s0 runtime has a different garbage collection implementation that |
| 2585 | does not require special compiler flags. |
| 2586 | .IP "\fB\-fobjc\-nilcheck\fR" 4 |
| 2587 | .IX Item "-fobjc-nilcheck" |
| 2588 | For the NeXT runtime with version 2 of the \s-1ABI\s0, check for a nil |
| 2589 | receiver in method invocations before doing the actual method call. |
| 2590 | This is the default and can be disabled using |
| 2591 | \&\fB\-fno\-objc\-nilcheck\fR. Class methods and super calls are never |
| 2592 | checked for nil in this way no matter what this flag is set to. |
| 2593 | Currently this flag does nothing when the \s-1GNU\s0 runtime, or an older |
| 2594 | version of the NeXT runtime \s-1ABI\s0, is used. |
| 2595 | .IP "\fB\-fobjc\-std=objc1\fR" 4 |
| 2596 | .IX Item "-fobjc-std=objc1" |
| 2597 | Conform to the language syntax of Objective-C 1.0, the language |
| 2598 | recognized by \s-1GCC\s0 4.0. This only affects the Objective-C additions to |
| 2599 | the C/\*(C+ language; it does not affect conformance to C/\*(C+ standards, |
| 2600 | which is controlled by the separate C/\*(C+ dialect option flags. When |
| 2601 | this option is used with the Objective-C or Objective\-\*(C+ compiler, |
| 2602 | any Objective-C syntax that is not recognized by \s-1GCC\s0 4.0 is rejected. |
| 2603 | This is useful if you need to make sure that your Objective-C code can |
| 2604 | be compiled with older versions of \s-1GCC\s0. |
| 2605 | .IP "\fB\-freplace\-objc\-classes\fR" 4 |
| 2606 | .IX Item "-freplace-objc-classes" |
| 2607 | Emit a special marker instructing \fB\f(BIld\fB\|(1)\fR not to statically link in |
| 2608 | the resulting object file, and allow \fB\f(BIdyld\fB\|(1)\fR to load it in at |
| 2609 | run time instead. This is used in conjunction with the Fix-and-Continue |
| 2610 | debugging mode, where the object file in question may be recompiled and |
| 2611 | dynamically reloaded in the course of program execution, without the need |
| 2612 | to restart the program itself. Currently, Fix-and-Continue functionality |
| 2613 | is only available in conjunction with the NeXT runtime on Mac \s-1OS\s0 X 10.3 |
| 2614 | and later. |
| 2615 | .IP "\fB\-fzero\-link\fR" 4 |
| 2616 | .IX Item "-fzero-link" |
| 2617 | When compiling for the NeXT runtime, the compiler ordinarily replaces calls |
| 2618 | to \f(CW\*(C`objc_getClass("...")\*(C'\fR (when the name of the class is known at |
| 2619 | compile time) with static class references that get initialized at load time, |
| 2620 | which improves run-time performance. Specifying the \fB\-fzero\-link\fR flag |
| 2621 | suppresses this behavior and causes calls to \f(CW\*(C`objc_getClass("...")\*(C'\fR |
| 2622 | to be retained. This is useful in Zero-Link debugging mode, since it allows |
| 2623 | for individual class implementations to be modified during program execution. |
| 2624 | The \s-1GNU\s0 runtime currently always retains calls to \f(CW\*(C`objc_get_class("...")\*(C'\fR |
| 2625 | regardless of command-line options. |
| 2626 | .IP "\fB\-gen\-decls\fR" 4 |
| 2627 | .IX Item "-gen-decls" |
| 2628 | Dump interface declarations for all classes seen in the source file to a |
| 2629 | file named \fI\fIsourcename\fI.decl\fR. |
| 2630 | .IP "\fB\-Wassign\-intercept\fR (Objective-C and Objective\-\*(C+ only)" 4 |
| 2631 | .IX Item "-Wassign-intercept (Objective-C and Objective- only)" |
| 2632 | Warn whenever an Objective-C assignment is being intercepted by the |
| 2633 | garbage collector. |
| 2634 | .IP "\fB\-Wno\-protocol\fR (Objective-C and Objective\-\*(C+ only)" 4 |
| 2635 | .IX Item "-Wno-protocol (Objective-C and Objective- only)" |
| 2636 | If a class is declared to implement a protocol, a warning is issued for |
| 2637 | every method in the protocol that is not implemented by the class. The |
| 2638 | default behavior is to issue a warning for every method not explicitly |
| 2639 | implemented in the class, even if a method implementation is inherited |
| 2640 | from the superclass. If you use the \fB\-Wno\-protocol\fR option, then |
| 2641 | methods inherited from the superclass are considered to be implemented, |
| 2642 | and no warning is issued for them. |
| 2643 | .IP "\fB\-Wselector\fR (Objective-C and Objective\-\*(C+ only)" 4 |
| 2644 | .IX Item "-Wselector (Objective-C and Objective- only)" |
| 2645 | Warn if multiple methods of different types for the same selector are |
| 2646 | found during compilation. The check is performed on the list of methods |
| 2647 | in the final stage of compilation. Additionally, a check is performed |
| 2648 | for each selector appearing in a \f(CW\*(C`@selector(...)\*(C'\fR |
| 2649 | expression, and a corresponding method for that selector has been found |
| 2650 | during compilation. Because these checks scan the method table only at |
| 2651 | the end of compilation, these warnings are not produced if the final |
| 2652 | stage of compilation is not reached, for example because an error is |
| 2653 | found during compilation, or because the \fB\-fsyntax\-only\fR option is |
| 2654 | being used. |
| 2655 | .IP "\fB\-Wstrict\-selector\-match\fR (Objective-C and Objective\-\*(C+ only)" 4 |
| 2656 | .IX Item "-Wstrict-selector-match (Objective-C and Objective- only)" |
| 2657 | Warn if multiple methods with differing argument and/or return types are |
| 2658 | found for a given selector when attempting to send a message using this |
| 2659 | selector to a receiver of type \f(CW\*(C`id\*(C'\fR or \f(CW\*(C`Class\*(C'\fR. When this flag |
| 2660 | is off (which is the default behavior), the compiler will omit such warnings |
| 2661 | if any differences found are confined to types that share the same size |
| 2662 | and alignment. |
| 2663 | .IP "\fB\-Wundeclared\-selector\fR (Objective-C and Objective\-\*(C+ only)" 4 |
| 2664 | .IX Item "-Wundeclared-selector (Objective-C and Objective- only)" |
| 2665 | Warn if a \f(CW\*(C`@selector(...)\*(C'\fR expression referring to an |
| 2666 | undeclared selector is found. A selector is considered undeclared if no |
| 2667 | method with that name has been declared before the |
| 2668 | \&\f(CW\*(C`@selector(...)\*(C'\fR expression, either explicitly in an |
| 2669 | \&\f(CW@interface\fR or \f(CW@protocol\fR declaration, or implicitly in |
| 2670 | an \f(CW@implementation\fR section. This option always performs its |
| 2671 | checks as soon as a \f(CW\*(C`@selector(...)\*(C'\fR expression is found, |
| 2672 | while \fB\-Wselector\fR only performs its checks in the final stage of |
| 2673 | compilation. This also enforces the coding style convention |
| 2674 | that methods and selectors must be declared before being used. |
| 2675 | .IP "\fB\-print\-objc\-runtime\-info\fR" 4 |
| 2676 | .IX Item "-print-objc-runtime-info" |
| 2677 | Generate C header describing the largest structure that is passed by |
| 2678 | value, if any. |
| 2679 | .Sh "Options to Control Diagnostic Messages Formatting" |
| 2680 | .IX Subsection "Options to Control Diagnostic Messages Formatting" |
| 2681 | Traditionally, diagnostic messages have been formatted irrespective of |
| 2682 | the output device's aspect (e.g. its width, ...). The options described |
| 2683 | below can be used to control the diagnostic messages formatting |
| 2684 | algorithm, e.g. how many characters per line, how often source location |
| 2685 | information should be reported. Right now, only the \*(C+ front end can |
| 2686 | honor these options. However it is expected, in the near future, that |
| 2687 | the remaining front ends would be able to digest them correctly. |
| 2688 | .IP "\fB\-fmessage\-length=\fR\fIn\fR" 4 |
| 2689 | .IX Item "-fmessage-length=n" |
| 2690 | Try to format error messages so that they fit on lines of about \fIn\fR |
| 2691 | characters. The default is 72 characters for \fBg++\fR and 0 for the rest of |
| 2692 | the front ends supported by \s-1GCC\s0. If \fIn\fR is zero, then no |
| 2693 | line-wrapping will be done; each error message will appear on a single |
| 2694 | line. |
| 2695 | .IP "\fB\-fdiagnostics\-show\-location=once\fR" 4 |
| 2696 | .IX Item "-fdiagnostics-show-location=once" |
| 2697 | Only meaningful in line-wrapping mode. Instructs the diagnostic messages |
| 2698 | reporter to emit \fIonce\fR source location information; that is, in |
| 2699 | case the message is too long to fit on a single physical line and has to |
| 2700 | be wrapped, the source location won't be emitted (as prefix) again, |
| 2701 | over and over, in subsequent continuation lines. This is the default |
| 2702 | behavior. |
| 2703 | .IP "\fB\-fdiagnostics\-show\-location=every\-line\fR" 4 |
| 2704 | .IX Item "-fdiagnostics-show-location=every-line" |
| 2705 | Only meaningful in line-wrapping mode. Instructs the diagnostic |
| 2706 | messages reporter to emit the same source location information (as |
| 2707 | prefix) for physical lines that result from the process of breaking |
| 2708 | a message which is too long to fit on a single line. |
| 2709 | .IP "\fB\-fno\-diagnostics\-show\-option\fR" 4 |
| 2710 | .IX Item "-fno-diagnostics-show-option" |
| 2711 | By default, each diagnostic emitted includes text indicating the |
| 2712 | command-line option that directly controls the diagnostic (if such an |
| 2713 | option is known to the diagnostic machinery). Specifying the |
| 2714 | \&\fB\-fno\-diagnostics\-show\-option\fR flag suppresses that behavior. |
| 2715 | .Sh "Options to Request or Suppress Warnings" |
| 2716 | .IX Subsection "Options to Request or Suppress Warnings" |
| 2717 | Warnings are diagnostic messages that report constructions that |
| 2718 | are not inherently erroneous but that are risky or suggest there |
| 2719 | may have been an error. |
| 2720 | .PP |
| 2721 | The following language-independent options do not enable specific |
| 2722 | warnings but control the kinds of diagnostics produced by \s-1GCC\s0. |
| 2723 | .IP "\fB\-fsyntax\-only\fR" 4 |
| 2724 | .IX Item "-fsyntax-only" |
| 2725 | Check the code for syntax errors, but don't do anything beyond that. |
| 2726 | .IP "\fB\-fmax\-errors=\fR\fIn\fR" 4 |
| 2727 | .IX Item "-fmax-errors=n" |
| 2728 | Limits the maximum number of error messages to \fIn\fR, at which point |
| 2729 | \&\s-1GCC\s0 bails out rather than attempting to continue processing the source |
| 2730 | code. If \fIn\fR is 0 (the default), there is no limit on the number |
| 2731 | of error messages produced. If \fB\-Wfatal\-errors\fR is also |
| 2732 | specified, then \fB\-Wfatal\-errors\fR takes precedence over this |
| 2733 | option. |
| 2734 | .IP "\fB\-w\fR" 4 |
| 2735 | .IX Item "-w" |
| 2736 | Inhibit all warning messages. |
| 2737 | .IP "\fB\-Werror\fR" 4 |
| 2738 | .IX Item "-Werror" |
| 2739 | Make all warnings into errors. |
| 2740 | .IP "\fB\-Werror=\fR" 4 |
| 2741 | .IX Item "-Werror=" |
| 2742 | Make the specified warning into an error. The specifier for a warning |
| 2743 | is appended, for example \fB\-Werror=switch\fR turns the warnings |
| 2744 | controlled by \fB\-Wswitch\fR into errors. This switch takes a |
| 2745 | negative form, to be used to negate \fB\-Werror\fR for specific |
| 2746 | warnings, for example \fB\-Wno\-error=switch\fR makes |
| 2747 | \&\fB\-Wswitch\fR warnings not be errors, even when \fB\-Werror\fR |
| 2748 | is in effect. |
| 2749 | .Sp |
| 2750 | The warning message for each controllable warning includes the |
| 2751 | option that controls the warning. That option can then be used with |
| 2752 | \&\fB\-Werror=\fR and \fB\-Wno\-error=\fR as described above. |
| 2753 | (Printing of the option in the warning message can be disabled using the |
| 2754 | \&\fB\-fno\-diagnostics\-show\-option\fR flag.) |
| 2755 | .Sp |
| 2756 | Note that specifying \fB\-Werror=\fR\fIfoo\fR automatically implies |
| 2757 | \&\fB\-W\fR\fIfoo\fR. However, \fB\-Wno\-error=\fR\fIfoo\fR does not |
| 2758 | imply anything. |
| 2759 | .IP "\fB\-Wfatal\-errors\fR" 4 |
| 2760 | .IX Item "-Wfatal-errors" |
| 2761 | This option causes the compiler to abort compilation on the first error |
| 2762 | occurred rather than trying to keep going and printing further error |
| 2763 | messages. |
| 2764 | .PP |
| 2765 | You can request many specific warnings with options beginning |
| 2766 | \&\fB\-W\fR, for example \fB\-Wimplicit\fR to request warnings on |
| 2767 | implicit declarations. Each of these specific warning options also |
| 2768 | has a negative form beginning \fB\-Wno\-\fR to turn off warnings; for |
| 2769 | example, \fB\-Wno\-implicit\fR. This manual lists only one of the |
| 2770 | two forms, whichever is not the default. For further, |
| 2771 | language-specific options also refer to \fB\*(C+ Dialect Options\fR and |
| 2772 | \&\fBObjective-C and Objective\-\*(C+ Dialect Options\fR. |
| 2773 | .PP |
| 2774 | When an unrecognized warning option is requested (e.g., |
| 2775 | \&\fB\-Wunknown\-warning\fR), \s-1GCC\s0 will emit a diagnostic stating |
| 2776 | that the option is not recognized. However, if the \fB\-Wno\-\fR form |
| 2777 | is used, the behavior is slightly different: No diagnostic will be |
| 2778 | produced for \fB\-Wno\-unknown\-warning\fR unless other diagnostics |
| 2779 | are being produced. This allows the use of new \fB\-Wno\-\fR options |
| 2780 | with old compilers, but if something goes wrong, the compiler will |
| 2781 | warn that an unrecognized option was used. |
| 2782 | .IP "\fB\-pedantic\fR" 4 |
| 2783 | .IX Item "-pedantic" |
| 2784 | Issue all the warnings demanded by strict \s-1ISO\s0 C and \s-1ISO\s0 \*(C+; |
| 2785 | reject all programs that use forbidden extensions, and some other |
| 2786 | programs that do not follow \s-1ISO\s0 C and \s-1ISO\s0 \*(C+. For \s-1ISO\s0 C, follows the |
| 2787 | version of the \s-1ISO\s0 C standard specified by any \fB\-std\fR option used. |
| 2788 | .Sp |
| 2789 | Valid \s-1ISO\s0 C and \s-1ISO\s0 \*(C+ programs should compile properly with or without |
| 2790 | this option (though a rare few will require \fB\-ansi\fR or a |
| 2791 | \&\fB\-std\fR option specifying the required version of \s-1ISO\s0 C). However, |
| 2792 | without this option, certain \s-1GNU\s0 extensions and traditional C and \*(C+ |
| 2793 | features are supported as well. With this option, they are rejected. |
| 2794 | .Sp |
| 2795 | \&\fB\-pedantic\fR does not cause warning messages for use of the |
| 2796 | alternate keywords whose names begin and end with \fB_\|_\fR. Pedantic |
| 2797 | warnings are also disabled in the expression that follows |
| 2798 | \&\f(CW\*(C`_\|_extension_\|_\*(C'\fR. However, only system header files should use |
| 2799 | these escape routes; application programs should avoid them. |
| 2800 | .Sp |
| 2801 | Some users try to use \fB\-pedantic\fR to check programs for strict \s-1ISO\s0 |
| 2802 | C conformance. They soon find that it does not do quite what they want: |
| 2803 | it finds some non-ISO practices, but not all\-\-\-only those for which |
| 2804 | \&\s-1ISO\s0 C \fIrequires\fR a diagnostic, and some others for which |
| 2805 | diagnostics have been added. |
| 2806 | .Sp |
| 2807 | A feature to report any failure to conform to \s-1ISO\s0 C might be useful in |
| 2808 | some instances, but would require considerable additional work and would |
| 2809 | be quite different from \fB\-pedantic\fR. We don't have plans to |
| 2810 | support such a feature in the near future. |
| 2811 | .Sp |
| 2812 | Where the standard specified with \fB\-std\fR represents a \s-1GNU\s0 |
| 2813 | extended dialect of C, such as \fBgnu90\fR or \fBgnu99\fR, there is a |
| 2814 | corresponding \fIbase standard\fR, the version of \s-1ISO\s0 C on which the \s-1GNU\s0 |
| 2815 | extended dialect is based. Warnings from \fB\-pedantic\fR are given |
| 2816 | where they are required by the base standard. (It would not make sense |
| 2817 | for such warnings to be given only for features not in the specified \s-1GNU\s0 |
| 2818 | C dialect, since by definition the \s-1GNU\s0 dialects of C include all |
| 2819 | features the compiler supports with the given option, and there would be |
| 2820 | nothing to warn about.) |
| 2821 | .IP "\fB\-pedantic\-errors\fR" 4 |
| 2822 | .IX Item "-pedantic-errors" |
| 2823 | Like \fB\-pedantic\fR, except that errors are produced rather than |
| 2824 | warnings. |
| 2825 | .IP "\fB\-Wall\fR" 4 |
| 2826 | .IX Item "-Wall" |
| 2827 | This enables all the warnings about constructions that some users |
| 2828 | consider questionable, and that are easy to avoid (or modify to |
| 2829 | prevent the warning), even in conjunction with macros. This also |
| 2830 | enables some language-specific warnings described in \fB\*(C+ Dialect |
| 2831 | Options\fR and \fBObjective-C and Objective\-\*(C+ Dialect Options\fR. |
| 2832 | .Sp |
| 2833 | \&\fB\-Wall\fR turns on the following warning flags: |
| 2834 | .Sp |
| 2835 | \&\fB\-Waddress |
| 2836 | \&\-Warray\-bounds\fR (only with\fB \fR\fB\-O2\fR) |
| 2837 | \&\fB\-Wc++11\-compat |
| 2838 | \&\-Wchar\-subscripts |
| 2839 | \&\-Wenum\-compare\fR (in C/Objc; this is on by default in \*(C+) |
| 2840 | \&\fB\-Wimplicit\-int\fR (C and Objective-C only) |
| 2841 | \&\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only) |
| 2842 | \&\fB\-Wcomment |
| 2843 | \&\-Wformat |
| 2844 | \&\-Wmain\fR (only for C/ObjC and unless\fB \fR\fB\-ffreestanding\fR) |
| 2845 | \&\fB\-Wmaybe\-uninitialized |
| 2846 | \&\-Wmissing\-braces |
| 2847 | \&\-Wnonnull |
| 2848 | \&\-Wparentheses |
| 2849 | \&\-Wpointer\-sign |
| 2850 | \&\-Wreorder |
| 2851 | \&\-Wreturn\-type |
| 2852 | \&\-Wsequence\-point |
| 2853 | \&\-Wsign\-compare\fR (only in \*(C+) |
| 2854 | \&\fB\-Wstrict\-aliasing |
| 2855 | \&\-Wstrict\-overflow=1 |
| 2856 | \&\-Wswitch |
| 2857 | \&\-Wtrigraphs |
| 2858 | \&\-Wuninitialized |
| 2859 | \&\-Wunknown\-pragmas |
| 2860 | \&\-Wunused\-function |
| 2861 | \&\-Wunused\-label |
| 2862 | \&\-Wunused\-value |
| 2863 | \&\-Wunused\-variable |
| 2864 | \&\-Wvolatile\-register\-var\fR |
| 2865 | .Sp |
| 2866 | Note that some warning flags are not implied by \fB\-Wall\fR. Some of |
| 2867 | them warn about constructions that users generally do not consider |
| 2868 | questionable, but which occasionally you might wish to check for; |
| 2869 | others warn about constructions that are necessary or hard to avoid in |
| 2870 | some cases, and there is no simple way to modify the code to suppress |
| 2871 | the warning. Some of them are enabled by \fB\-Wextra\fR but many of |
| 2872 | them must be enabled individually. |
| 2873 | .IP "\fB\-Wextra\fR" 4 |
| 2874 | .IX Item "-Wextra" |
| 2875 | This enables some extra warning flags that are not enabled by |
| 2876 | \&\fB\-Wall\fR. (This option used to be called \fB\-W\fR. The older |
| 2877 | name is still supported, but the newer name is more descriptive.) |
| 2878 | .Sp |
| 2879 | \&\fB\-Wclobbered |
| 2880 | \&\-Wempty\-body |
| 2881 | \&\-Wignored\-qualifiers |
| 2882 | \&\-Wmissing\-field\-initializers |
| 2883 | \&\-Wmissing\-parameter\-type\fR (C only) |
| 2884 | \&\fB\-Wold\-style\-declaration\fR (C only) |
| 2885 | \&\fB\-Woverride\-init |
| 2886 | \&\-Wsign\-compare |
| 2887 | \&\-Wtype\-limits |
| 2888 | \&\-Wuninitialized |
| 2889 | \&\-Wunused\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) |
| 2890 | \&\fB\-Wunused\-but\-set\-parameter\fR (only with\fB \fR\fB\-Wunused\fR\fB \fRor\fB \fR\fB\-Wall\fR) \fB \fR |
| 2891 | .Sp |
| 2892 | The option \fB\-Wextra\fR also prints warning messages for the |
| 2893 | following cases: |
| 2894 | .RS 4 |
| 2895 | .IP "\(bu" 4 |
| 2896 | A pointer is compared against integer zero with \fB<\fR, \fB<=\fR, |
| 2897 | \&\fB>\fR, or \fB>=\fR. |
| 2898 | .IP "\(bu" 4 |
| 2899 | (\*(C+ only) An enumerator and a non-enumerator both appear in a |
| 2900 | conditional expression. |
| 2901 | .IP "\(bu" 4 |
| 2902 | (\*(C+ only) Ambiguous virtual bases. |
| 2903 | .IP "\(bu" 4 |
| 2904 | (\*(C+ only) Subscripting an array that has been declared \fBregister\fR. |
| 2905 | .IP "\(bu" 4 |
| 2906 | (\*(C+ only) Taking the address of a variable that has been declared |
| 2907 | \&\fBregister\fR. |
| 2908 | .IP "\(bu" 4 |
| 2909 | (\*(C+ only) A base class is not initialized in a derived class' copy |
| 2910 | constructor. |
| 2911 | .RE |
| 2912 | .RS 4 |
| 2913 | .RE |
| 2914 | .IP "\fB\-Wchar\-subscripts\fR" 4 |
| 2915 | .IX Item "-Wchar-subscripts" |
| 2916 | Warn if an array subscript has type \f(CW\*(C`char\*(C'\fR. This is a common cause |
| 2917 | of error, as programmers often forget that this type is signed on some |
| 2918 | machines. |
| 2919 | This warning is enabled by \fB\-Wall\fR. |
| 2920 | .IP "\fB\-Wcomment\fR" 4 |
| 2921 | .IX Item "-Wcomment" |
| 2922 | Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR |
| 2923 | comment, or whenever a Backslash-Newline appears in a \fB//\fR comment. |
| 2924 | This warning is enabled by \fB\-Wall\fR. |
| 2925 | .IP "\fB\-Wno\-coverage\-mismatch\fR" 4 |
| 2926 | .IX Item "-Wno-coverage-mismatch" |
| 2927 | Warn if feedback profiles do not match when using the |
| 2928 | \&\fB\-fprofile\-use\fR option. |
| 2929 | If a source file was changed between \fB\-fprofile\-gen\fR and |
| 2930 | \&\fB\-fprofile\-use\fR, the files with the profile feedback can fail |
| 2931 | to match the source file and \s-1GCC\s0 cannot use the profile feedback |
| 2932 | information. By default, this warning is enabled and is treated as an |
| 2933 | error. \fB\-Wno\-coverage\-mismatch\fR can be used to disable the |
| 2934 | warning or \fB\-Wno\-error=coverage\-mismatch\fR can be used to |
| 2935 | disable the error. Disabling the error for this warning can result in |
| 2936 | poorly optimized code and is useful only in the |
| 2937 | case of very minor changes such as bug fixes to an existing code-base. |
| 2938 | Completely disabling the warning is not recommended. |
| 2939 | .IP "\fB\-Wno\-cpp\fR" 4 |
| 2940 | .IX Item "-Wno-cpp" |
| 2941 | (C, Objective-C, \*(C+, Objective\-\*(C+ and Fortran only) |
| 2942 | .Sp |
| 2943 | Suppress warning messages emitted by \f(CW\*(C`#warning\*(C'\fR directives. |
| 2944 | .IP "\fB\-Wdouble\-promotion\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 |
| 2945 | .IX Item "-Wdouble-promotion (C, , Objective-C and Objective- only)" |
| 2946 | Give a warning when a value of type \f(CW\*(C`float\*(C'\fR is implicitly |
| 2947 | promoted to \f(CW\*(C`double\*(C'\fR. CPUs with a 32\-bit \*(L"single-precision\*(R" |
| 2948 | floating-point unit implement \f(CW\*(C`float\*(C'\fR in hardware, but emulate |
| 2949 | \&\f(CW\*(C`double\*(C'\fR in software. On such a machine, doing computations |
| 2950 | using \f(CW\*(C`double\*(C'\fR values is much more expensive because of the |
| 2951 | overhead required for software emulation. |
| 2952 | .Sp |
| 2953 | It is easy to accidentally do computations with \f(CW\*(C`double\*(C'\fR because |
| 2954 | floating-point literals are implicitly of type \f(CW\*(C`double\*(C'\fR. For |
| 2955 | example, in: |
| 2956 | .Sp |
| 2957 | .Vb 4 |
| 2958 | \& float area(float radius) |
| 2959 | \& { |
| 2960 | \& return 3.14159 * radius * radius; |
| 2961 | \& } |
| 2962 | .Ve |
| 2963 | .Sp |
| 2964 | the compiler will perform the entire computation with \f(CW\*(C`double\*(C'\fR |
| 2965 | because the floating-point literal is a \f(CW\*(C`double\*(C'\fR. |
| 2966 | .IP "\fB\-Wformat\fR" 4 |
| 2967 | .IX Item "-Wformat" |
| 2968 | Check calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR, etc., to make sure that |
| 2969 | the arguments supplied have types appropriate to the format string |
| 2970 | specified, and that the conversions specified in the format string make |
| 2971 | sense. This includes standard functions, and others specified by format |
| 2972 | attributes, in the \f(CW\*(C`printf\*(C'\fR, |
| 2973 | \&\f(CW\*(C`scanf\*(C'\fR, \f(CW\*(C`strftime\*(C'\fR and \f(CW\*(C`strfmon\*(C'\fR (an X/Open extension, |
| 2974 | not in the C standard) families (or other target-specific families). |
| 2975 | Which functions are checked without format attributes having been |
| 2976 | specified depends on the standard version selected, and such checks of |
| 2977 | functions without the attribute specified are disabled by |
| 2978 | \&\fB\-ffreestanding\fR or \fB\-fno\-builtin\fR. |
| 2979 | .Sp |
| 2980 | The formats are checked against the format features supported by \s-1GNU\s0 |
| 2981 | libc version 2.2. These include all \s-1ISO\s0 C90 and C99 features, as well |
| 2982 | as features from the Single Unix Specification and some \s-1BSD\s0 and \s-1GNU\s0 |
| 2983 | extensions. Other library implementations may not support all these |
| 2984 | features; \s-1GCC\s0 does not support warning about features that go beyond a |
| 2985 | particular library's limitations. However, if \fB\-pedantic\fR is used |
| 2986 | with \fB\-Wformat\fR, warnings will be given about format features not |
| 2987 | in the selected standard version (but not for \f(CW\*(C`strfmon\*(C'\fR formats, |
| 2988 | since those are not in any version of the C standard). |
| 2989 | .Sp |
| 2990 | Since \fB\-Wformat\fR also checks for null format arguments for |
| 2991 | several functions, \fB\-Wformat\fR also implies \fB\-Wnonnull\fR. |
| 2992 | .Sp |
| 2993 | \&\fB\-Wformat\fR is included in \fB\-Wall\fR. For more control over some |
| 2994 | aspects of format checking, the options \fB\-Wformat\-y2k\fR, |
| 2995 | \&\fB\-Wno\-format\-extra\-args\fR, \fB\-Wno\-format\-zero\-length\fR, |
| 2996 | \&\fB\-Wformat\-nonliteral\fR, \fB\-Wformat\-security\fR, and |
| 2997 | \&\fB\-Wformat=2\fR are available, but are not included in \fB\-Wall\fR. |
| 2998 | .IP "\fB\-Wformat\-y2k\fR" 4 |
| 2999 | .IX Item "-Wformat-y2k" |
| 3000 | If \fB\-Wformat\fR is specified, also warn about \f(CW\*(C`strftime\*(C'\fR |
| 3001 | formats that may yield only a two-digit year. |
| 3002 | .IP "\fB\-Wno\-format\-contains\-nul\fR" 4 |
| 3003 | .IX Item "-Wno-format-contains-nul" |
| 3004 | If \fB\-Wformat\fR is specified, do not warn about format strings that |
| 3005 | contain \s-1NUL\s0 bytes. |
| 3006 | .IP "\fB\-Wno\-format\-extra\-args\fR" 4 |
| 3007 | .IX Item "-Wno-format-extra-args" |
| 3008 | If \fB\-Wformat\fR is specified, do not warn about excess arguments to a |
| 3009 | \&\f(CW\*(C`printf\*(C'\fR or \f(CW\*(C`scanf\*(C'\fR format function. The C standard specifies |
| 3010 | that such arguments are ignored. |
| 3011 | .Sp |
| 3012 | Where the unused arguments lie between used arguments that are |
| 3013 | specified with \fB$\fR operand number specifications, normally |
| 3014 | warnings are still given, since the implementation could not know what |
| 3015 | type to pass to \f(CW\*(C`va_arg\*(C'\fR to skip the unused arguments. However, |
| 3016 | in the case of \f(CW\*(C`scanf\*(C'\fR formats, this option will suppress the |
| 3017 | warning if the unused arguments are all pointers, since the Single |
| 3018 | Unix Specification says that such unused arguments are allowed. |
| 3019 | .IP "\fB\-Wno\-format\-zero\-length\fR" 4 |
| 3020 | .IX Item "-Wno-format-zero-length" |
| 3021 | If \fB\-Wformat\fR is specified, do not warn about zero-length formats. |
| 3022 | The C standard specifies that zero-length formats are allowed. |
| 3023 | .IP "\fB\-Wformat\-nonliteral\fR" 4 |
| 3024 | .IX Item "-Wformat-nonliteral" |
| 3025 | If \fB\-Wformat\fR is specified, also warn if the format string is not a |
| 3026 | string literal and so cannot be checked, unless the format function |
| 3027 | takes its format arguments as a \f(CW\*(C`va_list\*(C'\fR. |
| 3028 | .IP "\fB\-Wformat\-security\fR" 4 |
| 3029 | .IX Item "-Wformat-security" |
| 3030 | If \fB\-Wformat\fR is specified, also warn about uses of format |
| 3031 | functions that represent possible security problems. At present, this |
| 3032 | warns about calls to \f(CW\*(C`printf\*(C'\fR and \f(CW\*(C`scanf\*(C'\fR functions where the |
| 3033 | format string is not a string literal and there are no format arguments, |
| 3034 | as in \f(CW\*(C`printf (foo);\*(C'\fR. This may be a security hole if the format |
| 3035 | string came from untrusted input and contains \fB\f(CB%n\fB\fR. (This is |
| 3036 | currently a subset of what \fB\-Wformat\-nonliteral\fR warns about, but |
| 3037 | in future warnings may be added to \fB\-Wformat\-security\fR that are not |
| 3038 | included in \fB\-Wformat\-nonliteral\fR.) |
| 3039 | .IP "\fB\-Wformat=2\fR" 4 |
| 3040 | .IX Item "-Wformat=2" |
| 3041 | Enable \fB\-Wformat\fR plus format checks not included in |
| 3042 | \&\fB\-Wformat\fR. Currently equivalent to \fB\-Wformat |
| 3043 | \&\-Wformat\-nonliteral \-Wformat\-security \-Wformat\-y2k\fR. |
| 3044 | .IP "\fB\-Wnonnull\fR" 4 |
| 3045 | .IX Item "-Wnonnull" |
| 3046 | Warn about passing a null pointer for arguments marked as |
| 3047 | requiring a non-null value by the \f(CW\*(C`nonnull\*(C'\fR function attribute. |
| 3048 | .Sp |
| 3049 | \&\fB\-Wnonnull\fR is included in \fB\-Wall\fR and \fB\-Wformat\fR. It |
| 3050 | can be disabled with the \fB\-Wno\-nonnull\fR option. |
| 3051 | .IP "\fB\-Winit\-self\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 |
| 3052 | .IX Item "-Winit-self (C, , Objective-C and Objective- only)" |
| 3053 | Warn about uninitialized variables that are initialized with themselves. |
| 3054 | Note this option can only be used with the \fB\-Wuninitialized\fR option. |
| 3055 | .Sp |
| 3056 | For example, \s-1GCC\s0 will warn about \f(CW\*(C`i\*(C'\fR being uninitialized in the |
| 3057 | following snippet only when \fB\-Winit\-self\fR has been specified: |
| 3058 | .Sp |
| 3059 | .Vb 5 |
| 3060 | \& int f() |
| 3061 | \& { |
| 3062 | \& int i = i; |
| 3063 | \& return i; |
| 3064 | \& } |
| 3065 | .Ve |
| 3066 | .IP "\fB\-Wimplicit\-int\fR (C and Objective-C only)" 4 |
| 3067 | .IX Item "-Wimplicit-int (C and Objective-C only)" |
| 3068 | Warn when a declaration does not specify a type. |
| 3069 | This warning is enabled by \fB\-Wall\fR. |
| 3070 | .IP "\fB\-Wimplicit\-function\-declaration\fR (C and Objective-C only)" 4 |
| 3071 | .IX Item "-Wimplicit-function-declaration (C and Objective-C only)" |
| 3072 | Give a warning whenever a function is used before being declared. In |
| 3073 | C99 mode (\fB\-std=c99\fR or \fB\-std=gnu99\fR), this warning is |
| 3074 | enabled by default and it is made into an error by |
| 3075 | \&\fB\-pedantic\-errors\fR. This warning is also enabled by |
| 3076 | \&\fB\-Wall\fR. |
| 3077 | .IP "\fB\-Wimplicit\fR (C and Objective-C only)" 4 |
| 3078 | .IX Item "-Wimplicit (C and Objective-C only)" |
| 3079 | Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. |
| 3080 | This warning is enabled by \fB\-Wall\fR. |
| 3081 | .IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 |
| 3082 | .IX Item "-Wignored-qualifiers (C and only)" |
| 3083 | Warn if the return type of a function has a type qualifier |
| 3084 | such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, |
| 3085 | since the value returned by a function is not an lvalue. |
| 3086 | For \*(C+, the warning is only emitted for scalar types or \f(CW\*(C`void\*(C'\fR. |
| 3087 | \&\s-1ISO\s0 C prohibits qualified \f(CW\*(C`void\*(C'\fR return types on function |
| 3088 | definitions, so such return types always receive a warning |
| 3089 | even without this option. |
| 3090 | .Sp |
| 3091 | This warning is also enabled by \fB\-Wextra\fR. |
| 3092 | .IP "\fB\-Wmain\fR" 4 |
| 3093 | .IX Item "-Wmain" |
| 3094 | Warn if the type of \fBmain\fR is suspicious. \fBmain\fR should be |
| 3095 | a function with external linkage, returning int, taking either zero |
| 3096 | arguments, two, or three arguments of appropriate types. This warning |
| 3097 | is enabled by default in \*(C+ and is enabled by either \fB\-Wall\fR |
| 3098 | or \fB\-pedantic\fR. |
| 3099 | .IP "\fB\-Wmissing\-braces\fR" 4 |
| 3100 | .IX Item "-Wmissing-braces" |
| 3101 | Warn if an aggregate or union initializer is not fully bracketed. In |
| 3102 | the following example, the initializer for \fBa\fR is not fully |
| 3103 | bracketed, but that for \fBb\fR is fully bracketed. |
| 3104 | .Sp |
| 3105 | .Vb 2 |
| 3106 | \& int a[2][2] = { 0, 1, 2, 3 }; |
| 3107 | \& int b[2][2] = { { 0, 1 }, { 2, 3 } }; |
| 3108 | .Ve |
| 3109 | .Sp |
| 3110 | This warning is enabled by \fB\-Wall\fR. |
| 3111 | .IP "\fB\-Wmissing\-include\-dirs\fR (C, \*(C+, Objective-C and Objective\-\*(C+ only)" 4 |
| 3112 | .IX Item "-Wmissing-include-dirs (C, , Objective-C and Objective- only)" |
| 3113 | Warn if a user-supplied include directory does not exist. |
| 3114 | .IP "\fB\-Wparentheses\fR" 4 |
| 3115 | .IX Item "-Wparentheses" |
| 3116 | Warn if parentheses are omitted in certain contexts, such |
| 3117 | as when there is an assignment in a context where a truth value |
| 3118 | is expected, or when operators are nested whose precedence people |
| 3119 | often get confused about. |
| 3120 | .Sp |
| 3121 | Also warn if a comparison like \fBx<=y<=z\fR appears; this is |
| 3122 | equivalent to \fB(x<=y ? 1 : 0) <= z\fR, which is a different |
| 3123 | interpretation from that of ordinary mathematical notation. |
| 3124 | .Sp |
| 3125 | Also warn about constructions where there may be confusion to which |
| 3126 | \&\f(CW\*(C`if\*(C'\fR statement an \f(CW\*(C`else\*(C'\fR branch belongs. Here is an example of |
| 3127 | such a case: |
| 3128 | .Sp |
| 3129 | .Vb 7 |
| 3130 | \& { |
| 3131 | \& if (a) |
| 3132 | \& if (b) |
| 3133 | \& foo (); |
| 3134 | \& else |
| 3135 | \& bar (); |
| 3136 | \& } |
| 3137 | .Ve |
| 3138 | .Sp |
| 3139 | In C/\*(C+, every \f(CW\*(C`else\*(C'\fR branch belongs to the innermost possible |
| 3140 | \&\f(CW\*(C`if\*(C'\fR statement, which in this example is \f(CW\*(C`if (b)\*(C'\fR. This is |
| 3141 | often not what the programmer expected, as illustrated in the above |
| 3142 | example by indentation the programmer chose. When there is the |
| 3143 | potential for this confusion, \s-1GCC\s0 will issue a warning when this flag |
| 3144 | is specified. To eliminate the warning, add explicit braces around |
| 3145 | the innermost \f(CW\*(C`if\*(C'\fR statement so there is no way the \f(CW\*(C`else\*(C'\fR |
| 3146 | could belong to the enclosing \f(CW\*(C`if\*(C'\fR. The resulting code would |
| 3147 | look like this: |
| 3148 | .Sp |
| 3149 | .Vb 9 |
| 3150 | \& { |
| 3151 | \& if (a) |
| 3152 | \& { |
| 3153 | \& if (b) |
| 3154 | \& foo (); |
| 3155 | \& else |
| 3156 | \& bar (); |
| 3157 | \& } |
| 3158 | \& } |
| 3159 | .Ve |
| 3160 | .Sp |
| 3161 | Also warn for dangerous uses of the |
| 3162 | ?: with omitted middle operand \s-1GNU\s0 extension. When the condition |
| 3163 | in the ?: operator is a boolean expression the omitted value will |
| 3164 | be always 1. Often the user expects it to be a value computed |
| 3165 | inside the conditional expression instead. |
| 3166 | .Sp |
| 3167 | This warning is enabled by \fB\-Wall\fR. |
| 3168 | .IP "\fB\-Wsequence\-point\fR" 4 |
| 3169 | .IX Item "-Wsequence-point" |
| 3170 | Warn about code that may have undefined semantics because of violations |
| 3171 | of sequence point rules in the C and \*(C+ standards. |
| 3172 | .Sp |
| 3173 | The C and \*(C+ standards defines the order in which expressions in a C/\*(C+ |
| 3174 | program are evaluated in terms of \fIsequence points\fR, which represent |
| 3175 | a partial ordering between the execution of parts of the program: those |
| 3176 | executed before the sequence point, and those executed after it. These |
| 3177 | occur after the evaluation of a full expression (one which is not part |
| 3178 | of a larger expression), after the evaluation of the first operand of a |
| 3179 | \&\f(CW\*(C`&&\*(C'\fR, \f(CW\*(C`||\*(C'\fR, \f(CW\*(C`? :\*(C'\fR or \f(CW\*(C`,\*(C'\fR (comma) operator, before a |
| 3180 | function is called (but after the evaluation of its arguments and the |
| 3181 | expression denoting the called function), and in certain other places. |
| 3182 | Other than as expressed by the sequence point rules, the order of |
| 3183 | evaluation of subexpressions of an expression is not specified. All |
| 3184 | these rules describe only a partial order rather than a total order, |
| 3185 | since, for example, if two functions are called within one expression |
| 3186 | with no sequence point between them, the order in which the functions |
| 3187 | are called is not specified. However, the standards committee have |
| 3188 | ruled that function calls do not overlap. |
| 3189 | .Sp |
| 3190 | It is not specified when between sequence points modifications to the |
| 3191 | values of objects take effect. Programs whose behavior depends on this |
| 3192 | have undefined behavior; the C and \*(C+ standards specify that \*(L"Between |
| 3193 | the previous and next sequence point an object shall have its stored |
| 3194 | value modified at most once by the evaluation of an expression. |
| 3195 | Furthermore, the prior value shall be read only to determine the value |
| 3196 | to be stored.\*(R". If a program breaks these rules, the results on any |
| 3197 | particular implementation are entirely unpredictable. |
| 3198 | .Sp |
| 3199 | Examples of code with undefined behavior are \f(CW\*(C`a = a++;\*(C'\fR, \f(CW\*(C`a[n] |
| 3200 | = b[n++]\*(C'\fR and \f(CW\*(C`a[i++] = i;\*(C'\fR. Some more complicated cases are not |
| 3201 | diagnosed by this option, and it may give an occasional false positive |
| 3202 | result, but in general it has been found fairly effective at detecting |
| 3203 | this sort of problem in programs. |
| 3204 | .Sp |
| 3205 | The standard is worded confusingly, therefore there is some debate |
| 3206 | over the precise meaning of the sequence point rules in subtle cases. |
| 3207 | Links to discussions of the problem, including proposed formal |
| 3208 | definitions, may be found on the \s-1GCC\s0 readings page, at |
| 3209 | <\fBhttp://gcc.gnu.org/readings.html\fR>. |
| 3210 | .Sp |
| 3211 | This warning is enabled by \fB\-Wall\fR for C and \*(C+. |
| 3212 | .IP "\fB\-Wreturn\-type\fR" 4 |
| 3213 | .IX Item "-Wreturn-type" |
| 3214 | Warn whenever a function is defined with a return-type that defaults |
| 3215 | to \f(CW\*(C`int\*(C'\fR. Also warn about any \f(CW\*(C`return\*(C'\fR statement with no |
| 3216 | return-value in a function whose return-type is not \f(CW\*(C`void\*(C'\fR |
| 3217 | (falling off the end of the function body is considered returning |
| 3218 | without a value), and about a \f(CW\*(C`return\*(C'\fR statement with an |
| 3219 | expression in a function whose return-type is \f(CW\*(C`void\*(C'\fR. |
| 3220 | .Sp |
| 3221 | For \*(C+, a function without return type always produces a diagnostic |
| 3222 | message, even when \fB\-Wno\-return\-type\fR is specified. The only |
| 3223 | exceptions are \fBmain\fR and functions defined in system headers. |
| 3224 | .Sp |
| 3225 | This warning is enabled by \fB\-Wall\fR. |
| 3226 | .IP "\fB\-Wswitch\fR" 4 |
| 3227 | .IX Item "-Wswitch" |
| 3228 | Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type |
| 3229 | and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that |
| 3230 | enumeration. (The presence of a \f(CW\*(C`default\*(C'\fR label prevents this |
| 3231 | warning.) \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also |
| 3232 | provoke warnings when this option is used (even if there is a |
| 3233 | \&\f(CW\*(C`default\*(C'\fR label). |
| 3234 | This warning is enabled by \fB\-Wall\fR. |
| 3235 | .IP "\fB\-Wswitch\-default\fR" 4 |
| 3236 | .IX Item "-Wswitch-default" |
| 3237 | Warn whenever a \f(CW\*(C`switch\*(C'\fR statement does not have a \f(CW\*(C`default\*(C'\fR |
| 3238 | case. |
| 3239 | .IP "\fB\-Wswitch\-enum\fR" 4 |
| 3240 | .IX Item "-Wswitch-enum" |
| 3241 | Warn whenever a \f(CW\*(C`switch\*(C'\fR statement has an index of enumerated type |
| 3242 | and lacks a \f(CW\*(C`case\*(C'\fR for one or more of the named codes of that |
| 3243 | enumeration. \f(CW\*(C`case\*(C'\fR labels outside the enumeration range also |
| 3244 | provoke warnings when this option is used. The only difference |
| 3245 | between \fB\-Wswitch\fR and this option is that this option gives a |
| 3246 | warning about an omitted enumeration code even if there is a |
| 3247 | \&\f(CW\*(C`default\*(C'\fR label. |
| 3248 | .IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 |
| 3249 | .IX Item "-Wsync-nand (C and only)" |
| 3250 | Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR |
| 3251 | built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. |
| 3252 | .IP "\fB\-Wtrigraphs\fR" 4 |
| 3253 | .IX Item "-Wtrigraphs" |
| 3254 | Warn if any trigraphs are encountered that might change the meaning of |
| 3255 | the program (trigraphs within comments are not warned about). |
| 3256 | This warning is enabled by \fB\-Wall\fR. |
| 3257 | .IP "\fB\-Wunused\-but\-set\-parameter\fR" 4 |
| 3258 | .IX Item "-Wunused-but-set-parameter" |
| 3259 | Warn whenever a function parameter is assigned to, but otherwise unused |
| 3260 | (aside from its declaration). |
| 3261 | .Sp |
| 3262 | To suppress this warning use the \fBunused\fR attribute. |
| 3263 | .Sp |
| 3264 | This warning is also enabled by \fB\-Wunused\fR together with |
| 3265 | \&\fB\-Wextra\fR. |
| 3266 | .IP "\fB\-Wunused\-but\-set\-variable\fR" 4 |
| 3267 | .IX Item "-Wunused-but-set-variable" |
| 3268 | Warn whenever a local variable is assigned to, but otherwise unused |
| 3269 | (aside from its declaration). |
| 3270 | This warning is enabled by \fB\-Wall\fR. |
| 3271 | .Sp |
| 3272 | To suppress this warning use the \fBunused\fR attribute. |
| 3273 | .Sp |
| 3274 | This warning is also enabled by \fB\-Wunused\fR, which is enabled |
| 3275 | by \fB\-Wall\fR. |
| 3276 | .IP "\fB\-Wunused\-function\fR" 4 |
| 3277 | .IX Item "-Wunused-function" |
| 3278 | Warn whenever a static function is declared but not defined or a |
| 3279 | non-inline static function is unused. |
| 3280 | This warning is enabled by \fB\-Wall\fR. |
| 3281 | .IP "\fB\-Wunused\-label\fR" 4 |
| 3282 | .IX Item "-Wunused-label" |
| 3283 | Warn whenever a label is declared but not used. |
| 3284 | This warning is enabled by \fB\-Wall\fR. |
| 3285 | .Sp |
| 3286 | To suppress this warning use the \fBunused\fR attribute. |
| 3287 | .IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 |
| 3288 | .IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" |
| 3289 | Warn when a typedef locally defined in a function is not used. |
| 3290 | .IP "\fB\-Wunused\-parameter\fR" 4 |
| 3291 | .IX Item "-Wunused-parameter" |
| 3292 | Warn whenever a function parameter is unused aside from its declaration. |
| 3293 | .Sp |
| 3294 | To suppress this warning use the \fBunused\fR attribute. |
| 3295 | .IP "\fB\-Wno\-unused\-result\fR" 4 |
| 3296 | .IX Item "-Wno-unused-result" |
| 3297 | Do not warn if a caller of a function marked with attribute |
| 3298 | \&\f(CW\*(C`warn_unused_result\*(C'\fR does not use |
| 3299 | its return value. The default is \fB\-Wunused\-result\fR. |
| 3300 | .IP "\fB\-Wunused\-variable\fR" 4 |
| 3301 | .IX Item "-Wunused-variable" |
| 3302 | Warn whenever a local variable or non-constant static variable is unused |
| 3303 | aside from its declaration. |
| 3304 | This warning is enabled by \fB\-Wall\fR. |
| 3305 | .Sp |
| 3306 | To suppress this warning use the \fBunused\fR attribute. |
| 3307 | .IP "\fB\-Wunused\-value\fR" 4 |
| 3308 | .IX Item "-Wunused-value" |
| 3309 | Warn whenever a statement computes a result that is explicitly not |
| 3310 | used. To suppress this warning cast the unused expression to |
| 3311 | \&\fBvoid\fR. This includes an expression-statement or the left-hand |
| 3312 | side of a comma expression that contains no side effects. For example, |
| 3313 | an expression such as \fBx[i,j]\fR will cause a warning, while |
| 3314 | \&\fBx[(void)i,j]\fR will not. |
| 3315 | .Sp |
| 3316 | This warning is enabled by \fB\-Wall\fR. |
| 3317 | .IP "\fB\-Wunused\fR" 4 |
| 3318 | .IX Item "-Wunused" |
| 3319 | All the above \fB\-Wunused\fR options combined. |
| 3320 | .Sp |
| 3321 | In order to get a warning about an unused function parameter, you must |
| 3322 | either specify \fB\-Wextra \-Wunused\fR (note that \fB\-Wall\fR implies |
| 3323 | \&\fB\-Wunused\fR), or separately specify \fB\-Wunused\-parameter\fR. |
| 3324 | .IP "\fB\-Wuninitialized\fR" 4 |
| 3325 | .IX Item "-Wuninitialized" |
| 3326 | Warn if an automatic variable is used without first being initialized |
| 3327 | or if a variable may be clobbered by a \f(CW\*(C`setjmp\*(C'\fR call. In \*(C+, |
| 3328 | warn if a non-static reference or non-static \fBconst\fR member |
| 3329 | appears in a class without constructors. |
| 3330 | .Sp |
| 3331 | If you want to warn about code that uses the uninitialized value of the |
| 3332 | variable in its own initializer, use the \fB\-Winit\-self\fR option. |
| 3333 | .Sp |
| 3334 | These warnings occur for individual uninitialized or clobbered |
| 3335 | elements of structure, union or array variables as well as for |
| 3336 | variables that are uninitialized or clobbered as a whole. They do |
| 3337 | not occur for variables or elements declared \f(CW\*(C`volatile\*(C'\fR. Because |
| 3338 | these warnings depend on optimization, the exact variables or elements |
| 3339 | for which there are warnings will depend on the precise optimization |
| 3340 | options and version of \s-1GCC\s0 used. |
| 3341 | .Sp |
| 3342 | Note that there may be no warning about a variable that is used only |
| 3343 | to compute a value that itself is never used, because such |
| 3344 | computations may be deleted by data flow analysis before the warnings |
| 3345 | are printed. |
| 3346 | .IP "\fB\-Wmaybe\-uninitialized\fR" 4 |
| 3347 | .IX Item "-Wmaybe-uninitialized" |
| 3348 | For an automatic variable, if there exists a path from the function |
| 3349 | entry to a use of the variable that is initialized, but there exist |
| 3350 | some other paths the variable is not initialized, the compiler will |
| 3351 | emit a warning if it can not prove the uninitialized paths do not |
| 3352 | happen at run time. These warnings are made optional because \s-1GCC\s0 is |
| 3353 | not smart enough to see all the reasons why the code might be correct |
| 3354 | despite appearing to have an error. Here is one example of how |
| 3355 | this can happen: |
| 3356 | .Sp |
| 3357 | .Vb 12 |
| 3358 | \& { |
| 3359 | \& int x; |
| 3360 | \& switch (y) |
| 3361 | \& { |
| 3362 | \& case 1: x = 1; |
| 3363 | \& break; |
| 3364 | \& case 2: x = 4; |
| 3365 | \& break; |
| 3366 | \& case 3: x = 5; |
| 3367 | \& } |
| 3368 | \& foo (x); |
| 3369 | \& } |
| 3370 | .Ve |
| 3371 | .Sp |
| 3372 | If the value of \f(CW\*(C`y\*(C'\fR is always 1, 2 or 3, then \f(CW\*(C`x\*(C'\fR is |
| 3373 | always initialized, but \s-1GCC\s0 doesn't know this. To suppress the |
| 3374 | warning, the user needs to provide a default case with \fIassert\fR\|(0) or |
| 3375 | similar code. |
| 3376 | .Sp |
| 3377 | This option also warns when a non-volatile automatic variable might be |
| 3378 | changed by a call to \f(CW\*(C`longjmp\*(C'\fR. These warnings as well are possible |
| 3379 | only in optimizing compilation. |
| 3380 | .Sp |
| 3381 | The compiler sees only the calls to \f(CW\*(C`setjmp\*(C'\fR. It cannot know |
| 3382 | where \f(CW\*(C`longjmp\*(C'\fR will be called; in fact, a signal handler could |
| 3383 | call it at any point in the code. As a result, you may get a warning |
| 3384 | even when there is in fact no problem because \f(CW\*(C`longjmp\*(C'\fR cannot |
| 3385 | in fact be called at the place that would cause a problem. |
| 3386 | .Sp |
| 3387 | Some spurious warnings can be avoided if you declare all the functions |
| 3388 | you use that never return as \f(CW\*(C`noreturn\*(C'\fR. |
| 3389 | .Sp |
| 3390 | This warning is enabled by \fB\-Wall\fR or \fB\-Wextra\fR. |
| 3391 | .IP "\fB\-Wunknown\-pragmas\fR" 4 |
| 3392 | .IX Item "-Wunknown-pragmas" |
| 3393 | Warn when a \f(CW\*(C`#pragma\*(C'\fR directive is encountered that is not understood by |
| 3394 | \&\s-1GCC\s0. If this command-line option is used, warnings will even be issued |
| 3395 | for unknown pragmas in system header files. This is not the case if |
| 3396 | the warnings were only enabled by the \fB\-Wall\fR command-line option. |
| 3397 | .IP "\fB\-Wno\-pragmas\fR" 4 |
| 3398 | .IX Item "-Wno-pragmas" |
| 3399 | Do not warn about misuses of pragmas, such as incorrect parameters, |
| 3400 | invalid syntax, or conflicts between pragmas. See also |
| 3401 | \&\fB\-Wunknown\-pragmas\fR. |
| 3402 | .IP "\fB\-Wstrict\-aliasing\fR" 4 |
| 3403 | .IX Item "-Wstrict-aliasing" |
| 3404 | This option is only active when \fB\-fstrict\-aliasing\fR is active. |
| 3405 | It warns about code that might break the strict aliasing rules that the |
| 3406 | compiler is using for optimization. The warning does not catch all |
| 3407 | cases, but does attempt to catch the more common pitfalls. It is |
| 3408 | included in \fB\-Wall\fR. |
| 3409 | It is equivalent to \fB\-Wstrict\-aliasing=3\fR |
| 3410 | .IP "\fB\-Wstrict\-aliasing=n\fR" 4 |
| 3411 | .IX Item "-Wstrict-aliasing=n" |
| 3412 | This option is only active when \fB\-fstrict\-aliasing\fR is active. |
| 3413 | It warns about code that might break the strict aliasing rules that the |
| 3414 | compiler is using for optimization. |
| 3415 | Higher levels correspond to higher accuracy (fewer false positives). |
| 3416 | Higher levels also correspond to more effort, similar to the way \-O works. |
| 3417 | \&\fB\-Wstrict\-aliasing\fR is equivalent to \fB\-Wstrict\-aliasing=n\fR, |
| 3418 | with n=3. |
| 3419 | .Sp |
| 3420 | Level 1: Most aggressive, quick, least accurate. |
| 3421 | Possibly useful when higher levels |
| 3422 | do not warn but \-fstrict\-aliasing still breaks the code, as it has very few |
| 3423 | false negatives. However, it has many false positives. |
| 3424 | Warns for all pointer conversions between possibly incompatible types, |
| 3425 | even if never dereferenced. Runs in the front end only. |
| 3426 | .Sp |
| 3427 | Level 2: Aggressive, quick, not too precise. |
| 3428 | May still have many false positives (not as many as level 1 though), |
| 3429 | and few false negatives (but possibly more than level 1). |
| 3430 | Unlike level 1, it only warns when an address is taken. Warns about |
| 3431 | incomplete types. Runs in the front end only. |
| 3432 | .Sp |
| 3433 | Level 3 (default for \fB\-Wstrict\-aliasing\fR): |
| 3434 | Should have very few false positives and few false |
| 3435 | negatives. Slightly slower than levels 1 or 2 when optimization is enabled. |
| 3436 | Takes care of the common pun+dereference pattern in the front end: |
| 3437 | \&\f(CW\*(C`*(int*)&some_float\*(C'\fR. |
| 3438 | If optimization is enabled, it also runs in the back end, where it deals |
| 3439 | with multiple statement cases using flow-sensitive points-to information. |
| 3440 | Only warns when the converted pointer is dereferenced. |
| 3441 | Does not warn about incomplete types. |
| 3442 | .IP "\fB\-Wstrict\-overflow\fR" 4 |
| 3443 | .IX Item "-Wstrict-overflow" |
| 3444 | .PD 0 |
| 3445 | .IP "\fB\-Wstrict\-overflow=\fR\fIn\fR" 4 |
| 3446 | .IX Item "-Wstrict-overflow=n" |
| 3447 | .PD |
| 3448 | This option is only active when \fB\-fstrict\-overflow\fR is active. |
| 3449 | It warns about cases where the compiler optimizes based on the |
| 3450 | assumption that signed overflow does not occur. Note that it does not |
| 3451 | warn about all cases where the code might overflow: it only warns |
| 3452 | about cases where the compiler implements some optimization. Thus |
| 3453 | this warning depends on the optimization level. |
| 3454 | .Sp |
| 3455 | An optimization that assumes that signed overflow does not occur is |
| 3456 | perfectly safe if the values of the variables involved are such that |
| 3457 | overflow never does, in fact, occur. Therefore this warning can |
| 3458 | easily give a false positive: a warning about code that is not |
| 3459 | actually a problem. To help focus on important issues, several |
| 3460 | warning levels are defined. No warnings are issued for the use of |
| 3461 | undefined signed overflow when estimating how many iterations a loop |
| 3462 | will require, in particular when determining whether a loop will be |
| 3463 | executed at all. |
| 3464 | .RS 4 |
| 3465 | .IP "\fB\-Wstrict\-overflow=1\fR" 4 |
| 3466 | .IX Item "-Wstrict-overflow=1" |
| 3467 | Warn about cases that are both questionable and easy to avoid. For |
| 3468 | example: \f(CW\*(C`x + 1 > x\*(C'\fR; with \fB\-fstrict\-overflow\fR, the |
| 3469 | compiler will simplify this to \f(CW1\fR. This level of |
| 3470 | \&\fB\-Wstrict\-overflow\fR is enabled by \fB\-Wall\fR; higher levels |
| 3471 | are not, and must be explicitly requested. |
| 3472 | .IP "\fB\-Wstrict\-overflow=2\fR" 4 |
| 3473 | .IX Item "-Wstrict-overflow=2" |
| 3474 | Also warn about other cases where a comparison is simplified to a |
| 3475 | constant. For example: \f(CW\*(C`abs (x) >= 0\*(C'\fR. This can only be |
| 3476 | simplified when \fB\-fstrict\-overflow\fR is in effect, because |
| 3477 | \&\f(CW\*(C`abs (INT_MIN)\*(C'\fR overflows to \f(CW\*(C`INT_MIN\*(C'\fR, which is less than |
| 3478 | zero. \fB\-Wstrict\-overflow\fR (with no level) is the same as |
| 3479 | \&\fB\-Wstrict\-overflow=2\fR. |
| 3480 | .IP "\fB\-Wstrict\-overflow=3\fR" 4 |
| 3481 | .IX Item "-Wstrict-overflow=3" |
| 3482 | Also warn about other cases where a comparison is simplified. For |
| 3483 | example: \f(CW\*(C`x + 1 > 1\*(C'\fR will be simplified to \f(CW\*(C`x > 0\*(C'\fR. |
| 3484 | .IP "\fB\-Wstrict\-overflow=4\fR" 4 |
| 3485 | .IX Item "-Wstrict-overflow=4" |
| 3486 | Also warn about other simplifications not covered by the above cases. |
| 3487 | For example: \f(CW\*(C`(x * 10) / 5\*(C'\fR will be simplified to \f(CW\*(C`x * 2\*(C'\fR. |
| 3488 | .IP "\fB\-Wstrict\-overflow=5\fR" 4 |
| 3489 | .IX Item "-Wstrict-overflow=5" |
| 3490 | Also warn about cases where the compiler reduces the magnitude of a |
| 3491 | constant involved in a comparison. For example: \f(CW\*(C`x + 2 > y\*(C'\fR will |
| 3492 | be simplified to \f(CW\*(C`x + 1 >= y\*(C'\fR. This is reported only at the |
| 3493 | highest warning level because this simplification applies to many |
| 3494 | comparisons, so this warning level will give a very large number of |
| 3495 | false positives. |
| 3496 | .RE |
| 3497 | .RS 4 |
| 3498 | .RE |
| 3499 | .IP "\fB\-Wsuggest\-attribute=\fR[\fBpure\fR|\fBconst\fR|\fBnoreturn\fR]" 4 |
| 3500 | .IX Item "-Wsuggest-attribute=[pure|const|noreturn]" |
| 3501 | Warn for cases where adding an attribute may be beneficial. The |
| 3502 | attributes currently supported are listed below. |
| 3503 | .RS 4 |
| 3504 | .IP "\fB\-Wsuggest\-attribute=pure\fR" 4 |
| 3505 | .IX Item "-Wsuggest-attribute=pure" |
| 3506 | .PD 0 |
| 3507 | .IP "\fB\-Wsuggest\-attribute=const\fR" 4 |
| 3508 | .IX Item "-Wsuggest-attribute=const" |
| 3509 | .IP "\fB\-Wsuggest\-attribute=noreturn\fR" 4 |
| 3510 | .IX Item "-Wsuggest-attribute=noreturn" |
| 3511 | .PD |
| 3512 | Warn about functions that might be candidates for attributes |
| 3513 | \&\f(CW\*(C`pure\*(C'\fR, \f(CW\*(C`const\*(C'\fR or \f(CW\*(C`noreturn\*(C'\fR. The compiler only warns for |
| 3514 | functions visible in other compilation units or (in the case of \f(CW\*(C`pure\*(C'\fR and |
| 3515 | \&\f(CW\*(C`const\*(C'\fR) if it cannot prove that the function returns normally. A function |
| 3516 | returns normally if it doesn't contain an infinite loop nor returns abnormally |
| 3517 | by throwing, calling \f(CW\*(C`abort()\*(C'\fR or trapping. This analysis requires option |
| 3518 | \&\fB\-fipa\-pure\-const\fR, which is enabled by default at \fB\-O\fR and |
| 3519 | higher. Higher optimization levels improve the accuracy of the analysis. |
| 3520 | .RE |
| 3521 | .RS 4 |
| 3522 | .RE |
| 3523 | .IP "\fB\-Warray\-bounds\fR" 4 |
| 3524 | .IX Item "-Warray-bounds" |
| 3525 | This option is only active when \fB\-ftree\-vrp\fR is active |
| 3526 | (default for \fB\-O2\fR and above). It warns about subscripts to arrays |
| 3527 | that are always out of bounds. This warning is enabled by \fB\-Wall\fR. |
| 3528 | .IP "\fB\-Wno\-div\-by\-zero\fR" 4 |
| 3529 | .IX Item "-Wno-div-by-zero" |
| 3530 | Do not warn about compile-time integer division by zero. Floating-point |
| 3531 | division by zero is not warned about, as it can be a legitimate way of |
| 3532 | obtaining infinities and NaNs. |
| 3533 | .IP "\fB\-Wsystem\-headers\fR" 4 |
| 3534 | .IX Item "-Wsystem-headers" |
| 3535 | Print warning messages for constructs found in system header files. |
| 3536 | Warnings from system headers are normally suppressed, on the assumption |
| 3537 | that they usually do not indicate real problems and would only make the |
| 3538 | compiler output harder to read. Using this command-line option tells |
| 3539 | \&\s-1GCC\s0 to emit warnings from system headers as if they occurred in user |
| 3540 | code. However, note that using \fB\-Wall\fR in conjunction with this |
| 3541 | option will \fInot\fR warn about unknown pragmas in system |
| 3542 | headers\-\-\-for that, \fB\-Wunknown\-pragmas\fR must also be used. |
| 3543 | .IP "\fB\-Wtrampolines\fR" 4 |
| 3544 | .IX Item "-Wtrampolines" |
| 3545 | .Vb 1 |
| 3546 | \& Warn about trampolines generated for pointers to nested functions. |
| 3547 | \& |
| 3548 | \& A trampoline is a small piece of data or code that is created at run |
| 3549 | \& time on the stack when the address of a nested function is taken, and |
| 3550 | \& is used to call the nested function indirectly. For some targets, it |
| 3551 | \& is made up of data only and thus requires no special treatment. But, |
| 3552 | \& for most targets, it is made up of code and thus requires the stack |
| 3553 | \& to be made executable in order for the program to work properly. |
| 3554 | .Ve |
| 3555 | .IP "\fB\-Wfloat\-equal\fR" 4 |
| 3556 | .IX Item "-Wfloat-equal" |
| 3557 | Warn if floating-point values are used in equality comparisons. |
| 3558 | .Sp |
| 3559 | The idea behind this is that sometimes it is convenient (for the |
| 3560 | programmer) to consider floating-point values as approximations to |
| 3561 | infinitely precise real numbers. If you are doing this, then you need |
| 3562 | to compute (by analyzing the code, or in some other way) the maximum or |
| 3563 | likely maximum error that the computation introduces, and allow for it |
| 3564 | when performing comparisons (and when producing output, but that's a |
| 3565 | different problem). In particular, instead of testing for equality, you |
| 3566 | would check to see whether the two values have ranges that overlap; and |
| 3567 | this is done with the relational operators, so equality comparisons are |
| 3568 | probably mistaken. |
| 3569 | .IP "\fB\-Wtraditional\fR (C and Objective-C only)" 4 |
| 3570 | .IX Item "-Wtraditional (C and Objective-C only)" |
| 3571 | Warn about certain constructs that behave differently in traditional and |
| 3572 | \&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C |
| 3573 | equivalent, and/or problematic constructs that should be avoided. |
| 3574 | .RS 4 |
| 3575 | .IP "\(bu" 4 |
| 3576 | Macro parameters that appear within string literals in the macro body. |
| 3577 | In traditional C macro replacement takes place within string literals, |
| 3578 | but does not in \s-1ISO\s0 C. |
| 3579 | .IP "\(bu" 4 |
| 3580 | In traditional C, some preprocessor directives did not exist. |
| 3581 | Traditional preprocessors would only consider a line to be a directive |
| 3582 | if the \fB#\fR appeared in column 1 on the line. Therefore |
| 3583 | \&\fB\-Wtraditional\fR warns about directives that traditional C |
| 3584 | understands but would ignore because the \fB#\fR does not appear as the |
| 3585 | first character on the line. It also suggests you hide directives like |
| 3586 | \&\fB#pragma\fR not understood by traditional C by indenting them. Some |
| 3587 | traditional implementations would not recognize \fB#elif\fR, so it |
| 3588 | suggests avoiding it altogether. |
| 3589 | .IP "\(bu" 4 |
| 3590 | A function-like macro that appears without arguments. |
| 3591 | .IP "\(bu" 4 |
| 3592 | The unary plus operator. |
| 3593 | .IP "\(bu" 4 |
| 3594 | The \fBU\fR integer constant suffix, or the \fBF\fR or \fBL\fR floating-point |
| 3595 | constant suffixes. (Traditional C does support the \fBL\fR suffix on integer |
| 3596 | constants.) Note, these suffixes appear in macros defined in the system |
| 3597 | headers of most modern systems, e.g. the \fB_MIN\fR/\fB_MAX\fR macros in \f(CW\*(C`<limits.h>\*(C'\fR. |
| 3598 | Use of these macros in user code might normally lead to spurious |
| 3599 | warnings, however \s-1GCC\s0's integrated preprocessor has enough context to |
| 3600 | avoid warning in these cases. |
| 3601 | .IP "\(bu" 4 |
| 3602 | A function declared external in one block and then used after the end of |
| 3603 | the block. |
| 3604 | .IP "\(bu" 4 |
| 3605 | A \f(CW\*(C`switch\*(C'\fR statement has an operand of type \f(CW\*(C`long\*(C'\fR. |
| 3606 | .IP "\(bu" 4 |
| 3607 | A non\-\f(CW\*(C`static\*(C'\fR function declaration follows a \f(CW\*(C`static\*(C'\fR one. |
| 3608 | This construct is not accepted by some traditional C compilers. |
| 3609 | .IP "\(bu" 4 |
| 3610 | The \s-1ISO\s0 type of an integer constant has a different width or |
| 3611 | signedness from its traditional type. This warning is only issued if |
| 3612 | the base of the constant is ten. I.e. hexadecimal or octal values, which |
| 3613 | typically represent bit patterns, are not warned about. |
| 3614 | .IP "\(bu" 4 |
| 3615 | Usage of \s-1ISO\s0 string concatenation is detected. |
| 3616 | .IP "\(bu" 4 |
| 3617 | Initialization of automatic aggregates. |
| 3618 | .IP "\(bu" 4 |
| 3619 | Identifier conflicts with labels. Traditional C lacks a separate |
| 3620 | namespace for labels. |
| 3621 | .IP "\(bu" 4 |
| 3622 | Initialization of unions. If the initializer is zero, the warning is |
| 3623 | omitted. This is done under the assumption that the zero initializer in |
| 3624 | user code appears conditioned on e.g. \f(CW\*(C`_\|_STDC_\|_\*(C'\fR to avoid missing |
| 3625 | initializer warnings and relies on default initialization to zero in the |
| 3626 | traditional C case. |
| 3627 | .IP "\(bu" 4 |
| 3628 | Conversions by prototypes between fixed/floating\-point values and vice |
| 3629 | versa. The absence of these prototypes when compiling with traditional |
| 3630 | C would cause serious problems. This is a subset of the possible |
| 3631 | conversion warnings, for the full set use \fB\-Wtraditional\-conversion\fR. |
| 3632 | .IP "\(bu" 4 |
| 3633 | Use of \s-1ISO\s0 C style function definitions. This warning intentionally is |
| 3634 | \&\fInot\fR issued for prototype declarations or variadic functions |
| 3635 | because these \s-1ISO\s0 C features will appear in your code when using |
| 3636 | libiberty's traditional C compatibility macros, \f(CW\*(C`PARAMS\*(C'\fR and |
| 3637 | \&\f(CW\*(C`VPARAMS\*(C'\fR. This warning is also bypassed for nested functions |
| 3638 | because that feature is already a \s-1GCC\s0 extension and thus not relevant to |
| 3639 | traditional C compatibility. |
| 3640 | .RE |
| 3641 | .RS 4 |
| 3642 | .RE |
| 3643 | .IP "\fB\-Wtraditional\-conversion\fR (C and Objective-C only)" 4 |
| 3644 | .IX Item "-Wtraditional-conversion (C and Objective-C only)" |
| 3645 | Warn if a prototype causes a type conversion that is different from what |
| 3646 | would happen to the same argument in the absence of a prototype. This |
| 3647 | includes conversions of fixed point to floating and vice versa, and |
| 3648 | conversions changing the width or signedness of a fixed-point argument |
| 3649 | except when the same as the default promotion. |
| 3650 | .IP "\fB\-Wdeclaration\-after\-statement\fR (C and Objective-C only)" 4 |
| 3651 | .IX Item "-Wdeclaration-after-statement (C and Objective-C only)" |
| 3652 | Warn when a declaration is found after a statement in a block. This |
| 3653 | construct, known from \*(C+, was introduced with \s-1ISO\s0 C99 and is by default |
| 3654 | allowed in \s-1GCC\s0. It is not supported by \s-1ISO\s0 C90 and was not supported by |
| 3655 | \&\s-1GCC\s0 versions before \s-1GCC\s0 3.0. |
| 3656 | .IP "\fB\-Wundef\fR" 4 |
| 3657 | .IX Item "-Wundef" |
| 3658 | Warn if an undefined identifier is evaluated in an \fB#if\fR directive. |
| 3659 | .IP "\fB\-Wno\-endif\-labels\fR" 4 |
| 3660 | .IX Item "-Wno-endif-labels" |
| 3661 | Do not warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text. |
| 3662 | .IP "\fB\-Wshadow\fR" 4 |
| 3663 | .IX Item "-Wshadow" |
| 3664 | Warn whenever a local variable or type declaration shadows another variable, |
| 3665 | parameter, type, or class member (in \*(C+), or whenever a built-in function |
| 3666 | is shadowed. Note that in \*(C+, the compiler will not warn if a local variable |
| 3667 | shadows a struct/class/enum, but will warn if it shadows an explicit typedef. |
| 3668 | .IP "\fB\-Wlarger\-than=\fR\fIlen\fR" 4 |
| 3669 | .IX Item "-Wlarger-than=len" |
| 3670 | Warn whenever an object of larger than \fIlen\fR bytes is defined. |
| 3671 | .IP "\fB\-Wframe\-larger\-than=\fR\fIlen\fR" 4 |
| 3672 | .IX Item "-Wframe-larger-than=len" |
| 3673 | Warn if the size of a function frame is larger than \fIlen\fR bytes. |
| 3674 | The computation done to determine the stack frame size is approximate |
| 3675 | and not conservative. |
| 3676 | The actual requirements may be somewhat greater than \fIlen\fR |
| 3677 | even if you do not get a warning. In addition, any space allocated |
| 3678 | via \f(CW\*(C`alloca\*(C'\fR, variable-length arrays, or related constructs |
| 3679 | is not included by the compiler when determining |
| 3680 | whether or not to issue a warning. |
| 3681 | .IP "\fB\-Wno\-free\-nonheap\-object\fR" 4 |
| 3682 | .IX Item "-Wno-free-nonheap-object" |
| 3683 | Do not warn when attempting to free an object that was not allocated |
| 3684 | on the heap. |
| 3685 | .IP "\fB\-Wstack\-usage=\fR\fIlen\fR" 4 |
| 3686 | .IX Item "-Wstack-usage=len" |
| 3687 | Warn if the stack usage of a function might be larger than \fIlen\fR bytes. |
| 3688 | The computation done to determine the stack usage is conservative. |
| 3689 | Any space allocated via \f(CW\*(C`alloca\*(C'\fR, variable-length arrays, or related |
| 3690 | constructs is included by the compiler when determining whether or not to |
| 3691 | issue a warning. |
| 3692 | .Sp |
| 3693 | The message is in keeping with the output of \fB\-fstack\-usage\fR. |
| 3694 | .RS 4 |
| 3695 | .IP "\(bu" 4 |
| 3696 | If the stack usage is fully static but exceeds the specified amount, it's: |
| 3697 | .Sp |
| 3698 | .Vb 1 |
| 3699 | \& warning: stack usage is 1120 bytes |
| 3700 | .Ve |
| 3701 | .IP "\(bu" 4 |
| 3702 | If the stack usage is (partly) dynamic but bounded, it's: |
| 3703 | .Sp |
| 3704 | .Vb 1 |
| 3705 | \& warning: stack usage might be 1648 bytes |
| 3706 | .Ve |
| 3707 | .IP "\(bu" 4 |
| 3708 | If the stack usage is (partly) dynamic and not bounded, it's: |
| 3709 | .Sp |
| 3710 | .Vb 1 |
| 3711 | \& warning: stack usage might be unbounded |
| 3712 | .Ve |
| 3713 | .RE |
| 3714 | .RS 4 |
| 3715 | .RE |
| 3716 | .IP "\fB\-Wunsafe\-loop\-optimizations\fR" 4 |
| 3717 | .IX Item "-Wunsafe-loop-optimizations" |
| 3718 | Warn if the loop cannot be optimized because the compiler could not |
| 3719 | assume anything on the bounds of the loop indices. With |
| 3720 | \&\fB\-funsafe\-loop\-optimizations\fR warn if the compiler made |
| 3721 | such assumptions. |
| 3722 | .IP "\fB\-Wno\-pedantic\-ms\-format\fR (MinGW targets only)" 4 |
| 3723 | .IX Item "-Wno-pedantic-ms-format (MinGW targets only)" |
| 3724 | Disables the warnings about non-ISO \f(CW\*(C`printf\*(C'\fR / \f(CW\*(C`scanf\*(C'\fR format |
| 3725 | width specifiers \f(CW\*(C`I32\*(C'\fR, \f(CW\*(C`I64\*(C'\fR, and \f(CW\*(C`I\*(C'\fR used on Windows targets |
| 3726 | depending on the \s-1MS\s0 runtime, when you are using the options \fB\-Wformat\fR |
| 3727 | and \fB\-pedantic\fR without gnu-extensions. |
| 3728 | .IP "\fB\-Wpointer\-arith\fR" 4 |
| 3729 | .IX Item "-Wpointer-arith" |
| 3730 | Warn about anything that depends on the \*(L"size of\*(R" a function type or |
| 3731 | of \f(CW\*(C`void\*(C'\fR. \s-1GNU\s0 C assigns these types a size of 1, for |
| 3732 | convenience in calculations with \f(CW\*(C`void *\*(C'\fR pointers and pointers |
| 3733 | to functions. In \*(C+, warn also when an arithmetic operation involves |
| 3734 | \&\f(CW\*(C`NULL\*(C'\fR. This warning is also enabled by \fB\-pedantic\fR. |
| 3735 | .IP "\fB\-Wtype\-limits\fR" 4 |
| 3736 | .IX Item "-Wtype-limits" |
| 3737 | Warn if a comparison is always true or always false due to the limited |
| 3738 | range of the data type, but do not warn for constant expressions. For |
| 3739 | example, warn if an unsigned variable is compared against zero with |
| 3740 | \&\fB<\fR or \fB>=\fR. This warning is also enabled by |
| 3741 | \&\fB\-Wextra\fR. |
| 3742 | .IP "\fB\-Wbad\-function\-cast\fR (C and Objective-C only)" 4 |
| 3743 | .IX Item "-Wbad-function-cast (C and Objective-C only)" |
| 3744 | Warn whenever a function call is cast to a non-matching type. |
| 3745 | For example, warn if \f(CW\*(C`int malloc()\*(C'\fR is cast to \f(CW\*(C`anything *\*(C'\fR. |
| 3746 | .IP "\fB\-Wc++\-compat\fR (C and Objective-C only)" 4 |
| 3747 | .IX Item "-Wc++-compat (C and Objective-C only)" |
| 3748 | Warn about \s-1ISO\s0 C constructs that are outside of the common subset of |
| 3749 | \&\s-1ISO\s0 C and \s-1ISO\s0 \*(C+, e.g. request for implicit conversion from |
| 3750 | \&\f(CW\*(C`void *\*(C'\fR to a pointer to non\-\f(CW\*(C`void\*(C'\fR type. |
| 3751 | .IP "\fB\-Wc++11\-compat\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 3752 | .IX Item "-Wc++11-compat ( and Objective- only)" |
| 3753 | Warn about \*(C+ constructs whose meaning differs between \s-1ISO\s0 \*(C+ 1998 |
| 3754 | and \s-1ISO\s0 \*(C+ 2011, e.g., identifiers in \s-1ISO\s0 \*(C+ 1998 that are keywords |
| 3755 | in \s-1ISO\s0 \*(C+ 2011. This warning turns on \fB\-Wnarrowing\fR and is |
| 3756 | enabled by \fB\-Wall\fR. |
| 3757 | .IP "\fB\-Wcast\-qual\fR" 4 |
| 3758 | .IX Item "-Wcast-qual" |
| 3759 | Warn whenever a pointer is cast so as to remove a type qualifier from |
| 3760 | the target type. For example, warn if a \f(CW\*(C`const char *\*(C'\fR is cast |
| 3761 | to an ordinary \f(CW\*(C`char *\*(C'\fR. |
| 3762 | .Sp |
| 3763 | Also warn when making a cast that introduces a type qualifier in an |
| 3764 | unsafe way. For example, casting \f(CW\*(C`char **\*(C'\fR to \f(CW\*(C`const char **\*(C'\fR |
| 3765 | is unsafe, as in this example: |
| 3766 | .Sp |
| 3767 | .Vb 6 |
| 3768 | \& /* p is char ** value. */ |
| 3769 | \& const char **q = (const char **) p; |
| 3770 | \& /* Assignment of readonly string to const char * is OK. */ |
| 3771 | \& *q = "string"; |
| 3772 | \& /* Now char** pointer points to read\-only memory. */ |
| 3773 | \& **p = \*(Aqb\*(Aq; |
| 3774 | .Ve |
| 3775 | .IP "\fB\-Wcast\-align\fR" 4 |
| 3776 | .IX Item "-Wcast-align" |
| 3777 | Warn whenever a pointer is cast such that the required alignment of the |
| 3778 | target is increased. For example, warn if a \f(CW\*(C`char *\*(C'\fR is cast to |
| 3779 | an \f(CW\*(C`int *\*(C'\fR on machines where integers can only be accessed at |
| 3780 | two\- or four-byte boundaries. |
| 3781 | .IP "\fB\-Wwrite\-strings\fR" 4 |
| 3782 | .IX Item "-Wwrite-strings" |
| 3783 | When compiling C, give string constants the type \f(CW\*(C`const |
| 3784 | char[\f(CIlength\f(CW]\*(C'\fR so that copying the address of one into a |
| 3785 | non\-\f(CW\*(C`const\*(C'\fR \f(CW\*(C`char *\*(C'\fR pointer will get a warning. These |
| 3786 | warnings will help you find at compile time code that can try to write |
| 3787 | into a string constant, but only if you have been very careful about |
| 3788 | using \f(CW\*(C`const\*(C'\fR in declarations and prototypes. Otherwise, it will |
| 3789 | just be a nuisance. This is why we did not make \fB\-Wall\fR request |
| 3790 | these warnings. |
| 3791 | .Sp |
| 3792 | When compiling \*(C+, warn about the deprecated conversion from string |
| 3793 | literals to \f(CW\*(C`char *\*(C'\fR. This warning is enabled by default for \*(C+ |
| 3794 | programs. |
| 3795 | .IP "\fB\-Wclobbered\fR" 4 |
| 3796 | .IX Item "-Wclobbered" |
| 3797 | Warn for variables that might be changed by \fBlongjmp\fR or |
| 3798 | \&\fBvfork\fR. This warning is also enabled by \fB\-Wextra\fR. |
| 3799 | .IP "\fB\-Wconversion\fR" 4 |
| 3800 | .IX Item "-Wconversion" |
| 3801 | Warn for implicit conversions that may alter a value. This includes |
| 3802 | conversions between real and integer, like \f(CW\*(C`abs (x)\*(C'\fR when |
| 3803 | \&\f(CW\*(C`x\*(C'\fR is \f(CW\*(C`double\*(C'\fR; conversions between signed and unsigned, |
| 3804 | like \f(CW\*(C`unsigned ui = \-1\*(C'\fR; and conversions to smaller types, like |
| 3805 | \&\f(CW\*(C`sqrtf (M_PI)\*(C'\fR. Do not warn for explicit casts like \f(CW\*(C`abs |
| 3806 | ((int) x)\*(C'\fR and \f(CW\*(C`ui = (unsigned) \-1\*(C'\fR, or if the value is not |
| 3807 | changed by the conversion like in \f(CW\*(C`abs (2.0)\*(C'\fR. Warnings about |
| 3808 | conversions between signed and unsigned integers can be disabled by |
| 3809 | using \fB\-Wno\-sign\-conversion\fR. |
| 3810 | .Sp |
| 3811 | For \*(C+, also warn for confusing overload resolution for user-defined |
| 3812 | conversions; and conversions that will never use a type conversion |
| 3813 | operator: conversions to \f(CW\*(C`void\*(C'\fR, the same type, a base class or a |
| 3814 | reference to them. Warnings about conversions between signed and |
| 3815 | unsigned integers are disabled by default in \*(C+ unless |
| 3816 | \&\fB\-Wsign\-conversion\fR is explicitly enabled. |
| 3817 | .IP "\fB\-Wno\-conversion\-null\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 3818 | .IX Item "-Wno-conversion-null ( and Objective- only)" |
| 3819 | Do not warn for conversions between \f(CW\*(C`NULL\*(C'\fR and non-pointer |
| 3820 | types. \fB\-Wconversion\-null\fR is enabled by default. |
| 3821 | .IP "\fB\-Wzero\-as\-null\-pointer\-constant\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 3822 | .IX Item "-Wzero-as-null-pointer-constant ( and Objective- only)" |
| 3823 | Warn when a literal '0' is used as null pointer constant. This can |
| 3824 | be useful to facilitate the conversion to \f(CW\*(C`nullptr\*(C'\fR in \*(C+11. |
| 3825 | .IP "\fB\-Wempty\-body\fR" 4 |
| 3826 | .IX Item "-Wempty-body" |
| 3827 | Warn if an empty body occurs in an \fBif\fR, \fBelse\fR or \fBdo |
| 3828 | while\fR statement. This warning is also enabled by \fB\-Wextra\fR. |
| 3829 | .IP "\fB\-Wenum\-compare\fR" 4 |
| 3830 | .IX Item "-Wenum-compare" |
| 3831 | Warn about a comparison between values of different enumerated types. |
| 3832 | In \*(C+ enumeral mismatches in conditional expressions are also |
| 3833 | diagnosed and the warning is enabled by default. In C this warning is |
| 3834 | enabled by \fB\-Wall\fR. |
| 3835 | .IP "\fB\-Wjump\-misses\-init\fR (C, Objective-C only)" 4 |
| 3836 | .IX Item "-Wjump-misses-init (C, Objective-C only)" |
| 3837 | Warn if a \f(CW\*(C`goto\*(C'\fR statement or a \f(CW\*(C`switch\*(C'\fR statement jumps |
| 3838 | forward across the initialization of a variable, or jumps backward to a |
| 3839 | label after the variable has been initialized. This only warns about |
| 3840 | variables that are initialized when they are declared. This warning is |
| 3841 | only supported for C and Objective-C; in \*(C+ this sort of branch is an |
| 3842 | error in any case. |
| 3843 | .Sp |
| 3844 | \&\fB\-Wjump\-misses\-init\fR is included in \fB\-Wc++\-compat\fR. It |
| 3845 | can be disabled with the \fB\-Wno\-jump\-misses\-init\fR option. |
| 3846 | .IP "\fB\-Wsign\-compare\fR" 4 |
| 3847 | .IX Item "-Wsign-compare" |
| 3848 | Warn when a comparison between signed and unsigned values could produce |
| 3849 | an incorrect result when the signed value is converted to unsigned. |
| 3850 | This warning is also enabled by \fB\-Wextra\fR; to get the other warnings |
| 3851 | of \fB\-Wextra\fR without this warning, use \fB\-Wextra \-Wno\-sign\-compare\fR. |
| 3852 | .IP "\fB\-Wsign\-conversion\fR" 4 |
| 3853 | .IX Item "-Wsign-conversion" |
| 3854 | Warn for implicit conversions that may change the sign of an integer |
| 3855 | value, like assigning a signed integer expression to an unsigned |
| 3856 | integer variable. An explicit cast silences the warning. In C, this |
| 3857 | option is enabled also by \fB\-Wconversion\fR. |
| 3858 | .IP "\fB\-Waddress\fR" 4 |
| 3859 | .IX Item "-Waddress" |
| 3860 | Warn about suspicious uses of memory addresses. These include using |
| 3861 | the address of a function in a conditional expression, such as |
| 3862 | \&\f(CW\*(C`void func(void); if (func)\*(C'\fR, and comparisons against the memory |
| 3863 | address of a string literal, such as \f(CW\*(C`if (x == "abc")\*(C'\fR. Such |
| 3864 | uses typically indicate a programmer error: the address of a function |
| 3865 | always evaluates to true, so their use in a conditional usually |
| 3866 | indicate that the programmer forgot the parentheses in a function |
| 3867 | call; and comparisons against string literals result in unspecified |
| 3868 | behavior and are not portable in C, so they usually indicate that the |
| 3869 | programmer intended to use \f(CW\*(C`strcmp\*(C'\fR. This warning is enabled by |
| 3870 | \&\fB\-Wall\fR. |
| 3871 | .IP "\fB\-Wlogical\-op\fR" 4 |
| 3872 | .IX Item "-Wlogical-op" |
| 3873 | Warn about suspicious uses of logical operators in expressions. |
| 3874 | This includes using logical operators in contexts where a |
| 3875 | bit-wise operator is likely to be expected. |
| 3876 | .IP "\fB\-Waggregate\-return\fR" 4 |
| 3877 | .IX Item "-Waggregate-return" |
| 3878 | Warn if any functions that return structures or unions are defined or |
| 3879 | called. (In languages where you can return an array, this also elicits |
| 3880 | a warning.) |
| 3881 | .IP "\fB\-Wno\-attributes\fR" 4 |
| 3882 | .IX Item "-Wno-attributes" |
| 3883 | Do not warn if an unexpected \f(CW\*(C`_\|_attribute_\|_\*(C'\fR is used, such as |
| 3884 | unrecognized attributes, function attributes applied to variables, |
| 3885 | etc. This will not stop errors for incorrect use of supported |
| 3886 | attributes. |
| 3887 | .IP "\fB\-Wno\-builtin\-macro\-redefined\fR" 4 |
| 3888 | .IX Item "-Wno-builtin-macro-redefined" |
| 3889 | Do not warn if certain built-in macros are redefined. This suppresses |
| 3890 | warnings for redefinition of \f(CW\*(C`_\|_TIMESTAMP_\|_\*(C'\fR, \f(CW\*(C`_\|_TIME_\|_\*(C'\fR, |
| 3891 | \&\f(CW\*(C`_\|_DATE_\|_\*(C'\fR, \f(CW\*(C`_\|_FILE_\|_\*(C'\fR, and \f(CW\*(C`_\|_BASE_FILE_\|_\*(C'\fR. |
| 3892 | .IP "\fB\-Wstrict\-prototypes\fR (C and Objective-C only)" 4 |
| 3893 | .IX Item "-Wstrict-prototypes (C and Objective-C only)" |
| 3894 | Warn if a function is declared or defined without specifying the |
| 3895 | argument types. (An old-style function definition is permitted without |
| 3896 | a warning if preceded by a declaration that specifies the argument |
| 3897 | types.) |
| 3898 | .IP "\fB\-Wold\-style\-declaration\fR (C and Objective-C only)" 4 |
| 3899 | .IX Item "-Wold-style-declaration (C and Objective-C only)" |
| 3900 | Warn for obsolescent usages, according to the C Standard, in a |
| 3901 | declaration. For example, warn if storage-class specifiers like |
| 3902 | \&\f(CW\*(C`static\*(C'\fR are not the first things in a declaration. This warning |
| 3903 | is also enabled by \fB\-Wextra\fR. |
| 3904 | .IP "\fB\-Wold\-style\-definition\fR (C and Objective-C only)" 4 |
| 3905 | .IX Item "-Wold-style-definition (C and Objective-C only)" |
| 3906 | Warn if an old-style function definition is used. A warning is given |
| 3907 | even if there is a previous prototype. |
| 3908 | .IP "\fB\-Wmissing\-parameter\-type\fR (C and Objective-C only)" 4 |
| 3909 | .IX Item "-Wmissing-parameter-type (C and Objective-C only)" |
| 3910 | A function parameter is declared without a type specifier in K&R\-style |
| 3911 | functions: |
| 3912 | .Sp |
| 3913 | .Vb 1 |
| 3914 | \& void foo(bar) { } |
| 3915 | .Ve |
| 3916 | .Sp |
| 3917 | This warning is also enabled by \fB\-Wextra\fR. |
| 3918 | .IP "\fB\-Wmissing\-prototypes\fR (C and Objective-C only)" 4 |
| 3919 | .IX Item "-Wmissing-prototypes (C and Objective-C only)" |
| 3920 | Warn if a global function is defined without a previous prototype |
| 3921 | declaration. This warning is issued even if the definition itself |
| 3922 | provides a prototype. The aim is to detect global functions that |
| 3923 | are not declared in header files. |
| 3924 | .IP "\fB\-Wmissing\-declarations\fR" 4 |
| 3925 | .IX Item "-Wmissing-declarations" |
| 3926 | Warn if a global function is defined without a previous declaration. |
| 3927 | Do so even if the definition itself provides a prototype. |
| 3928 | Use this option to detect global functions that are not declared in |
| 3929 | header files. In \*(C+, no warnings are issued for function templates, |
| 3930 | or for inline functions, or for functions in anonymous namespaces. |
| 3931 | .IP "\fB\-Wmissing\-field\-initializers\fR" 4 |
| 3932 | .IX Item "-Wmissing-field-initializers" |
| 3933 | Warn if a structure's initializer has some fields missing. For |
| 3934 | example, the following code would cause such a warning, because |
| 3935 | \&\f(CW\*(C`x.h\*(C'\fR is implicitly zero: |
| 3936 | .Sp |
| 3937 | .Vb 2 |
| 3938 | \& struct s { int f, g, h; }; |
| 3939 | \& struct s x = { 3, 4 }; |
| 3940 | .Ve |
| 3941 | .Sp |
| 3942 | This option does not warn about designated initializers, so the following |
| 3943 | modification would not trigger a warning: |
| 3944 | .Sp |
| 3945 | .Vb 2 |
| 3946 | \& struct s { int f, g, h; }; |
| 3947 | \& struct s x = { .f = 3, .g = 4 }; |
| 3948 | .Ve |
| 3949 | .Sp |
| 3950 | This warning is included in \fB\-Wextra\fR. To get other \fB\-Wextra\fR |
| 3951 | warnings without this one, use \fB\-Wextra \-Wno\-missing\-field\-initializers\fR. |
| 3952 | .IP "\fB\-Wmissing\-format\-attribute\fR" 4 |
| 3953 | .IX Item "-Wmissing-format-attribute" |
| 3954 | Warn about function pointers that might be candidates for \f(CW\*(C`format\*(C'\fR |
| 3955 | attributes. Note these are only possible candidates, not absolute ones. |
| 3956 | \&\s-1GCC\s0 will guess that function pointers with \f(CW\*(C`format\*(C'\fR attributes that |
| 3957 | are used in assignment, initialization, parameter passing or return |
| 3958 | statements should have a corresponding \f(CW\*(C`format\*(C'\fR attribute in the |
| 3959 | resulting type. I.e. the left-hand side of the assignment or |
| 3960 | initialization, the type of the parameter variable, or the return type |
| 3961 | of the containing function respectively should also have a \f(CW\*(C`format\*(C'\fR |
| 3962 | attribute to avoid the warning. |
| 3963 | .Sp |
| 3964 | \&\s-1GCC\s0 will also warn about function definitions that might be |
| 3965 | candidates for \f(CW\*(C`format\*(C'\fR attributes. Again, these are only |
| 3966 | possible candidates. \s-1GCC\s0 will guess that \f(CW\*(C`format\*(C'\fR attributes |
| 3967 | might be appropriate for any function that calls a function like |
| 3968 | \&\f(CW\*(C`vprintf\*(C'\fR or \f(CW\*(C`vscanf\*(C'\fR, but this might not always be the |
| 3969 | case, and some functions for which \f(CW\*(C`format\*(C'\fR attributes are |
| 3970 | appropriate may not be detected. |
| 3971 | .IP "\fB\-Wno\-multichar\fR" 4 |
| 3972 | .IX Item "-Wno-multichar" |
| 3973 | Do not warn if a multicharacter constant (\fB'\s-1FOOF\s0'\fR) is used. |
| 3974 | Usually they indicate a typo in the user's code, as they have |
| 3975 | implementation-defined values, and should not be used in portable code. |
| 3976 | .IP "\fB\-Wnormalized=<none|id|nfc|nfkc>\fR" 4 |
| 3977 | .IX Item "-Wnormalized=<none|id|nfc|nfkc>" |
| 3978 | In \s-1ISO\s0 C and \s-1ISO\s0 \*(C+, two identifiers are different if they are |
| 3979 | different sequences of characters. However, sometimes when characters |
| 3980 | outside the basic \s-1ASCII\s0 character set are used, you can have two |
| 3981 | different character sequences that look the same. To avoid confusion, |
| 3982 | the \s-1ISO\s0 10646 standard sets out some \fInormalization rules\fR which |
| 3983 | when applied ensure that two sequences that look the same are turned into |
| 3984 | the same sequence. \s-1GCC\s0 can warn you if you are using identifiers that |
| 3985 | have not been normalized; this option controls that warning. |
| 3986 | .Sp |
| 3987 | There are four levels of warning supported by \s-1GCC\s0. The default is |
| 3988 | \&\fB\-Wnormalized=nfc\fR, which warns about any identifier that is |
| 3989 | not in the \s-1ISO\s0 10646 \*(L"C\*(R" normalized form, \fI\s-1NFC\s0\fR. \s-1NFC\s0 is the |
| 3990 | recommended form for most uses. |
| 3991 | .Sp |
| 3992 | Unfortunately, there are some characters allowed in identifiers by |
| 3993 | \&\s-1ISO\s0 C and \s-1ISO\s0 \*(C+ that, when turned into \s-1NFC\s0, are not allowed in |
| 3994 | identifiers. That is, there's no way to use these symbols in portable |
| 3995 | \&\s-1ISO\s0 C or \*(C+ and have all your identifiers in \s-1NFC\s0. |
| 3996 | \&\fB\-Wnormalized=id\fR suppresses the warning for these characters. |
| 3997 | It is hoped that future versions of the standards involved will correct |
| 3998 | this, which is why this option is not the default. |
| 3999 | .Sp |
| 4000 | You can switch the warning off for all characters by writing |
| 4001 | \&\fB\-Wnormalized=none\fR. You would only want to do this if you |
| 4002 | were using some other normalization scheme (like \*(L"D\*(R"), because |
| 4003 | otherwise you can easily create bugs that are literally impossible to see. |
| 4004 | .Sp |
| 4005 | Some characters in \s-1ISO\s0 10646 have distinct meanings but look identical |
| 4006 | in some fonts or display methodologies, especially once formatting has |
| 4007 | been applied. For instance \f(CW\*(C`\eu207F\*(C'\fR, \*(L"\s-1SUPERSCRIPT\s0 \s-1LATIN\s0 \s-1SMALL\s0 |
| 4008 | \&\s-1LETTER\s0 N\*(R", will display just like a regular \f(CW\*(C`n\*(C'\fR that has been |
| 4009 | placed in a superscript. \s-1ISO\s0 10646 defines the \fI\s-1NFKC\s0\fR |
| 4010 | normalization scheme to convert all these into a standard form as |
| 4011 | well, and \s-1GCC\s0 will warn if your code is not in \s-1NFKC\s0 if you use |
| 4012 | \&\fB\-Wnormalized=nfkc\fR. This warning is comparable to warning |
| 4013 | about every identifier that contains the letter O because it might be |
| 4014 | confused with the digit 0, and so is not the default, but may be |
| 4015 | useful as a local coding convention if the programming environment is |
| 4016 | unable to be fixed to display these characters distinctly. |
| 4017 | .IP "\fB\-Wno\-deprecated\fR" 4 |
| 4018 | .IX Item "-Wno-deprecated" |
| 4019 | Do not warn about usage of deprecated features. |
| 4020 | .IP "\fB\-Wno\-deprecated\-declarations\fR" 4 |
| 4021 | .IX Item "-Wno-deprecated-declarations" |
| 4022 | Do not warn about uses of functions, |
| 4023 | variables, and types marked as deprecated by using the \f(CW\*(C`deprecated\*(C'\fR |
| 4024 | attribute. |
| 4025 | .IP "\fB\-Wno\-overflow\fR" 4 |
| 4026 | .IX Item "-Wno-overflow" |
| 4027 | Do not warn about compile-time overflow in constant expressions. |
| 4028 | .IP "\fB\-Woverride\-init\fR (C and Objective-C only)" 4 |
| 4029 | .IX Item "-Woverride-init (C and Objective-C only)" |
| 4030 | Warn if an initialized field without side effects is overridden when |
| 4031 | using designated initializers. |
| 4032 | .Sp |
| 4033 | This warning is included in \fB\-Wextra\fR. To get other |
| 4034 | \&\fB\-Wextra\fR warnings without this one, use \fB\-Wextra |
| 4035 | \&\-Wno\-override\-init\fR. |
| 4036 | .IP "\fB\-Wpacked\fR" 4 |
| 4037 | .IX Item "-Wpacked" |
| 4038 | Warn if a structure is given the packed attribute, but the packed |
| 4039 | attribute has no effect on the layout or size of the structure. |
| 4040 | Such structures may be mis-aligned for little benefit. For |
| 4041 | instance, in this code, the variable \f(CW\*(C`f.x\*(C'\fR in \f(CW\*(C`struct bar\*(C'\fR |
| 4042 | will be misaligned even though \f(CW\*(C`struct bar\*(C'\fR does not itself |
| 4043 | have the packed attribute: |
| 4044 | .Sp |
| 4045 | .Vb 8 |
| 4046 | \& struct foo { |
| 4047 | \& int x; |
| 4048 | \& char a, b, c, d; |
| 4049 | \& } _\|_attribute_\|_((packed)); |
| 4050 | \& struct bar { |
| 4051 | \& char z; |
| 4052 | \& struct foo f; |
| 4053 | \& }; |
| 4054 | .Ve |
| 4055 | .IP "\fB\-Wpacked\-bitfield\-compat\fR" 4 |
| 4056 | .IX Item "-Wpacked-bitfield-compat" |
| 4057 | The 4.1, 4.2 and 4.3 series of \s-1GCC\s0 ignore the \f(CW\*(C`packed\*(C'\fR attribute |
| 4058 | on bit-fields of type \f(CW\*(C`char\*(C'\fR. This has been fixed in \s-1GCC\s0 4.4 but |
| 4059 | the change can lead to differences in the structure layout. \s-1GCC\s0 |
| 4060 | informs you when the offset of such a field has changed in \s-1GCC\s0 4.4. |
| 4061 | For example there is no longer a 4\-bit padding between field \f(CW\*(C`a\*(C'\fR |
| 4062 | and \f(CW\*(C`b\*(C'\fR in this structure: |
| 4063 | .Sp |
| 4064 | .Vb 5 |
| 4065 | \& struct foo |
| 4066 | \& { |
| 4067 | \& char a:4; |
| 4068 | \& char b:8; |
| 4069 | \& } _\|_attribute_\|_ ((packed)); |
| 4070 | .Ve |
| 4071 | .Sp |
| 4072 | This warning is enabled by default. Use |
| 4073 | \&\fB\-Wno\-packed\-bitfield\-compat\fR to disable this warning. |
| 4074 | .IP "\fB\-Wpadded\fR" 4 |
| 4075 | .IX Item "-Wpadded" |
| 4076 | Warn if padding is included in a structure, either to align an element |
| 4077 | of the structure or to align the whole structure. Sometimes when this |
| 4078 | happens it is possible to rearrange the fields of the structure to |
| 4079 | reduce the padding and so make the structure smaller. |
| 4080 | .IP "\fB\-Wredundant\-decls\fR" 4 |
| 4081 | .IX Item "-Wredundant-decls" |
| 4082 | Warn if anything is declared more than once in the same scope, even in |
| 4083 | cases where multiple declaration is valid and changes nothing. |
| 4084 | .IP "\fB\-Wnested\-externs\fR (C and Objective-C only)" 4 |
| 4085 | .IX Item "-Wnested-externs (C and Objective-C only)" |
| 4086 | Warn if an \f(CW\*(C`extern\*(C'\fR declaration is encountered within a function. |
| 4087 | .IP "\fB\-Winline\fR" 4 |
| 4088 | .IX Item "-Winline" |
| 4089 | Warn if a function can not be inlined and it was declared as inline. |
| 4090 | Even with this option, the compiler will not warn about failures to |
| 4091 | inline functions declared in system headers. |
| 4092 | .Sp |
| 4093 | The compiler uses a variety of heuristics to determine whether or not |
| 4094 | to inline a function. For example, the compiler takes into account |
| 4095 | the size of the function being inlined and the amount of inlining |
| 4096 | that has already been done in the current function. Therefore, |
| 4097 | seemingly insignificant changes in the source program can cause the |
| 4098 | warnings produced by \fB\-Winline\fR to appear or disappear. |
| 4099 | .IP "\fB\-Wno\-invalid\-offsetof\fR (\*(C+ and Objective\-\*(C+ only)" 4 |
| 4100 | .IX Item "-Wno-invalid-offsetof ( and Objective- only)" |
| 4101 | Suppress warnings from applying the \fBoffsetof\fR macro to a non-POD |
| 4102 | type. According to the 1998 \s-1ISO\s0 \*(C+ standard, applying \fBoffsetof\fR |
| 4103 | to a non-POD type is undefined. In existing \*(C+ implementations, |
| 4104 | however, \fBoffsetof\fR typically gives meaningful results even when |
| 4105 | applied to certain kinds of non-POD types. (Such as a simple |
| 4106 | \&\fBstruct\fR that fails to be a \s-1POD\s0 type only by virtue of having a |
| 4107 | constructor.) This flag is for users who are aware that they are |
| 4108 | writing nonportable code and who have deliberately chosen to ignore the |
| 4109 | warning about it. |
| 4110 | .Sp |
| 4111 | The restrictions on \fBoffsetof\fR may be relaxed in a future version |
| 4112 | of the \*(C+ standard. |
| 4113 | .IP "\fB\-Wno\-int\-to\-pointer\-cast\fR" 4 |
| 4114 | .IX Item "-Wno-int-to-pointer-cast" |
| 4115 | Suppress warnings from casts to pointer type of an integer of a |
| 4116 | different size. In \*(C+, casting to a pointer type of smaller size is |
| 4117 | an error. \fBWint-to-pointer-cast\fR is enabled by default. |
| 4118 | .IP "\fB\-Wno\-pointer\-to\-int\-cast\fR (C and Objective-C only)" 4 |
| 4119 | .IX Item "-Wno-pointer-to-int-cast (C and Objective-C only)" |
| 4120 | Suppress warnings from casts from a pointer to an integer type of a |
| 4121 | different size. |
| 4122 | .IP "\fB\-Winvalid\-pch\fR" 4 |
| 4123 | .IX Item "-Winvalid-pch" |
| 4124 | Warn if a precompiled header is found in |
| 4125 | the search path but can't be used. |
| 4126 | .IP "\fB\-Wlong\-long\fR" 4 |
| 4127 | .IX Item "-Wlong-long" |
| 4128 | Warn if \fBlong long\fR type is used. This is enabled by either |
| 4129 | \&\fB\-pedantic\fR or \fB\-Wtraditional\fR in \s-1ISO\s0 C90 and \*(C+98 |
| 4130 | modes. To inhibit the warning messages, use \fB\-Wno\-long\-long\fR. |
| 4131 | .IP "\fB\-Wvariadic\-macros\fR" 4 |
| 4132 | .IX Item "-Wvariadic-macros" |
| 4133 | Warn if variadic macros are used in pedantic \s-1ISO\s0 C90 mode, or the \s-1GNU\s0 |
| 4134 | alternate syntax when in pedantic \s-1ISO\s0 C99 mode. This is default. |
| 4135 | To inhibit the warning messages, use \fB\-Wno\-variadic\-macros\fR. |
| 4136 | .IP "\fB\-Wvector\-operation\-performance\fR" 4 |
| 4137 | .IX Item "-Wvector-operation-performance" |
| 4138 | Warn if vector operation is not implemented via \s-1SIMD\s0 capabilities of the |
| 4139 | architecture. Mainly useful for the performance tuning. |
| 4140 | Vector operation can be implemented \f(CW\*(C`piecewise\*(C'\fR, which means that the |
| 4141 | scalar operation is performed on every vector element; |
| 4142 | \&\f(CW\*(C`in parallel\*(C'\fR, which means that the vector operation is implemented |
| 4143 | using scalars of wider type, which normally is more performance efficient; |
| 4144 | and \f(CW\*(C`as a single scalar\*(C'\fR, which means that vector fits into a |
| 4145 | scalar type. |
| 4146 | .IP "\fB\-Wvla\fR" 4 |
| 4147 | .IX Item "-Wvla" |
| 4148 | Warn if variable length array is used in the code. |
| 4149 | \&\fB\-Wno\-vla\fR will prevent the \fB\-pedantic\fR warning of |
| 4150 | the variable length array. |
| 4151 | .IP "\fB\-Wvolatile\-register\-var\fR" 4 |
| 4152 | .IX Item "-Wvolatile-register-var" |
| 4153 | Warn if a register variable is declared volatile. The volatile |
| 4154 | modifier does not inhibit all optimizations that may eliminate reads |
| 4155 | and/or writes to register variables. This warning is enabled by |
| 4156 | \&\fB\-Wall\fR. |
| 4157 | .IP "\fB\-Wdisabled\-optimization\fR" 4 |
| 4158 | .IX Item "-Wdisabled-optimization" |
| 4159 | Warn if a requested optimization pass is disabled. This warning does |
| 4160 | not generally indicate that there is anything wrong with your code; it |
| 4161 | merely indicates that \s-1GCC\s0's optimizers were unable to handle the code |
| 4162 | effectively. Often, the problem is that your code is too big or too |
| 4163 | complex; \s-1GCC\s0 will refuse to optimize programs when the optimization |
| 4164 | itself is likely to take inordinate amounts of time. |
| 4165 | .IP "\fB\-Wpointer\-sign\fR (C and Objective-C only)" 4 |
| 4166 | .IX Item "-Wpointer-sign (C and Objective-C only)" |
| 4167 | Warn for pointer argument passing or assignment with different signedness. |
| 4168 | This option is only supported for C and Objective-C. It is implied by |
| 4169 | \&\fB\-Wall\fR and by \fB\-pedantic\fR, which can be disabled with |
| 4170 | \&\fB\-Wno\-pointer\-sign\fR. |
| 4171 | .IP "\fB\-Wstack\-protector\fR" 4 |
| 4172 | .IX Item "-Wstack-protector" |
| 4173 | This option is only active when \fB\-fstack\-protector\fR is active. It |
| 4174 | warns about functions that will not be protected against stack smashing. |
| 4175 | .IP "\fB\-Wno\-mudflap\fR" 4 |
| 4176 | .IX Item "-Wno-mudflap" |
| 4177 | Suppress warnings about constructs that cannot be instrumented by |
| 4178 | \&\fB\-fmudflap\fR. |
| 4179 | .IP "\fB\-Woverlength\-strings\fR" 4 |
| 4180 | .IX Item "-Woverlength-strings" |
| 4181 | Warn about string constants that are longer than the \*(L"minimum |
| 4182 | maximum\*(R" length specified in the C standard. Modern compilers |
| 4183 | generally allow string constants that are much longer than the |
| 4184 | standard's minimum limit, but very portable programs should avoid |
| 4185 | using longer strings. |
| 4186 | .Sp |
| 4187 | The limit applies \fIafter\fR string constant concatenation, and does |
| 4188 | not count the trailing \s-1NUL\s0. In C90, the limit was 509 characters; in |
| 4189 | C99, it was raised to 4095. \*(C+98 does not specify a normative |
| 4190 | minimum maximum, so we do not diagnose overlength strings in \*(C+. |
| 4191 | .Sp |
| 4192 | This option is implied by \fB\-pedantic\fR, and can be disabled with |
| 4193 | \&\fB\-Wno\-overlength\-strings\fR. |
| 4194 | .IP "\fB\-Wunsuffixed\-float\-constants\fR (C and Objective-C only)" 4 |
| 4195 | .IX Item "-Wunsuffixed-float-constants (C and Objective-C only)" |
| 4196 | \&\s-1GCC\s0 will issue a warning for any floating constant that does not have |
| 4197 | a suffix. When used together with \fB\-Wsystem\-headers\fR it will |
| 4198 | warn about such constants in system header files. This can be useful |
| 4199 | when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma |
| 4200 | from the decimal floating-point extension to C99. |
| 4201 | .Sh "Options for Debugging Your Program or \s-1GCC\s0" |
| 4202 | .IX Subsection "Options for Debugging Your Program or GCC" |
| 4203 | \&\s-1GCC\s0 has various special options that are used for debugging |
| 4204 | either your program or \s-1GCC:\s0 |
| 4205 | .IP "\fB\-g\fR" 4 |
| 4206 | .IX Item "-g" |
| 4207 | Produce debugging information in the operating system's native format |
| 4208 | (stabs, \s-1COFF\s0, \s-1XCOFF\s0, or \s-1DWARF\s0 2). \s-1GDB\s0 can work with this debugging |
| 4209 | information. |
| 4210 | .Sp |
| 4211 | On most systems that use stabs format, \fB\-g\fR enables use of extra |
| 4212 | debugging information that only \s-1GDB\s0 can use; this extra information |
| 4213 | makes debugging work better in \s-1GDB\s0 but will probably make other debuggers |
| 4214 | crash or |
| 4215 | refuse to read the program. If you want to control for certain whether |
| 4216 | to generate the extra information, use \fB\-gstabs+\fR, \fB\-gstabs\fR, |
| 4217 | \&\fB\-gxcoff+\fR, \fB\-gxcoff\fR, or \fB\-gvms\fR (see below). |
| 4218 | .Sp |
| 4219 | \&\s-1GCC\s0 allows you to use \fB\-g\fR with |
| 4220 | \&\fB\-O\fR. The shortcuts taken by optimized code may occasionally |
| 4221 | produce surprising results: some variables you declared may not exist |
| 4222 | at all; flow of control may briefly move where you did not expect it; |
| 4223 | some statements may not be executed because they compute constant |
| 4224 | results or their values were already at hand; some statements may |
| 4225 | execute in different places because they were moved out of loops. |
| 4226 | .Sp |
| 4227 | Nevertheless it proves possible to debug optimized output. This makes |
| 4228 | it reasonable to use the optimizer for programs that might have bugs. |
| 4229 | .Sp |
| 4230 | The following options are useful when \s-1GCC\s0 is generated with the |
| 4231 | capability for more than one debugging format. |
| 4232 | .IP "\fB\-ggdb\fR" 4 |
| 4233 | .IX Item "-ggdb" |
| 4234 | Produce debugging information for use by \s-1GDB\s0. This means to use the |
| 4235 | most expressive format available (\s-1DWARF\s0 2, stabs, or the native format |
| 4236 | if neither of those are supported), including \s-1GDB\s0 extensions if at all |
| 4237 | possible. |
| 4238 | .IP "\fB\-gstabs\fR" 4 |
| 4239 | .IX Item "-gstabs" |
| 4240 | Produce debugging information in stabs format (if that is supported), |
| 4241 | without \s-1GDB\s0 extensions. This is the format used by \s-1DBX\s0 on most \s-1BSD\s0 |
| 4242 | systems. On \s-1MIPS\s0, Alpha and System V Release 4 systems this option |
| 4243 | produces stabs debugging output that is not understood by \s-1DBX\s0 or \s-1SDB\s0. |
| 4244 | On System V Release 4 systems this option requires the \s-1GNU\s0 assembler. |
| 4245 | .IP "\fB\-feliminate\-unused\-debug\-symbols\fR" 4 |
| 4246 | .IX Item "-feliminate-unused-debug-symbols" |
| 4247 | Produce debugging information in stabs format (if that is supported), |
| 4248 | for only symbols that are actually used. |
| 4249 | .IP "\fB\-femit\-class\-debug\-always\fR" 4 |
| 4250 | .IX Item "-femit-class-debug-always" |
| 4251 | Instead of emitting debugging information for a \*(C+ class in only one |
| 4252 | object file, emit it in all object files using the class. This option |
| 4253 | should be used only with debuggers that are unable to handle the way \s-1GCC\s0 |
| 4254 | normally emits debugging information for classes because using this |
| 4255 | option will increase the size of debugging information by as much as a |
| 4256 | factor of two. |
| 4257 | .IP "\fB\-fno\-debug\-types\-section\fR" 4 |
| 4258 | .IX Item "-fno-debug-types-section" |
| 4259 | By default when using \s-1DWARF\s0 v4 or higher type DIEs will be put into |
| 4260 | their own .debug_types section instead of making them part of the |
| 4261 | \&.debug_info section. It is more efficient to put them in a separate |
| 4262 | comdat sections since the linker will then be able to remove duplicates. |
| 4263 | But not all \s-1DWARF\s0 consumers support .debug_types sections yet. |
| 4264 | .IP "\fB\-gstabs+\fR" 4 |
| 4265 | .IX Item "-gstabs+" |
| 4266 | Produce debugging information in stabs format (if that is supported), |
| 4267 | using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The |
| 4268 | use of these extensions is likely to make other debuggers crash or |
| 4269 | refuse to read the program. |
| 4270 | .IP "\fB\-gcoff\fR" 4 |
| 4271 | .IX Item "-gcoff" |
| 4272 | Produce debugging information in \s-1COFF\s0 format (if that is supported). |
| 4273 | This is the format used by \s-1SDB\s0 on most System V systems prior to |
| 4274 | System V Release 4. |
| 4275 | .IP "\fB\-gxcoff\fR" 4 |
| 4276 | .IX Item "-gxcoff" |
| 4277 | Produce debugging information in \s-1XCOFF\s0 format (if that is supported). |
| 4278 | This is the format used by the \s-1DBX\s0 debugger on \s-1IBM\s0 \s-1RS/6000\s0 systems. |
| 4279 | .IP "\fB\-gxcoff+\fR" 4 |
| 4280 | .IX Item "-gxcoff+" |
| 4281 | Produce debugging information in \s-1XCOFF\s0 format (if that is supported), |
| 4282 | using \s-1GNU\s0 extensions understood only by the \s-1GNU\s0 debugger (\s-1GDB\s0). The |
| 4283 | use of these extensions is likely to make other debuggers crash or |
| 4284 | refuse to read the program, and may cause assemblers other than the \s-1GNU\s0 |
| 4285 | assembler (\s-1GAS\s0) to fail with an error. |
| 4286 | .IP "\fB\-gdwarf\-\fR\fIversion\fR" 4 |
| 4287 | .IX Item "-gdwarf-version" |
| 4288 | Produce debugging information in \s-1DWARF\s0 format (if that is |
| 4289 | supported). This is the format used by \s-1DBX\s0 on \s-1IRIX\s0 6. The value |
| 4290 | of \fIversion\fR may be either 2, 3 or 4; the default version is 2. |
| 4291 | .Sp |
| 4292 | Note that with \s-1DWARF\s0 version 2 some ports require, and will always |
| 4293 | use, some non-conflicting \s-1DWARF\s0 3 extensions in the unwind tables. |
| 4294 | .Sp |
| 4295 | Version 4 may require \s-1GDB\s0 7.0 and \fB\-fvar\-tracking\-assignments\fR |
| 4296 | for maximum benefit. |
| 4297 | .IP "\fB\-grecord\-gcc\-switches\fR" 4 |
| 4298 | .IX Item "-grecord-gcc-switches" |
| 4299 | This switch causes the command-line options used to invoke the |
| 4300 | compiler that may affect code generation to be appended to the |
| 4301 | DW_AT_producer attribute in \s-1DWARF\s0 debugging information. The options |
| 4302 | are concatenated with spaces separating them from each other and from |
| 4303 | the compiler version. See also \fB\-frecord\-gcc\-switches\fR for another |
| 4304 | way of storing compiler options into the object file. |
| 4305 | .IP "\fB\-gno\-record\-gcc\-switches\fR" 4 |
| 4306 | .IX Item "-gno-record-gcc-switches" |
| 4307 | Disallow appending command-line options to the DW_AT_producer attribute |
| 4308 | in \s-1DWARF\s0 debugging information. This is the default. |
| 4309 | .IP "\fB\-gstrict\-dwarf\fR" 4 |
| 4310 | .IX Item "-gstrict-dwarf" |
| 4311 | Disallow using extensions of later \s-1DWARF\s0 standard version than selected |
| 4312 | with \fB\-gdwarf\-\fR\fIversion\fR. On most targets using non-conflicting |
| 4313 | \&\s-1DWARF\s0 extensions from later standard versions is allowed. |
| 4314 | .IP "\fB\-gno\-strict\-dwarf\fR" 4 |
| 4315 | .IX Item "-gno-strict-dwarf" |
| 4316 | Allow using extensions of later \s-1DWARF\s0 standard version than selected with |
| 4317 | \&\fB\-gdwarf\-\fR\fIversion\fR. |
| 4318 | .IP "\fB\-gvms\fR" 4 |
| 4319 | .IX Item "-gvms" |
| 4320 | Produce debugging information in \s-1VMS\s0 debug format (if that is |
| 4321 | supported). This is the format used by \s-1DEBUG\s0 on \s-1VMS\s0 systems. |
| 4322 | .IP "\fB\-g\fR\fIlevel\fR" 4 |
| 4323 | .IX Item "-glevel" |
| 4324 | .PD 0 |
| 4325 | .IP "\fB\-ggdb\fR\fIlevel\fR" 4 |
| 4326 | .IX Item "-ggdblevel" |
| 4327 | .IP "\fB\-gstabs\fR\fIlevel\fR" 4 |
| 4328 | .IX Item "-gstabslevel" |
| 4329 | .IP "\fB\-gcoff\fR\fIlevel\fR" 4 |
| 4330 | .IX Item "-gcofflevel" |
| 4331 | .IP "\fB\-gxcoff\fR\fIlevel\fR" 4 |
| 4332 | .IX Item "-gxcofflevel" |
| 4333 | .IP "\fB\-gvms\fR\fIlevel\fR" 4 |
| 4334 | .IX Item "-gvmslevel" |
| 4335 | .PD |
| 4336 | Request debugging information and also use \fIlevel\fR to specify how |
| 4337 | much information. The default level is 2. |
| 4338 | .Sp |
| 4339 | Level 0 produces no debug information at all. Thus, \fB\-g0\fR negates |
| 4340 | \&\fB\-g\fR. |
| 4341 | .Sp |
| 4342 | Level 1 produces minimal information, enough for making backtraces in |
| 4343 | parts of the program that you don't plan to debug. This includes |
| 4344 | descriptions of functions and external variables, but no information |
| 4345 | about local variables and no line numbers. |
| 4346 | .Sp |
| 4347 | Level 3 includes extra information, such as all the macro definitions |
| 4348 | present in the program. Some debuggers support macro expansion when |
| 4349 | you use \fB\-g3\fR. |
| 4350 | .Sp |
| 4351 | \&\fB\-gdwarf\-2\fR does not accept a concatenated debug level, because |
| 4352 | \&\s-1GCC\s0 used to support an option \fB\-gdwarf\fR that meant to generate |
| 4353 | debug information in version 1 of the \s-1DWARF\s0 format (which is very |
| 4354 | different from version 2), and it would have been too confusing. That |
| 4355 | debug format is long obsolete, but the option cannot be changed now. |
| 4356 | Instead use an additional \fB\-g\fR\fIlevel\fR option to change the |
| 4357 | debug level for \s-1DWARF\s0. |
| 4358 | .IP "\fB\-gtoggle\fR" 4 |
| 4359 | .IX Item "-gtoggle" |
| 4360 | Turn off generation of debug info, if leaving out this option would have |
| 4361 | generated it, or turn it on at level 2 otherwise. The position of this |
| 4362 | argument in the command line does not matter, it takes effect after all |
| 4363 | other options are processed, and it does so only once, no matter how |
| 4364 | many times it is given. This is mainly intended to be used with |
| 4365 | \&\fB\-fcompare\-debug\fR. |
| 4366 | .IP "\fB\-fdump\-final\-insns\fR[\fB=\fR\fIfile\fR]" 4 |
| 4367 | .IX Item "-fdump-final-insns[=file]" |
| 4368 | Dump the final internal representation (\s-1RTL\s0) to \fIfile\fR. If the |
| 4369 | optional argument is omitted (or if \fIfile\fR is \f(CW\*(C`.\*(C'\fR), the name |
| 4370 | of the dump file will be determined by appending \f(CW\*(C`.gkd\*(C'\fR to the |
| 4371 | compilation output file name. |
| 4372 | .IP "\fB\-fcompare\-debug\fR[\fB=\fR\fIopts\fR]" 4 |
| 4373 | .IX Item "-fcompare-debug[=opts]" |
| 4374 | If no error occurs during compilation, run the compiler a second time, |
| 4375 | adding \fIopts\fR and \fB\-fcompare\-debug\-second\fR to the arguments |
| 4376 | passed to the second compilation. Dump the final internal |
| 4377 | representation in both compilations, and print an error if they differ. |
| 4378 | .Sp |
| 4379 | If the equal sign is omitted, the default \fB\-gtoggle\fR is used. |
| 4380 | .Sp |
| 4381 | The environment variable \fB\s-1GCC_COMPARE_DEBUG\s0\fR, if defined, non-empty |
| 4382 | and nonzero, implicitly enables \fB\-fcompare\-debug\fR. If |
| 4383 | \&\fB\s-1GCC_COMPARE_DEBUG\s0\fR is defined to a string starting with a dash, |
| 4384 | then it is used for \fIopts\fR, otherwise the default \fB\-gtoggle\fR |
| 4385 | is used. |
| 4386 | .Sp |
| 4387 | \&\fB\-fcompare\-debug=\fR, with the equal sign but without \fIopts\fR, |
| 4388 | is equivalent to \fB\-fno\-compare\-debug\fR, which disables the dumping |
| 4389 | of the final representation and the second compilation, preventing even |
| 4390 | \&\fB\s-1GCC_COMPARE_DEBUG\s0\fR from taking effect. |
| 4391 | .Sp |
| 4392 | To verify full coverage during \fB\-fcompare\-debug\fR testing, set |
| 4393 | \&\fB\s-1GCC_COMPARE_DEBUG\s0\fR to say \fB\-fcompare\-debug\-not\-overridden\fR, |
| 4394 | which \s-1GCC\s0 will reject as an invalid option in any actual compilation |
| 4395 | (rather than preprocessing, assembly or linking). To get just a |
| 4396 | warning, setting \fB\s-1GCC_COMPARE_DEBUG\s0\fR to \fB\-w%n\-fcompare\-debug |
| 4397 | not overridden\fR will do. |
| 4398 | .IP "\fB\-fcompare\-debug\-second\fR" 4 |
| 4399 | .IX Item "-fcompare-debug-second" |
| 4400 | This option is implicitly passed to the compiler for the second |
| 4401 | compilation requested by \fB\-fcompare\-debug\fR, along with options to |
| 4402 | silence warnings, and omitting other options that would cause |
| 4403 | side-effect compiler outputs to files or to the standard output. Dump |
| 4404 | files and preserved temporary files are renamed so as to contain the |
| 4405 | \&\f(CW\*(C`.gk\*(C'\fR additional extension during the second compilation, to avoid |
| 4406 | overwriting those generated by the first. |
| 4407 | .Sp |
| 4408 | When this option is passed to the compiler driver, it causes the |
| 4409 | \&\fIfirst\fR compilation to be skipped, which makes it useful for little |
| 4410 | other than debugging the compiler proper. |
| 4411 | .IP "\fB\-feliminate\-dwarf2\-dups\fR" 4 |
| 4412 | .IX Item "-feliminate-dwarf2-dups" |
| 4413 | Compress \s-1DWARF2\s0 debugging information by eliminating duplicated |
| 4414 | information about each symbol. This option only makes sense when |
| 4415 | generating \s-1DWARF2\s0 debugging information with \fB\-gdwarf\-2\fR. |
| 4416 | .IP "\fB\-femit\-struct\-debug\-baseonly\fR" 4 |
| 4417 | .IX Item "-femit-struct-debug-baseonly" |
| 4418 | Emit debug information for struct-like types |
| 4419 | only when the base name of the compilation source file |
| 4420 | matches the base name of file in which the struct was defined. |
| 4421 | .Sp |
| 4422 | This option substantially reduces the size of debugging information, |
| 4423 | but at significant potential loss in type information to the debugger. |
| 4424 | See \fB\-femit\-struct\-debug\-reduced\fR for a less aggressive option. |
| 4425 | See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. |
| 4426 | .Sp |
| 4427 | This option works only with \s-1DWARF\s0 2. |
| 4428 | .IP "\fB\-femit\-struct\-debug\-reduced\fR" 4 |
| 4429 | .IX Item "-femit-struct-debug-reduced" |
| 4430 | Emit debug information for struct-like types |
| 4431 | only when the base name of the compilation source file |
| 4432 | matches the base name of file in which the type was defined, |
| 4433 | unless the struct is a template or defined in a system header. |
| 4434 | .Sp |
| 4435 | This option significantly reduces the size of debugging information, |
| 4436 | with some potential loss in type information to the debugger. |
| 4437 | See \fB\-femit\-struct\-debug\-baseonly\fR for a more aggressive option. |
| 4438 | See \fB\-femit\-struct\-debug\-detailed\fR for more detailed control. |
| 4439 | .Sp |
| 4440 | This option works only with \s-1DWARF\s0 2. |
| 4441 | .IP "\fB\-femit\-struct\-debug\-detailed\fR[\fB=\fR\fIspec-list\fR]" 4 |
| 4442 | .IX Item "-femit-struct-debug-detailed[=spec-list]" |
| 4443 | Specify the struct-like types |
| 4444 | for which the compiler will generate debug information. |
| 4445 | The intent is to reduce duplicate struct debug information |
| 4446 | between different object files within the same program. |
| 4447 | .Sp |
| 4448 | This option is a detailed version of |
| 4449 | \&\fB\-femit\-struct\-debug\-reduced\fR and \fB\-femit\-struct\-debug\-baseonly\fR, |
| 4450 | which will serve for most needs. |
| 4451 | .Sp |
| 4452 | A specification has the syntax[\fBdir:\fR|\fBind:\fR][\fBord:\fR|\fBgen:\fR](\fBany\fR|\fBsys\fR|\fBbase\fR|\fBnone\fR) |
| 4453 | .Sp |
| 4454 | The optional first word limits the specification to |
| 4455 | structs that are used directly (\fBdir:\fR) or used indirectly (\fBind:\fR). |
| 4456 | A struct type is used directly when it is the type of a variable, member. |
| 4457 | Indirect uses arise through pointers to structs. |
| 4458 | That is, when use of an incomplete struct would be legal, the use is indirect. |
| 4459 | An example is |
| 4460 | \&\fBstruct one direct; struct two * indirect;\fR. |
| 4461 | .Sp |
| 4462 | The optional second word limits the specification to |
| 4463 | ordinary structs (\fBord:\fR) or generic structs (\fBgen:\fR). |
| 4464 | Generic structs are a bit complicated to explain. |
| 4465 | For \*(C+, these are non-explicit specializations of template classes, |
| 4466 | or non-template classes within the above. |
| 4467 | Other programming languages have generics, |
| 4468 | but \fB\-femit\-struct\-debug\-detailed\fR does not yet implement them. |
| 4469 | .Sp |
| 4470 | The third word specifies the source files for those |
| 4471 | structs for which the compiler will emit debug information. |
| 4472 | The values \fBnone\fR and \fBany\fR have the normal meaning. |
| 4473 | The value \fBbase\fR means that |
| 4474 | the base of name of the file in which the type declaration appears |
| 4475 | must match the base of the name of the main compilation file. |
| 4476 | In practice, this means that |
| 4477 | types declared in \fIfoo.c\fR and \fIfoo.h\fR will have debug information, |
| 4478 | but types declared in other header will not. |
| 4479 | The value \fBsys\fR means those types satisfying \fBbase\fR |
| 4480 | or declared in system or compiler headers. |
| 4481 | .Sp |
| 4482 | You may need to experiment to determine the best settings for your application. |
| 4483 | .Sp |
| 4484 | The default is \fB\-femit\-struct\-debug\-detailed=all\fR. |
| 4485 | .Sp |
| 4486 | This option works only with \s-1DWARF\s0 2. |
| 4487 | .IP "\fB\-fno\-merge\-debug\-strings\fR" 4 |
| 4488 | .IX Item "-fno-merge-debug-strings" |
| 4489 | Direct the linker to not merge together strings in the debugging |
| 4490 | information that are identical in different object files. Merging is |
| 4491 | not supported by all assemblers or linkers. Merging decreases the size |
| 4492 | of the debug information in the output file at the cost of increasing |
| 4493 | link processing time. Merging is enabled by default. |
| 4494 | .IP "\fB\-fdebug\-prefix\-map=\fR\fIold\fR\fB=\fR\fInew\fR" 4 |
| 4495 | .IX Item "-fdebug-prefix-map=old=new" |
| 4496 | When compiling files in directory \fI\fIold\fI\fR, record debugging |
| 4497 | information describing them as in \fI\fInew\fI\fR instead. |
| 4498 | .IP "\fB\-fno\-dwarf2\-cfi\-asm\fR" 4 |
| 4499 | .IX Item "-fno-dwarf2-cfi-asm" |
| 4500 | Emit \s-1DWARF\s0 2 unwind info as compiler generated \f(CW\*(C`.eh_frame\*(C'\fR section |
| 4501 | instead of using \s-1GAS\s0 \f(CW\*(C`.cfi_*\*(C'\fR directives. |
| 4502 | .IP "\fB\-p\fR" 4 |
| 4503 | .IX Item "-p" |
| 4504 | Generate extra code to write profile information suitable for the |
| 4505 | analysis program \fBprof\fR. You must use this option when compiling |
| 4506 | the source files you want data about, and you must also use it when |
| 4507 | linking. |
| 4508 | .IP "\fB\-pg\fR" 4 |
| 4509 | .IX Item "-pg" |
| 4510 | Generate extra code to write profile information suitable for the |
| 4511 | analysis program \fBgprof\fR. You must use this option when compiling |
| 4512 | the source files you want data about, and you must also use it when |
| 4513 | linking. |
| 4514 | .IP "\fB\-Q\fR" 4 |
| 4515 | .IX Item "-Q" |
| 4516 | Makes the compiler print out each function name as it is compiled, and |
| 4517 | print some statistics about each pass when it finishes. |
| 4518 | .IP "\fB\-ftime\-report\fR" 4 |
| 4519 | .IX Item "-ftime-report" |
| 4520 | Makes the compiler print some statistics about the time consumed by each |
| 4521 | pass when it finishes. |
| 4522 | .IP "\fB\-fmem\-report\fR" 4 |
| 4523 | .IX Item "-fmem-report" |
| 4524 | Makes the compiler print some statistics about permanent memory |
| 4525 | allocation when it finishes. |
| 4526 | .IP "\fB\-fpre\-ipa\-mem\-report\fR" 4 |
| 4527 | .IX Item "-fpre-ipa-mem-report" |
| 4528 | .PD 0 |
| 4529 | .IP "\fB\-fpost\-ipa\-mem\-report\fR" 4 |
| 4530 | .IX Item "-fpost-ipa-mem-report" |
| 4531 | .PD |
| 4532 | Makes the compiler print some statistics about permanent memory |
| 4533 | allocation before or after interprocedural optimization. |
| 4534 | .IP "\fB\-fstack\-usage\fR" 4 |
| 4535 | .IX Item "-fstack-usage" |
| 4536 | Makes the compiler output stack usage information for the program, on a |
| 4537 | per-function basis. The filename for the dump is made by appending |
| 4538 | \&\fI.su\fR to the \fIauxname\fR. \fIauxname\fR is generated from the name of |
| 4539 | the output file, if explicitly specified and it is not an executable, |
| 4540 | otherwise it is the basename of the source file. An entry is made up |
| 4541 | of three fields: |
| 4542 | .RS 4 |
| 4543 | .IP "\(bu" 4 |
| 4544 | The name of the function. |
| 4545 | .IP "\(bu" 4 |
| 4546 | A number of bytes. |
| 4547 | .IP "\(bu" 4 |
| 4548 | One or more qualifiers: \f(CW\*(C`static\*(C'\fR, \f(CW\*(C`dynamic\*(C'\fR, \f(CW\*(C`bounded\*(C'\fR. |
| 4549 | .RE |
| 4550 | .RS 4 |
| 4551 | .Sp |
| 4552 | The qualifier \f(CW\*(C`static\*(C'\fR means that the function manipulates the stack |
| 4553 | statically: a fixed number of bytes are allocated for the frame on function |
| 4554 | entry and released on function exit; no stack adjustments are otherwise made |
| 4555 | in the function. The second field is this fixed number of bytes. |
| 4556 | .Sp |
| 4557 | The qualifier \f(CW\*(C`dynamic\*(C'\fR means that the function manipulates the stack |
| 4558 | dynamically: in addition to the static allocation described above, stack |
| 4559 | adjustments are made in the body of the function, for example to push/pop |
| 4560 | arguments around function calls. If the qualifier \f(CW\*(C`bounded\*(C'\fR is also |
| 4561 | present, the amount of these adjustments is bounded at compile time and |
| 4562 | the second field is an upper bound of the total amount of stack used by |
| 4563 | the function. If it is not present, the amount of these adjustments is |
| 4564 | not bounded at compile time and the second field only represents the |
| 4565 | bounded part. |
| 4566 | .RE |
| 4567 | .IP "\fB\-fprofile\-arcs\fR" 4 |
| 4568 | .IX Item "-fprofile-arcs" |
| 4569 | Add code so that program flow \fIarcs\fR are instrumented. During |
| 4570 | execution the program records how many times each branch and call is |
| 4571 | executed and how many times it is taken or returns. When the compiled |
| 4572 | program exits it saves this data to a file called |
| 4573 | \&\fI\fIauxname\fI.gcda\fR for each source file. The data may be used for |
| 4574 | profile-directed optimizations (\fB\-fbranch\-probabilities\fR), or for |
| 4575 | test coverage analysis (\fB\-ftest\-coverage\fR). Each object file's |
| 4576 | \&\fIauxname\fR is generated from the name of the output file, if |
| 4577 | explicitly specified and it is not the final executable, otherwise it is |
| 4578 | the basename of the source file. In both cases any suffix is removed |
| 4579 | (e.g. \fIfoo.gcda\fR for input file \fIdir/foo.c\fR, or |
| 4580 | \&\fIdir/foo.gcda\fR for output file specified as \fB\-o dir/foo.o\fR). |
| 4581 | .IP "\fB\-\-coverage\fR" 4 |
| 4582 | .IX Item "--coverage" |
| 4583 | This option is used to compile and link code instrumented for coverage |
| 4584 | analysis. The option is a synonym for \fB\-fprofile\-arcs\fR |
| 4585 | \&\fB\-ftest\-coverage\fR (when compiling) and \fB\-lgcov\fR (when |
| 4586 | linking). See the documentation for those options for more details. |
| 4587 | .RS 4 |
| 4588 | .IP "\(bu" 4 |
| 4589 | Compile the source files with \fB\-fprofile\-arcs\fR plus optimization |
| 4590 | and code generation options. For test coverage analysis, use the |
| 4591 | additional \fB\-ftest\-coverage\fR option. You do not need to profile |
| 4592 | every source file in a program. |
| 4593 | .IP "\(bu" 4 |
| 4594 | Link your object files with \fB\-lgcov\fR or \fB\-fprofile\-arcs\fR |
| 4595 | (the latter implies the former). |
| 4596 | .IP "\(bu" 4 |
| 4597 | Run the program on a representative workload to generate the arc profile |
| 4598 | information. This may be repeated any number of times. You can run |
| 4599 | concurrent instances of your program, and provided that the file system |
| 4600 | supports locking, the data files will be correctly updated. Also |
| 4601 | \&\f(CW\*(C`fork\*(C'\fR calls are detected and correctly handled (double counting |
| 4602 | will not happen). |
| 4603 | .IP "\(bu" 4 |
| 4604 | For profile-directed optimizations, compile the source files again with |
| 4605 | the same optimization and code generation options plus |
| 4606 | \&\fB\-fbranch\-probabilities\fR. |
| 4607 | .IP "\(bu" 4 |
| 4608 | For test coverage analysis, use \fBgcov\fR to produce human readable |
| 4609 | information from the \fI.gcno\fR and \fI.gcda\fR files. Refer to the |
| 4610 | \&\fBgcov\fR documentation for further information. |
| 4611 | .RE |
| 4612 | .RS 4 |
| 4613 | .Sp |
| 4614 | With \fB\-fprofile\-arcs\fR, for each function of your program \s-1GCC\s0 |
| 4615 | creates a program flow graph, then finds a spanning tree for the graph. |
| 4616 | Only arcs that are not on the spanning tree have to be instrumented: the |
| 4617 | compiler adds code to count the number of times that these arcs are |
| 4618 | executed. When an arc is the only exit or only entrance to a block, the |
| 4619 | instrumentation code can be added to the block; otherwise, a new basic |
| 4620 | block must be created to hold the instrumentation code. |
| 4621 | .RE |
| 4622 | .IP "\fB\-ftest\-coverage\fR" 4 |
| 4623 | .IX Item "-ftest-coverage" |
| 4624 | Produce a notes file that the \fBgcov\fR code-coverage utility can use to |
| 4625 | show program coverage. Each source file's note file is called |
| 4626 | \&\fI\fIauxname\fI.gcno\fR. Refer to the \fB\-fprofile\-arcs\fR option |
| 4627 | above for a description of \fIauxname\fR and instructions on how to |
| 4628 | generate test coverage data. Coverage data will match the source files |
| 4629 | more closely, if you do not optimize. |
| 4630 | .IP "\fB\-fdbg\-cnt\-list\fR" 4 |
| 4631 | .IX Item "-fdbg-cnt-list" |
| 4632 | Print the name and the counter upper bound for all debug counters. |
| 4633 | .IP "\fB\-fdbg\-cnt=\fR\fIcounter-value-list\fR" 4 |
| 4634 | .IX Item "-fdbg-cnt=counter-value-list" |
| 4635 | Set the internal debug counter upper bound. \fIcounter-value-list\fR |
| 4636 | is a comma-separated list of \fIname\fR:\fIvalue\fR pairs |
| 4637 | which sets the upper bound of each debug counter \fIname\fR to \fIvalue\fR. |
| 4638 | All debug counters have the initial upper bound of \fI\s-1UINT_MAX\s0\fR, |
| 4639 | thus \fIdbg_cnt()\fR returns true always unless the upper bound is set by this option. |
| 4640 | e.g. With \-fdbg\-cnt=dce:10,tail_call:0 |
| 4641 | dbg_cnt(dce) will return true only for first 10 invocations |
| 4642 | .IP "\fB\-fenable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR" 4 |
| 4643 | .IX Item "-fenable-kind-pass" |
| 4644 | .PD 0 |
| 4645 | .IP "\fB\-fdisable\-\fR\fIkind\fR\fB\-\fR\fIpass\fR\fB=\fR\fIrange-list\fR" 4 |
| 4646 | .IX Item "-fdisable-kind-pass=range-list" |
| 4647 | .PD |
| 4648 | This is a set of debugging options that are used to explicitly disable/enable |
| 4649 | optimization passes. For compiler users, regular options for enabling/disabling |
| 4650 | passes should be used instead. |
| 4651 | .RS 4 |
| 4652 | .IP "*<\-fdisable\-ipa\-\fIpass\fR>" 4 |
| 4653 | .IX Item "*<-fdisable-ipa-pass>" |
| 4654 | Disable ipa pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is |
| 4655 | statically invoked in the compiler multiple times, the pass name should be |
| 4656 | appended with a sequential number starting from 1. |
| 4657 | .IP "*<\-fdisable\-rtl\-\fIpass\fR>" 4 |
| 4658 | .IX Item "*<-fdisable-rtl-pass>" |
| 4659 | .PD 0 |
| 4660 | .IP "*<\-fdisable\-rtl\-\fIpass\fR=\fIrange-list\fR>" 4 |
| 4661 | .IX Item "*<-fdisable-rtl-pass=range-list>" |
| 4662 | .PD |
| 4663 | Disable rtl pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is |
| 4664 | statically invoked in the compiler multiple times, the pass name should be |
| 4665 | appended with a sequential number starting from 1. \fIrange-list\fR is a comma |
| 4666 | seperated list of function ranges or assembler names. Each range is a number |
| 4667 | pair seperated by a colon. The range is inclusive in both ends. If the range |
| 4668 | is trivial, the number pair can be simplified as a single number. If the |
| 4669 | function's cgraph node's \fIuid\fR is falling within one of the specified ranges, |
| 4670 | the \fIpass\fR is disabled for that function. The \fIuid\fR is shown in the |
| 4671 | function header of a dump file, and the pass names can be dumped by using |
| 4672 | option \fB\-fdump\-passes\fR. |
| 4673 | .IP "*<\-fdisable\-tree\-\fIpass\fR>" 4 |
| 4674 | .IX Item "*<-fdisable-tree-pass>" |
| 4675 | .PD 0 |
| 4676 | .IP "*<\-fdisable\-tree\-\fIpass\fR=\fIrange-list\fR>" 4 |
| 4677 | .IX Item "*<-fdisable-tree-pass=range-list>" |
| 4678 | .PD |
| 4679 | Disable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description of |
| 4680 | option arguments. |
| 4681 | .IP "*<\-fenable\-ipa\-\fIpass\fR>" 4 |
| 4682 | .IX Item "*<-fenable-ipa-pass>" |
| 4683 | Enable ipa pass \fIpass\fR. \fIpass\fR is the pass name. If the same pass is |
| 4684 | statically invoked in the compiler multiple times, the pass name should be |
| 4685 | appended with a sequential number starting from 1. |
| 4686 | .IP "*<\-fenable\-rtl\-\fIpass\fR>" 4 |
| 4687 | .IX Item "*<-fenable-rtl-pass>" |
| 4688 | .PD 0 |
| 4689 | .IP "*<\-fenable\-rtl\-\fIpass\fR=\fIrange-list\fR>" 4 |
| 4690 | .IX Item "*<-fenable-rtl-pass=range-list>" |
| 4691 | .PD |
| 4692 | Enable rtl pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for option argument |
| 4693 | description and examples. |
| 4694 | .IP "*<\-fenable\-tree\-\fIpass\fR>" 4 |
| 4695 | .IX Item "*<-fenable-tree-pass>" |
| 4696 | .PD 0 |
| 4697 | .IP "*<\-fenable\-tree\-\fIpass\fR=\fIrange-list\fR>" 4 |
| 4698 | .IX Item "*<-fenable-tree-pass=range-list>" |
| 4699 | .PD |
| 4700 | Enable tree pass \fIpass\fR. See \fB\-fdisable\-rtl\fR for the description |
| 4701 | of option arguments. |
| 4702 | .Sp |
| 4703 | .Vb 10 |
| 4704 | \& # disable ccp1 for all functions |
| 4705 | \& \-fdisable\-tree\-ccp1 |
| 4706 | \& # disable complete unroll for function whose cgraph node uid is 1 |
| 4707 | \& \-fenable\-tree\-cunroll=1 |
| 4708 | \& # disable gcse2 for functions at the following ranges [1,1], |
| 4709 | \& # [300,400], and [400,1000] |
| 4710 | \& # disable gcse2 for functions foo and foo2 |
| 4711 | \& \-fdisable\-rtl\-gcse2=foo,foo2 |
| 4712 | \& # disable early inlining |
| 4713 | \& \-fdisable\-tree\-einline |
| 4714 | \& # disable ipa inlining |
| 4715 | \& \-fdisable\-ipa\-inline |
| 4716 | \& # enable tree full unroll |
| 4717 | \& \-fenable\-tree\-unroll |
| 4718 | .Ve |
| 4719 | .RE |
| 4720 | .RS 4 |
| 4721 | .RE |
| 4722 | .IP "\fB\-d\fR\fIletters\fR" 4 |
| 4723 | .IX Item "-dletters" |
| 4724 | .PD 0 |
| 4725 | .IP "\fB\-fdump\-rtl\-\fR\fIpass\fR" 4 |
| 4726 | .IX Item "-fdump-rtl-pass" |
| 4727 | .PD |
| 4728 | Says to make debugging dumps during compilation at times specified by |
| 4729 | \&\fIletters\fR. This is used for debugging the RTL-based passes of the |
| 4730 | compiler. The file names for most of the dumps are made by appending |
| 4731 | a pass number and a word to the \fIdumpname\fR, and the files are |
| 4732 | created in the directory of the output file. Note that the pass |
| 4733 | number is computed statically as passes get registered into the pass |
| 4734 | manager. Thus the numbering is not related to the dynamic order of |
| 4735 | execution of passes. In particular, a pass installed by a plugin |
| 4736 | could have a number over 200 even if it executed quite early. |
| 4737 | \&\fIdumpname\fR is generated from the name of the output file, if |
| 4738 | explicitly specified and it is not an executable, otherwise it is the |
| 4739 | basename of the source file. These switches may have different effects |
| 4740 | when \fB\-E\fR is used for preprocessing. |
| 4741 | .Sp |
| 4742 | Debug dumps can be enabled with a \fB\-fdump\-rtl\fR switch or some |
| 4743 | \&\fB\-d\fR option \fIletters\fR. Here are the possible |
| 4744 | letters for use in \fIpass\fR and \fIletters\fR, and their meanings: |
| 4745 | .RS 4 |
| 4746 | .IP "\fB\-fdump\-rtl\-alignments\fR" 4 |
| 4747 | .IX Item "-fdump-rtl-alignments" |
| 4748 | Dump after branch alignments have been computed. |
| 4749 | .IP "\fB\-fdump\-rtl\-asmcons\fR" 4 |
| 4750 | .IX Item "-fdump-rtl-asmcons" |
| 4751 | Dump after fixing rtl statements that have unsatisfied in/out constraints. |
| 4752 | .IP "\fB\-fdump\-rtl\-auto_inc_dec\fR" 4 |
| 4753 | .IX Item "-fdump-rtl-auto_inc_dec" |
| 4754 | Dump after auto-inc-dec discovery. This pass is only run on |
| 4755 | architectures that have auto inc or auto dec instructions. |
| 4756 | .IP "\fB\-fdump\-rtl\-barriers\fR" 4 |
| 4757 | .IX Item "-fdump-rtl-barriers" |
| 4758 | Dump after cleaning up the barrier instructions. |
| 4759 | .IP "\fB\-fdump\-rtl\-bbpart\fR" 4 |
| 4760 | .IX Item "-fdump-rtl-bbpart" |
| 4761 | Dump after partitioning hot and cold basic blocks. |
| 4762 | .IP "\fB\-fdump\-rtl\-bbro\fR" 4 |
| 4763 | .IX Item "-fdump-rtl-bbro" |
| 4764 | Dump after block reordering. |
| 4765 | .IP "\fB\-fdump\-rtl\-btl1\fR" 4 |
| 4766 | .IX Item "-fdump-rtl-btl1" |
| 4767 | .PD 0 |
| 4768 | .IP "\fB\-fdump\-rtl\-btl2\fR" 4 |
| 4769 | .IX Item "-fdump-rtl-btl2" |
| 4770 | .PD |
| 4771 | \&\fB\-fdump\-rtl\-btl1\fR and \fB\-fdump\-rtl\-btl2\fR enable dumping |
| 4772 | after the two branch |
| 4773 | target load optimization passes. |
| 4774 | .IP "\fB\-fdump\-rtl\-bypass\fR" 4 |
| 4775 | .IX Item "-fdump-rtl-bypass" |
| 4776 | Dump after jump bypassing and control flow optimizations. |
| 4777 | .IP "\fB\-fdump\-rtl\-combine\fR" 4 |
| 4778 | .IX Item "-fdump-rtl-combine" |
| 4779 | Dump after the \s-1RTL\s0 instruction combination pass. |
| 4780 | .IP "\fB\-fdump\-rtl\-compgotos\fR" 4 |
| 4781 | .IX Item "-fdump-rtl-compgotos" |
| 4782 | Dump after duplicating the computed gotos. |
| 4783 | .IP "\fB\-fdump\-rtl\-ce1\fR" 4 |
| 4784 | .IX Item "-fdump-rtl-ce1" |
| 4785 | .PD 0 |
| 4786 | .IP "\fB\-fdump\-rtl\-ce2\fR" 4 |
| 4787 | .IX Item "-fdump-rtl-ce2" |
| 4788 | .IP "\fB\-fdump\-rtl\-ce3\fR" 4 |
| 4789 | .IX Item "-fdump-rtl-ce3" |
| 4790 | .PD |
| 4791 | \&\fB\-fdump\-rtl\-ce1\fR, \fB\-fdump\-rtl\-ce2\fR, and |
| 4792 | \&\fB\-fdump\-rtl\-ce3\fR enable dumping after the three |
| 4793 | if conversion passes. |
| 4794 | .IP "\fB\-fdump\-rtl\-cprop_hardreg\fR" 4 |
| 4795 | .IX Item "-fdump-rtl-cprop_hardreg" |
| 4796 | Dump after hard register copy propagation. |
| 4797 | .IP "\fB\-fdump\-rtl\-csa\fR" 4 |
| 4798 | .IX Item "-fdump-rtl-csa" |
| 4799 | Dump after combining stack adjustments. |
| 4800 | .IP "\fB\-fdump\-rtl\-cse1\fR" 4 |
| 4801 | .IX Item "-fdump-rtl-cse1" |
| 4802 | .PD 0 |
| 4803 | .IP "\fB\-fdump\-rtl\-cse2\fR" 4 |
| 4804 | .IX Item "-fdump-rtl-cse2" |
| 4805 | .PD |
| 4806 | \&\fB\-fdump\-rtl\-cse1\fR and \fB\-fdump\-rtl\-cse2\fR enable dumping after |
| 4807 | the two common sub-expression elimination passes. |
| 4808 | .IP "\fB\-fdump\-rtl\-dce\fR" 4 |
| 4809 | .IX Item "-fdump-rtl-dce" |
| 4810 | Dump after the standalone dead code elimination passes. |
| 4811 | .IP "\fB\-fdump\-rtl\-dbr\fR" 4 |
| 4812 | .IX Item "-fdump-rtl-dbr" |
| 4813 | Dump after delayed branch scheduling. |
| 4814 | .IP "\fB\-fdump\-rtl\-dce1\fR" 4 |
| 4815 | .IX Item "-fdump-rtl-dce1" |
| 4816 | .PD 0 |
| 4817 | .IP "\fB\-fdump\-rtl\-dce2\fR" 4 |
| 4818 | .IX Item "-fdump-rtl-dce2" |
| 4819 | .PD |
| 4820 | \&\fB\-fdump\-rtl\-dce1\fR and \fB\-fdump\-rtl\-dce2\fR enable dumping after |
| 4821 | the two dead store elimination passes. |
| 4822 | .IP "\fB\-fdump\-rtl\-eh\fR" 4 |
| 4823 | .IX Item "-fdump-rtl-eh" |
| 4824 | Dump after finalization of \s-1EH\s0 handling code. |
| 4825 | .IP "\fB\-fdump\-rtl\-eh_ranges\fR" 4 |
| 4826 | .IX Item "-fdump-rtl-eh_ranges" |
| 4827 | Dump after conversion of \s-1EH\s0 handling range regions. |
| 4828 | .IP "\fB\-fdump\-rtl\-expand\fR" 4 |
| 4829 | .IX Item "-fdump-rtl-expand" |
| 4830 | Dump after \s-1RTL\s0 generation. |
| 4831 | .IP "\fB\-fdump\-rtl\-fwprop1\fR" 4 |
| 4832 | .IX Item "-fdump-rtl-fwprop1" |
| 4833 | .PD 0 |
| 4834 | .IP "\fB\-fdump\-rtl\-fwprop2\fR" 4 |
| 4835 | .IX Item "-fdump-rtl-fwprop2" |
| 4836 | .PD |
| 4837 | \&\fB\-fdump\-rtl\-fwprop1\fR and \fB\-fdump\-rtl\-fwprop2\fR enable |
| 4838 | dumping after the two forward propagation passes. |
| 4839 | .IP "\fB\-fdump\-rtl\-gcse1\fR" 4 |
| 4840 | .IX Item "-fdump-rtl-gcse1" |
| 4841 | .PD 0 |
| 4842 | .IP "\fB\-fdump\-rtl\-gcse2\fR" 4 |
| 4843 | .IX Item "-fdump-rtl-gcse2" |
| 4844 | .PD |
| 4845 | \&\fB\-fdump\-rtl\-gcse1\fR and \fB\-fdump\-rtl\-gcse2\fR enable dumping |
| 4846 | after global common subexpression elimination. |
| 4847 | .IP "\fB\-fdump\-rtl\-init\-regs\fR" 4 |
| 4848 | .IX Item "-fdump-rtl-init-regs" |
| 4849 | Dump after the initialization of the registers. |
| 4850 | .IP "\fB\-fdump\-rtl\-initvals\fR" 4 |
| 4851 | .IX Item "-fdump-rtl-initvals" |
| 4852 | Dump after the computation of the initial value sets. |
| 4853 | .IP "\fB\-fdump\-rtl\-into_cfglayout\fR" 4 |
| 4854 | .IX Item "-fdump-rtl-into_cfglayout" |
| 4855 | Dump after converting to cfglayout mode. |
| 4856 | .IP "\fB\-fdump\-rtl\-ira\fR" 4 |
| 4857 | .IX Item "-fdump-rtl-ira" |
| 4858 | Dump after iterated register allocation. |
| 4859 | .IP "\fB\-fdump\-rtl\-jump\fR" 4 |
| 4860 | .IX Item "-fdump-rtl-jump" |
| 4861 | Dump after the second jump optimization. |
| 4862 | .IP "\fB\-fdump\-rtl\-loop2\fR" 4 |
| 4863 | .IX Item "-fdump-rtl-loop2" |
| 4864 | \&\fB\-fdump\-rtl\-loop2\fR enables dumping after the rtl |
| 4865 | loop optimization passes. |
| 4866 | .IP "\fB\-fdump\-rtl\-mach\fR" 4 |
| 4867 | .IX Item "-fdump-rtl-mach" |
| 4868 | Dump after performing the machine dependent reorganization pass, if that |
| 4869 | pass exists. |
| 4870 | .IP "\fB\-fdump\-rtl\-mode_sw\fR" 4 |
| 4871 | .IX Item "-fdump-rtl-mode_sw" |
| 4872 | Dump after removing redundant mode switches. |
| 4873 | .IP "\fB\-fdump\-rtl\-rnreg\fR" 4 |
| 4874 | .IX Item "-fdump-rtl-rnreg" |
| 4875 | Dump after register renumbering. |
| 4876 | .IP "\fB\-fdump\-rtl\-outof_cfglayout\fR" 4 |
| 4877 | .IX Item "-fdump-rtl-outof_cfglayout" |
| 4878 | Dump after converting from cfglayout mode. |
| 4879 | .IP "\fB\-fdump\-rtl\-peephole2\fR" 4 |
| 4880 | .IX Item "-fdump-rtl-peephole2" |
| 4881 | Dump after the peephole pass. |
| 4882 | .IP "\fB\-fdump\-rtl\-postreload\fR" 4 |
| 4883 | .IX Item "-fdump-rtl-postreload" |
| 4884 | Dump after post-reload optimizations. |
| 4885 | .IP "\fB\-fdump\-rtl\-pro_and_epilogue\fR" 4 |
| 4886 | .IX Item "-fdump-rtl-pro_and_epilogue" |
| 4887 | Dump after generating the function prologues and epilogues. |
| 4888 | .IP "\fB\-fdump\-rtl\-regmove\fR" 4 |
| 4889 | .IX Item "-fdump-rtl-regmove" |
| 4890 | Dump after the register move pass. |
| 4891 | .IP "\fB\-fdump\-rtl\-sched1\fR" 4 |
| 4892 | .IX Item "-fdump-rtl-sched1" |
| 4893 | .PD 0 |
| 4894 | .IP "\fB\-fdump\-rtl\-sched2\fR" 4 |
| 4895 | .IX Item "-fdump-rtl-sched2" |
| 4896 | .PD |
| 4897 | \&\fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR enable dumping |
| 4898 | after the basic block scheduling passes. |
| 4899 | .IP "\fB\-fdump\-rtl\-see\fR" 4 |
| 4900 | .IX Item "-fdump-rtl-see" |
| 4901 | Dump after sign extension elimination. |
| 4902 | .IP "\fB\-fdump\-rtl\-seqabstr\fR" 4 |
| 4903 | .IX Item "-fdump-rtl-seqabstr" |
| 4904 | Dump after common sequence discovery. |
| 4905 | .IP "\fB\-fdump\-rtl\-shorten\fR" 4 |
| 4906 | .IX Item "-fdump-rtl-shorten" |
| 4907 | Dump after shortening branches. |
| 4908 | .IP "\fB\-fdump\-rtl\-sibling\fR" 4 |
| 4909 | .IX Item "-fdump-rtl-sibling" |
| 4910 | Dump after sibling call optimizations. |
| 4911 | .IP "\fB\-fdump\-rtl\-split1\fR" 4 |
| 4912 | .IX Item "-fdump-rtl-split1" |
| 4913 | .PD 0 |
| 4914 | .IP "\fB\-fdump\-rtl\-split2\fR" 4 |
| 4915 | .IX Item "-fdump-rtl-split2" |
| 4916 | .IP "\fB\-fdump\-rtl\-split3\fR" 4 |
| 4917 | .IX Item "-fdump-rtl-split3" |
| 4918 | .IP "\fB\-fdump\-rtl\-split4\fR" 4 |
| 4919 | .IX Item "-fdump-rtl-split4" |
| 4920 | .IP "\fB\-fdump\-rtl\-split5\fR" 4 |
| 4921 | .IX Item "-fdump-rtl-split5" |
| 4922 | .PD |
| 4923 | \&\fB\-fdump\-rtl\-split1\fR, \fB\-fdump\-rtl\-split2\fR, |
| 4924 | \&\fB\-fdump\-rtl\-split3\fR, \fB\-fdump\-rtl\-split4\fR and |
| 4925 | \&\fB\-fdump\-rtl\-split5\fR enable dumping after five rounds of |
| 4926 | instruction splitting. |
| 4927 | .IP "\fB\-fdump\-rtl\-sms\fR" 4 |
| 4928 | .IX Item "-fdump-rtl-sms" |
| 4929 | Dump after modulo scheduling. This pass is only run on some |
| 4930 | architectures. |
| 4931 | .IP "\fB\-fdump\-rtl\-stack\fR" 4 |
| 4932 | .IX Item "-fdump-rtl-stack" |
| 4933 | Dump after conversion from \s-1GCC\s0's \*(L"flat register file\*(R" registers to the |
| 4934 | x87's stack-like registers. This pass is only run on x86 variants. |
| 4935 | .IP "\fB\-fdump\-rtl\-subreg1\fR" 4 |
| 4936 | .IX Item "-fdump-rtl-subreg1" |
| 4937 | .PD 0 |
| 4938 | .IP "\fB\-fdump\-rtl\-subreg2\fR" 4 |
| 4939 | .IX Item "-fdump-rtl-subreg2" |
| 4940 | .PD |
| 4941 | \&\fB\-fdump\-rtl\-subreg1\fR and \fB\-fdump\-rtl\-subreg2\fR enable dumping after |
| 4942 | the two subreg expansion passes. |
| 4943 | .IP "\fB\-fdump\-rtl\-unshare\fR" 4 |
| 4944 | .IX Item "-fdump-rtl-unshare" |
| 4945 | Dump after all rtl has been unshared. |
| 4946 | .IP "\fB\-fdump\-rtl\-vartrack\fR" 4 |
| 4947 | .IX Item "-fdump-rtl-vartrack" |
| 4948 | Dump after variable tracking. |
| 4949 | .IP "\fB\-fdump\-rtl\-vregs\fR" 4 |
| 4950 | .IX Item "-fdump-rtl-vregs" |
| 4951 | Dump after converting virtual registers to hard registers. |
| 4952 | .IP "\fB\-fdump\-rtl\-web\fR" 4 |
| 4953 | .IX Item "-fdump-rtl-web" |
| 4954 | Dump after live range splitting. |
| 4955 | .IP "\fB\-fdump\-rtl\-regclass\fR" 4 |
| 4956 | .IX Item "-fdump-rtl-regclass" |
| 4957 | .PD 0 |
| 4958 | .IP "\fB\-fdump\-rtl\-subregs_of_mode_init\fR" 4 |
| 4959 | .IX Item "-fdump-rtl-subregs_of_mode_init" |
| 4960 | .IP "\fB\-fdump\-rtl\-subregs_of_mode_finish\fR" 4 |
| 4961 | .IX Item "-fdump-rtl-subregs_of_mode_finish" |
| 4962 | .IP "\fB\-fdump\-rtl\-dfinit\fR" 4 |
| 4963 | .IX Item "-fdump-rtl-dfinit" |
| 4964 | .IP "\fB\-fdump\-rtl\-dfinish\fR" 4 |
| 4965 | .IX Item "-fdump-rtl-dfinish" |
| 4966 | .PD |
| 4967 | These dumps are defined but always produce empty files. |
| 4968 | .IP "\fB\-da\fR" 4 |
| 4969 | .IX Item "-da" |
| 4970 | .PD 0 |
| 4971 | .IP "\fB\-fdump\-rtl\-all\fR" 4 |
| 4972 | .IX Item "-fdump-rtl-all" |
| 4973 | .PD |
| 4974 | Produce all the dumps listed above. |
| 4975 | .IP "\fB\-dA\fR" 4 |
| 4976 | .IX Item "-dA" |
| 4977 | Annotate the assembler output with miscellaneous debugging information. |
| 4978 | .IP "\fB\-dD\fR" 4 |
| 4979 | .IX Item "-dD" |
| 4980 | Dump all macro definitions, at the end of preprocessing, in addition to |
| 4981 | normal output. |
| 4982 | .IP "\fB\-dH\fR" 4 |
| 4983 | .IX Item "-dH" |
| 4984 | Produce a core dump whenever an error occurs. |
| 4985 | .IP "\fB\-dp\fR" 4 |
| 4986 | .IX Item "-dp" |
| 4987 | Annotate the assembler output with a comment indicating which |
| 4988 | pattern and alternative was used. The length of each instruction is |
| 4989 | also printed. |
| 4990 | .IP "\fB\-dP\fR" 4 |
| 4991 | .IX Item "-dP" |
| 4992 | Dump the \s-1RTL\s0 in the assembler output as a comment before each instruction. |
| 4993 | Also turns on \fB\-dp\fR annotation. |
| 4994 | .IP "\fB\-dv\fR" 4 |
| 4995 | .IX Item "-dv" |
| 4996 | For each of the other indicated dump files (\fB\-fdump\-rtl\-\fR\fIpass\fR), |
| 4997 | dump a representation of the control flow graph suitable for viewing with \s-1VCG\s0 |
| 4998 | to \fI\fIfile\fI.\fIpass\fI.vcg\fR. |
| 4999 | .IP "\fB\-dx\fR" 4 |
| 5000 | .IX Item "-dx" |
| 5001 | Just generate \s-1RTL\s0 for a function instead of compiling it. Usually used |
| 5002 | with \fB\-fdump\-rtl\-expand\fR. |
| 5003 | .RE |
| 5004 | .RS 4 |
| 5005 | .RE |
| 5006 | .IP "\fB\-fdump\-noaddr\fR" 4 |
| 5007 | .IX Item "-fdump-noaddr" |
| 5008 | When doing debugging dumps, suppress address output. This makes it more |
| 5009 | feasible to use diff on debugging dumps for compiler invocations with |
| 5010 | different compiler binaries and/or different |
| 5011 | text / bss / data / heap / stack / dso start locations. |
| 5012 | .IP "\fB\-fdump\-unnumbered\fR" 4 |
| 5013 | .IX Item "-fdump-unnumbered" |
| 5014 | When doing debugging dumps, suppress instruction numbers and address output. |
| 5015 | This makes it more feasible to use diff on debugging dumps for compiler |
| 5016 | invocations with different options, in particular with and without |
| 5017 | \&\fB\-g\fR. |
| 5018 | .IP "\fB\-fdump\-unnumbered\-links\fR" 4 |
| 5019 | .IX Item "-fdump-unnumbered-links" |
| 5020 | When doing debugging dumps (see \fB\-d\fR option above), suppress |
| 5021 | instruction numbers for the links to the previous and next instructions |
| 5022 | in a sequence. |
| 5023 | .IP "\fB\-fdump\-translation\-unit\fR (\*(C+ only)" 4 |
| 5024 | .IX Item "-fdump-translation-unit ( only)" |
| 5025 | .PD 0 |
| 5026 | .IP "\fB\-fdump\-translation\-unit\-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4 |
| 5027 | .IX Item "-fdump-translation-unit-options ( only)" |
| 5028 | .PD |
| 5029 | Dump a representation of the tree structure for the entire translation |
| 5030 | unit to a file. The file name is made by appending \fI.tu\fR to the |
| 5031 | source file name, and the file is created in the same directory as the |
| 5032 | output file. If the \fB\-\fR\fIoptions\fR form is used, \fIoptions\fR |
| 5033 | controls the details of the dump as described for the |
| 5034 | \&\fB\-fdump\-tree\fR options. |
| 5035 | .IP "\fB\-fdump\-class\-hierarchy\fR (\*(C+ only)" 4 |
| 5036 | .IX Item "-fdump-class-hierarchy ( only)" |
| 5037 | .PD 0 |
| 5038 | .IP "\fB\-fdump\-class\-hierarchy\-\fR\fIoptions\fR\fB \fR(\*(C+ only)" 4 |
| 5039 | .IX Item "-fdump-class-hierarchy-options ( only)" |
| 5040 | .PD |
| 5041 | Dump a representation of each class's hierarchy and virtual function |
| 5042 | table layout to a file. The file name is made by appending |
| 5043 | \&\fI.class\fR to the source file name, and the file is created in the |
| 5044 | same directory as the output file. If the \fB\-\fR\fIoptions\fR form |
| 5045 | is used, \fIoptions\fR controls the details of the dump as described |
| 5046 | for the \fB\-fdump\-tree\fR options. |
| 5047 | .IP "\fB\-fdump\-ipa\-\fR\fIswitch\fR" 4 |
| 5048 | .IX Item "-fdump-ipa-switch" |
| 5049 | Control the dumping at various stages of inter-procedural analysis |
| 5050 | language tree to a file. The file name is generated by appending a |
| 5051 | switch specific suffix to the source file name, and the file is created |
| 5052 | in the same directory as the output file. The following dumps are |
| 5053 | possible: |
| 5054 | .RS 4 |
| 5055 | .IP "\fBall\fR" 4 |
| 5056 | .IX Item "all" |
| 5057 | Enables all inter-procedural analysis dumps. |
| 5058 | .IP "\fBcgraph\fR" 4 |
| 5059 | .IX Item "cgraph" |
| 5060 | Dumps information about call-graph optimization, unused function removal, |
| 5061 | and inlining decisions. |
| 5062 | .IP "\fBinline\fR" 4 |
| 5063 | .IX Item "inline" |
| 5064 | Dump after function inlining. |
| 5065 | .RE |
| 5066 | .RS 4 |
| 5067 | .RE |
| 5068 | .IP "\fB\-fdump\-passes\fR" 4 |
| 5069 | .IX Item "-fdump-passes" |
| 5070 | Dump the list of optimization passes that are turned on and off by |
| 5071 | the current command-line options. |
| 5072 | .IP "\fB\-fdump\-statistics\-\fR\fIoption\fR" 4 |
| 5073 | .IX Item "-fdump-statistics-option" |
| 5074 | Enable and control dumping of pass statistics in a separate file. The |
| 5075 | file name is generated by appending a suffix ending in |
| 5076 | \&\fB.statistics\fR to the source file name, and the file is created in |
| 5077 | the same directory as the output file. If the \fB\-\fR\fIoption\fR |
| 5078 | form is used, \fB\-stats\fR will cause counters to be summed over the |
| 5079 | whole compilation unit while \fB\-details\fR will dump every event as |
| 5080 | the passes generate them. The default with no option is to sum |
| 5081 | counters for each function compiled. |
| 5082 | .IP "\fB\-fdump\-tree\-\fR\fIswitch\fR" 4 |
| 5083 | .IX Item "-fdump-tree-switch" |
| 5084 | .PD 0 |
| 5085 | .IP "\fB\-fdump\-tree\-\fR\fIswitch\fR\fB\-\fR\fIoptions\fR" 4 |
| 5086 | .IX Item "-fdump-tree-switch-options" |
| 5087 | .PD |
| 5088 | Control the dumping at various stages of processing the intermediate |
| 5089 | language tree to a file. The file name is generated by appending a |
| 5090 | switch specific suffix to the source file name, and the file is |
| 5091 | created in the same directory as the output file. If the |
| 5092 | \&\fB\-\fR\fIoptions\fR form is used, \fIoptions\fR is a list of |
| 5093 | \&\fB\-\fR separated options which control the details of the dump. Not |
| 5094 | all options are applicable to all dumps; those that are not |
| 5095 | meaningful will be ignored. The following options are available |
| 5096 | .RS 4 |
| 5097 | .IP "\fBaddress\fR" 4 |
| 5098 | .IX Item "address" |
| 5099 | Print the address of each node. Usually this is not meaningful as it |
| 5100 | changes according to the environment and source file. Its primary use |
| 5101 | is for tying up a dump file with a debug environment. |
| 5102 | .IP "\fBasmname\fR" 4 |
| 5103 | .IX Item "asmname" |
| 5104 | If \f(CW\*(C`DECL_ASSEMBLER_NAME\*(C'\fR has been set for a given decl, use that |
| 5105 | in the dump instead of \f(CW\*(C`DECL_NAME\*(C'\fR. Its primary use is ease of |
| 5106 | use working backward from mangled names in the assembly file. |
| 5107 | .IP "\fBslim\fR" 4 |
| 5108 | .IX Item "slim" |
| 5109 | Inhibit dumping of members of a scope or body of a function merely |
| 5110 | because that scope has been reached. Only dump such items when they |
| 5111 | are directly reachable by some other path. When dumping pretty-printed |
| 5112 | trees, this option inhibits dumping the bodies of control structures. |
| 5113 | .IP "\fBraw\fR" 4 |
| 5114 | .IX Item "raw" |
| 5115 | Print a raw representation of the tree. By default, trees are |
| 5116 | pretty-printed into a C\-like representation. |
| 5117 | .IP "\fBdetails\fR" 4 |
| 5118 | .IX Item "details" |
| 5119 | Enable more detailed dumps (not honored by every dump option). |
| 5120 | .IP "\fBstats\fR" 4 |
| 5121 | .IX Item "stats" |
| 5122 | Enable dumping various statistics about the pass (not honored by every dump |
| 5123 | option). |
| 5124 | .IP "\fBblocks\fR" 4 |
| 5125 | .IX Item "blocks" |
| 5126 | Enable showing basic block boundaries (disabled in raw dumps). |
| 5127 | .IP "\fBvops\fR" 4 |
| 5128 | .IX Item "vops" |
| 5129 | Enable showing virtual operands for every statement. |
| 5130 | .IP "\fBlineno\fR" 4 |
| 5131 | .IX Item "lineno" |
| 5132 | Enable showing line numbers for statements. |
| 5133 | .IP "\fBuid\fR" 4 |
| 5134 | .IX Item "uid" |
| 5135 | Enable showing the unique \s-1ID\s0 (\f(CW\*(C`DECL_UID\*(C'\fR) for each variable. |
| 5136 | .IP "\fBverbose\fR" 4 |
| 5137 | .IX Item "verbose" |
| 5138 | Enable showing the tree dump for each statement. |
| 5139 | .IP "\fBeh\fR" 4 |
| 5140 | .IX Item "eh" |
| 5141 | Enable showing the \s-1EH\s0 region number holding each statement. |
| 5142 | .IP "\fBscev\fR" 4 |
| 5143 | .IX Item "scev" |
| 5144 | Enable showing scalar evolution analysis details. |
| 5145 | .IP "\fBall\fR" 4 |
| 5146 | .IX Item "all" |
| 5147 | Turn on all options, except \fBraw\fR, \fBslim\fR, \fBverbose\fR |
| 5148 | and \fBlineno\fR. |
| 5149 | .RE |
| 5150 | .RS 4 |
| 5151 | .Sp |
| 5152 | The following tree dumps are possible: |
| 5153 | .IP "\fBoriginal\fR" 4 |
| 5154 | .IX Item "original" |
| 5155 | Dump before any tree based optimization, to \fI\fIfile\fI.original\fR. |
| 5156 | .IP "\fBoptimized\fR" 4 |
| 5157 | .IX Item "optimized" |
| 5158 | Dump after all tree based optimization, to \fI\fIfile\fI.optimized\fR. |
| 5159 | .IP "\fBgimple\fR" 4 |
| 5160 | .IX Item "gimple" |
| 5161 | Dump each function before and after the gimplification pass to a file. The |
| 5162 | file name is made by appending \fI.gimple\fR to the source file name. |
| 5163 | .IP "\fBcfg\fR" 4 |
| 5164 | .IX Item "cfg" |
| 5165 | Dump the control flow graph of each function to a file. The file name is |
| 5166 | made by appending \fI.cfg\fR to the source file name. |
| 5167 | .IP "\fBvcg\fR" 4 |
| 5168 | .IX Item "vcg" |
| 5169 | Dump the control flow graph of each function to a file in \s-1VCG\s0 format. The |
| 5170 | file name is made by appending \fI.vcg\fR to the source file name. Note |
| 5171 | that if the file contains more than one function, the generated file cannot |
| 5172 | be used directly by \s-1VCG\s0. You will need to cut and paste each function's |
| 5173 | graph into its own separate file first. |
| 5174 | .IP "\fBch\fR" 4 |
| 5175 | .IX Item "ch" |
| 5176 | Dump each function after copying loop headers. The file name is made by |
| 5177 | appending \fI.ch\fR to the source file name. |
| 5178 | .IP "\fBssa\fR" 4 |
| 5179 | .IX Item "ssa" |
| 5180 | Dump \s-1SSA\s0 related information to a file. The file name is made by appending |
| 5181 | \&\fI.ssa\fR to the source file name. |
| 5182 | .IP "\fBalias\fR" 4 |
| 5183 | .IX Item "alias" |
| 5184 | Dump aliasing information for each function. The file name is made by |
| 5185 | appending \fI.alias\fR to the source file name. |
| 5186 | .IP "\fBccp\fR" 4 |
| 5187 | .IX Item "ccp" |
| 5188 | Dump each function after \s-1CCP\s0. The file name is made by appending |
| 5189 | \&\fI.ccp\fR to the source file name. |
| 5190 | .IP "\fBstoreccp\fR" 4 |
| 5191 | .IX Item "storeccp" |
| 5192 | Dump each function after STORE-CCP. The file name is made by appending |
| 5193 | \&\fI.storeccp\fR to the source file name. |
| 5194 | .IP "\fBpre\fR" 4 |
| 5195 | .IX Item "pre" |
| 5196 | Dump trees after partial redundancy elimination. The file name is made |
| 5197 | by appending \fI.pre\fR to the source file name. |
| 5198 | .IP "\fBfre\fR" 4 |
| 5199 | .IX Item "fre" |
| 5200 | Dump trees after full redundancy elimination. The file name is made |
| 5201 | by appending \fI.fre\fR to the source file name. |
| 5202 | .IP "\fBcopyprop\fR" 4 |
| 5203 | .IX Item "copyprop" |
| 5204 | Dump trees after copy propagation. The file name is made |
| 5205 | by appending \fI.copyprop\fR to the source file name. |
| 5206 | .IP "\fBstore_copyprop\fR" 4 |
| 5207 | .IX Item "store_copyprop" |
| 5208 | Dump trees after store copy-propagation. The file name is made |
| 5209 | by appending \fI.store_copyprop\fR to the source file name. |
| 5210 | .IP "\fBdce\fR" 4 |
| 5211 | .IX Item "dce" |
| 5212 | Dump each function after dead code elimination. The file name is made by |
| 5213 | appending \fI.dce\fR to the source file name. |
| 5214 | .IP "\fBmudflap\fR" 4 |
| 5215 | .IX Item "mudflap" |
| 5216 | Dump each function after adding mudflap instrumentation. The file name is |
| 5217 | made by appending \fI.mudflap\fR to the source file name. |
| 5218 | .IP "\fBsra\fR" 4 |
| 5219 | .IX Item "sra" |
| 5220 | Dump each function after performing scalar replacement of aggregates. The |
| 5221 | file name is made by appending \fI.sra\fR to the source file name. |
| 5222 | .IP "\fBsink\fR" 4 |
| 5223 | .IX Item "sink" |
| 5224 | Dump each function after performing code sinking. The file name is made |
| 5225 | by appending \fI.sink\fR to the source file name. |
| 5226 | .IP "\fBdom\fR" 4 |
| 5227 | .IX Item "dom" |
| 5228 | Dump each function after applying dominator tree optimizations. The file |
| 5229 | name is made by appending \fI.dom\fR to the source file name. |
| 5230 | .IP "\fBdse\fR" 4 |
| 5231 | .IX Item "dse" |
| 5232 | Dump each function after applying dead store elimination. The file |
| 5233 | name is made by appending \fI.dse\fR to the source file name. |
| 5234 | .IP "\fBphiopt\fR" 4 |
| 5235 | .IX Item "phiopt" |
| 5236 | Dump each function after optimizing \s-1PHI\s0 nodes into straightline code. The file |
| 5237 | name is made by appending \fI.phiopt\fR to the source file name. |
| 5238 | .IP "\fBforwprop\fR" 4 |
| 5239 | .IX Item "forwprop" |
| 5240 | Dump each function after forward propagating single use variables. The file |
| 5241 | name is made by appending \fI.forwprop\fR to the source file name. |
| 5242 | .IP "\fBcopyrename\fR" 4 |
| 5243 | .IX Item "copyrename" |
| 5244 | Dump each function after applying the copy rename optimization. The file |
| 5245 | name is made by appending \fI.copyrename\fR to the source file name. |
| 5246 | .IP "\fBnrv\fR" 4 |
| 5247 | .IX Item "nrv" |
| 5248 | Dump each function after applying the named return value optimization on |
| 5249 | generic trees. The file name is made by appending \fI.nrv\fR to the source |
| 5250 | file name. |
| 5251 | .IP "\fBvect\fR" 4 |
| 5252 | .IX Item "vect" |
| 5253 | Dump each function after applying vectorization of loops. The file name is |
| 5254 | made by appending \fI.vect\fR to the source file name. |
| 5255 | .IP "\fBslp\fR" 4 |
| 5256 | .IX Item "slp" |
| 5257 | Dump each function after applying vectorization of basic blocks. The file name |
| 5258 | is made by appending \fI.slp\fR to the source file name. |
| 5259 | .IP "\fBvrp\fR" 4 |
| 5260 | .IX Item "vrp" |
| 5261 | Dump each function after Value Range Propagation (\s-1VRP\s0). The file name |
| 5262 | is made by appending \fI.vrp\fR to the source file name. |
| 5263 | .IP "\fBall\fR" 4 |
| 5264 | .IX Item "all" |
| 5265 | Enable all the available tree dumps with the flags provided in this option. |
| 5266 | .RE |
| 5267 | .RS 4 |
| 5268 | .RE |
| 5269 | .IP "\fB\-ftree\-vectorizer\-verbose=\fR\fIn\fR" 4 |
| 5270 | .IX Item "-ftree-vectorizer-verbose=n" |
| 5271 | This option controls the amount of debugging output the vectorizer prints. |
| 5272 | This information is written to standard error, unless |
| 5273 | \&\fB\-fdump\-tree\-all\fR or \fB\-fdump\-tree\-vect\fR is specified, |
| 5274 | in which case it is output to the usual dump listing file, \fI.vect\fR. |
| 5275 | For \fIn\fR=0 no diagnostic information is reported. |
| 5276 | If \fIn\fR=1 the vectorizer reports each loop that got vectorized, |
| 5277 | and the total number of loops that got vectorized. |
| 5278 | If \fIn\fR=2 the vectorizer also reports non-vectorized loops that passed |
| 5279 | the first analysis phase (vect_analyze_loop_form) \- i.e. countable, |
| 5280 | inner-most, single-bb, single\-entry/exit loops. This is the same verbosity |
| 5281 | level that \fB\-fdump\-tree\-vect\-stats\fR uses. |
| 5282 | Higher verbosity levels mean either more information dumped for each |
| 5283 | reported loop, or same amount of information reported for more loops: |
| 5284 | if \fIn\fR=3, vectorizer cost model information is reported. |
| 5285 | If \fIn\fR=4, alignment related information is added to the reports. |
| 5286 | If \fIn\fR=5, data-references related information (e.g. memory dependences, |
| 5287 | memory access-patterns) is added to the reports. |
| 5288 | If \fIn\fR=6, the vectorizer reports also non-vectorized inner-most loops |
| 5289 | that did not pass the first analysis phase (i.e., may not be countable, or |
| 5290 | may have complicated control-flow). |
| 5291 | If \fIn\fR=7, the vectorizer reports also non-vectorized nested loops. |
| 5292 | If \fIn\fR=8, \s-1SLP\s0 related information is added to the reports. |
| 5293 | For \fIn\fR=9, all the information the vectorizer generates during its |
| 5294 | analysis and transformation is reported. This is the same verbosity level |
| 5295 | that \fB\-fdump\-tree\-vect\-details\fR uses. |
| 5296 | .IP "\fB\-frandom\-seed=\fR\fIstring\fR" 4 |
| 5297 | .IX Item "-frandom-seed=string" |
| 5298 | This option provides a seed that \s-1GCC\s0 uses when it would otherwise use |
| 5299 | random numbers. It is used to generate certain symbol names |
| 5300 | that have to be different in every compiled file. It is also used to |
| 5301 | place unique stamps in coverage data files and the object files that |
| 5302 | produce them. You can use the \fB\-frandom\-seed\fR option to produce |
| 5303 | reproducibly identical object files. |
| 5304 | .Sp |
| 5305 | The \fIstring\fR should be different for every file you compile. |
| 5306 | .IP "\fB\-fsched\-verbose=\fR\fIn\fR" 4 |
| 5307 | .IX Item "-fsched-verbose=n" |
| 5308 | On targets that use instruction scheduling, this option controls the |
| 5309 | amount of debugging output the scheduler prints. This information is |
| 5310 | written to standard error, unless \fB\-fdump\-rtl\-sched1\fR or |
| 5311 | \&\fB\-fdump\-rtl\-sched2\fR is specified, in which case it is output |
| 5312 | to the usual dump listing file, \fI.sched1\fR or \fI.sched2\fR |
| 5313 | respectively. However for \fIn\fR greater than nine, the output is |
| 5314 | always printed to standard error. |
| 5315 | .Sp |
| 5316 | For \fIn\fR greater than zero, \fB\-fsched\-verbose\fR outputs the |
| 5317 | same information as \fB\-fdump\-rtl\-sched1\fR and \fB\-fdump\-rtl\-sched2\fR. |
| 5318 | For \fIn\fR greater than one, it also output basic block probabilities, |
| 5319 | detailed ready list information and unit/insn info. For \fIn\fR greater |
| 5320 | than two, it includes \s-1RTL\s0 at abort point, control-flow and regions info. |
| 5321 | And for \fIn\fR over four, \fB\-fsched\-verbose\fR also includes |
| 5322 | dependence info. |
| 5323 | .IP "\fB\-save\-temps\fR" 4 |
| 5324 | .IX Item "-save-temps" |
| 5325 | .PD 0 |
| 5326 | .IP "\fB\-save\-temps=cwd\fR" 4 |
| 5327 | .IX Item "-save-temps=cwd" |
| 5328 | .PD |
| 5329 | Store the usual \*(L"temporary\*(R" intermediate files permanently; place them |
| 5330 | in the current directory and name them based on the source file. Thus, |
| 5331 | compiling \fIfoo.c\fR with \fB\-c \-save\-temps\fR would produce files |
| 5332 | \&\fIfoo.i\fR and \fIfoo.s\fR, as well as \fIfoo.o\fR. This creates a |
| 5333 | preprocessed \fIfoo.i\fR output file even though the compiler now |
| 5334 | normally uses an integrated preprocessor. |
| 5335 | .Sp |
| 5336 | When used in combination with the \fB\-x\fR command-line option, |
| 5337 | \&\fB\-save\-temps\fR is sensible enough to avoid over writing an |
| 5338 | input source file with the same extension as an intermediate file. |
| 5339 | The corresponding intermediate file may be obtained by renaming the |
| 5340 | source file before using \fB\-save\-temps\fR. |
| 5341 | .Sp |
| 5342 | If you invoke \s-1GCC\s0 in parallel, compiling several different source |
| 5343 | files that share a common base name in different subdirectories or the |
| 5344 | same source file compiled for multiple output destinations, it is |
| 5345 | likely that the different parallel compilers will interfere with each |
| 5346 | other, and overwrite the temporary files. For instance: |
| 5347 | .Sp |
| 5348 | .Vb 2 |
| 5349 | \& gcc \-save\-temps \-o outdir1/foo.o indir1/foo.c& |
| 5350 | \& gcc \-save\-temps \-o outdir2/foo.o indir2/foo.c& |
| 5351 | .Ve |
| 5352 | .Sp |
| 5353 | may result in \fIfoo.i\fR and \fIfoo.o\fR being written to |
| 5354 | simultaneously by both compilers. |
| 5355 | .IP "\fB\-save\-temps=obj\fR" 4 |
| 5356 | .IX Item "-save-temps=obj" |
| 5357 | Store the usual \*(L"temporary\*(R" intermediate files permanently. If the |
| 5358 | \&\fB\-o\fR option is used, the temporary files are based on the |
| 5359 | object file. If the \fB\-o\fR option is not used, the |
| 5360 | \&\fB\-save\-temps=obj\fR switch behaves like \fB\-save\-temps\fR. |
| 5361 | .Sp |
| 5362 | For example: |
| 5363 | .Sp |
| 5364 | .Vb 3 |
| 5365 | \& gcc \-save\-temps=obj \-c foo.c |
| 5366 | \& gcc \-save\-temps=obj \-c bar.c \-o dir/xbar.o |
| 5367 | \& gcc \-save\-temps=obj foobar.c \-o dir2/yfoobar |
| 5368 | .Ve |
| 5369 | .Sp |
| 5370 | would create \fIfoo.i\fR, \fIfoo.s\fR, \fIdir/xbar.i\fR, |
| 5371 | \&\fIdir/xbar.s\fR, \fIdir2/yfoobar.i\fR, \fIdir2/yfoobar.s\fR, and |
| 5372 | \&\fIdir2/yfoobar.o\fR. |
| 5373 | .IP "\fB\-time\fR[\fB=\fR\fIfile\fR]" 4 |
| 5374 | .IX Item "-time[=file]" |
| 5375 | Report the \s-1CPU\s0 time taken by each subprocess in the compilation |
| 5376 | sequence. For C source files, this is the compiler proper and assembler |
| 5377 | (plus the linker if linking is done). |
| 5378 | .Sp |
| 5379 | Without the specification of an output file, the output looks like this: |
| 5380 | .Sp |
| 5381 | .Vb 2 |
| 5382 | \& # cc1 0.12 0.01 |
| 5383 | \& # as 0.00 0.01 |
| 5384 | .Ve |
| 5385 | .Sp |
| 5386 | The first number on each line is the \*(L"user time\*(R", that is time spent |
| 5387 | executing the program itself. The second number is \*(L"system time\*(R", |
| 5388 | time spent executing operating system routines on behalf of the program. |
| 5389 | Both numbers are in seconds. |
| 5390 | .Sp |
| 5391 | With the specification of an output file, the output is appended to the |
| 5392 | named file, and it looks like this: |
| 5393 | .Sp |
| 5394 | .Vb 2 |
| 5395 | \& 0.12 0.01 cc1 <options> |
| 5396 | \& 0.00 0.01 as <options> |
| 5397 | .Ve |
| 5398 | .Sp |
| 5399 | The \*(L"user time\*(R" and the \*(L"system time\*(R" are moved before the program |
| 5400 | name, and the options passed to the program are displayed, so that one |
| 5401 | can later tell what file was being compiled, and with which options. |
| 5402 | .IP "\fB\-fvar\-tracking\fR" 4 |
| 5403 | .IX Item "-fvar-tracking" |
| 5404 | Run variable tracking pass. It computes where variables are stored at each |
| 5405 | position in code. Better debugging information is then generated |
| 5406 | (if the debugging information format supports this information). |
| 5407 | .Sp |
| 5408 | It is enabled by default when compiling with optimization (\fB\-Os\fR, |
| 5409 | \&\fB\-O\fR, \fB\-O2\fR, ...), debugging information (\fB\-g\fR) and |
| 5410 | the debug info format supports it. |
| 5411 | .IP "\fB\-fvar\-tracking\-assignments\fR" 4 |
| 5412 | .IX Item "-fvar-tracking-assignments" |
| 5413 | Annotate assignments to user variables early in the compilation and |
| 5414 | attempt to carry the annotations over throughout the compilation all the |
| 5415 | way to the end, in an attempt to improve debug information while |
| 5416 | optimizing. Use of \fB\-gdwarf\-4\fR is recommended along with it. |
| 5417 | .Sp |
| 5418 | It can be enabled even if var-tracking is disabled, in which case |
| 5419 | annotations will be created and maintained, but discarded at the end. |
| 5420 | .IP "\fB\-fvar\-tracking\-assignments\-toggle\fR" 4 |
| 5421 | .IX Item "-fvar-tracking-assignments-toggle" |
| 5422 | Toggle \fB\-fvar\-tracking\-assignments\fR, in the same way that |
| 5423 | \&\fB\-gtoggle\fR toggles \fB\-g\fR. |
| 5424 | .IP "\fB\-print\-file\-name=\fR\fIlibrary\fR" 4 |
| 5425 | .IX Item "-print-file-name=library" |
| 5426 | Print the full absolute name of the library file \fIlibrary\fR that |
| 5427 | would be used when linking\-\-\-and don't do anything else. With this |
| 5428 | option, \s-1GCC\s0 does not compile or link anything; it just prints the |
| 5429 | file name. |
| 5430 | .IP "\fB\-print\-multi\-directory\fR" 4 |
| 5431 | .IX Item "-print-multi-directory" |
| 5432 | Print the directory name corresponding to the multilib selected by any |
| 5433 | other switches present in the command line. This directory is supposed |
| 5434 | to exist in \fB\s-1GCC_EXEC_PREFIX\s0\fR. |
| 5435 | .IP "\fB\-print\-multi\-lib\fR" 4 |
| 5436 | .IX Item "-print-multi-lib" |
| 5437 | Print the mapping from multilib directory names to compiler switches |
| 5438 | that enable them. The directory name is separated from the switches by |
| 5439 | \&\fB;\fR, and each switch starts with an \fB@\fR instead of the |
| 5440 | \&\fB\-\fR, without spaces between multiple switches. This is supposed to |
| 5441 | ease shell-processing. |
| 5442 | .IP "\fB\-print\-multi\-os\-directory\fR" 4 |
| 5443 | .IX Item "-print-multi-os-directory" |
| 5444 | Print the path to \s-1OS\s0 libraries for the selected |
| 5445 | multilib, relative to some \fIlib\fR subdirectory. If \s-1OS\s0 libraries are |
| 5446 | present in the \fIlib\fR subdirectory and no multilibs are used, this is |
| 5447 | usually just \fI.\fR, if \s-1OS\s0 libraries are present in \fIlib\fIsuffix\fI\fR |
| 5448 | sibling directories this prints e.g. \fI../lib64\fR, \fI../lib\fR or |
| 5449 | \&\fI../lib32\fR, or if \s-1OS\s0 libraries are present in \fIlib/\fIsubdir\fI\fR |
| 5450 | subdirectories it prints e.g. \fIamd64\fR, \fIsparcv9\fR or \fIev6\fR. |
| 5451 | .IP "\fB\-print\-multiarch\fR" 4 |
| 5452 | .IX Item "-print-multiarch" |
| 5453 | Print the path to \s-1OS\s0 libraries for the selected multiarch, |
| 5454 | relative to some \fIlib\fR subdirectory. |
| 5455 | .IP "\fB\-print\-prog\-name=\fR\fIprogram\fR" 4 |
| 5456 | .IX Item "-print-prog-name=program" |
| 5457 | Like \fB\-print\-file\-name\fR, but searches for a program such as \fBcpp\fR. |
| 5458 | .IP "\fB\-print\-libgcc\-file\-name\fR" 4 |
| 5459 | .IX Item "-print-libgcc-file-name" |
| 5460 | Same as \fB\-print\-file\-name=libgcc.a\fR. |
| 5461 | .Sp |
| 5462 | This is useful when you use \fB\-nostdlib\fR or \fB\-nodefaultlibs\fR |
| 5463 | but you do want to link with \fIlibgcc.a\fR. You can do |
| 5464 | .Sp |
| 5465 | .Vb 1 |
| 5466 | \& gcc \-nostdlib <files>... \`gcc \-print\-libgcc\-file\-name\` |
| 5467 | .Ve |
| 5468 | .IP "\fB\-print\-search\-dirs\fR" 4 |
| 5469 | .IX Item "-print-search-dirs" |
| 5470 | Print the name of the configured installation directory and a list of |
| 5471 | program and library directories \fBgcc\fR will search\-\-\-and don't do anything else. |
| 5472 | .Sp |
| 5473 | This is useful when \fBgcc\fR prints the error message |
| 5474 | \&\fBinstallation problem, cannot exec cpp0: No such file or directory\fR. |
| 5475 | To resolve this you either need to put \fIcpp0\fR and the other compiler |
| 5476 | components where \fBgcc\fR expects to find them, or you can set the environment |
| 5477 | variable \fB\s-1GCC_EXEC_PREFIX\s0\fR to the directory where you installed them. |
| 5478 | Don't forget the trailing \fB/\fR. |
| 5479 | .IP "\fB\-print\-sysroot\fR" 4 |
| 5480 | .IX Item "-print-sysroot" |
| 5481 | Print the target sysroot directory that will be used during |
| 5482 | compilation. This is the target sysroot specified either at configure |
| 5483 | time or using the \fB\-\-sysroot\fR option, possibly with an extra |
| 5484 | suffix that depends on compilation options. If no target sysroot is |
| 5485 | specified, the option prints nothing. |
| 5486 | .IP "\fB\-print\-sysroot\-headers\-suffix\fR" 4 |
| 5487 | .IX Item "-print-sysroot-headers-suffix" |
| 5488 | Print the suffix added to the target sysroot when searching for |
| 5489 | headers, or give an error if the compiler is not configured with such |
| 5490 | a suffix\-\-\-and don't do anything else. |
| 5491 | .IP "\fB\-dumpmachine\fR" 4 |
| 5492 | .IX Item "-dumpmachine" |
| 5493 | Print the compiler's target machine (for example, |
| 5494 | \&\fBi686\-pc\-linux\-gnu\fR)\-\-\-and don't do anything else. |
| 5495 | .IP "\fB\-dumpversion\fR" 4 |
| 5496 | .IX Item "-dumpversion" |
| 5497 | Print the compiler version (for example, \fB3.0\fR)\-\-\-and don't do |
| 5498 | anything else. |
| 5499 | .IP "\fB\-dumpspecs\fR" 4 |
| 5500 | .IX Item "-dumpspecs" |
| 5501 | Print the compiler's built-in specs\-\-\-and don't do anything else. (This |
| 5502 | is used when \s-1GCC\s0 itself is being built.) |
| 5503 | .IP "\fB\-feliminate\-unused\-debug\-types\fR" 4 |
| 5504 | .IX Item "-feliminate-unused-debug-types" |
| 5505 | Normally, when producing \s-1DWARF2\s0 output, \s-1GCC\s0 will emit debugging |
| 5506 | information for all types declared in a compilation |
| 5507 | unit, regardless of whether or not they are actually used |
| 5508 | in that compilation unit. Sometimes this is useful, such as |
| 5509 | if, in the debugger, you want to cast a value to a type that is |
| 5510 | not actually used in your program (but is declared). More often, |
| 5511 | however, this results in a significant amount of wasted space. |
| 5512 | With this option, \s-1GCC\s0 will avoid producing debug symbol output |
| 5513 | for types that are nowhere used in the source file being compiled. |
| 5514 | .Sh "Options That Control Optimization" |
| 5515 | .IX Subsection "Options That Control Optimization" |
| 5516 | These options control various sorts of optimizations. |
| 5517 | .PP |
| 5518 | Without any optimization option, the compiler's goal is to reduce the |
| 5519 | cost of compilation and to make debugging produce the expected |
| 5520 | results. Statements are independent: if you stop the program with a |
| 5521 | breakpoint between statements, you can then assign a new value to any |
| 5522 | variable or change the program counter to any other statement in the |
| 5523 | function and get exactly the results you would expect from the source |
| 5524 | code. |
| 5525 | .PP |
| 5526 | Turning on optimization flags makes the compiler attempt to improve |
| 5527 | the performance and/or code size at the expense of compilation time |
| 5528 | and possibly the ability to debug the program. |
| 5529 | .PP |
| 5530 | The compiler performs optimization based on the knowledge it has of the |
| 5531 | program. Compiling multiple files at once to a single output file mode allows |
| 5532 | the compiler to use information gained from all of the files when compiling |
| 5533 | each of them. |
| 5534 | .PP |
| 5535 | Not all optimizations are controlled directly by a flag. Only |
| 5536 | optimizations that have a flag are listed in this section. |
| 5537 | .PP |
| 5538 | Most optimizations are only enabled if an \fB\-O\fR level is set on |
| 5539 | the command line. Otherwise they are disabled, even if individual |
| 5540 | optimization flags are specified. |
| 5541 | .PP |
| 5542 | Depending on the target and how \s-1GCC\s0 was configured, a slightly different |
| 5543 | set of optimizations may be enabled at each \fB\-O\fR level than |
| 5544 | those listed here. You can invoke \s-1GCC\s0 with \fB\-Q \-\-help=optimizers\fR |
| 5545 | to find out the exact set of optimizations that are enabled at each level. |
| 5546 | .IP "\fB\-O\fR" 4 |
| 5547 | .IX Item "-O" |
| 5548 | .PD 0 |
| 5549 | .IP "\fB\-O1\fR" 4 |
| 5550 | .IX Item "-O1" |
| 5551 | .PD |
| 5552 | Optimize. Optimizing compilation takes somewhat more time, and a lot |
| 5553 | more memory for a large function. |
| 5554 | .Sp |
| 5555 | With \fB\-O\fR, the compiler tries to reduce code size and execution |
| 5556 | time, without performing any optimizations that take a great deal of |
| 5557 | compilation time. |
| 5558 | .Sp |
| 5559 | \&\fB\-O\fR turns on the following optimization flags: |
| 5560 | .Sp |
| 5561 | \&\fB\-fauto\-inc\-dec |
| 5562 | \&\-fcompare\-elim |
| 5563 | \&\-fcprop\-registers |
| 5564 | \&\-fdce |
| 5565 | \&\-fdefer\-pop |
| 5566 | \&\-fdelayed\-branch |
| 5567 | \&\-fdse |
| 5568 | \&\-fguess\-branch\-probability |
| 5569 | \&\-fif\-conversion2 |
| 5570 | \&\-fif\-conversion |
| 5571 | \&\-fipa\-pure\-const |
| 5572 | \&\-fipa\-profile |
| 5573 | \&\-fipa\-reference |
| 5574 | \&\-fmerge\-constants |
| 5575 | \&\-fsplit\-wide\-types |
| 5576 | \&\-ftree\-bit\-ccp |
| 5577 | \&\-ftree\-builtin\-call\-dce |
| 5578 | \&\-ftree\-ccp |
| 5579 | \&\-ftree\-ch |
| 5580 | \&\-ftree\-copyrename |
| 5581 | \&\-ftree\-dce |
| 5582 | \&\-ftree\-dominator\-opts |
| 5583 | \&\-ftree\-dse |
| 5584 | \&\-ftree\-forwprop |
| 5585 | \&\-ftree\-fre |
| 5586 | \&\-ftree\-phiprop |
| 5587 | \&\-ftree\-sra |
| 5588 | \&\-ftree\-pta |
| 5589 | \&\-ftree\-ter |
| 5590 | \&\-funit\-at\-a\-time\fR |
| 5591 | .Sp |
| 5592 | \&\fB\-O\fR also turns on \fB\-fomit\-frame\-pointer\fR on machines |
| 5593 | where doing so does not interfere with debugging. |
| 5594 | .IP "\fB\-O2\fR" 4 |
| 5595 | .IX Item "-O2" |
| 5596 | Optimize even more. \s-1GCC\s0 performs nearly all supported optimizations |
| 5597 | that do not involve a space-speed tradeoff. |
| 5598 | As compared to \fB\-O\fR, this option increases both compilation time |
| 5599 | and the performance of the generated code. |
| 5600 | .Sp |
| 5601 | \&\fB\-O2\fR turns on all optimization flags specified by \fB\-O\fR. It |
| 5602 | also turns on the following optimization flags: |
| 5603 | \&\fB\-fthread\-jumps |
| 5604 | \&\-falign\-functions \-falign\-jumps |
| 5605 | \&\-falign\-loops \-falign\-labels |
| 5606 | \&\-fcaller\-saves |
| 5607 | \&\-fcrossjumping |
| 5608 | \&\-fcse\-follow\-jumps \-fcse\-skip\-blocks |
| 5609 | \&\-fdelete\-null\-pointer\-checks |
| 5610 | \&\-fdevirtualize |
| 5611 | \&\-fexpensive\-optimizations |
| 5612 | \&\-fgcse \-fgcse\-lm |
| 5613 | \&\-finline\-small\-functions |
| 5614 | \&\-findirect\-inlining |
| 5615 | \&\-fipa\-sra |
| 5616 | \&\-foptimize\-sibling\-calls |
| 5617 | \&\-fpartial\-inlining |
| 5618 | \&\-fpeephole2 |
| 5619 | \&\-fregmove |
| 5620 | \&\-freorder\-blocks \-freorder\-functions |
| 5621 | \&\-frerun\-cse\-after\-loop |
| 5622 | \&\-fsched\-interblock \-fsched\-spec |
| 5623 | \&\-fschedule\-insns \-fschedule\-insns2 |
| 5624 | \&\-fstrict\-aliasing \-fstrict\-overflow |
| 5625 | \&\-ftree\-switch\-conversion \-ftree\-tail\-merge |
| 5626 | \&\-ftree\-pre |
| 5627 | \&\-ftree\-vrp\fR |
| 5628 | .Sp |
| 5629 | Please note the warning under \fB\-fgcse\fR about |
| 5630 | invoking \fB\-O2\fR on programs that use computed gotos. |
| 5631 | .IP "\fB\-O3\fR" 4 |
| 5632 | .IX Item "-O3" |
| 5633 | Optimize yet more. \fB\-O3\fR turns on all optimizations specified |
| 5634 | by \fB\-O2\fR and also turns on the \fB\-finline\-functions\fR, |
| 5635 | \&\fB\-funswitch\-loops\fR, \fB\-fpredictive\-commoning\fR, |
| 5636 | \&\fB\-fgcse\-after\-reload\fR, \fB\-ftree\-vectorize\fR and |
| 5637 | \&\fB\-fipa\-cp\-clone\fR options. |
| 5638 | .IP "\fB\-O0\fR" 4 |
| 5639 | .IX Item "-O0" |
| 5640 | Reduce compilation time and make debugging produce the expected |
| 5641 | results. This is the default. |
| 5642 | .IP "\fB\-Os\fR" 4 |
| 5643 | .IX Item "-Os" |
| 5644 | Optimize for size. \fB\-Os\fR enables all \fB\-O2\fR optimizations that |
| 5645 | do not typically increase code size. It also performs further |
| 5646 | optimizations designed to reduce code size. |
| 5647 | .Sp |
| 5648 | \&\fB\-Os\fR disables the following optimization flags: |
| 5649 | \&\fB\-falign\-functions \-falign\-jumps \-falign\-loops |
| 5650 | \&\-falign\-labels \-freorder\-blocks \-freorder\-blocks\-and\-partition |
| 5651 | \&\-fprefetch\-loop\-arrays \-ftree\-vect\-loop\-version\fR |
| 5652 | .IP "\fB\-Ofast\fR" 4 |
| 5653 | .IX Item "-Ofast" |
| 5654 | Disregard strict standards compliance. \fB\-Ofast\fR enables all |
| 5655 | \&\fB\-O3\fR optimizations. It also enables optimizations that are not |
| 5656 | valid for all standard compliant programs. |
| 5657 | It turns on \fB\-ffast\-math\fR and the Fortran-specific |
| 5658 | \&\fB\-fno\-protect\-parens\fR and \fB\-fstack\-arrays\fR. |
| 5659 | .Sp |
| 5660 | If you use multiple \fB\-O\fR options, with or without level numbers, |
| 5661 | the last such option is the one that is effective. |
| 5662 | .PP |
| 5663 | Options of the form \fB\-f\fR\fIflag\fR specify machine-independent |
| 5664 | flags. Most flags have both positive and negative forms; the negative |
| 5665 | form of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. In the table |
| 5666 | below, only one of the forms is listed\-\-\-the one you typically will |
| 5667 | use. You can figure out the other form by either removing \fBno\-\fR |
| 5668 | or adding it. |
| 5669 | .PP |
| 5670 | The following options control specific optimizations. They are either |
| 5671 | activated by \fB\-O\fR options or are related to ones that are. You |
| 5672 | can use the following flags in the rare cases when \*(L"fine-tuning\*(R" of |
| 5673 | optimizations to be performed is desired. |
| 5674 | .IP "\fB\-fno\-default\-inline\fR" 4 |
| 5675 | .IX Item "-fno-default-inline" |
| 5676 | Do not make member functions inline by default merely because they are |
| 5677 | defined inside the class scope (\*(C+ only). Otherwise, when you specify |
| 5678 | \&\fB\-O\fR, member functions defined inside class scope are compiled |
| 5679 | inline by default; i.e., you don't need to add \fBinline\fR in front of |
| 5680 | the member function name. |
| 5681 | .IP "\fB\-fno\-defer\-pop\fR" 4 |
| 5682 | .IX Item "-fno-defer-pop" |
| 5683 | Always pop the arguments to each function call as soon as that function |
| 5684 | returns. For machines that must pop arguments after a function call, |
| 5685 | the compiler normally lets arguments accumulate on the stack for several |
| 5686 | function calls and pops them all at once. |
| 5687 | .Sp |
| 5688 | Disabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5689 | .IP "\fB\-fforward\-propagate\fR" 4 |
| 5690 | .IX Item "-fforward-propagate" |
| 5691 | Perform a forward propagation pass on \s-1RTL\s0. The pass tries to combine two |
| 5692 | instructions and checks if the result can be simplified. If loop unrolling |
| 5693 | is active, two passes are performed and the second is scheduled after |
| 5694 | loop unrolling. |
| 5695 | .Sp |
| 5696 | This option is enabled by default at optimization levels \fB\-O\fR, |
| 5697 | \&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5698 | .IP "\fB\-ffp\-contract=\fR\fIstyle\fR" 4 |
| 5699 | .IX Item "-ffp-contract=style" |
| 5700 | \&\fB\-ffp\-contract=off\fR disables floating-point expression contraction. |
| 5701 | \&\fB\-ffp\-contract=fast\fR enables floating-point expression contraction |
| 5702 | such as forming of fused multiply-add operations if the target has |
| 5703 | native support for them. |
| 5704 | \&\fB\-ffp\-contract=on\fR enables floating-point expression contraction |
| 5705 | if allowed by the language standard. This is currently not implemented |
| 5706 | and treated equal to \fB\-ffp\-contract=off\fR. |
| 5707 | .Sp |
| 5708 | The default is \fB\-ffp\-contract=fast\fR. |
| 5709 | .IP "\fB\-fomit\-frame\-pointer\fR" 4 |
| 5710 | .IX Item "-fomit-frame-pointer" |
| 5711 | Don't keep the frame pointer in a register for functions that |
| 5712 | don't need one. This avoids the instructions to save, set up and |
| 5713 | restore frame pointers; it also makes an extra register available |
| 5714 | in many functions. \fBIt also makes debugging impossible on |
| 5715 | some machines.\fR |
| 5716 | .Sp |
| 5717 | On some machines, such as the \s-1VAX\s0, this flag has no effect, because |
| 5718 | the standard calling sequence automatically handles the frame pointer |
| 5719 | and nothing is saved by pretending it doesn't exist. The |
| 5720 | machine-description macro \f(CW\*(C`FRAME_POINTER_REQUIRED\*(C'\fR controls |
| 5721 | whether a target machine supports this flag. |
| 5722 | .Sp |
| 5723 | Starting with \s-1GCC\s0 version 4.6, the default setting (when not optimizing for |
| 5724 | size) for 32\-bit Linux x86 and 32\-bit Darwin x86 targets has been changed to |
| 5725 | \&\fB\-fomit\-frame\-pointer\fR. The default can be reverted to |
| 5726 | \&\fB\-fno\-omit\-frame\-pointer\fR by configuring \s-1GCC\s0 with the |
| 5727 | \&\fB\-\-enable\-frame\-pointer\fR configure option. |
| 5728 | .Sp |
| 5729 | Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5730 | .IP "\fB\-foptimize\-sibling\-calls\fR" 4 |
| 5731 | .IX Item "-foptimize-sibling-calls" |
| 5732 | Optimize sibling and tail recursive calls. |
| 5733 | .Sp |
| 5734 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5735 | .IP "\fB\-fno\-inline\fR" 4 |
| 5736 | .IX Item "-fno-inline" |
| 5737 | Do not expand any functions inline apart from those marked with |
| 5738 | the \f(CW\*(C`always_inline\*(C'\fR attribute. This is the default when not |
| 5739 | optimizing. |
| 5740 | .Sp |
| 5741 | Single functions can be exempted from inlining by marking them |
| 5742 | with the \f(CW\*(C`noinline\*(C'\fR attribute. |
| 5743 | .IP "\fB\-finline\-small\-functions\fR" 4 |
| 5744 | .IX Item "-finline-small-functions" |
| 5745 | Integrate functions into their callers when their body is smaller than expected |
| 5746 | function call code (so overall size of program gets smaller). The compiler |
| 5747 | heuristically decides which functions are simple enough to be worth integrating |
| 5748 | in this way. This inlining applies to all functions, even those not declared |
| 5749 | inline. |
| 5750 | .Sp |
| 5751 | Enabled at level \fB\-O2\fR. |
| 5752 | .IP "\fB\-findirect\-inlining\fR" 4 |
| 5753 | .IX Item "-findirect-inlining" |
| 5754 | Inline also indirect calls that are discovered to be known at compile |
| 5755 | time thanks to previous inlining. This option has any effect only |
| 5756 | when inlining itself is turned on by the \fB\-finline\-functions\fR |
| 5757 | or \fB\-finline\-small\-functions\fR options. |
| 5758 | .Sp |
| 5759 | Enabled at level \fB\-O2\fR. |
| 5760 | .IP "\fB\-finline\-functions\fR" 4 |
| 5761 | .IX Item "-finline-functions" |
| 5762 | Consider all functions for inlining, even if they are not declared inline. |
| 5763 | The compiler heuristically decides which functions are worth integrating |
| 5764 | in this way. |
| 5765 | .Sp |
| 5766 | If all calls to a given function are integrated, and the function is |
| 5767 | declared \f(CW\*(C`static\*(C'\fR, then the function is normally not output as |
| 5768 | assembler code in its own right. |
| 5769 | .Sp |
| 5770 | Enabled at level \fB\-O3\fR. |
| 5771 | .IP "\fB\-finline\-functions\-called\-once\fR" 4 |
| 5772 | .IX Item "-finline-functions-called-once" |
| 5773 | Consider all \f(CW\*(C`static\*(C'\fR functions called once for inlining into their |
| 5774 | caller even if they are not marked \f(CW\*(C`inline\*(C'\fR. If a call to a given |
| 5775 | function is integrated, then the function is not output as assembler code |
| 5776 | in its own right. |
| 5777 | .Sp |
| 5778 | Enabled at levels \fB\-O1\fR, \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR. |
| 5779 | .IP "\fB\-fearly\-inlining\fR" 4 |
| 5780 | .IX Item "-fearly-inlining" |
| 5781 | Inline functions marked by \f(CW\*(C`always_inline\*(C'\fR and functions whose body seems |
| 5782 | smaller than the function call overhead early before doing |
| 5783 | \&\fB\-fprofile\-generate\fR instrumentation and real inlining pass. Doing so |
| 5784 | makes profiling significantly cheaper and usually inlining faster on programs |
| 5785 | having large chains of nested wrapper functions. |
| 5786 | .Sp |
| 5787 | Enabled by default. |
| 5788 | .IP "\fB\-fipa\-sra\fR" 4 |
| 5789 | .IX Item "-fipa-sra" |
| 5790 | Perform interprocedural scalar replacement of aggregates, removal of |
| 5791 | unused parameters and replacement of parameters passed by reference |
| 5792 | by parameters passed by value. |
| 5793 | .Sp |
| 5794 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR and \fB\-Os\fR. |
| 5795 | .IP "\fB\-finline\-limit=\fR\fIn\fR" 4 |
| 5796 | .IX Item "-finline-limit=n" |
| 5797 | By default, \s-1GCC\s0 limits the size of functions that can be inlined. This flag |
| 5798 | allows coarse control of this limit. \fIn\fR is the size of functions that |
| 5799 | can be inlined in number of pseudo instructions. |
| 5800 | .Sp |
| 5801 | Inlining is actually controlled by a number of parameters, which may be |
| 5802 | specified individually by using \fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR. |
| 5803 | The \fB\-finline\-limit=\fR\fIn\fR option sets some of these parameters |
| 5804 | as follows: |
| 5805 | .RS 4 |
| 5806 | .IP "\fBmax-inline-insns-single\fR" 4 |
| 5807 | .IX Item "max-inline-insns-single" |
| 5808 | is set to \fIn\fR/2. |
| 5809 | .IP "\fBmax-inline-insns-auto\fR" 4 |
| 5810 | .IX Item "max-inline-insns-auto" |
| 5811 | is set to \fIn\fR/2. |
| 5812 | .RE |
| 5813 | .RS 4 |
| 5814 | .Sp |
| 5815 | See below for a documentation of the individual |
| 5816 | parameters controlling inlining and for the defaults of these parameters. |
| 5817 | .Sp |
| 5818 | \&\fINote:\fR there may be no value to \fB\-finline\-limit\fR that results |
| 5819 | in default behavior. |
| 5820 | .Sp |
| 5821 | \&\fINote:\fR pseudo instruction represents, in this particular context, an |
| 5822 | abstract measurement of function's size. In no way does it represent a count |
| 5823 | of assembly instructions and as such its exact meaning might change from one |
| 5824 | release to an another. |
| 5825 | .RE |
| 5826 | .IP "\fB\-fno\-keep\-inline\-dllexport\fR" 4 |
| 5827 | .IX Item "-fno-keep-inline-dllexport" |
| 5828 | This is a more fine-grained version of \fB\-fkeep\-inline\-functions\fR, |
| 5829 | which applies only to functions that are declared using the \f(CW\*(C`dllexport\*(C'\fR |
| 5830 | attribute or declspec |
| 5831 | .IP "\fB\-fkeep\-inline\-functions\fR" 4 |
| 5832 | .IX Item "-fkeep-inline-functions" |
| 5833 | In C, emit \f(CW\*(C`static\*(C'\fR functions that are declared \f(CW\*(C`inline\*(C'\fR |
| 5834 | into the object file, even if the function has been inlined into all |
| 5835 | of its callers. This switch does not affect functions using the |
| 5836 | \&\f(CW\*(C`extern inline\*(C'\fR extension in \s-1GNU\s0 C90. In \*(C+, emit any and all |
| 5837 | inline functions into the object file. |
| 5838 | .IP "\fB\-fkeep\-static\-consts\fR" 4 |
| 5839 | .IX Item "-fkeep-static-consts" |
| 5840 | Emit variables declared \f(CW\*(C`static const\*(C'\fR when optimization isn't turned |
| 5841 | on, even if the variables aren't referenced. |
| 5842 | .Sp |
| 5843 | \&\s-1GCC\s0 enables this option by default. If you want to force the compiler to |
| 5844 | check if the variable was referenced, regardless of whether or not |
| 5845 | optimization is turned on, use the \fB\-fno\-keep\-static\-consts\fR option. |
| 5846 | .IP "\fB\-fmerge\-constants\fR" 4 |
| 5847 | .IX Item "-fmerge-constants" |
| 5848 | Attempt to merge identical constants (string constants and floating-point |
| 5849 | constants) across compilation units. |
| 5850 | .Sp |
| 5851 | This option is the default for optimized compilation if the assembler and |
| 5852 | linker support it. Use \fB\-fno\-merge\-constants\fR to inhibit this |
| 5853 | behavior. |
| 5854 | .Sp |
| 5855 | Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5856 | .IP "\fB\-fmerge\-all\-constants\fR" 4 |
| 5857 | .IX Item "-fmerge-all-constants" |
| 5858 | Attempt to merge identical constants and identical variables. |
| 5859 | .Sp |
| 5860 | This option implies \fB\-fmerge\-constants\fR. In addition to |
| 5861 | \&\fB\-fmerge\-constants\fR this considers e.g. even constant initialized |
| 5862 | arrays or initialized constant variables with integral or floating-point |
| 5863 | types. Languages like C or \*(C+ require each variable, including multiple |
| 5864 | instances of the same variable in recursive calls, to have distinct locations, |
| 5865 | so using this option will result in non-conforming |
| 5866 | behavior. |
| 5867 | .IP "\fB\-fmodulo\-sched\fR" 4 |
| 5868 | .IX Item "-fmodulo-sched" |
| 5869 | Perform swing modulo scheduling immediately before the first scheduling |
| 5870 | pass. This pass looks at innermost loops and reorders their |
| 5871 | instructions by overlapping different iterations. |
| 5872 | .IP "\fB\-fmodulo\-sched\-allow\-regmoves\fR" 4 |
| 5873 | .IX Item "-fmodulo-sched-allow-regmoves" |
| 5874 | Perform more aggressive \s-1SMS\s0 based modulo scheduling with register moves |
| 5875 | allowed. By setting this flag certain anti-dependences edges will be |
| 5876 | deleted which will trigger the generation of reg-moves based on the |
| 5877 | life-range analysis. This option is effective only with |
| 5878 | \&\fB\-fmodulo\-sched\fR enabled. |
| 5879 | .IP "\fB\-fno\-branch\-count\-reg\fR" 4 |
| 5880 | .IX Item "-fno-branch-count-reg" |
| 5881 | Do not use \*(L"decrement and branch\*(R" instructions on a count register, |
| 5882 | but instead generate a sequence of instructions that decrement a |
| 5883 | register, compare it against zero, then branch based upon the result. |
| 5884 | This option is only meaningful on architectures that support such |
| 5885 | instructions, which include x86, PowerPC, \s-1IA\-64\s0 and S/390. |
| 5886 | .Sp |
| 5887 | The default is \fB\-fbranch\-count\-reg\fR. |
| 5888 | .IP "\fB\-fno\-function\-cse\fR" 4 |
| 5889 | .IX Item "-fno-function-cse" |
| 5890 | Do not put function addresses in registers; make each instruction that |
| 5891 | calls a constant function contain the function's address explicitly. |
| 5892 | .Sp |
| 5893 | This option results in less efficient code, but some strange hacks |
| 5894 | that alter the assembler output may be confused by the optimizations |
| 5895 | performed when this option is not used. |
| 5896 | .Sp |
| 5897 | The default is \fB\-ffunction\-cse\fR |
| 5898 | .IP "\fB\-fno\-zero\-initialized\-in\-bss\fR" 4 |
| 5899 | .IX Item "-fno-zero-initialized-in-bss" |
| 5900 | If the target supports a \s-1BSS\s0 section, \s-1GCC\s0 by default puts variables that |
| 5901 | are initialized to zero into \s-1BSS\s0. This can save space in the resulting |
| 5902 | code. |
| 5903 | .Sp |
| 5904 | This option turns off this behavior because some programs explicitly |
| 5905 | rely on variables going to the data section. E.g., so that the |
| 5906 | resulting executable can find the beginning of that section and/or make |
| 5907 | assumptions based on that. |
| 5908 | .Sp |
| 5909 | The default is \fB\-fzero\-initialized\-in\-bss\fR. |
| 5910 | .IP "\fB\-fmudflap \-fmudflapth \-fmudflapir\fR" 4 |
| 5911 | .IX Item "-fmudflap -fmudflapth -fmudflapir" |
| 5912 | For front-ends that support it (C and \*(C+), instrument all risky |
| 5913 | pointer/array dereferencing operations, some standard library |
| 5914 | string/heap functions, and some other associated constructs with |
| 5915 | range/validity tests. Modules so instrumented should be immune to |
| 5916 | buffer overflows, invalid heap use, and some other classes of C/\*(C+ |
| 5917 | programming errors. The instrumentation relies on a separate runtime |
| 5918 | library (\fIlibmudflap\fR), which will be linked into a program if |
| 5919 | \&\fB\-fmudflap\fR is given at link time. Run-time behavior of the |
| 5920 | instrumented program is controlled by the \fB\s-1MUDFLAP_OPTIONS\s0\fR |
| 5921 | environment variable. See \f(CW\*(C`env MUDFLAP_OPTIONS=\-help a.out\*(C'\fR |
| 5922 | for its options. |
| 5923 | .Sp |
| 5924 | Use \fB\-fmudflapth\fR instead of \fB\-fmudflap\fR to compile and to |
| 5925 | link if your program is multi-threaded. Use \fB\-fmudflapir\fR, in |
| 5926 | addition to \fB\-fmudflap\fR or \fB\-fmudflapth\fR, if |
| 5927 | instrumentation should ignore pointer reads. This produces less |
| 5928 | instrumentation (and therefore faster execution) and still provides |
| 5929 | some protection against outright memory corrupting writes, but allows |
| 5930 | erroneously read data to propagate within a program. |
| 5931 | .IP "\fB\-fthread\-jumps\fR" 4 |
| 5932 | .IX Item "-fthread-jumps" |
| 5933 | Perform optimizations where we check to see if a jump branches to a |
| 5934 | location where another comparison subsumed by the first is found. If |
| 5935 | so, the first branch is redirected to either the destination of the |
| 5936 | second branch or a point immediately following it, depending on whether |
| 5937 | the condition is known to be true or false. |
| 5938 | .Sp |
| 5939 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5940 | .IP "\fB\-fsplit\-wide\-types\fR" 4 |
| 5941 | .IX Item "-fsplit-wide-types" |
| 5942 | When using a type that occupies multiple registers, such as \f(CW\*(C`long |
| 5943 | long\*(C'\fR on a 32\-bit system, split the registers apart and allocate them |
| 5944 | independently. This normally generates better code for those types, |
| 5945 | but may make debugging more difficult. |
| 5946 | .Sp |
| 5947 | Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, |
| 5948 | \&\fB\-Os\fR. |
| 5949 | .IP "\fB\-fcse\-follow\-jumps\fR" 4 |
| 5950 | .IX Item "-fcse-follow-jumps" |
| 5951 | In common subexpression elimination (\s-1CSE\s0), scan through jump instructions |
| 5952 | when the target of the jump is not reached by any other path. For |
| 5953 | example, when \s-1CSE\s0 encounters an \f(CW\*(C`if\*(C'\fR statement with an |
| 5954 | \&\f(CW\*(C`else\*(C'\fR clause, \s-1CSE\s0 will follow the jump when the condition |
| 5955 | tested is false. |
| 5956 | .Sp |
| 5957 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5958 | .IP "\fB\-fcse\-skip\-blocks\fR" 4 |
| 5959 | .IX Item "-fcse-skip-blocks" |
| 5960 | This is similar to \fB\-fcse\-follow\-jumps\fR, but causes \s-1CSE\s0 to |
| 5961 | follow jumps that conditionally skip over blocks. When \s-1CSE\s0 |
| 5962 | encounters a simple \f(CW\*(C`if\*(C'\fR statement with no else clause, |
| 5963 | \&\fB\-fcse\-skip\-blocks\fR causes \s-1CSE\s0 to follow the jump around the |
| 5964 | body of the \f(CW\*(C`if\*(C'\fR. |
| 5965 | .Sp |
| 5966 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5967 | .IP "\fB\-frerun\-cse\-after\-loop\fR" 4 |
| 5968 | .IX Item "-frerun-cse-after-loop" |
| 5969 | Re-run common subexpression elimination after loop optimizations has been |
| 5970 | performed. |
| 5971 | .Sp |
| 5972 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5973 | .IP "\fB\-fgcse\fR" 4 |
| 5974 | .IX Item "-fgcse" |
| 5975 | Perform a global common subexpression elimination pass. |
| 5976 | This pass also performs global constant and copy propagation. |
| 5977 | .Sp |
| 5978 | \&\fINote:\fR When compiling a program using computed gotos, a \s-1GCC\s0 |
| 5979 | extension, you may get better run-time performance if you disable |
| 5980 | the global common subexpression elimination pass by adding |
| 5981 | \&\fB\-fno\-gcse\fR to the command line. |
| 5982 | .Sp |
| 5983 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 5984 | .IP "\fB\-fgcse\-lm\fR" 4 |
| 5985 | .IX Item "-fgcse-lm" |
| 5986 | When \fB\-fgcse\-lm\fR is enabled, global common subexpression elimination will |
| 5987 | attempt to move loads that are only killed by stores into themselves. This |
| 5988 | allows a loop containing a load/store sequence to be changed to a load outside |
| 5989 | the loop, and a copy/store within the loop. |
| 5990 | .Sp |
| 5991 | Enabled by default when gcse is enabled. |
| 5992 | .IP "\fB\-fgcse\-sm\fR" 4 |
| 5993 | .IX Item "-fgcse-sm" |
| 5994 | When \fB\-fgcse\-sm\fR is enabled, a store motion pass is run after |
| 5995 | global common subexpression elimination. This pass will attempt to move |
| 5996 | stores out of loops. When used in conjunction with \fB\-fgcse\-lm\fR, |
| 5997 | loops containing a load/store sequence can be changed to a load before |
| 5998 | the loop and a store after the loop. |
| 5999 | .Sp |
| 6000 | Not enabled at any optimization level. |
| 6001 | .IP "\fB\-fgcse\-las\fR" 4 |
| 6002 | .IX Item "-fgcse-las" |
| 6003 | When \fB\-fgcse\-las\fR is enabled, the global common subexpression |
| 6004 | elimination pass eliminates redundant loads that come after stores to the |
| 6005 | same memory location (both partial and full redundancies). |
| 6006 | .Sp |
| 6007 | Not enabled at any optimization level. |
| 6008 | .IP "\fB\-fgcse\-after\-reload\fR" 4 |
| 6009 | .IX Item "-fgcse-after-reload" |
| 6010 | When \fB\-fgcse\-after\-reload\fR is enabled, a redundant load elimination |
| 6011 | pass is performed after reload. The purpose of this pass is to cleanup |
| 6012 | redundant spilling. |
| 6013 | .IP "\fB\-funsafe\-loop\-optimizations\fR" 4 |
| 6014 | .IX Item "-funsafe-loop-optimizations" |
| 6015 | If given, the loop optimizer will assume that loop indices do not |
| 6016 | overflow, and that the loops with nontrivial exit condition are not |
| 6017 | infinite. This enables a wider range of loop optimizations even if |
| 6018 | the loop optimizer itself cannot prove that these assumptions are valid. |
| 6019 | Using \fB\-Wunsafe\-loop\-optimizations\fR, the compiler will warn you |
| 6020 | if it finds this kind of loop. |
| 6021 | .IP "\fB\-fcrossjumping\fR" 4 |
| 6022 | .IX Item "-fcrossjumping" |
| 6023 | Perform cross-jumping transformation. This transformation unifies equivalent code and save code size. The |
| 6024 | resulting code may or may not perform better than without cross-jumping. |
| 6025 | .Sp |
| 6026 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6027 | .IP "\fB\-fauto\-inc\-dec\fR" 4 |
| 6028 | .IX Item "-fauto-inc-dec" |
| 6029 | Combine increments or decrements of addresses with memory accesses. |
| 6030 | This pass is always skipped on architectures that do not have |
| 6031 | instructions to support this. Enabled by default at \fB\-O\fR and |
| 6032 | higher on architectures that support this. |
| 6033 | .IP "\fB\-fdce\fR" 4 |
| 6034 | .IX Item "-fdce" |
| 6035 | Perform dead code elimination (\s-1DCE\s0) on \s-1RTL\s0. |
| 6036 | Enabled by default at \fB\-O\fR and higher. |
| 6037 | .IP "\fB\-fdse\fR" 4 |
| 6038 | .IX Item "-fdse" |
| 6039 | Perform dead store elimination (\s-1DSE\s0) on \s-1RTL\s0. |
| 6040 | Enabled by default at \fB\-O\fR and higher. |
| 6041 | .IP "\fB\-fif\-conversion\fR" 4 |
| 6042 | .IX Item "-fif-conversion" |
| 6043 | Attempt to transform conditional jumps into branch-less equivalents. This |
| 6044 | include use of conditional moves, min, max, set flags and abs instructions, and |
| 6045 | some tricks doable by standard arithmetics. The use of conditional execution |
| 6046 | on chips where it is available is controlled by \f(CW\*(C`if\-conversion2\*(C'\fR. |
| 6047 | .Sp |
| 6048 | Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6049 | .IP "\fB\-fif\-conversion2\fR" 4 |
| 6050 | .IX Item "-fif-conversion2" |
| 6051 | Use conditional execution (where available) to transform conditional jumps into |
| 6052 | branch-less equivalents. |
| 6053 | .Sp |
| 6054 | Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6055 | .IP "\fB\-fdelete\-null\-pointer\-checks\fR" 4 |
| 6056 | .IX Item "-fdelete-null-pointer-checks" |
| 6057 | Assume that programs cannot safely dereference null pointers, and that |
| 6058 | no code or data element resides there. This enables simple constant |
| 6059 | folding optimizations at all optimization levels. In addition, other |
| 6060 | optimization passes in \s-1GCC\s0 use this flag to control global dataflow |
| 6061 | analyses that eliminate useless checks for null pointers; these assume |
| 6062 | that if a pointer is checked after it has already been dereferenced, |
| 6063 | it cannot be null. |
| 6064 | .Sp |
| 6065 | Note however that in some environments this assumption is not true. |
| 6066 | Use \fB\-fno\-delete\-null\-pointer\-checks\fR to disable this optimization |
| 6067 | for programs that depend on that behavior. |
| 6068 | .Sp |
| 6069 | Some targets, especially embedded ones, disable this option at all levels. |
| 6070 | Otherwise it is enabled at all levels: \fB\-O0\fR, \fB\-O1\fR, |
| 6071 | \&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. Passes that use the information |
| 6072 | are enabled independently at different optimization levels. |
| 6073 | .IP "\fB\-fdevirtualize\fR" 4 |
| 6074 | .IX Item "-fdevirtualize" |
| 6075 | Attempt to convert calls to virtual functions to direct calls. This |
| 6076 | is done both within a procedure and interprocedurally as part of |
| 6077 | indirect inlining (\f(CW\*(C`\-findirect\-inlining\*(C'\fR) and interprocedural constant |
| 6078 | propagation (\fB\-fipa\-cp\fR). |
| 6079 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6080 | .IP "\fB\-fexpensive\-optimizations\fR" 4 |
| 6081 | .IX Item "-fexpensive-optimizations" |
| 6082 | Perform a number of minor optimizations that are relatively expensive. |
| 6083 | .Sp |
| 6084 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6085 | .IP "\fB\-free\fR" 4 |
| 6086 | .IX Item "-free" |
| 6087 | Attempt to remove redundant extension instructions. This is especially |
| 6088 | helpful for the x86\-64 architecture which implicitly zero-extends in 64\-bit |
| 6089 | registers after writing to their lower 32\-bit half. |
| 6090 | .Sp |
| 6091 | Enabled for x86 at levels \fB\-O2\fR, \fB\-O3\fR. |
| 6092 | .IP "\fB\-foptimize\-register\-move\fR" 4 |
| 6093 | .IX Item "-foptimize-register-move" |
| 6094 | .PD 0 |
| 6095 | .IP "\fB\-fregmove\fR" 4 |
| 6096 | .IX Item "-fregmove" |
| 6097 | .PD |
| 6098 | Attempt to reassign register numbers in move instructions and as |
| 6099 | operands of other simple instructions in order to maximize the amount of |
| 6100 | register tying. This is especially helpful on machines with two-operand |
| 6101 | instructions. |
| 6102 | .Sp |
| 6103 | Note \fB\-fregmove\fR and \fB\-foptimize\-register\-move\fR are the same |
| 6104 | optimization. |
| 6105 | .Sp |
| 6106 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6107 | .IP "\fB\-fira\-algorithm=\fR\fIalgorithm\fR" 4 |
| 6108 | .IX Item "-fira-algorithm=algorithm" |
| 6109 | Use the specified coloring algorithm for the integrated register |
| 6110 | allocator. The \fIalgorithm\fR argument can be \fBpriority\fR, which |
| 6111 | specifies Chow's priority coloring, or \fB\s-1CB\s0\fR, which specifies |
| 6112 | Chaitin-Briggs coloring. Chaitin-Briggs coloring is not implemented |
| 6113 | for all architectures, but for those targets that do support it, it is |
| 6114 | the default because it generates better code. |
| 6115 | .IP "\fB\-fira\-region=\fR\fIregion\fR" 4 |
| 6116 | .IX Item "-fira-region=region" |
| 6117 | Use specified regions for the integrated register allocator. The |
| 6118 | \&\fIregion\fR argument should be one of the following: |
| 6119 | .RS 4 |
| 6120 | .IP "\fBall\fR" 4 |
| 6121 | .IX Item "all" |
| 6122 | Use all loops as register allocation regions. |
| 6123 | This can give the best results for machines with a small and/or |
| 6124 | irregular register set. |
| 6125 | .IP "\fBmixed\fR" 4 |
| 6126 | .IX Item "mixed" |
| 6127 | Use all loops except for loops with small register pressure |
| 6128 | as the regions. This value usually gives |
| 6129 | the best results in most cases and for most architectures, |
| 6130 | and is enabled by default when compiling with optimization for speed |
| 6131 | (\fB\-O\fR, \fB\-O2\fR, ...). |
| 6132 | .IP "\fBone\fR" 4 |
| 6133 | .IX Item "one" |
| 6134 | Use all functions as a single region. |
| 6135 | This typically results in the smallest code size, and is enabled by default for |
| 6136 | \&\fB\-Os\fR or \fB\-O0\fR. |
| 6137 | .RE |
| 6138 | .RS 4 |
| 6139 | .RE |
| 6140 | .IP "\fB\-fira\-loop\-pressure\fR" 4 |
| 6141 | .IX Item "-fira-loop-pressure" |
| 6142 | Use \s-1IRA\s0 to evaluate register pressure in loops for decisions to move |
| 6143 | loop invariants. This option usually results in generation |
| 6144 | of faster and smaller code on machines with large register files (>= 32 |
| 6145 | registers), but it can slow the compiler down. |
| 6146 | .Sp |
| 6147 | This option is enabled at level \fB\-O3\fR for some targets. |
| 6148 | .IP "\fB\-fno\-ira\-share\-save\-slots\fR" 4 |
| 6149 | .IX Item "-fno-ira-share-save-slots" |
| 6150 | Disable sharing of stack slots used for saving call-used hard |
| 6151 | registers living through a call. Each hard register gets a |
| 6152 | separate stack slot, and as a result function stack frames are |
| 6153 | larger. |
| 6154 | .IP "\fB\-fno\-ira\-share\-spill\-slots\fR" 4 |
| 6155 | .IX Item "-fno-ira-share-spill-slots" |
| 6156 | Disable sharing of stack slots allocated for pseudo-registers. Each |
| 6157 | pseudo-register that does not get a hard register gets a separate |
| 6158 | stack slot, and as a result function stack frames are larger. |
| 6159 | .IP "\fB\-fira\-verbose=\fR\fIn\fR" 4 |
| 6160 | .IX Item "-fira-verbose=n" |
| 6161 | Control the verbosity of the dump file for the integrated register allocator. |
| 6162 | The default value is 5. If the value \fIn\fR is greater or equal to 10, |
| 6163 | the dump output is sent to stderr using the same format as \fIn\fR minus 10. |
| 6164 | .IP "\fB\-fdelayed\-branch\fR" 4 |
| 6165 | .IX Item "-fdelayed-branch" |
| 6166 | If supported for the target machine, attempt to reorder instructions |
| 6167 | to exploit instruction slots available after delayed branch |
| 6168 | instructions. |
| 6169 | .Sp |
| 6170 | Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6171 | .IP "\fB\-fschedule\-insns\fR" 4 |
| 6172 | .IX Item "-fschedule-insns" |
| 6173 | If supported for the target machine, attempt to reorder instructions to |
| 6174 | eliminate execution stalls due to required data being unavailable. This |
| 6175 | helps machines that have slow floating point or memory load instructions |
| 6176 | by allowing other instructions to be issued until the result of the load |
| 6177 | or floating-point instruction is required. |
| 6178 | .Sp |
| 6179 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR. |
| 6180 | .IP "\fB\-fschedule\-insns2\fR" 4 |
| 6181 | .IX Item "-fschedule-insns2" |
| 6182 | Similar to \fB\-fschedule\-insns\fR, but requests an additional pass of |
| 6183 | instruction scheduling after register allocation has been done. This is |
| 6184 | especially useful on machines with a relatively small number of |
| 6185 | registers and where memory load instructions take more than one cycle. |
| 6186 | .Sp |
| 6187 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6188 | .IP "\fB\-fno\-sched\-interblock\fR" 4 |
| 6189 | .IX Item "-fno-sched-interblock" |
| 6190 | Don't schedule instructions across basic blocks. This is normally |
| 6191 | enabled by default when scheduling before register allocation, i.e. |
| 6192 | with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. |
| 6193 | .IP "\fB\-fno\-sched\-spec\fR" 4 |
| 6194 | .IX Item "-fno-sched-spec" |
| 6195 | Don't allow speculative motion of non-load instructions. This is normally |
| 6196 | enabled by default when scheduling before register allocation, i.e. |
| 6197 | with \fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. |
| 6198 | .IP "\fB\-fsched\-pressure\fR" 4 |
| 6199 | .IX Item "-fsched-pressure" |
| 6200 | Enable register pressure sensitive insn scheduling before the register |
| 6201 | allocation. This only makes sense when scheduling before register |
| 6202 | allocation is enabled, i.e. with \fB\-fschedule\-insns\fR or at |
| 6203 | \&\fB\-O2\fR or higher. Usage of this option can improve the |
| 6204 | generated code and decrease its size by preventing register pressure |
| 6205 | increase above the number of available hard registers and as a |
| 6206 | consequence register spills in the register allocation. |
| 6207 | .IP "\fB\-fsched\-spec\-load\fR" 4 |
| 6208 | .IX Item "-fsched-spec-load" |
| 6209 | Allow speculative motion of some load instructions. This only makes |
| 6210 | sense when scheduling before register allocation, i.e. with |
| 6211 | \&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. |
| 6212 | .IP "\fB\-fsched\-spec\-load\-dangerous\fR" 4 |
| 6213 | .IX Item "-fsched-spec-load-dangerous" |
| 6214 | Allow speculative motion of more load instructions. This only makes |
| 6215 | sense when scheduling before register allocation, i.e. with |
| 6216 | \&\fB\-fschedule\-insns\fR or at \fB\-O2\fR or higher. |
| 6217 | .IP "\fB\-fsched\-stalled\-insns\fR" 4 |
| 6218 | .IX Item "-fsched-stalled-insns" |
| 6219 | .PD 0 |
| 6220 | .IP "\fB\-fsched\-stalled\-insns=\fR\fIn\fR" 4 |
| 6221 | .IX Item "-fsched-stalled-insns=n" |
| 6222 | .PD |
| 6223 | Define how many insns (if any) can be moved prematurely from the queue |
| 6224 | of stalled insns into the ready list, during the second scheduling pass. |
| 6225 | \&\fB\-fno\-sched\-stalled\-insns\fR means that no insns will be moved |
| 6226 | prematurely, \fB\-fsched\-stalled\-insns=0\fR means there is no limit |
| 6227 | on how many queued insns can be moved prematurely. |
| 6228 | \&\fB\-fsched\-stalled\-insns\fR without a value is equivalent to |
| 6229 | \&\fB\-fsched\-stalled\-insns=1\fR. |
| 6230 | .IP "\fB\-fsched\-stalled\-insns\-dep\fR" 4 |
| 6231 | .IX Item "-fsched-stalled-insns-dep" |
| 6232 | .PD 0 |
| 6233 | .IP "\fB\-fsched\-stalled\-insns\-dep=\fR\fIn\fR" 4 |
| 6234 | .IX Item "-fsched-stalled-insns-dep=n" |
| 6235 | .PD |
| 6236 | Define how many insn groups (cycles) will be examined for a dependency |
| 6237 | on a stalled insn that is candidate for premature removal from the queue |
| 6238 | of stalled insns. This has an effect only during the second scheduling pass, |
| 6239 | and only if \fB\-fsched\-stalled\-insns\fR is used. |
| 6240 | \&\fB\-fno\-sched\-stalled\-insns\-dep\fR is equivalent to |
| 6241 | \&\fB\-fsched\-stalled\-insns\-dep=0\fR. |
| 6242 | \&\fB\-fsched\-stalled\-insns\-dep\fR without a value is equivalent to |
| 6243 | \&\fB\-fsched\-stalled\-insns\-dep=1\fR. |
| 6244 | .IP "\fB\-fsched2\-use\-superblocks\fR" 4 |
| 6245 | .IX Item "-fsched2-use-superblocks" |
| 6246 | When scheduling after register allocation, do use superblock scheduling |
| 6247 | algorithm. Superblock scheduling allows motion across basic block boundaries |
| 6248 | resulting on faster schedules. This option is experimental, as not all machine |
| 6249 | descriptions used by \s-1GCC\s0 model the \s-1CPU\s0 closely enough to avoid unreliable |
| 6250 | results from the algorithm. |
| 6251 | .Sp |
| 6252 | This only makes sense when scheduling after register allocation, i.e. with |
| 6253 | \&\fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. |
| 6254 | .IP "\fB\-fsched\-group\-heuristic\fR" 4 |
| 6255 | .IX Item "-fsched-group-heuristic" |
| 6256 | Enable the group heuristic in the scheduler. This heuristic favors |
| 6257 | the instruction that belongs to a schedule group. This is enabled |
| 6258 | by default when scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR |
| 6259 | or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. |
| 6260 | .IP "\fB\-fsched\-critical\-path\-heuristic\fR" 4 |
| 6261 | .IX Item "-fsched-critical-path-heuristic" |
| 6262 | Enable the critical-path heuristic in the scheduler. This heuristic favors |
| 6263 | instructions on the critical path. This is enabled by default when |
| 6264 | scheduling is enabled, i.e. with \fB\-fschedule\-insns\fR |
| 6265 | or \fB\-fschedule\-insns2\fR or at \fB\-O2\fR or higher. |
| 6266 | .IP "\fB\-fsched\-spec\-insn\-heuristic\fR" 4 |
| 6267 | .IX Item "-fsched-spec-insn-heuristic" |
| 6268 | Enable the speculative instruction heuristic in the scheduler. This |
| 6269 | heuristic favors speculative instructions with greater dependency weakness. |
| 6270 | This is enabled by default when scheduling is enabled, i.e. |
| 6271 | with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR |
| 6272 | or at \fB\-O2\fR or higher. |
| 6273 | .IP "\fB\-fsched\-rank\-heuristic\fR" 4 |
| 6274 | .IX Item "-fsched-rank-heuristic" |
| 6275 | Enable the rank heuristic in the scheduler. This heuristic favors |
| 6276 | the instruction belonging to a basic block with greater size or frequency. |
| 6277 | This is enabled by default when scheduling is enabled, i.e. |
| 6278 | with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or |
| 6279 | at \fB\-O2\fR or higher. |
| 6280 | .IP "\fB\-fsched\-last\-insn\-heuristic\fR" 4 |
| 6281 | .IX Item "-fsched-last-insn-heuristic" |
| 6282 | Enable the last-instruction heuristic in the scheduler. This heuristic |
| 6283 | favors the instruction that is less dependent on the last instruction |
| 6284 | scheduled. This is enabled by default when scheduling is enabled, |
| 6285 | i.e. with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or |
| 6286 | at \fB\-O2\fR or higher. |
| 6287 | .IP "\fB\-fsched\-dep\-count\-heuristic\fR" 4 |
| 6288 | .IX Item "-fsched-dep-count-heuristic" |
| 6289 | Enable the dependent-count heuristic in the scheduler. This heuristic |
| 6290 | favors the instruction that has more instructions depending on it. |
| 6291 | This is enabled by default when scheduling is enabled, i.e. |
| 6292 | with \fB\-fschedule\-insns\fR or \fB\-fschedule\-insns2\fR or |
| 6293 | at \fB\-O2\fR or higher. |
| 6294 | .IP "\fB\-freschedule\-modulo\-scheduled\-loops\fR" 4 |
| 6295 | .IX Item "-freschedule-modulo-scheduled-loops" |
| 6296 | The modulo scheduling comes before the traditional scheduling, if a loop |
| 6297 | was modulo scheduled we may want to prevent the later scheduling passes |
| 6298 | from changing its schedule, we use this option to control that. |
| 6299 | .IP "\fB\-fselective\-scheduling\fR" 4 |
| 6300 | .IX Item "-fselective-scheduling" |
| 6301 | Schedule instructions using selective scheduling algorithm. Selective |
| 6302 | scheduling runs instead of the first scheduler pass. |
| 6303 | .IP "\fB\-fselective\-scheduling2\fR" 4 |
| 6304 | .IX Item "-fselective-scheduling2" |
| 6305 | Schedule instructions using selective scheduling algorithm. Selective |
| 6306 | scheduling runs instead of the second scheduler pass. |
| 6307 | .IP "\fB\-fsel\-sched\-pipelining\fR" 4 |
| 6308 | .IX Item "-fsel-sched-pipelining" |
| 6309 | Enable software pipelining of innermost loops during selective scheduling. |
| 6310 | This option has no effect until one of \fB\-fselective\-scheduling\fR or |
| 6311 | \&\fB\-fselective\-scheduling2\fR is turned on. |
| 6312 | .IP "\fB\-fsel\-sched\-pipelining\-outer\-loops\fR" 4 |
| 6313 | .IX Item "-fsel-sched-pipelining-outer-loops" |
| 6314 | When pipelining loops during selective scheduling, also pipeline outer loops. |
| 6315 | This option has no effect until \fB\-fsel\-sched\-pipelining\fR is turned on. |
| 6316 | .IP "\fB\-fshrink\-wrap\fR" 4 |
| 6317 | .IX Item "-fshrink-wrap" |
| 6318 | Emit function prologues only before parts of the function that need it, |
| 6319 | rather than at the top of the function. This flag is enabled by default at |
| 6320 | \&\fB\-O\fR and higher. |
| 6321 | .IP "\fB\-fcaller\-saves\fR" 4 |
| 6322 | .IX Item "-fcaller-saves" |
| 6323 | Enable values to be allocated in registers that will be clobbered by |
| 6324 | function calls, by emitting extra instructions to save and restore the |
| 6325 | registers around such calls. Such allocation is done only when it |
| 6326 | seems to result in better code than would otherwise be produced. |
| 6327 | .Sp |
| 6328 | This option is always enabled by default on certain machines, usually |
| 6329 | those which have no call-preserved registers to use instead. |
| 6330 | .Sp |
| 6331 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6332 | .IP "\fB\-fcombine\-stack\-adjustments\fR" 4 |
| 6333 | .IX Item "-fcombine-stack-adjustments" |
| 6334 | Tracks stack adjustments (pushes and pops) and stack memory references |
| 6335 | and then tries to find ways to combine them. |
| 6336 | .Sp |
| 6337 | Enabled by default at \fB\-O1\fR and higher. |
| 6338 | .IP "\fB\-fconserve\-stack\fR" 4 |
| 6339 | .IX Item "-fconserve-stack" |
| 6340 | Attempt to minimize stack usage. The compiler will attempt to use less |
| 6341 | stack space, even if that makes the program slower. This option |
| 6342 | implies setting the \fBlarge-stack-frame\fR parameter to 100 |
| 6343 | and the \fBlarge-stack-frame-growth\fR parameter to 400. |
| 6344 | .IP "\fB\-ftree\-reassoc\fR" 4 |
| 6345 | .IX Item "-ftree-reassoc" |
| 6346 | Perform reassociation on trees. This flag is enabled by default |
| 6347 | at \fB\-O\fR and higher. |
| 6348 | .IP "\fB\-ftree\-pre\fR" 4 |
| 6349 | .IX Item "-ftree-pre" |
| 6350 | Perform partial redundancy elimination (\s-1PRE\s0) on trees. This flag is |
| 6351 | enabled by default at \fB\-O2\fR and \fB\-O3\fR. |
| 6352 | .IP "\fB\-ftree\-forwprop\fR" 4 |
| 6353 | .IX Item "-ftree-forwprop" |
| 6354 | Perform forward propagation on trees. This flag is enabled by default |
| 6355 | at \fB\-O\fR and higher. |
| 6356 | .IP "\fB\-ftree\-fre\fR" 4 |
| 6357 | .IX Item "-ftree-fre" |
| 6358 | Perform full redundancy elimination (\s-1FRE\s0) on trees. The difference |
| 6359 | between \s-1FRE\s0 and \s-1PRE\s0 is that \s-1FRE\s0 only considers expressions |
| 6360 | that are computed on all paths leading to the redundant computation. |
| 6361 | This analysis is faster than \s-1PRE\s0, though it exposes fewer redundancies. |
| 6362 | This flag is enabled by default at \fB\-O\fR and higher. |
| 6363 | .IP "\fB\-ftree\-phiprop\fR" 4 |
| 6364 | .IX Item "-ftree-phiprop" |
| 6365 | Perform hoisting of loads from conditional pointers on trees. This |
| 6366 | pass is enabled by default at \fB\-O\fR and higher. |
| 6367 | .IP "\fB\-ftree\-copy\-prop\fR" 4 |
| 6368 | .IX Item "-ftree-copy-prop" |
| 6369 | Perform copy propagation on trees. This pass eliminates unnecessary |
| 6370 | copy operations. This flag is enabled by default at \fB\-O\fR and |
| 6371 | higher. |
| 6372 | .IP "\fB\-fipa\-pure\-const\fR" 4 |
| 6373 | .IX Item "-fipa-pure-const" |
| 6374 | Discover which functions are pure or constant. |
| 6375 | Enabled by default at \fB\-O\fR and higher. |
| 6376 | .IP "\fB\-fipa\-reference\fR" 4 |
| 6377 | .IX Item "-fipa-reference" |
| 6378 | Discover which static variables do not escape cannot escape the |
| 6379 | compilation unit. |
| 6380 | Enabled by default at \fB\-O\fR and higher. |
| 6381 | .IP "\fB\-fipa\-pta\fR" 4 |
| 6382 | .IX Item "-fipa-pta" |
| 6383 | Perform interprocedural pointer analysis and interprocedural modification |
| 6384 | and reference analysis. This option can cause excessive memory and |
| 6385 | compile-time usage on large compilation units. It is not enabled by |
| 6386 | default at any optimization level. |
| 6387 | .IP "\fB\-fipa\-profile\fR" 4 |
| 6388 | .IX Item "-fipa-profile" |
| 6389 | Perform interprocedural profile propagation. The functions called only from |
| 6390 | cold functions are marked as cold. Also functions executed once (such as |
| 6391 | \&\f(CW\*(C`cold\*(C'\fR, \f(CW\*(C`noreturn\*(C'\fR, static constructors or destructors) are identified. Cold |
| 6392 | functions and loop less parts of functions executed once are then optimized for |
| 6393 | size. |
| 6394 | Enabled by default at \fB\-O\fR and higher. |
| 6395 | .IP "\fB\-fipa\-cp\fR" 4 |
| 6396 | .IX Item "-fipa-cp" |
| 6397 | Perform interprocedural constant propagation. |
| 6398 | This optimization analyzes the program to determine when values passed |
| 6399 | to functions are constants and then optimizes accordingly. |
| 6400 | This optimization can substantially increase performance |
| 6401 | if the application has constants passed to functions. |
| 6402 | This flag is enabled by default at \fB\-O2\fR, \fB\-Os\fR and \fB\-O3\fR. |
| 6403 | .IP "\fB\-fipa\-cp\-clone\fR" 4 |
| 6404 | .IX Item "-fipa-cp-clone" |
| 6405 | Perform function cloning to make interprocedural constant propagation stronger. |
| 6406 | When enabled, interprocedural constant propagation will perform function cloning |
| 6407 | when externally visible function can be called with constant arguments. |
| 6408 | Because this optimization can create multiple copies of functions, |
| 6409 | it may significantly increase code size |
| 6410 | (see \fB\-\-param ipcp\-unit\-growth=\fR\fIvalue\fR). |
| 6411 | This flag is enabled by default at \fB\-O3\fR. |
| 6412 | .IP "\fB\-fipa\-matrix\-reorg\fR" 4 |
| 6413 | .IX Item "-fipa-matrix-reorg" |
| 6414 | Perform matrix flattening and transposing. |
| 6415 | Matrix flattening tries to replace an m\-dimensional matrix |
| 6416 | with its equivalent n\-dimensional matrix, where n < m. |
| 6417 | This reduces the level of indirection needed for accessing the elements |
| 6418 | of the matrix. The second optimization is matrix transposing, which |
| 6419 | attempts to change the order of the matrix's dimensions in order to |
| 6420 | improve cache locality. |
| 6421 | Both optimizations need the \fB\-fwhole\-program\fR flag. |
| 6422 | Transposing is enabled only if profiling information is available. |
| 6423 | .IP "\fB\-ftree\-sink\fR" 4 |
| 6424 | .IX Item "-ftree-sink" |
| 6425 | Perform forward store motion on trees. This flag is |
| 6426 | enabled by default at \fB\-O\fR and higher. |
| 6427 | .IP "\fB\-ftree\-bit\-ccp\fR" 4 |
| 6428 | .IX Item "-ftree-bit-ccp" |
| 6429 | Perform sparse conditional bit constant propagation on trees and propagate |
| 6430 | pointer alignment information. |
| 6431 | This pass only operates on local scalar variables and is enabled by default |
| 6432 | at \fB\-O\fR and higher. It requires that \fB\-ftree\-ccp\fR is enabled. |
| 6433 | .IP "\fB\-ftree\-ccp\fR" 4 |
| 6434 | .IX Item "-ftree-ccp" |
| 6435 | Perform sparse conditional constant propagation (\s-1CCP\s0) on trees. This |
| 6436 | pass only operates on local scalar variables and is enabled by default |
| 6437 | at \fB\-O\fR and higher. |
| 6438 | .IP "\fB\-ftree\-switch\-conversion\fR" 4 |
| 6439 | .IX Item "-ftree-switch-conversion" |
| 6440 | Perform conversion of simple initializations in a switch to |
| 6441 | initializations from a scalar array. This flag is enabled by default |
| 6442 | at \fB\-O2\fR and higher. |
| 6443 | .IP "\fB\-ftree\-tail\-merge\fR" 4 |
| 6444 | .IX Item "-ftree-tail-merge" |
| 6445 | Look for identical code sequences. When found, replace one with a jump to the |
| 6446 | other. This optimization is known as tail merging or cross jumping. This flag |
| 6447 | is enabled by default at \fB\-O2\fR and higher. The compilation time |
| 6448 | in this pass can |
| 6449 | be limited using \fBmax-tail-merge-comparisons\fR parameter and |
| 6450 | \&\fBmax-tail-merge-iterations\fR parameter. |
| 6451 | .IP "\fB\-ftree\-dce\fR" 4 |
| 6452 | .IX Item "-ftree-dce" |
| 6453 | Perform dead code elimination (\s-1DCE\s0) on trees. This flag is enabled by |
| 6454 | default at \fB\-O\fR and higher. |
| 6455 | .IP "\fB\-ftree\-builtin\-call\-dce\fR" 4 |
| 6456 | .IX Item "-ftree-builtin-call-dce" |
| 6457 | Perform conditional dead code elimination (\s-1DCE\s0) for calls to builtin functions |
| 6458 | that may set \f(CW\*(C`errno\*(C'\fR but are otherwise side-effect free. This flag is |
| 6459 | enabled by default at \fB\-O2\fR and higher if \fB\-Os\fR is not also |
| 6460 | specified. |
| 6461 | .IP "\fB\-ftree\-dominator\-opts\fR" 4 |
| 6462 | .IX Item "-ftree-dominator-opts" |
| 6463 | Perform a variety of simple scalar cleanups (constant/copy |
| 6464 | propagation, redundancy elimination, range propagation and expression |
| 6465 | simplification) based on a dominator tree traversal. This also |
| 6466 | performs jump threading (to reduce jumps to jumps). This flag is |
| 6467 | enabled by default at \fB\-O\fR and higher. |
| 6468 | .IP "\fB\-ftree\-dse\fR" 4 |
| 6469 | .IX Item "-ftree-dse" |
| 6470 | Perform dead store elimination (\s-1DSE\s0) on trees. A dead store is a store into |
| 6471 | a memory location that is later overwritten by another store without |
| 6472 | any intervening loads. In this case the earlier store can be deleted. This |
| 6473 | flag is enabled by default at \fB\-O\fR and higher. |
| 6474 | .IP "\fB\-ftree\-ch\fR" 4 |
| 6475 | .IX Item "-ftree-ch" |
| 6476 | Perform loop header copying on trees. This is beneficial since it increases |
| 6477 | effectiveness of code motion optimizations. It also saves one jump. This flag |
| 6478 | is enabled by default at \fB\-O\fR and higher. It is not enabled |
| 6479 | for \fB\-Os\fR, since it usually increases code size. |
| 6480 | .IP "\fB\-ftree\-loop\-optimize\fR" 4 |
| 6481 | .IX Item "-ftree-loop-optimize" |
| 6482 | Perform loop optimizations on trees. This flag is enabled by default |
| 6483 | at \fB\-O\fR and higher. |
| 6484 | .IP "\fB\-ftree\-loop\-linear\fR" 4 |
| 6485 | .IX Item "-ftree-loop-linear" |
| 6486 | Perform loop interchange transformations on tree. Same as |
| 6487 | \&\fB\-floop\-interchange\fR. To use this code transformation, \s-1GCC\s0 has |
| 6488 | to be configured with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to |
| 6489 | enable the Graphite loop transformation infrastructure. |
| 6490 | .IP "\fB\-floop\-interchange\fR" 4 |
| 6491 | .IX Item "-floop-interchange" |
| 6492 | Perform loop interchange transformations on loops. Interchanging two |
| 6493 | nested loops switches the inner and outer loops. For example, given a |
| 6494 | loop like: |
| 6495 | .Sp |
| 6496 | .Vb 5 |
| 6497 | \& DO J = 1, M |
| 6498 | \& DO I = 1, N |
| 6499 | \& A(J, I) = A(J, I) * C |
| 6500 | \& ENDDO |
| 6501 | \& ENDDO |
| 6502 | .Ve |
| 6503 | .Sp |
| 6504 | loop interchange will transform the loop as if the user had written: |
| 6505 | .Sp |
| 6506 | .Vb 5 |
| 6507 | \& DO I = 1, N |
| 6508 | \& DO J = 1, M |
| 6509 | \& A(J, I) = A(J, I) * C |
| 6510 | \& ENDDO |
| 6511 | \& ENDDO |
| 6512 | .Ve |
| 6513 | .Sp |
| 6514 | which can be beneficial when \f(CW\*(C`N\*(C'\fR is larger than the caches, |
| 6515 | because in Fortran, the elements of an array are stored in memory |
| 6516 | contiguously by column, and the original loop iterates over rows, |
| 6517 | potentially creating at each access a cache miss. This optimization |
| 6518 | applies to all the languages supported by \s-1GCC\s0 and is not limited to |
| 6519 | Fortran. To use this code transformation, \s-1GCC\s0 has to be configured |
| 6520 | with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to enable the |
| 6521 | Graphite loop transformation infrastructure. |
| 6522 | .IP "\fB\-floop\-strip\-mine\fR" 4 |
| 6523 | .IX Item "-floop-strip-mine" |
| 6524 | Perform loop strip mining transformations on loops. Strip mining |
| 6525 | splits a loop into two nested loops. The outer loop has strides |
| 6526 | equal to the strip size and the inner loop has strides of the |
| 6527 | original loop within a strip. The strip length can be changed |
| 6528 | using the \fBloop-block-tile-size\fR parameter. For example, |
| 6529 | given a loop like: |
| 6530 | .Sp |
| 6531 | .Vb 3 |
| 6532 | \& DO I = 1, N |
| 6533 | \& A(I) = A(I) + C |
| 6534 | \& ENDDO |
| 6535 | .Ve |
| 6536 | .Sp |
| 6537 | loop strip mining will transform the loop as if the user had written: |
| 6538 | .Sp |
| 6539 | .Vb 5 |
| 6540 | \& DO II = 1, N, 51 |
| 6541 | \& DO I = II, min (II + 50, N) |
| 6542 | \& A(I) = A(I) + C |
| 6543 | \& ENDDO |
| 6544 | \& ENDDO |
| 6545 | .Ve |
| 6546 | .Sp |
| 6547 | This optimization applies to all the languages supported by \s-1GCC\s0 and is |
| 6548 | not limited to Fortran. To use this code transformation, \s-1GCC\s0 has to |
| 6549 | be configured with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to |
| 6550 | enable the Graphite loop transformation infrastructure. |
| 6551 | .IP "\fB\-floop\-block\fR" 4 |
| 6552 | .IX Item "-floop-block" |
| 6553 | Perform loop blocking transformations on loops. Blocking strip mines |
| 6554 | each loop in the loop nest such that the memory accesses of the |
| 6555 | element loops fit inside caches. The strip length can be changed |
| 6556 | using the \fBloop-block-tile-size\fR parameter. For example, given |
| 6557 | a loop like: |
| 6558 | .Sp |
| 6559 | .Vb 5 |
| 6560 | \& DO I = 1, N |
| 6561 | \& DO J = 1, M |
| 6562 | \& A(J, I) = B(I) + C(J) |
| 6563 | \& ENDDO |
| 6564 | \& ENDDO |
| 6565 | .Ve |
| 6566 | .Sp |
| 6567 | loop blocking will transform the loop as if the user had written: |
| 6568 | .Sp |
| 6569 | .Vb 9 |
| 6570 | \& DO II = 1, N, 51 |
| 6571 | \& DO JJ = 1, M, 51 |
| 6572 | \& DO I = II, min (II + 50, N) |
| 6573 | \& DO J = JJ, min (JJ + 50, M) |
| 6574 | \& A(J, I) = B(I) + C(J) |
| 6575 | \& ENDDO |
| 6576 | \& ENDDO |
| 6577 | \& ENDDO |
| 6578 | \& ENDDO |
| 6579 | .Ve |
| 6580 | .Sp |
| 6581 | which can be beneficial when \f(CW\*(C`M\*(C'\fR is larger than the caches, |
| 6582 | because the innermost loop will iterate over a smaller amount of data |
| 6583 | which can be kept in the caches. This optimization applies to all the |
| 6584 | languages supported by \s-1GCC\s0 and is not limited to Fortran. To use this |
| 6585 | code transformation, \s-1GCC\s0 has to be configured with \fB\-\-with\-ppl\fR |
| 6586 | and \fB\-\-with\-cloog\fR to enable the Graphite loop transformation |
| 6587 | infrastructure. |
| 6588 | .IP "\fB\-fgraphite\-identity\fR" 4 |
| 6589 | .IX Item "-fgraphite-identity" |
| 6590 | Enable the identity transformation for graphite. For every SCoP we generate |
| 6591 | the polyhedral representation and transform it back to gimple. Using |
| 6592 | \&\fB\-fgraphite\-identity\fR we can check the costs or benefits of the |
| 6593 | \&\s-1GIMPLE\s0 \-> \s-1GRAPHITE\s0 \-> \s-1GIMPLE\s0 transformation. Some minimal optimizations |
| 6594 | are also performed by the code generator CLooG, like index splitting and |
| 6595 | dead code elimination in loops. |
| 6596 | .IP "\fB\-floop\-flatten\fR" 4 |
| 6597 | .IX Item "-floop-flatten" |
| 6598 | Removes the loop nesting structure: transforms the loop nest into a |
| 6599 | single loop. This transformation can be useful as an enablement |
| 6600 | transform for vectorization and parallelization. This feature |
| 6601 | is experimental. |
| 6602 | To use this code transformation, \s-1GCC\s0 has to be configured |
| 6603 | with \fB\-\-with\-ppl\fR and \fB\-\-with\-cloog\fR to enable the |
| 6604 | Graphite loop transformation infrastructure. |
| 6605 | .IP "\fB\-floop\-parallelize\-all\fR" 4 |
| 6606 | .IX Item "-floop-parallelize-all" |
| 6607 | Use the Graphite data dependence analysis to identify loops that can |
| 6608 | be parallelized. Parallelize all the loops that can be analyzed to |
| 6609 | not contain loop carried dependences without checking that it is |
| 6610 | profitable to parallelize the loops. |
| 6611 | .IP "\fB\-fcheck\-data\-deps\fR" 4 |
| 6612 | .IX Item "-fcheck-data-deps" |
| 6613 | Compare the results of several data dependence analyzers. This option |
| 6614 | is used for debugging the data dependence analyzers. |
| 6615 | .IP "\fB\-ftree\-loop\-if\-convert\fR" 4 |
| 6616 | .IX Item "-ftree-loop-if-convert" |
| 6617 | Attempt to transform conditional jumps in the innermost loops to |
| 6618 | branch-less equivalents. The intent is to remove control-flow from |
| 6619 | the innermost loops in order to improve the ability of the |
| 6620 | vectorization pass to handle these loops. This is enabled by default |
| 6621 | if vectorization is enabled. |
| 6622 | .IP "\fB\-ftree\-loop\-if\-convert\-stores\fR" 4 |
| 6623 | .IX Item "-ftree-loop-if-convert-stores" |
| 6624 | Attempt to also if-convert conditional jumps containing memory writes. |
| 6625 | This transformation can be unsafe for multi-threaded programs as it |
| 6626 | transforms conditional memory writes into unconditional memory writes. |
| 6627 | For example, |
| 6628 | .Sp |
| 6629 | .Vb 3 |
| 6630 | \& for (i = 0; i < N; i++) |
| 6631 | \& if (cond) |
| 6632 | \& A[i] = expr; |
| 6633 | .Ve |
| 6634 | .Sp |
| 6635 | would be transformed to |
| 6636 | .Sp |
| 6637 | .Vb 2 |
| 6638 | \& for (i = 0; i < N; i++) |
| 6639 | \& A[i] = cond ? expr : A[i]; |
| 6640 | .Ve |
| 6641 | .Sp |
| 6642 | potentially producing data races. |
| 6643 | .IP "\fB\-ftree\-loop\-distribution\fR" 4 |
| 6644 | .IX Item "-ftree-loop-distribution" |
| 6645 | Perform loop distribution. This flag can improve cache performance on |
| 6646 | big loop bodies and allow further loop optimizations, like |
| 6647 | parallelization or vectorization, to take place. For example, the loop |
| 6648 | .Sp |
| 6649 | .Vb 4 |
| 6650 | \& DO I = 1, N |
| 6651 | \& A(I) = B(I) + C |
| 6652 | \& D(I) = E(I) * F |
| 6653 | \& ENDDO |
| 6654 | .Ve |
| 6655 | .Sp |
| 6656 | is transformed to |
| 6657 | .Sp |
| 6658 | .Vb 6 |
| 6659 | \& DO I = 1, N |
| 6660 | \& A(I) = B(I) + C |
| 6661 | \& ENDDO |
| 6662 | \& DO I = 1, N |
| 6663 | \& D(I) = E(I) * F |
| 6664 | \& ENDDO |
| 6665 | .Ve |
| 6666 | .IP "\fB\-ftree\-loop\-distribute\-patterns\fR" 4 |
| 6667 | .IX Item "-ftree-loop-distribute-patterns" |
| 6668 | Perform loop distribution of patterns that can be code generated with |
| 6669 | calls to a library. This flag is enabled by default at \fB\-O3\fR. |
| 6670 | .Sp |
| 6671 | This pass distributes the initialization loops and generates a call to |
| 6672 | memset zero. For example, the loop |
| 6673 | .Sp |
| 6674 | .Vb 4 |
| 6675 | \& DO I = 1, N |
| 6676 | \& A(I) = 0 |
| 6677 | \& B(I) = A(I) + I |
| 6678 | \& ENDDO |
| 6679 | .Ve |
| 6680 | .Sp |
| 6681 | is transformed to |
| 6682 | .Sp |
| 6683 | .Vb 6 |
| 6684 | \& DO I = 1, N |
| 6685 | \& A(I) = 0 |
| 6686 | \& ENDDO |
| 6687 | \& DO I = 1, N |
| 6688 | \& B(I) = A(I) + I |
| 6689 | \& ENDDO |
| 6690 | .Ve |
| 6691 | .Sp |
| 6692 | and the initialization loop is transformed into a call to memset zero. |
| 6693 | .IP "\fB\-ftree\-loop\-im\fR" 4 |
| 6694 | .IX Item "-ftree-loop-im" |
| 6695 | Perform loop invariant motion on trees. This pass moves only invariants that |
| 6696 | would be hard to handle at \s-1RTL\s0 level (function calls, operations that expand to |
| 6697 | nontrivial sequences of insns). With \fB\-funswitch\-loops\fR it also moves |
| 6698 | operands of conditions that are invariant out of the loop, so that we can use |
| 6699 | just trivial invariantness analysis in loop unswitching. The pass also includes |
| 6700 | store motion. |
| 6701 | .IP "\fB\-ftree\-loop\-ivcanon\fR" 4 |
| 6702 | .IX Item "-ftree-loop-ivcanon" |
| 6703 | Create a canonical counter for number of iterations in loops for which |
| 6704 | determining number of iterations requires complicated analysis. Later |
| 6705 | optimizations then may determine the number easily. Useful especially |
| 6706 | in connection with unrolling. |
| 6707 | .IP "\fB\-fivopts\fR" 4 |
| 6708 | .IX Item "-fivopts" |
| 6709 | Perform induction variable optimizations (strength reduction, induction |
| 6710 | variable merging and induction variable elimination) on trees. |
| 6711 | .IP "\fB\-ftree\-parallelize\-loops=n\fR" 4 |
| 6712 | .IX Item "-ftree-parallelize-loops=n" |
| 6713 | Parallelize loops, i.e., split their iteration space to run in n threads. |
| 6714 | This is only possible for loops whose iterations are independent |
| 6715 | and can be arbitrarily reordered. The optimization is only |
| 6716 | profitable on multiprocessor machines, for loops that are CPU-intensive, |
| 6717 | rather than constrained e.g. by memory bandwidth. This option |
| 6718 | implies \fB\-pthread\fR, and thus is only supported on targets |
| 6719 | that have support for \fB\-pthread\fR. |
| 6720 | .IP "\fB\-ftree\-pta\fR" 4 |
| 6721 | .IX Item "-ftree-pta" |
| 6722 | Perform function-local points-to analysis on trees. This flag is |
| 6723 | enabled by default at \fB\-O\fR and higher. |
| 6724 | .IP "\fB\-ftree\-sra\fR" 4 |
| 6725 | .IX Item "-ftree-sra" |
| 6726 | Perform scalar replacement of aggregates. This pass replaces structure |
| 6727 | references with scalars to prevent committing structures to memory too |
| 6728 | early. This flag is enabled by default at \fB\-O\fR and higher. |
| 6729 | .IP "\fB\-ftree\-copyrename\fR" 4 |
| 6730 | .IX Item "-ftree-copyrename" |
| 6731 | Perform copy renaming on trees. This pass attempts to rename compiler |
| 6732 | temporaries to other variables at copy locations, usually resulting in |
| 6733 | variable names which more closely resemble the original variables. This flag |
| 6734 | is enabled by default at \fB\-O\fR and higher. |
| 6735 | .IP "\fB\-ftree\-ter\fR" 4 |
| 6736 | .IX Item "-ftree-ter" |
| 6737 | Perform temporary expression replacement during the \s-1SSA\-\s0>normal phase. Single |
| 6738 | use/single def temporaries are replaced at their use location with their |
| 6739 | defining expression. This results in non-GIMPLE code, but gives the expanders |
| 6740 | much more complex trees to work on resulting in better \s-1RTL\s0 generation. This is |
| 6741 | enabled by default at \fB\-O\fR and higher. |
| 6742 | .IP "\fB\-ftree\-vectorize\fR" 4 |
| 6743 | .IX Item "-ftree-vectorize" |
| 6744 | Perform loop vectorization on trees. This flag is enabled by default at |
| 6745 | \&\fB\-O3\fR. |
| 6746 | .IP "\fB\-ftree\-slp\-vectorize\fR" 4 |
| 6747 | .IX Item "-ftree-slp-vectorize" |
| 6748 | Perform basic block vectorization on trees. This flag is enabled by default at |
| 6749 | \&\fB\-O3\fR and when \fB\-ftree\-vectorize\fR is enabled. |
| 6750 | .IP "\fB\-ftree\-vect\-loop\-version\fR" 4 |
| 6751 | .IX Item "-ftree-vect-loop-version" |
| 6752 | Perform loop versioning when doing loop vectorization on trees. When a loop |
| 6753 | appears to be vectorizable except that data alignment or data dependence cannot |
| 6754 | be determined at compile time, then vectorized and non-vectorized versions of |
| 6755 | the loop are generated along with run-time checks for alignment or dependence |
| 6756 | to control which version is executed. This option is enabled by default |
| 6757 | except at level \fB\-Os\fR where it is disabled. |
| 6758 | .IP "\fB\-fvect\-cost\-model\fR" 4 |
| 6759 | .IX Item "-fvect-cost-model" |
| 6760 | Enable cost model for vectorization. |
| 6761 | .IP "\fB\-ftree\-vrp\fR" 4 |
| 6762 | .IX Item "-ftree-vrp" |
| 6763 | Perform Value Range Propagation on trees. This is similar to the |
| 6764 | constant propagation pass, but instead of values, ranges of values are |
| 6765 | propagated. This allows the optimizers to remove unnecessary range |
| 6766 | checks like array bound checks and null pointer checks. This is |
| 6767 | enabled by default at \fB\-O2\fR and higher. Null pointer check |
| 6768 | elimination is only done if \fB\-fdelete\-null\-pointer\-checks\fR is |
| 6769 | enabled. |
| 6770 | .IP "\fB\-ftracer\fR" 4 |
| 6771 | .IX Item "-ftracer" |
| 6772 | Perform tail duplication to enlarge superblock size. This transformation |
| 6773 | simplifies the control flow of the function allowing other optimizations to do |
| 6774 | better job. |
| 6775 | .IP "\fB\-funroll\-loops\fR" 4 |
| 6776 | .IX Item "-funroll-loops" |
| 6777 | Unroll loops whose number of iterations can be determined at compile |
| 6778 | time or upon entry to the loop. \fB\-funroll\-loops\fR implies |
| 6779 | \&\fB\-frerun\-cse\-after\-loop\fR. This option makes code larger, |
| 6780 | and may or may not make it run faster. |
| 6781 | .IP "\fB\-funroll\-all\-loops\fR" 4 |
| 6782 | .IX Item "-funroll-all-loops" |
| 6783 | Unroll all loops, even if their number of iterations is uncertain when |
| 6784 | the loop is entered. This usually makes programs run more slowly. |
| 6785 | \&\fB\-funroll\-all\-loops\fR implies the same options as |
| 6786 | \&\fB\-funroll\-loops\fR, |
| 6787 | .IP "\fB\-fsplit\-ivs\-in\-unroller\fR" 4 |
| 6788 | .IX Item "-fsplit-ivs-in-unroller" |
| 6789 | Enables expressing of values of induction variables in later iterations |
| 6790 | of the unrolled loop using the value in the first iteration. This breaks |
| 6791 | long dependency chains, thus improving efficiency of the scheduling passes. |
| 6792 | .Sp |
| 6793 | Combination of \fB\-fweb\fR and \s-1CSE\s0 is often sufficient to obtain the |
| 6794 | same effect. However in cases the loop body is more complicated than |
| 6795 | a single basic block, this is not reliable. It also does not work at all |
| 6796 | on some of the architectures due to restrictions in the \s-1CSE\s0 pass. |
| 6797 | .Sp |
| 6798 | This optimization is enabled by default. |
| 6799 | .IP "\fB\-fvariable\-expansion\-in\-unroller\fR" 4 |
| 6800 | .IX Item "-fvariable-expansion-in-unroller" |
| 6801 | With this option, the compiler will create multiple copies of some |
| 6802 | local variables when unrolling a loop which can result in superior code. |
| 6803 | .IP "\fB\-fpartial\-inlining\fR" 4 |
| 6804 | .IX Item "-fpartial-inlining" |
| 6805 | Inline parts of functions. This option has any effect only |
| 6806 | when inlining itself is turned on by the \fB\-finline\-functions\fR |
| 6807 | or \fB\-finline\-small\-functions\fR options. |
| 6808 | .Sp |
| 6809 | Enabled at level \fB\-O2\fR. |
| 6810 | .IP "\fB\-fpredictive\-commoning\fR" 4 |
| 6811 | .IX Item "-fpredictive-commoning" |
| 6812 | Perform predictive commoning optimization, i.e., reusing computations |
| 6813 | (especially memory loads and stores) performed in previous |
| 6814 | iterations of loops. |
| 6815 | .Sp |
| 6816 | This option is enabled at level \fB\-O3\fR. |
| 6817 | .IP "\fB\-fprefetch\-loop\-arrays\fR" 4 |
| 6818 | .IX Item "-fprefetch-loop-arrays" |
| 6819 | If supported by the target machine, generate instructions to prefetch |
| 6820 | memory to improve the performance of loops that access large arrays. |
| 6821 | .Sp |
| 6822 | This option may generate better or worse code; results are highly |
| 6823 | dependent on the structure of loops within the source code. |
| 6824 | .Sp |
| 6825 | Disabled at level \fB\-Os\fR. |
| 6826 | .IP "\fB\-fno\-peephole\fR" 4 |
| 6827 | .IX Item "-fno-peephole" |
| 6828 | .PD 0 |
| 6829 | .IP "\fB\-fno\-peephole2\fR" 4 |
| 6830 | .IX Item "-fno-peephole2" |
| 6831 | .PD |
| 6832 | Disable any machine-specific peephole optimizations. The difference |
| 6833 | between \fB\-fno\-peephole\fR and \fB\-fno\-peephole2\fR is in how they |
| 6834 | are implemented in the compiler; some targets use one, some use the |
| 6835 | other, a few use both. |
| 6836 | .Sp |
| 6837 | \&\fB\-fpeephole\fR is enabled by default. |
| 6838 | \&\fB\-fpeephole2\fR enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6839 | .IP "\fB\-fno\-guess\-branch\-probability\fR" 4 |
| 6840 | .IX Item "-fno-guess-branch-probability" |
| 6841 | Do not guess branch probabilities using heuristics. |
| 6842 | .Sp |
| 6843 | \&\s-1GCC\s0 will use heuristics to guess branch probabilities if they are |
| 6844 | not provided by profiling feedback (\fB\-fprofile\-arcs\fR). These |
| 6845 | heuristics are based on the control flow graph. If some branch probabilities |
| 6846 | are specified by \fB_\|_builtin_expect\fR, then the heuristics will be |
| 6847 | used to guess branch probabilities for the rest of the control flow graph, |
| 6848 | taking the \fB_\|_builtin_expect\fR info into account. The interactions |
| 6849 | between the heuristics and \fB_\|_builtin_expect\fR can be complex, and in |
| 6850 | some cases, it may be useful to disable the heuristics so that the effects |
| 6851 | of \fB_\|_builtin_expect\fR are easier to understand. |
| 6852 | .Sp |
| 6853 | The default is \fB\-fguess\-branch\-probability\fR at levels |
| 6854 | \&\fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6855 | .IP "\fB\-freorder\-blocks\fR" 4 |
| 6856 | .IX Item "-freorder-blocks" |
| 6857 | Reorder basic blocks in the compiled function in order to reduce number of |
| 6858 | taken branches and improve code locality. |
| 6859 | .Sp |
| 6860 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR. |
| 6861 | .IP "\fB\-freorder\-blocks\-and\-partition\fR" 4 |
| 6862 | .IX Item "-freorder-blocks-and-partition" |
| 6863 | In addition to reordering basic blocks in the compiled function, in order |
| 6864 | to reduce number of taken branches, partitions hot and cold basic blocks |
| 6865 | into separate sections of the assembly and .o files, to improve |
| 6866 | paging and cache locality performance. |
| 6867 | .Sp |
| 6868 | This optimization is automatically turned off in the presence of |
| 6869 | exception handling, for linkonce sections, for functions with a user-defined |
| 6870 | section attribute and on any architecture that does not support named |
| 6871 | sections. |
| 6872 | .IP "\fB\-freorder\-functions\fR" 4 |
| 6873 | .IX Item "-freorder-functions" |
| 6874 | Reorder functions in the object file in order to |
| 6875 | improve code locality. This is implemented by using special |
| 6876 | subsections \f(CW\*(C`.text.hot\*(C'\fR for most frequently executed functions and |
| 6877 | \&\f(CW\*(C`.text.unlikely\*(C'\fR for unlikely executed functions. Reordering is done by |
| 6878 | the linker so object file format must support named sections and linker must |
| 6879 | place them in a reasonable way. |
| 6880 | .Sp |
| 6881 | Also profile feedback must be available in to make this option effective. See |
| 6882 | \&\fB\-fprofile\-arcs\fR for details. |
| 6883 | .Sp |
| 6884 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6885 | .IP "\fB\-fstrict\-aliasing\fR" 4 |
| 6886 | .IX Item "-fstrict-aliasing" |
| 6887 | Allow the compiler to assume the strictest aliasing rules applicable to |
| 6888 | the language being compiled. For C (and \*(C+), this activates |
| 6889 | optimizations based on the type of expressions. In particular, an |
| 6890 | object of one type is assumed never to reside at the same address as an |
| 6891 | object of a different type, unless the types are almost the same. For |
| 6892 | example, an \f(CW\*(C`unsigned int\*(C'\fR can alias an \f(CW\*(C`int\*(C'\fR, but not a |
| 6893 | \&\f(CW\*(C`void*\*(C'\fR or a \f(CW\*(C`double\*(C'\fR. A character type may alias any other |
| 6894 | type. |
| 6895 | .Sp |
| 6896 | Pay special attention to code like this: |
| 6897 | .Sp |
| 6898 | .Vb 4 |
| 6899 | \& union a_union { |
| 6900 | \& int i; |
| 6901 | \& double d; |
| 6902 | \& }; |
| 6903 | \& |
| 6904 | \& int f() { |
| 6905 | \& union a_union t; |
| 6906 | \& t.d = 3.0; |
| 6907 | \& return t.i; |
| 6908 | \& } |
| 6909 | .Ve |
| 6910 | .Sp |
| 6911 | The practice of reading from a different union member than the one most |
| 6912 | recently written to (called \*(L"type-punning\*(R") is common. Even with |
| 6913 | \&\fB\-fstrict\-aliasing\fR, type-punning is allowed, provided the memory |
| 6914 | is accessed through the union type. So, the code above will work as |
| 6915 | expected. However, this code might not: |
| 6916 | .Sp |
| 6917 | .Vb 7 |
| 6918 | \& int f() { |
| 6919 | \& union a_union t; |
| 6920 | \& int* ip; |
| 6921 | \& t.d = 3.0; |
| 6922 | \& ip = &t.i; |
| 6923 | \& return *ip; |
| 6924 | \& } |
| 6925 | .Ve |
| 6926 | .Sp |
| 6927 | Similarly, access by taking the address, casting the resulting pointer |
| 6928 | and dereferencing the result has undefined behavior, even if the cast |
| 6929 | uses a union type, e.g.: |
| 6930 | .Sp |
| 6931 | .Vb 4 |
| 6932 | \& int f() { |
| 6933 | \& double d = 3.0; |
| 6934 | \& return ((union a_union *) &d)\->i; |
| 6935 | \& } |
| 6936 | .Ve |
| 6937 | .Sp |
| 6938 | The \fB\-fstrict\-aliasing\fR option is enabled at levels |
| 6939 | \&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6940 | .IP "\fB\-fstrict\-overflow\fR" 4 |
| 6941 | .IX Item "-fstrict-overflow" |
| 6942 | Allow the compiler to assume strict signed overflow rules, depending |
| 6943 | on the language being compiled. For C (and \*(C+) this means that |
| 6944 | overflow when doing arithmetic with signed numbers is undefined, which |
| 6945 | means that the compiler may assume that it will not happen. This |
| 6946 | permits various optimizations. For example, the compiler will assume |
| 6947 | that an expression like \f(CW\*(C`i + 10 > i\*(C'\fR will always be true for |
| 6948 | signed \f(CW\*(C`i\*(C'\fR. This assumption is only valid if signed overflow is |
| 6949 | undefined, as the expression is false if \f(CW\*(C`i + 10\*(C'\fR overflows when |
| 6950 | using twos complement arithmetic. When this option is in effect any |
| 6951 | attempt to determine whether an operation on signed numbers will |
| 6952 | overflow must be written carefully to not actually involve overflow. |
| 6953 | .Sp |
| 6954 | This option also allows the compiler to assume strict pointer |
| 6955 | semantics: given a pointer to an object, if adding an offset to that |
| 6956 | pointer does not produce a pointer to the same object, the addition is |
| 6957 | undefined. This permits the compiler to conclude that \f(CW\*(C`p + u > |
| 6958 | p\*(C'\fR is always true for a pointer \f(CW\*(C`p\*(C'\fR and unsigned integer |
| 6959 | \&\f(CW\*(C`u\*(C'\fR. This assumption is only valid because pointer wraparound is |
| 6960 | undefined, as the expression is false if \f(CW\*(C`p + u\*(C'\fR overflows using |
| 6961 | twos complement arithmetic. |
| 6962 | .Sp |
| 6963 | See also the \fB\-fwrapv\fR option. Using \fB\-fwrapv\fR means |
| 6964 | that integer signed overflow is fully defined: it wraps. When |
| 6965 | \&\fB\-fwrapv\fR is used, there is no difference between |
| 6966 | \&\fB\-fstrict\-overflow\fR and \fB\-fno\-strict\-overflow\fR for |
| 6967 | integers. With \fB\-fwrapv\fR certain types of overflow are |
| 6968 | permitted. For example, if the compiler gets an overflow when doing |
| 6969 | arithmetic on constants, the overflowed value can still be used with |
| 6970 | \&\fB\-fwrapv\fR, but not otherwise. |
| 6971 | .Sp |
| 6972 | The \fB\-fstrict\-overflow\fR option is enabled at levels |
| 6973 | \&\fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 6974 | .IP "\fB\-falign\-functions\fR" 4 |
| 6975 | .IX Item "-falign-functions" |
| 6976 | .PD 0 |
| 6977 | .IP "\fB\-falign\-functions=\fR\fIn\fR" 4 |
| 6978 | .IX Item "-falign-functions=n" |
| 6979 | .PD |
| 6980 | Align the start of functions to the next power-of-two greater than |
| 6981 | \&\fIn\fR, skipping up to \fIn\fR bytes. For instance, |
| 6982 | \&\fB\-falign\-functions=32\fR aligns functions to the next 32\-byte |
| 6983 | boundary, but \fB\-falign\-functions=24\fR would align to the next |
| 6984 | 32\-byte boundary only if this can be done by skipping 23 bytes or less. |
| 6985 | .Sp |
| 6986 | \&\fB\-fno\-align\-functions\fR and \fB\-falign\-functions=1\fR are |
| 6987 | equivalent and mean that functions will not be aligned. |
| 6988 | .Sp |
| 6989 | Some assemblers only support this flag when \fIn\fR is a power of two; |
| 6990 | in that case, it is rounded up. |
| 6991 | .Sp |
| 6992 | If \fIn\fR is not specified or is zero, use a machine-dependent default. |
| 6993 | .Sp |
| 6994 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR. |
| 6995 | .IP "\fB\-falign\-labels\fR" 4 |
| 6996 | .IX Item "-falign-labels" |
| 6997 | .PD 0 |
| 6998 | .IP "\fB\-falign\-labels=\fR\fIn\fR" 4 |
| 6999 | .IX Item "-falign-labels=n" |
| 7000 | .PD |
| 7001 | Align all branch targets to a power-of-two boundary, skipping up to |
| 7002 | \&\fIn\fR bytes like \fB\-falign\-functions\fR. This option can easily |
| 7003 | make code slower, because it must insert dummy operations for when the |
| 7004 | branch target is reached in the usual flow of the code. |
| 7005 | .Sp |
| 7006 | \&\fB\-fno\-align\-labels\fR and \fB\-falign\-labels=1\fR are |
| 7007 | equivalent and mean that labels will not be aligned. |
| 7008 | .Sp |
| 7009 | If \fB\-falign\-loops\fR or \fB\-falign\-jumps\fR are applicable and |
| 7010 | are greater than this value, then their values are used instead. |
| 7011 | .Sp |
| 7012 | If \fIn\fR is not specified or is zero, use a machine-dependent default |
| 7013 | which is very likely to be \fB1\fR, meaning no alignment. |
| 7014 | .Sp |
| 7015 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR. |
| 7016 | .IP "\fB\-falign\-loops\fR" 4 |
| 7017 | .IX Item "-falign-loops" |
| 7018 | .PD 0 |
| 7019 | .IP "\fB\-falign\-loops=\fR\fIn\fR" 4 |
| 7020 | .IX Item "-falign-loops=n" |
| 7021 | .PD |
| 7022 | Align loops to a power-of-two boundary, skipping up to \fIn\fR bytes |
| 7023 | like \fB\-falign\-functions\fR. The hope is that the loop will be |
| 7024 | executed many times, which will make up for any execution of the dummy |
| 7025 | operations. |
| 7026 | .Sp |
| 7027 | \&\fB\-fno\-align\-loops\fR and \fB\-falign\-loops=1\fR are |
| 7028 | equivalent and mean that loops will not be aligned. |
| 7029 | .Sp |
| 7030 | If \fIn\fR is not specified or is zero, use a machine-dependent default. |
| 7031 | .Sp |
| 7032 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR. |
| 7033 | .IP "\fB\-falign\-jumps\fR" 4 |
| 7034 | .IX Item "-falign-jumps" |
| 7035 | .PD 0 |
| 7036 | .IP "\fB\-falign\-jumps=\fR\fIn\fR" 4 |
| 7037 | .IX Item "-falign-jumps=n" |
| 7038 | .PD |
| 7039 | Align branch targets to a power-of-two boundary, for branch targets |
| 7040 | where the targets can only be reached by jumping, skipping up to \fIn\fR |
| 7041 | bytes like \fB\-falign\-functions\fR. In this case, no dummy operations |
| 7042 | need be executed. |
| 7043 | .Sp |
| 7044 | \&\fB\-fno\-align\-jumps\fR and \fB\-falign\-jumps=1\fR are |
| 7045 | equivalent and mean that loops will not be aligned. |
| 7046 | .Sp |
| 7047 | If \fIn\fR is not specified or is zero, use a machine-dependent default. |
| 7048 | .Sp |
| 7049 | Enabled at levels \fB\-O2\fR, \fB\-O3\fR. |
| 7050 | .IP "\fB\-funit\-at\-a\-time\fR" 4 |
| 7051 | .IX Item "-funit-at-a-time" |
| 7052 | This option is left for compatibility reasons. \fB\-funit\-at\-a\-time\fR |
| 7053 | has no effect, while \fB\-fno\-unit\-at\-a\-time\fR implies |
| 7054 | \&\fB\-fno\-toplevel\-reorder\fR and \fB\-fno\-section\-anchors\fR. |
| 7055 | .Sp |
| 7056 | Enabled by default. |
| 7057 | .IP "\fB\-fno\-toplevel\-reorder\fR" 4 |
| 7058 | .IX Item "-fno-toplevel-reorder" |
| 7059 | Do not reorder top-level functions, variables, and \f(CW\*(C`asm\*(C'\fR |
| 7060 | statements. Output them in the same order that they appear in the |
| 7061 | input file. When this option is used, unreferenced static variables |
| 7062 | will not be removed. This option is intended to support existing code |
| 7063 | that relies on a particular ordering. For new code, it is better to |
| 7064 | use attributes. |
| 7065 | .Sp |
| 7066 | Enabled at level \fB\-O0\fR. When disabled explicitly, it also implies |
| 7067 | \&\fB\-fno\-section\-anchors\fR, which is otherwise enabled at \fB\-O0\fR on some |
| 7068 | targets. |
| 7069 | .IP "\fB\-fweb\fR" 4 |
| 7070 | .IX Item "-fweb" |
| 7071 | Constructs webs as commonly used for register allocation purposes and assign |
| 7072 | each web individual pseudo register. This allows the register allocation pass |
| 7073 | to operate on pseudos directly, but also strengthens several other optimization |
| 7074 | passes, such as \s-1CSE\s0, loop optimizer and trivial dead code remover. It can, |
| 7075 | however, make debugging impossible, since variables will no longer stay in a |
| 7076 | \&\*(L"home register\*(R". |
| 7077 | .Sp |
| 7078 | Enabled by default with \fB\-funroll\-loops\fR. |
| 7079 | .IP "\fB\-fwhole\-program\fR" 4 |
| 7080 | .IX Item "-fwhole-program" |
| 7081 | Assume that the current compilation unit represents the whole program being |
| 7082 | compiled. All public functions and variables with the exception of \f(CW\*(C`main\*(C'\fR |
| 7083 | and those merged by attribute \f(CW\*(C`externally_visible\*(C'\fR become static functions |
| 7084 | and in effect are optimized more aggressively by interprocedural optimizers. If \fBgold\fR is used as the linker plugin, \f(CW\*(C`externally_visible\*(C'\fR attributes are automatically added to functions (not variable yet due to a current \fBgold\fR issue) that are accessed outside of \s-1LTO\s0 objects according to resolution file produced by \fBgold\fR. For other linkers that cannot generate resolution file, explicit \f(CW\*(C`externally_visible\*(C'\fR attributes are still necessary. |
| 7085 | While this option is equivalent to proper use of the \f(CW\*(C`static\*(C'\fR keyword for |
| 7086 | programs consisting of a single file, in combination with option |
| 7087 | \&\fB\-flto\fR this flag can be used to |
| 7088 | compile many smaller scale programs since the functions and variables become |
| 7089 | local for the whole combined compilation unit, not for the single source file |
| 7090 | itself. |
| 7091 | .Sp |
| 7092 | This option implies \fB\-fwhole\-file\fR for Fortran programs. |
| 7093 | .IP "\fB\-flto[=\fR\fIn\fR\fB]\fR" 4 |
| 7094 | .IX Item "-flto[=n]" |
| 7095 | This option runs the standard link-time optimizer. When invoked |
| 7096 | with source code, it generates \s-1GIMPLE\s0 (one of \s-1GCC\s0's internal |
| 7097 | representations) and writes it to special \s-1ELF\s0 sections in the object |
| 7098 | file. When the object files are linked together, all the function |
| 7099 | bodies are read from these \s-1ELF\s0 sections and instantiated as if they |
| 7100 | had been part of the same translation unit. |
| 7101 | .Sp |
| 7102 | To use the link-time optimizer, \fB\-flto\fR needs to be specified at |
| 7103 | compile time and during the final link. For example: |
| 7104 | .Sp |
| 7105 | .Vb 3 |
| 7106 | \& gcc \-c \-O2 \-flto foo.c |
| 7107 | \& gcc \-c \-O2 \-flto bar.c |
| 7108 | \& gcc \-o myprog \-flto \-O2 foo.o bar.o |
| 7109 | .Ve |
| 7110 | .Sp |
| 7111 | The first two invocations to \s-1GCC\s0 save a bytecode representation |
| 7112 | of \s-1GIMPLE\s0 into special \s-1ELF\s0 sections inside \fIfoo.o\fR and |
| 7113 | \&\fIbar.o\fR. The final invocation reads the \s-1GIMPLE\s0 bytecode from |
| 7114 | \&\fIfoo.o\fR and \fIbar.o\fR, merges the two files into a single |
| 7115 | internal image, and compiles the result as usual. Since both |
| 7116 | \&\fIfoo.o\fR and \fIbar.o\fR are merged into a single image, this |
| 7117 | causes all the interprocedural analyses and optimizations in \s-1GCC\s0 to |
| 7118 | work across the two files as if they were a single one. This means, |
| 7119 | for example, that the inliner is able to inline functions in |
| 7120 | \&\fIbar.o\fR into functions in \fIfoo.o\fR and vice-versa. |
| 7121 | .Sp |
| 7122 | Another (simpler) way to enable link-time optimization is: |
| 7123 | .Sp |
| 7124 | .Vb 1 |
| 7125 | \& gcc \-o myprog \-flto \-O2 foo.c bar.c |
| 7126 | .Ve |
| 7127 | .Sp |
| 7128 | The above generates bytecode for \fIfoo.c\fR and \fIbar.c\fR, |
| 7129 | merges them together into a single \s-1GIMPLE\s0 representation and optimizes |
| 7130 | them as usual to produce \fImyprog\fR. |
| 7131 | .Sp |
| 7132 | The only important thing to keep in mind is that to enable link-time |
| 7133 | optimizations the \fB\-flto\fR flag needs to be passed to both the |
| 7134 | compile and the link commands. |
| 7135 | .Sp |
| 7136 | To make whole program optimization effective, it is necessary to make |
| 7137 | certain whole program assumptions. The compiler needs to know |
| 7138 | what functions and variables can be accessed by libraries and runtime |
| 7139 | outside of the link-time optimized unit. When supported by the linker, |
| 7140 | the linker plugin (see \fB\-fuse\-linker\-plugin\fR) passes information |
| 7141 | to the compiler about used and externally visible symbols. When |
| 7142 | the linker plugin is not available, \fB\-fwhole\-program\fR should be |
| 7143 | used to allow the compiler to make these assumptions, which leads |
| 7144 | to more aggressive optimization decisions. |
| 7145 | .Sp |
| 7146 | Note that when a file is compiled with \fB\-flto\fR, the generated |
| 7147 | object file is larger than a regular object file because it |
| 7148 | contains \s-1GIMPLE\s0 bytecodes and the usual final code. This means that |
| 7149 | object files with \s-1LTO\s0 information can be linked as normal object |
| 7150 | files; if \fB\-flto\fR is not passed to the linker, no |
| 7151 | interprocedural optimizations are applied. |
| 7152 | .Sp |
| 7153 | Additionally, the optimization flags used to compile individual files |
| 7154 | are not necessarily related to those used at link time. For instance, |
| 7155 | .Sp |
| 7156 | .Vb 3 |
| 7157 | \& gcc \-c \-O0 \-flto foo.c |
| 7158 | \& gcc \-c \-O0 \-flto bar.c |
| 7159 | \& gcc \-o myprog \-flto \-O3 foo.o bar.o |
| 7160 | .Ve |
| 7161 | .Sp |
| 7162 | This produces individual object files with unoptimized assembler |
| 7163 | code, but the resulting binary \fImyprog\fR is optimized at |
| 7164 | \&\fB\-O3\fR. If, instead, the final binary is generated without |
| 7165 | \&\fB\-flto\fR, then \fImyprog\fR is not optimized. |
| 7166 | .Sp |
| 7167 | When producing the final binary with \fB\-flto\fR, \s-1GCC\s0 only |
| 7168 | applies link-time optimizations to those files that contain bytecode. |
| 7169 | Therefore, you can mix and match object files and libraries with |
| 7170 | \&\s-1GIMPLE\s0 bytecodes and final object code. \s-1GCC\s0 automatically selects |
| 7171 | which files to optimize in \s-1LTO\s0 mode and which files to link without |
| 7172 | further processing. |
| 7173 | .Sp |
| 7174 | There are some code generation flags preserved by \s-1GCC\s0 when |
| 7175 | generating bytecodes, as they need to be used during the final link |
| 7176 | stage. Currently, the following options are saved into the \s-1GIMPLE\s0 |
| 7177 | bytecode files: \fB\-fPIC\fR, \fB\-fcommon\fR and all the |
| 7178 | \&\fB\-m\fR target flags. |
| 7179 | .Sp |
| 7180 | At link time, these options are read in and reapplied. Note that the |
| 7181 | current implementation makes no attempt to recognize conflicting |
| 7182 | values for these options. If different files have conflicting option |
| 7183 | values (e.g., one file is compiled with \fB\-fPIC\fR and another |
| 7184 | isn't), the compiler simply uses the last value read from the |
| 7185 | bytecode files. It is recommended, then, that you compile all the files |
| 7186 | participating in the same link with the same options. |
| 7187 | .Sp |
| 7188 | If \s-1LTO\s0 encounters objects with C linkage declared with incompatible |
| 7189 | types in separate translation units to be linked together (undefined |
| 7190 | behavior according to \s-1ISO\s0 C99 6.2.7), a non-fatal diagnostic may be |
| 7191 | issued. The behavior is still undefined at run time. |
| 7192 | .Sp |
| 7193 | Another feature of \s-1LTO\s0 is that it is possible to apply interprocedural |
| 7194 | optimizations on files written in different languages. This requires |
| 7195 | support in the language front end. Currently, the C, \*(C+ and |
| 7196 | Fortran front ends are capable of emitting \s-1GIMPLE\s0 bytecodes, so |
| 7197 | something like this should work: |
| 7198 | .Sp |
| 7199 | .Vb 4 |
| 7200 | \& gcc \-c \-flto foo.c |
| 7201 | \& g++ \-c \-flto bar.cc |
| 7202 | \& gfortran \-c \-flto baz.f90 |
| 7203 | \& g++ \-o myprog \-flto \-O3 foo.o bar.o baz.o \-lgfortran |
| 7204 | .Ve |
| 7205 | .Sp |
| 7206 | Notice that the final link is done with \fBg++\fR to get the \*(C+ |
| 7207 | runtime libraries and \fB\-lgfortran\fR is added to get the Fortran |
| 7208 | runtime libraries. In general, when mixing languages in \s-1LTO\s0 mode, you |
| 7209 | should use the same link command options as when mixing languages in a |
| 7210 | regular (non-LTO) compilation; all you need to add is \fB\-flto\fR to |
| 7211 | all the compile and link commands. |
| 7212 | .Sp |
| 7213 | If object files containing \s-1GIMPLE\s0 bytecode are stored in a library archive, say |
| 7214 | \&\fIlibfoo.a\fR, it is possible to extract and use them in an \s-1LTO\s0 link if you |
| 7215 | are using a linker with plugin support. To enable this feature, use |
| 7216 | the flag \fB\-fuse\-linker\-plugin\fR at link time: |
| 7217 | .Sp |
| 7218 | .Vb 1 |
| 7219 | \& gcc \-o myprog \-O2 \-flto \-fuse\-linker\-plugin a.o b.o \-lfoo |
| 7220 | .Ve |
| 7221 | .Sp |
| 7222 | With the linker plugin enabled, the linker extracts the needed |
| 7223 | \&\s-1GIMPLE\s0 files from \fIlibfoo.a\fR and passes them on to the running \s-1GCC\s0 |
| 7224 | to make them part of the aggregated \s-1GIMPLE\s0 image to be optimized. |
| 7225 | .Sp |
| 7226 | If you are not using a linker with plugin support and/or do not |
| 7227 | enable the linker plugin, then the objects inside \fIlibfoo.a\fR |
| 7228 | are extracted and linked as usual, but they do not participate |
| 7229 | in the \s-1LTO\s0 optimization process. |
| 7230 | .Sp |
| 7231 | Link-time optimizations do not require the presence of the whole program to |
| 7232 | operate. If the program does not require any symbols to be exported, it is |
| 7233 | possible to combine \fB\-flto\fR and \fB\-fwhole\-program\fR to allow |
| 7234 | the interprocedural optimizers to use more aggressive assumptions which may |
| 7235 | lead to improved optimization opportunities. |
| 7236 | Use of \fB\-fwhole\-program\fR is not needed when linker plugin is |
| 7237 | active (see \fB\-fuse\-linker\-plugin\fR). |
| 7238 | .Sp |
| 7239 | The current implementation of \s-1LTO\s0 makes no |
| 7240 | attempt to generate bytecode that is portable between different |
| 7241 | types of hosts. The bytecode files are versioned and there is a |
| 7242 | strict version check, so bytecode files generated in one version of |
| 7243 | \&\s-1GCC\s0 will not work with an older/newer version of \s-1GCC\s0. |
| 7244 | .Sp |
| 7245 | Link-time optimization does not work well with generation of debugging |
| 7246 | information. Combining \fB\-flto\fR with |
| 7247 | \&\fB\-g\fR is currently experimental and expected to produce wrong |
| 7248 | results. |
| 7249 | .Sp |
| 7250 | If you specify the optional \fIn\fR, the optimization and code |
| 7251 | generation done at link time is executed in parallel using \fIn\fR |
| 7252 | parallel jobs by utilizing an installed \fBmake\fR program. The |
| 7253 | environment variable \fB\s-1MAKE\s0\fR may be used to override the program |
| 7254 | used. The default value for \fIn\fR is 1. |
| 7255 | .Sp |
| 7256 | You can also specify \fB\-flto=jobserver\fR to use \s-1GNU\s0 make's |
| 7257 | job server mode to determine the number of parallel jobs. This |
| 7258 | is useful when the Makefile calling \s-1GCC\s0 is already executing in parallel. |
| 7259 | You must prepend a \fB+\fR to the command recipe in the parent Makefile |
| 7260 | for this to work. This option likely only works if \fB\s-1MAKE\s0\fR is |
| 7261 | \&\s-1GNU\s0 make. |
| 7262 | .Sp |
| 7263 | This option is disabled by default |
| 7264 | .IP "\fB\-flto\-partition=\fR\fIalg\fR" 4 |
| 7265 | .IX Item "-flto-partition=alg" |
| 7266 | Specify the partitioning algorithm used by the link-time optimizer. |
| 7267 | The value is either \f(CW\*(C`1to1\*(C'\fR to specify a partitioning mirroring |
| 7268 | the original source files or \f(CW\*(C`balanced\*(C'\fR to specify partitioning |
| 7269 | into equally sized chunks (whenever possible). Specifying \f(CW\*(C`none\*(C'\fR |
| 7270 | as an algorithm disables partitioning and streaming completely. The |
| 7271 | default value is \f(CW\*(C`balanced\*(C'\fR. |
| 7272 | .IP "\fB\-flto\-compression\-level=\fR\fIn\fR" 4 |
| 7273 | .IX Item "-flto-compression-level=n" |
| 7274 | This option specifies the level of compression used for intermediate |
| 7275 | language written to \s-1LTO\s0 object files, and is only meaningful in |
| 7276 | conjunction with \s-1LTO\s0 mode (\fB\-flto\fR). Valid |
| 7277 | values are 0 (no compression) to 9 (maximum compression). Values |
| 7278 | outside this range are clamped to either 0 or 9. If the option is not |
| 7279 | given, a default balanced compression setting is used. |
| 7280 | .IP "\fB\-flto\-report\fR" 4 |
| 7281 | .IX Item "-flto-report" |
| 7282 | Prints a report with internal details on the workings of the link-time |
| 7283 | optimizer. The contents of this report vary from version to version. |
| 7284 | It is meant to be useful to \s-1GCC\s0 developers when processing object |
| 7285 | files in \s-1LTO\s0 mode (via \fB\-flto\fR). |
| 7286 | .Sp |
| 7287 | Disabled by default. |
| 7288 | .IP "\fB\-fuse\-linker\-plugin\fR" 4 |
| 7289 | .IX Item "-fuse-linker-plugin" |
| 7290 | Enables the use of a linker plugin during link-time optimization. This |
| 7291 | option relies on plugin support in the linker, which is available in gold |
| 7292 | or in \s-1GNU\s0 ld 2.21 or newer. |
| 7293 | .Sp |
| 7294 | This option enables the extraction of object files with \s-1GIMPLE\s0 bytecode out |
| 7295 | of library archives. This improves the quality of optimization by exposing |
| 7296 | more code to the link-time optimizer. This information specifies what |
| 7297 | symbols can be accessed externally (by non-LTO object or during dynamic |
| 7298 | linking). Resulting code quality improvements on binaries (and shared |
| 7299 | libraries that use hidden visibility) are similar to \f(CW\*(C`\-fwhole\-program\*(C'\fR. |
| 7300 | See \fB\-flto\fR for a description of the effect of this flag and how to |
| 7301 | use it. |
| 7302 | .Sp |
| 7303 | This option is enabled by default when \s-1LTO\s0 support in \s-1GCC\s0 is enabled |
| 7304 | and \s-1GCC\s0 was configured for use with |
| 7305 | a linker supporting plugins (\s-1GNU\s0 ld 2.21 or newer or gold). |
| 7306 | .IP "\fB\-ffat\-lto\-objects\fR" 4 |
| 7307 | .IX Item "-ffat-lto-objects" |
| 7308 | Fat \s-1LTO\s0 objects are object files that contain both the intermediate language |
| 7309 | and the object code. This makes them usable for both \s-1LTO\s0 linking and normal |
| 7310 | linking. This option is effective only when compiling with \fB\-flto\fR |
| 7311 | and is ignored at link time. |
| 7312 | .Sp |
| 7313 | \&\fB\-fno\-fat\-lto\-objects\fR improves compilation time over plain \s-1LTO\s0, but |
| 7314 | requires the complete toolchain to be aware of \s-1LTO\s0. It requires a linker with |
| 7315 | linker plugin support for basic functionality. Additionally, nm, ar and ranlib |
| 7316 | need to support linker plugins to allow a full-featured build environment |
| 7317 | (capable of building static libraries etc). |
| 7318 | .Sp |
| 7319 | The default is \fB\-ffat\-lto\-objects\fR but this default is intended to |
| 7320 | change in future releases when linker plugin enabled environments become more |
| 7321 | common. |
| 7322 | .IP "\fB\-fcompare\-elim\fR" 4 |
| 7323 | .IX Item "-fcompare-elim" |
| 7324 | After register allocation and post-register allocation instruction splitting, |
| 7325 | identify arithmetic instructions that compute processor flags similar to a |
| 7326 | comparison operation based on that arithmetic. If possible, eliminate the |
| 7327 | explicit comparison operation. |
| 7328 | .Sp |
| 7329 | This pass only applies to certain targets that cannot explicitly represent |
| 7330 | the comparison operation before register allocation is complete. |
| 7331 | .Sp |
| 7332 | Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 7333 | .IP "\fB\-fcprop\-registers\fR" 4 |
| 7334 | .IX Item "-fcprop-registers" |
| 7335 | After register allocation and post-register allocation instruction splitting, |
| 7336 | we perform a copy-propagation pass to try to reduce scheduling dependencies |
| 7337 | and occasionally eliminate the copy. |
| 7338 | .Sp |
| 7339 | Enabled at levels \fB\-O\fR, \fB\-O2\fR, \fB\-O3\fR, \fB\-Os\fR. |
| 7340 | .IP "\fB\-fprofile\-correction\fR" 4 |
| 7341 | .IX Item "-fprofile-correction" |
| 7342 | Profiles collected using an instrumented binary for multi-threaded programs may |
| 7343 | be inconsistent due to missed counter updates. When this option is specified, |
| 7344 | \&\s-1GCC\s0 will use heuristics to correct or smooth out such inconsistencies. By |
| 7345 | default, \s-1GCC\s0 will emit an error message when an inconsistent profile is detected. |
| 7346 | .IP "\fB\-fprofile\-dir=\fR\fIpath\fR" 4 |
| 7347 | .IX Item "-fprofile-dir=path" |
| 7348 | Set the directory to search for the profile data files in to \fIpath\fR. |
| 7349 | This option affects only the profile data generated by |
| 7350 | \&\fB\-fprofile\-generate\fR, \fB\-ftest\-coverage\fR, \fB\-fprofile\-arcs\fR |
| 7351 | and used by \fB\-fprofile\-use\fR and \fB\-fbranch\-probabilities\fR |
| 7352 | and its related options. Both absolute and relative paths can be used. |
| 7353 | By default, \s-1GCC\s0 will use the current directory as \fIpath\fR, thus the |
| 7354 | profile data file will appear in the same directory as the object file. |
| 7355 | .IP "\fB\-fprofile\-generate\fR" 4 |
| 7356 | .IX Item "-fprofile-generate" |
| 7357 | .PD 0 |
| 7358 | .IP "\fB\-fprofile\-generate=\fR\fIpath\fR" 4 |
| 7359 | .IX Item "-fprofile-generate=path" |
| 7360 | .PD |
| 7361 | Enable options usually used for instrumenting application to produce |
| 7362 | profile useful for later recompilation with profile feedback based |
| 7363 | optimization. You must use \fB\-fprofile\-generate\fR both when |
| 7364 | compiling and when linking your program. |
| 7365 | .Sp |
| 7366 | The following options are enabled: \f(CW\*(C`\-fprofile\-arcs\*(C'\fR, \f(CW\*(C`\-fprofile\-values\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR. |
| 7367 | .Sp |
| 7368 | If \fIpath\fR is specified, \s-1GCC\s0 will look at the \fIpath\fR to find |
| 7369 | the profile feedback data files. See \fB\-fprofile\-dir\fR. |
| 7370 | .IP "\fB\-fprofile\-use\fR" 4 |
| 7371 | .IX Item "-fprofile-use" |
| 7372 | .PD 0 |
| 7373 | .IP "\fB\-fprofile\-use=\fR\fIpath\fR" 4 |
| 7374 | .IX Item "-fprofile-use=path" |
| 7375 | .PD |
| 7376 | Enable profile feedback directed optimizations, and optimizations |
| 7377 | generally profitable only with profile feedback available. |
| 7378 | .Sp |
| 7379 | The following options are enabled: \f(CW\*(C`\-fbranch\-probabilities\*(C'\fR, \f(CW\*(C`\-fvpt\*(C'\fR, |
| 7380 | \&\f(CW\*(C`\-funroll\-loops\*(C'\fR, \f(CW\*(C`\-fpeel\-loops\*(C'\fR, \f(CW\*(C`\-ftracer\*(C'\fR |
| 7381 | .Sp |
| 7382 | By default, \s-1GCC\s0 emits an error message if the feedback profiles do not |
| 7383 | match the source code. This error can be turned into a warning by using |
| 7384 | \&\fB\-Wcoverage\-mismatch\fR. Note this may result in poorly optimized |
| 7385 | code. |
| 7386 | .Sp |
| 7387 | If \fIpath\fR is specified, \s-1GCC\s0 will look at the \fIpath\fR to find |
| 7388 | the profile feedback data files. See \fB\-fprofile\-dir\fR. |
| 7389 | .PP |
| 7390 | The following options control compiler behavior regarding floating-point |
| 7391 | arithmetic. These options trade off between speed and |
| 7392 | correctness. All must be specifically enabled. |
| 7393 | .IP "\fB\-ffloat\-store\fR" 4 |
| 7394 | .IX Item "-ffloat-store" |
| 7395 | Do not store floating-point variables in registers, and inhibit other |
| 7396 | options that might change whether a floating-point value is taken from a |
| 7397 | register or memory. |
| 7398 | .Sp |
| 7399 | This option prevents undesirable excess precision on machines such as |
| 7400 | the 68000 where the floating registers (of the 68881) keep more |
| 7401 | precision than a \f(CW\*(C`double\*(C'\fR is supposed to have. Similarly for the |
| 7402 | x86 architecture. For most programs, the excess precision does only |
| 7403 | good, but a few programs rely on the precise definition of \s-1IEEE\s0 floating |
| 7404 | point. Use \fB\-ffloat\-store\fR for such programs, after modifying |
| 7405 | them to store all pertinent intermediate computations into variables. |
| 7406 | .IP "\fB\-fexcess\-precision=\fR\fIstyle\fR" 4 |
| 7407 | .IX Item "-fexcess-precision=style" |
| 7408 | This option allows further control over excess precision on machines |
| 7409 | where floating-point registers have more precision than the \s-1IEEE\s0 |
| 7410 | \&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR types and the processor does not |
| 7411 | support operations rounding to those types. By default, |
| 7412 | \&\fB\-fexcess\-precision=fast\fR is in effect; this means that |
| 7413 | operations are carried out in the precision of the registers and that |
| 7414 | it is unpredictable when rounding to the types specified in the source |
| 7415 | code takes place. When compiling C, if |
| 7416 | \&\fB\-fexcess\-precision=standard\fR is specified then excess |
| 7417 | precision will follow the rules specified in \s-1ISO\s0 C99; in particular, |
| 7418 | both casts and assignments cause values to be rounded to their |
| 7419 | semantic types (whereas \fB\-ffloat\-store\fR only affects |
| 7420 | assignments). This option is enabled by default for C if a strict |
| 7421 | conformance option such as \fB\-std=c99\fR is used. |
| 7422 | .Sp |
| 7423 | \&\fB\-fexcess\-precision=standard\fR is not implemented for languages |
| 7424 | other than C, and has no effect if |
| 7425 | \&\fB\-funsafe\-math\-optimizations\fR or \fB\-ffast\-math\fR is |
| 7426 | specified. On the x86, it also has no effect if \fB\-mfpmath=sse\fR |
| 7427 | or \fB\-mfpmath=sse+387\fR is specified; in the former case, \s-1IEEE\s0 |
| 7428 | semantics apply without excess precision, and in the latter, rounding |
| 7429 | is unpredictable. |
| 7430 | .IP "\fB\-ffast\-math\fR" 4 |
| 7431 | .IX Item "-ffast-math" |
| 7432 | Sets \fB\-fno\-math\-errno\fR, \fB\-funsafe\-math\-optimizations\fR, |
| 7433 | \&\fB\-ffinite\-math\-only\fR, \fB\-fno\-rounding\-math\fR, |
| 7434 | \&\fB\-fno\-signaling\-nans\fR and \fB\-fcx\-limited\-range\fR. |
| 7435 | .Sp |
| 7436 | This option causes the preprocessor macro \f(CW\*(C`_\|_FAST_MATH_\|_\*(C'\fR to be defined. |
| 7437 | .Sp |
| 7438 | This option is not turned on by any \fB\-O\fR option besides |
| 7439 | \&\fB\-Ofast\fR since it can result in incorrect output for programs |
| 7440 | that depend on an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications |
| 7441 | for math functions. It may, however, yield faster code for programs |
| 7442 | that do not require the guarantees of these specifications. |
| 7443 | .IP "\fB\-fno\-math\-errno\fR" 4 |
| 7444 | .IX Item "-fno-math-errno" |
| 7445 | Do not set \s-1ERRNO\s0 after calling math functions that are executed |
| 7446 | with a single instruction, e.g., sqrt. A program that relies on |
| 7447 | \&\s-1IEEE\s0 exceptions for math error handling may want to use this flag |
| 7448 | for speed while maintaining \s-1IEEE\s0 arithmetic compatibility. |
| 7449 | .Sp |
| 7450 | This option is not turned on by any \fB\-O\fR option since |
| 7451 | it can result in incorrect output for programs that depend on |
| 7452 | an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for |
| 7453 | math functions. It may, however, yield faster code for programs |
| 7454 | that do not require the guarantees of these specifications. |
| 7455 | .Sp |
| 7456 | The default is \fB\-fmath\-errno\fR. |
| 7457 | .Sp |
| 7458 | On Darwin systems, the math library never sets \f(CW\*(C`errno\*(C'\fR. There is |
| 7459 | therefore no reason for the compiler to consider the possibility that |
| 7460 | it might, and \fB\-fno\-math\-errno\fR is the default. |
| 7461 | .IP "\fB\-funsafe\-math\-optimizations\fR" 4 |
| 7462 | .IX Item "-funsafe-math-optimizations" |
| 7463 | Allow optimizations for floating-point arithmetic that (a) assume |
| 7464 | that arguments and results are valid and (b) may violate \s-1IEEE\s0 or |
| 7465 | \&\s-1ANSI\s0 standards. When used at link-time, it may include libraries |
| 7466 | or startup files that change the default \s-1FPU\s0 control word or other |
| 7467 | similar optimizations. |
| 7468 | .Sp |
| 7469 | This option is not turned on by any \fB\-O\fR option since |
| 7470 | it can result in incorrect output for programs that depend on |
| 7471 | an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for |
| 7472 | math functions. It may, however, yield faster code for programs |
| 7473 | that do not require the guarantees of these specifications. |
| 7474 | Enables \fB\-fno\-signed\-zeros\fR, \fB\-fno\-trapping\-math\fR, |
| 7475 | \&\fB\-fassociative\-math\fR and \fB\-freciprocal\-math\fR. |
| 7476 | .Sp |
| 7477 | The default is \fB\-fno\-unsafe\-math\-optimizations\fR. |
| 7478 | .IP "\fB\-fassociative\-math\fR" 4 |
| 7479 | .IX Item "-fassociative-math" |
| 7480 | Allow re-association of operands in series of floating-point operations. |
| 7481 | This violates the \s-1ISO\s0 C and \*(C+ language standard by possibly changing |
| 7482 | computation result. \s-1NOTE:\s0 re-ordering may change the sign of zero as |
| 7483 | well as ignore NaNs and inhibit or create underflow or overflow (and |
| 7484 | thus cannot be used on code that relies on rounding behavior like |
| 7485 | \&\f(CW\*(C`(x + 2**52) \- 2**52\*(C'\fR. May also reorder floating-point comparisons |
| 7486 | and thus may not be used when ordered comparisons are required. |
| 7487 | This option requires that both \fB\-fno\-signed\-zeros\fR and |
| 7488 | \&\fB\-fno\-trapping\-math\fR be in effect. Moreover, it doesn't make |
| 7489 | much sense with \fB\-frounding\-math\fR. For Fortran the option |
| 7490 | is automatically enabled when both \fB\-fno\-signed\-zeros\fR and |
| 7491 | \&\fB\-fno\-trapping\-math\fR are in effect. |
| 7492 | .Sp |
| 7493 | The default is \fB\-fno\-associative\-math\fR. |
| 7494 | .IP "\fB\-freciprocal\-math\fR" 4 |
| 7495 | .IX Item "-freciprocal-math" |
| 7496 | Allow the reciprocal of a value to be used instead of dividing by |
| 7497 | the value if this enables optimizations. For example \f(CW\*(C`x / y\*(C'\fR |
| 7498 | can be replaced with \f(CW\*(C`x * (1/y)\*(C'\fR, which is useful if \f(CW\*(C`(1/y)\*(C'\fR |
| 7499 | is subject to common subexpression elimination. Note that this loses |
| 7500 | precision and increases the number of flops operating on the value. |
| 7501 | .Sp |
| 7502 | The default is \fB\-fno\-reciprocal\-math\fR. |
| 7503 | .IP "\fB\-ffinite\-math\-only\fR" 4 |
| 7504 | .IX Item "-ffinite-math-only" |
| 7505 | Allow optimizations for floating-point arithmetic that assume |
| 7506 | that arguments and results are not NaNs or +\-Infs. |
| 7507 | .Sp |
| 7508 | This option is not turned on by any \fB\-O\fR option since |
| 7509 | it can result in incorrect output for programs that depend on |
| 7510 | an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for |
| 7511 | math functions. It may, however, yield faster code for programs |
| 7512 | that do not require the guarantees of these specifications. |
| 7513 | .Sp |
| 7514 | The default is \fB\-fno\-finite\-math\-only\fR. |
| 7515 | .IP "\fB\-fno\-signed\-zeros\fR" 4 |
| 7516 | .IX Item "-fno-signed-zeros" |
| 7517 | Allow optimizations for floating-point arithmetic that ignore the |
| 7518 | signedness of zero. \s-1IEEE\s0 arithmetic specifies the behavior of |
| 7519 | distinct +0.0 and \-0.0 values, which then prohibits simplification |
| 7520 | of expressions such as x+0.0 or 0.0*x (even with \fB\-ffinite\-math\-only\fR). |
| 7521 | This option implies that the sign of a zero result isn't significant. |
| 7522 | .Sp |
| 7523 | The default is \fB\-fsigned\-zeros\fR. |
| 7524 | .IP "\fB\-fno\-trapping\-math\fR" 4 |
| 7525 | .IX Item "-fno-trapping-math" |
| 7526 | Compile code assuming that floating-point operations cannot generate |
| 7527 | user-visible traps. These traps include division by zero, overflow, |
| 7528 | underflow, inexact result and invalid operation. This option requires |
| 7529 | that \fB\-fno\-signaling\-nans\fR be in effect. Setting this option may |
| 7530 | allow faster code if one relies on \*(L"non-stop\*(R" \s-1IEEE\s0 arithmetic, for example. |
| 7531 | .Sp |
| 7532 | This option should never be turned on by any \fB\-O\fR option since |
| 7533 | it can result in incorrect output for programs that depend on |
| 7534 | an exact implementation of \s-1IEEE\s0 or \s-1ISO\s0 rules/specifications for |
| 7535 | math functions. |
| 7536 | .Sp |
| 7537 | The default is \fB\-ftrapping\-math\fR. |
| 7538 | .IP "\fB\-frounding\-math\fR" 4 |
| 7539 | .IX Item "-frounding-math" |
| 7540 | Disable transformations and optimizations that assume default floating-point |
| 7541 | rounding behavior. This is round-to-zero for all floating point |
| 7542 | to integer conversions, and round-to-nearest for all other arithmetic |
| 7543 | truncations. This option should be specified for programs that change |
| 7544 | the \s-1FP\s0 rounding mode dynamically, or that may be executed with a |
| 7545 | non-default rounding mode. This option disables constant folding of |
| 7546 | floating-point expressions at compile time (which may be affected by |
| 7547 | rounding mode) and arithmetic transformations that are unsafe in the |
| 7548 | presence of sign-dependent rounding modes. |
| 7549 | .Sp |
| 7550 | The default is \fB\-fno\-rounding\-math\fR. |
| 7551 | .Sp |
| 7552 | This option is experimental and does not currently guarantee to |
| 7553 | disable all \s-1GCC\s0 optimizations that are affected by rounding mode. |
| 7554 | Future versions of \s-1GCC\s0 may provide finer control of this setting |
| 7555 | using C99's \f(CW\*(C`FENV_ACCESS\*(C'\fR pragma. This command-line option |
| 7556 | will be used to specify the default state for \f(CW\*(C`FENV_ACCESS\*(C'\fR. |
| 7557 | .IP "\fB\-fsignaling\-nans\fR" 4 |
| 7558 | .IX Item "-fsignaling-nans" |
| 7559 | Compile code assuming that \s-1IEEE\s0 signaling NaNs may generate user-visible |
| 7560 | traps during floating-point operations. Setting this option disables |
| 7561 | optimizations that may change the number of exceptions visible with |
| 7562 | signaling NaNs. This option implies \fB\-ftrapping\-math\fR. |
| 7563 | .Sp |
| 7564 | This option causes the preprocessor macro \f(CW\*(C`_\|_SUPPORT_SNAN_\|_\*(C'\fR to |
| 7565 | be defined. |
| 7566 | .Sp |
| 7567 | The default is \fB\-fno\-signaling\-nans\fR. |
| 7568 | .Sp |
| 7569 | This option is experimental and does not currently guarantee to |
| 7570 | disable all \s-1GCC\s0 optimizations that affect signaling NaN behavior. |
| 7571 | .IP "\fB\-fsingle\-precision\-constant\fR" 4 |
| 7572 | .IX Item "-fsingle-precision-constant" |
| 7573 | Treat floating-point constants as single precision instead of |
| 7574 | implicitly converting them to double-precision constants. |
| 7575 | .IP "\fB\-fcx\-limited\-range\fR" 4 |
| 7576 | .IX Item "-fcx-limited-range" |
| 7577 | When enabled, this option states that a range reduction step is not |
| 7578 | needed when performing complex division. Also, there is no checking |
| 7579 | whether the result of a complex multiplication or division is \f(CW\*(C`NaN |
| 7580 | + I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. The |
| 7581 | default is \fB\-fno\-cx\-limited\-range\fR, but is enabled by |
| 7582 | \&\fB\-ffast\-math\fR. |
| 7583 | .Sp |
| 7584 | This option controls the default setting of the \s-1ISO\s0 C99 |
| 7585 | \&\f(CW\*(C`CX_LIMITED_RANGE\*(C'\fR pragma. Nevertheless, the option applies to |
| 7586 | all languages. |
| 7587 | .IP "\fB\-fcx\-fortran\-rules\fR" 4 |
| 7588 | .IX Item "-fcx-fortran-rules" |
| 7589 | Complex multiplication and division follow Fortran rules. Range |
| 7590 | reduction is done as part of complex division, but there is no checking |
| 7591 | whether the result of a complex multiplication or division is \f(CW\*(C`NaN |
| 7592 | + I*NaN\*(C'\fR, with an attempt to rescue the situation in that case. |
| 7593 | .Sp |
| 7594 | The default is \fB\-fno\-cx\-fortran\-rules\fR. |
| 7595 | .PP |
| 7596 | The following options control optimizations that may improve |
| 7597 | performance, but are not enabled by any \fB\-O\fR options. This |
| 7598 | section includes experimental options that may produce broken code. |
| 7599 | .IP "\fB\-fbranch\-probabilities\fR" 4 |
| 7600 | .IX Item "-fbranch-probabilities" |
| 7601 | After running a program compiled with \fB\-fprofile\-arcs\fR, you can compile it a second time using |
| 7602 | \&\fB\-fbranch\-probabilities\fR, to improve optimizations based on |
| 7603 | the number of times each branch was taken. When the program |
| 7604 | compiled with \fB\-fprofile\-arcs\fR exits it saves arc execution |
| 7605 | counts to a file called \fI\fIsourcename\fI.gcda\fR for each source |
| 7606 | file. The information in this data file is very dependent on the |
| 7607 | structure of the generated code, so you must use the same source code |
| 7608 | and the same optimization options for both compilations. |
| 7609 | .Sp |
| 7610 | With \fB\-fbranch\-probabilities\fR, \s-1GCC\s0 puts a |
| 7611 | \&\fB\s-1REG_BR_PROB\s0\fR note on each \fB\s-1JUMP_INSN\s0\fR and \fB\s-1CALL_INSN\s0\fR. |
| 7612 | These can be used to improve optimization. Currently, they are only |
| 7613 | used in one place: in \fIreorg.c\fR, instead of guessing which path a |
| 7614 | branch is most likely to take, the \fB\s-1REG_BR_PROB\s0\fR values are used to |
| 7615 | exactly determine which path is taken more often. |
| 7616 | .IP "\fB\-fprofile\-values\fR" 4 |
| 7617 | .IX Item "-fprofile-values" |
| 7618 | If combined with \fB\-fprofile\-arcs\fR, it adds code so that some |
| 7619 | data about values of expressions in the program is gathered. |
| 7620 | .Sp |
| 7621 | With \fB\-fbranch\-probabilities\fR, it reads back the data gathered |
| 7622 | from profiling values of expressions for usage in optimizations. |
| 7623 | .Sp |
| 7624 | Enabled with \fB\-fprofile\-generate\fR and \fB\-fprofile\-use\fR. |
| 7625 | .IP "\fB\-fvpt\fR" 4 |
| 7626 | .IX Item "-fvpt" |
| 7627 | If combined with \fB\-fprofile\-arcs\fR, it instructs the compiler to add |
| 7628 | a code to gather information about values of expressions. |
| 7629 | .Sp |
| 7630 | With \fB\-fbranch\-probabilities\fR, it reads back the data gathered |
| 7631 | and actually performs the optimizations based on them. |
| 7632 | Currently the optimizations include specialization of division operation |
| 7633 | using the knowledge about the value of the denominator. |
| 7634 | .IP "\fB\-frename\-registers\fR" 4 |
| 7635 | .IX Item "-frename-registers" |
| 7636 | Attempt to avoid false dependencies in scheduled code by making use |
| 7637 | of registers left over after register allocation. This optimization |
| 7638 | will most benefit processors with lots of registers. Depending on the |
| 7639 | debug information format adopted by the target, however, it can |
| 7640 | make debugging impossible, since variables will no longer stay in |
| 7641 | a \*(L"home register\*(R". |
| 7642 | .Sp |
| 7643 | Enabled by default with \fB\-funroll\-loops\fR and \fB\-fpeel\-loops\fR. |
| 7644 | .IP "\fB\-ftracer\fR" 4 |
| 7645 | .IX Item "-ftracer" |
| 7646 | Perform tail duplication to enlarge superblock size. This transformation |
| 7647 | simplifies the control flow of the function allowing other optimizations to do |
| 7648 | better job. |
| 7649 | .Sp |
| 7650 | Enabled with \fB\-fprofile\-use\fR. |
| 7651 | .IP "\fB\-funroll\-loops\fR" 4 |
| 7652 | .IX Item "-funroll-loops" |
| 7653 | Unroll loops whose number of iterations can be determined at compile time or |
| 7654 | upon entry to the loop. \fB\-funroll\-loops\fR implies |
| 7655 | \&\fB\-frerun\-cse\-after\-loop\fR, \fB\-fweb\fR and \fB\-frename\-registers\fR. |
| 7656 | It also turns on complete loop peeling (i.e. complete removal of loops with |
| 7657 | small constant number of iterations). This option makes code larger, and may |
| 7658 | or may not make it run faster. |
| 7659 | .Sp |
| 7660 | Enabled with \fB\-fprofile\-use\fR. |
| 7661 | .IP "\fB\-funroll\-all\-loops\fR" 4 |
| 7662 | .IX Item "-funroll-all-loops" |
| 7663 | Unroll all loops, even if their number of iterations is uncertain when |
| 7664 | the loop is entered. This usually makes programs run more slowly. |
| 7665 | \&\fB\-funroll\-all\-loops\fR implies the same options as |
| 7666 | \&\fB\-funroll\-loops\fR. |
| 7667 | .IP "\fB\-fpeel\-loops\fR" 4 |
| 7668 | .IX Item "-fpeel-loops" |
| 7669 | Peels loops for which there is enough information that they do not |
| 7670 | roll much (from profile feedback). It also turns on complete loop peeling |
| 7671 | (i.e. complete removal of loops with small constant number of iterations). |
| 7672 | .Sp |
| 7673 | Enabled with \fB\-fprofile\-use\fR. |
| 7674 | .IP "\fB\-fmove\-loop\-invariants\fR" 4 |
| 7675 | .IX Item "-fmove-loop-invariants" |
| 7676 | Enables the loop invariant motion pass in the \s-1RTL\s0 loop optimizer. Enabled |
| 7677 | at level \fB\-O1\fR |
| 7678 | .IP "\fB\-funswitch\-loops\fR" 4 |
| 7679 | .IX Item "-funswitch-loops" |
| 7680 | Move branches with loop invariant conditions out of the loop, with duplicates |
| 7681 | of the loop on both branches (modified according to result of the condition). |
| 7682 | .IP "\fB\-ffunction\-sections\fR" 4 |
| 7683 | .IX Item "-ffunction-sections" |
| 7684 | .PD 0 |
| 7685 | .IP "\fB\-fdata\-sections\fR" 4 |
| 7686 | .IX Item "-fdata-sections" |
| 7687 | .PD |
| 7688 | Place each function or data item into its own section in the output |
| 7689 | file if the target supports arbitrary sections. The name of the |
| 7690 | function or the name of the data item determines the section's name |
| 7691 | in the output file. |
| 7692 | .Sp |
| 7693 | Use these options on systems where the linker can perform optimizations |
| 7694 | to improve locality of reference in the instruction space. Most systems |
| 7695 | using the \s-1ELF\s0 object format and \s-1SPARC\s0 processors running Solaris 2 have |
| 7696 | linkers with such optimizations. \s-1AIX\s0 may have these optimizations in |
| 7697 | the future. |
| 7698 | .Sp |
| 7699 | Only use these options when there are significant benefits from doing |
| 7700 | so. When you specify these options, the assembler and linker will |
| 7701 | create larger object and executable files and will also be slower. |
| 7702 | You will not be able to use \f(CW\*(C`gprof\*(C'\fR on all systems if you |
| 7703 | specify this option and you may have problems with debugging if |
| 7704 | you specify both this option and \fB\-g\fR. |
| 7705 | .IP "\fB\-fbranch\-target\-load\-optimize\fR" 4 |
| 7706 | .IX Item "-fbranch-target-load-optimize" |
| 7707 | Perform branch target register load optimization before prologue / epilogue |
| 7708 | threading. |
| 7709 | The use of target registers can typically be exposed only during reload, |
| 7710 | thus hoisting loads out of loops and doing inter-block scheduling needs |
| 7711 | a separate optimization pass. |
| 7712 | .IP "\fB\-fbranch\-target\-load\-optimize2\fR" 4 |
| 7713 | .IX Item "-fbranch-target-load-optimize2" |
| 7714 | Perform branch target register load optimization after prologue / epilogue |
| 7715 | threading. |
| 7716 | .IP "\fB\-fbtr\-bb\-exclusive\fR" 4 |
| 7717 | .IX Item "-fbtr-bb-exclusive" |
| 7718 | When performing branch target register load optimization, don't reuse |
| 7719 | branch target registers in within any basic block. |
| 7720 | .IP "\fB\-fstack\-protector\fR" 4 |
| 7721 | .IX Item "-fstack-protector" |
| 7722 | Emit extra code to check for buffer overflows, such as stack smashing |
| 7723 | attacks. This is done by adding a guard variable to functions with |
| 7724 | vulnerable objects. This includes functions that call alloca, and |
| 7725 | functions with buffers larger than 8 bytes. The guards are initialized |
| 7726 | when a function is entered and then checked when the function exits. |
| 7727 | If a guard check fails, an error message is printed and the program exits. |
| 7728 | .IP "\fB\-fstack\-protector\-all\fR" 4 |
| 7729 | .IX Item "-fstack-protector-all" |
| 7730 | Like \fB\-fstack\-protector\fR except that all functions are protected. |
| 7731 | .IP "\fB\-fsection\-anchors\fR" 4 |
| 7732 | .IX Item "-fsection-anchors" |
| 7733 | Try to reduce the number of symbolic address calculations by using |
| 7734 | shared \*(L"anchor\*(R" symbols to address nearby objects. This transformation |
| 7735 | can help to reduce the number of \s-1GOT\s0 entries and \s-1GOT\s0 accesses on some |
| 7736 | targets. |
| 7737 | .Sp |
| 7738 | For example, the implementation of the following function \f(CW\*(C`foo\*(C'\fR: |
| 7739 | .Sp |
| 7740 | .Vb 2 |
| 7741 | \& static int a, b, c; |
| 7742 | \& int foo (void) { return a + b + c; } |
| 7743 | .Ve |
| 7744 | .Sp |
| 7745 | would usually calculate the addresses of all three variables, but if you |
| 7746 | compile it with \fB\-fsection\-anchors\fR, it will access the variables |
| 7747 | from a common anchor point instead. The effect is similar to the |
| 7748 | following pseudocode (which isn't valid C): |
| 7749 | .Sp |
| 7750 | .Vb 5 |
| 7751 | \& int foo (void) |
| 7752 | \& { |
| 7753 | \& register int *xr = &x; |
| 7754 | \& return xr[&a \- &x] + xr[&b \- &x] + xr[&c \- &x]; |
| 7755 | \& } |
| 7756 | .Ve |
| 7757 | .Sp |
| 7758 | Not all targets support this option. |
| 7759 | .IP "\fB\-\-param\fR \fIname\fR\fB=\fR\fIvalue\fR" 4 |
| 7760 | .IX Item "--param name=value" |
| 7761 | In some places, \s-1GCC\s0 uses various constants to control the amount of |
| 7762 | optimization that is done. For example, \s-1GCC\s0 will not inline functions |
| 7763 | that contain more than a certain number of instructions. You can |
| 7764 | control some of these constants on the command line using the |
| 7765 | \&\fB\-\-param\fR option. |
| 7766 | .Sp |
| 7767 | The names of specific parameters, and the meaning of the values, are |
| 7768 | tied to the internals of the compiler, and are subject to change |
| 7769 | without notice in future releases. |
| 7770 | .Sp |
| 7771 | In each case, the \fIvalue\fR is an integer. The allowable choices for |
| 7772 | \&\fIname\fR are given in the following table: |
| 7773 | .RS 4 |
| 7774 | .IP "\fBpredictable-branch-outcome\fR" 4 |
| 7775 | .IX Item "predictable-branch-outcome" |
| 7776 | When branch is predicted to be taken with probability lower than this threshold |
| 7777 | (in percent), then it is considered well predictable. The default is 10. |
| 7778 | .IP "\fBmax-crossjump-edges\fR" 4 |
| 7779 | .IX Item "max-crossjump-edges" |
| 7780 | The maximum number of incoming edges to consider for crossjumping. |
| 7781 | The algorithm used by \fB\-fcrossjumping\fR is O(N^2) in |
| 7782 | the number of edges incoming to each block. Increasing values mean |
| 7783 | more aggressive optimization, making the compilation time increase with |
| 7784 | probably small improvement in executable size. |
| 7785 | .IP "\fBmin-crossjump-insns\fR" 4 |
| 7786 | .IX Item "min-crossjump-insns" |
| 7787 | The minimum number of instructions that must be matched at the end |
| 7788 | of two blocks before crossjumping will be performed on them. This |
| 7789 | value is ignored in the case where all instructions in the block being |
| 7790 | crossjumped from are matched. The default value is 5. |
| 7791 | .IP "\fBmax-grow-copy-bb-insns\fR" 4 |
| 7792 | .IX Item "max-grow-copy-bb-insns" |
| 7793 | The maximum code size expansion factor when copying basic blocks |
| 7794 | instead of jumping. The expansion is relative to a jump instruction. |
| 7795 | The default value is 8. |
| 7796 | .IP "\fBmax-goto-duplication-insns\fR" 4 |
| 7797 | .IX Item "max-goto-duplication-insns" |
| 7798 | The maximum number of instructions to duplicate to a block that jumps |
| 7799 | to a computed goto. To avoid O(N^2) behavior in a number of |
| 7800 | passes, \s-1GCC\s0 factors computed gotos early in the compilation process, |
| 7801 | and unfactors them as late as possible. Only computed jumps at the |
| 7802 | end of a basic blocks with no more than max-goto-duplication-insns are |
| 7803 | unfactored. The default value is 8. |
| 7804 | .IP "\fBmax-delay-slot-insn-search\fR" 4 |
| 7805 | .IX Item "max-delay-slot-insn-search" |
| 7806 | The maximum number of instructions to consider when looking for an |
| 7807 | instruction to fill a delay slot. If more than this arbitrary number of |
| 7808 | instructions is searched, the time savings from filling the delay slot |
| 7809 | will be minimal so stop searching. Increasing values mean more |
| 7810 | aggressive optimization, making the compilation time increase with probably |
| 7811 | small improvement in execution time. |
| 7812 | .IP "\fBmax-delay-slot-live-search\fR" 4 |
| 7813 | .IX Item "max-delay-slot-live-search" |
| 7814 | When trying to fill delay slots, the maximum number of instructions to |
| 7815 | consider when searching for a block with valid live register |
| 7816 | information. Increasing this arbitrarily chosen value means more |
| 7817 | aggressive optimization, increasing the compilation time. This parameter |
| 7818 | should be removed when the delay slot code is rewritten to maintain the |
| 7819 | control-flow graph. |
| 7820 | .IP "\fBmax-gcse-memory\fR" 4 |
| 7821 | .IX Item "max-gcse-memory" |
| 7822 | The approximate maximum amount of memory that will be allocated in |
| 7823 | order to perform the global common subexpression elimination |
| 7824 | optimization. If more memory than specified is required, the |
| 7825 | optimization will not be done. |
| 7826 | .IP "\fBmax-gcse-insertion-ratio\fR" 4 |
| 7827 | .IX Item "max-gcse-insertion-ratio" |
| 7828 | If the ratio of expression insertions to deletions is larger than this value |
| 7829 | for any expression, then \s-1RTL\s0 \s-1PRE\s0 will insert or remove the expression and thus |
| 7830 | leave partially redundant computations in the instruction stream. The default value is 20. |
| 7831 | .IP "\fBmax-pending-list-length\fR" 4 |
| 7832 | .IX Item "max-pending-list-length" |
| 7833 | The maximum number of pending dependencies scheduling will allow |
| 7834 | before flushing the current state and starting over. Large functions |
| 7835 | with few branches or calls can create excessively large lists which |
| 7836 | needlessly consume memory and resources. |
| 7837 | .IP "\fBmax-modulo-backtrack-attempts\fR" 4 |
| 7838 | .IX Item "max-modulo-backtrack-attempts" |
| 7839 | The maximum number of backtrack attempts the scheduler should make |
| 7840 | when modulo scheduling a loop. Larger values can exponentially increase |
| 7841 | compilation time. |
| 7842 | .IP "\fBmax-inline-insns-single\fR" 4 |
| 7843 | .IX Item "max-inline-insns-single" |
| 7844 | Several parameters control the tree inliner used in gcc. |
| 7845 | This number sets the maximum number of instructions (counted in \s-1GCC\s0's |
| 7846 | internal representation) in a single function that the tree inliner |
| 7847 | will consider for inlining. This only affects functions declared |
| 7848 | inline and methods implemented in a class declaration (\*(C+). |
| 7849 | The default value is 400. |
| 7850 | .IP "\fBmax-inline-insns-auto\fR" 4 |
| 7851 | .IX Item "max-inline-insns-auto" |
| 7852 | When you use \fB\-finline\-functions\fR (included in \fB\-O3\fR), |
| 7853 | a lot of functions that would otherwise not be considered for inlining |
| 7854 | by the compiler will be investigated. To those functions, a different |
| 7855 | (more restrictive) limit compared to functions declared inline can |
| 7856 | be applied. |
| 7857 | The default value is 40. |
| 7858 | .IP "\fBlarge-function-insns\fR" 4 |
| 7859 | .IX Item "large-function-insns" |
| 7860 | The limit specifying really large functions. For functions larger than this |
| 7861 | limit after inlining, inlining is constrained by |
| 7862 | \&\fB\-\-param large-function-growth\fR. This parameter is useful primarily |
| 7863 | to avoid extreme compilation time caused by non-linear algorithms used by the |
| 7864 | back end. |
| 7865 | The default value is 2700. |
| 7866 | .IP "\fBlarge-function-growth\fR" 4 |
| 7867 | .IX Item "large-function-growth" |
| 7868 | Specifies maximal growth of large function caused by inlining in percents. |
| 7869 | The default value is 100 which limits large function growth to 2.0 times |
| 7870 | the original size. |
| 7871 | .IP "\fBlarge-unit-insns\fR" 4 |
| 7872 | .IX Item "large-unit-insns" |
| 7873 | The limit specifying large translation unit. Growth caused by inlining of |
| 7874 | units larger than this limit is limited by \fB\-\-param inline-unit-growth\fR. |
| 7875 | For small units this might be too tight (consider unit consisting of function A |
| 7876 | that is inline and B that just calls A three time. If B is small relative to |
| 7877 | A, the growth of unit is 300\e% and yet such inlining is very sane. For very |
| 7878 | large units consisting of small inlineable functions however the overall unit |
| 7879 | growth limit is needed to avoid exponential explosion of code size. Thus for |
| 7880 | smaller units, the size is increased to \fB\-\-param large-unit-insns\fR |
| 7881 | before applying \fB\-\-param inline-unit-growth\fR. The default is 10000 |
| 7882 | .IP "\fBinline-unit-growth\fR" 4 |
| 7883 | .IX Item "inline-unit-growth" |
| 7884 | Specifies maximal overall growth of the compilation unit caused by inlining. |
| 7885 | The default value is 30 which limits unit growth to 1.3 times the original |
| 7886 | size. |
| 7887 | .IP "\fBipcp-unit-growth\fR" 4 |
| 7888 | .IX Item "ipcp-unit-growth" |
| 7889 | Specifies maximal overall growth of the compilation unit caused by |
| 7890 | interprocedural constant propagation. The default value is 10 which limits |
| 7891 | unit growth to 1.1 times the original size. |
| 7892 | .IP "\fBlarge-stack-frame\fR" 4 |
| 7893 | .IX Item "large-stack-frame" |
| 7894 | The limit specifying large stack frames. While inlining the algorithm is trying |
| 7895 | to not grow past this limit too much. Default value is 256 bytes. |
| 7896 | .IP "\fBlarge-stack-frame-growth\fR" 4 |
| 7897 | .IX Item "large-stack-frame-growth" |
| 7898 | Specifies maximal growth of large stack frames caused by inlining in percents. |
| 7899 | The default value is 1000 which limits large stack frame growth to 11 times |
| 7900 | the original size. |
| 7901 | .IP "\fBmax-inline-insns-recursive\fR" 4 |
| 7902 | .IX Item "max-inline-insns-recursive" |
| 7903 | .PD 0 |
| 7904 | .IP "\fBmax-inline-insns-recursive-auto\fR" 4 |
| 7905 | .IX Item "max-inline-insns-recursive-auto" |
| 7906 | .PD |
| 7907 | Specifies maximum number of instructions out-of-line copy of self recursive inline |
| 7908 | function can grow into by performing recursive inlining. |
| 7909 | .Sp |
| 7910 | For functions declared inline \fB\-\-param max-inline-insns-recursive\fR is |
| 7911 | taken into account. For function not declared inline, recursive inlining |
| 7912 | happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is |
| 7913 | enabled and \fB\-\-param max-inline-insns-recursive-auto\fR is used. The |
| 7914 | default value is 450. |
| 7915 | .IP "\fBmax-inline-recursive-depth\fR" 4 |
| 7916 | .IX Item "max-inline-recursive-depth" |
| 7917 | .PD 0 |
| 7918 | .IP "\fBmax-inline-recursive-depth-auto\fR" 4 |
| 7919 | .IX Item "max-inline-recursive-depth-auto" |
| 7920 | .PD |
| 7921 | Specifies maximum recursion depth used by the recursive inlining. |
| 7922 | .Sp |
| 7923 | For functions declared inline \fB\-\-param max-inline-recursive-depth\fR is |
| 7924 | taken into account. For function not declared inline, recursive inlining |
| 7925 | happens only when \fB\-finline\-functions\fR (included in \fB\-O3\fR) is |
| 7926 | enabled and \fB\-\-param max-inline-recursive-depth-auto\fR is used. The |
| 7927 | default value is 8. |
| 7928 | .IP "\fBmin-inline-recursive-probability\fR" 4 |
| 7929 | .IX Item "min-inline-recursive-probability" |
| 7930 | Recursive inlining is profitable only for function having deep recursion |
| 7931 | in average and can hurt for function having little recursion depth by |
| 7932 | increasing the prologue size or complexity of function body to other |
| 7933 | optimizers. |
| 7934 | .Sp |
| 7935 | When profile feedback is available (see \fB\-fprofile\-generate\fR) the actual |
| 7936 | recursion depth can be guessed from probability that function will recurse via |
| 7937 | given call expression. This parameter limits inlining only to call expression |
| 7938 | whose probability exceeds given threshold (in percents). The default value is |
| 7939 | 10. |
| 7940 | .IP "\fBearly-inlining-insns\fR" 4 |
| 7941 | .IX Item "early-inlining-insns" |
| 7942 | Specify growth that early inliner can make. In effect it increases amount of |
| 7943 | inlining for code having large abstraction penalty. The default value is 10. |
| 7944 | .IP "\fBmax-early-inliner-iterations\fR" 4 |
| 7945 | .IX Item "max-early-inliner-iterations" |
| 7946 | .PD 0 |
| 7947 | .IP "\fBmax-early-inliner-iterations\fR" 4 |
| 7948 | .IX Item "max-early-inliner-iterations" |
| 7949 | .PD |
| 7950 | Limit of iterations of early inliner. This basically bounds number of nested |
| 7951 | indirect calls early inliner can resolve. Deeper chains are still handled by |
| 7952 | late inlining. |
| 7953 | .IP "\fBcomdat-sharing-probability\fR" 4 |
| 7954 | .IX Item "comdat-sharing-probability" |
| 7955 | .PD 0 |
| 7956 | .IP "\fBcomdat-sharing-probability\fR" 4 |
| 7957 | .IX Item "comdat-sharing-probability" |
| 7958 | .PD |
| 7959 | Probability (in percent) that \*(C+ inline function with comdat visibility |
| 7960 | will be shared across multiple compilation units. The default value is 20. |
| 7961 | .IP "\fBmin-vect-loop-bound\fR" 4 |
| 7962 | .IX Item "min-vect-loop-bound" |
| 7963 | The minimum number of iterations under which a loop will not get vectorized |
| 7964 | when \fB\-ftree\-vectorize\fR is used. The number of iterations after |
| 7965 | vectorization needs to be greater than the value specified by this option |
| 7966 | to allow vectorization. The default value is 0. |
| 7967 | .IP "\fBgcse-cost-distance-ratio\fR" 4 |
| 7968 | .IX Item "gcse-cost-distance-ratio" |
| 7969 | Scaling factor in calculation of maximum distance an expression |
| 7970 | can be moved by \s-1GCSE\s0 optimizations. This is currently supported only in the |
| 7971 | code hoisting pass. The bigger the ratio, the more aggressive code hoisting |
| 7972 | will be with simple expressions, i.e., the expressions that have cost |
| 7973 | less than \fBgcse-unrestricted-cost\fR. Specifying 0 will disable |
| 7974 | hoisting of simple expressions. The default value is 10. |
| 7975 | .IP "\fBgcse-unrestricted-cost\fR" 4 |
| 7976 | .IX Item "gcse-unrestricted-cost" |
| 7977 | Cost, roughly measured as the cost of a single typical machine |
| 7978 | instruction, at which \s-1GCSE\s0 optimizations will not constrain |
| 7979 | the distance an expression can travel. This is currently |
| 7980 | supported only in the code hoisting pass. The lesser the cost, |
| 7981 | the more aggressive code hoisting will be. Specifying 0 will |
| 7982 | allow all expressions to travel unrestricted distances. |
| 7983 | The default value is 3. |
| 7984 | .IP "\fBmax-hoist-depth\fR" 4 |
| 7985 | .IX Item "max-hoist-depth" |
| 7986 | The depth of search in the dominator tree for expressions to hoist. |
| 7987 | This is used to avoid quadratic behavior in hoisting algorithm. |
| 7988 | The value of 0 will avoid limiting the search, but may slow down compilation |
| 7989 | of huge functions. The default value is 30. |
| 7990 | .IP "\fBmax-tail-merge-comparisons\fR" 4 |
| 7991 | .IX Item "max-tail-merge-comparisons" |
| 7992 | The maximum amount of similar bbs to compare a bb with. This is used to |
| 7993 | avoid quadratic behavior in tree tail merging. The default value is 10. |
| 7994 | .IP "\fBmax-tail-merge-iterations\fR" 4 |
| 7995 | .IX Item "max-tail-merge-iterations" |
| 7996 | The maximum amount of iterations of the pass over the function. This is used to |
| 7997 | limit compilation time in tree tail merging. The default value is 2. |
| 7998 | .IP "\fBmax-unrolled-insns\fR" 4 |
| 7999 | .IX Item "max-unrolled-insns" |
| 8000 | The maximum number of instructions that a loop should have if that loop |
| 8001 | is unrolled, and if the loop is unrolled, it determines how many times |
| 8002 | the loop code is unrolled. |
| 8003 | .IP "\fBmax-average-unrolled-insns\fR" 4 |
| 8004 | .IX Item "max-average-unrolled-insns" |
| 8005 | The maximum number of instructions biased by probabilities of their execution |
| 8006 | that a loop should have if that loop is unrolled, and if the loop is unrolled, |
| 8007 | it determines how many times the loop code is unrolled. |
| 8008 | .IP "\fBmax-unroll-times\fR" 4 |
| 8009 | .IX Item "max-unroll-times" |
| 8010 | The maximum number of unrollings of a single loop. |
| 8011 | .IP "\fBmax-peeled-insns\fR" 4 |
| 8012 | .IX Item "max-peeled-insns" |
| 8013 | The maximum number of instructions that a loop should have if that loop |
| 8014 | is peeled, and if the loop is peeled, it determines how many times |
| 8015 | the loop code is peeled. |
| 8016 | .IP "\fBmax-peel-times\fR" 4 |
| 8017 | .IX Item "max-peel-times" |
| 8018 | The maximum number of peelings of a single loop. |
| 8019 | .IP "\fBmax-completely-peeled-insns\fR" 4 |
| 8020 | .IX Item "max-completely-peeled-insns" |
| 8021 | The maximum number of insns of a completely peeled loop. |
| 8022 | .IP "\fBmax-completely-peel-times\fR" 4 |
| 8023 | .IX Item "max-completely-peel-times" |
| 8024 | The maximum number of iterations of a loop to be suitable for complete peeling. |
| 8025 | .IP "\fBmax-completely-peel-loop-nest-depth\fR" 4 |
| 8026 | .IX Item "max-completely-peel-loop-nest-depth" |
| 8027 | The maximum depth of a loop nest suitable for complete peeling. |
| 8028 | .IP "\fBmax-unswitch-insns\fR" 4 |
| 8029 | .IX Item "max-unswitch-insns" |
| 8030 | The maximum number of insns of an unswitched loop. |
| 8031 | .IP "\fBmax-unswitch-level\fR" 4 |
| 8032 | .IX Item "max-unswitch-level" |
| 8033 | The maximum number of branches unswitched in a single loop. |
| 8034 | .IP "\fBlim-expensive\fR" 4 |
| 8035 | .IX Item "lim-expensive" |
| 8036 | The minimum cost of an expensive expression in the loop invariant motion. |
| 8037 | .IP "\fBiv-consider-all-candidates-bound\fR" 4 |
| 8038 | .IX Item "iv-consider-all-candidates-bound" |
| 8039 | Bound on number of candidates for induction variables below that |
| 8040 | all candidates are considered for each use in induction variable |
| 8041 | optimizations. Only the most relevant candidates are considered |
| 8042 | if there are more candidates, to avoid quadratic time complexity. |
| 8043 | .IP "\fBiv-max-considered-uses\fR" 4 |
| 8044 | .IX Item "iv-max-considered-uses" |
| 8045 | The induction variable optimizations give up on loops that contain more |
| 8046 | induction variable uses. |
| 8047 | .IP "\fBiv-always-prune-cand-set-bound\fR" 4 |
| 8048 | .IX Item "iv-always-prune-cand-set-bound" |
| 8049 | If number of candidates in the set is smaller than this value, |
| 8050 | we always try to remove unnecessary ivs from the set during its |
| 8051 | optimization when a new iv is added to the set. |
| 8052 | .IP "\fBscev-max-expr-size\fR" 4 |
| 8053 | .IX Item "scev-max-expr-size" |
| 8054 | Bound on size of expressions used in the scalar evolutions analyzer. |
| 8055 | Large expressions slow the analyzer. |
| 8056 | .IP "\fBscev-max-expr-complexity\fR" 4 |
| 8057 | .IX Item "scev-max-expr-complexity" |
| 8058 | Bound on the complexity of the expressions in the scalar evolutions analyzer. |
| 8059 | Complex expressions slow the analyzer. |
| 8060 | .IP "\fBomega-max-vars\fR" 4 |
| 8061 | .IX Item "omega-max-vars" |
| 8062 | The maximum number of variables in an Omega constraint system. |
| 8063 | The default value is 128. |
| 8064 | .IP "\fBomega-max-geqs\fR" 4 |
| 8065 | .IX Item "omega-max-geqs" |
| 8066 | The maximum number of inequalities in an Omega constraint system. |
| 8067 | The default value is 256. |
| 8068 | .IP "\fBomega-max-eqs\fR" 4 |
| 8069 | .IX Item "omega-max-eqs" |
| 8070 | The maximum number of equalities in an Omega constraint system. |
| 8071 | The default value is 128. |
| 8072 | .IP "\fBomega-max-wild-cards\fR" 4 |
| 8073 | .IX Item "omega-max-wild-cards" |
| 8074 | The maximum number of wildcard variables that the Omega solver will |
| 8075 | be able to insert. The default value is 18. |
| 8076 | .IP "\fBomega-hash-table-size\fR" 4 |
| 8077 | .IX Item "omega-hash-table-size" |
| 8078 | The size of the hash table in the Omega solver. The default value is |
| 8079 | 550. |
| 8080 | .IP "\fBomega-max-keys\fR" 4 |
| 8081 | .IX Item "omega-max-keys" |
| 8082 | The maximal number of keys used by the Omega solver. The default |
| 8083 | value is 500. |
| 8084 | .IP "\fBomega-eliminate-redundant-constraints\fR" 4 |
| 8085 | .IX Item "omega-eliminate-redundant-constraints" |
| 8086 | When set to 1, use expensive methods to eliminate all redundant |
| 8087 | constraints. The default value is 0. |
| 8088 | .IP "\fBvect-max-version-for-alignment-checks\fR" 4 |
| 8089 | .IX Item "vect-max-version-for-alignment-checks" |
| 8090 | The maximum number of run-time checks that can be performed when |
| 8091 | doing loop versioning for alignment in the vectorizer. See option |
| 8092 | ftree-vect-loop-version for more information. |
| 8093 | .IP "\fBvect-max-version-for-alias-checks\fR" 4 |
| 8094 | .IX Item "vect-max-version-for-alias-checks" |
| 8095 | The maximum number of run-time checks that can be performed when |
| 8096 | doing loop versioning for alias in the vectorizer. See option |
| 8097 | ftree-vect-loop-version for more information. |
| 8098 | .IP "\fBmax-iterations-to-track\fR" 4 |
| 8099 | .IX Item "max-iterations-to-track" |
| 8100 | The maximum number of iterations of a loop the brute force algorithm |
| 8101 | for analysis of # of iterations of the loop tries to evaluate. |
| 8102 | .IP "\fBhot-bb-count-fraction\fR" 4 |
| 8103 | .IX Item "hot-bb-count-fraction" |
| 8104 | Select fraction of the maximal count of repetitions of basic block in program |
| 8105 | given basic block needs to have to be considered hot. |
| 8106 | .IP "\fBhot-bb-frequency-fraction\fR" 4 |
| 8107 | .IX Item "hot-bb-frequency-fraction" |
| 8108 | Select fraction of the entry block frequency of executions of basic block in |
| 8109 | function given basic block needs to have to be considered hot. |
| 8110 | .IP "\fBmax-predicted-iterations\fR" 4 |
| 8111 | .IX Item "max-predicted-iterations" |
| 8112 | The maximum number of loop iterations we predict statically. This is useful |
| 8113 | in cases where function contain single loop with known bound and other loop |
| 8114 | with unknown. We predict the known number of iterations correctly, while |
| 8115 | the unknown number of iterations average to roughly 10. This means that the |
| 8116 | loop without bounds would appear artificially cold relative to the other one. |
| 8117 | .IP "\fBalign-threshold\fR" 4 |
| 8118 | .IX Item "align-threshold" |
| 8119 | Select fraction of the maximal frequency of executions of basic block in |
| 8120 | function given basic block will get aligned. |
| 8121 | .IP "\fBalign-loop-iterations\fR" 4 |
| 8122 | .IX Item "align-loop-iterations" |
| 8123 | A loop expected to iterate at lest the selected number of iterations will get |
| 8124 | aligned. |
| 8125 | .IP "\fBtracer-dynamic-coverage\fR" 4 |
| 8126 | .IX Item "tracer-dynamic-coverage" |
| 8127 | .PD 0 |
| 8128 | .IP "\fBtracer-dynamic-coverage-feedback\fR" 4 |
| 8129 | .IX Item "tracer-dynamic-coverage-feedback" |
| 8130 | .PD |
| 8131 | This value is used to limit superblock formation once the given percentage of |
| 8132 | executed instructions is covered. This limits unnecessary code size |
| 8133 | expansion. |
| 8134 | .Sp |
| 8135 | The \fBtracer-dynamic-coverage-feedback\fR is used only when profile |
| 8136 | feedback is available. The real profiles (as opposed to statically estimated |
| 8137 | ones) are much less balanced allowing the threshold to be larger value. |
| 8138 | .IP "\fBtracer-max-code-growth\fR" 4 |
| 8139 | .IX Item "tracer-max-code-growth" |
| 8140 | Stop tail duplication once code growth has reached given percentage. This is |
| 8141 | rather hokey argument, as most of the duplicates will be eliminated later in |
| 8142 | cross jumping, so it may be set to much higher values than is the desired code |
| 8143 | growth. |
| 8144 | .IP "\fBtracer-min-branch-ratio\fR" 4 |
| 8145 | .IX Item "tracer-min-branch-ratio" |
| 8146 | Stop reverse growth when the reverse probability of best edge is less than this |
| 8147 | threshold (in percent). |
| 8148 | .IP "\fBtracer-min-branch-ratio\fR" 4 |
| 8149 | .IX Item "tracer-min-branch-ratio" |
| 8150 | .PD 0 |
| 8151 | .IP "\fBtracer-min-branch-ratio-feedback\fR" 4 |
| 8152 | .IX Item "tracer-min-branch-ratio-feedback" |
| 8153 | .PD |
| 8154 | Stop forward growth if the best edge do have probability lower than this |
| 8155 | threshold. |
| 8156 | .Sp |
| 8157 | Similarly to \fBtracer-dynamic-coverage\fR two values are present, one for |
| 8158 | compilation for profile feedback and one for compilation without. The value |
| 8159 | for compilation with profile feedback needs to be more conservative (higher) in |
| 8160 | order to make tracer effective. |
| 8161 | .IP "\fBmax-cse-path-length\fR" 4 |
| 8162 | .IX Item "max-cse-path-length" |
| 8163 | Maximum number of basic blocks on path that cse considers. The default is 10. |
| 8164 | .IP "\fBmax-cse-insns\fR" 4 |
| 8165 | .IX Item "max-cse-insns" |
| 8166 | The maximum instructions \s-1CSE\s0 process before flushing. The default is 1000. |
| 8167 | .IP "\fBggc-min-expand\fR" 4 |
| 8168 | .IX Item "ggc-min-expand" |
| 8169 | \&\s-1GCC\s0 uses a garbage collector to manage its own memory allocation. This |
| 8170 | parameter specifies the minimum percentage by which the garbage |
| 8171 | collector's heap should be allowed to expand between collections. |
| 8172 | Tuning this may improve compilation speed; it has no effect on code |
| 8173 | generation. |
| 8174 | .Sp |
| 8175 | The default is 30% + 70% * (\s-1RAM/1GB\s0) with an upper bound of 100% when |
| 8176 | \&\s-1RAM\s0 >= 1GB. If \f(CW\*(C`getrlimit\*(C'\fR is available, the notion of \*(L"\s-1RAM\s0\*(R" is |
| 8177 | the smallest of actual \s-1RAM\s0 and \f(CW\*(C`RLIMIT_DATA\*(C'\fR or \f(CW\*(C`RLIMIT_AS\*(C'\fR. If |
| 8178 | \&\s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a particular platform, the lower |
| 8179 | bound of 30% is used. Setting this parameter and |
| 8180 | \&\fBggc-min-heapsize\fR to zero causes a full collection to occur at |
| 8181 | every opportunity. This is extremely slow, but can be useful for |
| 8182 | debugging. |
| 8183 | .IP "\fBggc-min-heapsize\fR" 4 |
| 8184 | .IX Item "ggc-min-heapsize" |
| 8185 | Minimum size of the garbage collector's heap before it begins bothering |
| 8186 | to collect garbage. The first collection occurs after the heap expands |
| 8187 | by \fBggc-min-expand\fR% beyond \fBggc-min-heapsize\fR. Again, |
| 8188 | tuning this may improve compilation speed, and has no effect on code |
| 8189 | generation. |
| 8190 | .Sp |
| 8191 | The default is the smaller of \s-1RAM/8\s0, \s-1RLIMIT_RSS\s0, or a limit that |
| 8192 | tries to ensure that \s-1RLIMIT_DATA\s0 or \s-1RLIMIT_AS\s0 are not exceeded, but |
| 8193 | with a lower bound of 4096 (four megabytes) and an upper bound of |
| 8194 | 131072 (128 megabytes). If \s-1GCC\s0 is not able to calculate \s-1RAM\s0 on a |
| 8195 | particular platform, the lower bound is used. Setting this parameter |
| 8196 | very large effectively disables garbage collection. Setting this |
| 8197 | parameter and \fBggc-min-expand\fR to zero causes a full collection |
| 8198 | to occur at every opportunity. |
| 8199 | .IP "\fBmax-reload-search-insns\fR" 4 |
| 8200 | .IX Item "max-reload-search-insns" |
| 8201 | The maximum number of instruction reload should look backward for equivalent |
| 8202 | register. Increasing values mean more aggressive optimization, making the |
| 8203 | compilation time increase with probably slightly better performance. |
| 8204 | The default value is 100. |
| 8205 | .IP "\fBmax-cselib-memory-locations\fR" 4 |
| 8206 | .IX Item "max-cselib-memory-locations" |
| 8207 | The maximum number of memory locations cselib should take into account. |
| 8208 | Increasing values mean more aggressive optimization, making the compilation time |
| 8209 | increase with probably slightly better performance. The default value is 500. |
| 8210 | .IP "\fBreorder-blocks-duplicate\fR" 4 |
| 8211 | .IX Item "reorder-blocks-duplicate" |
| 8212 | .PD 0 |
| 8213 | .IP "\fBreorder-blocks-duplicate-feedback\fR" 4 |
| 8214 | .IX Item "reorder-blocks-duplicate-feedback" |
| 8215 | .PD |
| 8216 | Used by basic block reordering pass to decide whether to use unconditional |
| 8217 | branch or duplicate the code on its destination. Code is duplicated when its |
| 8218 | estimated size is smaller than this value multiplied by the estimated size of |
| 8219 | unconditional jump in the hot spots of the program. |
| 8220 | .Sp |
| 8221 | The \fBreorder-block-duplicate-feedback\fR is used only when profile |
| 8222 | feedback is available and may be set to higher values than |
| 8223 | \&\fBreorder-block-duplicate\fR since information about the hot spots is more |
| 8224 | accurate. |
| 8225 | .IP "\fBmax-sched-ready-insns\fR" 4 |
| 8226 | .IX Item "max-sched-ready-insns" |
| 8227 | The maximum number of instructions ready to be issued the scheduler should |
| 8228 | consider at any given time during the first scheduling pass. Increasing |
| 8229 | values mean more thorough searches, making the compilation time increase |
| 8230 | with probably little benefit. The default value is 100. |
| 8231 | .IP "\fBmax-sched-region-blocks\fR" 4 |
| 8232 | .IX Item "max-sched-region-blocks" |
| 8233 | The maximum number of blocks in a region to be considered for |
| 8234 | interblock scheduling. The default value is 10. |
| 8235 | .IP "\fBmax-pipeline-region-blocks\fR" 4 |
| 8236 | .IX Item "max-pipeline-region-blocks" |
| 8237 | The maximum number of blocks in a region to be considered for |
| 8238 | pipelining in the selective scheduler. The default value is 15. |
| 8239 | .IP "\fBmax-sched-region-insns\fR" 4 |
| 8240 | .IX Item "max-sched-region-insns" |
| 8241 | The maximum number of insns in a region to be considered for |
| 8242 | interblock scheduling. The default value is 100. |
| 8243 | .IP "\fBmax-pipeline-region-insns\fR" 4 |
| 8244 | .IX Item "max-pipeline-region-insns" |
| 8245 | The maximum number of insns in a region to be considered for |
| 8246 | pipelining in the selective scheduler. The default value is 200. |
| 8247 | .IP "\fBmin-spec-prob\fR" 4 |
| 8248 | .IX Item "min-spec-prob" |
| 8249 | The minimum probability (in percents) of reaching a source block |
| 8250 | for interblock speculative scheduling. The default value is 40. |
| 8251 | .IP "\fBmax-sched-extend-regions-iters\fR" 4 |
| 8252 | .IX Item "max-sched-extend-regions-iters" |
| 8253 | The maximum number of iterations through \s-1CFG\s0 to extend regions. |
| 8254 | 0 \- disable region extension, |
| 8255 | N \- do at most N iterations. |
| 8256 | The default value is 0. |
| 8257 | .IP "\fBmax-sched-insn-conflict-delay\fR" 4 |
| 8258 | .IX Item "max-sched-insn-conflict-delay" |
| 8259 | The maximum conflict delay for an insn to be considered for speculative motion. |
| 8260 | The default value is 3. |
| 8261 | .IP "\fBsched-spec-prob-cutoff\fR" 4 |
| 8262 | .IX Item "sched-spec-prob-cutoff" |
| 8263 | The minimal probability of speculation success (in percents), so that |
| 8264 | speculative insn will be scheduled. |
| 8265 | The default value is 40. |
| 8266 | .IP "\fBsched-mem-true-dep-cost\fR" 4 |
| 8267 | .IX Item "sched-mem-true-dep-cost" |
| 8268 | Minimal distance (in \s-1CPU\s0 cycles) between store and load targeting same |
| 8269 | memory locations. The default value is 1. |
| 8270 | .IP "\fBselsched-max-lookahead\fR" 4 |
| 8271 | .IX Item "selsched-max-lookahead" |
| 8272 | The maximum size of the lookahead window of selective scheduling. It is a |
| 8273 | depth of search for available instructions. |
| 8274 | The default value is 50. |
| 8275 | .IP "\fBselsched-max-sched-times\fR" 4 |
| 8276 | .IX Item "selsched-max-sched-times" |
| 8277 | The maximum number of times that an instruction will be scheduled during |
| 8278 | selective scheduling. This is the limit on the number of iterations |
| 8279 | through which the instruction may be pipelined. The default value is 2. |
| 8280 | .IP "\fBselsched-max-insns-to-rename\fR" 4 |
| 8281 | .IX Item "selsched-max-insns-to-rename" |
| 8282 | The maximum number of best instructions in the ready list that are considered |
| 8283 | for renaming in the selective scheduler. The default value is 2. |
| 8284 | .IP "\fBsms-min-sc\fR" 4 |
| 8285 | .IX Item "sms-min-sc" |
| 8286 | The minimum value of stage count that swing modulo scheduler will |
| 8287 | generate. The default value is 2. |
| 8288 | .IP "\fBmax-last-value-rtl\fR" 4 |
| 8289 | .IX Item "max-last-value-rtl" |
| 8290 | The maximum size measured as number of RTLs that can be recorded in an expression |
| 8291 | in combiner for a pseudo register as last known value of that register. The default |
| 8292 | is 10000. |
| 8293 | .IP "\fBinteger-share-limit\fR" 4 |
| 8294 | .IX Item "integer-share-limit" |
| 8295 | Small integer constants can use a shared data structure, reducing the |
| 8296 | compiler's memory usage and increasing its speed. This sets the maximum |
| 8297 | value of a shared integer constant. The default value is 256. |
| 8298 | .IP "\fBmin-virtual-mappings\fR" 4 |
| 8299 | .IX Item "min-virtual-mappings" |
| 8300 | Specifies the minimum number of virtual mappings in the incremental |
| 8301 | \&\s-1SSA\s0 updater that should be registered to trigger the virtual mappings |
| 8302 | heuristic defined by virtual-mappings-ratio. The default value is |
| 8303 | 100. |
| 8304 | .IP "\fBvirtual-mappings-ratio\fR" 4 |
| 8305 | .IX Item "virtual-mappings-ratio" |
| 8306 | If the number of virtual mappings is virtual-mappings-ratio bigger |
| 8307 | than the number of virtual symbols to be updated, then the incremental |
| 8308 | \&\s-1SSA\s0 updater switches to a full update for those symbols. The default |
| 8309 | ratio is 3. |
| 8310 | .IP "\fBssp-buffer-size\fR" 4 |
| 8311 | .IX Item "ssp-buffer-size" |
| 8312 | The minimum size of buffers (i.e. arrays) that will receive stack smashing |
| 8313 | protection when \fB\-fstack\-protection\fR is used. |
| 8314 | .IP "\fBmax-jump-thread-duplication-stmts\fR" 4 |
| 8315 | .IX Item "max-jump-thread-duplication-stmts" |
| 8316 | Maximum number of statements allowed in a block that needs to be |
| 8317 | duplicated when threading jumps. |
| 8318 | .IP "\fBmax-fields-for-field-sensitive\fR" 4 |
| 8319 | .IX Item "max-fields-for-field-sensitive" |
| 8320 | Maximum number of fields in a structure we will treat in |
| 8321 | a field sensitive manner during pointer analysis. The default is zero |
| 8322 | for \-O0, and \-O1 and 100 for \-Os, \-O2, and \-O3. |
| 8323 | .IP "\fBprefetch-latency\fR" 4 |
| 8324 | .IX Item "prefetch-latency" |
| 8325 | Estimate on average number of instructions that are executed before |
| 8326 | prefetch finishes. The distance we prefetch ahead is proportional |
| 8327 | to this constant. Increasing this number may also lead to less |
| 8328 | streams being prefetched (see \fBsimultaneous-prefetches\fR). |
| 8329 | .IP "\fBsimultaneous-prefetches\fR" 4 |
| 8330 | .IX Item "simultaneous-prefetches" |
| 8331 | Maximum number of prefetches that can run at the same time. |
| 8332 | .IP "\fBl1\-cache\-line\-size\fR" 4 |
| 8333 | .IX Item "l1-cache-line-size" |
| 8334 | The size of cache line in L1 cache, in bytes. |
| 8335 | .IP "\fBl1\-cache\-size\fR" 4 |
| 8336 | .IX Item "l1-cache-size" |
| 8337 | The size of L1 cache, in kilobytes. |
| 8338 | .IP "\fBl2\-cache\-size\fR" 4 |
| 8339 | .IX Item "l2-cache-size" |
| 8340 | The size of L2 cache, in kilobytes. |
| 8341 | .IP "\fBmin-insn-to-prefetch-ratio\fR" 4 |
| 8342 | .IX Item "min-insn-to-prefetch-ratio" |
| 8343 | The minimum ratio between the number of instructions and the |
| 8344 | number of prefetches to enable prefetching in a loop. |
| 8345 | .IP "\fBprefetch-min-insn-to-mem-ratio\fR" 4 |
| 8346 | .IX Item "prefetch-min-insn-to-mem-ratio" |
| 8347 | The minimum ratio between the number of instructions and the |
| 8348 | number of memory references to enable prefetching in a loop. |
| 8349 | .IP "\fBuse-canonical-types\fR" 4 |
| 8350 | .IX Item "use-canonical-types" |
| 8351 | Whether the compiler should use the \*(L"canonical\*(R" type system. By |
| 8352 | default, this should always be 1, which uses a more efficient internal |
| 8353 | mechanism for comparing types in \*(C+ and Objective\-\*(C+. However, if |
| 8354 | bugs in the canonical type system are causing compilation failures, |
| 8355 | set this value to 0 to disable canonical types. |
| 8356 | .IP "\fBswitch-conversion-max-branch-ratio\fR" 4 |
| 8357 | .IX Item "switch-conversion-max-branch-ratio" |
| 8358 | Switch initialization conversion will refuse to create arrays that are |
| 8359 | bigger than \fBswitch-conversion-max-branch-ratio\fR times the number of |
| 8360 | branches in the switch. |
| 8361 | .IP "\fBmax-partial-antic-length\fR" 4 |
| 8362 | .IX Item "max-partial-antic-length" |
| 8363 | Maximum length of the partial antic set computed during the tree |
| 8364 | partial redundancy elimination optimization (\fB\-ftree\-pre\fR) when |
| 8365 | optimizing at \fB\-O3\fR and above. For some sorts of source code |
| 8366 | the enhanced partial redundancy elimination optimization can run away, |
| 8367 | consuming all of the memory available on the host machine. This |
| 8368 | parameter sets a limit on the length of the sets that are computed, |
| 8369 | which prevents the runaway behavior. Setting a value of 0 for |
| 8370 | this parameter will allow an unlimited set length. |
| 8371 | .IP "\fBsccvn-max-scc-size\fR" 4 |
| 8372 | .IX Item "sccvn-max-scc-size" |
| 8373 | Maximum size of a strongly connected component (\s-1SCC\s0) during \s-1SCCVN\s0 |
| 8374 | processing. If this limit is hit, \s-1SCCVN\s0 processing for the whole |
| 8375 | function will not be done and optimizations depending on it will |
| 8376 | be disabled. The default maximum \s-1SCC\s0 size is 10000. |
| 8377 | .IP "\fBira-max-loops-num\fR" 4 |
| 8378 | .IX Item "ira-max-loops-num" |
| 8379 | \&\s-1IRA\s0 uses regional register allocation by default. If a function |
| 8380 | contains more loops than the number given by this parameter, only at most |
| 8381 | the given number of the most frequently-executed loops form regions |
| 8382 | for regional register allocation. The default value of the |
| 8383 | parameter is 100. |
| 8384 | .IP "\fBira-max-conflict-table-size\fR" 4 |
| 8385 | .IX Item "ira-max-conflict-table-size" |
| 8386 | Although \s-1IRA\s0 uses a sophisticated algorithm to compress the conflict |
| 8387 | table, the table can still require excessive amounts of memory for |
| 8388 | huge functions. If the conflict table for a function could be more |
| 8389 | than the size in \s-1MB\s0 given by this parameter, the register allocator |
| 8390 | instead uses a faster, simpler, and lower-quality |
| 8391 | algorithm that does not require building a pseudo-register conflict table. |
| 8392 | The default value of the parameter is 2000. |
| 8393 | .IP "\fBira-loop-reserved-regs\fR" 4 |
| 8394 | .IX Item "ira-loop-reserved-regs" |
| 8395 | \&\s-1IRA\s0 can be used to evaluate more accurate register pressure in loops |
| 8396 | for decisions to move loop invariants (see \fB\-O3\fR). The number |
| 8397 | of available registers reserved for some other purposes is given |
| 8398 | by this parameter. The default value of the parameter is 2, which is |
| 8399 | the minimal number of registers needed by typical instructions. |
| 8400 | This value is the best found from numerous experiments. |
| 8401 | .IP "\fBloop-invariant-max-bbs-in-loop\fR" 4 |
| 8402 | .IX Item "loop-invariant-max-bbs-in-loop" |
| 8403 | Loop invariant motion can be very expensive, both in compilation time and |
| 8404 | in amount of needed compile-time memory, with very large loops. Loops |
| 8405 | with more basic blocks than this parameter won't have loop invariant |
| 8406 | motion optimization performed on them. The default value of the |
| 8407 | parameter is 1000 for \-O1 and 10000 for \-O2 and above. |
| 8408 | .IP "\fBloop-max-datarefs-for-datadeps\fR" 4 |
| 8409 | .IX Item "loop-max-datarefs-for-datadeps" |
| 8410 | Building data dapendencies is expensive for very large loops. This |
| 8411 | parameter limits the number of data references in loops that are |
| 8412 | considered for data dependence analysis. These large loops will not |
| 8413 | be handled then by the optimizations using loop data dependencies. |
| 8414 | The default value is 1000. |
| 8415 | .IP "\fBmax-vartrack-size\fR" 4 |
| 8416 | .IX Item "max-vartrack-size" |
| 8417 | Sets a maximum number of hash table slots to use during variable |
| 8418 | tracking dataflow analysis of any function. If this limit is exceeded |
| 8419 | with variable tracking at assignments enabled, analysis for that |
| 8420 | function is retried without it, after removing all debug insns from |
| 8421 | the function. If the limit is exceeded even without debug insns, var |
| 8422 | tracking analysis is completely disabled for the function. Setting |
| 8423 | the parameter to zero makes it unlimited. |
| 8424 | .IP "\fBmax-vartrack-expr-depth\fR" 4 |
| 8425 | .IX Item "max-vartrack-expr-depth" |
| 8426 | Sets a maximum number of recursion levels when attempting to map |
| 8427 | variable names or debug temporaries to value expressions. This trades |
| 8428 | compilation time for more complete debug information. If this is set too |
| 8429 | low, value expressions that are available and could be represented in |
| 8430 | debug information may end up not being used; setting this higher may |
| 8431 | enable the compiler to find more complex debug expressions, but compile |
| 8432 | time and memory use may grow. The default is 12. |
| 8433 | .IP "\fBmin-nondebug-insn-uid\fR" 4 |
| 8434 | .IX Item "min-nondebug-insn-uid" |
| 8435 | Use uids starting at this parameter for nondebug insns. The range below |
| 8436 | the parameter is reserved exclusively for debug insns created by |
| 8437 | \&\fB\-fvar\-tracking\-assignments\fR, but debug insns may get |
| 8438 | (non-overlapping) uids above it if the reserved range is exhausted. |
| 8439 | .IP "\fBipa-sra-ptr-growth-factor\fR" 4 |
| 8440 | .IX Item "ipa-sra-ptr-growth-factor" |
| 8441 | IPA-SRA will replace a pointer to an aggregate with one or more new |
| 8442 | parameters only when their cumulative size is less or equal to |
| 8443 | \&\fBipa-sra-ptr-growth-factor\fR times the size of the original |
| 8444 | pointer parameter. |
| 8445 | .IP "\fBtm-max-aggregate-size\fR" 4 |
| 8446 | .IX Item "tm-max-aggregate-size" |
| 8447 | When making copies of thread-local variables in a transaction, this |
| 8448 | parameter specifies the size in bytes after which variables will be |
| 8449 | saved with the logging functions as opposed to save/restore code |
| 8450 | sequence pairs. This option only applies when using |
| 8451 | \&\fB\-fgnu\-tm\fR. |
| 8452 | .IP "\fBgraphite-max-nb-scop-params\fR" 4 |
| 8453 | .IX Item "graphite-max-nb-scop-params" |
| 8454 | To avoid exponential effects in the Graphite loop transforms, the |
| 8455 | number of parameters in a Static Control Part (SCoP) is bounded. The |
| 8456 | default value is 10 parameters. A variable whose value is unknown at |
| 8457 | compilation time and defined outside a SCoP is a parameter of the SCoP. |
| 8458 | .IP "\fBgraphite-max-bbs-per-function\fR" 4 |
| 8459 | .IX Item "graphite-max-bbs-per-function" |
| 8460 | To avoid exponential effects in the detection of SCoPs, the size of |
| 8461 | the functions analyzed by Graphite is bounded. The default value is |
| 8462 | 100 basic blocks. |
| 8463 | .IP "\fBloop-block-tile-size\fR" 4 |
| 8464 | .IX Item "loop-block-tile-size" |
| 8465 | Loop blocking or strip mining transforms, enabled with |
| 8466 | \&\fB\-floop\-block\fR or \fB\-floop\-strip\-mine\fR, strip mine each |
| 8467 | loop in the loop nest by a given number of iterations. The strip |
| 8468 | length can be changed using the \fBloop-block-tile-size\fR |
| 8469 | parameter. The default value is 51 iterations. |
| 8470 | .IP "\fBipa-cp-value-list-size\fR" 4 |
| 8471 | .IX Item "ipa-cp-value-list-size" |
| 8472 | IPA-CP attempts to track all possible values and types passed to a function's |
| 8473 | parameter in order to propagate them and perform devirtualization. |
| 8474 | \&\fBipa-cp-value-list-size\fR is the maximum number of values and types it |
| 8475 | stores per one formal parameter of a function. |
| 8476 | .IP "\fBlto-partitions\fR" 4 |
| 8477 | .IX Item "lto-partitions" |
| 8478 | Specify desired number of partitions produced during \s-1WHOPR\s0 compilation. |
| 8479 | The number of partitions should exceed the number of CPUs used for compilation. |
| 8480 | The default value is 32. |
| 8481 | .IP "\fBlto-minpartition\fR" 4 |
| 8482 | .IX Item "lto-minpartition" |
| 8483 | Size of minimal partition for \s-1WHOPR\s0 (in estimated instructions). |
| 8484 | This prevents expenses of splitting very small programs into too many |
| 8485 | partitions. |
| 8486 | .IP "\fBcxx-max-namespaces-for-diagnostic-help\fR" 4 |
| 8487 | .IX Item "cxx-max-namespaces-for-diagnostic-help" |
| 8488 | The maximum number of namespaces to consult for suggestions when \*(C+ |
| 8489 | name lookup fails for an identifier. The default is 1000. |
| 8490 | .IP "\fBsink-frequency-threshold\fR" 4 |
| 8491 | .IX Item "sink-frequency-threshold" |
| 8492 | The maximum relative execution frequency (in percents) of the target block |
| 8493 | relative to a statement's original block to allow statement sinking of a |
| 8494 | statement. Larger numbers result in more aggressive statement sinking. |
| 8495 | The default value is 75. A small positive adjustment is applied for |
| 8496 | statements with memory operands as those are even more profitable so sink. |
| 8497 | .IP "\fBmax-stores-to-sink\fR" 4 |
| 8498 | .IX Item "max-stores-to-sink" |
| 8499 | The maximum number of conditional stores paires that can be sunk. Set to 0 |
| 8500 | if either vectorization (\fB\-ftree\-vectorize\fR) or if-conversion |
| 8501 | (\fB\-ftree\-loop\-if\-convert\fR) is disabled. The default is 2. |
| 8502 | .IP "\fBallow-load-data-races\fR" 4 |
| 8503 | .IX Item "allow-load-data-races" |
| 8504 | Allow optimizers to introduce new data races on loads. |
| 8505 | Set to 1 to allow, otherwise to 0. This option is enabled by default |
| 8506 | unless implicitly set by the \fB\-fmemory\-model=\fR option. |
| 8507 | .IP "\fBallow-store-data-races\fR" 4 |
| 8508 | .IX Item "allow-store-data-races" |
| 8509 | Allow optimizers to introduce new data races on stores. |
| 8510 | Set to 1 to allow, otherwise to 0. This option is enabled by default |
| 8511 | unless implicitly set by the \fB\-fmemory\-model=\fR option. |
| 8512 | .IP "\fBallow-packed-load-data-races\fR" 4 |
| 8513 | .IX Item "allow-packed-load-data-races" |
| 8514 | Allow optimizers to introduce new data races on packed data loads. |
| 8515 | Set to 1 to allow, otherwise to 0. This option is enabled by default |
| 8516 | unless implicitly set by the \fB\-fmemory\-model=\fR option. |
| 8517 | .IP "\fBallow-packed-store-data-races\fR" 4 |
| 8518 | .IX Item "allow-packed-store-data-races" |
| 8519 | Allow optimizers to introduce new data races on packed data stores. |
| 8520 | Set to 1 to allow, otherwise to 0. This option is enabled by default |
| 8521 | unless implicitly set by the \fB\-fmemory\-model=\fR option. |
| 8522 | .IP "\fBcase-values-threshold\fR" 4 |
| 8523 | .IX Item "case-values-threshold" |
| 8524 | The smallest number of different values for which it is best to use a |
| 8525 | jump-table instead of a tree of conditional branches. If the value is |
| 8526 | 0, use the default for the machine. The default is 0. |
| 8527 | .IP "\fBtree-reassoc-width\fR" 4 |
| 8528 | .IX Item "tree-reassoc-width" |
| 8529 | Set the maximum number of instructions executed in parallel in |
| 8530 | reassociated tree. This parameter overrides target dependent |
| 8531 | heuristics used by default if has non zero value. |
| 8532 | .RE |
| 8533 | .RS 4 |
| 8534 | .RE |
| 8535 | .Sh "Options Controlling the Preprocessor" |
| 8536 | .IX Subsection "Options Controlling the Preprocessor" |
| 8537 | These options control the C preprocessor, which is run on each C source |
| 8538 | file before actual compilation. |
| 8539 | .PP |
| 8540 | If you use the \fB\-E\fR option, nothing is done except preprocessing. |
| 8541 | Some of these options make sense only together with \fB\-E\fR because |
| 8542 | they cause the preprocessor output to be unsuitable for actual |
| 8543 | compilation. |
| 8544 | .IP "\fB\-Wp,\fR\fIoption\fR" 4 |
| 8545 | .IX Item "-Wp,option" |
| 8546 | You can use \fB\-Wp,\fR\fIoption\fR to bypass the compiler driver |
| 8547 | and pass \fIoption\fR directly through to the preprocessor. If |
| 8548 | \&\fIoption\fR contains commas, it is split into multiple options at the |
| 8549 | commas. However, many options are modified, translated or interpreted |
| 8550 | by the compiler driver before being passed to the preprocessor, and |
| 8551 | \&\fB\-Wp\fR forcibly bypasses this phase. The preprocessor's direct |
| 8552 | interface is undocumented and subject to change, so whenever possible |
| 8553 | you should avoid using \fB\-Wp\fR and let the driver handle the |
| 8554 | options instead. |
| 8555 | .IP "\fB\-Xpreprocessor\fR \fIoption\fR" 4 |
| 8556 | .IX Item "-Xpreprocessor option" |
| 8557 | Pass \fIoption\fR as an option to the preprocessor. You can use this to |
| 8558 | supply system-specific preprocessor options that \s-1GCC\s0 does not know how to |
| 8559 | recognize. |
| 8560 | .Sp |
| 8561 | If you want to pass an option that takes an argument, you must use |
| 8562 | \&\fB\-Xpreprocessor\fR twice, once for the option and once for the argument. |
| 8563 | .IP "\fB\-D\fR \fIname\fR" 4 |
| 8564 | .IX Item "-D name" |
| 8565 | Predefine \fIname\fR as a macro, with definition \f(CW1\fR. |
| 8566 | .IP "\fB\-D\fR \fIname\fR\fB=\fR\fIdefinition\fR" 4 |
| 8567 | .IX Item "-D name=definition" |
| 8568 | The contents of \fIdefinition\fR are tokenized and processed as if |
| 8569 | they appeared during translation phase three in a \fB#define\fR |
| 8570 | directive. In particular, the definition will be truncated by |
| 8571 | embedded newline characters. |
| 8572 | .Sp |
| 8573 | If you are invoking the preprocessor from a shell or shell-like |
| 8574 | program you may need to use the shell's quoting syntax to protect |
| 8575 | characters such as spaces that have a meaning in the shell syntax. |
| 8576 | .Sp |
| 8577 | If you wish to define a function-like macro on the command line, write |
| 8578 | its argument list with surrounding parentheses before the equals sign |
| 8579 | (if any). Parentheses are meaningful to most shells, so you will need |
| 8580 | to quote the option. With \fBsh\fR and \fBcsh\fR, |
| 8581 | \&\fB\-D'\fR\fIname\fR\fB(\fR\fIargs...\fR\fB)=\fR\fIdefinition\fR\fB'\fR works. |
| 8582 | .Sp |
| 8583 | \&\fB\-D\fR and \fB\-U\fR options are processed in the order they |
| 8584 | are given on the command line. All \fB\-imacros\fR \fIfile\fR and |
| 8585 | \&\fB\-include\fR \fIfile\fR options are processed after all |
| 8586 | \&\fB\-D\fR and \fB\-U\fR options. |
| 8587 | .IP "\fB\-U\fR \fIname\fR" 4 |
| 8588 | .IX Item "-U name" |
| 8589 | Cancel any previous definition of \fIname\fR, either built in or |
| 8590 | provided with a \fB\-D\fR option. |
| 8591 | .IP "\fB\-undef\fR" 4 |
| 8592 | .IX Item "-undef" |
| 8593 | Do not predefine any system-specific or GCC-specific macros. The |
| 8594 | standard predefined macros remain defined. |
| 8595 | .IP "\fB\-I\fR \fIdir\fR" 4 |
| 8596 | .IX Item "-I dir" |
| 8597 | Add the directory \fIdir\fR to the list of directories to be searched |
| 8598 | for header files. |
| 8599 | Directories named by \fB\-I\fR are searched before the standard |
| 8600 | system include directories. If the directory \fIdir\fR is a standard |
| 8601 | system include directory, the option is ignored to ensure that the |
| 8602 | default search order for system directories and the special treatment |
| 8603 | of system headers are not defeated |
| 8604 | \&. |
| 8605 | If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced |
| 8606 | by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. |
| 8607 | .IP "\fB\-o\fR \fIfile\fR" 4 |
| 8608 | .IX Item "-o file" |
| 8609 | Write output to \fIfile\fR. This is the same as specifying \fIfile\fR |
| 8610 | as the second non-option argument to \fBcpp\fR. \fBgcc\fR has a |
| 8611 | different interpretation of a second non-option argument, so you must |
| 8612 | use \fB\-o\fR to specify the output file. |
| 8613 | .IP "\fB\-Wall\fR" 4 |
| 8614 | .IX Item "-Wall" |
| 8615 | Turns on all optional warnings which are desirable for normal code. |
| 8616 | At present this is \fB\-Wcomment\fR, \fB\-Wtrigraphs\fR, |
| 8617 | \&\fB\-Wmultichar\fR and a warning about integer promotion causing a |
| 8618 | change of sign in \f(CW\*(C`#if\*(C'\fR expressions. Note that many of the |
| 8619 | preprocessor's warnings are on by default and have no options to |
| 8620 | control them. |
| 8621 | .IP "\fB\-Wcomment\fR" 4 |
| 8622 | .IX Item "-Wcomment" |
| 8623 | .PD 0 |
| 8624 | .IP "\fB\-Wcomments\fR" 4 |
| 8625 | .IX Item "-Wcomments" |
| 8626 | .PD |
| 8627 | Warn whenever a comment-start sequence \fB/*\fR appears in a \fB/*\fR |
| 8628 | comment, or whenever a backslash-newline appears in a \fB//\fR comment. |
| 8629 | (Both forms have the same effect.) |
| 8630 | .IP "\fB\-Wtrigraphs\fR" 4 |
| 8631 | .IX Item "-Wtrigraphs" |
| 8632 | Most trigraphs in comments cannot affect the meaning of the program. |
| 8633 | However, a trigraph that would form an escaped newline (\fB??/\fR at |
| 8634 | the end of a line) can, by changing where the comment begins or ends. |
| 8635 | Therefore, only trigraphs that would form escaped newlines produce |
| 8636 | warnings inside a comment. |
| 8637 | .Sp |
| 8638 | This option is implied by \fB\-Wall\fR. If \fB\-Wall\fR is not |
| 8639 | given, this option is still enabled unless trigraphs are enabled. To |
| 8640 | get trigraph conversion without warnings, but get the other |
| 8641 | \&\fB\-Wall\fR warnings, use \fB\-trigraphs \-Wall \-Wno\-trigraphs\fR. |
| 8642 | .IP "\fB\-Wtraditional\fR" 4 |
| 8643 | .IX Item "-Wtraditional" |
| 8644 | Warn about certain constructs that behave differently in traditional and |
| 8645 | \&\s-1ISO\s0 C. Also warn about \s-1ISO\s0 C constructs that have no traditional C |
| 8646 | equivalent, and problematic constructs which should be avoided. |
| 8647 | .IP "\fB\-Wundef\fR" 4 |
| 8648 | .IX Item "-Wundef" |
| 8649 | Warn whenever an identifier which is not a macro is encountered in an |
| 8650 | \&\fB#if\fR directive, outside of \fBdefined\fR. Such identifiers are |
| 8651 | replaced with zero. |
| 8652 | .IP "\fB\-Wunused\-macros\fR" 4 |
| 8653 | .IX Item "-Wunused-macros" |
| 8654 | Warn about macros defined in the main file that are unused. A macro |
| 8655 | is \fIused\fR if it is expanded or tested for existence at least once. |
| 8656 | The preprocessor will also warn if the macro has not been used at the |
| 8657 | time it is redefined or undefined. |
| 8658 | .Sp |
| 8659 | Built-in macros, macros defined on the command line, and macros |
| 8660 | defined in include files are not warned about. |
| 8661 | .Sp |
| 8662 | \&\fINote:\fR If a macro is actually used, but only used in skipped |
| 8663 | conditional blocks, then \s-1CPP\s0 will report it as unused. To avoid the |
| 8664 | warning in such a case, you might improve the scope of the macro's |
| 8665 | definition by, for example, moving it into the first skipped block. |
| 8666 | Alternatively, you could provide a dummy use with something like: |
| 8667 | .Sp |
| 8668 | .Vb 2 |
| 8669 | \& #if defined the_macro_causing_the_warning |
| 8670 | \& #endif |
| 8671 | .Ve |
| 8672 | .IP "\fB\-Wendif\-labels\fR" 4 |
| 8673 | .IX Item "-Wendif-labels" |
| 8674 | Warn whenever an \fB#else\fR or an \fB#endif\fR are followed by text. |
| 8675 | This usually happens in code of the form |
| 8676 | .Sp |
| 8677 | .Vb 5 |
| 8678 | \& #if FOO |
| 8679 | \& ... |
| 8680 | \& #else FOO |
| 8681 | \& ... |
| 8682 | \& #endif FOO |
| 8683 | .Ve |
| 8684 | .Sp |
| 8685 | The second and third \f(CW\*(C`FOO\*(C'\fR should be in comments, but often are not |
| 8686 | in older programs. This warning is on by default. |
| 8687 | .IP "\fB\-Werror\fR" 4 |
| 8688 | .IX Item "-Werror" |
| 8689 | Make all warnings into hard errors. Source code which triggers warnings |
| 8690 | will be rejected. |
| 8691 | .IP "\fB\-Wsystem\-headers\fR" 4 |
| 8692 | .IX Item "-Wsystem-headers" |
| 8693 | Issue warnings for code in system headers. These are normally unhelpful |
| 8694 | in finding bugs in your own code, therefore suppressed. If you are |
| 8695 | responsible for the system library, you may want to see them. |
| 8696 | .IP "\fB\-w\fR" 4 |
| 8697 | .IX Item "-w" |
| 8698 | Suppress all warnings, including those which \s-1GNU\s0 \s-1CPP\s0 issues by default. |
| 8699 | .IP "\fB\-pedantic\fR" 4 |
| 8700 | .IX Item "-pedantic" |
| 8701 | Issue all the mandatory diagnostics listed in the C standard. Some of |
| 8702 | them are left out by default, since they trigger frequently on harmless |
| 8703 | code. |
| 8704 | .IP "\fB\-pedantic\-errors\fR" 4 |
| 8705 | .IX Item "-pedantic-errors" |
| 8706 | Issue all the mandatory diagnostics, and make all mandatory diagnostics |
| 8707 | into errors. This includes mandatory diagnostics that \s-1GCC\s0 issues |
| 8708 | without \fB\-pedantic\fR but treats as warnings. |
| 8709 | .IP "\fB\-M\fR" 4 |
| 8710 | .IX Item "-M" |
| 8711 | Instead of outputting the result of preprocessing, output a rule |
| 8712 | suitable for \fBmake\fR describing the dependencies of the main |
| 8713 | source file. The preprocessor outputs one \fBmake\fR rule containing |
| 8714 | the object file name for that source file, a colon, and the names of all |
| 8715 | the included files, including those coming from \fB\-include\fR or |
| 8716 | \&\fB\-imacros\fR command line options. |
| 8717 | .Sp |
| 8718 | Unless specified explicitly (with \fB\-MT\fR or \fB\-MQ\fR), the |
| 8719 | object file name consists of the name of the source file with any |
| 8720 | suffix replaced with object file suffix and with any leading directory |
| 8721 | parts removed. If there are many included files then the rule is |
| 8722 | split into several lines using \fB\e\fR\-newline. The rule has no |
| 8723 | commands. |
| 8724 | .Sp |
| 8725 | This option does not suppress the preprocessor's debug output, such as |
| 8726 | \&\fB\-dM\fR. To avoid mixing such debug output with the dependency |
| 8727 | rules you should explicitly specify the dependency output file with |
| 8728 | \&\fB\-MF\fR, or use an environment variable like |
| 8729 | \&\fB\s-1DEPENDENCIES_OUTPUT\s0\fR. Debug output |
| 8730 | will still be sent to the regular output stream as normal. |
| 8731 | .Sp |
| 8732 | Passing \fB\-M\fR to the driver implies \fB\-E\fR, and suppresses |
| 8733 | warnings with an implicit \fB\-w\fR. |
| 8734 | .IP "\fB\-MM\fR" 4 |
| 8735 | .IX Item "-MM" |
| 8736 | Like \fB\-M\fR but do not mention header files that are found in |
| 8737 | system header directories, nor header files that are included, |
| 8738 | directly or indirectly, from such a header. |
| 8739 | .Sp |
| 8740 | This implies that the choice of angle brackets or double quotes in an |
| 8741 | \&\fB#include\fR directive does not in itself determine whether that |
| 8742 | header will appear in \fB\-MM\fR dependency output. This is a |
| 8743 | slight change in semantics from \s-1GCC\s0 versions 3.0 and earlier. |
| 8744 | .IP "\fB\-MF\fR \fIfile\fR" 4 |
| 8745 | .IX Item "-MF file" |
| 8746 | When used with \fB\-M\fR or \fB\-MM\fR, specifies a |
| 8747 | file to write the dependencies to. If no \fB\-MF\fR switch is given |
| 8748 | the preprocessor sends the rules to the same place it would have sent |
| 8749 | preprocessed output. |
| 8750 | .Sp |
| 8751 | When used with the driver options \fB\-MD\fR or \fB\-MMD\fR, |
| 8752 | \&\fB\-MF\fR overrides the default dependency output file. |
| 8753 | .IP "\fB\-MG\fR" 4 |
| 8754 | .IX Item "-MG" |
| 8755 | In conjunction with an option such as \fB\-M\fR requesting |
| 8756 | dependency generation, \fB\-MG\fR assumes missing header files are |
| 8757 | generated files and adds them to the dependency list without raising |
| 8758 | an error. The dependency filename is taken directly from the |
| 8759 | \&\f(CW\*(C`#include\*(C'\fR directive without prepending any path. \fB\-MG\fR |
| 8760 | also suppresses preprocessed output, as a missing header file renders |
| 8761 | this useless. |
| 8762 | .Sp |
| 8763 | This feature is used in automatic updating of makefiles. |
| 8764 | .IP "\fB\-MP\fR" 4 |
| 8765 | .IX Item "-MP" |
| 8766 | This option instructs \s-1CPP\s0 to add a phony target for each dependency |
| 8767 | other than the main file, causing each to depend on nothing. These |
| 8768 | dummy rules work around errors \fBmake\fR gives if you remove header |
| 8769 | files without updating the \fIMakefile\fR to match. |
| 8770 | .Sp |
| 8771 | This is typical output: |
| 8772 | .Sp |
| 8773 | .Vb 1 |
| 8774 | \& test.o: test.c test.h |
| 8775 | \& |
| 8776 | \& test.h: |
| 8777 | .Ve |
| 8778 | .IP "\fB\-MT\fR \fItarget\fR" 4 |
| 8779 | .IX Item "-MT target" |
| 8780 | Change the target of the rule emitted by dependency generation. By |
| 8781 | default \s-1CPP\s0 takes the name of the main input file, deletes any |
| 8782 | directory components and any file suffix such as \fB.c\fR, and |
| 8783 | appends the platform's usual object suffix. The result is the target. |
| 8784 | .Sp |
| 8785 | An \fB\-MT\fR option will set the target to be exactly the string you |
| 8786 | specify. If you want multiple targets, you can specify them as a single |
| 8787 | argument to \fB\-MT\fR, or use multiple \fB\-MT\fR options. |
| 8788 | .Sp |
| 8789 | For example, \fB\-MT\ '$(objpfx)foo.o'\fR might give |
| 8790 | .Sp |
| 8791 | .Vb 1 |
| 8792 | \& $(objpfx)foo.o: foo.c |
| 8793 | .Ve |
| 8794 | .IP "\fB\-MQ\fR \fItarget\fR" 4 |
| 8795 | .IX Item "-MQ target" |
| 8796 | Same as \fB\-MT\fR, but it quotes any characters which are special to |
| 8797 | Make. \fB\-MQ\ '$(objpfx)foo.o'\fR gives |
| 8798 | .Sp |
| 8799 | .Vb 1 |
| 8800 | \& $$(objpfx)foo.o: foo.c |
| 8801 | .Ve |
| 8802 | .Sp |
| 8803 | The default target is automatically quoted, as if it were given with |
| 8804 | \&\fB\-MQ\fR. |
| 8805 | .IP "\fB\-MD\fR" 4 |
| 8806 | .IX Item "-MD" |
| 8807 | \&\fB\-MD\fR is equivalent to \fB\-M \-MF\fR \fIfile\fR, except that |
| 8808 | \&\fB\-E\fR is not implied. The driver determines \fIfile\fR based on |
| 8809 | whether an \fB\-o\fR option is given. If it is, the driver uses its |
| 8810 | argument but with a suffix of \fI.d\fR, otherwise it takes the name |
| 8811 | of the input file, removes any directory components and suffix, and |
| 8812 | applies a \fI.d\fR suffix. |
| 8813 | .Sp |
| 8814 | If \fB\-MD\fR is used in conjunction with \fB\-E\fR, any |
| 8815 | \&\fB\-o\fR switch is understood to specify the dependency output file, but if used without \fB\-E\fR, each \fB\-o\fR |
| 8816 | is understood to specify a target object file. |
| 8817 | .Sp |
| 8818 | Since \fB\-E\fR is not implied, \fB\-MD\fR can be used to generate |
| 8819 | a dependency output file as a side-effect of the compilation process. |
| 8820 | .IP "\fB\-MMD\fR" 4 |
| 8821 | .IX Item "-MMD" |
| 8822 | Like \fB\-MD\fR except mention only user header files, not system |
| 8823 | header files. |
| 8824 | .IP "\fB\-fpch\-deps\fR" 4 |
| 8825 | .IX Item "-fpch-deps" |
| 8826 | When using precompiled headers, this flag |
| 8827 | will cause the dependency-output flags to also list the files from the |
| 8828 | precompiled header's dependencies. If not specified only the |
| 8829 | precompiled header would be listed and not the files that were used to |
| 8830 | create it because those files are not consulted when a precompiled |
| 8831 | header is used. |
| 8832 | .IP "\fB\-fpch\-preprocess\fR" 4 |
| 8833 | .IX Item "-fpch-preprocess" |
| 8834 | This option allows use of a precompiled header together with \fB\-E\fR. It inserts a special \f(CW\*(C`#pragma\*(C'\fR, |
| 8835 | \&\f(CW\*(C`#pragma GCC pch_preprocess "\f(CIfilename\f(CW"\*(C'\fR in the output to mark |
| 8836 | the place where the precompiled header was found, and its \fIfilename\fR. |
| 8837 | When \fB\-fpreprocessed\fR is in use, \s-1GCC\s0 recognizes this \f(CW\*(C`#pragma\*(C'\fR |
| 8838 | and loads the \s-1PCH\s0. |
| 8839 | .Sp |
| 8840 | This option is off by default, because the resulting preprocessed output |
| 8841 | is only really suitable as input to \s-1GCC\s0. It is switched on by |
| 8842 | \&\fB\-save\-temps\fR. |
| 8843 | .Sp |
| 8844 | You should not write this \f(CW\*(C`#pragma\*(C'\fR in your own code, but it is |
| 8845 | safe to edit the filename if the \s-1PCH\s0 file is available in a different |
| 8846 | location. The filename may be absolute or it may be relative to \s-1GCC\s0's |
| 8847 | current directory. |
| 8848 | .IP "\fB\-x c\fR" 4 |
| 8849 | .IX Item "-x c" |
| 8850 | .PD 0 |
| 8851 | .IP "\fB\-x c++\fR" 4 |
| 8852 | .IX Item "-x c++" |
| 8853 | .IP "\fB\-x objective-c\fR" 4 |
| 8854 | .IX Item "-x objective-c" |
| 8855 | .IP "\fB\-x assembler-with-cpp\fR" 4 |
| 8856 | .IX Item "-x assembler-with-cpp" |
| 8857 | .PD |
| 8858 | Specify the source language: C, \*(C+, Objective-C, or assembly. This has |
| 8859 | nothing to do with standards conformance or extensions; it merely |
| 8860 | selects which base syntax to expect. If you give none of these options, |
| 8861 | cpp will deduce the language from the extension of the source file: |
| 8862 | \&\fB.c\fR, \fB.cc\fR, \fB.m\fR, or \fB.S\fR. Some other common |
| 8863 | extensions for \*(C+ and assembly are also recognized. If cpp does not |
| 8864 | recognize the extension, it will treat the file as C; this is the most |
| 8865 | generic mode. |
| 8866 | .Sp |
| 8867 | \&\fINote:\fR Previous versions of cpp accepted a \fB\-lang\fR option |
| 8868 | which selected both the language and the standards conformance level. |
| 8869 | This option has been removed, because it conflicts with the \fB\-l\fR |
| 8870 | option. |
| 8871 | .IP "\fB\-std=\fR\fIstandard\fR" 4 |
| 8872 | .IX Item "-std=standard" |
| 8873 | .PD 0 |
| 8874 | .IP "\fB\-ansi\fR" 4 |
| 8875 | .IX Item "-ansi" |
| 8876 | .PD |
| 8877 | Specify the standard to which the code should conform. Currently \s-1CPP\s0 |
| 8878 | knows about C and \*(C+ standards; others may be added in the future. |
| 8879 | .Sp |
| 8880 | \&\fIstandard\fR |
| 8881 | may be one of: |
| 8882 | .RS 4 |
| 8883 | .ie n .IP """c90""" 4 |
| 8884 | .el .IP "\f(CWc90\fR" 4 |
| 8885 | .IX Item "c90" |
| 8886 | .PD 0 |
| 8887 | .ie n .IP """c89""" 4 |
| 8888 | .el .IP "\f(CWc89\fR" 4 |
| 8889 | .IX Item "c89" |
| 8890 | .ie n .IP """iso9899:1990""" 4 |
| 8891 | .el .IP "\f(CWiso9899:1990\fR" 4 |
| 8892 | .IX Item "iso9899:1990" |
| 8893 | .PD |
| 8894 | The \s-1ISO\s0 C standard from 1990. \fBc90\fR is the customary shorthand for |
| 8895 | this version of the standard. |
| 8896 | .Sp |
| 8897 | The \fB\-ansi\fR option is equivalent to \fB\-std=c90\fR. |
| 8898 | .ie n .IP """iso9899:199409""" 4 |
| 8899 | .el .IP "\f(CWiso9899:199409\fR" 4 |
| 8900 | .IX Item "iso9899:199409" |
| 8901 | The 1990 C standard, as amended in 1994. |
| 8902 | .ie n .IP """iso9899:1999""" 4 |
| 8903 | .el .IP "\f(CWiso9899:1999\fR" 4 |
| 8904 | .IX Item "iso9899:1999" |
| 8905 | .PD 0 |
| 8906 | .ie n .IP """c99""" 4 |
| 8907 | .el .IP "\f(CWc99\fR" 4 |
| 8908 | .IX Item "c99" |
| 8909 | .ie n .IP """iso9899:199x""" 4 |
| 8910 | .el .IP "\f(CWiso9899:199x\fR" 4 |
| 8911 | .IX Item "iso9899:199x" |
| 8912 | .ie n .IP """c9x""" 4 |
| 8913 | .el .IP "\f(CWc9x\fR" 4 |
| 8914 | .IX Item "c9x" |
| 8915 | .PD |
| 8916 | The revised \s-1ISO\s0 C standard, published in December 1999. Before |
| 8917 | publication, this was known as C9X. |
| 8918 | .ie n .IP """iso9899:2011""" 4 |
| 8919 | .el .IP "\f(CWiso9899:2011\fR" 4 |
| 8920 | .IX Item "iso9899:2011" |
| 8921 | .PD 0 |
| 8922 | .ie n .IP """c11""" 4 |
| 8923 | .el .IP "\f(CWc11\fR" 4 |
| 8924 | .IX Item "c11" |
| 8925 | .ie n .IP """c1x""" 4 |
| 8926 | .el .IP "\f(CWc1x\fR" 4 |
| 8927 | .IX Item "c1x" |
| 8928 | .PD |
| 8929 | The revised \s-1ISO\s0 C standard, published in December 2011. Before |
| 8930 | publication, this was known as C1X. |
| 8931 | .ie n .IP """gnu90""" 4 |
| 8932 | .el .IP "\f(CWgnu90\fR" 4 |
| 8933 | .IX Item "gnu90" |
| 8934 | .PD 0 |
| 8935 | .ie n .IP """gnu89""" 4 |
| 8936 | .el .IP "\f(CWgnu89\fR" 4 |
| 8937 | .IX Item "gnu89" |
| 8938 | .PD |
| 8939 | The 1990 C standard plus \s-1GNU\s0 extensions. This is the default. |
| 8940 | .ie n .IP """gnu99""" 4 |
| 8941 | .el .IP "\f(CWgnu99\fR" 4 |
| 8942 | .IX Item "gnu99" |
| 8943 | .PD 0 |
| 8944 | .ie n .IP """gnu9x""" 4 |
| 8945 | .el .IP "\f(CWgnu9x\fR" 4 |
| 8946 | .IX Item "gnu9x" |
| 8947 | .PD |
| 8948 | The 1999 C standard plus \s-1GNU\s0 extensions. |
| 8949 | .ie n .IP """gnu11""" 4 |
| 8950 | .el .IP "\f(CWgnu11\fR" 4 |
| 8951 | .IX Item "gnu11" |
| 8952 | .PD 0 |
| 8953 | .ie n .IP """gnu1x""" 4 |
| 8954 | .el .IP "\f(CWgnu1x\fR" 4 |
| 8955 | .IX Item "gnu1x" |
| 8956 | .PD |
| 8957 | The 2011 C standard plus \s-1GNU\s0 extensions. |
| 8958 | .ie n .IP """c++98""" 4 |
| 8959 | .el .IP "\f(CWc++98\fR" 4 |
| 8960 | .IX Item "c++98" |
| 8961 | The 1998 \s-1ISO\s0 \*(C+ standard plus amendments. |
| 8962 | .ie n .IP """gnu++98""" 4 |
| 8963 | .el .IP "\f(CWgnu++98\fR" 4 |
| 8964 | .IX Item "gnu++98" |
| 8965 | The same as \fB\-std=c++98\fR plus \s-1GNU\s0 extensions. This is the |
| 8966 | default for \*(C+ code. |
| 8967 | .RE |
| 8968 | .RS 4 |
| 8969 | .RE |
| 8970 | .IP "\fB\-I\-\fR" 4 |
| 8971 | .IX Item "-I-" |
| 8972 | Split the include path. Any directories specified with \fB\-I\fR |
| 8973 | options before \fB\-I\-\fR are searched only for headers requested with |
| 8974 | \&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for |
| 8975 | \&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR. If additional directories are |
| 8976 | specified with \fB\-I\fR options after the \fB\-I\-\fR, those |
| 8977 | directories are searched for all \fB#include\fR directives. |
| 8978 | .Sp |
| 8979 | In addition, \fB\-I\-\fR inhibits the use of the directory of the current |
| 8980 | file directory as the first search directory for \f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR. |
| 8981 | This option has been deprecated. |
| 8982 | .IP "\fB\-nostdinc\fR" 4 |
| 8983 | .IX Item "-nostdinc" |
| 8984 | Do not search the standard system directories for header files. |
| 8985 | Only the directories you have specified with \fB\-I\fR options |
| 8986 | (and the directory of the current file, if appropriate) are searched. |
| 8987 | .IP "\fB\-nostdinc++\fR" 4 |
| 8988 | .IX Item "-nostdinc++" |
| 8989 | Do not search for header files in the \*(C+\-specific standard directories, |
| 8990 | but do still search the other standard directories. (This option is |
| 8991 | used when building the \*(C+ library.) |
| 8992 | .IP "\fB\-include\fR \fIfile\fR" 4 |
| 8993 | .IX Item "-include file" |
| 8994 | Process \fIfile\fR as if \f(CW\*(C`#include "file"\*(C'\fR appeared as the first |
| 8995 | line of the primary source file. However, the first directory searched |
| 8996 | for \fIfile\fR is the preprocessor's working directory \fIinstead of\fR |
| 8997 | the directory containing the main source file. If not found there, it |
| 8998 | is searched for in the remainder of the \f(CW\*(C`#include "..."\*(C'\fR search |
| 8999 | chain as normal. |
| 9000 | .Sp |
| 9001 | If multiple \fB\-include\fR options are given, the files are included |
| 9002 | in the order they appear on the command line. |
| 9003 | .IP "\fB\-imacros\fR \fIfile\fR" 4 |
| 9004 | .IX Item "-imacros file" |
| 9005 | Exactly like \fB\-include\fR, except that any output produced by |
| 9006 | scanning \fIfile\fR is thrown away. Macros it defines remain defined. |
| 9007 | This allows you to acquire all the macros from a header without also |
| 9008 | processing its declarations. |
| 9009 | .Sp |
| 9010 | All files specified by \fB\-imacros\fR are processed before all files |
| 9011 | specified by \fB\-include\fR. |
| 9012 | .IP "\fB\-idirafter\fR \fIdir\fR" 4 |
| 9013 | .IX Item "-idirafter dir" |
| 9014 | Search \fIdir\fR for header files, but do it \fIafter\fR all |
| 9015 | directories specified with \fB\-I\fR and the standard system directories |
| 9016 | have been exhausted. \fIdir\fR is treated as a system include directory. |
| 9017 | If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced |
| 9018 | by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. |
| 9019 | .IP "\fB\-iprefix\fR \fIprefix\fR" 4 |
| 9020 | .IX Item "-iprefix prefix" |
| 9021 | Specify \fIprefix\fR as the prefix for subsequent \fB\-iwithprefix\fR |
| 9022 | options. If the prefix represents a directory, you should include the |
| 9023 | final \fB/\fR. |
| 9024 | .IP "\fB\-iwithprefix\fR \fIdir\fR" 4 |
| 9025 | .IX Item "-iwithprefix dir" |
| 9026 | .PD 0 |
| 9027 | .IP "\fB\-iwithprefixbefore\fR \fIdir\fR" 4 |
| 9028 | .IX Item "-iwithprefixbefore dir" |
| 9029 | .PD |
| 9030 | Append \fIdir\fR to the prefix specified previously with |
| 9031 | \&\fB\-iprefix\fR, and add the resulting directory to the include search |
| 9032 | path. \fB\-iwithprefixbefore\fR puts it in the same place \fB\-I\fR |
| 9033 | would; \fB\-iwithprefix\fR puts it where \fB\-idirafter\fR would. |
| 9034 | .IP "\fB\-isysroot\fR \fIdir\fR" 4 |
| 9035 | .IX Item "-isysroot dir" |
| 9036 | This option is like the \fB\-\-sysroot\fR option, but applies only to |
| 9037 | header files (except for Darwin targets, where it applies to both header |
| 9038 | files and libraries). See the \fB\-\-sysroot\fR option for more |
| 9039 | information. |
| 9040 | .IP "\fB\-imultilib\fR \fIdir\fR" 4 |
| 9041 | .IX Item "-imultilib dir" |
| 9042 | Use \fIdir\fR as a subdirectory of the directory containing |
| 9043 | target-specific \*(C+ headers. |
| 9044 | .IP "\fB\-isystem\fR \fIdir\fR" 4 |
| 9045 | .IX Item "-isystem dir" |
| 9046 | Search \fIdir\fR for header files, after all directories specified by |
| 9047 | \&\fB\-I\fR but before the standard system directories. Mark it |
| 9048 | as a system directory, so that it gets the same special treatment as |
| 9049 | is applied to the standard system directories. |
| 9050 | If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced |
| 9051 | by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. |
| 9052 | .IP "\fB\-iquote\fR \fIdir\fR" 4 |
| 9053 | .IX Item "-iquote dir" |
| 9054 | Search \fIdir\fR only for header files requested with |
| 9055 | \&\f(CW\*(C`#include\ "\f(CIfile\f(CW"\*(C'\fR; they are not searched for |
| 9056 | \&\f(CW\*(C`#include\ <\f(CIfile\f(CW>\*(C'\fR, before all directories specified by |
| 9057 | \&\fB\-I\fR and before the standard system directories. |
| 9058 | If \fIdir\fR begins with \f(CW\*(C`=\*(C'\fR, then the \f(CW\*(C`=\*(C'\fR will be replaced |
| 9059 | by the sysroot prefix; see \fB\-\-sysroot\fR and \fB\-isysroot\fR. |
| 9060 | .IP "\fB\-fdirectives\-only\fR" 4 |
| 9061 | .IX Item "-fdirectives-only" |
| 9062 | When preprocessing, handle directives, but do not expand macros. |
| 9063 | .Sp |
| 9064 | The option's behavior depends on the \fB\-E\fR and \fB\-fpreprocessed\fR |
| 9065 | options. |
| 9066 | .Sp |
| 9067 | With \fB\-E\fR, preprocessing is limited to the handling of directives |
| 9068 | such as \f(CW\*(C`#define\*(C'\fR, \f(CW\*(C`#ifdef\*(C'\fR, and \f(CW\*(C`#error\*(C'\fR. Other |
| 9069 | preprocessor operations, such as macro expansion and trigraph |
| 9070 | conversion are not performed. In addition, the \fB\-dD\fR option is |
| 9071 | implicitly enabled. |
| 9072 | .Sp |
| 9073 | With \fB\-fpreprocessed\fR, predefinition of command line and most |
| 9074 | builtin macros is disabled. Macros such as \f(CW\*(C`_\|_LINE_\|_\*(C'\fR, which are |
| 9075 | contextually dependent, are handled normally. This enables compilation of |
| 9076 | files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. |
| 9077 | .Sp |
| 9078 | With both \fB\-E\fR and \fB\-fpreprocessed\fR, the rules for |
| 9079 | \&\fB\-fpreprocessed\fR take precedence. This enables full preprocessing of |
| 9080 | files previously preprocessed with \f(CW\*(C`\-E \-fdirectives\-only\*(C'\fR. |
| 9081 | .IP "\fB\-fdollars\-in\-identifiers\fR" 4 |
| 9082 | .IX Item "-fdollars-in-identifiers" |
| 9083 | Accept \fB$\fR in identifiers. |
| 9084 | .IP "\fB\-fextended\-identifiers\fR" 4 |
| 9085 | .IX Item "-fextended-identifiers" |
| 9086 | Accept universal character names in identifiers. This option is |
| 9087 | experimental; in a future version of \s-1GCC\s0, it will be enabled by |
| 9088 | default for C99 and \*(C+. |
| 9089 | .IP "\fB\-fpreprocessed\fR" 4 |
| 9090 | .IX Item "-fpreprocessed" |
| 9091 | Indicate to the preprocessor that the input file has already been |
| 9092 | preprocessed. This suppresses things like macro expansion, trigraph |
| 9093 | conversion, escaped newline splicing, and processing of most directives. |
| 9094 | The preprocessor still recognizes and removes comments, so that you can |
| 9095 | pass a file preprocessed with \fB\-C\fR to the compiler without |
| 9096 | problems. In this mode the integrated preprocessor is little more than |
| 9097 | a tokenizer for the front ends. |
| 9098 | .Sp |
| 9099 | \&\fB\-fpreprocessed\fR is implicit if the input file has one of the |
| 9100 | extensions \fB.i\fR, \fB.ii\fR or \fB.mi\fR. These are the |
| 9101 | extensions that \s-1GCC\s0 uses for preprocessed files created by |
| 9102 | \&\fB\-save\-temps\fR. |
| 9103 | .IP "\fB\-ftabstop=\fR\fIwidth\fR" 4 |
| 9104 | .IX Item "-ftabstop=width" |
| 9105 | Set the distance between tab stops. This helps the preprocessor report |
| 9106 | correct column numbers in warnings or errors, even if tabs appear on the |
| 9107 | line. If the value is less than 1 or greater than 100, the option is |
| 9108 | ignored. The default is 8. |
| 9109 | .IP "\fB\-fdebug\-cpp\fR" 4 |
| 9110 | .IX Item "-fdebug-cpp" |
| 9111 | This option is only useful for debugging \s-1GCC\s0. When used with |
| 9112 | \&\fB\-E\fR, dumps debugging information about location maps. Every |
| 9113 | token in the output is preceded by the dump of the map its location |
| 9114 | belongs to. The dump of the map holding the location of a token would |
| 9115 | be: |
| 9116 | .Sp |
| 9117 | .Vb 1 |
| 9118 | \& {"P":F</file/path>;"F":F</includer/path>;"L":<line_num>;"C":<col_num>;"S":<system_header_p>;"M":<map_address>;"E":<macro_expansion_p>,"loc":<location>} |
| 9119 | .Ve |
| 9120 | .Sp |
| 9121 | When used without \fB\-E\fR, this option has no effect. |
| 9122 | .IP "\fB\-ftrack\-macro\-expansion\fR[\fB=\fR\fIlevel\fR]" 4 |
| 9123 | .IX Item "-ftrack-macro-expansion[=level]" |
| 9124 | Track locations of tokens across macro expansions. This allows the |
| 9125 | compiler to emit diagnostic about the current macro expansion stack |
| 9126 | when a compilation error occurs in a macro expansion. Using this |
| 9127 | option makes the preprocessor and the compiler consume more |
| 9128 | memory. The \fIlevel\fR parameter can be used to choose the level of |
| 9129 | precision of token location tracking thus decreasing the memory |
| 9130 | consumption if necessary. Value \fB0\fR of \fIlevel\fR de-activates |
| 9131 | this option just as if no \fB\-ftrack\-macro\-expansion\fR was present |
| 9132 | on the command line. Value \fB1\fR tracks tokens locations in a |
| 9133 | degraded mode for the sake of minimal memory overhead. In this mode |
| 9134 | all tokens resulting from the expansion of an argument of a |
| 9135 | function-like macro have the same location. Value \fB2\fR tracks |
| 9136 | tokens locations completely. This value is the most memory hungry. |
| 9137 | When this option is given no argument, the default parameter value is |
| 9138 | \&\fB2\fR. |
| 9139 | .IP "\fB\-fexec\-charset=\fR\fIcharset\fR" 4 |
| 9140 | .IX Item "-fexec-charset=charset" |
| 9141 | Set the execution character set, used for string and character |
| 9142 | constants. The default is \s-1UTF\-8\s0. \fIcharset\fR can be any encoding |
| 9143 | supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. |
| 9144 | .IP "\fB\-fwide\-exec\-charset=\fR\fIcharset\fR" 4 |
| 9145 | .IX Item "-fwide-exec-charset=charset" |
| 9146 | Set the wide execution character set, used for wide string and |
| 9147 | character constants. The default is \s-1UTF\-32\s0 or \s-1UTF\-16\s0, whichever |
| 9148 | corresponds to the width of \f(CW\*(C`wchar_t\*(C'\fR. As with |
| 9149 | \&\fB\-fexec\-charset\fR, \fIcharset\fR can be any encoding supported |
| 9150 | by the system's \f(CW\*(C`iconv\*(C'\fR library routine; however, you will have |
| 9151 | problems with encodings that do not fit exactly in \f(CW\*(C`wchar_t\*(C'\fR. |
| 9152 | .IP "\fB\-finput\-charset=\fR\fIcharset\fR" 4 |
| 9153 | .IX Item "-finput-charset=charset" |
| 9154 | Set the input character set, used for translation from the character |
| 9155 | set of the input file to the source character set used by \s-1GCC\s0. If the |
| 9156 | locale does not specify, or \s-1GCC\s0 cannot get this information from the |
| 9157 | locale, the default is \s-1UTF\-8\s0. This can be overridden by either the locale |
| 9158 | or this command line option. Currently the command line option takes |
| 9159 | precedence if there's a conflict. \fIcharset\fR can be any encoding |
| 9160 | supported by the system's \f(CW\*(C`iconv\*(C'\fR library routine. |
| 9161 | .IP "\fB\-fworking\-directory\fR" 4 |
| 9162 | .IX Item "-fworking-directory" |
| 9163 | Enable generation of linemarkers in the preprocessor output that will |
| 9164 | let the compiler know the current working directory at the time of |
| 9165 | preprocessing. When this option is enabled, the preprocessor will |
| 9166 | emit, after the initial linemarker, a second linemarker with the |
| 9167 | current working directory followed by two slashes. \s-1GCC\s0 will use this |
| 9168 | directory, when it's present in the preprocessed input, as the |
| 9169 | directory emitted as the current working directory in some debugging |
| 9170 | information formats. This option is implicitly enabled if debugging |
| 9171 | information is enabled, but this can be inhibited with the negated |
| 9172 | form \fB\-fno\-working\-directory\fR. If the \fB\-P\fR flag is |
| 9173 | present in the command line, this option has no effect, since no |
| 9174 | \&\f(CW\*(C`#line\*(C'\fR directives are emitted whatsoever. |
| 9175 | .IP "\fB\-fno\-show\-column\fR" 4 |
| 9176 | .IX Item "-fno-show-column" |
| 9177 | Do not print column numbers in diagnostics. This may be necessary if |
| 9178 | diagnostics are being scanned by a program that does not understand the |
| 9179 | column numbers, such as \fBdejagnu\fR. |
| 9180 | .IP "\fB\-A\fR \fIpredicate\fR\fB=\fR\fIanswer\fR" 4 |
| 9181 | .IX Item "-A predicate=answer" |
| 9182 | Make an assertion with the predicate \fIpredicate\fR and answer |
| 9183 | \&\fIanswer\fR. This form is preferred to the older form \fB\-A\fR |
| 9184 | \&\fIpredicate\fR\fB(\fR\fIanswer\fR\fB)\fR, which is still supported, because |
| 9185 | it does not use shell special characters. |
| 9186 | .IP "\fB\-A \-\fR\fIpredicate\fR\fB=\fR\fIanswer\fR" 4 |
| 9187 | .IX Item "-A -predicate=answer" |
| 9188 | Cancel an assertion with the predicate \fIpredicate\fR and answer |
| 9189 | \&\fIanswer\fR. |
| 9190 | .IP "\fB\-dCHARS\fR" 4 |
| 9191 | .IX Item "-dCHARS" |
| 9192 | \&\fI\s-1CHARS\s0\fR is a sequence of one or more of the following characters, |
| 9193 | and must not be preceded by a space. Other characters are interpreted |
| 9194 | by the compiler proper, or reserved for future versions of \s-1GCC\s0, and so |
| 9195 | are silently ignored. If you specify characters whose behavior |
| 9196 | conflicts, the result is undefined. |
| 9197 | .RS 4 |
| 9198 | .IP "\fBM\fR" 4 |
| 9199 | .IX Item "M" |
| 9200 | Instead of the normal output, generate a list of \fB#define\fR |
| 9201 | directives for all the macros defined during the execution of the |
| 9202 | preprocessor, including predefined macros. This gives you a way of |
| 9203 | finding out what is predefined in your version of the preprocessor. |
| 9204 | Assuming you have no file \fIfoo.h\fR, the command |
| 9205 | .Sp |
| 9206 | .Vb 1 |
| 9207 | \& touch foo.h; cpp \-dM foo.h |
| 9208 | .Ve |
| 9209 | .Sp |
| 9210 | will show all the predefined macros. |
| 9211 | .Sp |
| 9212 | If you use \fB\-dM\fR without the \fB\-E\fR option, \fB\-dM\fR is |
| 9213 | interpreted as a synonym for \fB\-fdump\-rtl\-mach\fR. |
| 9214 | .IP "\fBD\fR" 4 |
| 9215 | .IX Item "D" |
| 9216 | Like \fBM\fR except in two respects: it does \fInot\fR include the |
| 9217 | predefined macros, and it outputs \fIboth\fR the \fB#define\fR |
| 9218 | directives and the result of preprocessing. Both kinds of output go to |
| 9219 | the standard output file. |
| 9220 | .IP "\fBN\fR" 4 |
| 9221 | .IX Item "N" |
| 9222 | Like \fBD\fR, but emit only the macro names, not their expansions. |
| 9223 | .IP "\fBI\fR" 4 |
| 9224 | .IX Item "I" |
| 9225 | Output \fB#include\fR directives in addition to the result of |
| 9226 | preprocessing. |
| 9227 | .IP "\fBU\fR" 4 |
| 9228 | .IX Item "U" |
| 9229 | Like \fBD\fR except that only macros that are expanded, or whose |
| 9230 | definedness is tested in preprocessor directives, are output; the |
| 9231 | output is delayed until the use or test of the macro; and |
| 9232 | \&\fB#undef\fR directives are also output for macros tested but |
| 9233 | undefined at the time. |
| 9234 | .RE |
| 9235 | .RS 4 |
| 9236 | .RE |
| 9237 | .IP "\fB\-P\fR" 4 |
| 9238 | .IX Item "-P" |
| 9239 | Inhibit generation of linemarkers in the output from the preprocessor. |
| 9240 | This might be useful when running the preprocessor on something that is |
| 9241 | not C code, and will be sent to a program which might be confused by the |
| 9242 | linemarkers. |
| 9243 | .IP "\fB\-C\fR" 4 |
| 9244 | .IX Item "-C" |
| 9245 | Do not discard comments. All comments are passed through to the output |
| 9246 | file, except for comments in processed directives, which are deleted |
| 9247 | along with the directive. |
| 9248 | .Sp |
| 9249 | You should be prepared for side effects when using \fB\-C\fR; it |
| 9250 | causes the preprocessor to treat comments as tokens in their own right. |
| 9251 | For example, comments appearing at the start of what would be a |
| 9252 | directive line have the effect of turning that line into an ordinary |
| 9253 | source line, since the first token on the line is no longer a \fB#\fR. |
| 9254 | .IP "\fB\-CC\fR" 4 |
| 9255 | .IX Item "-CC" |
| 9256 | Do not discard comments, including during macro expansion. This is |
| 9257 | like \fB\-C\fR, except that comments contained within macros are |
| 9258 | also passed through to the output file where the macro is expanded. |
| 9259 | .Sp |
| 9260 | In addition to the side-effects of the \fB\-C\fR option, the |
| 9261 | \&\fB\-CC\fR option causes all \*(C+\-style comments inside a macro |
| 9262 | to be converted to C\-style comments. This is to prevent later use |
| 9263 | of that macro from inadvertently commenting out the remainder of |
| 9264 | the source line. |
| 9265 | .Sp |
| 9266 | The \fB\-CC\fR option is generally used to support lint comments. |
| 9267 | .IP "\fB\-traditional\-cpp\fR" 4 |
| 9268 | .IX Item "-traditional-cpp" |
| 9269 | Try to imitate the behavior of old-fashioned C preprocessors, as |
| 9270 | opposed to \s-1ISO\s0 C preprocessors. |
| 9271 | .IP "\fB\-trigraphs\fR" 4 |
| 9272 | .IX Item "-trigraphs" |
| 9273 | Process trigraph sequences. |
| 9274 | These are three-character sequences, all starting with \fB??\fR, that |
| 9275 | are defined by \s-1ISO\s0 C to stand for single characters. For example, |
| 9276 | \&\fB??/\fR stands for \fB\e\fR, so \fB'??/n'\fR is a character |
| 9277 | constant for a newline. By default, \s-1GCC\s0 ignores trigraphs, but in |
| 9278 | standard-conforming modes it converts them. See the \fB\-std\fR and |
| 9279 | \&\fB\-ansi\fR options. |
| 9280 | .Sp |
| 9281 | The nine trigraphs and their replacements are |
| 9282 | .Sp |
| 9283 | .Vb 2 |
| 9284 | \& Trigraph: ??( ??) ??< ??> ??= ??/ ??\*(Aq ??! ??\- |
| 9285 | \& Replacement: [ ] { } # \e ^ | ~ |
| 9286 | .Ve |
| 9287 | .IP "\fB\-remap\fR" 4 |
| 9288 | .IX Item "-remap" |
| 9289 | Enable special code to work around file systems which only permit very |
| 9290 | short file names, such as MS-DOS. |
| 9291 | .IP "\fB\-\-help\fR" 4 |
| 9292 | .IX Item "--help" |
| 9293 | .PD 0 |
| 9294 | .IP "\fB\-\-target\-help\fR" 4 |
| 9295 | .IX Item "--target-help" |
| 9296 | .PD |
| 9297 | Print text describing all the command line options instead of |
| 9298 | preprocessing anything. |
| 9299 | .IP "\fB\-v\fR" 4 |
| 9300 | .IX Item "-v" |
| 9301 | Verbose mode. Print out \s-1GNU\s0 \s-1CPP\s0's version number at the beginning of |
| 9302 | execution, and report the final form of the include path. |
| 9303 | .IP "\fB\-H\fR" 4 |
| 9304 | .IX Item "-H" |
| 9305 | Print the name of each header file used, in addition to other normal |
| 9306 | activities. Each name is indented to show how deep in the |
| 9307 | \&\fB#include\fR stack it is. Precompiled header files are also |
| 9308 | printed, even if they are found to be invalid; an invalid precompiled |
| 9309 | header file is printed with \fB...x\fR and a valid one with \fB...!\fR . |
| 9310 | .IP "\fB\-version\fR" 4 |
| 9311 | .IX Item "-version" |
| 9312 | .PD 0 |
| 9313 | .IP "\fB\-\-version\fR" 4 |
| 9314 | .IX Item "--version" |
| 9315 | .PD |
| 9316 | Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to |
| 9317 | preprocess as normal. With two dashes, exit immediately. |
| 9318 | .Sh "Passing Options to the Assembler" |
| 9319 | .IX Subsection "Passing Options to the Assembler" |
| 9320 | You can pass options to the assembler. |
| 9321 | .IP "\fB\-Wa,\fR\fIoption\fR" 4 |
| 9322 | .IX Item "-Wa,option" |
| 9323 | Pass \fIoption\fR as an option to the assembler. If \fIoption\fR |
| 9324 | contains commas, it is split into multiple options at the commas. |
| 9325 | .IP "\fB\-Xassembler\fR \fIoption\fR" 4 |
| 9326 | .IX Item "-Xassembler option" |
| 9327 | Pass \fIoption\fR as an option to the assembler. You can use this to |
| 9328 | supply system-specific assembler options that \s-1GCC\s0 does not know how to |
| 9329 | recognize. |
| 9330 | .Sp |
| 9331 | If you want to pass an option that takes an argument, you must use |
| 9332 | \&\fB\-Xassembler\fR twice, once for the option and once for the argument. |
| 9333 | .Sh "Options for Linking" |
| 9334 | .IX Subsection "Options for Linking" |
| 9335 | These options come into play when the compiler links object files into |
| 9336 | an executable output file. They are meaningless if the compiler is |
| 9337 | not doing a link step. |
| 9338 | .IP "\fIobject-file-name\fR" 4 |
| 9339 | .IX Item "object-file-name" |
| 9340 | A file name that does not end in a special recognized suffix is |
| 9341 | considered to name an object file or library. (Object files are |
| 9342 | distinguished from libraries by the linker according to the file |
| 9343 | contents.) If linking is done, these object files are used as input |
| 9344 | to the linker. |
| 9345 | .IP "\fB\-c\fR" 4 |
| 9346 | .IX Item "-c" |
| 9347 | .PD 0 |
| 9348 | .IP "\fB\-S\fR" 4 |
| 9349 | .IX Item "-S" |
| 9350 | .IP "\fB\-E\fR" 4 |
| 9351 | .IX Item "-E" |
| 9352 | .PD |
| 9353 | If any of these options is used, then the linker is not run, and |
| 9354 | object file names should not be used as arguments. |
| 9355 | .IP "\fB\-l\fR\fIlibrary\fR" 4 |
| 9356 | .IX Item "-llibrary" |
| 9357 | .PD 0 |
| 9358 | .IP "\fB\-l\fR \fIlibrary\fR" 4 |
| 9359 | .IX Item "-l library" |
| 9360 | .PD |
| 9361 | Search the library named \fIlibrary\fR when linking. (The second |
| 9362 | alternative with the library as a separate argument is only for |
| 9363 | \&\s-1POSIX\s0 compliance and is not recommended.) |
| 9364 | .Sp |
| 9365 | It makes a difference where in the command you write this option; the |
| 9366 | linker searches and processes libraries and object files in the order they |
| 9367 | are specified. Thus, \fBfoo.o \-lz bar.o\fR searches library \fBz\fR |
| 9368 | after file \fIfoo.o\fR but before \fIbar.o\fR. If \fIbar.o\fR refers |
| 9369 | to functions in \fBz\fR, those functions may not be loaded. |
| 9370 | .Sp |
| 9371 | The linker searches a standard list of directories for the library, |
| 9372 | which is actually a file named \fIlib\fIlibrary\fI.a\fR. The linker |
| 9373 | then uses this file as if it had been specified precisely by name. |
| 9374 | .Sp |
| 9375 | The directories searched include several standard system directories |
| 9376 | plus any that you specify with \fB\-L\fR. |
| 9377 | .Sp |
| 9378 | Normally the files found this way are library files\-\-\-archive files |
| 9379 | whose members are object files. The linker handles an archive file by |
| 9380 | scanning through it for members which define symbols that have so far |
| 9381 | been referenced but not defined. But if the file that is found is an |
| 9382 | ordinary object file, it is linked in the usual fashion. The only |
| 9383 | difference between using an \fB\-l\fR option and specifying a file name |
| 9384 | is that \fB\-l\fR surrounds \fIlibrary\fR with \fBlib\fR and \fB.a\fR |
| 9385 | and searches several directories. |
| 9386 | .IP "\fB\-lobjc\fR" 4 |
| 9387 | .IX Item "-lobjc" |
| 9388 | You need this special case of the \fB\-l\fR option in order to |
| 9389 | link an Objective-C or Objective\-\*(C+ program. |
| 9390 | .IP "\fB\-nostartfiles\fR" 4 |
| 9391 | .IX Item "-nostartfiles" |
| 9392 | Do not use the standard system startup files when linking. |
| 9393 | The standard system libraries are used normally, unless \fB\-nostdlib\fR |
| 9394 | or \fB\-nodefaultlibs\fR is used. |
| 9395 | .IP "\fB\-nodefaultlibs\fR" 4 |
| 9396 | .IX Item "-nodefaultlibs" |
| 9397 | Do not use the standard system libraries when linking. |
| 9398 | Only the libraries you specify will be passed to the linker, options |
| 9399 | specifying linkage of the system libraries, such as \f(CW\*(C`\-static\-libgcc\*(C'\fR |
| 9400 | or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, will be ignored. |
| 9401 | The standard startup files are used normally, unless \fB\-nostartfiles\fR |
| 9402 | is used. The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, |
| 9403 | \&\f(CW\*(C`memset\*(C'\fR, \f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. |
| 9404 | These entries are usually resolved by entries in |
| 9405 | libc. These entry points should be supplied through some other |
| 9406 | mechanism when this option is specified. |
| 9407 | .IP "\fB\-nostdlib\fR" 4 |
| 9408 | .IX Item "-nostdlib" |
| 9409 | Do not use the standard system startup files or libraries when linking. |
| 9410 | No startup files and only the libraries you specify will be passed to |
| 9411 | the linker, options specifying linkage of the system libraries, such as |
| 9412 | \&\f(CW\*(C`\-static\-libgcc\*(C'\fR or \f(CW\*(C`\-shared\-libgcc\*(C'\fR, will be ignored. |
| 9413 | The compiler may generate calls to \f(CW\*(C`memcmp\*(C'\fR, \f(CW\*(C`memset\*(C'\fR, |
| 9414 | \&\f(CW\*(C`memcpy\*(C'\fR and \f(CW\*(C`memmove\*(C'\fR. |
| 9415 | These entries are usually resolved by entries in |
| 9416 | libc. These entry points should be supplied through some other |
| 9417 | mechanism when this option is specified. |
| 9418 | .Sp |
| 9419 | One of the standard libraries bypassed by \fB\-nostdlib\fR and |
| 9420 | \&\fB\-nodefaultlibs\fR is \fIlibgcc.a\fR, a library of internal subroutines |
| 9421 | which \s-1GCC\s0 uses to overcome shortcomings of particular machines, or special |
| 9422 | needs for some languages. |
| 9423 | .Sp |
| 9424 | In most cases, you need \fIlibgcc.a\fR even when you want to avoid |
| 9425 | other standard libraries. In other words, when you specify \fB\-nostdlib\fR |
| 9426 | or \fB\-nodefaultlibs\fR you should usually specify \fB\-lgcc\fR as well. |
| 9427 | This ensures that you have no unresolved references to internal \s-1GCC\s0 |
| 9428 | library subroutines. (For example, \fB_\|_main\fR, used to ensure \*(C+ |
| 9429 | constructors will be called.) |
| 9430 | .IP "\fB\-pie\fR" 4 |
| 9431 | .IX Item "-pie" |
| 9432 | Produce a position independent executable on targets that support it. |
| 9433 | For predictable results, you must also specify the same set of options |
| 9434 | that were used to generate code (\fB\-fpie\fR, \fB\-fPIE\fR, |
| 9435 | or model suboptions) when you specify this option. |
| 9436 | .IP "\fB\-rdynamic\fR" 4 |
| 9437 | .IX Item "-rdynamic" |
| 9438 | Pass the flag \fB\-export\-dynamic\fR to the \s-1ELF\s0 linker, on targets |
| 9439 | that support it. This instructs the linker to add all symbols, not |
| 9440 | only used ones, to the dynamic symbol table. This option is needed |
| 9441 | for some uses of \f(CW\*(C`dlopen\*(C'\fR or to allow obtaining backtraces |
| 9442 | from within a program. |
| 9443 | .IP "\fB\-s\fR" 4 |
| 9444 | .IX Item "-s" |
| 9445 | Remove all symbol table and relocation information from the executable. |
| 9446 | .IP "\fB\-static\fR" 4 |
| 9447 | .IX Item "-static" |
| 9448 | On systems that support dynamic linking, this prevents linking with the shared |
| 9449 | libraries. On other systems, this option has no effect. |
| 9450 | .IP "\fB\-shared\fR" 4 |
| 9451 | .IX Item "-shared" |
| 9452 | Produce a shared object which can then be linked with other objects to |
| 9453 | form an executable. Not all systems support this option. For predictable |
| 9454 | results, you must also specify the same set of options that were used to |
| 9455 | generate code (\fB\-fpic\fR, \fB\-fPIC\fR, or model suboptions) |
| 9456 | when you specify this option.[1] |
| 9457 | .IP "\fB\-shared\-libgcc\fR" 4 |
| 9458 | .IX Item "-shared-libgcc" |
| 9459 | .PD 0 |
| 9460 | .IP "\fB\-static\-libgcc\fR" 4 |
| 9461 | .IX Item "-static-libgcc" |
| 9462 | .PD |
| 9463 | On systems that provide \fIlibgcc\fR as a shared library, these options |
| 9464 | force the use of either the shared or static version respectively. |
| 9465 | If no shared version of \fIlibgcc\fR was built when the compiler was |
| 9466 | configured, these options have no effect. |
| 9467 | .Sp |
| 9468 | There are several situations in which an application should use the |
| 9469 | shared \fIlibgcc\fR instead of the static version. The most common |
| 9470 | of these is when the application wishes to throw and catch exceptions |
| 9471 | across different shared libraries. In that case, each of the libraries |
| 9472 | as well as the application itself should use the shared \fIlibgcc\fR. |
| 9473 | .Sp |
| 9474 | Therefore, the G++ and \s-1GCJ\s0 drivers automatically add |
| 9475 | \&\fB\-shared\-libgcc\fR whenever you build a shared library or a main |
| 9476 | executable, because \*(C+ and Java programs typically use exceptions, so |
| 9477 | this is the right thing to do. |
| 9478 | .Sp |
| 9479 | If, instead, you use the \s-1GCC\s0 driver to create shared libraries, you may |
| 9480 | find that they will not always be linked with the shared \fIlibgcc\fR. |
| 9481 | If \s-1GCC\s0 finds, at its configuration time, that you have a non-GNU linker |
| 9482 | or a \s-1GNU\s0 linker that does not support option \fB\-\-eh\-frame\-hdr\fR, |
| 9483 | it will link the shared version of \fIlibgcc\fR into shared libraries |
| 9484 | by default. Otherwise, it will take advantage of the linker and optimize |
| 9485 | away the linking with the shared version of \fIlibgcc\fR, linking with |
| 9486 | the static version of libgcc by default. This allows exceptions to |
| 9487 | propagate through such shared libraries, without incurring relocation |
| 9488 | costs at library load time. |
| 9489 | .Sp |
| 9490 | However, if a library or main executable is supposed to throw or catch |
| 9491 | exceptions, you must link it using the G++ or \s-1GCJ\s0 driver, as appropriate |
| 9492 | for the languages used in the program, or using the option |
| 9493 | \&\fB\-shared\-libgcc\fR, such that it is linked with the shared |
| 9494 | \&\fIlibgcc\fR. |
| 9495 | .IP "\fB\-static\-libstdc++\fR" 4 |
| 9496 | .IX Item "-static-libstdc++" |
| 9497 | When the \fBg++\fR program is used to link a \*(C+ program, it will |
| 9498 | normally automatically link against \fBlibstdc++\fR. If |
| 9499 | \&\fIlibstdc++\fR is available as a shared library, and the |
| 9500 | \&\fB\-static\fR option is not used, then this will link against the |
| 9501 | shared version of \fIlibstdc++\fR. That is normally fine. However, it |
| 9502 | is sometimes useful to freeze the version of \fIlibstdc++\fR used by |
| 9503 | the program without going all the way to a fully static link. The |
| 9504 | \&\fB\-static\-libstdc++\fR option directs the \fBg++\fR driver to |
| 9505 | link \fIlibstdc++\fR statically, without necessarily linking other |
| 9506 | libraries statically. |
| 9507 | .IP "\fB\-symbolic\fR" 4 |
| 9508 | .IX Item "-symbolic" |
| 9509 | Bind references to global symbols when building a shared object. Warn |
| 9510 | about any unresolved references (unless overridden by the link editor |
| 9511 | option \fB\-Xlinker \-z \-Xlinker defs\fR). Only a few systems support |
| 9512 | this option. |
| 9513 | .IP "\fB\-T\fR \fIscript\fR" 4 |
| 9514 | .IX Item "-T script" |
| 9515 | Use \fIscript\fR as the linker script. This option is supported by most |
| 9516 | systems using the \s-1GNU\s0 linker. On some targets, such as bare-board |
| 9517 | targets without an operating system, the \fB\-T\fR option may be required |
| 9518 | when linking to avoid references to undefined symbols. |
| 9519 | .IP "\fB\-Xlinker\fR \fIoption\fR" 4 |
| 9520 | .IX Item "-Xlinker option" |
| 9521 | Pass \fIoption\fR as an option to the linker. You can use this to |
| 9522 | supply system-specific linker options that \s-1GCC\s0 does not recognize. |
| 9523 | .Sp |
| 9524 | If you want to pass an option that takes a separate argument, you must use |
| 9525 | \&\fB\-Xlinker\fR twice, once for the option and once for the argument. |
| 9526 | For example, to pass \fB\-assert definitions\fR, you must write |
| 9527 | \&\fB\-Xlinker \-assert \-Xlinker definitions\fR. It does not work to write |
| 9528 | \&\fB\-Xlinker \*(L"\-assert definitions\*(R"\fR, because this passes the entire |
| 9529 | string as a single argument, which is not what the linker expects. |
| 9530 | .Sp |
| 9531 | When using the \s-1GNU\s0 linker, it is usually more convenient to pass |
| 9532 | arguments to linker options using the \fIoption\fR\fB=\fR\fIvalue\fR |
| 9533 | syntax than as separate arguments. For example, you can specify |
| 9534 | \&\fB\-Xlinker \-Map=output.map\fR rather than |
| 9535 | \&\fB\-Xlinker \-Map \-Xlinker output.map\fR. Other linkers may not support |
| 9536 | this syntax for command-line options. |
| 9537 | .IP "\fB\-Wl,\fR\fIoption\fR" 4 |
| 9538 | .IX Item "-Wl,option" |
| 9539 | Pass \fIoption\fR as an option to the linker. If \fIoption\fR contains |
| 9540 | commas, it is split into multiple options at the commas. You can use this |
| 9541 | syntax to pass an argument to the option. |
| 9542 | For example, \fB\-Wl,\-Map,output.map\fR passes \fB\-Map output.map\fR to the |
| 9543 | linker. When using the \s-1GNU\s0 linker, you can also get the same effect with |
| 9544 | \&\fB\-Wl,\-Map=output.map\fR. |
| 9545 | .IP "\fB\-u\fR \fIsymbol\fR" 4 |
| 9546 | .IX Item "-u symbol" |
| 9547 | Pretend the symbol \fIsymbol\fR is undefined, to force linking of |
| 9548 | library modules to define it. You can use \fB\-u\fR multiple times with |
| 9549 | different symbols to force loading of additional library modules. |
| 9550 | .Sh "Options for Directory Search" |
| 9551 | .IX Subsection "Options for Directory Search" |
| 9552 | These options specify directories to search for header files, for |
| 9553 | libraries and for parts of the compiler: |
| 9554 | .IP "\fB\-I\fR\fIdir\fR" 4 |
| 9555 | .IX Item "-Idir" |
| 9556 | Add the directory \fIdir\fR to the head of the list of directories to be |
| 9557 | searched for header files. This can be used to override a system header |
| 9558 | file, substituting your own version, since these directories are |
| 9559 | searched before the system header file directories. However, you should |
| 9560 | not use this option to add directories that contain vendor-supplied |
| 9561 | system header files (use \fB\-isystem\fR for that). If you use more than |
| 9562 | one \fB\-I\fR option, the directories are scanned in left-to-right |
| 9563 | order; the standard system directories come after. |
| 9564 | .Sp |
| 9565 | If a standard system include directory, or a directory specified with |
| 9566 | \&\fB\-isystem\fR, is also specified with \fB\-I\fR, the \fB\-I\fR |
| 9567 | option will be ignored. The directory will still be searched but as a |
| 9568 | system directory at its normal position in the system include chain. |
| 9569 | This is to ensure that \s-1GCC\s0's procedure to fix buggy system headers and |
| 9570 | the ordering for the include_next directive are not inadvertently changed. |
| 9571 | If you really need to change the search order for system directories, |
| 9572 | use the \fB\-nostdinc\fR and/or \fB\-isystem\fR options. |
| 9573 | .IP "\fB\-iplugindir=\fR\fIdir\fR" 4 |
| 9574 | .IX Item "-iplugindir=dir" |
| 9575 | Set the directory to search for plugins that are passed |
| 9576 | by \fB\-fplugin=\fR\fIname\fR instead of |
| 9577 | \&\fB\-fplugin=\fR\fIpath\fR\fB/\fR\fIname\fR\fB.so\fR. This option is not meant |
| 9578 | to be used by the user, but only passed by the driver. |
| 9579 | .IP "\fB\-iquote\fR\fIdir\fR" 4 |
| 9580 | .IX Item "-iquotedir" |
| 9581 | Add the directory \fIdir\fR to the head of the list of directories to |
| 9582 | be searched for header files only for the case of \fB#include |
| 9583 | "\fR\fIfile\fR\fB"\fR; they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR, |
| 9584 | otherwise just like \fB\-I\fR. |
| 9585 | .IP "\fB\-L\fR\fIdir\fR" 4 |
| 9586 | .IX Item "-Ldir" |
| 9587 | Add directory \fIdir\fR to the list of directories to be searched |
| 9588 | for \fB\-l\fR. |
| 9589 | .IP "\fB\-B\fR\fIprefix\fR" 4 |
| 9590 | .IX Item "-Bprefix" |
| 9591 | This option specifies where to find the executables, libraries, |
| 9592 | include files, and data files of the compiler itself. |
| 9593 | .Sp |
| 9594 | The compiler driver program runs one or more of the subprograms |
| 9595 | \&\fIcpp\fR, \fIcc1\fR, \fIas\fR and \fIld\fR. It tries |
| 9596 | \&\fIprefix\fR as a prefix for each program it tries to run, both with and |
| 9597 | without \fImachine\fR\fB/\fR\fIversion\fR\fB/\fR. |
| 9598 | .Sp |
| 9599 | For each subprogram to be run, the compiler driver first tries the |
| 9600 | \&\fB\-B\fR prefix, if any. If that name is not found, or if \fB\-B\fR |
| 9601 | was not specified, the driver tries two standard prefixes, |
| 9602 | \&\fI/usr/lib/gcc/\fR and \fI/usr/local/lib/gcc/\fR. If neither of |
| 9603 | those results in a file name that is found, the unmodified program |
| 9604 | name is searched for using the directories specified in your |
| 9605 | \&\fB\s-1PATH\s0\fR environment variable. |
| 9606 | .Sp |
| 9607 | The compiler will check to see if the path provided by the \fB\-B\fR |
| 9608 | refers to a directory, and if necessary it will add a directory |
| 9609 | separator character at the end of the path. |
| 9610 | .Sp |
| 9611 | \&\fB\-B\fR prefixes that effectively specify directory names also apply |
| 9612 | to libraries in the linker, because the compiler translates these |
| 9613 | options into \fB\-L\fR options for the linker. They also apply to |
| 9614 | includes files in the preprocessor, because the compiler translates these |
| 9615 | options into \fB\-isystem\fR options for the preprocessor. In this case, |
| 9616 | the compiler appends \fBinclude\fR to the prefix. |
| 9617 | .Sp |
| 9618 | The runtime support file \fIlibgcc.a\fR can also be searched for using |
| 9619 | the \fB\-B\fR prefix, if needed. If it is not found there, the two |
| 9620 | standard prefixes above are tried, and that is all. The file is left |
| 9621 | out of the link if it is not found by those means. |
| 9622 | .Sp |
| 9623 | Another way to specify a prefix much like the \fB\-B\fR prefix is to use |
| 9624 | the environment variable \fB\s-1GCC_EXEC_PREFIX\s0\fR. |
| 9625 | .Sp |
| 9626 | As a special kludge, if the path provided by \fB\-B\fR is |
| 9627 | \&\fI[dir/]stage\fIN\fI/\fR, where \fIN\fR is a number in the range 0 to |
| 9628 | 9, then it will be replaced by \fI[dir/]include\fR. This is to help |
| 9629 | with boot-strapping the compiler. |
| 9630 | .IP "\fB\-specs=\fR\fIfile\fR" 4 |
| 9631 | .IX Item "-specs=file" |
| 9632 | Process \fIfile\fR after the compiler reads in the standard \fIspecs\fR |
| 9633 | file, in order to override the defaults which the \fIgcc\fR driver |
| 9634 | program uses when determining what switches to pass to \fIcc1\fR, |
| 9635 | \&\fIcc1plus\fR, \fIas\fR, \fIld\fR, etc. More than one |
| 9636 | \&\fB\-specs=\fR\fIfile\fR can be specified on the command line, and they |
| 9637 | are processed in order, from left to right. |
| 9638 | .IP "\fB\-\-sysroot=\fR\fIdir\fR" 4 |
| 9639 | .IX Item "--sysroot=dir" |
| 9640 | Use \fIdir\fR as the logical root directory for headers and libraries. |
| 9641 | For example, if the compiler would normally search for headers in |
| 9642 | \&\fI/usr/include\fR and libraries in \fI/usr/lib\fR, it will instead |
| 9643 | search \fI\fIdir\fI/usr/include\fR and \fI\fIdir\fI/usr/lib\fR. |
| 9644 | .Sp |
| 9645 | If you use both this option and the \fB\-isysroot\fR option, then |
| 9646 | the \fB\-\-sysroot\fR option will apply to libraries, but the |
| 9647 | \&\fB\-isysroot\fR option will apply to header files. |
| 9648 | .Sp |
| 9649 | The \s-1GNU\s0 linker (beginning with version 2.16) has the necessary support |
| 9650 | for this option. If your linker does not support this option, the |
| 9651 | header file aspect of \fB\-\-sysroot\fR will still work, but the |
| 9652 | library aspect will not. |
| 9653 | .IP "\fB\-I\-\fR" 4 |
| 9654 | .IX Item "-I-" |
| 9655 | This option has been deprecated. Please use \fB\-iquote\fR instead for |
| 9656 | \&\fB\-I\fR directories before the \fB\-I\-\fR and remove the \fB\-I\-\fR. |
| 9657 | Any directories you specify with \fB\-I\fR options before the \fB\-I\-\fR |
| 9658 | option are searched only for the case of \fB#include "\fR\fIfile\fR\fB"\fR; |
| 9659 | they are not searched for \fB#include <\fR\fIfile\fR\fB>\fR. |
| 9660 | .Sp |
| 9661 | If additional directories are specified with \fB\-I\fR options after |
| 9662 | the \fB\-I\-\fR, these directories are searched for all \fB#include\fR |
| 9663 | directives. (Ordinarily \fIall\fR \fB\-I\fR directories are used |
| 9664 | this way.) |
| 9665 | .Sp |
| 9666 | In addition, the \fB\-I\-\fR option inhibits the use of the current |
| 9667 | directory (where the current input file came from) as the first search |
| 9668 | directory for \fB#include "\fR\fIfile\fR\fB"\fR. There is no way to |
| 9669 | override this effect of \fB\-I\-\fR. With \fB\-I.\fR you can specify |
| 9670 | searching the directory that was current when the compiler was |
| 9671 | invoked. That is not exactly the same as what the preprocessor does |
| 9672 | by default, but it is often satisfactory. |
| 9673 | .Sp |
| 9674 | \&\fB\-I\-\fR does not inhibit the use of the standard system directories |
| 9675 | for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are |
| 9676 | independent. |
| 9677 | .Sh "Specifying Target Machine and Compiler Version" |
| 9678 | .IX Subsection "Specifying Target Machine and Compiler Version" |
| 9679 | The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or |
| 9680 | \&\fImachine\fR\fB\-gcc\fR when cross-compiling, or |
| 9681 | \&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a version other than the |
| 9682 | one that was installed last. |
| 9683 | .Sh "Hardware Models and Configurations" |
| 9684 | .IX Subsection "Hardware Models and Configurations" |
| 9685 | Each target machine types can have its own |
| 9686 | special options, starting with \fB\-m\fR, to choose among various |
| 9687 | hardware models or configurations\-\-\-for example, 68010 vs 68020, |
| 9688 | floating coprocessor or none. A single installed version of the |
| 9689 | compiler can compile for any model or configuration, according to the |
| 9690 | options specified. |
| 9691 | .PP |
| 9692 | Some configurations of the compiler also support additional special |
| 9693 | options, usually for compatibility with other compilers on the same |
| 9694 | platform. |
| 9695 | .PP |
| 9696 | \fIAdapteva Epiphany Options\fR |
| 9697 | .IX Subsection "Adapteva Epiphany Options" |
| 9698 | .PP |
| 9699 | These \fB\-m\fR options are defined for Adapteva Epiphany: |
| 9700 | .IP "\fB\-mhalf\-reg\-file\fR" 4 |
| 9701 | .IX Item "-mhalf-reg-file" |
| 9702 | Don't allocate any register in the range \f(CW\*(C`r32\*(C'\fR...\f(CW\*(C`r63\*(C'\fR. |
| 9703 | That allows code to run on hardware variants that lack these registers. |
| 9704 | .IP "\fB\-mprefer\-short\-insn\-regs\fR" 4 |
| 9705 | .IX Item "-mprefer-short-insn-regs" |
| 9706 | Preferrentially allocate registers that allow short instruction generation. |
| 9707 | This can result in increasesd instruction count, so if this reduces or |
| 9708 | increases code size might vary from case to case. |
| 9709 | .IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4 |
| 9710 | .IX Item "-mbranch-cost=num" |
| 9711 | Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions. |
| 9712 | This cost is only a heuristic and is not guaranteed to produce |
| 9713 | consistent results across releases. |
| 9714 | .IP "\fB\-mcmove\fR" 4 |
| 9715 | .IX Item "-mcmove" |
| 9716 | Enable the generation of conditional moves. |
| 9717 | .IP "\fB\-mnops=\fR\fInum\fR" 4 |
| 9718 | .IX Item "-mnops=num" |
| 9719 | Emit \fInum\fR nops before every other generated instruction. |
| 9720 | .IP "\fB\-mno\-soft\-cmpsf\fR" 4 |
| 9721 | .IX Item "-mno-soft-cmpsf" |
| 9722 | For single-precision floating-point comparisons, emit an fsub instruction |
| 9723 | and test the flags. This is faster than a software comparison, but can |
| 9724 | get incorrect results in the presence of NaNs, or when two different small |
| 9725 | numbers are compared such that their difference is calculated as zero. |
| 9726 | The default is \fB\-msoft\-cmpsf\fR, which uses slower, but IEEE-compliant, |
| 9727 | software comparisons. |
| 9728 | .IP "\fB\-mstack\-offset=\fR\fInum\fR" 4 |
| 9729 | .IX Item "-mstack-offset=num" |
| 9730 | Set the offset between the top of the stack and the stack pointer. |
| 9731 | E.g., a value of 8 means that the eight bytes in the range sp+0...sp+7 |
| 9732 | can be used by leaf functions without stack allocation. |
| 9733 | Values other than \fB8\fR or \fB16\fR are untested and unlikely to work. |
| 9734 | Note also that this option changes the \s-1ABI\s0, compiling a program with a |
| 9735 | different stack offset than the libraries have been compiled with |
| 9736 | will generally not work. |
| 9737 | This option can be useful if you want to evaluate if a different stack |
| 9738 | offset would give you better code, but to actually use a different stack |
| 9739 | offset to build working programs, it is recommended to configure the |
| 9740 | toolchain with the appropriate \fB\-\-with\-stack\-offset=\fR\fInum\fR option. |
| 9741 | .IP "\fB\-mno\-round\-nearest\fR" 4 |
| 9742 | .IX Item "-mno-round-nearest" |
| 9743 | Make the scheduler assume that the rounding mode has been set to |
| 9744 | truncating. The default is \fB\-mround\-nearest\fR. |
| 9745 | .IP "\fB\-mlong\-calls\fR" 4 |
| 9746 | .IX Item "-mlong-calls" |
| 9747 | If not otherwise specified by an attribute, assume all calls might be beyond |
| 9748 | the offset range of the b / bl instructions, and therefore load the |
| 9749 | function address into a register before performing a (otherwise direct) call. |
| 9750 | This is the default. |
| 9751 | .IP "\fB\-mshort\-calls\fR" 4 |
| 9752 | .IX Item "-mshort-calls" |
| 9753 | If not otherwise specified by an attribute, assume all direct calls are |
| 9754 | in the range of the b / bl instructions, so use these instructions |
| 9755 | for direct calls. The default is \fB\-mlong\-calls\fR. |
| 9756 | .IP "\fB\-msmall16\fR" 4 |
| 9757 | .IX Item "-msmall16" |
| 9758 | Assume addresses can be loaded as 16\-bit unsigned values. This does not |
| 9759 | apply to function addresses for which \fB\-mlong\-calls\fR semantics |
| 9760 | are in effect. |
| 9761 | .IP "\fB\-mfp\-mode=\fR\fImode\fR" 4 |
| 9762 | .IX Item "-mfp-mode=mode" |
| 9763 | Set the prevailing mode of the floating-point unit. |
| 9764 | This determines the floating-point mode that is provided and expected |
| 9765 | at function call and return time. Making this mode match the mode you |
| 9766 | predominantly need at function start can make your programs smaller and |
| 9767 | faster by avoiding unnecessary mode switches. |
| 9768 | .Sp |
| 9769 | \&\fImode\fR can be set to one the following values: |
| 9770 | .RS 4 |
| 9771 | .IP "\fBcaller\fR" 4 |
| 9772 | .IX Item "caller" |
| 9773 | Any mode at function entry is valid, and retained or restored when |
| 9774 | the function returns, and when it calls other functions. |
| 9775 | This mode is useful for compiling libraries or other compilation units |
| 9776 | you might want to incorporate into different programs with different |
| 9777 | prevailing \s-1FPU\s0 modes, and the convenience of being able to use a single |
| 9778 | object file outweighs the size and speed overhead for any extra |
| 9779 | mode switching that might be needed, compared with what would be needed |
| 9780 | with a more specific choice of prevailing \s-1FPU\s0 mode. |
| 9781 | .IP "\fBtruncate\fR" 4 |
| 9782 | .IX Item "truncate" |
| 9783 | This is the mode used for floating-point calculations with |
| 9784 | truncating (i.e. round towards zero) rounding mode. That includes |
| 9785 | conversion from floating point to integer. |
| 9786 | .IP "\fBround-nearest\fR" 4 |
| 9787 | .IX Item "round-nearest" |
| 9788 | This is the mode used for floating-point calculations with |
| 9789 | round-to-nearest-or-even rounding mode. |
| 9790 | .IP "\fBint\fR" 4 |
| 9791 | .IX Item "int" |
| 9792 | This is the mode used to perform integer calculations in the \s-1FPU\s0, e.g. |
| 9793 | integer multiply, or integer multiply-and-accumulate. |
| 9794 | .RE |
| 9795 | .RS 4 |
| 9796 | .Sp |
| 9797 | The default is \fB\-mfp\-mode=caller\fR |
| 9798 | .RE |
| 9799 | .IP "\fB\-mnosplit\-lohi\fR" 4 |
| 9800 | .IX Item "-mnosplit-lohi" |
| 9801 | .PD 0 |
| 9802 | .IP "\fB\-mno\-postinc\fR" 4 |
| 9803 | .IX Item "-mno-postinc" |
| 9804 | .IP "\fB\-mno\-postmodify\fR" 4 |
| 9805 | .IX Item "-mno-postmodify" |
| 9806 | .PD |
| 9807 | Code generation tweaks that disable, respectively, splitting of 32\-bit |
| 9808 | loads, generation of post-increment addresses, and generation of |
| 9809 | post-modify addresses. The defaults are \fBmsplit-lohi\fR, |
| 9810 | \&\fB\-mpost\-inc\fR, and \fB\-mpost\-modify\fR. |
| 9811 | .IP "\fB\-mnovect\-double\fR" 4 |
| 9812 | .IX Item "-mnovect-double" |
| 9813 | Change the preferred \s-1SIMD\s0 mode to SImode. The default is |
| 9814 | \&\fB\-mvect\-double\fR, which uses DImode as preferred \s-1SIMD\s0 mode. |
| 9815 | .IP "\fB\-max\-vect\-align=\fR\fInum\fR" 4 |
| 9816 | .IX Item "-max-vect-align=num" |
| 9817 | The maximum alignment for \s-1SIMD\s0 vector mode types. |
| 9818 | \&\fInum\fR may be 4 or 8. The default is 8. |
| 9819 | Note that this is an \s-1ABI\s0 change, even though many library function |
| 9820 | interfaces will be unaffected, if they don't use \s-1SIMD\s0 vector modes |
| 9821 | in places where they affect size and/or alignment of relevant types. |
| 9822 | .IP "\fB\-msplit\-vecmove\-early\fR" 4 |
| 9823 | .IX Item "-msplit-vecmove-early" |
| 9824 | Split vector moves into single word moves before reload. In theory this |
| 9825 | could give better register allocation, but so far the reverse seems to be |
| 9826 | generally the case. |
| 9827 | .IP "\fB\-m1reg\-\fR\fIreg\fR" 4 |
| 9828 | .IX Item "-m1reg-reg" |
| 9829 | Specify a register to hold the constant \-1, which makes loading small negative |
| 9830 | constants and certain bitmasks faster. |
| 9831 | Allowable values for reg are r43 and r63, which specify to use that register |
| 9832 | as a fixed register, and none, which means that no register is used for this |
| 9833 | purpose. The default is \fB\-m1reg\-none\fR. |
| 9834 | .PP |
| 9835 | \fI\s-1ARM\s0 Options\fR |
| 9836 | .IX Subsection "ARM Options" |
| 9837 | .PP |
| 9838 | These \fB\-m\fR options are defined for Advanced \s-1RISC\s0 Machines (\s-1ARM\s0) |
| 9839 | architectures: |
| 9840 | .IP "\fB\-mabi=\fR\fIname\fR" 4 |
| 9841 | .IX Item "-mabi=name" |
| 9842 | Generate code for the specified \s-1ABI\s0. Permissible values are: \fBapcs-gnu\fR, |
| 9843 | \&\fBatpcs\fR, \fBaapcs\fR, \fBaapcs-linux\fR and \fBiwmmxt\fR. |
| 9844 | .IP "\fB\-mapcs\-frame\fR" 4 |
| 9845 | .IX Item "-mapcs-frame" |
| 9846 | Generate a stack frame that is compliant with the \s-1ARM\s0 Procedure Call |
| 9847 | Standard for all functions, even if this is not strictly necessary for |
| 9848 | correct execution of the code. Specifying \fB\-fomit\-frame\-pointer\fR |
| 9849 | with this option will cause the stack frames not to be generated for |
| 9850 | leaf functions. The default is \fB\-mno\-apcs\-frame\fR. |
| 9851 | .IP "\fB\-mapcs\fR" 4 |
| 9852 | .IX Item "-mapcs" |
| 9853 | This is a synonym for \fB\-mapcs\-frame\fR. |
| 9854 | .IP "\fB\-mthumb\-interwork\fR" 4 |
| 9855 | .IX Item "-mthumb-interwork" |
| 9856 | Generate code that supports calling between the \s-1ARM\s0 and Thumb |
| 9857 | instruction sets. Without this option, on pre\-v5 architectures, the |
| 9858 | two instruction sets cannot be reliably used inside one program. The |
| 9859 | default is \fB\-mno\-thumb\-interwork\fR, since slightly larger code |
| 9860 | is generated when \fB\-mthumb\-interwork\fR is specified. In \s-1AAPCS\s0 |
| 9861 | configurations this option is meaningless. |
| 9862 | .IP "\fB\-mno\-sched\-prolog\fR" 4 |
| 9863 | .IX Item "-mno-sched-prolog" |
| 9864 | Prevent the reordering of instructions in the function prologue, or the |
| 9865 | merging of those instruction with the instructions in the function's |
| 9866 | body. This means that all functions will start with a recognizable set |
| 9867 | of instructions (or in fact one of a choice from a small set of |
| 9868 | different function prologues), and this information can be used to |
| 9869 | locate the start if functions inside an executable piece of code. The |
| 9870 | default is \fB\-msched\-prolog\fR. |
| 9871 | .IP "\fB\-mfloat\-abi=\fR\fIname\fR" 4 |
| 9872 | .IX Item "-mfloat-abi=name" |
| 9873 | Specifies which floating-point \s-1ABI\s0 to use. Permissible values |
| 9874 | are: \fBsoft\fR, \fBsoftfp\fR and \fBhard\fR. |
| 9875 | .Sp |
| 9876 | Specifying \fBsoft\fR causes \s-1GCC\s0 to generate output containing |
| 9877 | library calls for floating-point operations. |
| 9878 | \&\fBsoftfp\fR allows the generation of code using hardware floating-point |
| 9879 | instructions, but still uses the soft-float calling conventions. |
| 9880 | \&\fBhard\fR allows generation of floating-point instructions |
| 9881 | and uses FPU-specific calling conventions. |
| 9882 | .Sp |
| 9883 | The default depends on the specific target configuration. Note that |
| 9884 | the hard-float and soft-float ABIs are not link-compatible; you must |
| 9885 | compile your entire program with the same \s-1ABI\s0, and link with a |
| 9886 | compatible set of libraries. |
| 9887 | .IP "\fB\-mlittle\-endian\fR" 4 |
| 9888 | .IX Item "-mlittle-endian" |
| 9889 | Generate code for a processor running in little-endian mode. This is |
| 9890 | the default for all standard configurations. |
| 9891 | .IP "\fB\-mbig\-endian\fR" 4 |
| 9892 | .IX Item "-mbig-endian" |
| 9893 | Generate code for a processor running in big-endian mode; the default is |
| 9894 | to compile code for a little-endian processor. |
| 9895 | .IP "\fB\-mwords\-little\-endian\fR" 4 |
| 9896 | .IX Item "-mwords-little-endian" |
| 9897 | This option only applies when generating code for big-endian processors. |
| 9898 | Generate code for a little-endian word order but a big-endian byte |
| 9899 | order. That is, a byte order of the form \fB32107654\fR. Note: this |
| 9900 | option should only be used if you require compatibility with code for |
| 9901 | big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to |
| 9902 | 2.8. This option is now deprecated. |
| 9903 | .IP "\fB\-march=\fR\fIname\fR" 4 |
| 9904 | .IX Item "-march=name" |
| 9905 | This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this |
| 9906 | name to determine what kind of instructions it can emit when generating |
| 9907 | assembly code. This option can be used in conjunction with or instead |
| 9908 | of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, |
| 9909 | \&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, |
| 9910 | \&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, |
| 9911 | \&\fBarmv6\fR, \fBarmv6j\fR, |
| 9912 | \&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, |
| 9913 | \&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, \fBarmv7e\-m\fR, |
| 9914 | \&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. |
| 9915 | .Sp |
| 9916 | \&\fB\-march=native\fR causes the compiler to auto-detect the architecture |
| 9917 | of the build computer. At present, this feature is only supported on |
| 9918 | Linux, and not all architectures are recognized. If the auto-detect is |
| 9919 | unsuccessful the option has no effect. |
| 9920 | .IP "\fB\-mtune=\fR\fIname\fR" 4 |
| 9921 | .IX Item "-mtune=name" |
| 9922 | This option specifies the name of the target \s-1ARM\s0 processor for |
| 9923 | which \s-1GCC\s0 should tune the performance of the code. |
| 9924 | For some \s-1ARM\s0 implementations better performance can be obtained by using |
| 9925 | this option. |
| 9926 | Permissible names are: \fBarm2\fR, \fBarm250\fR, |
| 9927 | \&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR, |
| 9928 | \&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR, |
| 9929 | \&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR, |
| 9930 | \&\fBarm700i\fR, \fBarm710\fR, \fBarm710c\fR, \fBarm7100\fR, |
| 9931 | \&\fBarm720\fR, |
| 9932 | \&\fBarm7500\fR, \fBarm7500fe\fR, \fBarm7tdmi\fR, \fBarm7tdmi\-s\fR, |
| 9933 | \&\fBarm710t\fR, \fBarm720t\fR, \fBarm740t\fR, |
| 9934 | \&\fBstrongarm\fR, \fBstrongarm110\fR, \fBstrongarm1100\fR, |
| 9935 | \&\fBstrongarm1110\fR, |
| 9936 | \&\fBarm8\fR, \fBarm810\fR, \fBarm9\fR, \fBarm9e\fR, \fBarm920\fR, |
| 9937 | \&\fBarm920t\fR, \fBarm922t\fR, \fBarm946e\-s\fR, \fBarm966e\-s\fR, |
| 9938 | \&\fBarm968e\-s\fR, \fBarm926ej\-s\fR, \fBarm940t\fR, \fBarm9tdmi\fR, |
| 9939 | \&\fBarm10tdmi\fR, \fBarm1020t\fR, \fBarm1026ej\-s\fR, |
| 9940 | \&\fBarm10e\fR, \fBarm1020e\fR, \fBarm1022e\fR, |
| 9941 | \&\fBarm1136j\-s\fR, \fBarm1136jf\-s\fR, \fBmpcore\fR, \fBmpcorenovfp\fR, |
| 9942 | \&\fBarm1156t2\-s\fR, \fBarm1156t2f\-s\fR, \fBarm1176jz\-s\fR, \fBarm1176jzf\-s\fR, |
| 9943 | \&\fBcortex\-a5\fR, \fBcortex\-a7\fR, \fBcortex\-a8\fR, \fBcortex\-a9\fR, |
| 9944 | \&\fBcortex\-a15\fR, \fBcortex\-r4\fR, \fBcortex\-r4f\fR, \fBcortex\-r5\fR, |
| 9945 | \&\fBcortex\-m4\fR, \fBcortex\-m3\fR, |
| 9946 | \&\fBcortex\-m1\fR, |
| 9947 | \&\fBcortex\-m0\fR, |
| 9948 | \&\fBxscale\fR, \fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR, |
| 9949 | \&\fBfa526\fR, \fBfa626\fR, |
| 9950 | \&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR. |
| 9951 | .Sp |
| 9952 | \&\fB\-mtune=generic\-\fR\fIarch\fR specifies that \s-1GCC\s0 should tune the |
| 9953 | performance for a blend of processors within architecture \fIarch\fR. |
| 9954 | The aim is to generate code that run well on the current most popular |
| 9955 | processors, balancing between optimizations that benefit some CPUs in the |
| 9956 | range, and avoiding performance pitfalls of other CPUs. The effects of |
| 9957 | this option may change in future \s-1GCC\s0 versions as \s-1CPU\s0 models come and go. |
| 9958 | .Sp |
| 9959 | \&\fB\-mtune=native\fR causes the compiler to auto-detect the \s-1CPU\s0 |
| 9960 | of the build computer. At present, this feature is only supported on |
| 9961 | Linux, and not all architectures are recognized. If the auto-detect is |
| 9962 | unsuccessful the option has no effect. |
| 9963 | .IP "\fB\-mcpu=\fR\fIname\fR" 4 |
| 9964 | .IX Item "-mcpu=name" |
| 9965 | This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name |
| 9966 | to derive the name of the target \s-1ARM\s0 architecture (as if specified |
| 9967 | by \fB\-march\fR) and the \s-1ARM\s0 processor type for which to tune for |
| 9968 | performance (as if specified by \fB\-mtune\fR). Where this option |
| 9969 | is used in conjunction with \fB\-march\fR or \fB\-mtune\fR, |
| 9970 | those options take precedence over the appropriate part of this option. |
| 9971 | .Sp |
| 9972 | Permissible names for this option are the same as those for |
| 9973 | \&\fB\-mtune\fR. |
| 9974 | .Sp |
| 9975 | \&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is |
| 9976 | equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. |
| 9977 | See \fB\-mtune\fR for more information. |
| 9978 | .Sp |
| 9979 | \&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 |
| 9980 | of the build computer. At present, this feature is only supported on |
| 9981 | Linux, and not all architectures are recognized. If the auto-detect is |
| 9982 | unsuccessful the option has no effect. |
| 9983 | .IP "\fB\-mfpu=\fR\fIname\fR" 4 |
| 9984 | .IX Item "-mfpu=name" |
| 9985 | .PD 0 |
| 9986 | .IP "\fB\-mfpe=\fR\fInumber\fR" 4 |
| 9987 | .IX Item "-mfpe=number" |
| 9988 | .IP "\fB\-mfp=\fR\fInumber\fR" 4 |
| 9989 | .IX Item "-mfp=number" |
| 9990 | .PD |
| 9991 | This specifies what floating-point hardware (or hardware emulation) is |
| 9992 | available on the target. Permissible names are: \fBfpa\fR, \fBfpe2\fR, |
| 9993 | \&\fBfpe3\fR, \fBmaverick\fR, \fBvfp\fR, \fBvfpv3\fR, \fBvfpv3\-fp16\fR, |
| 9994 | \&\fBvfpv3\-d16\fR, \fBvfpv3\-d16\-fp16\fR, \fBvfpv3xd\fR, \fBvfpv3xd\-fp16\fR, |
| 9995 | \&\fBneon\fR, \fBneon\-fp16\fR, \fBvfpv4\fR, \fBvfpv4\-d16\fR, |
| 9996 | \&\fBfpv4\-sp\-d16\fR and \fBneon\-vfpv4\fR. |
| 9997 | \&\fB\-mfp\fR and \fB\-mfpe\fR are synonyms for |
| 9998 | \&\fB\-mfpu\fR=\fBfpe\fR\fInumber\fR, for compatibility with older versions |
| 9999 | of \s-1GCC\s0. |
| 10000 | .Sp |
| 10001 | If \fB\-msoft\-float\fR is specified this specifies the format of |
| 10002 | floating-point values. |
| 10003 | .Sp |
| 10004 | If the selected floating-point hardware includes the \s-1NEON\s0 extension |
| 10005 | (e.g. \fB\-mfpu\fR=\fBneon\fR), note that floating-point |
| 10006 | operations will not be used by \s-1GCC\s0's auto-vectorization pass unless |
| 10007 | \&\fB\-funsafe\-math\-optimizations\fR is also specified. This is |
| 10008 | because \s-1NEON\s0 hardware does not fully implement the \s-1IEEE\s0 754 standard for |
| 10009 | floating-point arithmetic (in particular denormal values are treated as |
| 10010 | zero), so the use of \s-1NEON\s0 instructions may lead to a loss of precision. |
| 10011 | .IP "\fB\-mfp16\-format=\fR\fIname\fR" 4 |
| 10012 | .IX Item "-mfp16-format=name" |
| 10013 | Specify the format of the \f(CW\*(C`_\|_fp16\*(C'\fR half-precision floating-point type. |
| 10014 | Permissible names are \fBnone\fR, \fBieee\fR, and \fBalternative\fR; |
| 10015 | the default is \fBnone\fR, in which case the \f(CW\*(C`_\|_fp16\*(C'\fR type is not |
| 10016 | defined. |
| 10017 | .IP "\fB\-mstructure\-size\-boundary=\fR\fIn\fR" 4 |
| 10018 | .IX Item "-mstructure-size-boundary=n" |
| 10019 | The size of all structures and unions will be rounded up to a multiple |
| 10020 | of the number of bits set by this option. Permissible values are 8, 32 |
| 10021 | and 64. The default value varies for different toolchains. For the \s-1COFF\s0 |
| 10022 | targeted toolchain the default value is 8. A value of 64 is only allowed |
| 10023 | if the underlying \s-1ABI\s0 supports it. |
| 10024 | .Sp |
| 10025 | Specifying the larger number can produce faster, more efficient code, but |
| 10026 | can also increase the size of the program. Different values are potentially |
| 10027 | incompatible. Code compiled with one value cannot necessarily expect to |
| 10028 | work with code or libraries compiled with another value, if they exchange |
| 10029 | information using structures or unions. |
| 10030 | .IP "\fB\-mabort\-on\-noreturn\fR" 4 |
| 10031 | .IX Item "-mabort-on-noreturn" |
| 10032 | Generate a call to the function \f(CW\*(C`abort\*(C'\fR at the end of a |
| 10033 | \&\f(CW\*(C`noreturn\*(C'\fR function. It will be executed if the function tries to |
| 10034 | return. |
| 10035 | .IP "\fB\-mlong\-calls\fR" 4 |
| 10036 | .IX Item "-mlong-calls" |
| 10037 | .PD 0 |
| 10038 | .IP "\fB\-mno\-long\-calls\fR" 4 |
| 10039 | .IX Item "-mno-long-calls" |
| 10040 | .PD |
| 10041 | Tells the compiler to perform function calls by first loading the |
| 10042 | address of the function into a register and then performing a subroutine |
| 10043 | call on this register. This switch is needed if the target function |
| 10044 | will lie outside of the 64 megabyte addressing range of the offset based |
| 10045 | version of subroutine call instruction. |
| 10046 | .Sp |
| 10047 | Even if this switch is enabled, not all function calls will be turned |
| 10048 | into long calls. The heuristic is that static functions, functions |
| 10049 | that have the \fBshort-call\fR attribute, functions that are inside |
| 10050 | the scope of a \fB#pragma no_long_calls\fR directive and functions whose |
| 10051 | definitions have already been compiled within the current compilation |
| 10052 | unit, will not be turned into long calls. The exception to this rule is |
| 10053 | that weak function definitions, functions with the \fBlong-call\fR |
| 10054 | attribute or the \fBsection\fR attribute, and functions that are within |
| 10055 | the scope of a \fB#pragma long_calls\fR directive, will always be |
| 10056 | turned into long calls. |
| 10057 | .Sp |
| 10058 | This feature is not enabled by default. Specifying |
| 10059 | \&\fB\-mno\-long\-calls\fR will restore the default behavior, as will |
| 10060 | placing the function calls within the scope of a \fB#pragma |
| 10061 | long_calls_off\fR directive. Note these switches have no effect on how |
| 10062 | the compiler generates code to handle function calls via function |
| 10063 | pointers. |
| 10064 | .IP "\fB\-msingle\-pic\-base\fR" 4 |
| 10065 | .IX Item "-msingle-pic-base" |
| 10066 | Treat the register used for \s-1PIC\s0 addressing as read-only, rather than |
| 10067 | loading it in the prologue for each function. The runtime system is |
| 10068 | responsible for initializing this register with an appropriate value |
| 10069 | before execution begins. |
| 10070 | .IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 |
| 10071 | .IX Item "-mpic-register=reg" |
| 10072 | Specify the register to be used for \s-1PIC\s0 addressing. The default is R10 |
| 10073 | unless stack-checking is enabled, when R9 is used. |
| 10074 | .IP "\fB\-mcirrus\-fix\-invalid\-insns\fR" 4 |
| 10075 | .IX Item "-mcirrus-fix-invalid-insns" |
| 10076 | Insert NOPs into the instruction stream to in order to work around |
| 10077 | problems with invalid Maverick instruction combinations. This option |
| 10078 | is only valid if the \fB\-mcpu=ep9312\fR option has been used to |
| 10079 | enable generation of instructions for the Cirrus Maverick floating-point |
| 10080 | co-processor. This option is not enabled by default, since the |
| 10081 | problem is only present in older Maverick implementations. The default |
| 10082 | can be re-enabled by use of the \fB\-mno\-cirrus\-fix\-invalid\-insns\fR |
| 10083 | switch. |
| 10084 | .IP "\fB\-mpoke\-function\-name\fR" 4 |
| 10085 | .IX Item "-mpoke-function-name" |
| 10086 | Write the name of each function into the text section, directly |
| 10087 | preceding the function prologue. The generated code is similar to this: |
| 10088 | .Sp |
| 10089 | .Vb 9 |
| 10090 | \& t0 |
| 10091 | \& .ascii "arm_poke_function_name", 0 |
| 10092 | \& .align |
| 10093 | \& t1 |
| 10094 | \& .word 0xff000000 + (t1 \- t0) |
| 10095 | \& arm_poke_function_name |
| 10096 | \& mov ip, sp |
| 10097 | \& stmfd sp!, {fp, ip, lr, pc} |
| 10098 | \& sub fp, ip, #4 |
| 10099 | .Ve |
| 10100 | .Sp |
| 10101 | When performing a stack backtrace, code can inspect the value of |
| 10102 | \&\f(CW\*(C`pc\*(C'\fR stored at \f(CW\*(C`fp + 0\*(C'\fR. If the trace function then looks at |
| 10103 | location \f(CW\*(C`pc \- 12\*(C'\fR and the top 8 bits are set, then we know that |
| 10104 | there is a function name embedded immediately preceding this location |
| 10105 | and has length \f(CW\*(C`((pc[\-3]) & 0xff000000)\*(C'\fR. |
| 10106 | .IP "\fB\-mthumb\fR" 4 |
| 10107 | .IX Item "-mthumb" |
| 10108 | .PD 0 |
| 10109 | .IP "\fB\-marm\fR" 4 |
| 10110 | .IX Item "-marm" |
| 10111 | .PD |
| 10112 | Select between generating code that executes in \s-1ARM\s0 and Thumb |
| 10113 | states. The default for most configurations is to generate code |
| 10114 | that executes in \s-1ARM\s0 state, but the default can be changed by |
| 10115 | configuring \s-1GCC\s0 with the \fB\-\-with\-mode=\fR\fIstate\fR |
| 10116 | configure option. |
| 10117 | .IP "\fB\-mtpcs\-frame\fR" 4 |
| 10118 | .IX Item "-mtpcs-frame" |
| 10119 | Generate a stack frame that is compliant with the Thumb Procedure Call |
| 10120 | Standard for all non-leaf functions. (A leaf function is one that does |
| 10121 | not call any other functions.) The default is \fB\-mno\-tpcs\-frame\fR. |
| 10122 | .IP "\fB\-mtpcs\-leaf\-frame\fR" 4 |
| 10123 | .IX Item "-mtpcs-leaf-frame" |
| 10124 | Generate a stack frame that is compliant with the Thumb Procedure Call |
| 10125 | Standard for all leaf functions. (A leaf function is one that does |
| 10126 | not call any other functions.) The default is \fB\-mno\-apcs\-leaf\-frame\fR. |
| 10127 | .IP "\fB\-mcallee\-super\-interworking\fR" 4 |
| 10128 | .IX Item "-mcallee-super-interworking" |
| 10129 | Gives all externally visible functions in the file being compiled an \s-1ARM\s0 |
| 10130 | instruction set header which switches to Thumb mode before executing the |
| 10131 | rest of the function. This allows these functions to be called from |
| 10132 | non-interworking code. This option is not valid in \s-1AAPCS\s0 configurations |
| 10133 | because interworking is enabled by default. |
| 10134 | .IP "\fB\-mcaller\-super\-interworking\fR" 4 |
| 10135 | .IX Item "-mcaller-super-interworking" |
| 10136 | Allows calls via function pointers (including virtual functions) to |
| 10137 | execute correctly regardless of whether the target code has been |
| 10138 | compiled for interworking or not. There is a small overhead in the cost |
| 10139 | of executing a function pointer if this option is enabled. This option |
| 10140 | is not valid in \s-1AAPCS\s0 configurations because interworking is enabled |
| 10141 | by default. |
| 10142 | .IP "\fB\-mtp=\fR\fIname\fR" 4 |
| 10143 | .IX Item "-mtp=name" |
| 10144 | Specify the access model for the thread local storage pointer. The valid |
| 10145 | models are \fBsoft\fR, which generates calls to \f(CW\*(C`_\|_aeabi_read_tp\*(C'\fR, |
| 10146 | \&\fBcp15\fR, which fetches the thread pointer from \f(CW\*(C`cp15\*(C'\fR directly |
| 10147 | (supported in the arm6k architecture), and \fBauto\fR, which uses the |
| 10148 | best available method for the selected processor. The default setting is |
| 10149 | \&\fBauto\fR. |
| 10150 | .IP "\fB\-mtls\-dialect=\fR\fIdialect\fR" 4 |
| 10151 | .IX Item "-mtls-dialect=dialect" |
| 10152 | Specify the dialect to use for accessing thread local storage. Two |
| 10153 | dialects are supported \-\-\- \fBgnu\fR and \fBgnu2\fR. The |
| 10154 | \&\fBgnu\fR dialect selects the original \s-1GNU\s0 scheme for supporting |
| 10155 | local and global dynamic \s-1TLS\s0 models. The \fBgnu2\fR dialect |
| 10156 | selects the \s-1GNU\s0 descriptor scheme, which provides better performance |
| 10157 | for shared libraries. The \s-1GNU\s0 descriptor scheme is compatible with |
| 10158 | the original scheme, but does require new assembler, linker and |
| 10159 | library support. Initial and local exec \s-1TLS\s0 models are unaffected by |
| 10160 | this option and always use the original scheme. |
| 10161 | .IP "\fB\-mword\-relocations\fR" 4 |
| 10162 | .IX Item "-mword-relocations" |
| 10163 | Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32). |
| 10164 | This is enabled by default on targets (uClinux, SymbianOS) where the runtime |
| 10165 | loader imposes this restriction, and when \fB\-fpic\fR or \fB\-fPIC\fR |
| 10166 | is specified. |
| 10167 | .IP "\fB\-mfix\-cortex\-m3\-ldrd\fR" 4 |
| 10168 | .IX Item "-mfix-cortex-m3-ldrd" |
| 10169 | Some Cortex\-M3 cores can cause data corruption when \f(CW\*(C`ldrd\*(C'\fR instructions |
| 10170 | with overlapping destination and base registers are used. This option avoids |
| 10171 | generating these instructions. This option is enabled by default when |
| 10172 | \&\fB\-mcpu=cortex\-m3\fR is specified. |
| 10173 | .IP "\fB\-munaligned\-access\fR" 4 |
| 10174 | .IX Item "-munaligned-access" |
| 10175 | .PD 0 |
| 10176 | .IP "\fB\-mno\-unaligned\-access\fR" 4 |
| 10177 | .IX Item "-mno-unaligned-access" |
| 10178 | .PD |
| 10179 | Enables (or disables) reading and writing of 16\- and 32\- bit values |
| 10180 | from addresses that are not 16\- or 32\- bit aligned. By default |
| 10181 | unaligned access is disabled for all pre\-ARMv6 and all ARMv6\-M |
| 10182 | architectures, and enabled for all other architectures. If unaligned |
| 10183 | access is not enabled then words in packed data structures will be |
| 10184 | accessed a byte at a time. |
| 10185 | .Sp |
| 10186 | The \s-1ARM\s0 attribute \f(CW\*(C`Tag_CPU_unaligned_access\*(C'\fR will be set in the |
| 10187 | generated object file to either true or false, depending upon the |
| 10188 | setting of this option. If unaligned access is enabled then the |
| 10189 | preprocessor symbol \f(CW\*(C`_\|_ARM_FEATURE_UNALIGNED\*(C'\fR will also be |
| 10190 | defined. |
| 10191 | .PP |
| 10192 | \fI\s-1AVR\s0 Options\fR |
| 10193 | .IX Subsection "AVR Options" |
| 10194 | .IP "\fB\-mmcu=\fR\fImcu\fR" 4 |
| 10195 | .IX Item "-mmcu=mcu" |
| 10196 | Specify Atmel \s-1AVR\s0 instruction set architectures (\s-1ISA\s0) or \s-1MCU\s0 type. |
| 10197 | .Sp |
| 10198 | The default for this option is@tie{}\f(CW\*(C`avr2\*(C'\fR. |
| 10199 | .Sp |
| 10200 | \&\s-1GCC\s0 supports the following \s-1AVR\s0 devices and ISAs: |
| 10201 | .RS 4 |
| 10202 | .ie n .IP """avr2""" 4 |
| 10203 | .el .IP "\f(CWavr2\fR" 4 |
| 10204 | .IX Item "avr2" |
| 10205 | \&\*(L"Classic\*(R" devices with up to 8@tie{}KiB of program memory. |
| 10206 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`attiny22\*(C'\fR, \f(CW\*(C`attiny26\*(C'\fR, \f(CW\*(C`at90c8534\*(C'\fR, |
| 10207 | \&\f(CW\*(C`at90s2313\*(C'\fR, \f(CW\*(C`at90s2323\*(C'\fR, \f(CW\*(C`at90s2333\*(C'\fR, |
| 10208 | \&\f(CW\*(C`at90s2343\*(C'\fR, \f(CW\*(C`at90s4414\*(C'\fR, \f(CW\*(C`at90s4433\*(C'\fR, |
| 10209 | \&\f(CW\*(C`at90s4434\*(C'\fR, \f(CW\*(C`at90s8515\*(C'\fR, \f(CW\*(C`at90s8535\*(C'\fR. |
| 10210 | .ie n .IP """avr25""" 4 |
| 10211 | .el .IP "\f(CWavr25\fR" 4 |
| 10212 | .IX Item "avr25" |
| 10213 | \&\*(L"Classic\*(R" devices with up to 8@tie{}KiB of program memory and with |
| 10214 | the \f(CW\*(C`MOVW\*(C'\fR instruction. |
| 10215 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata6289\*(C'\fR, \f(CW\*(C`attiny13\*(C'\fR, \f(CW\*(C`attiny13a\*(C'\fR, |
| 10216 | \&\f(CW\*(C`attiny2313\*(C'\fR, \f(CW\*(C`attiny2313a\*(C'\fR, \f(CW\*(C`attiny24\*(C'\fR, |
| 10217 | \&\f(CW\*(C`attiny24a\*(C'\fR, \f(CW\*(C`attiny25\*(C'\fR, \f(CW\*(C`attiny261\*(C'\fR, |
| 10218 | \&\f(CW\*(C`attiny261a\*(C'\fR, \f(CW\*(C`attiny43u\*(C'\fR, \f(CW\*(C`attiny4313\*(C'\fR, |
| 10219 | \&\f(CW\*(C`attiny44\*(C'\fR, \f(CW\*(C`attiny44a\*(C'\fR, \f(CW\*(C`attiny45\*(C'\fR, \f(CW\*(C`attiny461\*(C'\fR, |
| 10220 | \&\f(CW\*(C`attiny461a\*(C'\fR, \f(CW\*(C`attiny48\*(C'\fR, \f(CW\*(C`attiny84\*(C'\fR, \f(CW\*(C`attiny84a\*(C'\fR, |
| 10221 | \&\f(CW\*(C`attiny85\*(C'\fR, \f(CW\*(C`attiny861\*(C'\fR, \f(CW\*(C`attiny861a\*(C'\fR, \f(CW\*(C`attiny87\*(C'\fR, |
| 10222 | \&\f(CW\*(C`attiny88\*(C'\fR, \f(CW\*(C`at86rf401\*(C'\fR. |
| 10223 | .ie n .IP """avr3""" 4 |
| 10224 | .el .IP "\f(CWavr3\fR" 4 |
| 10225 | .IX Item "avr3" |
| 10226 | \&\*(L"Classic\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. |
| 10227 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`at43usb355\*(C'\fR, \f(CW\*(C`at76c711\*(C'\fR. |
| 10228 | .ie n .IP """avr31""" 4 |
| 10229 | .el .IP "\f(CWavr31\fR" 4 |
| 10230 | .IX Item "avr31" |
| 10231 | \&\*(L"Classic\*(R" devices with 128@tie{}KiB of program memory. |
| 10232 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega103\*(C'\fR, \f(CW\*(C`at43usb320\*(C'\fR. |
| 10233 | .ie n .IP """avr35""" 4 |
| 10234 | .el .IP "\f(CWavr35\fR" 4 |
| 10235 | .IX Item "avr35" |
| 10236 | \&\*(L"Classic\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program |
| 10237 | memory and with the \f(CW\*(C`MOVW\*(C'\fR instruction. |
| 10238 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega16u2\*(C'\fR, \f(CW\*(C`atmega32u2\*(C'\fR, |
| 10239 | \&\f(CW\*(C`atmega8u2\*(C'\fR, \f(CW\*(C`attiny167\*(C'\fR, \f(CW\*(C`at90usb162\*(C'\fR, |
| 10240 | \&\f(CW\*(C`at90usb82\*(C'\fR. |
| 10241 | .ie n .IP """avr4""" 4 |
| 10242 | .el .IP "\f(CWavr4\fR" 4 |
| 10243 | .IX Item "avr4" |
| 10244 | \&\*(L"Enhanced\*(R" devices with up to 8@tie{}KiB of program memory. |
| 10245 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega48\*(C'\fR, \f(CW\*(C`atmega48a\*(C'\fR, |
| 10246 | \&\f(CW\*(C`atmega48p\*(C'\fR, \f(CW\*(C`atmega8\*(C'\fR, \f(CW\*(C`atmega8hva\*(C'\fR, |
| 10247 | \&\f(CW\*(C`atmega8515\*(C'\fR, \f(CW\*(C`atmega8535\*(C'\fR, \f(CW\*(C`atmega88\*(C'\fR, |
| 10248 | \&\f(CW\*(C`atmega88a\*(C'\fR, \f(CW\*(C`atmega88p\*(C'\fR, \f(CW\*(C`atmega88pa\*(C'\fR, |
| 10249 | \&\f(CW\*(C`at90pwm1\*(C'\fR, \f(CW\*(C`at90pwm2\*(C'\fR, \f(CW\*(C`at90pwm2b\*(C'\fR, \f(CW\*(C`at90pwm3\*(C'\fR, |
| 10250 | \&\f(CW\*(C`at90pwm3b\*(C'\fR, \f(CW\*(C`at90pwm81\*(C'\fR. |
| 10251 | .ie n .IP """avr5""" 4 |
| 10252 | .el .IP "\f(CWavr5\fR" 4 |
| 10253 | .IX Item "avr5" |
| 10254 | \&\*(L"Enhanced\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. |
| 10255 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, |
| 10256 | \&\f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, |
| 10257 | \&\f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, |
| 10258 | \&\f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, |
| 10259 | \&\f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, |
| 10260 | \&\f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, |
| 10261 | \&\f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, |
| 10262 | \&\f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, |
| 10263 | \&\f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, |
| 10264 | \&\f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, |
| 10265 | \&\f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, |
| 10266 | \&\f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, |
| 10267 | \&\f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, |
| 10268 | \&\f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, |
| 10269 | \&\f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, |
| 10270 | \&\f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, |
| 10271 | \&\f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, |
| 10272 | \&\f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, |
| 10273 | \&\f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, |
| 10274 | \&\f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, |
| 10275 | \&\f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, |
| 10276 | \&\f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, |
| 10277 | \&\f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, |
| 10278 | \&\f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, |
| 10279 | \&\f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, |
| 10280 | \&\f(CW\*(C`m3000\*(C'\fR. |
| 10281 | .ie n .IP """avr51""" 4 |
| 10282 | .el .IP "\f(CWavr51\fR" 4 |
| 10283 | .IX Item "avr51" |
| 10284 | \&\*(L"Enhanced\*(R" devices with 128@tie{}KiB of program memory. |
| 10285 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega128\*(C'\fR, \f(CW\*(C`atmega128rfa1\*(C'\fR, |
| 10286 | \&\f(CW\*(C`atmega1280\*(C'\fR, \f(CW\*(C`atmega1281\*(C'\fR, \f(CW\*(C`atmega1284p\*(C'\fR, |
| 10287 | \&\f(CW\*(C`at90can128\*(C'\fR, \f(CW\*(C`at90usb1286\*(C'\fR, \f(CW\*(C`at90usb1287\*(C'\fR. |
| 10288 | .ie n .IP """avr6""" 4 |
| 10289 | .el .IP "\f(CWavr6\fR" 4 |
| 10290 | .IX Item "avr6" |
| 10291 | \&\*(L"Enhanced\*(R" devices with 3\-byte \s-1PC\s0, i.e. with more than |
| 10292 | 128@tie{}KiB of program memory. |
| 10293 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atmega2560\*(C'\fR, \f(CW\*(C`atmega2561\*(C'\fR. |
| 10294 | .ie n .IP """avrxmega2""" 4 |
| 10295 | .el .IP "\f(CWavrxmega2\fR" 4 |
| 10296 | .IX Item "avrxmega2" |
| 10297 | \&\*(L"\s-1XMEGA\s0\*(R" devices with more than 8@tie{}KiB and up to 64@tie{}KiB of |
| 10298 | program memory. |
| 10299 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega16a4\*(C'\fR, \f(CW\*(C`atxmega16d4\*(C'\fR, |
| 10300 | \&\f(CW\*(C`atxmega16x1\*(C'\fR, \f(CW\*(C`atxmega32a4\*(C'\fR, \f(CW\*(C`atxmega32d4\*(C'\fR, |
| 10301 | \&\f(CW\*(C`atxmega32x1\*(C'\fR. |
| 10302 | .ie n .IP """avrxmega4""" 4 |
| 10303 | .el .IP "\f(CWavrxmega4\fR" 4 |
| 10304 | .IX Item "avrxmega4" |
| 10305 | \&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of |
| 10306 | program memory. |
| 10307 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a3\*(C'\fR, \f(CW\*(C`atxmega64d3\*(C'\fR. |
| 10308 | .ie n .IP """avrxmega5""" 4 |
| 10309 | .el .IP "\f(CWavrxmega5\fR" 4 |
| 10310 | .IX Item "avrxmega5" |
| 10311 | \&\*(L"\s-1XMEGA\s0\*(R" devices with more than 64@tie{}KiB and up to 128@tie{}KiB of |
| 10312 | program memory and more than 64@tie{}KiB of \s-1RAM\s0. |
| 10313 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega64a1\*(C'\fR, \f(CW\*(C`atxmega64a1u\*(C'\fR. |
| 10314 | .ie n .IP """avrxmega6""" 4 |
| 10315 | .el .IP "\f(CWavrxmega6\fR" 4 |
| 10316 | .IX Item "avrxmega6" |
| 10317 | \&\*(L"\s-1XMEGA\s0\*(R" devices with more than 128@tie{}KiB of program memory. |
| 10318 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a3\*(C'\fR, \f(CW\*(C`atxmega128d3\*(C'\fR, |
| 10319 | \&\f(CW\*(C`atxmega192a3\*(C'\fR, \f(CW\*(C`atxmega192d3\*(C'\fR, \f(CW\*(C`atxmega256a3\*(C'\fR, |
| 10320 | \&\f(CW\*(C`atxmega256a3b\*(C'\fR, \f(CW\*(C`atxmega256a3bu\*(C'\fR, \f(CW\*(C`atxmega256d3\*(C'\fR. |
| 10321 | .ie n .IP """avrxmega7""" 4 |
| 10322 | .el .IP "\f(CWavrxmega7\fR" 4 |
| 10323 | .IX Item "avrxmega7" |
| 10324 | \&\*(L"\s-1XMEGA\s0\*(R" devices with more than 128@tie{}KiB of program memory and |
| 10325 | more than 64@tie{}KiB of \s-1RAM\s0. |
| 10326 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`atxmega128a1\*(C'\fR, \f(CW\*(C`atxmega128a1u\*(C'\fR. |
| 10327 | .ie n .IP """avr1""" 4 |
| 10328 | .el .IP "\f(CWavr1\fR" 4 |
| 10329 | .IX Item "avr1" |
| 10330 | This \s-1ISA\s0 is implemented by the minimal \s-1AVR\s0 core and supported for |
| 10331 | assembler only. |
| 10332 | \&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`attiny11\*(C'\fR, \f(CW\*(C`attiny12\*(C'\fR, \f(CW\*(C`attiny15\*(C'\fR, |
| 10333 | \&\f(CW\*(C`attiny28\*(C'\fR, \f(CW\*(C`at90s1200\*(C'\fR. |
| 10334 | .RE |
| 10335 | .RS 4 |
| 10336 | .RE |
| 10337 | .IP "\fB\-maccumulate\-args\fR" 4 |
| 10338 | .IX Item "-maccumulate-args" |
| 10339 | Accumulate outgoing function arguments and acquire/release the needed |
| 10340 | stack space for outgoing function arguments once in function |
| 10341 | prologue/epilogue. Without this option, outgoing arguments are pushed |
| 10342 | before calling a function and popped afterwards. |
| 10343 | .Sp |
| 10344 | Popping the arguments after the function call can be expensive on |
| 10345 | \&\s-1AVR\s0 so that accumulating the stack space might lead to smaller |
| 10346 | executables because arguments need not to be removed from the |
| 10347 | stack after such a function call. |
| 10348 | .Sp |
| 10349 | This option can lead to reduced code size for functions that perform |
| 10350 | several calls to functions that get their arguments on the stack like |
| 10351 | calls to printf-like functions. |
| 10352 | .IP "\fB\-mbranch\-cost=\fR\fIcost\fR" 4 |
| 10353 | .IX Item "-mbranch-cost=cost" |
| 10354 | Set the branch costs for conditional branch instructions to |
| 10355 | \&\fIcost\fR. Reasonable values for \fIcost\fR are small, non-negative |
| 10356 | integers. The default branch cost is 0. |
| 10357 | .IP "\fB\-mcall\-prologues\fR" 4 |
| 10358 | .IX Item "-mcall-prologues" |
| 10359 | Functions prologues/epilogues are expanded as calls to appropriate |
| 10360 | subroutines. Code size is smaller. |
| 10361 | .IP "\fB\-mint8\fR" 4 |
| 10362 | .IX Item "-mint8" |
| 10363 | Assume \f(CW\*(C`int\*(C'\fR to be 8\-bit integer. This affects the sizes of all types: a |
| 10364 | \&\f(CW\*(C`char\*(C'\fR is 1 byte, an \f(CW\*(C`int\*(C'\fR is 1 byte, a \f(CW\*(C`long\*(C'\fR is 2 bytes, |
| 10365 | and \f(CW\*(C`long long\*(C'\fR is 4 bytes. Please note that this option does not |
| 10366 | conform to the C standards, but it results in smaller code |
| 10367 | size. |
| 10368 | .IP "\fB\-mno\-interrupts\fR" 4 |
| 10369 | .IX Item "-mno-interrupts" |
| 10370 | Generated code is not compatible with hardware interrupts. |
| 10371 | Code size is smaller. |
| 10372 | .IP "\fB\-mrelax\fR" 4 |
| 10373 | .IX Item "-mrelax" |
| 10374 | Try to replace \f(CW\*(C`CALL\*(C'\fR resp. \f(CW\*(C`JMP\*(C'\fR instruction by the shorter |
| 10375 | \&\f(CW\*(C`RCALL\*(C'\fR resp. \f(CW\*(C`RJMP\*(C'\fR instruction if applicable. |
| 10376 | Setting \f(CW\*(C`\-mrelax\*(C'\fR just adds the \f(CW\*(C`\-\-relax\*(C'\fR option to the |
| 10377 | linker command line when the linker is called. |
| 10378 | .Sp |
| 10379 | Jump relaxing is performed by the linker because jump offsets are not |
| 10380 | known before code is located. Therefore, the assembler code generated by the |
| 10381 | compiler is the same, but the instructions in the executable may |
| 10382 | differ from instructions in the assembler code. |
| 10383 | .Sp |
| 10384 | Relaxing must be turned on if linker stubs are needed, see the |
| 10385 | section on \f(CW\*(C`EIND\*(C'\fR and linker stubs below. |
| 10386 | .IP "\fB\-mshort\-calls\fR" 4 |
| 10387 | .IX Item "-mshort-calls" |
| 10388 | This option has been deprecated and will be removed in \s-1GCC\s0 4.8. |
| 10389 | See \f(CW\*(C`\-mrelax\*(C'\fR for a replacement. |
| 10390 | .Sp |
| 10391 | Use \f(CW\*(C`RCALL\*(C'\fR/\f(CW\*(C`RJMP\*(C'\fR instructions even on devices with |
| 10392 | 16@tie{}KiB or more of program memory, i.e. on devices that |
| 10393 | have the \f(CW\*(C`CALL\*(C'\fR and \f(CW\*(C`JMP\*(C'\fR instructions. |
| 10394 | .IP "\fB\-msp8\fR" 4 |
| 10395 | .IX Item "-msp8" |
| 10396 | Treat the stack pointer register as an 8\-bit register, |
| 10397 | i.e. assume the high byte of the stack pointer is zero. |
| 10398 | In general, you don't need to set this option by hand. |
| 10399 | .Sp |
| 10400 | This option is used internally by the compiler to select and |
| 10401 | build multilibs for architectures \f(CW\*(C`avr2\*(C'\fR and \f(CW\*(C`avr25\*(C'\fR. |
| 10402 | These architectures mix devices with and without \f(CW\*(C`SPH\*(C'\fR. |
| 10403 | For any setting other than \f(CW\*(C`\-mmcu=avr2\*(C'\fR or \f(CW\*(C`\-mmcu=avr25\*(C'\fR |
| 10404 | the compiler driver will add or remove this option from the compiler |
| 10405 | proper's command line, because the compiler then knows if the device |
| 10406 | or architecture has an 8\-bit stack pointer and thus no \f(CW\*(C`SPH\*(C'\fR |
| 10407 | register or not. |
| 10408 | .IP "\fB\-mstrict\-X\fR" 4 |
| 10409 | .IX Item "-mstrict-X" |
| 10410 | Use address register \f(CW\*(C`X\*(C'\fR in a way proposed by the hardware. This means |
| 10411 | that \f(CW\*(C`X\*(C'\fR is only used in indirect, post-increment or |
| 10412 | pre-decrement addressing. |
| 10413 | .Sp |
| 10414 | Without this option, the \f(CW\*(C`X\*(C'\fR register may be used in the same way |
| 10415 | as \f(CW\*(C`Y\*(C'\fR or \f(CW\*(C`Z\*(C'\fR which then is emulated by additional |
| 10416 | instructions. |
| 10417 | For example, loading a value with \f(CW\*(C`X+const\*(C'\fR addressing with a |
| 10418 | small non-negative \f(CW\*(C`const < 64\*(C'\fR to a register \fIRn\fR is |
| 10419 | performed as |
| 10420 | .Sp |
| 10421 | .Vb 3 |
| 10422 | \& adiw r26, const ; X += const |
| 10423 | \& ld <Rn>, X ; <Rn> = *X |
| 10424 | \& sbiw r26, const ; X \-= const |
| 10425 | .Ve |
| 10426 | .IP "\fB\-mtiny\-stack\fR" 4 |
| 10427 | .IX Item "-mtiny-stack" |
| 10428 | Only change the lower 8@tie{}bits of the stack pointer. |
| 10429 | .PP |
| 10430 | \f(CW\*(C`EIND\*(C'\fR and Devices with more than 128 Ki Bytes of Flash |
| 10431 | .IX Subsection "EIND and Devices with more than 128 Ki Bytes of Flash" |
| 10432 | .PP |
| 10433 | Pointers in the implementation are 16@tie{}bits wide. |
| 10434 | The address of a function or label is represented as word address so |
| 10435 | that indirect jumps and calls can target any code address in the |
| 10436 | range of 64@tie{}Ki words. |
| 10437 | .PP |
| 10438 | In order to facilitate indirect jump on devices with more than 128@tie{}Ki |
| 10439 | bytes of program memory space, there is a special function register called |
| 10440 | \&\f(CW\*(C`EIND\*(C'\fR that serves as most significant part of the target address |
| 10441 | when \f(CW\*(C`EICALL\*(C'\fR or \f(CW\*(C`EIJMP\*(C'\fR instructions are used. |
| 10442 | .PP |
| 10443 | Indirect jumps and calls on these devices are handled as follows by |
| 10444 | the compiler and are subject to some limitations: |
| 10445 | .IP "\(bu" 4 |
| 10446 | The compiler never sets \f(CW\*(C`EIND\*(C'\fR. |
| 10447 | .IP "\(bu" 4 |
| 10448 | The compiler uses \f(CW\*(C`EIND\*(C'\fR implicitely in \f(CW\*(C`EICALL\*(C'\fR/\f(CW\*(C`EIJMP\*(C'\fR |
| 10449 | instructions or might read \f(CW\*(C`EIND\*(C'\fR directly in order to emulate an |
| 10450 | indirect call/jump by means of a \f(CW\*(C`RET\*(C'\fR instruction. |
| 10451 | .IP "\(bu" 4 |
| 10452 | The compiler assumes that \f(CW\*(C`EIND\*(C'\fR never changes during the startup |
| 10453 | code or during the application. In particular, \f(CW\*(C`EIND\*(C'\fR is not |
| 10454 | saved/restored in function or interrupt service routine |
| 10455 | prologue/epilogue. |
| 10456 | .IP "\(bu" 4 |
| 10457 | For indirect calls to functions and computed goto, the linker |
| 10458 | generates \fIstubs\fR. Stubs are jump pads sometimes also called |
| 10459 | \&\fItrampolines\fR. Thus, the indirect call/jump jumps to such a stub. |
| 10460 | The stub contains a direct jump to the desired address. |
| 10461 | .IP "\(bu" 4 |
| 10462 | Linker relaxation must be turned on so that the linker will generate |
| 10463 | the stubs correctly an all situaltion. See the compiler option |
| 10464 | \&\f(CW\*(C`\-mrelax\*(C'\fR and the linler option \f(CW\*(C`\-\-relax\*(C'\fR. |
| 10465 | There are corner cases where the linker is supposed to generate stubs |
| 10466 | but aborts without relaxation and without a helpful error message. |
| 10467 | .IP "\(bu" 4 |
| 10468 | The default linker script is arranged for code with \f(CW\*(C`EIND = 0\*(C'\fR. |
| 10469 | If code is supposed to work for a setup with \f(CW\*(C`EIND != 0\*(C'\fR, a custom |
| 10470 | linker script has to be used in order to place the sections whose |
| 10471 | name start with \f(CW\*(C`.trampolines\*(C'\fR into the segment where \f(CW\*(C`EIND\*(C'\fR |
| 10472 | points to. |
| 10473 | .IP "\(bu" 4 |
| 10474 | The startup code from libgcc never sets \f(CW\*(C`EIND\*(C'\fR. |
| 10475 | Notice that startup code is a blend of code from libgcc and AVR-LibC. |
| 10476 | For the impact of AVR-LibC on \f(CW\*(C`EIND\*(C'\fR, see the |
| 10477 | AVR-LibC\ user\ manual (\f(CW\*(C`http://nongnu.org/avr\-libc/user\-manual/\*(C'\fR). |
| 10478 | .IP "\(bu" 4 |
| 10479 | It is legitimate for user-specific startup code to set up \f(CW\*(C`EIND\*(C'\fR |
| 10480 | early, for example by means of initialization code located in |
| 10481 | section \f(CW\*(C`.init3\*(C'\fR. Such code runs prior to general startup code |
| 10482 | that initializes \s-1RAM\s0 and calls constructors, but after the bit |
| 10483 | of startup code from AVR-LibC that sets \f(CW\*(C`EIND\*(C'\fR to the segment |
| 10484 | where the vector table is located. |
| 10485 | .Sp |
| 10486 | .Vb 1 |
| 10487 | \& #include <avr/io.h> |
| 10488 | \& |
| 10489 | \& static void |
| 10490 | \& _\|_attribute_\|_((section(".init3"),naked,used,no_instrument_function)) |
| 10491 | \& init3_set_eind (void) |
| 10492 | \& { |
| 10493 | \& _\|_asm volatile ("ldi r24,pm_hh8(_\|_trampolines_start)\en\et" |
| 10494 | \& "out %i0,r24" :: "n" (&EIND) : "r24","memory"); |
| 10495 | \& } |
| 10496 | .Ve |
| 10497 | .Sp |
| 10498 | The \f(CW\*(C`_\|_trampolines_start\*(C'\fR symbol is defined in the linker script. |
| 10499 | .IP "\(bu" 4 |
| 10500 | Stubs are generated automatically by the linker if |
| 10501 | the following two conditions are met: |
| 10502 | .RS 4 |
| 10503 | .ie n .IP "\-<The address of a label is taken by means of the ""gs"" modifier>" 4 |
| 10504 | .el .IP "\-<The address of a label is taken by means of the \f(CWgs\fR modifier>" 4 |
| 10505 | .IX Item "-<The address of a label is taken by means of the gs modifier>" |
| 10506 | (short for \fIgenerate stubs\fR) like so: |
| 10507 | .Sp |
| 10508 | .Vb 2 |
| 10509 | \& LDI r24, lo8(gs(<func>)) |
| 10510 | \& LDI r25, hi8(gs(<func>)) |
| 10511 | .Ve |
| 10512 | .IP "\-<The final location of that label is in a code segment>" 4 |
| 10513 | .IX Item "-<The final location of that label is in a code segment>" |
| 10514 | \&\fIoutside\fR the segment where the stubs are located. |
| 10515 | .RE |
| 10516 | .RS 4 |
| 10517 | .RE |
| 10518 | .IP "\(bu" 4 |
| 10519 | The compiler emits such \f(CW\*(C`gs\*(C'\fR modifiers for code labels in the |
| 10520 | following situations: |
| 10521 | .RS 4 |
| 10522 | .IP "\-<Taking address of a function or code label.>" 4 |
| 10523 | .IX Item "-<Taking address of a function or code label.>" |
| 10524 | .PD 0 |
| 10525 | .IP "\-<Computed goto.>" 4 |
| 10526 | .IX Item "-<Computed goto.>" |
| 10527 | .IP "\-<If prologue-save function is used, see \fB\-mcall\-prologues\fR>" 4 |
| 10528 | .IX Item "-<If prologue-save function is used, see -mcall-prologues>" |
| 10529 | .PD |
| 10530 | command-line option. |
| 10531 | .IP "\-<Switch/case dispatch tables. If you do not want such dispatch>" 4 |
| 10532 | .IX Item "-<Switch/case dispatch tables. If you do not want such dispatch>" |
| 10533 | tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. |
| 10534 | .IP "\-<C and \*(C+ constructors/destructors called during startup/shutdown.>" 4 |
| 10535 | .IX Item "-<C and constructors/destructors called during startup/shutdown.>" |
| 10536 | .PD 0 |
| 10537 | .ie n .IP "\-<If the tools hit a ""gs()"" modifier explained above.>" 4 |
| 10538 | .el .IP "\-<If the tools hit a \f(CWgs()\fR modifier explained above.>" 4 |
| 10539 | .IX Item "-<If the tools hit a gs() modifier explained above.>" |
| 10540 | .RE |
| 10541 | .RS 4 |
| 10542 | .RE |
| 10543 | .IP "\(bu" 4 |
| 10544 | .PD |
| 10545 | Jumping to non-symbolic addresses like so is \fInot\fR supported: |
| 10546 | .Sp |
| 10547 | .Vb 5 |
| 10548 | \& int main (void) |
| 10549 | \& { |
| 10550 | \& /* Call function at word address 0x2 */ |
| 10551 | \& return ((int(*)(void)) 0x2)(); |
| 10552 | \& } |
| 10553 | .Ve |
| 10554 | .Sp |
| 10555 | Instead, a stub has to be set up, i.e. the function has to be called |
| 10556 | through a symbol (\f(CW\*(C`func_4\*(C'\fR in the example): |
| 10557 | .Sp |
| 10558 | .Vb 3 |
| 10559 | \& int main (void) |
| 10560 | \& { |
| 10561 | \& extern int func_4 (void); |
| 10562 | \& |
| 10563 | \& /* Call function at byte address 0x4 */ |
| 10564 | \& return func_4(); |
| 10565 | \& } |
| 10566 | .Ve |
| 10567 | .Sp |
| 10568 | and the application be linked with \f(CW\*(C`\-Wl,\-\-defsym,func_4=0x4\*(C'\fR. |
| 10569 | Alternatively, \f(CW\*(C`func_4\*(C'\fR can be defined in the linker script. |
| 10570 | .PP |
| 10571 | Handling of the \f(CW\*(C`RAMPD\*(C'\fR, \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`RAMPY\*(C'\fR and \f(CW\*(C`RAMPZ\*(C'\fR Special Function Registers |
| 10572 | .IX Subsection "Handling of the RAMPD, RAMPX, RAMPY and RAMPZ Special Function Registers" |
| 10573 | .PP |
| 10574 | Some \s-1AVR\s0 devices support memories larger than the 64@tie{}KiB range |
| 10575 | that can be accessed with 16\-bit pointers. To access memory locations |
| 10576 | outside this 64@tie{}KiB range, the contentent of a \f(CW\*(C`RAMP\*(C'\fR |
| 10577 | register is used as high part of the address: |
| 10578 | The \f(CW\*(C`X\*(C'\fR, \f(CW\*(C`Y\*(C'\fR, \f(CW\*(C`Z\*(C'\fR address register is concatenated |
| 10579 | with the \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`RAMPY\*(C'\fR, \f(CW\*(C`RAMPZ\*(C'\fR special function |
| 10580 | register, respectively, to get a wide address. Similarly, |
| 10581 | \&\f(CW\*(C`RAMPD\*(C'\fR is used together with direct addressing. |
| 10582 | .IP "\(bu" 4 |
| 10583 | The startup code initializes the \f(CW\*(C`RAMP\*(C'\fR special function |
| 10584 | registers with zero. |
| 10585 | .IP "\(bu" 4 |
| 10586 | If a \fB\s-1AVR\s0 Named Address Spaces,named address space\fR other than |
| 10587 | generic or \f(CW\*(C`_\|_flash\*(C'\fR is used, then \f(CW\*(C`RAMPZ\*(C'\fR is set |
| 10588 | as needed before the operation. |
| 10589 | .IP "\(bu" 4 |
| 10590 | If the device supports \s-1RAM\s0 larger than 64@tie{KiB} and the compiler |
| 10591 | needs to change \f(CW\*(C`RAMPZ\*(C'\fR to accomplish an operation, \f(CW\*(C`RAMPZ\*(C'\fR |
| 10592 | is reset to zero after the operation. |
| 10593 | .IP "\(bu" 4 |
| 10594 | If the device comes with a specific \f(CW\*(C`RAMP\*(C'\fR register, the \s-1ISR\s0 |
| 10595 | prologue/epilogue saves/restores that \s-1SFR\s0 and initializes it with |
| 10596 | zero in case the \s-1ISR\s0 code might (implicitly) use it. |
| 10597 | .IP "\(bu" 4 |
| 10598 | \&\s-1RAM\s0 larger than 64@tie{KiB} is not supported by \s-1GCC\s0 for \s-1AVR\s0 targets. |
| 10599 | If you use inline assembler to read from locations outside the |
| 10600 | 16\-bit address range and change one of the \f(CW\*(C`RAMP\*(C'\fR registers, |
| 10601 | you must reset it to zero after the access. |
| 10602 | .PP |
| 10603 | \s-1AVR\s0 Built-in Macros |
| 10604 | .IX Subsection "AVR Built-in Macros" |
| 10605 | .PP |
| 10606 | \&\s-1GCC\s0 defines several built-in macros so that the user code can test |
| 10607 | for the presence or absence of features. Almost any of the following |
| 10608 | built-in macros are deduced from device capabilities and thus |
| 10609 | triggered by the \f(CW\*(C`\-mmcu=\*(C'\fR command-line option. |
| 10610 | .PP |
| 10611 | For even more AVR-specific built-in macros see |
| 10612 | \&\fB\s-1AVR\s0 Named Address Spaces\fR and \fB\s-1AVR\s0 Built-in Functions\fR. |
| 10613 | .ie n .IP """_\|_AVR_ARCH_\|_""" 4 |
| 10614 | .el .IP "\f(CW_\|_AVR_ARCH_\|_\fR" 4 |
| 10615 | .IX Item "__AVR_ARCH__" |
| 10616 | Build-in macro that resolves to a decimal number that identifies the |
| 10617 | architecture and depends on the \f(CW\*(C`\-mmcu=\f(CImcu\f(CW\*(C'\fR option. |
| 10618 | Possible values are: |
| 10619 | .Sp |
| 10620 | \&\f(CW2\fR, \f(CW25\fR, \f(CW3\fR, \f(CW31\fR, \f(CW35\fR, |
| 10621 | \&\f(CW4\fR, \f(CW5\fR, \f(CW51\fR, \f(CW6\fR, \f(CW102\fR, \f(CW104\fR, |
| 10622 | \&\f(CW105\fR, \f(CW106\fR, \f(CW107\fR |
| 10623 | .Sp |
| 10624 | for \fImcu\fR=\f(CW\*(C`avr2\*(C'\fR, \f(CW\*(C`avr25\*(C'\fR, \f(CW\*(C`avr3\*(C'\fR, |
| 10625 | \&\f(CW\*(C`avr31\*(C'\fR, \f(CW\*(C`avr35\*(C'\fR, \f(CW\*(C`avr4\*(C'\fR, \f(CW\*(C`avr5\*(C'\fR, \f(CW\*(C`avr51\*(C'\fR, |
| 10626 | \&\f(CW\*(C`avr6\*(C'\fR, \f(CW\*(C`avrxmega2\*(C'\fR, \f(CW\*(C`avrxmega4\*(C'\fR, \f(CW\*(C`avrxmega5\*(C'\fR, |
| 10627 | \&\f(CW\*(C`avrxmega6\*(C'\fR, \f(CW\*(C`avrxmega7\*(C'\fR, respectively. |
| 10628 | If \fImcu\fR specifies a device, this built-in macro is set |
| 10629 | accordingly. For example, with \f(CW\*(C`\-mmcu=atmega8\*(C'\fR the macro will be |
| 10630 | defined to \f(CW4\fR. |
| 10631 | .ie n .IP """_\|_AVR_\f(CIDevice\f(CW_\|_""" 4 |
| 10632 | .el .IP "\f(CW_\|_AVR_\f(CIDevice\f(CW_\|_\fR" 4 |
| 10633 | .IX Item "__AVR_Device__" |
| 10634 | Setting \f(CW\*(C`\-mmcu=\f(CIdevice\f(CW\*(C'\fR defines this built-in macro which reflects |
| 10635 | the device's name. For example, \f(CW\*(C`\-mmcu=atmega8\*(C'\fR defines the |
| 10636 | built-in macro \f(CW\*(C`_\|_AVR_ATmega8_\|_\*(C'\fR, \f(CW\*(C`\-mmcu=attiny261a\*(C'\fR defines |
| 10637 | \&\f(CW\*(C`_\|_AVR_ATtiny261A_\|_\*(C'\fR, etc. |
| 10638 | .Sp |
| 10639 | The built-in macros' names follow |
| 10640 | the scheme \f(CW\*(C`_\|_AVR_\f(CIDevice\f(CW_\|_\*(C'\fR where \fIDevice\fR is |
| 10641 | the device name as from the \s-1AVR\s0 user manual. The difference between |
| 10642 | \&\fIDevice\fR in the built-in macro and \fIdevice\fR in |
| 10643 | \&\f(CW\*(C`\-mmcu=\f(CIdevice\f(CW\*(C'\fR is that the latter is always lowercase. |
| 10644 | .Sp |
| 10645 | If \fIdevice\fR is not a device but only a core architecture like |
| 10646 | \&\f(CW\*(C`avr51\*(C'\fR, this macro will not be defined. |
| 10647 | .ie n .IP """_\|_AVR_XMEGA_\|_""" 4 |
| 10648 | .el .IP "\f(CW_\|_AVR_XMEGA_\|_\fR" 4 |
| 10649 | .IX Item "__AVR_XMEGA__" |
| 10650 | The device/architecture belongs to the \s-1XMEGA\s0 family of devices. |
| 10651 | .ie n .IP """_\|_AVR_HAVE_ELPM_\|_""" 4 |
| 10652 | .el .IP "\f(CW_\|_AVR_HAVE_ELPM_\|_\fR" 4 |
| 10653 | .IX Item "__AVR_HAVE_ELPM__" |
| 10654 | The device has the the \f(CW\*(C`ELPM\*(C'\fR instruction. |
| 10655 | .ie n .IP """_\|_AVR_HAVE_ELPMX_\|_""" 4 |
| 10656 | .el .IP "\f(CW_\|_AVR_HAVE_ELPMX_\|_\fR" 4 |
| 10657 | .IX Item "__AVR_HAVE_ELPMX__" |
| 10658 | The device has the \f(CW\*(C`ELPM R\f(CIn\f(CW,Z\*(C'\fR and \f(CW\*(C`ELPM |
| 10659 | R\f(CIn\f(CW,Z+\*(C'\fR instructions. |
| 10660 | .ie n .IP """_\|_AVR_HAVE_MOVW_\|_""" 4 |
| 10661 | .el .IP "\f(CW_\|_AVR_HAVE_MOVW_\|_\fR" 4 |
| 10662 | .IX Item "__AVR_HAVE_MOVW__" |
| 10663 | The device has the \f(CW\*(C`MOVW\*(C'\fR instruction to perform 16\-bit |
| 10664 | register-register moves. |
| 10665 | .ie n .IP """_\|_AVR_HAVE_LPMX_\|_""" 4 |
| 10666 | .el .IP "\f(CW_\|_AVR_HAVE_LPMX_\|_\fR" 4 |
| 10667 | .IX Item "__AVR_HAVE_LPMX__" |
| 10668 | The device has the \f(CW\*(C`LPM R\f(CIn\f(CW,Z\*(C'\fR and |
| 10669 | \&\f(CW\*(C`LPM R\f(CIn\f(CW,Z+\*(C'\fR instructions. |
| 10670 | .ie n .IP """_\|_AVR_HAVE_MUL_\|_""" 4 |
| 10671 | .el .IP "\f(CW_\|_AVR_HAVE_MUL_\|_\fR" 4 |
| 10672 | .IX Item "__AVR_HAVE_MUL__" |
| 10673 | The device has a hardware multiplier. |
| 10674 | .ie n .IP """_\|_AVR_HAVE_JMP_CALL_\|_""" 4 |
| 10675 | .el .IP "\f(CW_\|_AVR_HAVE_JMP_CALL_\|_\fR" 4 |
| 10676 | .IX Item "__AVR_HAVE_JMP_CALL__" |
| 10677 | The device has the \f(CW\*(C`JMP\*(C'\fR and \f(CW\*(C`CALL\*(C'\fR instructions. |
| 10678 | This is the case for devices with at least 16@tie{}KiB of program |
| 10679 | memory and if \f(CW\*(C`\-mshort\-calls\*(C'\fR is not set. |
| 10680 | .ie n .IP """_\|_AVR_HAVE_EIJMP_EICALL_\|_""" 4 |
| 10681 | .el .IP "\f(CW_\|_AVR_HAVE_EIJMP_EICALL_\|_\fR" 4 |
| 10682 | .IX Item "__AVR_HAVE_EIJMP_EICALL__" |
| 10683 | .PD 0 |
| 10684 | .ie n .IP """_\|_AVR_3_BYTE_PC_\|_""" 4 |
| 10685 | .el .IP "\f(CW_\|_AVR_3_BYTE_PC_\|_\fR" 4 |
| 10686 | .IX Item "__AVR_3_BYTE_PC__" |
| 10687 | .PD |
| 10688 | The device has the \f(CW\*(C`EIJMP\*(C'\fR and \f(CW\*(C`EICALL\*(C'\fR instructions. |
| 10689 | This is the case for devices with more than 128@tie{}KiB of program memory. |
| 10690 | This also means that the program counter |
| 10691 | (\s-1PC\s0) is 3@tie{}bytes wide. |
| 10692 | .ie n .IP """_\|_AVR_2_BYTE_PC_\|_""" 4 |
| 10693 | .el .IP "\f(CW_\|_AVR_2_BYTE_PC_\|_\fR" 4 |
| 10694 | .IX Item "__AVR_2_BYTE_PC__" |
| 10695 | The program counter (\s-1PC\s0) is 2@tie{}bytes wide. This is the case for devices |
| 10696 | with up to 128@tie{}KiB of program memory. |
| 10697 | .ie n .IP """_\|_AVR_HAVE_8BIT_SP_\|_""" 4 |
| 10698 | .el .IP "\f(CW_\|_AVR_HAVE_8BIT_SP_\|_\fR" 4 |
| 10699 | .IX Item "__AVR_HAVE_8BIT_SP__" |
| 10700 | .PD 0 |
| 10701 | .ie n .IP """_\|_AVR_HAVE_16BIT_SP_\|_""" 4 |
| 10702 | .el .IP "\f(CW_\|_AVR_HAVE_16BIT_SP_\|_\fR" 4 |
| 10703 | .IX Item "__AVR_HAVE_16BIT_SP__" |
| 10704 | .PD |
| 10705 | The stack pointer (\s-1SP\s0) register is treated as 8\-bit respectively |
| 10706 | 16\-bit register by the compiler. |
| 10707 | The definition of these macros is affected by \f(CW\*(C`\-mtiny\-stack\*(C'\fR. |
| 10708 | .ie n .IP """_\|_AVR_HAVE_SPH_\|_""" 4 |
| 10709 | .el .IP "\f(CW_\|_AVR_HAVE_SPH_\|_\fR" 4 |
| 10710 | .IX Item "__AVR_HAVE_SPH__" |
| 10711 | .PD 0 |
| 10712 | .ie n .IP """_\|_AVR_SP8_\|_""" 4 |
| 10713 | .el .IP "\f(CW_\|_AVR_SP8_\|_\fR" 4 |
| 10714 | .IX Item "__AVR_SP8__" |
| 10715 | .PD |
| 10716 | The device has the \s-1SPH\s0 (high part of stack pointer) special function |
| 10717 | register or has an 8\-bit stack pointer, respectively. |
| 10718 | The definition of these macros is affected by \f(CW\*(C`\-mmcu=\*(C'\fR and |
| 10719 | in the cases of \f(CW\*(C`\-mmcu=avr2\*(C'\fR and \f(CW\*(C`\-mmcu=avr25\*(C'\fR also |
| 10720 | by \f(CW\*(C`\-msp8\*(C'\fR. |
| 10721 | .ie n .IP """_\|_AVR_HAVE_RAMPD_\|_""" 4 |
| 10722 | .el .IP "\f(CW_\|_AVR_HAVE_RAMPD_\|_\fR" 4 |
| 10723 | .IX Item "__AVR_HAVE_RAMPD__" |
| 10724 | .PD 0 |
| 10725 | .ie n .IP """_\|_AVR_HAVE_RAMPX_\|_""" 4 |
| 10726 | .el .IP "\f(CW_\|_AVR_HAVE_RAMPX_\|_\fR" 4 |
| 10727 | .IX Item "__AVR_HAVE_RAMPX__" |
| 10728 | .ie n .IP """_\|_AVR_HAVE_RAMPY_\|_""" 4 |
| 10729 | .el .IP "\f(CW_\|_AVR_HAVE_RAMPY_\|_\fR" 4 |
| 10730 | .IX Item "__AVR_HAVE_RAMPY__" |
| 10731 | .ie n .IP """_\|_AVR_HAVE_RAMPZ_\|_""" 4 |
| 10732 | .el .IP "\f(CW_\|_AVR_HAVE_RAMPZ_\|_\fR" 4 |
| 10733 | .IX Item "__AVR_HAVE_RAMPZ__" |
| 10734 | .PD |
| 10735 | The device has the \f(CW\*(C`RAMPD\*(C'\fR, \f(CW\*(C`RAMPX\*(C'\fR, \f(CW\*(C`RAMPY\*(C'\fR, |
| 10736 | \&\f(CW\*(C`RAMPZ\*(C'\fR special function register, respectively. |
| 10737 | .ie n .IP """_\|_NO_INTERRUPTS_\|_""" 4 |
| 10738 | .el .IP "\f(CW_\|_NO_INTERRUPTS_\|_\fR" 4 |
| 10739 | .IX Item "__NO_INTERRUPTS__" |
| 10740 | This macro reflects the \f(CW\*(C`\-mno\-interrupts\*(C'\fR command line option. |
| 10741 | .ie n .IP """_\|_AVR_ERRATA_SKIP_\|_""" 4 |
| 10742 | .el .IP "\f(CW_\|_AVR_ERRATA_SKIP_\|_\fR" 4 |
| 10743 | .IX Item "__AVR_ERRATA_SKIP__" |
| 10744 | .PD 0 |
| 10745 | .ie n .IP """_\|_AVR_ERRATA_SKIP_JMP_CALL_\|_""" 4 |
| 10746 | .el .IP "\f(CW_\|_AVR_ERRATA_SKIP_JMP_CALL_\|_\fR" 4 |
| 10747 | .IX Item "__AVR_ERRATA_SKIP_JMP_CALL__" |
| 10748 | .PD |
| 10749 | Some \s-1AVR\s0 devices (\s-1AT90S8515\s0, ATmega103) must not skip 32\-bit |
| 10750 | instructions because of a hardware erratum. Skip instructions are |
| 10751 | \&\f(CW\*(C`SBRS\*(C'\fR, \f(CW\*(C`SBRC\*(C'\fR, \f(CW\*(C`SBIS\*(C'\fR, \f(CW\*(C`SBIC\*(C'\fR and \f(CW\*(C`CPSE\*(C'\fR. |
| 10752 | The second macro is only defined if \f(CW\*(C`_\|_AVR_HAVE_JMP_CALL_\|_\*(C'\fR is also |
| 10753 | set. |
| 10754 | .ie n .IP """_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW""" 4 |
| 10755 | .el .IP "\f(CW_\|_AVR_SFR_OFFSET_\|_=\f(CIoffset\f(CW\fR" 4 |
| 10756 | .IX Item "__AVR_SFR_OFFSET__=offset" |
| 10757 | Instructions that can address I/O special function registers directly |
| 10758 | like \f(CW\*(C`IN\*(C'\fR, \f(CW\*(C`OUT\*(C'\fR, \f(CW\*(C`SBI\*(C'\fR, etc. may use a different |
| 10759 | address as if addressed by an instruction to access \s-1RAM\s0 like \f(CW\*(C`LD\*(C'\fR |
| 10760 | or \f(CW\*(C`STS\*(C'\fR. This offset depends on the device architecture and has |
| 10761 | to be subtracted from the \s-1RAM\s0 address in order to get the |
| 10762 | respective I/O@tie{}address. |
| 10763 | .ie n .IP """_\|_WITH_AVRLIBC_\|_""" 4 |
| 10764 | .el .IP "\f(CW_\|_WITH_AVRLIBC_\|_\fR" 4 |
| 10765 | .IX Item "__WITH_AVRLIBC__" |
| 10766 | The compiler is configured to be used together with AVR-Libc. |
| 10767 | See the \f(CW\*(C`\-\-with\-avrlibc\*(C'\fR configure option. |
| 10768 | .PP |
| 10769 | \fIBlackfin Options\fR |
| 10770 | .IX Subsection "Blackfin Options" |
| 10771 | .IP "\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR]" 4 |
| 10772 | .IX Item "-mcpu=cpu[-sirevision]" |
| 10773 | Specifies the name of the target Blackfin processor. Currently, \fIcpu\fR |
| 10774 | can be one of \fBbf512\fR, \fBbf514\fR, \fBbf516\fR, \fBbf518\fR, |
| 10775 | \&\fBbf522\fR, \fBbf523\fR, \fBbf524\fR, \fBbf525\fR, \fBbf526\fR, |
| 10776 | \&\fBbf527\fR, \fBbf531\fR, \fBbf532\fR, \fBbf533\fR, |
| 10777 | \&\fBbf534\fR, \fBbf536\fR, \fBbf537\fR, \fBbf538\fR, \fBbf539\fR, |
| 10778 | \&\fBbf542\fR, \fBbf544\fR, \fBbf547\fR, \fBbf548\fR, \fBbf549\fR, |
| 10779 | \&\fBbf542m\fR, \fBbf544m\fR, \fBbf547m\fR, \fBbf548m\fR, \fBbf549m\fR, |
| 10780 | \&\fBbf561\fR, \fBbf592\fR. |
| 10781 | The optional \fIsirevision\fR specifies the silicon revision of the target |
| 10782 | Blackfin processor. Any workarounds available for the targeted silicon revision |
| 10783 | will be enabled. If \fIsirevision\fR is \fBnone\fR, no workarounds are enabled. |
| 10784 | If \fIsirevision\fR is \fBany\fR, all workarounds for the targeted processor |
| 10785 | will be enabled. The \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR macro is defined to two |
| 10786 | hexadecimal digits representing the major and minor numbers in the silicon |
| 10787 | revision. If \fIsirevision\fR is \fBnone\fR, the \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR |
| 10788 | is not defined. If \fIsirevision\fR is \fBany\fR, the |
| 10789 | \&\f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR is defined to be \f(CW0xffff\fR. |
| 10790 | If this optional \fIsirevision\fR is not used, \s-1GCC\s0 assumes the latest known |
| 10791 | silicon revision of the targeted Blackfin processor. |
| 10792 | .Sp |
| 10793 | Support for \fBbf561\fR is incomplete. For \fBbf561\fR, |
| 10794 | Only the processor macro is defined. |
| 10795 | Without this option, \fBbf532\fR is used as the processor by default. |
| 10796 | The corresponding predefined processor macros for \fIcpu\fR is to |
| 10797 | be defined. And for \fBbfin-elf\fR toolchain, this causes the hardware \s-1BSP\s0 |
| 10798 | provided by libgloss to be linked in if \fB\-msim\fR is not given. |
| 10799 | .IP "\fB\-msim\fR" 4 |
| 10800 | .IX Item "-msim" |
| 10801 | Specifies that the program will be run on the simulator. This causes |
| 10802 | the simulator \s-1BSP\s0 provided by libgloss to be linked in. This option |
| 10803 | has effect only for \fBbfin-elf\fR toolchain. |
| 10804 | Certain other options, such as \fB\-mid\-shared\-library\fR and |
| 10805 | \&\fB\-mfdpic\fR, imply \fB\-msim\fR. |
| 10806 | .IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 |
| 10807 | .IX Item "-momit-leaf-frame-pointer" |
| 10808 | Don't keep the frame pointer in a register for leaf functions. This |
| 10809 | avoids the instructions to save, set up and restore frame pointers and |
| 10810 | makes an extra register available in leaf functions. The option |
| 10811 | \&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions, |
| 10812 | which might make debugging harder. |
| 10813 | .IP "\fB\-mspecld\-anomaly\fR" 4 |
| 10814 | .IX Item "-mspecld-anomaly" |
| 10815 | When enabled, the compiler will ensure that the generated code does not |
| 10816 | contain speculative loads after jump instructions. If this option is used, |
| 10817 | \&\f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_LOADS\*(C'\fR is defined. |
| 10818 | .IP "\fB\-mno\-specld\-anomaly\fR" 4 |
| 10819 | .IX Item "-mno-specld-anomaly" |
| 10820 | Don't generate extra code to prevent speculative loads from occurring. |
| 10821 | .IP "\fB\-mcsync\-anomaly\fR" 4 |
| 10822 | .IX Item "-mcsync-anomaly" |
| 10823 | When enabled, the compiler will ensure that the generated code does not |
| 10824 | contain \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions too soon after conditional branches. |
| 10825 | If this option is used, \f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_SYNCS\*(C'\fR is defined. |
| 10826 | .IP "\fB\-mno\-csync\-anomaly\fR" 4 |
| 10827 | .IX Item "-mno-csync-anomaly" |
| 10828 | Don't generate extra code to prevent \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions from |
| 10829 | occurring too soon after a conditional branch. |
| 10830 | .IP "\fB\-mlow\-64k\fR" 4 |
| 10831 | .IX Item "-mlow-64k" |
| 10832 | When enabled, the compiler is free to take advantage of the knowledge that |
| 10833 | the entire program fits into the low 64k of memory. |
| 10834 | .IP "\fB\-mno\-low\-64k\fR" 4 |
| 10835 | .IX Item "-mno-low-64k" |
| 10836 | Assume that the program is arbitrarily large. This is the default. |
| 10837 | .IP "\fB\-mstack\-check\-l1\fR" 4 |
| 10838 | .IX Item "-mstack-check-l1" |
| 10839 | Do stack checking using information placed into L1 scratchpad memory by the |
| 10840 | uClinux kernel. |
| 10841 | .IP "\fB\-mid\-shared\-library\fR" 4 |
| 10842 | .IX Item "-mid-shared-library" |
| 10843 | Generate code that supports shared libraries via the library \s-1ID\s0 method. |
| 10844 | This allows for execute in place and shared libraries in an environment |
| 10845 | without virtual memory management. This option implies \fB\-fPIC\fR. |
| 10846 | With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. |
| 10847 | .IP "\fB\-mno\-id\-shared\-library\fR" 4 |
| 10848 | .IX Item "-mno-id-shared-library" |
| 10849 | Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used. |
| 10850 | This is the default. |
| 10851 | .IP "\fB\-mleaf\-id\-shared\-library\fR" 4 |
| 10852 | .IX Item "-mleaf-id-shared-library" |
| 10853 | Generate code that supports shared libraries via the library \s-1ID\s0 method, |
| 10854 | but assumes that this library or executable won't link against any other |
| 10855 | \&\s-1ID\s0 shared libraries. That allows the compiler to use faster code for jumps |
| 10856 | and calls. |
| 10857 | .IP "\fB\-mno\-leaf\-id\-shared\-library\fR" 4 |
| 10858 | .IX Item "-mno-leaf-id-shared-library" |
| 10859 | Do not assume that the code being compiled won't link against any \s-1ID\s0 shared |
| 10860 | libraries. Slower code will be generated for jump and call insns. |
| 10861 | .IP "\fB\-mshared\-library\-id=n\fR" 4 |
| 10862 | .IX Item "-mshared-library-id=n" |
| 10863 | Specified the identification number of the \s-1ID\s0 based shared library being |
| 10864 | compiled. Specifying a value of 0 will generate more compact code, specifying |
| 10865 | other values will force the allocation of that number to the current |
| 10866 | library but is no more space or time efficient than omitting this option. |
| 10867 | .IP "\fB\-msep\-data\fR" 4 |
| 10868 | .IX Item "-msep-data" |
| 10869 | Generate code that allows the data segment to be located in a different |
| 10870 | area of memory from the text segment. This allows for execute in place in |
| 10871 | an environment without virtual memory management by eliminating relocations |
| 10872 | against the text section. |
| 10873 | .IP "\fB\-mno\-sep\-data\fR" 4 |
| 10874 | .IX Item "-mno-sep-data" |
| 10875 | Generate code that assumes that the data segment follows the text segment. |
| 10876 | This is the default. |
| 10877 | .IP "\fB\-mlong\-calls\fR" 4 |
| 10878 | .IX Item "-mlong-calls" |
| 10879 | .PD 0 |
| 10880 | .IP "\fB\-mno\-long\-calls\fR" 4 |
| 10881 | .IX Item "-mno-long-calls" |
| 10882 | .PD |
| 10883 | Tells the compiler to perform function calls by first loading the |
| 10884 | address of the function into a register and then performing a subroutine |
| 10885 | call on this register. This switch is needed if the target function |
| 10886 | lies outside of the 24\-bit addressing range of the offset-based |
| 10887 | version of subroutine call instruction. |
| 10888 | .Sp |
| 10889 | This feature is not enabled by default. Specifying |
| 10890 | \&\fB\-mno\-long\-calls\fR will restore the default behavior. Note these |
| 10891 | switches have no effect on how the compiler generates code to handle |
| 10892 | function calls via function pointers. |
| 10893 | .IP "\fB\-mfast\-fp\fR" 4 |
| 10894 | .IX Item "-mfast-fp" |
| 10895 | Link with the fast floating-point library. This library relaxes some of |
| 10896 | the \s-1IEEE\s0 floating-point standard's rules for checking inputs against |
| 10897 | Not-a-Number (\s-1NAN\s0), in the interest of performance. |
| 10898 | .IP "\fB\-minline\-plt\fR" 4 |
| 10899 | .IX Item "-minline-plt" |
| 10900 | Enable inlining of \s-1PLT\s0 entries in function calls to functions that are |
| 10901 | not known to bind locally. It has no effect without \fB\-mfdpic\fR. |
| 10902 | .IP "\fB\-mmulticore\fR" 4 |
| 10903 | .IX Item "-mmulticore" |
| 10904 | Build standalone application for multicore Blackfin processor. Proper |
| 10905 | start files and link scripts will be used to support multicore. |
| 10906 | This option defines \f(CW\*(C`_\|_BFIN_MULTICORE\*(C'\fR. It can only be used with |
| 10907 | \&\fB\-mcpu=bf561\fR[\fB\-\fR\fIsirevision\fR]. It can be used with |
| 10908 | \&\fB\-mcorea\fR or \fB\-mcoreb\fR. If it's used without |
| 10909 | \&\fB\-mcorea\fR or \fB\-mcoreb\fR, single application/dual core |
| 10910 | programming model is used. In this model, the main function of Core B |
| 10911 | should be named as coreb_main. If it's used with \fB\-mcorea\fR or |
| 10912 | \&\fB\-mcoreb\fR, one application per core programming model is used. |
| 10913 | If this option is not used, single core application programming |
| 10914 | model is used. |
| 10915 | .IP "\fB\-mcorea\fR" 4 |
| 10916 | .IX Item "-mcorea" |
| 10917 | Build standalone application for Core A of \s-1BF561\s0 when using |
| 10918 | one application per core programming model. Proper start files |
| 10919 | and link scripts will be used to support Core A. This option |
| 10920 | defines \f(CW\*(C`_\|_BFIN_COREA\*(C'\fR. It must be used with \fB\-mmulticore\fR. |
| 10921 | .IP "\fB\-mcoreb\fR" 4 |
| 10922 | .IX Item "-mcoreb" |
| 10923 | Build standalone application for Core B of \s-1BF561\s0 when using |
| 10924 | one application per core programming model. Proper start files |
| 10925 | and link scripts will be used to support Core B. This option |
| 10926 | defines \f(CW\*(C`_\|_BFIN_COREB\*(C'\fR. When this option is used, coreb_main |
| 10927 | should be used instead of main. It must be used with |
| 10928 | \&\fB\-mmulticore\fR. |
| 10929 | .IP "\fB\-msdram\fR" 4 |
| 10930 | .IX Item "-msdram" |
| 10931 | Build standalone application for \s-1SDRAM\s0. Proper start files and |
| 10932 | link scripts will be used to put the application into \s-1SDRAM\s0. |
| 10933 | Loader should initialize \s-1SDRAM\s0 before loading the application |
| 10934 | into \s-1SDRAM\s0. This option defines \f(CW\*(C`_\|_BFIN_SDRAM\*(C'\fR. |
| 10935 | .IP "\fB\-micplb\fR" 4 |
| 10936 | .IX Item "-micplb" |
| 10937 | Assume that ICPLBs are enabled at run time. This has an effect on certain |
| 10938 | anomaly workarounds. For Linux targets, the default is to assume ICPLBs |
| 10939 | are enabled; for standalone applications the default is off. |
| 10940 | .PP |
| 10941 | \fIC6X Options\fR |
| 10942 | .IX Subsection "C6X Options" |
| 10943 | .IP "\fB\-march=\fR\fIname\fR" 4 |
| 10944 | .IX Item "-march=name" |
| 10945 | This specifies the name of the target architecture. \s-1GCC\s0 uses this |
| 10946 | name to determine what kind of instructions it can emit when generating |
| 10947 | assembly code. Permissible names are: \fBc62x\fR, |
| 10948 | \&\fBc64x\fR, \fBc64x+\fR, \fBc67x\fR, \fBc67x+\fR, \fBc674x\fR. |
| 10949 | .IP "\fB\-mbig\-endian\fR" 4 |
| 10950 | .IX Item "-mbig-endian" |
| 10951 | Generate code for a big-endian target. |
| 10952 | .IP "\fB\-mlittle\-endian\fR" 4 |
| 10953 | .IX Item "-mlittle-endian" |
| 10954 | Generate code for a little-endian target. This is the default. |
| 10955 | .IP "\fB\-msim\fR" 4 |
| 10956 | .IX Item "-msim" |
| 10957 | Choose startup files and linker script suitable for the simulator. |
| 10958 | .IP "\fB\-msdata=default\fR" 4 |
| 10959 | .IX Item "-msdata=default" |
| 10960 | Put small global and static data in the \fB.neardata\fR section, |
| 10961 | which is pointed to by register \f(CW\*(C`B14\*(C'\fR. Put small uninitialized |
| 10962 | global and static data in the \fB.bss\fR section, which is adjacent |
| 10963 | to the \fB.neardata\fR section. Put small read-only data into the |
| 10964 | \&\fB.rodata\fR section. The corresponding sections used for large |
| 10965 | pieces of data are \fB.fardata\fR, \fB.far\fR and \fB.const\fR. |
| 10966 | .IP "\fB\-msdata=all\fR" 4 |
| 10967 | .IX Item "-msdata=all" |
| 10968 | Put all data, not just small objets, into the sections reserved for |
| 10969 | small data, and use addressing relative to the \f(CW\*(C`B14\*(C'\fR register to |
| 10970 | access them. |
| 10971 | .IP "\fB\-msdata=none\fR" 4 |
| 10972 | .IX Item "-msdata=none" |
| 10973 | Make no use of the sections reserved for small data, and use absolute |
| 10974 | addresses to access all data. Put all initialized global and static |
| 10975 | data in the \fB.fardata\fR section, and all uninitialized data in the |
| 10976 | \&\fB.far\fR section. Put all constant data into the \fB.const\fR |
| 10977 | section. |
| 10978 | .PP |
| 10979 | \fI\s-1CRIS\s0 Options\fR |
| 10980 | .IX Subsection "CRIS Options" |
| 10981 | .PP |
| 10982 | These options are defined specifically for the \s-1CRIS\s0 ports. |
| 10983 | .IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 |
| 10984 | .IX Item "-march=architecture-type" |
| 10985 | .PD 0 |
| 10986 | .IP "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4 |
| 10987 | .IX Item "-mcpu=architecture-type" |
| 10988 | .PD |
| 10989 | Generate code for the specified architecture. The choices for |
| 10990 | \&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for |
| 10991 | respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0. |
| 10992 | Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is |
| 10993 | \&\fBv10\fR. |
| 10994 | .IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4 |
| 10995 | .IX Item "-mtune=architecture-type" |
| 10996 | Tune to \fIarchitecture-type\fR everything applicable about the generated |
| 10997 | code, except for the \s-1ABI\s0 and the set of available instructions. The |
| 10998 | choices for \fIarchitecture-type\fR are the same as for |
| 10999 | \&\fB\-march=\fR\fIarchitecture-type\fR. |
| 11000 | .IP "\fB\-mmax\-stack\-frame=\fR\fIn\fR" 4 |
| 11001 | .IX Item "-mmax-stack-frame=n" |
| 11002 | Warn when the stack frame of a function exceeds \fIn\fR bytes. |
| 11003 | .IP "\fB\-metrax4\fR" 4 |
| 11004 | .IX Item "-metrax4" |
| 11005 | .PD 0 |
| 11006 | .IP "\fB\-metrax100\fR" 4 |
| 11007 | .IX Item "-metrax100" |
| 11008 | .PD |
| 11009 | The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for |
| 11010 | \&\fB\-march=v3\fR and \fB\-march=v8\fR respectively. |
| 11011 | .IP "\fB\-mmul\-bug\-workaround\fR" 4 |
| 11012 | .IX Item "-mmul-bug-workaround" |
| 11013 | .PD 0 |
| 11014 | .IP "\fB\-mno\-mul\-bug\-workaround\fR" 4 |
| 11015 | .IX Item "-mno-mul-bug-workaround" |
| 11016 | .PD |
| 11017 | Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0 |
| 11018 | models where it applies. This option is active by default. |
| 11019 | .IP "\fB\-mpdebug\fR" 4 |
| 11020 | .IX Item "-mpdebug" |
| 11021 | Enable CRIS-specific verbose debug-related information in the assembly |
| 11022 | code. This option also has the effect to turn off the \fB#NO_APP\fR |
| 11023 | formatted-code indicator to the assembler at the beginning of the |
| 11024 | assembly file. |
| 11025 | .IP "\fB\-mcc\-init\fR" 4 |
| 11026 | .IX Item "-mcc-init" |
| 11027 | Do not use condition-code results from previous instruction; always emit |
| 11028 | compare and test instructions before use of condition codes. |
| 11029 | .IP "\fB\-mno\-side\-effects\fR" 4 |
| 11030 | .IX Item "-mno-side-effects" |
| 11031 | Do not emit instructions with side-effects in addressing modes other than |
| 11032 | post-increment. |
| 11033 | .IP "\fB\-mstack\-align\fR" 4 |
| 11034 | .IX Item "-mstack-align" |
| 11035 | .PD 0 |
| 11036 | .IP "\fB\-mno\-stack\-align\fR" 4 |
| 11037 | .IX Item "-mno-stack-align" |
| 11038 | .IP "\fB\-mdata\-align\fR" 4 |
| 11039 | .IX Item "-mdata-align" |
| 11040 | .IP "\fB\-mno\-data\-align\fR" 4 |
| 11041 | .IX Item "-mno-data-align" |
| 11042 | .IP "\fB\-mconst\-align\fR" 4 |
| 11043 | .IX Item "-mconst-align" |
| 11044 | .IP "\fB\-mno\-const\-align\fR" 4 |
| 11045 | .IX Item "-mno-const-align" |
| 11046 | .PD |
| 11047 | These options (no-options) arranges (eliminate arrangements) for the |
| 11048 | stack-frame, individual data and constants to be aligned for the maximum |
| 11049 | single data access size for the chosen \s-1CPU\s0 model. The default is to |
| 11050 | arrange for 32\-bit alignment. \s-1ABI\s0 details such as structure layout are |
| 11051 | not affected by these options. |
| 11052 | .IP "\fB\-m32\-bit\fR" 4 |
| 11053 | .IX Item "-m32-bit" |
| 11054 | .PD 0 |
| 11055 | .IP "\fB\-m16\-bit\fR" 4 |
| 11056 | .IX Item "-m16-bit" |
| 11057 | .IP "\fB\-m8\-bit\fR" 4 |
| 11058 | .IX Item "-m8-bit" |
| 11059 | .PD |
| 11060 | Similar to the stack\- data\- and const-align options above, these options |
| 11061 | arrange for stack-frame, writable data and constants to all be 32\-bit, |
| 11062 | 16\-bit or 8\-bit aligned. The default is 32\-bit alignment. |
| 11063 | .IP "\fB\-mno\-prologue\-epilogue\fR" 4 |
| 11064 | .IX Item "-mno-prologue-epilogue" |
| 11065 | .PD 0 |
| 11066 | .IP "\fB\-mprologue\-epilogue\fR" 4 |
| 11067 | .IX Item "-mprologue-epilogue" |
| 11068 | .PD |
| 11069 | With \fB\-mno\-prologue\-epilogue\fR, the normal function prologue and |
| 11070 | epilogue which set up the stack frame are omitted and no return |
| 11071 | instructions or return sequences are generated in the code. Use this |
| 11072 | option only together with visual inspection of the compiled code: no |
| 11073 | warnings or errors are generated when call-saved registers must be saved, |
| 11074 | or storage for local variable needs to be allocated. |
| 11075 | .IP "\fB\-mno\-gotplt\fR" 4 |
| 11076 | .IX Item "-mno-gotplt" |
| 11077 | .PD 0 |
| 11078 | .IP "\fB\-mgotplt\fR" 4 |
| 11079 | .IX Item "-mgotplt" |
| 11080 | .PD |
| 11081 | With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate) |
| 11082 | instruction sequences that load addresses for functions from the \s-1PLT\s0 part |
| 11083 | of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the |
| 11084 | \&\s-1PLT\s0. The default is \fB\-mgotplt\fR. |
| 11085 | .IP "\fB\-melf\fR" 4 |
| 11086 | .IX Item "-melf" |
| 11087 | Legacy no-op option only recognized with the cris-axis-elf and |
| 11088 | cris-axis-linux-gnu targets. |
| 11089 | .IP "\fB\-mlinux\fR" 4 |
| 11090 | .IX Item "-mlinux" |
| 11091 | Legacy no-op option only recognized with the cris-axis-linux-gnu target. |
| 11092 | .IP "\fB\-sim\fR" 4 |
| 11093 | .IX Item "-sim" |
| 11094 | This option, recognized for the cris-axis-elf arranges |
| 11095 | to link with input-output functions from a simulator library. Code, |
| 11096 | initialized data and zero-initialized data are allocated consecutively. |
| 11097 | .IP "\fB\-sim2\fR" 4 |
| 11098 | .IX Item "-sim2" |
| 11099 | Like \fB\-sim\fR, but pass linker options to locate initialized data at |
| 11100 | 0x40000000 and zero-initialized data at 0x80000000. |
| 11101 | .PP |
| 11102 | \fI\s-1CR16\s0 Options\fR |
| 11103 | .IX Subsection "CR16 Options" |
| 11104 | .PP |
| 11105 | These options are defined specifically for the \s-1CR16\s0 ports. |
| 11106 | .IP "\fB\-mmac\fR" 4 |
| 11107 | .IX Item "-mmac" |
| 11108 | Enable the use of multiply-accumulate instructions. Disabled by default. |
| 11109 | .IP "\fB\-mcr16cplus\fR" 4 |
| 11110 | .IX Item "-mcr16cplus" |
| 11111 | .PD 0 |
| 11112 | .IP "\fB\-mcr16c\fR" 4 |
| 11113 | .IX Item "-mcr16c" |
| 11114 | .PD |
| 11115 | Generate code for \s-1CR16C\s0 or \s-1CR16C+\s0 architecture. \s-1CR16C+\s0 architecture |
| 11116 | is default. |
| 11117 | .IP "\fB\-msim\fR" 4 |
| 11118 | .IX Item "-msim" |
| 11119 | Links the library libsim.a which is in compatible with simulator. Applicable |
| 11120 | to elf compiler only. |
| 11121 | .IP "\fB\-mint32\fR" 4 |
| 11122 | .IX Item "-mint32" |
| 11123 | Choose integer type as 32\-bit wide. |
| 11124 | .IP "\fB\-mbit\-ops\fR" 4 |
| 11125 | .IX Item "-mbit-ops" |
| 11126 | Generates sbit/cbit instructions for bit manipulations. |
| 11127 | .IP "\fB\-mdata\-model=\fR\fImodel\fR" 4 |
| 11128 | .IX Item "-mdata-model=model" |
| 11129 | Choose a data model. The choices for \fImodel\fR are \fBnear\fR, |
| 11130 | \&\fBfar\fR or \fBmedium\fR. \fBmedium\fR is default. |
| 11131 | However, \fBfar\fR is not valid when \-mcr16c option is chosen as |
| 11132 | \&\s-1CR16C\s0 architecture does not support far data model. |
| 11133 | .PP |
| 11134 | \fIDarwin Options\fR |
| 11135 | .IX Subsection "Darwin Options" |
| 11136 | .PP |
| 11137 | These options are defined for all architectures running the Darwin operating |
| 11138 | system. |
| 11139 | .PP |
| 11140 | \&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it will create |
| 11141 | an object file for the single architecture that it was built to |
| 11142 | target. Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple |
| 11143 | \&\fB\-arch\fR options are used; it does so by running the compiler or |
| 11144 | linker multiple times and joining the results together with |
| 11145 | \&\fIlipo\fR. |
| 11146 | .PP |
| 11147 | The subtype of the file created (like \fBppc7400\fR or \fBppc970\fR or |
| 11148 | \&\fBi686\fR) is determined by the flags that specify the \s-1ISA\s0 |
| 11149 | that \s-1GCC\s0 is targetting, like \fB\-mcpu\fR or \fB\-march\fR. The |
| 11150 | \&\fB\-force_cpusubtype_ALL\fR option can be used to override this. |
| 11151 | .PP |
| 11152 | The Darwin tools vary in their behavior when presented with an \s-1ISA\s0 |
| 11153 | mismatch. The assembler, \fIas\fR, will only permit instructions to |
| 11154 | be used that are valid for the subtype of the file it is generating, |
| 11155 | so you cannot put 64\-bit instructions in a \fBppc750\fR object file. |
| 11156 | The linker for shared libraries, \fI/usr/bin/libtool\fR, will fail |
| 11157 | and print an error if asked to create a shared library with a less |
| 11158 | restrictive subtype than its input files (for instance, trying to put |
| 11159 | a \fBppc970\fR object file in a \fBppc7400\fR library). The linker |
| 11160 | for executables, \fIld\fR, will quietly give the executable the most |
| 11161 | restrictive subtype of any of its input files. |
| 11162 | .IP "\fB\-F\fR\fIdir\fR" 4 |
| 11163 | .IX Item "-Fdir" |
| 11164 | Add the framework directory \fIdir\fR to the head of the list of |
| 11165 | directories to be searched for header files. These directories are |
| 11166 | interleaved with those specified by \fB\-I\fR options and are |
| 11167 | scanned in a left-to-right order. |
| 11168 | .Sp |
| 11169 | A framework directory is a directory with frameworks in it. A |
| 11170 | framework is a directory with a \fB\*(L"Headers\*(R"\fR and/or |
| 11171 | \&\fB\*(L"PrivateHeaders\*(R"\fR directory contained directly in it that ends |
| 11172 | in \fB\*(L".framework\*(R"\fR. The name of a framework is the name of this |
| 11173 | directory excluding the \fB\*(L".framework\*(R"\fR. Headers associated with |
| 11174 | the framework are found in one of those two directories, with |
| 11175 | \&\fB\*(L"Headers\*(R"\fR being searched first. A subframework is a framework |
| 11176 | directory that is in a framework's \fB\*(L"Frameworks\*(R"\fR directory. |
| 11177 | Includes of subframework headers can only appear in a header of a |
| 11178 | framework that contains the subframework, or in a sibling subframework |
| 11179 | header. Two subframeworks are siblings if they occur in the same |
| 11180 | framework. A subframework should not have the same name as a |
| 11181 | framework, a warning will be issued if this is violated. Currently a |
| 11182 | subframework cannot have subframeworks, in the future, the mechanism |
| 11183 | may be extended to support this. The standard frameworks can be found |
| 11184 | in \fB\*(L"/System/Library/Frameworks\*(R"\fR and |
| 11185 | \&\fB\*(L"/Library/Frameworks\*(R"\fR. An example include looks like |
| 11186 | \&\f(CW\*(C`#include <Framework/header.h>\*(C'\fR, where \fBFramework\fR denotes |
| 11187 | the name of the framework and header.h is found in the |
| 11188 | \&\fB\*(L"PrivateHeaders\*(R"\fR or \fB\*(L"Headers\*(R"\fR directory. |
| 11189 | .IP "\fB\-iframework\fR\fIdir\fR" 4 |
| 11190 | .IX Item "-iframeworkdir" |
| 11191 | Like \fB\-F\fR except the directory is a treated as a system |
| 11192 | directory. The main difference between this \fB\-iframework\fR and |
| 11193 | \&\fB\-F\fR is that with \fB\-iframework\fR the compiler does not |
| 11194 | warn about constructs contained within header files found via |
| 11195 | \&\fIdir\fR. This option is valid only for the C family of languages. |
| 11196 | .IP "\fB\-gused\fR" 4 |
| 11197 | .IX Item "-gused" |
| 11198 | Emit debugging information for symbols that are used. For \s-1STABS\s0 |
| 11199 | debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR. |
| 11200 | This is by default \s-1ON\s0. |
| 11201 | .IP "\fB\-gfull\fR" 4 |
| 11202 | .IX Item "-gfull" |
| 11203 | Emit debugging information for all symbols and types. |
| 11204 | .IP "\fB\-mmacosx\-version\-min=\fR\fIversion\fR" 4 |
| 11205 | .IX Item "-mmacosx-version-min=version" |
| 11206 | The earliest version of MacOS X that this executable will run on |
| 11207 | is \fIversion\fR. Typical values of \fIversion\fR include \f(CW10.1\fR, |
| 11208 | \&\f(CW10.2\fR, and \f(CW10.3.9\fR. |
| 11209 | .Sp |
| 11210 | If the compiler was built to use the system's headers by default, |
| 11211 | then the default for this option is the system version on which the |
| 11212 | compiler is running, otherwise the default is to make choices that |
| 11213 | are compatible with as many systems and code bases as possible. |
| 11214 | .IP "\fB\-mkernel\fR" 4 |
| 11215 | .IX Item "-mkernel" |
| 11216 | Enable kernel development mode. The \fB\-mkernel\fR option sets |
| 11217 | \&\fB\-static\fR, \fB\-fno\-common\fR, \fB\-fno\-cxa\-atexit\fR, |
| 11218 | \&\fB\-fno\-exceptions\fR, \fB\-fno\-non\-call\-exceptions\fR, |
| 11219 | \&\fB\-fapple\-kext\fR, \fB\-fno\-weak\fR and \fB\-fno\-rtti\fR where |
| 11220 | applicable. This mode also sets \fB\-mno\-altivec\fR, |
| 11221 | \&\fB\-msoft\-float\fR, \fB\-fno\-builtin\fR and |
| 11222 | \&\fB\-mlong\-branch\fR for PowerPC targets. |
| 11223 | .IP "\fB\-mone\-byte\-bool\fR" 4 |
| 11224 | .IX Item "-mone-byte-bool" |
| 11225 | Override the defaults for \fBbool\fR so that \fBsizeof(bool)==1\fR. |
| 11226 | By default \fBsizeof(bool)\fR is \fB4\fR when compiling for |
| 11227 | Darwin/PowerPC and \fB1\fR when compiling for Darwin/x86, so this |
| 11228 | option has no effect on x86. |
| 11229 | .Sp |
| 11230 | \&\fBWarning:\fR The \fB\-mone\-byte\-bool\fR switch causes \s-1GCC\s0 |
| 11231 | to generate code that is not binary compatible with code generated |
| 11232 | without that switch. Using this switch may require recompiling all |
| 11233 | other modules in a program, including system libraries. Use this |
| 11234 | switch to conform to a non-default data model. |
| 11235 | .IP "\fB\-mfix\-and\-continue\fR" 4 |
| 11236 | .IX Item "-mfix-and-continue" |
| 11237 | .PD 0 |
| 11238 | .IP "\fB\-ffix\-and\-continue\fR" 4 |
| 11239 | .IX Item "-ffix-and-continue" |
| 11240 | .IP "\fB\-findirect\-data\fR" 4 |
| 11241 | .IX Item "-findirect-data" |
| 11242 | .PD |
| 11243 | Generate code suitable for fast turn around development. Needed to |
| 11244 | enable gdb to dynamically load \f(CW\*(C`.o\*(C'\fR files into already running |
| 11245 | programs. \fB\-findirect\-data\fR and \fB\-ffix\-and\-continue\fR |
| 11246 | are provided for backwards compatibility. |
| 11247 | .IP "\fB\-all_load\fR" 4 |
| 11248 | .IX Item "-all_load" |
| 11249 | Loads all members of static archive libraries. |
| 11250 | See man \fIld\fR\|(1) for more information. |
| 11251 | .IP "\fB\-arch_errors_fatal\fR" 4 |
| 11252 | .IX Item "-arch_errors_fatal" |
| 11253 | Cause the errors having to do with files that have the wrong architecture |
| 11254 | to be fatal. |
| 11255 | .IP "\fB\-bind_at_load\fR" 4 |
| 11256 | .IX Item "-bind_at_load" |
| 11257 | Causes the output file to be marked such that the dynamic linker will |
| 11258 | bind all undefined references when the file is loaded or launched. |
| 11259 | .IP "\fB\-bundle\fR" 4 |
| 11260 | .IX Item "-bundle" |
| 11261 | Produce a Mach-o bundle format file. |
| 11262 | See man \fIld\fR\|(1) for more information. |
| 11263 | .IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4 |
| 11264 | .IX Item "-bundle_loader executable" |
| 11265 | This option specifies the \fIexecutable\fR that will be loading the build |
| 11266 | output file being linked. See man \fIld\fR\|(1) for more information. |
| 11267 | .IP "\fB\-dynamiclib\fR" 4 |
| 11268 | .IX Item "-dynamiclib" |
| 11269 | When passed this option, \s-1GCC\s0 will produce a dynamic library instead of |
| 11270 | an executable when linking, using the Darwin \fIlibtool\fR command. |
| 11271 | .IP "\fB\-force_cpusubtype_ALL\fR" 4 |
| 11272 | .IX Item "-force_cpusubtype_ALL" |
| 11273 | This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of |
| 11274 | one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. |
| 11275 | .IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 |
| 11276 | .IX Item "-allowable_client client_name" |
| 11277 | .PD 0 |
| 11278 | .IP "\fB\-client_name\fR" 4 |
| 11279 | .IX Item "-client_name" |
| 11280 | .IP "\fB\-compatibility_version\fR" 4 |
| 11281 | .IX Item "-compatibility_version" |
| 11282 | .IP "\fB\-current_version\fR" 4 |
| 11283 | .IX Item "-current_version" |
| 11284 | .IP "\fB\-dead_strip\fR" 4 |
| 11285 | .IX Item "-dead_strip" |
| 11286 | .IP "\fB\-dependency\-file\fR" 4 |
| 11287 | .IX Item "-dependency-file" |
| 11288 | .IP "\fB\-dylib_file\fR" 4 |
| 11289 | .IX Item "-dylib_file" |
| 11290 | .IP "\fB\-dylinker_install_name\fR" 4 |
| 11291 | .IX Item "-dylinker_install_name" |
| 11292 | .IP "\fB\-dynamic\fR" 4 |
| 11293 | .IX Item "-dynamic" |
| 11294 | .IP "\fB\-exported_symbols_list\fR" 4 |
| 11295 | .IX Item "-exported_symbols_list" |
| 11296 | .IP "\fB\-filelist\fR" 4 |
| 11297 | .IX Item "-filelist" |
| 11298 | .IP "\fB\-flat_namespace\fR" 4 |
| 11299 | .IX Item "-flat_namespace" |
| 11300 | .IP "\fB\-force_flat_namespace\fR" 4 |
| 11301 | .IX Item "-force_flat_namespace" |
| 11302 | .IP "\fB\-headerpad_max_install_names\fR" 4 |
| 11303 | .IX Item "-headerpad_max_install_names" |
| 11304 | .IP "\fB\-image_base\fR" 4 |
| 11305 | .IX Item "-image_base" |
| 11306 | .IP "\fB\-init\fR" 4 |
| 11307 | .IX Item "-init" |
| 11308 | .IP "\fB\-install_name\fR" 4 |
| 11309 | .IX Item "-install_name" |
| 11310 | .IP "\fB\-keep_private_externs\fR" 4 |
| 11311 | .IX Item "-keep_private_externs" |
| 11312 | .IP "\fB\-multi_module\fR" 4 |
| 11313 | .IX Item "-multi_module" |
| 11314 | .IP "\fB\-multiply_defined\fR" 4 |
| 11315 | .IX Item "-multiply_defined" |
| 11316 | .IP "\fB\-multiply_defined_unused\fR" 4 |
| 11317 | .IX Item "-multiply_defined_unused" |
| 11318 | .IP "\fB\-noall_load\fR" 4 |
| 11319 | .IX Item "-noall_load" |
| 11320 | .IP "\fB\-no_dead_strip_inits_and_terms\fR" 4 |
| 11321 | .IX Item "-no_dead_strip_inits_and_terms" |
| 11322 | .IP "\fB\-nofixprebinding\fR" 4 |
| 11323 | .IX Item "-nofixprebinding" |
| 11324 | .IP "\fB\-nomultidefs\fR" 4 |
| 11325 | .IX Item "-nomultidefs" |
| 11326 | .IP "\fB\-noprebind\fR" 4 |
| 11327 | .IX Item "-noprebind" |
| 11328 | .IP "\fB\-noseglinkedit\fR" 4 |
| 11329 | .IX Item "-noseglinkedit" |
| 11330 | .IP "\fB\-pagezero_size\fR" 4 |
| 11331 | .IX Item "-pagezero_size" |
| 11332 | .IP "\fB\-prebind\fR" 4 |
| 11333 | .IX Item "-prebind" |
| 11334 | .IP "\fB\-prebind_all_twolevel_modules\fR" 4 |
| 11335 | .IX Item "-prebind_all_twolevel_modules" |
| 11336 | .IP "\fB\-private_bundle\fR" 4 |
| 11337 | .IX Item "-private_bundle" |
| 11338 | .IP "\fB\-read_only_relocs\fR" 4 |
| 11339 | .IX Item "-read_only_relocs" |
| 11340 | .IP "\fB\-sectalign\fR" 4 |
| 11341 | .IX Item "-sectalign" |
| 11342 | .IP "\fB\-sectobjectsymbols\fR" 4 |
| 11343 | .IX Item "-sectobjectsymbols" |
| 11344 | .IP "\fB\-whyload\fR" 4 |
| 11345 | .IX Item "-whyload" |
| 11346 | .IP "\fB\-seg1addr\fR" 4 |
| 11347 | .IX Item "-seg1addr" |
| 11348 | .IP "\fB\-sectcreate\fR" 4 |
| 11349 | .IX Item "-sectcreate" |
| 11350 | .IP "\fB\-sectobjectsymbols\fR" 4 |
| 11351 | .IX Item "-sectobjectsymbols" |
| 11352 | .IP "\fB\-sectorder\fR" 4 |
| 11353 | .IX Item "-sectorder" |
| 11354 | .IP "\fB\-segaddr\fR" 4 |
| 11355 | .IX Item "-segaddr" |
| 11356 | .IP "\fB\-segs_read_only_addr\fR" 4 |
| 11357 | .IX Item "-segs_read_only_addr" |
| 11358 | .IP "\fB\-segs_read_write_addr\fR" 4 |
| 11359 | .IX Item "-segs_read_write_addr" |
| 11360 | .IP "\fB\-seg_addr_table\fR" 4 |
| 11361 | .IX Item "-seg_addr_table" |
| 11362 | .IP "\fB\-seg_addr_table_filename\fR" 4 |
| 11363 | .IX Item "-seg_addr_table_filename" |
| 11364 | .IP "\fB\-seglinkedit\fR" 4 |
| 11365 | .IX Item "-seglinkedit" |
| 11366 | .IP "\fB\-segprot\fR" 4 |
| 11367 | .IX Item "-segprot" |
| 11368 | .IP "\fB\-segs_read_only_addr\fR" 4 |
| 11369 | .IX Item "-segs_read_only_addr" |
| 11370 | .IP "\fB\-segs_read_write_addr\fR" 4 |
| 11371 | .IX Item "-segs_read_write_addr" |
| 11372 | .IP "\fB\-single_module\fR" 4 |
| 11373 | .IX Item "-single_module" |
| 11374 | .IP "\fB\-static\fR" 4 |
| 11375 | .IX Item "-static" |
| 11376 | .IP "\fB\-sub_library\fR" 4 |
| 11377 | .IX Item "-sub_library" |
| 11378 | .IP "\fB\-sub_umbrella\fR" 4 |
| 11379 | .IX Item "-sub_umbrella" |
| 11380 | .IP "\fB\-twolevel_namespace\fR" 4 |
| 11381 | .IX Item "-twolevel_namespace" |
| 11382 | .IP "\fB\-umbrella\fR" 4 |
| 11383 | .IX Item "-umbrella" |
| 11384 | .IP "\fB\-undefined\fR" 4 |
| 11385 | .IX Item "-undefined" |
| 11386 | .IP "\fB\-unexported_symbols_list\fR" 4 |
| 11387 | .IX Item "-unexported_symbols_list" |
| 11388 | .IP "\fB\-weak_reference_mismatches\fR" 4 |
| 11389 | .IX Item "-weak_reference_mismatches" |
| 11390 | .IP "\fB\-whatsloaded\fR" 4 |
| 11391 | .IX Item "-whatsloaded" |
| 11392 | .PD |
| 11393 | These options are passed to the Darwin linker. The Darwin linker man page |
| 11394 | describes them in detail. |
| 11395 | .PP |
| 11396 | \fI\s-1DEC\s0 Alpha Options\fR |
| 11397 | .IX Subsection "DEC Alpha Options" |
| 11398 | .PP |
| 11399 | These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations: |
| 11400 | .IP "\fB\-mno\-soft\-float\fR" 4 |
| 11401 | .IX Item "-mno-soft-float" |
| 11402 | .PD 0 |
| 11403 | .IP "\fB\-msoft\-float\fR" 4 |
| 11404 | .IX Item "-msoft-float" |
| 11405 | .PD |
| 11406 | Use (do not use) the hardware floating-point instructions for |
| 11407 | floating-point operations. When \fB\-msoft\-float\fR is specified, |
| 11408 | functions in \fIlibgcc.a\fR will be used to perform floating-point |
| 11409 | operations. Unless they are replaced by routines that emulate the |
| 11410 | floating-point operations, or compiled in such a way as to call such |
| 11411 | emulations routines, these routines will issue floating-point |
| 11412 | operations. If you are compiling for an Alpha without floating-point |
| 11413 | operations, you must ensure that the library is built so as not to call |
| 11414 | them. |
| 11415 | .Sp |
| 11416 | Note that Alpha implementations without floating-point operations are |
| 11417 | required to have floating-point registers. |
| 11418 | .IP "\fB\-mfp\-reg\fR" 4 |
| 11419 | .IX Item "-mfp-reg" |
| 11420 | .PD 0 |
| 11421 | .IP "\fB\-mno\-fp\-regs\fR" 4 |
| 11422 | .IX Item "-mno-fp-regs" |
| 11423 | .PD |
| 11424 | Generate code that uses (does not use) the floating-point register set. |
| 11425 | \&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR. If the floating-point |
| 11426 | register set is not used, floating-point operands are passed in integer |
| 11427 | registers as if they were integers and floating-point results are passed |
| 11428 | in \f(CW$0\fR instead of \f(CW$f0\fR. This is a non-standard calling sequence, |
| 11429 | so any function with a floating-point argument or return value called by code |
| 11430 | compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that |
| 11431 | option. |
| 11432 | .Sp |
| 11433 | A typical use of this option is building a kernel that does not use, |
| 11434 | and hence need not save and restore, any floating-point registers. |
| 11435 | .IP "\fB\-mieee\fR" 4 |
| 11436 | .IX Item "-mieee" |
| 11437 | The Alpha architecture implements floating-point hardware optimized for |
| 11438 | maximum performance. It is mostly compliant with the \s-1IEEE\s0 floating-point |
| 11439 | standard. However, for full compliance, software assistance is |
| 11440 | required. This option generates code fully IEEE-compliant code |
| 11441 | \&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below). |
| 11442 | If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is |
| 11443 | defined during compilation. The resulting code is less efficient but is |
| 11444 | able to correctly support denormalized numbers and exceptional \s-1IEEE\s0 |
| 11445 | values such as not-a-number and plus/minus infinity. Other Alpha |
| 11446 | compilers call this option \fB\-ieee_with_no_inexact\fR. |
| 11447 | .IP "\fB\-mieee\-with\-inexact\fR" 4 |
| 11448 | .IX Item "-mieee-with-inexact" |
| 11449 | This is like \fB\-mieee\fR except the generated code also maintains |
| 11450 | the \s-1IEEE\s0 \fIinexact-flag\fR. Turning on this option causes the |
| 11451 | generated code to implement fully-compliant \s-1IEEE\s0 math. In addition to |
| 11452 | \&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor |
| 11453 | macro. On some Alpha implementations the resulting code may execute |
| 11454 | significantly slower than the code generated by default. Since there is |
| 11455 | very little code that depends on the \fIinexact-flag\fR, you should |
| 11456 | normally not specify this option. Other Alpha compilers call this |
| 11457 | option \fB\-ieee_with_inexact\fR. |
| 11458 | .IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4 |
| 11459 | .IX Item "-mfp-trap-mode=trap-mode" |
| 11460 | This option controls what floating-point related traps are enabled. |
| 11461 | Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR. |
| 11462 | The trap mode can be set to one of four values: |
| 11463 | .RS 4 |
| 11464 | .IP "\fBn\fR" 4 |
| 11465 | .IX Item "n" |
| 11466 | This is the default (normal) setting. The only traps that are enabled |
| 11467 | are the ones that cannot be disabled in software (e.g., division by zero |
| 11468 | trap). |
| 11469 | .IP "\fBu\fR" 4 |
| 11470 | .IX Item "u" |
| 11471 | In addition to the traps enabled by \fBn\fR, underflow traps are enabled |
| 11472 | as well. |
| 11473 | .IP "\fBsu\fR" 4 |
| 11474 | .IX Item "su" |
| 11475 | Like \fBu\fR, but the instructions are marked to be safe for software |
| 11476 | completion (see Alpha architecture manual for details). |
| 11477 | .IP "\fBsui\fR" 4 |
| 11478 | .IX Item "sui" |
| 11479 | Like \fBsu\fR, but inexact traps are enabled as well. |
| 11480 | .RE |
| 11481 | .RS 4 |
| 11482 | .RE |
| 11483 | .IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4 |
| 11484 | .IX Item "-mfp-rounding-mode=rounding-mode" |
| 11485 | Selects the \s-1IEEE\s0 rounding mode. Other Alpha compilers call this option |
| 11486 | \&\fB\-fprm\fR \fIrounding-mode\fR. The \fIrounding-mode\fR can be one |
| 11487 | of: |
| 11488 | .RS 4 |
| 11489 | .IP "\fBn\fR" 4 |
| 11490 | .IX Item "n" |
| 11491 | Normal \s-1IEEE\s0 rounding mode. Floating-point numbers are rounded towards |
| 11492 | the nearest machine number or towards the even machine number in case |
| 11493 | of a tie. |
| 11494 | .IP "\fBm\fR" 4 |
| 11495 | .IX Item "m" |
| 11496 | Round towards minus infinity. |
| 11497 | .IP "\fBc\fR" 4 |
| 11498 | .IX Item "c" |
| 11499 | Chopped rounding mode. Floating-point numbers are rounded towards zero. |
| 11500 | .IP "\fBd\fR" 4 |
| 11501 | .IX Item "d" |
| 11502 | Dynamic rounding mode. A field in the floating-point control register |
| 11503 | (\fIfpcr\fR, see Alpha architecture reference manual) controls the |
| 11504 | rounding mode in effect. The C library initializes this register for |
| 11505 | rounding towards plus infinity. Thus, unless your program modifies the |
| 11506 | \&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity. |
| 11507 | .RE |
| 11508 | .RS 4 |
| 11509 | .RE |
| 11510 | .IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4 |
| 11511 | .IX Item "-mtrap-precision=trap-precision" |
| 11512 | In the Alpha architecture, floating-point traps are imprecise. This |
| 11513 | means without software assistance it is impossible to recover from a |
| 11514 | floating trap and program execution normally needs to be terminated. |
| 11515 | \&\s-1GCC\s0 can generate code that can assist operating system trap handlers |
| 11516 | in determining the exact location that caused a floating-point trap. |
| 11517 | Depending on the requirements of an application, different levels of |
| 11518 | precisions can be selected: |
| 11519 | .RS 4 |
| 11520 | .IP "\fBp\fR" 4 |
| 11521 | .IX Item "p" |
| 11522 | Program precision. This option is the default and means a trap handler |
| 11523 | can only identify which program caused a floating-point exception. |
| 11524 | .IP "\fBf\fR" 4 |
| 11525 | .IX Item "f" |
| 11526 | Function precision. The trap handler can determine the function that |
| 11527 | caused a floating-point exception. |
| 11528 | .IP "\fBi\fR" 4 |
| 11529 | .IX Item "i" |
| 11530 | Instruction precision. The trap handler can determine the exact |
| 11531 | instruction that caused a floating-point exception. |
| 11532 | .RE |
| 11533 | .RS 4 |
| 11534 | .Sp |
| 11535 | Other Alpha compilers provide the equivalent options called |
| 11536 | \&\fB\-scope_safe\fR and \fB\-resumption_safe\fR. |
| 11537 | .RE |
| 11538 | .IP "\fB\-mieee\-conformant\fR" 4 |
| 11539 | .IX Item "-mieee-conformant" |
| 11540 | This option marks the generated code as \s-1IEEE\s0 conformant. You must not |
| 11541 | use this option unless you also specify \fB\-mtrap\-precision=i\fR and either |
| 11542 | \&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR. Its only effect |
| 11543 | is to emit the line \fB.eflag 48\fR in the function prologue of the |
| 11544 | generated assembly file. Under \s-1DEC\s0 Unix, this has the effect that |
| 11545 | IEEE-conformant math library routines will be linked in. |
| 11546 | .IP "\fB\-mbuild\-constants\fR" 4 |
| 11547 | .IX Item "-mbuild-constants" |
| 11548 | Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to |
| 11549 | see if it can construct it from smaller constants in two or three |
| 11550 | instructions. If it cannot, it will output the constant as a literal and |
| 11551 | generate code to load it from the data segment at run time. |
| 11552 | .Sp |
| 11553 | Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants |
| 11554 | using code, even if it takes more instructions (the maximum is six). |
| 11555 | .Sp |
| 11556 | You would typically use this option to build a shared library dynamic |
| 11557 | loader. Itself a shared library, it must relocate itself in memory |
| 11558 | before it can find the variables and constants in its own data segment. |
| 11559 | .IP "\fB\-malpha\-as\fR" 4 |
| 11560 | .IX Item "-malpha-as" |
| 11561 | .PD 0 |
| 11562 | .IP "\fB\-mgas\fR" 4 |
| 11563 | .IX Item "-mgas" |
| 11564 | .PD |
| 11565 | Select whether to generate code to be assembled by the vendor-supplied |
| 11566 | assembler (\fB\-malpha\-as\fR) or by the \s-1GNU\s0 assembler \fB\-mgas\fR. |
| 11567 | .IP "\fB\-mbwx\fR" 4 |
| 11568 | .IX Item "-mbwx" |
| 11569 | .PD 0 |
| 11570 | .IP "\fB\-mno\-bwx\fR" 4 |
| 11571 | .IX Item "-mno-bwx" |
| 11572 | .IP "\fB\-mcix\fR" 4 |
| 11573 | .IX Item "-mcix" |
| 11574 | .IP "\fB\-mno\-cix\fR" 4 |
| 11575 | .IX Item "-mno-cix" |
| 11576 | .IP "\fB\-mfix\fR" 4 |
| 11577 | .IX Item "-mfix" |
| 11578 | .IP "\fB\-mno\-fix\fR" 4 |
| 11579 | .IX Item "-mno-fix" |
| 11580 | .IP "\fB\-mmax\fR" 4 |
| 11581 | .IX Item "-mmax" |
| 11582 | .IP "\fB\-mno\-max\fR" 4 |
| 11583 | .IX Item "-mno-max" |
| 11584 | .PD |
| 11585 | Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0, |
| 11586 | \&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets. The default is to use the instruction |
| 11587 | sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that |
| 11588 | of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none was specified. |
| 11589 | .IP "\fB\-mfloat\-vax\fR" 4 |
| 11590 | .IX Item "-mfloat-vax" |
| 11591 | .PD 0 |
| 11592 | .IP "\fB\-mfloat\-ieee\fR" 4 |
| 11593 | .IX Item "-mfloat-ieee" |
| 11594 | .PD |
| 11595 | Generate code that uses (does not use) \s-1VAX\s0 F and G floating-point |
| 11596 | arithmetic instead of \s-1IEEE\s0 single and double precision. |
| 11597 | .IP "\fB\-mexplicit\-relocs\fR" 4 |
| 11598 | .IX Item "-mexplicit-relocs" |
| 11599 | .PD 0 |
| 11600 | .IP "\fB\-mno\-explicit\-relocs\fR" 4 |
| 11601 | .IX Item "-mno-explicit-relocs" |
| 11602 | .PD |
| 11603 | Older Alpha assemblers provided no way to generate symbol relocations |
| 11604 | except via assembler macros. Use of these macros does not allow |
| 11605 | optimal instruction scheduling. \s-1GNU\s0 binutils as of version 2.12 |
| 11606 | supports a new syntax that allows the compiler to explicitly mark |
| 11607 | which relocations should apply to which instructions. This option |
| 11608 | is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of |
| 11609 | the assembler when it is built and sets the default accordingly. |
| 11610 | .IP "\fB\-msmall\-data\fR" 4 |
| 11611 | .IX Item "-msmall-data" |
| 11612 | .PD 0 |
| 11613 | .IP "\fB\-mlarge\-data\fR" 4 |
| 11614 | .IX Item "-mlarge-data" |
| 11615 | .PD |
| 11616 | When \fB\-mexplicit\-relocs\fR is in effect, static data is |
| 11617 | accessed via \fIgp-relative\fR relocations. When \fB\-msmall\-data\fR |
| 11618 | is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR |
| 11619 | (the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via |
| 11620 | 16\-bit relocations off of the \f(CW$gp\fR register. This limits the |
| 11621 | size of the small data area to 64KB, but allows the variables to be |
| 11622 | directly accessed via a single instruction. |
| 11623 | .Sp |
| 11624 | The default is \fB\-mlarge\-data\fR. With this option the data area |
| 11625 | is limited to just below 2GB. Programs that require more than 2GB of |
| 11626 | data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the |
| 11627 | heap instead of in the program's data segment. |
| 11628 | .Sp |
| 11629 | When generating code for shared libraries, \fB\-fpic\fR implies |
| 11630 | \&\fB\-msmall\-data\fR and \fB\-fPIC\fR implies \fB\-mlarge\-data\fR. |
| 11631 | .IP "\fB\-msmall\-text\fR" 4 |
| 11632 | .IX Item "-msmall-text" |
| 11633 | .PD 0 |
| 11634 | .IP "\fB\-mlarge\-text\fR" 4 |
| 11635 | .IX Item "-mlarge-text" |
| 11636 | .PD |
| 11637 | When \fB\-msmall\-text\fR is used, the compiler assumes that the |
| 11638 | code of the entire program (or shared library) fits in 4MB, and is |
| 11639 | thus reachable with a branch instruction. When \fB\-msmall\-data\fR |
| 11640 | is used, the compiler can assume that all local symbols share the |
| 11641 | same \f(CW$gp\fR value, and thus reduce the number of instructions |
| 11642 | required for a function call from 4 to 1. |
| 11643 | .Sp |
| 11644 | The default is \fB\-mlarge\-text\fR. |
| 11645 | .IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 |
| 11646 | .IX Item "-mcpu=cpu_type" |
| 11647 | Set the instruction set and instruction scheduling parameters for |
| 11648 | machine type \fIcpu_type\fR. You can specify either the \fB\s-1EV\s0\fR |
| 11649 | style name or the corresponding chip number. \s-1GCC\s0 supports scheduling |
| 11650 | parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and will |
| 11651 | choose the default values for the instruction set from the processor |
| 11652 | you specify. If you do not specify a processor type, \s-1GCC\s0 will default |
| 11653 | to the processor on which the compiler was built. |
| 11654 | .Sp |
| 11655 | Supported values for \fIcpu_type\fR are |
| 11656 | .RS 4 |
| 11657 | .IP "\fBev4\fR" 4 |
| 11658 | .IX Item "ev4" |
| 11659 | .PD 0 |
| 11660 | .IP "\fBev45\fR" 4 |
| 11661 | .IX Item "ev45" |
| 11662 | .IP "\fB21064\fR" 4 |
| 11663 | .IX Item "21064" |
| 11664 | .PD |
| 11665 | Schedules as an \s-1EV4\s0 and has no instruction set extensions. |
| 11666 | .IP "\fBev5\fR" 4 |
| 11667 | .IX Item "ev5" |
| 11668 | .PD 0 |
| 11669 | .IP "\fB21164\fR" 4 |
| 11670 | .IX Item "21164" |
| 11671 | .PD |
| 11672 | Schedules as an \s-1EV5\s0 and has no instruction set extensions. |
| 11673 | .IP "\fBev56\fR" 4 |
| 11674 | .IX Item "ev56" |
| 11675 | .PD 0 |
| 11676 | .IP "\fB21164a\fR" 4 |
| 11677 | .IX Item "21164a" |
| 11678 | .PD |
| 11679 | Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension. |
| 11680 | .IP "\fBpca56\fR" 4 |
| 11681 | .IX Item "pca56" |
| 11682 | .PD 0 |
| 11683 | .IP "\fB21164pc\fR" 4 |
| 11684 | .IX Item "21164pc" |
| 11685 | .IP "\fB21164PC\fR" 4 |
| 11686 | .IX Item "21164PC" |
| 11687 | .PD |
| 11688 | Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions. |
| 11689 | .IP "\fBev6\fR" 4 |
| 11690 | .IX Item "ev6" |
| 11691 | .PD 0 |
| 11692 | .IP "\fB21264\fR" 4 |
| 11693 | .IX Item "21264" |
| 11694 | .PD |
| 11695 | Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. |
| 11696 | .IP "\fBev67\fR" 4 |
| 11697 | .IX Item "ev67" |
| 11698 | .PD 0 |
| 11699 | .IP "\fB21264a\fR" 4 |
| 11700 | .IX Item "21264a" |
| 11701 | .PD |
| 11702 | Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions. |
| 11703 | .RE |
| 11704 | .RS 4 |
| 11705 | .Sp |
| 11706 | Native toolchains also support the value \fBnative\fR, |
| 11707 | which selects the best architecture option for the host processor. |
| 11708 | \&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize |
| 11709 | the processor. |
| 11710 | .RE |
| 11711 | .IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 |
| 11712 | .IX Item "-mtune=cpu_type" |
| 11713 | Set only the instruction scheduling parameters for machine type |
| 11714 | \&\fIcpu_type\fR. The instruction set is not changed. |
| 11715 | .Sp |
| 11716 | Native toolchains also support the value \fBnative\fR, |
| 11717 | which selects the best architecture option for the host processor. |
| 11718 | \&\fB\-mtune=native\fR has no effect if \s-1GCC\s0 does not recognize |
| 11719 | the processor. |
| 11720 | .IP "\fB\-mmemory\-latency=\fR\fItime\fR" 4 |
| 11721 | .IX Item "-mmemory-latency=time" |
| 11722 | Sets the latency the scheduler should assume for typical memory |
| 11723 | references as seen by the application. This number is highly |
| 11724 | dependent on the memory access patterns used by the application |
| 11725 | and the size of the external cache on the machine. |
| 11726 | .Sp |
| 11727 | Valid options for \fItime\fR are |
| 11728 | .RS 4 |
| 11729 | .IP "\fInumber\fR" 4 |
| 11730 | .IX Item "number" |
| 11731 | A decimal number representing clock cycles. |
| 11732 | .IP "\fBL1\fR" 4 |
| 11733 | .IX Item "L1" |
| 11734 | .PD 0 |
| 11735 | .IP "\fBL2\fR" 4 |
| 11736 | .IX Item "L2" |
| 11737 | .IP "\fBL3\fR" 4 |
| 11738 | .IX Item "L3" |
| 11739 | .IP "\fBmain\fR" 4 |
| 11740 | .IX Item "main" |
| 11741 | .PD |
| 11742 | The compiler contains estimates of the number of clock cycles for |
| 11743 | \&\*(L"typical\*(R" \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches |
| 11744 | (also called Dcache, Scache, and Bcache), as well as to main memory. |
| 11745 | Note that L3 is only valid for \s-1EV5\s0. |
| 11746 | .RE |
| 11747 | .RS 4 |
| 11748 | .RE |
| 11749 | .PP |
| 11750 | \fI\s-1DEC\s0 Alpha/VMS Options\fR |
| 11751 | .IX Subsection "DEC Alpha/VMS Options" |
| 11752 | .PP |
| 11753 | These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha/VMS implementations: |
| 11754 | .IP "\fB\-mvms\-return\-codes\fR" 4 |
| 11755 | .IX Item "-mvms-return-codes" |
| 11756 | Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0 |
| 11757 | style condition (e.g. error) codes. |
| 11758 | .IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 |
| 11759 | .IX Item "-mdebug-main=prefix" |
| 11760 | Flag the first routine whose name starts with \fIprefix\fR as the main |
| 11761 | routine for the debugger. |
| 11762 | .IP "\fB\-mmalloc64\fR" 4 |
| 11763 | .IX Item "-mmalloc64" |
| 11764 | Default to 64\-bit memory allocation routines. |
| 11765 | .PP |
| 11766 | \fI\s-1FR30\s0 Options\fR |
| 11767 | .IX Subsection "FR30 Options" |
| 11768 | .PP |
| 11769 | These options are defined specifically for the \s-1FR30\s0 port. |
| 11770 | .IP "\fB\-msmall\-model\fR" 4 |
| 11771 | .IX Item "-msmall-model" |
| 11772 | Use the small address space model. This can produce smaller code, but |
| 11773 | it does assume that all symbolic values and addresses will fit into a |
| 11774 | 20\-bit range. |
| 11775 | .IP "\fB\-mno\-lsim\fR" 4 |
| 11776 | .IX Item "-mno-lsim" |
| 11777 | Assume that runtime support has been provided and so there is no need |
| 11778 | to include the simulator library (\fIlibsim.a\fR) on the linker |
| 11779 | command line. |
| 11780 | .PP |
| 11781 | \fI\s-1FRV\s0 Options\fR |
| 11782 | .IX Subsection "FRV Options" |
| 11783 | .IP "\fB\-mgpr\-32\fR" 4 |
| 11784 | .IX Item "-mgpr-32" |
| 11785 | Only use the first 32 general-purpose registers. |
| 11786 | .IP "\fB\-mgpr\-64\fR" 4 |
| 11787 | .IX Item "-mgpr-64" |
| 11788 | Use all 64 general-purpose registers. |
| 11789 | .IP "\fB\-mfpr\-32\fR" 4 |
| 11790 | .IX Item "-mfpr-32" |
| 11791 | Use only the first 32 floating-point registers. |
| 11792 | .IP "\fB\-mfpr\-64\fR" 4 |
| 11793 | .IX Item "-mfpr-64" |
| 11794 | Use all 64 floating-point registers. |
| 11795 | .IP "\fB\-mhard\-float\fR" 4 |
| 11796 | .IX Item "-mhard-float" |
| 11797 | Use hardware instructions for floating-point operations. |
| 11798 | .IP "\fB\-msoft\-float\fR" 4 |
| 11799 | .IX Item "-msoft-float" |
| 11800 | Use library routines for floating-point operations. |
| 11801 | .IP "\fB\-malloc\-cc\fR" 4 |
| 11802 | .IX Item "-malloc-cc" |
| 11803 | Dynamically allocate condition code registers. |
| 11804 | .IP "\fB\-mfixed\-cc\fR" 4 |
| 11805 | .IX Item "-mfixed-cc" |
| 11806 | Do not try to dynamically allocate condition code registers, only |
| 11807 | use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR. |
| 11808 | .IP "\fB\-mdword\fR" 4 |
| 11809 | .IX Item "-mdword" |
| 11810 | Change \s-1ABI\s0 to use double word insns. |
| 11811 | .IP "\fB\-mno\-dword\fR" 4 |
| 11812 | .IX Item "-mno-dword" |
| 11813 | Do not use double word instructions. |
| 11814 | .IP "\fB\-mdouble\fR" 4 |
| 11815 | .IX Item "-mdouble" |
| 11816 | Use floating-point double instructions. |
| 11817 | .IP "\fB\-mno\-double\fR" 4 |
| 11818 | .IX Item "-mno-double" |
| 11819 | Do not use floating-point double instructions. |
| 11820 | .IP "\fB\-mmedia\fR" 4 |
| 11821 | .IX Item "-mmedia" |
| 11822 | Use media instructions. |
| 11823 | .IP "\fB\-mno\-media\fR" 4 |
| 11824 | .IX Item "-mno-media" |
| 11825 | Do not use media instructions. |
| 11826 | .IP "\fB\-mmuladd\fR" 4 |
| 11827 | .IX Item "-mmuladd" |
| 11828 | Use multiply and add/subtract instructions. |
| 11829 | .IP "\fB\-mno\-muladd\fR" 4 |
| 11830 | .IX Item "-mno-muladd" |
| 11831 | Do not use multiply and add/subtract instructions. |
| 11832 | .IP "\fB\-mfdpic\fR" 4 |
| 11833 | .IX Item "-mfdpic" |
| 11834 | Select the \s-1FDPIC\s0 \s-1ABI\s0, which uses function descriptors to represent |
| 11835 | pointers to functions. Without any PIC/PIE\-related options, it |
| 11836 | implies \fB\-fPIE\fR. With \fB\-fpic\fR or \fB\-fpie\fR, it |
| 11837 | assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the |
| 11838 | \&\s-1GOT\s0 base address; with \fB\-fPIC\fR or \fB\-fPIE\fR, \s-1GOT\s0 offsets |
| 11839 | are computed with 32 bits. |
| 11840 | With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR. |
| 11841 | .IP "\fB\-minline\-plt\fR" 4 |
| 11842 | .IX Item "-minline-plt" |
| 11843 | Enable inlining of \s-1PLT\s0 entries in function calls to functions that are |
| 11844 | not known to bind locally. It has no effect without \fB\-mfdpic\fR. |
| 11845 | It's enabled by default if optimizing for speed and compiling for |
| 11846 | shared libraries (i.e., \fB\-fPIC\fR or \fB\-fpic\fR), or when an |
| 11847 | optimization option such as \fB\-O3\fR or above is present in the |
| 11848 | command line. |
| 11849 | .IP "\fB\-mTLS\fR" 4 |
| 11850 | .IX Item "-mTLS" |
| 11851 | Assume a large \s-1TLS\s0 segment when generating thread-local code. |
| 11852 | .IP "\fB\-mtls\fR" 4 |
| 11853 | .IX Item "-mtls" |
| 11854 | Do not assume a large \s-1TLS\s0 segment when generating thread-local code. |
| 11855 | .IP "\fB\-mgprel\-ro\fR" 4 |
| 11856 | .IX Item "-mgprel-ro" |
| 11857 | Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC\s0 \s-1ABI\s0 for data |
| 11858 | that is known to be in read-only sections. It's enabled by default, |
| 11859 | except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help |
| 11860 | make the global offset table smaller, it trades 1 instruction for 4. |
| 11861 | With \fB\-fPIC\fR or \fB\-fPIE\fR, it trades 3 instructions for 4, |
| 11862 | one of which may be shared by multiple symbols, and it avoids the need |
| 11863 | for a \s-1GOT\s0 entry for the referenced symbol, so it's more likely to be a |
| 11864 | win. If it is not, \fB\-mno\-gprel\-ro\fR can be used to disable it. |
| 11865 | .IP "\fB\-multilib\-library\-pic\fR" 4 |
| 11866 | .IX Item "-multilib-library-pic" |
| 11867 | Link with the (library, not \s-1FD\s0) pic libraries. It's implied by |
| 11868 | \&\fB\-mlibrary\-pic\fR, as well as by \fB\-fPIC\fR and |
| 11869 | \&\fB\-fpic\fR without \fB\-mfdpic\fR. You should never have to use |
| 11870 | it explicitly. |
| 11871 | .IP "\fB\-mlinked\-fp\fR" 4 |
| 11872 | .IX Item "-mlinked-fp" |
| 11873 | Follow the \s-1EABI\s0 requirement of always creating a frame pointer whenever |
| 11874 | a stack frame is allocated. This option is enabled by default and can |
| 11875 | be disabled with \fB\-mno\-linked\-fp\fR. |
| 11876 | .IP "\fB\-mlong\-calls\fR" 4 |
| 11877 | .IX Item "-mlong-calls" |
| 11878 | Use indirect addressing to call functions outside the current |
| 11879 | compilation unit. This allows the functions to be placed anywhere |
| 11880 | within the 32\-bit address space. |
| 11881 | .IP "\fB\-malign\-labels\fR" 4 |
| 11882 | .IX Item "-malign-labels" |
| 11883 | Try to align labels to an 8\-byte boundary by inserting nops into the |
| 11884 | previous packet. This option only has an effect when \s-1VLIW\s0 packing |
| 11885 | is enabled. It doesn't create new packets; it merely adds nops to |
| 11886 | existing ones. |
| 11887 | .IP "\fB\-mlibrary\-pic\fR" 4 |
| 11888 | .IX Item "-mlibrary-pic" |
| 11889 | Generate position-independent \s-1EABI\s0 code. |
| 11890 | .IP "\fB\-macc\-4\fR" 4 |
| 11891 | .IX Item "-macc-4" |
| 11892 | Use only the first four media accumulator registers. |
| 11893 | .IP "\fB\-macc\-8\fR" 4 |
| 11894 | .IX Item "-macc-8" |
| 11895 | Use all eight media accumulator registers. |
| 11896 | .IP "\fB\-mpack\fR" 4 |
| 11897 | .IX Item "-mpack" |
| 11898 | Pack \s-1VLIW\s0 instructions. |
| 11899 | .IP "\fB\-mno\-pack\fR" 4 |
| 11900 | .IX Item "-mno-pack" |
| 11901 | Do not pack \s-1VLIW\s0 instructions. |
| 11902 | .IP "\fB\-mno\-eflags\fR" 4 |
| 11903 | .IX Item "-mno-eflags" |
| 11904 | Do not mark \s-1ABI\s0 switches in e_flags. |
| 11905 | .IP "\fB\-mcond\-move\fR" 4 |
| 11906 | .IX Item "-mcond-move" |
| 11907 | Enable the use of conditional-move instructions (default). |
| 11908 | .Sp |
| 11909 | This switch is mainly for debugging the compiler and will likely be removed |
| 11910 | in a future version. |
| 11911 | .IP "\fB\-mno\-cond\-move\fR" 4 |
| 11912 | .IX Item "-mno-cond-move" |
| 11913 | Disable the use of conditional-move instructions. |
| 11914 | .Sp |
| 11915 | This switch is mainly for debugging the compiler and will likely be removed |
| 11916 | in a future version. |
| 11917 | .IP "\fB\-mscc\fR" 4 |
| 11918 | .IX Item "-mscc" |
| 11919 | Enable the use of conditional set instructions (default). |
| 11920 | .Sp |
| 11921 | This switch is mainly for debugging the compiler and will likely be removed |
| 11922 | in a future version. |
| 11923 | .IP "\fB\-mno\-scc\fR" 4 |
| 11924 | .IX Item "-mno-scc" |
| 11925 | Disable the use of conditional set instructions. |
| 11926 | .Sp |
| 11927 | This switch is mainly for debugging the compiler and will likely be removed |
| 11928 | in a future version. |
| 11929 | .IP "\fB\-mcond\-exec\fR" 4 |
| 11930 | .IX Item "-mcond-exec" |
| 11931 | Enable the use of conditional execution (default). |
| 11932 | .Sp |
| 11933 | This switch is mainly for debugging the compiler and will likely be removed |
| 11934 | in a future version. |
| 11935 | .IP "\fB\-mno\-cond\-exec\fR" 4 |
| 11936 | .IX Item "-mno-cond-exec" |
| 11937 | Disable the use of conditional execution. |
| 11938 | .Sp |
| 11939 | This switch is mainly for debugging the compiler and will likely be removed |
| 11940 | in a future version. |
| 11941 | .IP "\fB\-mvliw\-branch\fR" 4 |
| 11942 | .IX Item "-mvliw-branch" |
| 11943 | Run a pass to pack branches into \s-1VLIW\s0 instructions (default). |
| 11944 | .Sp |
| 11945 | This switch is mainly for debugging the compiler and will likely be removed |
| 11946 | in a future version. |
| 11947 | .IP "\fB\-mno\-vliw\-branch\fR" 4 |
| 11948 | .IX Item "-mno-vliw-branch" |
| 11949 | Do not run a pass to pack branches into \s-1VLIW\s0 instructions. |
| 11950 | .Sp |
| 11951 | This switch is mainly for debugging the compiler and will likely be removed |
| 11952 | in a future version. |
| 11953 | .IP "\fB\-mmulti\-cond\-exec\fR" 4 |
| 11954 | .IX Item "-mmulti-cond-exec" |
| 11955 | Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution |
| 11956 | (default). |
| 11957 | .Sp |
| 11958 | This switch is mainly for debugging the compiler and will likely be removed |
| 11959 | in a future version. |
| 11960 | .IP "\fB\-mno\-multi\-cond\-exec\fR" 4 |
| 11961 | .IX Item "-mno-multi-cond-exec" |
| 11962 | Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution. |
| 11963 | .Sp |
| 11964 | This switch is mainly for debugging the compiler and will likely be removed |
| 11965 | in a future version. |
| 11966 | .IP "\fB\-mnested\-cond\-exec\fR" 4 |
| 11967 | .IX Item "-mnested-cond-exec" |
| 11968 | Enable nested conditional execution optimizations (default). |
| 11969 | .Sp |
| 11970 | This switch is mainly for debugging the compiler and will likely be removed |
| 11971 | in a future version. |
| 11972 | .IP "\fB\-mno\-nested\-cond\-exec\fR" 4 |
| 11973 | .IX Item "-mno-nested-cond-exec" |
| 11974 | Disable nested conditional execution optimizations. |
| 11975 | .Sp |
| 11976 | This switch is mainly for debugging the compiler and will likely be removed |
| 11977 | in a future version. |
| 11978 | .IP "\fB\-moptimize\-membar\fR" 4 |
| 11979 | .IX Item "-moptimize-membar" |
| 11980 | This switch removes redundant \f(CW\*(C`membar\*(C'\fR instructions from the |
| 11981 | compiler generated code. It is enabled by default. |
| 11982 | .IP "\fB\-mno\-optimize\-membar\fR" 4 |
| 11983 | .IX Item "-mno-optimize-membar" |
| 11984 | This switch disables the automatic removal of redundant \f(CW\*(C`membar\*(C'\fR |
| 11985 | instructions from the generated code. |
| 11986 | .IP "\fB\-mtomcat\-stats\fR" 4 |
| 11987 | .IX Item "-mtomcat-stats" |
| 11988 | Cause gas to print out tomcat statistics. |
| 11989 | .IP "\fB\-mcpu=\fR\fIcpu\fR" 4 |
| 11990 | .IX Item "-mcpu=cpu" |
| 11991 | Select the processor type for which to generate code. Possible values are |
| 11992 | \&\fBfrv\fR, \fBfr550\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr450\fR, |
| 11993 | \&\fBfr405\fR, \fBfr400\fR, \fBfr300\fR and \fBsimple\fR. |
| 11994 | .PP |
| 11995 | \fIGNU/Linux Options\fR |
| 11996 | .IX Subsection "GNU/Linux Options" |
| 11997 | .PP |
| 11998 | These \fB\-m\fR options are defined for GNU/Linux targets: |
| 11999 | .IP "\fB\-mglibc\fR" 4 |
| 12000 | .IX Item "-mglibc" |
| 12001 | Use the \s-1GNU\s0 C library. This is the default except |
| 12002 | on \fB*\-*\-linux\-*uclibc*\fR and \fB*\-*\-linux\-*android*\fR targets. |
| 12003 | .IP "\fB\-muclibc\fR" 4 |
| 12004 | .IX Item "-muclibc" |
| 12005 | Use uClibc C library. This is the default on |
| 12006 | \&\fB*\-*\-linux\-*uclibc*\fR targets. |
| 12007 | .IP "\fB\-mbionic\fR" 4 |
| 12008 | .IX Item "-mbionic" |
| 12009 | Use Bionic C library. This is the default on |
| 12010 | \&\fB*\-*\-linux\-*android*\fR targets. |
| 12011 | .IP "\fB\-mandroid\fR" 4 |
| 12012 | .IX Item "-mandroid" |
| 12013 | Compile code compatible with Android platform. This is the default on |
| 12014 | \&\fB*\-*\-linux\-*android*\fR targets. |
| 12015 | .Sp |
| 12016 | When compiling, this option enables \fB\-mbionic\fR, \fB\-fPIC\fR, |
| 12017 | \&\fB\-fno\-exceptions\fR and \fB\-fno\-rtti\fR by default. When linking, |
| 12018 | this option makes the \s-1GCC\s0 driver pass Android-specific options to the linker. |
| 12019 | Finally, this option causes the preprocessor macro \f(CW\*(C`_\|_ANDROID_\|_\*(C'\fR |
| 12020 | to be defined. |
| 12021 | .IP "\fB\-tno\-android\-cc\fR" 4 |
| 12022 | .IX Item "-tno-android-cc" |
| 12023 | Disable compilation effects of \fB\-mandroid\fR, i.e., do not enable |
| 12024 | \&\fB\-mbionic\fR, \fB\-fPIC\fR, \fB\-fno\-exceptions\fR and |
| 12025 | \&\fB\-fno\-rtti\fR by default. |
| 12026 | .IP "\fB\-tno\-android\-ld\fR" 4 |
| 12027 | .IX Item "-tno-android-ld" |
| 12028 | Disable linking effects of \fB\-mandroid\fR, i.e., pass standard Linux |
| 12029 | linking options to the linker. |
| 12030 | .PP |
| 12031 | \fIH8/300 Options\fR |
| 12032 | .IX Subsection "H8/300 Options" |
| 12033 | .PP |
| 12034 | These \fB\-m\fR options are defined for the H8/300 implementations: |
| 12035 | .IP "\fB\-mrelax\fR" 4 |
| 12036 | .IX Item "-mrelax" |
| 12037 | Shorten some address references at link time, when possible; uses the |
| 12038 | linker option \fB\-relax\fR. |
| 12039 | .IP "\fB\-mh\fR" 4 |
| 12040 | .IX Item "-mh" |
| 12041 | Generate code for the H8/300H. |
| 12042 | .IP "\fB\-ms\fR" 4 |
| 12043 | .IX Item "-ms" |
| 12044 | Generate code for the H8S. |
| 12045 | .IP "\fB\-mn\fR" 4 |
| 12046 | .IX Item "-mn" |
| 12047 | Generate code for the H8S and H8/300H in the normal mode. This switch |
| 12048 | must be used either with \fB\-mh\fR or \fB\-ms\fR. |
| 12049 | .IP "\fB\-ms2600\fR" 4 |
| 12050 | .IX Item "-ms2600" |
| 12051 | Generate code for the H8S/2600. This switch must be used with \fB\-ms\fR. |
| 12052 | .IP "\fB\-mint32\fR" 4 |
| 12053 | .IX Item "-mint32" |
| 12054 | Make \f(CW\*(C`int\*(C'\fR data 32 bits by default. |
| 12055 | .IP "\fB\-malign\-300\fR" 4 |
| 12056 | .IX Item "-malign-300" |
| 12057 | On the H8/300H and H8S, use the same alignment rules as for the H8/300. |
| 12058 | The default for the H8/300H and H8S is to align longs and floats on |
| 12059 | 4\-byte boundaries. |
| 12060 | \&\fB\-malign\-300\fR causes them to be aligned on 2\-byte boundaries. |
| 12061 | This option has no effect on the H8/300. |
| 12062 | .PP |
| 12063 | \fI\s-1HPPA\s0 Options\fR |
| 12064 | .IX Subsection "HPPA Options" |
| 12065 | .PP |
| 12066 | These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers: |
| 12067 | .IP "\fB\-march=\fR\fIarchitecture-type\fR" 4 |
| 12068 | .IX Item "-march=architecture-type" |
| 12069 | Generate code for the specified architecture. The choices for |
| 12070 | \&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0 |
| 12071 | 1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors. Refer to |
| 12072 | \&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper |
| 12073 | architecture option for your machine. Code compiled for lower numbered |
| 12074 | architectures will run on higher numbered architectures, but not the |
| 12075 | other way around. |
| 12076 | .IP "\fB\-mpa\-risc\-1\-0\fR" 4 |
| 12077 | .IX Item "-mpa-risc-1-0" |
| 12078 | .PD 0 |
| 12079 | .IP "\fB\-mpa\-risc\-1\-1\fR" 4 |
| 12080 | .IX Item "-mpa-risc-1-1" |
| 12081 | .IP "\fB\-mpa\-risc\-2\-0\fR" 4 |
| 12082 | .IX Item "-mpa-risc-2-0" |
| 12083 | .PD |
| 12084 | Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively. |
| 12085 | .IP "\fB\-mbig\-switch\fR" 4 |
| 12086 | .IX Item "-mbig-switch" |
| 12087 | Generate code suitable for big switch tables. Use this option only if |
| 12088 | the assembler/linker complain about out of range branches within a switch |
| 12089 | table. |
| 12090 | .IP "\fB\-mjump\-in\-delay\fR" 4 |
| 12091 | .IX Item "-mjump-in-delay" |
| 12092 | Fill delay slots of function calls with unconditional jump instructions |
| 12093 | by modifying the return pointer for the function call to be the target |
| 12094 | of the conditional jump. |
| 12095 | .IP "\fB\-mdisable\-fpregs\fR" 4 |
| 12096 | .IX Item "-mdisable-fpregs" |
| 12097 | Prevent floating-point registers from being used in any manner. This is |
| 12098 | necessary for compiling kernels that perform lazy context switching of |
| 12099 | floating-point registers. If you use this option and attempt to perform |
| 12100 | floating-point operations, the compiler aborts. |
| 12101 | .IP "\fB\-mdisable\-indexing\fR" 4 |
| 12102 | .IX Item "-mdisable-indexing" |
| 12103 | Prevent the compiler from using indexing address modes. This avoids some |
| 12104 | rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0. |
| 12105 | .IP "\fB\-mno\-space\-regs\fR" 4 |
| 12106 | .IX Item "-mno-space-regs" |
| 12107 | Generate code that assumes the target has no space registers. This allows |
| 12108 | \&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes. |
| 12109 | .Sp |
| 12110 | Such code is suitable for level 0 \s-1PA\s0 systems and kernels. |
| 12111 | .IP "\fB\-mfast\-indirect\-calls\fR" 4 |
| 12112 | .IX Item "-mfast-indirect-calls" |
| 12113 | Generate code that assumes calls never cross space boundaries. This |
| 12114 | allows \s-1GCC\s0 to emit code that performs faster indirect calls. |
| 12115 | .Sp |
| 12116 | This option will not work in the presence of shared libraries or nested |
| 12117 | functions. |
| 12118 | .IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 |
| 12119 | .IX Item "-mfixed-range=register-range" |
| 12120 | Generate code treating the given register range as fixed registers. |
| 12121 | A fixed register is one that the register allocator can not use. This is |
| 12122 | useful when compiling kernel code. A register range is specified as |
| 12123 | two registers separated by a dash. Multiple register ranges can be |
| 12124 | specified separated by a comma. |
| 12125 | .IP "\fB\-mlong\-load\-store\fR" 4 |
| 12126 | .IX Item "-mlong-load-store" |
| 12127 | Generate 3\-instruction load and store sequences as sometimes required by |
| 12128 | the HP-UX 10 linker. This is equivalent to the \fB+k\fR option to |
| 12129 | the \s-1HP\s0 compilers. |
| 12130 | .IP "\fB\-mportable\-runtime\fR" 4 |
| 12131 | .IX Item "-mportable-runtime" |
| 12132 | Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems. |
| 12133 | .IP "\fB\-mgas\fR" 4 |
| 12134 | .IX Item "-mgas" |
| 12135 | Enable the use of assembler directives only \s-1GAS\s0 understands. |
| 12136 | .IP "\fB\-mschedule=\fR\fIcpu-type\fR" 4 |
| 12137 | .IX Item "-mschedule=cpu-type" |
| 12138 | Schedule code according to the constraints for the machine type |
| 12139 | \&\fIcpu-type\fR. The choices for \fIcpu-type\fR are \fB700\fR |
| 12140 | \&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR. Refer |
| 12141 | to \fI/usr/lib/sched.models\fR on an HP-UX system to determine the |
| 12142 | proper scheduling option for your machine. The default scheduling is |
| 12143 | \&\fB8000\fR. |
| 12144 | .IP "\fB\-mlinker\-opt\fR" 4 |
| 12145 | .IX Item "-mlinker-opt" |
| 12146 | Enable the optimization pass in the HP-UX linker. Note this makes symbolic |
| 12147 | debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9 |
| 12148 | linkers in which they give bogus error messages when linking some programs. |
| 12149 | .IP "\fB\-msoft\-float\fR" 4 |
| 12150 | .IX Item "-msoft-float" |
| 12151 | Generate output containing library calls for floating point. |
| 12152 | \&\fBWarning:\fR the requisite libraries are not available for all \s-1HPPA\s0 |
| 12153 | targets. Normally the facilities of the machine's usual C compiler are |
| 12154 | used, but this cannot be done directly in cross-compilation. You must make |
| 12155 | your own arrangements to provide suitable library functions for |
| 12156 | cross-compilation. |
| 12157 | .Sp |
| 12158 | \&\fB\-msoft\-float\fR changes the calling convention in the output file; |
| 12159 | therefore, it is only useful if you compile \fIall\fR of a program with |
| 12160 | this option. In particular, you need to compile \fIlibgcc.a\fR, the |
| 12161 | library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for |
| 12162 | this to work. |
| 12163 | .IP "\fB\-msio\fR" 4 |
| 12164 | .IX Item "-msio" |
| 12165 | Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO\s0. The default is |
| 12166 | \&\fB\-mwsio\fR. This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR, |
| 12167 | \&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO\s0. These |
| 12168 | options are available under HP-UX and HI-UX. |
| 12169 | .IP "\fB\-mgnu\-ld\fR" 4 |
| 12170 | .IX Item "-mgnu-ld" |
| 12171 | Use \s-1GNU\s0 ld specific options. This passes \fB\-shared\fR to ld when |
| 12172 | building a shared library. It is the default when \s-1GCC\s0 is configured, |
| 12173 | explicitly or implicitly, with the \s-1GNU\s0 linker. This option does not |
| 12174 | have any affect on which ld is called, it only changes what parameters |
| 12175 | are passed to that ld. The ld that is called is determined by the |
| 12176 | \&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and |
| 12177 | finally by the user's \fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed |
| 12178 | using \fBwhich `gcc \-print\-prog\-name=ld`\fR. This option is only available |
| 12179 | on the 64\-bit HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. |
| 12180 | .IP "\fB\-mhp\-ld\fR" 4 |
| 12181 | .IX Item "-mhp-ld" |
| 12182 | Use \s-1HP\s0 ld specific options. This passes \fB\-b\fR to ld when building |
| 12183 | a shared library and passes \fB+Accept TypeMismatch\fR to ld on all |
| 12184 | links. It is the default when \s-1GCC\s0 is configured, explicitly or |
| 12185 | implicitly, with the \s-1HP\s0 linker. This option does not have any affect on |
| 12186 | which ld is called, it only changes what parameters are passed to that |
| 12187 | ld. The ld that is called is determined by the \fB\-\-with\-ld\fR |
| 12188 | configure option, \s-1GCC\s0's program search path, and finally by the user's |
| 12189 | \&\fB\s-1PATH\s0\fR. The linker used by \s-1GCC\s0 can be printed using \fBwhich |
| 12190 | `gcc \-print\-prog\-name=ld`\fR. This option is only available on the 64\-bit |
| 12191 | HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR. |
| 12192 | .IP "\fB\-mlong\-calls\fR" 4 |
| 12193 | .IX Item "-mlong-calls" |
| 12194 | Generate code that uses long call sequences. This ensures that a call |
| 12195 | is always able to reach linker generated stubs. The default is to generate |
| 12196 | long calls only when the distance from the call site to the beginning |
| 12197 | of the function or translation unit, as the case may be, exceeds a |
| 12198 | predefined limit set by the branch type being used. The limits for |
| 12199 | normal calls are 7,600,000 and 240,000 bytes, respectively for the |
| 12200 | \&\s-1PA\s0 2.0 and \s-1PA\s0 1.X architectures. Sibcalls are always limited at |
| 12201 | 240,000 bytes. |
| 12202 | .Sp |
| 12203 | Distances are measured from the beginning of functions when using the |
| 12204 | \&\fB\-ffunction\-sections\fR option, or when using the \fB\-mgas\fR |
| 12205 | and \fB\-mno\-portable\-runtime\fR options together under HP-UX with |
| 12206 | the \s-1SOM\s0 linker. |
| 12207 | .Sp |
| 12208 | It is normally not desirable to use this option as it will degrade |
| 12209 | performance. However, it may be useful in large applications, |
| 12210 | particularly when partial linking is used to build the application. |
| 12211 | .Sp |
| 12212 | The types of long calls used depends on the capabilities of the |
| 12213 | assembler and linker, and the type of code being generated. The |
| 12214 | impact on systems that support long absolute calls, and long pic |
| 12215 | symbol-difference or pc-relative calls should be relatively small. |
| 12216 | However, an indirect call is used on 32\-bit \s-1ELF\s0 systems in pic code |
| 12217 | and it is quite long. |
| 12218 | .IP "\fB\-munix=\fR\fIunix-std\fR" 4 |
| 12219 | .IX Item "-munix=unix-std" |
| 12220 | Generate compiler predefines and select a startfile for the specified |
| 12221 | \&\s-1UNIX\s0 standard. The choices for \fIunix-std\fR are \fB93\fR, \fB95\fR |
| 12222 | and \fB98\fR. \fB93\fR is supported on all HP-UX versions. \fB95\fR |
| 12223 | is available on HP-UX 10.10 and later. \fB98\fR is available on HP-UX |
| 12224 | 11.11 and later. The default values are \fB93\fR for HP-UX 10.00, |
| 12225 | \&\fB95\fR for HP-UX 10.10 though to 11.00, and \fB98\fR for HP-UX 11.11 |
| 12226 | and later. |
| 12227 | .Sp |
| 12228 | \&\fB\-munix=93\fR provides the same predefines as \s-1GCC\s0 3.3 and 3.4. |
| 12229 | \&\fB\-munix=95\fR provides additional predefines for \f(CW\*(C`XOPEN_UNIX\*(C'\fR |
| 12230 | and \f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, and the startfile \fIunix95.o\fR. |
| 12231 | \&\fB\-munix=98\fR provides additional predefines for \f(CW\*(C`_XOPEN_UNIX\*(C'\fR, |
| 12232 | \&\f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, \f(CW\*(C`_INCLUDE_\|_STDC_A1_SOURCE\*(C'\fR and |
| 12233 | \&\f(CW\*(C`_INCLUDE_XOPEN_SOURCE_500\*(C'\fR, and the startfile \fIunix98.o\fR. |
| 12234 | .Sp |
| 12235 | It is \fIimportant\fR to note that this option changes the interfaces |
| 12236 | for various library routines. It also affects the operational behavior |
| 12237 | of the C library. Thus, \fIextreme\fR care is needed in using this |
| 12238 | option. |
| 12239 | .Sp |
| 12240 | Library code that is intended to operate with more than one \s-1UNIX\s0 |
| 12241 | standard must test, set and restore the variable \fI_\|_xpg4_extended_mask\fR |
| 12242 | as appropriate. Most \s-1GNU\s0 software doesn't provide this capability. |
| 12243 | .IP "\fB\-nolibdld\fR" 4 |
| 12244 | .IX Item "-nolibdld" |
| 12245 | Suppress the generation of link options to search libdld.sl when the |
| 12246 | \&\fB\-static\fR option is specified on HP-UX 10 and later. |
| 12247 | .IP "\fB\-static\fR" 4 |
| 12248 | .IX Item "-static" |
| 12249 | The HP-UX implementation of setlocale in libc has a dependency on |
| 12250 | libdld.sl. There isn't an archive version of libdld.sl. Thus, |
| 12251 | when the \fB\-static\fR option is specified, special link options |
| 12252 | are needed to resolve this dependency. |
| 12253 | .Sp |
| 12254 | On HP-UX 10 and later, the \s-1GCC\s0 driver adds the necessary options to |
| 12255 | link with libdld.sl when the \fB\-static\fR option is specified. |
| 12256 | This causes the resulting binary to be dynamic. On the 64\-bit port, |
| 12257 | the linkers generate dynamic binaries by default in any case. The |
| 12258 | \&\fB\-nolibdld\fR option can be used to prevent the \s-1GCC\s0 driver from |
| 12259 | adding these link options. |
| 12260 | .IP "\fB\-threads\fR" 4 |
| 12261 | .IX Item "-threads" |
| 12262 | Add support for multithreading with the \fIdce thread\fR library |
| 12263 | under HP-UX. This option sets flags for both the preprocessor and |
| 12264 | linker. |
| 12265 | .PP |
| 12266 | \fIIntel 386 and \s-1AMD\s0 x86\-64 Options\fR |
| 12267 | .IX Subsection "Intel 386 and AMD x86-64 Options" |
| 12268 | .PP |
| 12269 | These \fB\-m\fR options are defined for the i386 and x86\-64 family of |
| 12270 | computers: |
| 12271 | .IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 |
| 12272 | .IX Item "-mtune=cpu-type" |
| 12273 | Tune to \fIcpu-type\fR everything applicable about the generated code, except |
| 12274 | for the \s-1ABI\s0 and the set of available instructions. The choices for |
| 12275 | \&\fIcpu-type\fR are: |
| 12276 | .RS 4 |
| 12277 | .IP "\fIgeneric\fR" 4 |
| 12278 | .IX Item "generic" |
| 12279 | Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors. |
| 12280 | If you know the \s-1CPU\s0 on which your code will run, then you should use |
| 12281 | the corresponding \fB\-mtune\fR option instead of |
| 12282 | \&\fB\-mtune=generic\fR. But, if you do not know exactly what \s-1CPU\s0 users |
| 12283 | of your application will have, then you should use this option. |
| 12284 | .Sp |
| 12285 | As new processors are deployed in the marketplace, the behavior of this |
| 12286 | option will change. Therefore, if you upgrade to a newer version of |
| 12287 | \&\s-1GCC\s0, the code generated option will change to reflect the processors |
| 12288 | that were most common when that version of \s-1GCC\s0 was released. |
| 12289 | .Sp |
| 12290 | There is no \fB\-march=generic\fR option because \fB\-march\fR |
| 12291 | indicates the instruction set the compiler can use, and there is no |
| 12292 | generic instruction set applicable to all processors. In contrast, |
| 12293 | \&\fB\-mtune\fR indicates the processor (or, in this case, collection of |
| 12294 | processors) for which the code is optimized. |
| 12295 | .IP "\fInative\fR" 4 |
| 12296 | .IX Item "native" |
| 12297 | This selects the \s-1CPU\s0 to tune for at compilation time by determining |
| 12298 | the processor type of the compiling machine. Using \fB\-mtune=native\fR |
| 12299 | will produce code optimized for the local machine under the constraints |
| 12300 | of the selected instruction set. Using \fB\-march=native\fR will |
| 12301 | enable all instruction subsets supported by the local machine (hence |
| 12302 | the result might not run on different machines). |
| 12303 | .IP "\fIi386\fR" 4 |
| 12304 | .IX Item "i386" |
| 12305 | Original Intel's i386 \s-1CPU\s0. |
| 12306 | .IP "\fIi486\fR" 4 |
| 12307 | .IX Item "i486" |
| 12308 | Intel's i486 \s-1CPU\s0. (No scheduling is implemented for this chip.) |
| 12309 | .IP "\fIi586, pentium\fR" 4 |
| 12310 | .IX Item "i586, pentium" |
| 12311 | Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support. |
| 12312 | .IP "\fIpentium-mmx\fR" 4 |
| 12313 | .IX Item "pentium-mmx" |
| 12314 | Intel PentiumMMX \s-1CPU\s0 based on Pentium core with \s-1MMX\s0 instruction set support. |
| 12315 | .IP "\fIpentiumpro\fR" 4 |
| 12316 | .IX Item "pentiumpro" |
| 12317 | Intel PentiumPro \s-1CPU\s0. |
| 12318 | .IP "\fIi686\fR" 4 |
| 12319 | .IX Item "i686" |
| 12320 | Same as \f(CW\*(C`generic\*(C'\fR, but when used as \f(CW\*(C`march\*(C'\fR option, PentiumPro |
| 12321 | instruction set will be used, so the code will run on all i686 family chips. |
| 12322 | .IP "\fIpentium2\fR" 4 |
| 12323 | .IX Item "pentium2" |
| 12324 | Intel Pentium2 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 instruction set support. |
| 12325 | .IP "\fIpentium3, pentium3m\fR" 4 |
| 12326 | .IX Item "pentium3, pentium3m" |
| 12327 | Intel Pentium3 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 and \s-1SSE\s0 instruction set |
| 12328 | support. |
| 12329 | .IP "\fIpentium-m\fR" 4 |
| 12330 | .IX Item "pentium-m" |
| 12331 | Low power version of Intel Pentium3 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set |
| 12332 | support. Used by Centrino notebooks. |
| 12333 | .IP "\fIpentium4, pentium4m\fR" 4 |
| 12334 | .IX Item "pentium4, pentium4m" |
| 12335 | Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support. |
| 12336 | .IP "\fIprescott\fR" 4 |
| 12337 | .IX Item "prescott" |
| 12338 | Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction |
| 12339 | set support. |
| 12340 | .IP "\fInocona\fR" 4 |
| 12341 | .IX Item "nocona" |
| 12342 | Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, |
| 12343 | \&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support. |
| 12344 | .IP "\fIcore2\fR" 4 |
| 12345 | .IX Item "core2" |
| 12346 | Intel Core2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 |
| 12347 | instruction set support. |
| 12348 | .IP "\fIcorei7\fR" 4 |
| 12349 | .IX Item "corei7" |
| 12350 | Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1 |
| 12351 | and \s-1SSE4\s0.2 instruction set support. |
| 12352 | .IP "\fIcorei7\-avx\fR" 4 |
| 12353 | .IX Item "corei7-avx" |
| 12354 | Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, |
| 12355 | \&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0 and \s-1PCLMUL\s0 instruction set support. |
| 12356 | .IP "\fIcore-avx-i\fR" 4 |
| 12357 | .IX Item "core-avx-i" |
| 12358 | Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, |
| 12359 | \&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction |
| 12360 | set support. |
| 12361 | .IP "\fIatom\fR" 4 |
| 12362 | .IX Item "atom" |
| 12363 | Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 |
| 12364 | instruction set support. |
| 12365 | .IP "\fIk6\fR" 4 |
| 12366 | .IX Item "k6" |
| 12367 | \&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support. |
| 12368 | .IP "\fIk6\-2, k6\-3\fR" 4 |
| 12369 | .IX Item "k6-2, k6-3" |
| 12370 | Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. |
| 12371 | .IP "\fIathlon, athlon-tbird\fR" 4 |
| 12372 | .IX Item "athlon, athlon-tbird" |
| 12373 | \&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3DNow! and \s-1SSE\s0 prefetch instructions |
| 12374 | support. |
| 12375 | .IP "\fIathlon\-4, athlon-xp, athlon-mp\fR" 4 |
| 12376 | .IX Item "athlon-4, athlon-xp, athlon-mp" |
| 12377 | Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3DNow!, enhanced 3DNow! and full \s-1SSE\s0 |
| 12378 | instruction set support. |
| 12379 | .IP "\fIk8, opteron, athlon64, athlon-fx\fR" 4 |
| 12380 | .IX Item "k8, opteron, athlon64, athlon-fx" |
| 12381 | \&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support. (This supersets |
| 12382 | \&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3DNow!, enhanced 3DNow! and 64\-bit instruction set extensions.) |
| 12383 | .IP "\fIk8\-sse3, opteron\-sse3, athlon64\-sse3\fR" 4 |
| 12384 | .IX Item "k8-sse3, opteron-sse3, athlon64-sse3" |
| 12385 | Improved versions of k8, opteron and athlon64 with \s-1SSE3\s0 instruction set support. |
| 12386 | .IP "\fIamdfam10, barcelona\fR" 4 |
| 12387 | .IX Item "amdfam10, barcelona" |
| 12388 | \&\s-1AMD\s0 Family 10h core based CPUs with x86\-64 instruction set support. (This |
| 12389 | supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, 3DNow!, enhanced 3DNow!, \s-1ABM\s0 and 64\-bit |
| 12390 | instruction set extensions.) |
| 12391 | .IP "\fIbdver1\fR" 4 |
| 12392 | .IX Item "bdver1" |
| 12393 | \&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This |
| 12394 | supersets \s-1FMA4\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, |
| 12395 | \&\s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set extensions.) |
| 12396 | .IP "\fIbdver2\fR" 4 |
| 12397 | .IX Item "bdver2" |
| 12398 | \&\s-1AMD\s0 Family 15h core based CPUs with x86\-64 instruction set support. (This |
| 12399 | supersets \s-1BMI\s0, \s-1TBM\s0, F16C, \s-1FMA\s0, \s-1AVX\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1AES\s0, \s-1PCL_MUL\s0, \s-1CX16\s0, \s-1MMX\s0, \s-1SSE\s0, |
| 12400 | \&\s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1ABM\s0 and 64\-bit instruction set |
| 12401 | extensions.) |
| 12402 | .IP "\fIbtver1\fR" 4 |
| 12403 | .IX Item "btver1" |
| 12404 | \&\s-1AMD\s0 Family 14h core based CPUs with x86\-64 instruction set support. (This |
| 12405 | supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4A\s0, \s-1CX16\s0, \s-1ABM\s0 and 64\-bit |
| 12406 | instruction set extensions.) |
| 12407 | .IP "\fIwinchip\-c6\fR" 4 |
| 12408 | .IX Item "winchip-c6" |
| 12409 | \&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction |
| 12410 | set support. |
| 12411 | .IP "\fIwinchip2\fR" 4 |
| 12412 | .IX Item "winchip2" |
| 12413 | \&\s-1IDT\s0 Winchip2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3DNow! |
| 12414 | instruction set support. |
| 12415 | .IP "\fIc3\fR" 4 |
| 12416 | .IX Item "c3" |
| 12417 | Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. (No scheduling is |
| 12418 | implemented for this chip.) |
| 12419 | .IP "\fIc3\-2\fR" 4 |
| 12420 | .IX Item "c3-2" |
| 12421 | Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support. (No scheduling is |
| 12422 | implemented for this chip.) |
| 12423 | .IP "\fIgeode\fR" 4 |
| 12424 | .IX Item "geode" |
| 12425 | Embedded \s-1AMD\s0 \s-1CPU\s0 with \s-1MMX\s0 and 3DNow! instruction set support. |
| 12426 | .RE |
| 12427 | .RS 4 |
| 12428 | .Sp |
| 12429 | While picking a specific \fIcpu-type\fR will schedule things appropriately |
| 12430 | for that particular chip, the compiler will not generate any code that |
| 12431 | does not run on the default machine type without the \fB\-march=\fR\fIcpu-type\fR |
| 12432 | option being used. For example, if \s-1GCC\s0 is configured for i686\-pc\-linux\-gnu |
| 12433 | then \fB\-mtune=pentium4\fR will generate code that is tuned for Pentium4 |
| 12434 | but will still run on i686 machines. |
| 12435 | .RE |
| 12436 | .IP "\fB\-march=\fR\fIcpu-type\fR" 4 |
| 12437 | .IX Item "-march=cpu-type" |
| 12438 | Generate instructions for the machine type \fIcpu-type\fR. The choices |
| 12439 | for \fIcpu-type\fR are the same as for \fB\-mtune\fR. Moreover, |
| 12440 | specifying \fB\-march=\fR\fIcpu-type\fR implies \fB\-mtune=\fR\fIcpu-type\fR. |
| 12441 | .IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 |
| 12442 | .IX Item "-mcpu=cpu-type" |
| 12443 | A deprecated synonym for \fB\-mtune\fR. |
| 12444 | .IP "\fB\-mfpmath=\fR\fIunit\fR" 4 |
| 12445 | .IX Item "-mfpmath=unit" |
| 12446 | Generate floating-point arithmetic for selected unit \fIunit\fR. The choices |
| 12447 | for \fIunit\fR are: |
| 12448 | .RS 4 |
| 12449 | .IP "\fB387\fR" 4 |
| 12450 | .IX Item "387" |
| 12451 | Use the standard 387 floating-point coprocessor present on the majority of chips and |
| 12452 | emulated otherwise. Code compiled with this option runs almost everywhere. |
| 12453 | The temporary results are computed in 80\-bit precision instead of the precision |
| 12454 | specified by the type, resulting in slightly different results compared to most |
| 12455 | of other chips. See \fB\-ffloat\-store\fR for more detailed description. |
| 12456 | .Sp |
| 12457 | This is the default choice for i386 compiler. |
| 12458 | .IP "\fBsse\fR" 4 |
| 12459 | .IX Item "sse" |
| 12460 | Use scalar floating-point instructions present in the \s-1SSE\s0 instruction set. |
| 12461 | This instruction set is supported by Pentium3 and newer chips, in the \s-1AMD\s0 line |
| 12462 | by Athlon\-4, Athlon-xp and Athlon-mp chips. The earlier version of \s-1SSE\s0 |
| 12463 | instruction set supports only single-precision arithmetic, thus the double and |
| 12464 | extended-precision arithmetic are still done using 387. A later version, present |
| 12465 | only in Pentium4 and the future \s-1AMD\s0 x86\-64 chips, supports double-precision |
| 12466 | arithmetic too. |
| 12467 | .Sp |
| 12468 | For the i386 compiler, you need to use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR |
| 12469 | or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option |
| 12470 | effective. For the x86\-64 compiler, these extensions are enabled by default. |
| 12471 | .Sp |
| 12472 | The resulting code should be considerably faster in the majority of cases and avoid |
| 12473 | the numerical instability problems of 387 code, but may break some existing |
| 12474 | code that expects temporaries to be 80 bits. |
| 12475 | .Sp |
| 12476 | This is the default choice for the x86\-64 compiler. |
| 12477 | .IP "\fBsse,387\fR" 4 |
| 12478 | .IX Item "sse,387" |
| 12479 | .PD 0 |
| 12480 | .IP "\fBsse+387\fR" 4 |
| 12481 | .IX Item "sse+387" |
| 12482 | .IP "\fBboth\fR" 4 |
| 12483 | .IX Item "both" |
| 12484 | .PD |
| 12485 | Attempt to utilize both instruction sets at once. This effectively double the |
| 12486 | amount of available registers and on chips with separate execution units for |
| 12487 | 387 and \s-1SSE\s0 the execution resources too. Use this option with care, as it is |
| 12488 | still experimental, because the \s-1GCC\s0 register allocator does not model separate |
| 12489 | functional units well resulting in instable performance. |
| 12490 | .RE |
| 12491 | .RS 4 |
| 12492 | .RE |
| 12493 | .IP "\fB\-masm=\fR\fIdialect\fR" 4 |
| 12494 | .IX Item "-masm=dialect" |
| 12495 | Output asm instructions using selected \fIdialect\fR. Supported |
| 12496 | choices are \fBintel\fR or \fBatt\fR (the default one). Darwin does |
| 12497 | not support \fBintel\fR. |
| 12498 | .IP "\fB\-mieee\-fp\fR" 4 |
| 12499 | .IX Item "-mieee-fp" |
| 12500 | .PD 0 |
| 12501 | .IP "\fB\-mno\-ieee\-fp\fR" 4 |
| 12502 | .IX Item "-mno-ieee-fp" |
| 12503 | .PD |
| 12504 | Control whether or not the compiler uses \s-1IEEE\s0 floating-point |
| 12505 | comparisons. These handle correctly the case where the result of a |
| 12506 | comparison is unordered. |
| 12507 | .IP "\fB\-msoft\-float\fR" 4 |
| 12508 | .IX Item "-msoft-float" |
| 12509 | Generate output containing library calls for floating point. |
| 12510 | \&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0. |
| 12511 | Normally the facilities of the machine's usual C compiler are used, but |
| 12512 | this can't be done directly in cross-compilation. You must make your |
| 12513 | own arrangements to provide suitable library functions for |
| 12514 | cross-compilation. |
| 12515 | .Sp |
| 12516 | On machines where a function returns floating-point results in the 80387 |
| 12517 | register stack, some floating-point opcodes may be emitted even if |
| 12518 | \&\fB\-msoft\-float\fR is used. |
| 12519 | .IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4 |
| 12520 | .IX Item "-mno-fp-ret-in-387" |
| 12521 | Do not use the \s-1FPU\s0 registers for return values of functions. |
| 12522 | .Sp |
| 12523 | The usual calling convention has functions return values of types |
| 12524 | \&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there |
| 12525 | is no \s-1FPU\s0. The idea is that the operating system should emulate |
| 12526 | an \s-1FPU\s0. |
| 12527 | .Sp |
| 12528 | The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned |
| 12529 | in ordinary \s-1CPU\s0 registers instead. |
| 12530 | .IP "\fB\-mno\-fancy\-math\-387\fR" 4 |
| 12531 | .IX Item "-mno-fancy-math-387" |
| 12532 | Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and |
| 12533 | \&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387. Specify this option to avoid |
| 12534 | generating those instructions. This option is the default on FreeBSD, |
| 12535 | OpenBSD and NetBSD. This option is overridden when \fB\-march\fR |
| 12536 | indicates that the target \s-1CPU\s0 will always have an \s-1FPU\s0 and so the |
| 12537 | instruction will not need emulation. As of revision 2.6.1, these |
| 12538 | instructions are not generated unless you also use the |
| 12539 | \&\fB\-funsafe\-math\-optimizations\fR switch. |
| 12540 | .IP "\fB\-malign\-double\fR" 4 |
| 12541 | .IX Item "-malign-double" |
| 12542 | .PD 0 |
| 12543 | .IP "\fB\-mno\-align\-double\fR" 4 |
| 12544 | .IX Item "-mno-align-double" |
| 12545 | .PD |
| 12546 | Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and |
| 12547 | \&\f(CW\*(C`long long\*(C'\fR variables on a two-word boundary or a one-word |
| 12548 | boundary. Aligning \f(CW\*(C`double\*(C'\fR variables on a two-word boundary |
| 12549 | produces code that runs somewhat faster on a \fBPentium\fR at the |
| 12550 | expense of more memory. |
| 12551 | .Sp |
| 12552 | On x86\-64, \fB\-malign\-double\fR is enabled by default. |
| 12553 | .Sp |
| 12554 | \&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch, |
| 12555 | structures containing the above types will be aligned differently than |
| 12556 | the published application binary interface specifications for the 386 |
| 12557 | and will not be binary compatible with structures in code compiled |
| 12558 | without that switch. |
| 12559 | .IP "\fB\-m96bit\-long\-double\fR" 4 |
| 12560 | .IX Item "-m96bit-long-double" |
| 12561 | .PD 0 |
| 12562 | .IP "\fB\-m128bit\-long\-double\fR" 4 |
| 12563 | .IX Item "-m128bit-long-double" |
| 12564 | .PD |
| 12565 | These switches control the size of \f(CW\*(C`long double\*(C'\fR type. The i386 |
| 12566 | application binary interface specifies the size to be 96 bits, |
| 12567 | so \fB\-m96bit\-long\-double\fR is the default in 32\-bit mode. |
| 12568 | .Sp |
| 12569 | Modern architectures (Pentium and newer) prefer \f(CW\*(C`long double\*(C'\fR |
| 12570 | to be aligned to an 8\- or 16\-byte boundary. In arrays or structures |
| 12571 | conforming to the \s-1ABI\s0, this is not possible. So specifying |
| 12572 | \&\fB\-m128bit\-long\-double\fR aligns \f(CW\*(C`long double\*(C'\fR |
| 12573 | to a 16\-byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional |
| 12574 | 32\-bit zero. |
| 12575 | .Sp |
| 12576 | In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as |
| 12577 | its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is to be aligned on 16\-byte boundary. |
| 12578 | .Sp |
| 12579 | Notice that neither of these options enable any extra precision over the x87 |
| 12580 | standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR. |
| 12581 | .Sp |
| 12582 | \&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, the |
| 12583 | structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables will change |
| 12584 | their size as well as function calling convention for function taking |
| 12585 | \&\f(CW\*(C`long double\*(C'\fR will be modified. Hence they will not be binary |
| 12586 | compatible with arrays or structures in code compiled without that switch. |
| 12587 | .IP "\fB\-mlarge\-data\-threshold=\fR\fInumber\fR" 4 |
| 12588 | .IX Item "-mlarge-data-threshold=number" |
| 12589 | When \fB\-mcmodel=medium\fR is specified, the data greater than |
| 12590 | \&\fIthreshold\fR are placed in large data section. This value must be the |
| 12591 | same across all object linked into the binary and defaults to 65535. |
| 12592 | .IP "\fB\-mrtd\fR" 4 |
| 12593 | .IX Item "-mrtd" |
| 12594 | Use a different function-calling convention, in which functions that |
| 12595 | take a fixed number of arguments return with the \f(CW\*(C`ret\*(C'\fR \fInum\fR |
| 12596 | instruction, which pops their arguments while returning. This saves one |
| 12597 | instruction in the caller since there is no need to pop the arguments |
| 12598 | there. |
| 12599 | .Sp |
| 12600 | You can specify that an individual function is called with this calling |
| 12601 | sequence with the function attribute \fBstdcall\fR. You can also |
| 12602 | override the \fB\-mrtd\fR option by using the function attribute |
| 12603 | \&\fBcdecl\fR. |
| 12604 | .Sp |
| 12605 | \&\fBWarning:\fR this calling convention is incompatible with the one |
| 12606 | normally used on Unix, so you cannot use it if you need to call |
| 12607 | libraries compiled with the Unix compiler. |
| 12608 | .Sp |
| 12609 | Also, you must provide function prototypes for all functions that |
| 12610 | take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); |
| 12611 | otherwise incorrect code will be generated for calls to those |
| 12612 | functions. |
| 12613 | .Sp |
| 12614 | In addition, seriously incorrect code will result if you call a |
| 12615 | function with too many arguments. (Normally, extra arguments are |
| 12616 | harmlessly ignored.) |
| 12617 | .IP "\fB\-mregparm=\fR\fInum\fR" 4 |
| 12618 | .IX Item "-mregparm=num" |
| 12619 | Control how many registers are used to pass integer arguments. By |
| 12620 | default, no registers are used to pass arguments, and at most 3 |
| 12621 | registers can be used. You can control this behavior for a specific |
| 12622 | function by using the function attribute \fBregparm\fR. |
| 12623 | .Sp |
| 12624 | \&\fBWarning:\fR if you use this switch, and |
| 12625 | \&\fInum\fR is nonzero, then you must build all modules with the same |
| 12626 | value, including any libraries. This includes the system libraries and |
| 12627 | startup modules. |
| 12628 | .IP "\fB\-msseregparm\fR" 4 |
| 12629 | .IX Item "-msseregparm" |
| 12630 | Use \s-1SSE\s0 register passing conventions for float and double arguments |
| 12631 | and return values. You can control this behavior for a specific |
| 12632 | function by using the function attribute \fBsseregparm\fR. |
| 12633 | .Sp |
| 12634 | \&\fBWarning:\fR if you use this switch then you must build all |
| 12635 | modules with the same value, including any libraries. This includes |
| 12636 | the system libraries and startup modules. |
| 12637 | .IP "\fB\-mvect8\-ret\-in\-mem\fR" 4 |
| 12638 | .IX Item "-mvect8-ret-in-mem" |
| 12639 | Return 8\-byte vectors in memory instead of \s-1MMX\s0 registers. This is the |
| 12640 | default on Solaris@tie{}8 and 9 and VxWorks to match the \s-1ABI\s0 of the Sun |
| 12641 | Studio compilers until version 12. Later compiler versions (starting |
| 12642 | with Studio 12 Update@tie{}1) follow the \s-1ABI\s0 used by other x86 targets, which |
| 12643 | is the default on Solaris@tie{}10 and later. \fIOnly\fR use this option if |
| 12644 | you need to remain compatible with existing code produced by those |
| 12645 | previous compiler versions or older versions of \s-1GCC\s0. |
| 12646 | .IP "\fB\-mpc32\fR" 4 |
| 12647 | .IX Item "-mpc32" |
| 12648 | .PD 0 |
| 12649 | .IP "\fB\-mpc64\fR" 4 |
| 12650 | .IX Item "-mpc64" |
| 12651 | .IP "\fB\-mpc80\fR" 4 |
| 12652 | .IX Item "-mpc80" |
| 12653 | .PD |
| 12654 | Set 80387 floating-point precision to 32, 64 or 80 bits. When \fB\-mpc32\fR |
| 12655 | is specified, the significands of results of floating-point operations are |
| 12656 | rounded to 24 bits (single precision); \fB\-mpc64\fR rounds the |
| 12657 | significands of results of floating-point operations to 53 bits (double |
| 12658 | precision) and \fB\-mpc80\fR rounds the significands of results of |
| 12659 | floating-point operations to 64 bits (extended double precision), which is |
| 12660 | the default. When this option is used, floating-point operations in higher |
| 12661 | precisions are not available to the programmer without setting the \s-1FPU\s0 |
| 12662 | control word explicitly. |
| 12663 | .Sp |
| 12664 | Setting the rounding of floating-point operations to less than the default |
| 12665 | 80 bits can speed some programs by 2% or more. Note that some mathematical |
| 12666 | libraries assume that extended-precision (80\-bit) floating-point operations |
| 12667 | are enabled by default; routines in such libraries could suffer significant |
| 12668 | loss of accuracy, typically through so-called \*(L"catastrophic cancellation\*(R", |
| 12669 | when this option is used to set the precision to less than extended precision. |
| 12670 | .IP "\fB\-mstackrealign\fR" 4 |
| 12671 | .IX Item "-mstackrealign" |
| 12672 | Realign the stack at entry. On the Intel x86, the \fB\-mstackrealign\fR |
| 12673 | option will generate an alternate prologue and epilogue that realigns the |
| 12674 | run-time stack if necessary. This supports mixing legacy codes that keep |
| 12675 | a 4\-byte aligned stack with modern codes that keep a 16\-byte stack for |
| 12676 | \&\s-1SSE\s0 compatibility. See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR, |
| 12677 | applicable to individual functions. |
| 12678 | .IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4 |
| 12679 | .IX Item "-mpreferred-stack-boundary=num" |
| 12680 | Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR |
| 12681 | byte boundary. If \fB\-mpreferred\-stack\-boundary\fR is not specified, |
| 12682 | the default is 4 (16 bytes or 128 bits). |
| 12683 | .IP "\fB\-mincoming\-stack\-boundary=\fR\fInum\fR" 4 |
| 12684 | .IX Item "-mincoming-stack-boundary=num" |
| 12685 | Assume the incoming stack is aligned to a 2 raised to \fInum\fR byte |
| 12686 | boundary. If \fB\-mincoming\-stack\-boundary\fR is not specified, |
| 12687 | the one specified by \fB\-mpreferred\-stack\-boundary\fR will be used. |
| 12688 | .Sp |
| 12689 | On Pentium and PentiumPro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values |
| 12690 | should be aligned to an 8\-byte boundary (see \fB\-malign\-double\fR) or |
| 12691 | suffer significant run time performance penalties. On Pentium \s-1III\s0, the |
| 12692 | Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work |
| 12693 | properly if it is not 16\-byte aligned. |
| 12694 | .Sp |
| 12695 | To ensure proper alignment of this values on the stack, the stack boundary |
| 12696 | must be as aligned as that required by any value stored on the stack. |
| 12697 | Further, every function must be generated such that it keeps the stack |
| 12698 | aligned. Thus calling a function compiled with a higher preferred |
| 12699 | stack boundary from a function compiled with a lower preferred stack |
| 12700 | boundary will most likely misalign the stack. It is recommended that |
| 12701 | libraries that use callbacks always use the default setting. |
| 12702 | .Sp |
| 12703 | This extra alignment does consume extra stack space, and generally |
| 12704 | increases code size. Code that is sensitive to stack space usage, such |
| 12705 | as embedded systems and operating system kernels, may want to reduce the |
| 12706 | preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR. |
| 12707 | .IP "\fB\-mmmx\fR" 4 |
| 12708 | .IX Item "-mmmx" |
| 12709 | .PD 0 |
| 12710 | .IP "\fB\-mno\-mmx\fR" 4 |
| 12711 | .IX Item "-mno-mmx" |
| 12712 | .IP "\fB\-msse\fR" 4 |
| 12713 | .IX Item "-msse" |
| 12714 | .IP "\fB\-mno\-sse\fR" 4 |
| 12715 | .IX Item "-mno-sse" |
| 12716 | .IP "\fB\-msse2\fR" 4 |
| 12717 | .IX Item "-msse2" |
| 12718 | .IP "\fB\-mno\-sse2\fR" 4 |
| 12719 | .IX Item "-mno-sse2" |
| 12720 | .IP "\fB\-msse3\fR" 4 |
| 12721 | .IX Item "-msse3" |
| 12722 | .IP "\fB\-mno\-sse3\fR" 4 |
| 12723 | .IX Item "-mno-sse3" |
| 12724 | .IP "\fB\-mssse3\fR" 4 |
| 12725 | .IX Item "-mssse3" |
| 12726 | .IP "\fB\-mno\-ssse3\fR" 4 |
| 12727 | .IX Item "-mno-ssse3" |
| 12728 | .IP "\fB\-msse4.1\fR" 4 |
| 12729 | .IX Item "-msse4.1" |
| 12730 | .IP "\fB\-mno\-sse4.1\fR" 4 |
| 12731 | .IX Item "-mno-sse4.1" |
| 12732 | .IP "\fB\-msse4.2\fR" 4 |
| 12733 | .IX Item "-msse4.2" |
| 12734 | .IP "\fB\-mno\-sse4.2\fR" 4 |
| 12735 | .IX Item "-mno-sse4.2" |
| 12736 | .IP "\fB\-msse4\fR" 4 |
| 12737 | .IX Item "-msse4" |
| 12738 | .IP "\fB\-mno\-sse4\fR" 4 |
| 12739 | .IX Item "-mno-sse4" |
| 12740 | .IP "\fB\-mavx\fR" 4 |
| 12741 | .IX Item "-mavx" |
| 12742 | .IP "\fB\-mno\-avx\fR" 4 |
| 12743 | .IX Item "-mno-avx" |
| 12744 | .IP "\fB\-mavx2\fR" 4 |
| 12745 | .IX Item "-mavx2" |
| 12746 | .IP "\fB\-mno\-avx2\fR" 4 |
| 12747 | .IX Item "-mno-avx2" |
| 12748 | .IP "\fB\-maes\fR" 4 |
| 12749 | .IX Item "-maes" |
| 12750 | .IP "\fB\-mno\-aes\fR" 4 |
| 12751 | .IX Item "-mno-aes" |
| 12752 | .IP "\fB\-mpclmul\fR" 4 |
| 12753 | .IX Item "-mpclmul" |
| 12754 | .IP "\fB\-mno\-pclmul\fR" 4 |
| 12755 | .IX Item "-mno-pclmul" |
| 12756 | .IP "\fB\-mfsgsbase\fR" 4 |
| 12757 | .IX Item "-mfsgsbase" |
| 12758 | .IP "\fB\-mno\-fsgsbase\fR" 4 |
| 12759 | .IX Item "-mno-fsgsbase" |
| 12760 | .IP "\fB\-mrdrnd\fR" 4 |
| 12761 | .IX Item "-mrdrnd" |
| 12762 | .IP "\fB\-mno\-rdrnd\fR" 4 |
| 12763 | .IX Item "-mno-rdrnd" |
| 12764 | .IP "\fB\-mf16c\fR" 4 |
| 12765 | .IX Item "-mf16c" |
| 12766 | .IP "\fB\-mno\-f16c\fR" 4 |
| 12767 | .IX Item "-mno-f16c" |
| 12768 | .IP "\fB\-mfma\fR" 4 |
| 12769 | .IX Item "-mfma" |
| 12770 | .IP "\fB\-mno\-fma\fR" 4 |
| 12771 | .IX Item "-mno-fma" |
| 12772 | .IP "\fB\-msse4a\fR" 4 |
| 12773 | .IX Item "-msse4a" |
| 12774 | .IP "\fB\-mno\-sse4a\fR" 4 |
| 12775 | .IX Item "-mno-sse4a" |
| 12776 | .IP "\fB\-mfma4\fR" 4 |
| 12777 | .IX Item "-mfma4" |
| 12778 | .IP "\fB\-mno\-fma4\fR" 4 |
| 12779 | .IX Item "-mno-fma4" |
| 12780 | .IP "\fB\-mxop\fR" 4 |
| 12781 | .IX Item "-mxop" |
| 12782 | .IP "\fB\-mno\-xop\fR" 4 |
| 12783 | .IX Item "-mno-xop" |
| 12784 | .IP "\fB\-mlwp\fR" 4 |
| 12785 | .IX Item "-mlwp" |
| 12786 | .IP "\fB\-mno\-lwp\fR" 4 |
| 12787 | .IX Item "-mno-lwp" |
| 12788 | .IP "\fB\-m3dnow\fR" 4 |
| 12789 | .IX Item "-m3dnow" |
| 12790 | .IP "\fB\-mno\-3dnow\fR" 4 |
| 12791 | .IX Item "-mno-3dnow" |
| 12792 | .IP "\fB\-mpopcnt\fR" 4 |
| 12793 | .IX Item "-mpopcnt" |
| 12794 | .IP "\fB\-mno\-popcnt\fR" 4 |
| 12795 | .IX Item "-mno-popcnt" |
| 12796 | .IP "\fB\-mabm\fR" 4 |
| 12797 | .IX Item "-mabm" |
| 12798 | .IP "\fB\-mno\-abm\fR" 4 |
| 12799 | .IX Item "-mno-abm" |
| 12800 | .IP "\fB\-mbmi\fR" 4 |
| 12801 | .IX Item "-mbmi" |
| 12802 | .IP "\fB\-mbmi2\fR" 4 |
| 12803 | .IX Item "-mbmi2" |
| 12804 | .IP "\fB\-mno\-bmi\fR" 4 |
| 12805 | .IX Item "-mno-bmi" |
| 12806 | .IP "\fB\-mno\-bmi2\fR" 4 |
| 12807 | .IX Item "-mno-bmi2" |
| 12808 | .IP "\fB\-mlzcnt\fR" 4 |
| 12809 | .IX Item "-mlzcnt" |
| 12810 | .IP "\fB\-mno\-lzcnt\fR" 4 |
| 12811 | .IX Item "-mno-lzcnt" |
| 12812 | .IP "\fB\-mtbm\fR" 4 |
| 12813 | .IX Item "-mtbm" |
| 12814 | .IP "\fB\-mno\-tbm\fR" 4 |
| 12815 | .IX Item "-mno-tbm" |
| 12816 | .PD |
| 12817 | These switches enable or disable the use of instructions in the \s-1MMX\s0, \s-1SSE\s0, |
| 12818 | \&\s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, F16C, |
| 12819 | \&\s-1FMA\s0, \s-1SSE4A\s0, \s-1FMA4\s0, \s-1XOP\s0, \s-1LWP\s0, \s-1ABM\s0, \s-1BMI\s0, \s-1BMI2\s0, \s-1LZCNT\s0 or 3DNow! |
| 12820 | extended instruction sets. |
| 12821 | These extensions are also available as built-in functions: see |
| 12822 | \&\fBX86 Built-in Functions\fR, for details of the functions enabled and |
| 12823 | disabled by these switches. |
| 12824 | .Sp |
| 12825 | To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point |
| 12826 | code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR. |
| 12827 | .Sp |
| 12828 | \&\s-1GCC\s0 depresses SSEx instructions when \fB\-mavx\fR is used. Instead, it |
| 12829 | generates new \s-1AVX\s0 instructions or \s-1AVX\s0 equivalence for all SSEx instructions |
| 12830 | when needed. |
| 12831 | .Sp |
| 12832 | These options will enable \s-1GCC\s0 to use these extended instructions in |
| 12833 | generated code, even without \fB\-mfpmath=sse\fR. Applications that |
| 12834 | perform run-time \s-1CPU\s0 detection must compile separate files for each |
| 12835 | supported architecture, using the appropriate flags. In particular, |
| 12836 | the file containing the \s-1CPU\s0 detection code should be compiled without |
| 12837 | these options. |
| 12838 | .IP "\fB\-mcld\fR" 4 |
| 12839 | .IX Item "-mcld" |
| 12840 | This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`cld\*(C'\fR instruction in the prologue |
| 12841 | of functions that use string instructions. String instructions depend on |
| 12842 | the \s-1DF\s0 flag to select between autoincrement or autodecrement mode. While the |
| 12843 | \&\s-1ABI\s0 specifies the \s-1DF\s0 flag to be cleared on function entry, some operating |
| 12844 | systems violate this specification by not clearing the \s-1DF\s0 flag in their |
| 12845 | exception dispatchers. The exception handler can be invoked with the \s-1DF\s0 flag |
| 12846 | set, which leads to wrong direction mode when string instructions are used. |
| 12847 | This option can be enabled by default on 32\-bit x86 targets by configuring |
| 12848 | \&\s-1GCC\s0 with the \fB\-\-enable\-cld\fR configure option. Generation of \f(CW\*(C`cld\*(C'\fR |
| 12849 | instructions can be suppressed with the \fB\-mno\-cld\fR compiler option |
| 12850 | in this case. |
| 12851 | .IP "\fB\-mvzeroupper\fR" 4 |
| 12852 | .IX Item "-mvzeroupper" |
| 12853 | This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`vzeroupper\*(C'\fR instruction |
| 12854 | before a transfer of control flow out of the function to minimize |
| 12855 | \&\s-1AVX\s0 to \s-1SSE\s0 transition penalty as well as remove unnecessary zeroupper |
| 12856 | intrinsics. |
| 12857 | .IP "\fB\-mprefer\-avx128\fR" 4 |
| 12858 | .IX Item "-mprefer-avx128" |
| 12859 | This option instructs \s-1GCC\s0 to use 128\-bit \s-1AVX\s0 instructions instead of |
| 12860 | 256\-bit \s-1AVX\s0 instructions in the auto-vectorizer. |
| 12861 | .IP "\fB\-mcx16\fR" 4 |
| 12862 | .IX Item "-mcx16" |
| 12863 | This option will enable \s-1GCC\s0 to use \s-1CMPXCHG16B\s0 instruction in generated code. |
| 12864 | \&\s-1CMPXCHG16B\s0 allows for atomic operations on 128\-bit double quadword (or oword) |
| 12865 | data types. This is useful for high resolution counters that could be updated |
| 12866 | by multiple processors (or cores). This instruction is generated as part of |
| 12867 | atomic built-in functions: see \fB_\|_sync Builtins\fR or |
| 12868 | \&\fB_\|_atomic Builtins\fR for details. |
| 12869 | .IP "\fB\-msahf\fR" 4 |
| 12870 | .IX Item "-msahf" |
| 12871 | This option will enable \s-1GCC\s0 to use \s-1SAHF\s0 instruction in generated 64\-bit code. |
| 12872 | Early Intel CPUs with Intel 64 lacked \s-1LAHF\s0 and \s-1SAHF\s0 instructions supported |
| 12873 | by \s-1AMD64\s0 until introduction of Pentium 4 G1 step in December 2005. \s-1LAHF\s0 and |
| 12874 | \&\s-1SAHF\s0 are load and store instructions, respectively, for certain status flags. |
| 12875 | In 64\-bit mode, \s-1SAHF\s0 instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, \f(CW\*(C`drem\*(C'\fR |
| 12876 | or \f(CW\*(C`remainder\*(C'\fR built-in functions: see \fBOther Builtins\fR for details. |
| 12877 | .IP "\fB\-mmovbe\fR" 4 |
| 12878 | .IX Item "-mmovbe" |
| 12879 | This option will enable \s-1GCC\s0 to use movbe instruction to implement |
| 12880 | \&\f(CW\*(C`_\|_builtin_bswap32\*(C'\fR and \f(CW\*(C`_\|_builtin_bswap64\*(C'\fR. |
| 12881 | .IP "\fB\-mcrc32\fR" 4 |
| 12882 | .IX Item "-mcrc32" |
| 12883 | This option will enable built-in functions, \f(CW\*(C`_\|_builtin_ia32_crc32qi\*(C'\fR, |
| 12884 | \&\f(CW\*(C`_\|_builtin_ia32_crc32hi\*(C'\fR. \f(CW\*(C`_\|_builtin_ia32_crc32si\*(C'\fR and |
| 12885 | \&\f(CW\*(C`_\|_builtin_ia32_crc32di\*(C'\fR to generate the crc32 machine instruction. |
| 12886 | .IP "\fB\-mrecip\fR" 4 |
| 12887 | .IX Item "-mrecip" |
| 12888 | This option will enable \s-1GCC\s0 to use \s-1RCPSS\s0 and \s-1RSQRTSS\s0 instructions (and their |
| 12889 | vectorized variants \s-1RCPPS\s0 and \s-1RSQRTPS\s0) with an additional Newton-Raphson step |
| 12890 | to increase precision instead of \s-1DIVSS\s0 and \s-1SQRTSS\s0 (and their vectorized |
| 12891 | variants) for single-precision floating-point arguments. These instructions |
| 12892 | are generated only when \fB\-funsafe\-math\-optimizations\fR is enabled |
| 12893 | together with \fB\-finite\-math\-only\fR and \fB\-fno\-trapping\-math\fR. |
| 12894 | Note that while the throughput of the sequence is higher than the throughput |
| 12895 | of the non-reciprocal instruction, the precision of the sequence can be |
| 12896 | decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994). |
| 12897 | .Sp |
| 12898 | Note that \s-1GCC\s0 implements \f(CW\*(C`1.0f/sqrtf(\f(CIx\f(CW)\*(C'\fR in terms of \s-1RSQRTSS\s0 |
| 12899 | (or \s-1RSQRTPS\s0) already with \fB\-ffast\-math\fR (or the above option |
| 12900 | combination), and doesn't need \fB\-mrecip\fR. |
| 12901 | .Sp |
| 12902 | Also note that \s-1GCC\s0 emits the above sequence with additional Newton-Raphson step |
| 12903 | for vectorized single-float division and vectorized \f(CW\*(C`sqrtf(\f(CIx\f(CW)\*(C'\fR |
| 12904 | already with \fB\-ffast\-math\fR (or the above option combination), and |
| 12905 | doesn't need \fB\-mrecip\fR. |
| 12906 | .IP "\fB\-mrecip=\fR\fIopt\fR" 4 |
| 12907 | .IX Item "-mrecip=opt" |
| 12908 | This option allows to control which reciprocal estimate instructions |
| 12909 | may be used. \fIopt\fR is a comma separated list of options, which may |
| 12910 | be preceded by a \f(CW\*(C`!\*(C'\fR to invert the option: |
| 12911 | \&\f(CW\*(C`all\*(C'\fR: enable all estimate instructions, |
| 12912 | \&\f(CW\*(C`default\*(C'\fR: enable the default instructions, equivalent to \fB\-mrecip\fR, |
| 12913 | \&\f(CW\*(C`none\*(C'\fR: disable all estimate instructions, equivalent to \fB\-mno\-recip\fR, |
| 12914 | \&\f(CW\*(C`div\*(C'\fR: enable the approximation for scalar division, |
| 12915 | \&\f(CW\*(C`vec\-div\*(C'\fR: enable the approximation for vectorized division, |
| 12916 | \&\f(CW\*(C`sqrt\*(C'\fR: enable the approximation for scalar square root, |
| 12917 | \&\f(CW\*(C`vec\-sqrt\*(C'\fR: enable the approximation for vectorized square root. |
| 12918 | .Sp |
| 12919 | So for example, \fB\-mrecip=all,!sqrt\fR would enable |
| 12920 | all of the reciprocal approximations, except for square root. |
| 12921 | .IP "\fB\-mveclibabi=\fR\fItype\fR" 4 |
| 12922 | .IX Item "-mveclibabi=type" |
| 12923 | Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an |
| 12924 | external library. Supported types are \f(CW\*(C`svml\*(C'\fR for the Intel short |
| 12925 | vector math library and \f(CW\*(C`acml\*(C'\fR for the \s-1AMD\s0 math core library style |
| 12926 | of interfacing. \s-1GCC\s0 will currently emit calls to \f(CW\*(C`vmldExp2\*(C'\fR, |
| 12927 | \&\f(CW\*(C`vmldLn2\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldLog102\*(C'\fR, \f(CW\*(C`vmldPow2\*(C'\fR, |
| 12928 | \&\f(CW\*(C`vmldTanh2\*(C'\fR, \f(CW\*(C`vmldTan2\*(C'\fR, \f(CW\*(C`vmldAtan2\*(C'\fR, \f(CW\*(C`vmldAtanh2\*(C'\fR, |
| 12929 | \&\f(CW\*(C`vmldCbrt2\*(C'\fR, \f(CW\*(C`vmldSinh2\*(C'\fR, \f(CW\*(C`vmldSin2\*(C'\fR, \f(CW\*(C`vmldAsinh2\*(C'\fR, |
| 12930 | \&\f(CW\*(C`vmldAsin2\*(C'\fR, \f(CW\*(C`vmldCosh2\*(C'\fR, \f(CW\*(C`vmldCos2\*(C'\fR, \f(CW\*(C`vmldAcosh2\*(C'\fR, |
| 12931 | \&\f(CW\*(C`vmldAcos2\*(C'\fR, \f(CW\*(C`vmlsExp4\*(C'\fR, \f(CW\*(C`vmlsLn4\*(C'\fR, \f(CW\*(C`vmlsLog104\*(C'\fR, |
| 12932 | \&\f(CW\*(C`vmlsLog104\*(C'\fR, \f(CW\*(C`vmlsPow4\*(C'\fR, \f(CW\*(C`vmlsTanh4\*(C'\fR, \f(CW\*(C`vmlsTan4\*(C'\fR, |
| 12933 | \&\f(CW\*(C`vmlsAtan4\*(C'\fR, \f(CW\*(C`vmlsAtanh4\*(C'\fR, \f(CW\*(C`vmlsCbrt4\*(C'\fR, \f(CW\*(C`vmlsSinh4\*(C'\fR, |
| 12934 | \&\f(CW\*(C`vmlsSin4\*(C'\fR, \f(CW\*(C`vmlsAsinh4\*(C'\fR, \f(CW\*(C`vmlsAsin4\*(C'\fR, \f(CW\*(C`vmlsCosh4\*(C'\fR, |
| 12935 | \&\f(CW\*(C`vmlsCos4\*(C'\fR, \f(CW\*(C`vmlsAcosh4\*(C'\fR and \f(CW\*(C`vmlsAcos4\*(C'\fR for corresponding |
| 12936 | function type when \fB\-mveclibabi=svml\fR is used and \f(CW\*(C`_\|_vrd2_sin\*(C'\fR, |
| 12937 | \&\f(CW\*(C`_\|_vrd2_cos\*(C'\fR, \f(CW\*(C`_\|_vrd2_exp\*(C'\fR, \f(CW\*(C`_\|_vrd2_log\*(C'\fR, \f(CW\*(C`_\|_vrd2_log2\*(C'\fR, |
| 12938 | \&\f(CW\*(C`_\|_vrd2_log10\*(C'\fR, \f(CW\*(C`_\|_vrs4_sinf\*(C'\fR, \f(CW\*(C`_\|_vrs4_cosf\*(C'\fR, |
| 12939 | \&\f(CW\*(C`_\|_vrs4_expf\*(C'\fR, \f(CW\*(C`_\|_vrs4_logf\*(C'\fR, \f(CW\*(C`_\|_vrs4_log2f\*(C'\fR, |
| 12940 | \&\f(CW\*(C`_\|_vrs4_log10f\*(C'\fR and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR for corresponding function type |
| 12941 | when \fB\-mveclibabi=acml\fR is used. Both \fB\-ftree\-vectorize\fR and |
| 12942 | \&\fB\-funsafe\-math\-optimizations\fR have to be enabled. A \s-1SVML\s0 or \s-1ACML\s0 \s-1ABI\s0 |
| 12943 | compatible library will have to be specified at link time. |
| 12944 | .IP "\fB\-mabi=\fR\fIname\fR" 4 |
| 12945 | .IX Item "-mabi=name" |
| 12946 | Generate code for the specified calling convention. Permissible values |
| 12947 | are: \fBsysv\fR for the \s-1ABI\s0 used on GNU/Linux and other systems and |
| 12948 | \&\fBms\fR for the Microsoft \s-1ABI\s0. The default is to use the Microsoft |
| 12949 | \&\s-1ABI\s0 when targeting Windows. On all other systems, the default is the |
| 12950 | \&\s-1SYSV\s0 \s-1ABI\s0. You can control this behavior for a specific function by |
| 12951 | using the function attribute \fBms_abi\fR/\fBsysv_abi\fR. |
| 12952 | .IP "\fB\-mtls\-dialect=\fR\fItype\fR" 4 |
| 12953 | .IX Item "-mtls-dialect=type" |
| 12954 | Generate code to access thread-local storage using the \fBgnu\fR or |
| 12955 | \&\fBgnu2\fR conventions. \fBgnu\fR is the conservative default; |
| 12956 | \&\fBgnu2\fR is more efficient, but it may add compile\- and run-time |
| 12957 | requirements that cannot be satisfied on all systems. |
| 12958 | .IP "\fB\-mpush\-args\fR" 4 |
| 12959 | .IX Item "-mpush-args" |
| 12960 | .PD 0 |
| 12961 | .IP "\fB\-mno\-push\-args\fR" 4 |
| 12962 | .IX Item "-mno-push-args" |
| 12963 | .PD |
| 12964 | Use \s-1PUSH\s0 operations to store outgoing parameters. This method is shorter |
| 12965 | and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled |
| 12966 | by default. In some cases disabling it may improve performance because of |
| 12967 | improved scheduling and reduced dependencies. |
| 12968 | .IP "\fB\-maccumulate\-outgoing\-args\fR" 4 |
| 12969 | .IX Item "-maccumulate-outgoing-args" |
| 12970 | If enabled, the maximum amount of space required for outgoing arguments will be |
| 12971 | computed in the function prologue. This is faster on most modern CPUs |
| 12972 | because of reduced dependencies, improved scheduling and reduced stack usage |
| 12973 | when preferred stack boundary is not equal to 2. The drawback is a notable |
| 12974 | increase in code size. This switch implies \fB\-mno\-push\-args\fR. |
| 12975 | .IP "\fB\-mthreads\fR" 4 |
| 12976 | .IX Item "-mthreads" |
| 12977 | Support thread-safe exception handling on \fBMingw32\fR. Code that relies |
| 12978 | on thread-safe exception handling must compile and link all code with the |
| 12979 | \&\fB\-mthreads\fR option. When compiling, \fB\-mthreads\fR defines |
| 12980 | \&\fB\-D_MT\fR; when linking, it links in a special thread helper library |
| 12981 | \&\fB\-lmingwthrd\fR which cleans up per thread exception handling data. |
| 12982 | .IP "\fB\-mno\-align\-stringops\fR" 4 |
| 12983 | .IX Item "-mno-align-stringops" |
| 12984 | Do not align destination of inlined string operations. This switch reduces |
| 12985 | code size and improves performance in case the destination is already aligned, |
| 12986 | but \s-1GCC\s0 doesn't know about it. |
| 12987 | .IP "\fB\-minline\-all\-stringops\fR" 4 |
| 12988 | .IX Item "-minline-all-stringops" |
| 12989 | By default \s-1GCC\s0 inlines string operations only when the destination is |
| 12990 | known to be aligned to least a 4\-byte boundary. |
| 12991 | This enables more inlining, increase code |
| 12992 | size, but may improve performance of code that depends on fast memcpy, strlen |
| 12993 | and memset for short lengths. |
| 12994 | .IP "\fB\-minline\-stringops\-dynamically\fR" 4 |
| 12995 | .IX Item "-minline-stringops-dynamically" |
| 12996 | For string operations of unknown size, use run-time checks with |
| 12997 | inline code for small blocks and a library call for large blocks. |
| 12998 | .IP "\fB\-mstringop\-strategy=\fR\fIalg\fR" 4 |
| 12999 | .IX Item "-mstringop-strategy=alg" |
| 13000 | Overwrite internal decision heuristic about particular algorithm to inline |
| 13001 | string operation with. The allowed values are \f(CW\*(C`rep_byte\*(C'\fR, |
| 13002 | \&\f(CW\*(C`rep_4byte\*(C'\fR, \f(CW\*(C`rep_8byte\*(C'\fR for expanding using i386 \f(CW\*(C`rep\*(C'\fR prefix |
| 13003 | of specified size, \f(CW\*(C`byte_loop\*(C'\fR, \f(CW\*(C`loop\*(C'\fR, \f(CW\*(C`unrolled_loop\*(C'\fR for |
| 13004 | expanding inline loop, \f(CW\*(C`libcall\*(C'\fR for always expanding library call. |
| 13005 | .IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4 |
| 13006 | .IX Item "-momit-leaf-frame-pointer" |
| 13007 | Don't keep the frame pointer in a register for leaf functions. This |
| 13008 | avoids the instructions to save, set up and restore frame pointers and |
| 13009 | makes an extra register available in leaf functions. The option |
| 13010 | \&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions, |
| 13011 | which might make debugging harder. |
| 13012 | .IP "\fB\-mtls\-direct\-seg\-refs\fR" 4 |
| 13013 | .IX Item "-mtls-direct-seg-refs" |
| 13014 | .PD 0 |
| 13015 | .IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4 |
| 13016 | .IX Item "-mno-tls-direct-seg-refs" |
| 13017 | .PD |
| 13018 | Controls whether \s-1TLS\s0 variables may be accessed with offsets from the |
| 13019 | \&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit), |
| 13020 | or whether the thread base pointer must be added. Whether or not this |
| 13021 | is legal depends on the operating system, and whether it maps the |
| 13022 | segment to cover the entire \s-1TLS\s0 area. |
| 13023 | .Sp |
| 13024 | For systems that use \s-1GNU\s0 libc, the default is on. |
| 13025 | .IP "\fB\-msse2avx\fR" 4 |
| 13026 | .IX Item "-msse2avx" |
| 13027 | .PD 0 |
| 13028 | .IP "\fB\-mno\-sse2avx\fR" 4 |
| 13029 | .IX Item "-mno-sse2avx" |
| 13030 | .PD |
| 13031 | Specify that the assembler should encode \s-1SSE\s0 instructions with \s-1VEX\s0 |
| 13032 | prefix. The option \fB\-mavx\fR turns this on by default. |
| 13033 | .IP "\fB\-mfentry\fR" 4 |
| 13034 | .IX Item "-mfentry" |
| 13035 | .PD 0 |
| 13036 | .IP "\fB\-mno\-fentry\fR" 4 |
| 13037 | .IX Item "-mno-fentry" |
| 13038 | .PD |
| 13039 | If profiling is active \fB\-pg\fR put the profiling |
| 13040 | counter call before prologue. |
| 13041 | Note: On x86 architectures the attribute \f(CW\*(C`ms_hook_prologue\*(C'\fR |
| 13042 | isn't possible at the moment for \fB\-mfentry\fR and \fB\-pg\fR. |
| 13043 | .IP "\fB\-m8bit\-idiv\fR" 4 |
| 13044 | .IX Item "-m8bit-idiv" |
| 13045 | .PD 0 |
| 13046 | .IP "\fB\-mno\-8bit\-idiv\fR" 4 |
| 13047 | .IX Item "-mno-8bit-idiv" |
| 13048 | .PD |
| 13049 | On some processors, like Intel Atom, 8\-bit unsigned integer divide is |
| 13050 | much faster than 32\-bit/64\-bit integer divide. This option generates a |
| 13051 | run-time check. If both dividend and divisor are within range of 0 |
| 13052 | to 255, 8\-bit unsigned integer divide is used instead of |
| 13053 | 32\-bit/64\-bit integer divide. |
| 13054 | .IP "\fB\-mavx256\-split\-unaligned\-load\fR" 4 |
| 13055 | .IX Item "-mavx256-split-unaligned-load" |
| 13056 | .PD 0 |
| 13057 | .IP "\fB\-mavx256\-split\-unaligned\-store\fR" 4 |
| 13058 | .IX Item "-mavx256-split-unaligned-store" |
| 13059 | .PD |
| 13060 | Split 32\-byte \s-1AVX\s0 unaligned load and store. |
| 13061 | .PP |
| 13062 | These \fB\-m\fR switches are supported in addition to the above |
| 13063 | on \s-1AMD\s0 x86\-64 processors in 64\-bit environments. |
| 13064 | .IP "\fB\-m32\fR" 4 |
| 13065 | .IX Item "-m32" |
| 13066 | .PD 0 |
| 13067 | .IP "\fB\-m64\fR" 4 |
| 13068 | .IX Item "-m64" |
| 13069 | .IP "\fB\-mx32\fR" 4 |
| 13070 | .IX Item "-mx32" |
| 13071 | .PD |
| 13072 | Generate code for a 32\-bit or 64\-bit environment. |
| 13073 | The \fB\-m32\fR option sets int, long and pointer to 32 bits and |
| 13074 | generates code that runs on any i386 system. |
| 13075 | The \fB\-m64\fR option sets int to 32 bits and long and pointer |
| 13076 | to 64 bits and generates code for \s-1AMD\s0's x86\-64 architecture. |
| 13077 | The \fB\-mx32\fR option sets int, long and pointer to 32 bits and |
| 13078 | generates code for \s-1AMD\s0's x86\-64 architecture. |
| 13079 | For darwin only the \fB\-m64\fR option turns off the \fB\-fno\-pic\fR |
| 13080 | and \fB\-mdynamic\-no\-pic\fR options. |
| 13081 | .IP "\fB\-mno\-red\-zone\fR" 4 |
| 13082 | .IX Item "-mno-red-zone" |
| 13083 | Do not use a so called red zone for x86\-64 code. The red zone is mandated |
| 13084 | by the x86\-64 \s-1ABI\s0, it is a 128\-byte area beyond the location of the |
| 13085 | stack pointer that will not be modified by signal or interrupt handlers |
| 13086 | and therefore can be used for temporary data without adjusting the stack |
| 13087 | pointer. The flag \fB\-mno\-red\-zone\fR disables this red zone. |
| 13088 | .IP "\fB\-mcmodel=small\fR" 4 |
| 13089 | .IX Item "-mcmodel=small" |
| 13090 | Generate code for the small code model: the program and its symbols must |
| 13091 | be linked in the lower 2 \s-1GB\s0 of the address space. Pointers are 64 bits. |
| 13092 | Programs can be statically or dynamically linked. This is the default |
| 13093 | code model. |
| 13094 | .IP "\fB\-mcmodel=kernel\fR" 4 |
| 13095 | .IX Item "-mcmodel=kernel" |
| 13096 | Generate code for the kernel code model. The kernel runs in the |
| 13097 | negative 2 \s-1GB\s0 of the address space. |
| 13098 | This model has to be used for Linux kernel code. |
| 13099 | .IP "\fB\-mcmodel=medium\fR" 4 |
| 13100 | .IX Item "-mcmodel=medium" |
| 13101 | Generate code for the medium model: The program is linked in the lower 2 |
| 13102 | \&\s-1GB\s0 of the address space. Small symbols are also placed there. Symbols |
| 13103 | with sizes larger than \fB\-mlarge\-data\-threshold\fR are put into |
| 13104 | large data or bss sections and can be located above 2GB. Programs can |
| 13105 | be statically or dynamically linked. |
| 13106 | .IP "\fB\-mcmodel=large\fR" 4 |
| 13107 | .IX Item "-mcmodel=large" |
| 13108 | Generate code for the large model: This model makes no assumptions |
| 13109 | about addresses and sizes of sections. |
| 13110 | .PP |
| 13111 | \fIi386 and x86\-64 Windows Options\fR |
| 13112 | .IX Subsection "i386 and x86-64 Windows Options" |
| 13113 | .PP |
| 13114 | These additional options are available for Windows targets: |
| 13115 | .IP "\fB\-mconsole\fR" 4 |
| 13116 | .IX Item "-mconsole" |
| 13117 | This option is available for Cygwin and MinGW targets. It |
| 13118 | specifies that a console application is to be generated, by |
| 13119 | instructing the linker to set the \s-1PE\s0 header subsystem type |
| 13120 | required for console applications. |
| 13121 | This is the default behavior for Cygwin and MinGW targets. |
| 13122 | .IP "\fB\-mdll\fR" 4 |
| 13123 | .IX Item "-mdll" |
| 13124 | This option is available for Cygwin and MinGW targets. It |
| 13125 | specifies that a \s-1DLL\s0 \- a dynamic link library \- is to be |
| 13126 | generated, enabling the selection of the required runtime |
| 13127 | startup object and entry point. |
| 13128 | .IP "\fB\-mnop\-fun\-dllimport\fR" 4 |
| 13129 | .IX Item "-mnop-fun-dllimport" |
| 13130 | This option is available for Cygwin and MinGW targets. It |
| 13131 | specifies that the dllimport attribute should be ignored. |
| 13132 | .IP "\fB\-mthread\fR" 4 |
| 13133 | .IX Item "-mthread" |
| 13134 | This option is available for MinGW targets. It specifies |
| 13135 | that MinGW-specific thread support is to be used. |
| 13136 | .IP "\fB\-municode\fR" 4 |
| 13137 | .IX Item "-municode" |
| 13138 | This option is available for mingw\-w64 targets. It specifies |
| 13139 | that the \s-1UNICODE\s0 macro is getting pre-defined and that the |
| 13140 | unicode capable runtime startup code is chosen. |
| 13141 | .IP "\fB\-mwin32\fR" 4 |
| 13142 | .IX Item "-mwin32" |
| 13143 | This option is available for Cygwin and MinGW targets. It |
| 13144 | specifies that the typical Windows pre-defined macros are to |
| 13145 | be set in the pre-processor, but does not influence the choice |
| 13146 | of runtime library/startup code. |
| 13147 | .IP "\fB\-mwindows\fR" 4 |
| 13148 | .IX Item "-mwindows" |
| 13149 | This option is available for Cygwin and MinGW targets. It |
| 13150 | specifies that a \s-1GUI\s0 application is to be generated by |
| 13151 | instructing the linker to set the \s-1PE\s0 header subsystem type |
| 13152 | appropriately. |
| 13153 | .IP "\fB\-fno\-set\-stack\-executable\fR" 4 |
| 13154 | .IX Item "-fno-set-stack-executable" |
| 13155 | This option is available for MinGW targets. It specifies that |
| 13156 | the executable flag for stack used by nested functions isn't |
| 13157 | set. This is necessary for binaries running in kernel mode of |
| 13158 | Windows, as there the user32 \s-1API\s0, which is used to set executable |
| 13159 | privileges, isn't available. |
| 13160 | .IP "\fB\-mpe\-aligned\-commons\fR" 4 |
| 13161 | .IX Item "-mpe-aligned-commons" |
| 13162 | This option is available for Cygwin and MinGW targets. It |
| 13163 | specifies that the \s-1GNU\s0 extension to the \s-1PE\s0 file format that |
| 13164 | permits the correct alignment of \s-1COMMON\s0 variables should be |
| 13165 | used when generating code. It will be enabled by default if |
| 13166 | \&\s-1GCC\s0 detects that the target assembler found during configuration |
| 13167 | supports the feature. |
| 13168 | .PP |
| 13169 | See also under \fBi386 and x86\-64 Options\fR for standard options. |
| 13170 | .PP |
| 13171 | \fI\s-1IA\-64\s0 Options\fR |
| 13172 | .IX Subsection "IA-64 Options" |
| 13173 | .PP |
| 13174 | These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture. |
| 13175 | .IP "\fB\-mbig\-endian\fR" 4 |
| 13176 | .IX Item "-mbig-endian" |
| 13177 | Generate code for a big-endian target. This is the default for HP-UX. |
| 13178 | .IP "\fB\-mlittle\-endian\fR" 4 |
| 13179 | .IX Item "-mlittle-endian" |
| 13180 | Generate code for a little-endian target. This is the default for \s-1AIX5\s0 |
| 13181 | and GNU/Linux. |
| 13182 | .IP "\fB\-mgnu\-as\fR" 4 |
| 13183 | .IX Item "-mgnu-as" |
| 13184 | .PD 0 |
| 13185 | .IP "\fB\-mno\-gnu\-as\fR" 4 |
| 13186 | .IX Item "-mno-gnu-as" |
| 13187 | .PD |
| 13188 | Generate (or don't) code for the \s-1GNU\s0 assembler. This is the default. |
| 13189 | .IP "\fB\-mgnu\-ld\fR" 4 |
| 13190 | .IX Item "-mgnu-ld" |
| 13191 | .PD 0 |
| 13192 | .IP "\fB\-mno\-gnu\-ld\fR" 4 |
| 13193 | .IX Item "-mno-gnu-ld" |
| 13194 | .PD |
| 13195 | Generate (or don't) code for the \s-1GNU\s0 linker. This is the default. |
| 13196 | .IP "\fB\-mno\-pic\fR" 4 |
| 13197 | .IX Item "-mno-pic" |
| 13198 | Generate code that does not use a global pointer register. The result |
| 13199 | is not position independent code, and violates the \s-1IA\-64\s0 \s-1ABI\s0. |
| 13200 | .IP "\fB\-mvolatile\-asm\-stop\fR" 4 |
| 13201 | .IX Item "-mvolatile-asm-stop" |
| 13202 | .PD 0 |
| 13203 | .IP "\fB\-mno\-volatile\-asm\-stop\fR" 4 |
| 13204 | .IX Item "-mno-volatile-asm-stop" |
| 13205 | .PD |
| 13206 | Generate (or don't) a stop bit immediately before and after volatile asm |
| 13207 | statements. |
| 13208 | .IP "\fB\-mregister\-names\fR" 4 |
| 13209 | .IX Item "-mregister-names" |
| 13210 | .PD 0 |
| 13211 | .IP "\fB\-mno\-register\-names\fR" 4 |
| 13212 | .IX Item "-mno-register-names" |
| 13213 | .PD |
| 13214 | Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for |
| 13215 | the stacked registers. This may make assembler output more readable. |
| 13216 | .IP "\fB\-mno\-sdata\fR" 4 |
| 13217 | .IX Item "-mno-sdata" |
| 13218 | .PD 0 |
| 13219 | .IP "\fB\-msdata\fR" 4 |
| 13220 | .IX Item "-msdata" |
| 13221 | .PD |
| 13222 | Disable (or enable) optimizations that use the small data section. This may |
| 13223 | be useful for working around optimizer bugs. |
| 13224 | .IP "\fB\-mconstant\-gp\fR" 4 |
| 13225 | .IX Item "-mconstant-gp" |
| 13226 | Generate code that uses a single constant global pointer value. This is |
| 13227 | useful when compiling kernel code. |
| 13228 | .IP "\fB\-mauto\-pic\fR" 4 |
| 13229 | .IX Item "-mauto-pic" |
| 13230 | Generate code that is self-relocatable. This implies \fB\-mconstant\-gp\fR. |
| 13231 | This is useful when compiling firmware code. |
| 13232 | .IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4 |
| 13233 | .IX Item "-minline-float-divide-min-latency" |
| 13234 | Generate code for inline divides of floating-point values |
| 13235 | using the minimum latency algorithm. |
| 13236 | .IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4 |
| 13237 | .IX Item "-minline-float-divide-max-throughput" |
| 13238 | Generate code for inline divides of floating-point values |
| 13239 | using the maximum throughput algorithm. |
| 13240 | .IP "\fB\-mno\-inline\-float\-divide\fR" 4 |
| 13241 | .IX Item "-mno-inline-float-divide" |
| 13242 | Do not generate inline code for divides of floating-point values. |
| 13243 | .IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4 |
| 13244 | .IX Item "-minline-int-divide-min-latency" |
| 13245 | Generate code for inline divides of integer values |
| 13246 | using the minimum latency algorithm. |
| 13247 | .IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4 |
| 13248 | .IX Item "-minline-int-divide-max-throughput" |
| 13249 | Generate code for inline divides of integer values |
| 13250 | using the maximum throughput algorithm. |
| 13251 | .IP "\fB\-mno\-inline\-int\-divide\fR" 4 |
| 13252 | .IX Item "-mno-inline-int-divide" |
| 13253 | Do not generate inline code for divides of integer values. |
| 13254 | .IP "\fB\-minline\-sqrt\-min\-latency\fR" 4 |
| 13255 | .IX Item "-minline-sqrt-min-latency" |
| 13256 | Generate code for inline square roots |
| 13257 | using the minimum latency algorithm. |
| 13258 | .IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4 |
| 13259 | .IX Item "-minline-sqrt-max-throughput" |
| 13260 | Generate code for inline square roots |
| 13261 | using the maximum throughput algorithm. |
| 13262 | .IP "\fB\-mno\-inline\-sqrt\fR" 4 |
| 13263 | .IX Item "-mno-inline-sqrt" |
| 13264 | Do not generate inline code for sqrt. |
| 13265 | .IP "\fB\-mfused\-madd\fR" 4 |
| 13266 | .IX Item "-mfused-madd" |
| 13267 | .PD 0 |
| 13268 | .IP "\fB\-mno\-fused\-madd\fR" 4 |
| 13269 | .IX Item "-mno-fused-madd" |
| 13270 | .PD |
| 13271 | Do (don't) generate code that uses the fused multiply/add or multiply/subtract |
| 13272 | instructions. The default is to use these instructions. |
| 13273 | .IP "\fB\-mno\-dwarf2\-asm\fR" 4 |
| 13274 | .IX Item "-mno-dwarf2-asm" |
| 13275 | .PD 0 |
| 13276 | .IP "\fB\-mdwarf2\-asm\fR" 4 |
| 13277 | .IX Item "-mdwarf2-asm" |
| 13278 | .PD |
| 13279 | Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging |
| 13280 | info. This may be useful when not using the \s-1GNU\s0 assembler. |
| 13281 | .IP "\fB\-mearly\-stop\-bits\fR" 4 |
| 13282 | .IX Item "-mearly-stop-bits" |
| 13283 | .PD 0 |
| 13284 | .IP "\fB\-mno\-early\-stop\-bits\fR" 4 |
| 13285 | .IX Item "-mno-early-stop-bits" |
| 13286 | .PD |
| 13287 | Allow stop bits to be placed earlier than immediately preceding the |
| 13288 | instruction that triggered the stop bit. This can improve instruction |
| 13289 | scheduling, but does not always do so. |
| 13290 | .IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 |
| 13291 | .IX Item "-mfixed-range=register-range" |
| 13292 | Generate code treating the given register range as fixed registers. |
| 13293 | A fixed register is one that the register allocator can not use. This is |
| 13294 | useful when compiling kernel code. A register range is specified as |
| 13295 | two registers separated by a dash. Multiple register ranges can be |
| 13296 | specified separated by a comma. |
| 13297 | .IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4 |
| 13298 | .IX Item "-mtls-size=tls-size" |
| 13299 | Specify bit size of immediate \s-1TLS\s0 offsets. Valid values are 14, 22, and |
| 13300 | 64. |
| 13301 | .IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 |
| 13302 | .IX Item "-mtune=cpu-type" |
| 13303 | Tune the instruction scheduling for a particular \s-1CPU\s0, Valid values are |
| 13304 | itanium, itanium1, merced, itanium2, and mckinley. |
| 13305 | .IP "\fB\-milp32\fR" 4 |
| 13306 | .IX Item "-milp32" |
| 13307 | .PD 0 |
| 13308 | .IP "\fB\-mlp64\fR" 4 |
| 13309 | .IX Item "-mlp64" |
| 13310 | .PD |
| 13311 | Generate code for a 32\-bit or 64\-bit environment. |
| 13312 | The 32\-bit environment sets int, long and pointer to 32 bits. |
| 13313 | The 64\-bit environment sets int to 32 bits and long and pointer |
| 13314 | to 64 bits. These are HP-UX specific flags. |
| 13315 | .IP "\fB\-mno\-sched\-br\-data\-spec\fR" 4 |
| 13316 | .IX Item "-mno-sched-br-data-spec" |
| 13317 | .PD 0 |
| 13318 | .IP "\fB\-msched\-br\-data\-spec\fR" 4 |
| 13319 | .IX Item "-msched-br-data-spec" |
| 13320 | .PD |
| 13321 | (Dis/En)able data speculative scheduling before reload. |
| 13322 | This will result in generation of the ld.a instructions and |
| 13323 | the corresponding check instructions (ld.c / chk.a). |
| 13324 | The default is 'disable'. |
| 13325 | .IP "\fB\-msched\-ar\-data\-spec\fR" 4 |
| 13326 | .IX Item "-msched-ar-data-spec" |
| 13327 | .PD 0 |
| 13328 | .IP "\fB\-mno\-sched\-ar\-data\-spec\fR" 4 |
| 13329 | .IX Item "-mno-sched-ar-data-spec" |
| 13330 | .PD |
| 13331 | (En/Dis)able data speculative scheduling after reload. |
| 13332 | This will result in generation of the ld.a instructions and |
| 13333 | the corresponding check instructions (ld.c / chk.a). |
| 13334 | The default is 'enable'. |
| 13335 | .IP "\fB\-mno\-sched\-control\-spec\fR" 4 |
| 13336 | .IX Item "-mno-sched-control-spec" |
| 13337 | .PD 0 |
| 13338 | .IP "\fB\-msched\-control\-spec\fR" 4 |
| 13339 | .IX Item "-msched-control-spec" |
| 13340 | .PD |
| 13341 | (Dis/En)able control speculative scheduling. This feature is |
| 13342 | available only during region scheduling (i.e. before reload). |
| 13343 | This will result in generation of the ld.s instructions and |
| 13344 | the corresponding check instructions chk.s . |
| 13345 | The default is 'disable'. |
| 13346 | .IP "\fB\-msched\-br\-in\-data\-spec\fR" 4 |
| 13347 | .IX Item "-msched-br-in-data-spec" |
| 13348 | .PD 0 |
| 13349 | .IP "\fB\-mno\-sched\-br\-in\-data\-spec\fR" 4 |
| 13350 | .IX Item "-mno-sched-br-in-data-spec" |
| 13351 | .PD |
| 13352 | (En/Dis)able speculative scheduling of the instructions that |
| 13353 | are dependent on the data speculative loads before reload. |
| 13354 | This is effective only with \fB\-msched\-br\-data\-spec\fR enabled. |
| 13355 | The default is 'enable'. |
| 13356 | .IP "\fB\-msched\-ar\-in\-data\-spec\fR" 4 |
| 13357 | .IX Item "-msched-ar-in-data-spec" |
| 13358 | .PD 0 |
| 13359 | .IP "\fB\-mno\-sched\-ar\-in\-data\-spec\fR" 4 |
| 13360 | .IX Item "-mno-sched-ar-in-data-spec" |
| 13361 | .PD |
| 13362 | (En/Dis)able speculative scheduling of the instructions that |
| 13363 | are dependent on the data speculative loads after reload. |
| 13364 | This is effective only with \fB\-msched\-ar\-data\-spec\fR enabled. |
| 13365 | The default is 'enable'. |
| 13366 | .IP "\fB\-msched\-in\-control\-spec\fR" 4 |
| 13367 | .IX Item "-msched-in-control-spec" |
| 13368 | .PD 0 |
| 13369 | .IP "\fB\-mno\-sched\-in\-control\-spec\fR" 4 |
| 13370 | .IX Item "-mno-sched-in-control-spec" |
| 13371 | .PD |
| 13372 | (En/Dis)able speculative scheduling of the instructions that |
| 13373 | are dependent on the control speculative loads. |
| 13374 | This is effective only with \fB\-msched\-control\-spec\fR enabled. |
| 13375 | The default is 'enable'. |
| 13376 | .IP "\fB\-mno\-sched\-prefer\-non\-data\-spec\-insns\fR" 4 |
| 13377 | .IX Item "-mno-sched-prefer-non-data-spec-insns" |
| 13378 | .PD 0 |
| 13379 | .IP "\fB\-msched\-prefer\-non\-data\-spec\-insns\fR" 4 |
| 13380 | .IX Item "-msched-prefer-non-data-spec-insns" |
| 13381 | .PD |
| 13382 | If enabled, data speculative instructions will be chosen for schedule |
| 13383 | only if there are no other choices at the moment. This will make |
| 13384 | the use of the data speculation much more conservative. |
| 13385 | The default is 'disable'. |
| 13386 | .IP "\fB\-mno\-sched\-prefer\-non\-control\-spec\-insns\fR" 4 |
| 13387 | .IX Item "-mno-sched-prefer-non-control-spec-insns" |
| 13388 | .PD 0 |
| 13389 | .IP "\fB\-msched\-prefer\-non\-control\-spec\-insns\fR" 4 |
| 13390 | .IX Item "-msched-prefer-non-control-spec-insns" |
| 13391 | .PD |
| 13392 | If enabled, control speculative instructions will be chosen for schedule |
| 13393 | only if there are no other choices at the moment. This will make |
| 13394 | the use of the control speculation much more conservative. |
| 13395 | The default is 'disable'. |
| 13396 | .IP "\fB\-mno\-sched\-count\-spec\-in\-critical\-path\fR" 4 |
| 13397 | .IX Item "-mno-sched-count-spec-in-critical-path" |
| 13398 | .PD 0 |
| 13399 | .IP "\fB\-msched\-count\-spec\-in\-critical\-path\fR" 4 |
| 13400 | .IX Item "-msched-count-spec-in-critical-path" |
| 13401 | .PD |
| 13402 | If enabled, speculative dependencies will be considered during |
| 13403 | computation of the instructions priorities. This will make the use of the |
| 13404 | speculation a bit more conservative. |
| 13405 | The default is 'disable'. |
| 13406 | .IP "\fB\-msched\-spec\-ldc\fR" 4 |
| 13407 | .IX Item "-msched-spec-ldc" |
| 13408 | Use a simple data speculation check. This option is on by default. |
| 13409 | .IP "\fB\-msched\-control\-spec\-ldc\fR" 4 |
| 13410 | .IX Item "-msched-control-spec-ldc" |
| 13411 | Use a simple check for control speculation. This option is on by default. |
| 13412 | .IP "\fB\-msched\-stop\-bits\-after\-every\-cycle\fR" 4 |
| 13413 | .IX Item "-msched-stop-bits-after-every-cycle" |
| 13414 | Place a stop bit after every cycle when scheduling. This option is on |
| 13415 | by default. |
| 13416 | .IP "\fB\-msched\-fp\-mem\-deps\-zero\-cost\fR" 4 |
| 13417 | .IX Item "-msched-fp-mem-deps-zero-cost" |
| 13418 | Assume that floating-point stores and loads are not likely to cause a conflict |
| 13419 | when placed into the same instruction group. This option is disabled by |
| 13420 | default. |
| 13421 | .IP "\fB\-msel\-sched\-dont\-check\-control\-spec\fR" 4 |
| 13422 | .IX Item "-msel-sched-dont-check-control-spec" |
| 13423 | Generate checks for control speculation in selective scheduling. |
| 13424 | This flag is disabled by default. |
| 13425 | .IP "\fB\-msched\-max\-memory\-insns=\fR\fImax-insns\fR" 4 |
| 13426 | .IX Item "-msched-max-memory-insns=max-insns" |
| 13427 | Limit on the number of memory insns per instruction group, giving lower |
| 13428 | priority to subsequent memory insns attempting to schedule in the same |
| 13429 | instruction group. Frequently useful to prevent cache bank conflicts. |
| 13430 | The default value is 1. |
| 13431 | .IP "\fB\-msched\-max\-memory\-insns\-hard\-limit\fR" 4 |
| 13432 | .IX Item "-msched-max-memory-insns-hard-limit" |
| 13433 | Disallow more than `msched\-max\-memory\-insns' in instruction group. |
| 13434 | Otherwise, limit is `soft' meaning that we would prefer non-memory operations |
| 13435 | when limit is reached but may still schedule memory operations. |
| 13436 | .PP |
| 13437 | \fI\s-1IA\-64/VMS\s0 Options\fR |
| 13438 | .IX Subsection "IA-64/VMS Options" |
| 13439 | .PP |
| 13440 | These \fB\-m\fR options are defined for the \s-1IA\-64/VMS\s0 implementations: |
| 13441 | .IP "\fB\-mvms\-return\-codes\fR" 4 |
| 13442 | .IX Item "-mvms-return-codes" |
| 13443 | Return \s-1VMS\s0 condition codes from main. The default is to return \s-1POSIX\s0 |
| 13444 | style condition (e.g. error) codes. |
| 13445 | .IP "\fB\-mdebug\-main=\fR\fIprefix\fR" 4 |
| 13446 | .IX Item "-mdebug-main=prefix" |
| 13447 | Flag the first routine whose name starts with \fIprefix\fR as the main |
| 13448 | routine for the debugger. |
| 13449 | .IP "\fB\-mmalloc64\fR" 4 |
| 13450 | .IX Item "-mmalloc64" |
| 13451 | Default to 64\-bit memory allocation routines. |
| 13452 | .PP |
| 13453 | \fI\s-1LM32\s0 Options\fR |
| 13454 | .IX Subsection "LM32 Options" |
| 13455 | .PP |
| 13456 | These \fB\-m\fR options are defined for the Lattice Mico32 architecture: |
| 13457 | .IP "\fB\-mbarrel\-shift\-enabled\fR" 4 |
| 13458 | .IX Item "-mbarrel-shift-enabled" |
| 13459 | Enable barrel-shift instructions. |
| 13460 | .IP "\fB\-mdivide\-enabled\fR" 4 |
| 13461 | .IX Item "-mdivide-enabled" |
| 13462 | Enable divide and modulus instructions. |
| 13463 | .IP "\fB\-mmultiply\-enabled\fR" 4 |
| 13464 | .IX Item "-mmultiply-enabled" |
| 13465 | Enable multiply instructions. |
| 13466 | .IP "\fB\-msign\-extend\-enabled\fR" 4 |
| 13467 | .IX Item "-msign-extend-enabled" |
| 13468 | Enable sign extend instructions. |
| 13469 | .IP "\fB\-muser\-enabled\fR" 4 |
| 13470 | .IX Item "-muser-enabled" |
| 13471 | Enable user-defined instructions. |
| 13472 | .PP |
| 13473 | \fIM32C Options\fR |
| 13474 | .IX Subsection "M32C Options" |
| 13475 | .IP "\fB\-mcpu=\fR\fIname\fR" 4 |
| 13476 | .IX Item "-mcpu=name" |
| 13477 | Select the \s-1CPU\s0 for which code is generated. \fIname\fR may be one of |
| 13478 | \&\fBr8c\fR for the R8C/Tiny series, \fBm16c\fR for the M16C (up to |
| 13479 | /60) series, \fBm32cm\fR for the M16C/80 series, or \fBm32c\fR for |
| 13480 | the M32C/80 series. |
| 13481 | .IP "\fB\-msim\fR" 4 |
| 13482 | .IX Item "-msim" |
| 13483 | Specifies that the program will be run on the simulator. This causes |
| 13484 | an alternate runtime library to be linked in which supports, for |
| 13485 | example, file I/O. You must not use this option when generating |
| 13486 | programs that will run on real hardware; you must provide your own |
| 13487 | runtime library for whatever I/O functions are needed. |
| 13488 | .IP "\fB\-memregs=\fR\fInumber\fR" 4 |
| 13489 | .IX Item "-memregs=number" |
| 13490 | Specifies the number of memory-based pseudo-registers \s-1GCC\s0 will use |
| 13491 | during code generation. These pseudo-registers will be used like real |
| 13492 | registers, so there is a tradeoff between \s-1GCC\s0's ability to fit the |
| 13493 | code into available registers, and the performance penalty of using |
| 13494 | memory instead of registers. Note that all modules in a program must |
| 13495 | be compiled with the same value for this option. Because of that, you |
| 13496 | must not use this option with the default runtime libraries gcc |
| 13497 | builds. |
| 13498 | .PP |
| 13499 | \fIM32R/D Options\fR |
| 13500 | .IX Subsection "M32R/D Options" |
| 13501 | .PP |
| 13502 | These \fB\-m\fR options are defined for Renesas M32R/D architectures: |
| 13503 | .IP "\fB\-m32r2\fR" 4 |
| 13504 | .IX Item "-m32r2" |
| 13505 | Generate code for the M32R/2. |
| 13506 | .IP "\fB\-m32rx\fR" 4 |
| 13507 | .IX Item "-m32rx" |
| 13508 | Generate code for the M32R/X. |
| 13509 | .IP "\fB\-m32r\fR" 4 |
| 13510 | .IX Item "-m32r" |
| 13511 | Generate code for the M32R. This is the default. |
| 13512 | .IP "\fB\-mmodel=small\fR" 4 |
| 13513 | .IX Item "-mmodel=small" |
| 13514 | Assume all objects live in the lower 16MB of memory (so that their addresses |
| 13515 | can be loaded with the \f(CW\*(C`ld24\*(C'\fR instruction), and assume all subroutines |
| 13516 | are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. |
| 13517 | This is the default. |
| 13518 | .Sp |
| 13519 | The addressability of a particular object can be set with the |
| 13520 | \&\f(CW\*(C`model\*(C'\fR attribute. |
| 13521 | .IP "\fB\-mmodel=medium\fR" 4 |
| 13522 | .IX Item "-mmodel=medium" |
| 13523 | Assume objects may be anywhere in the 32\-bit address space (the compiler |
| 13524 | will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and |
| 13525 | assume all subroutines are reachable with the \f(CW\*(C`bl\*(C'\fR instruction. |
| 13526 | .IP "\fB\-mmodel=large\fR" 4 |
| 13527 | .IX Item "-mmodel=large" |
| 13528 | Assume objects may be anywhere in the 32\-bit address space (the compiler |
| 13529 | will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and |
| 13530 | assume subroutines may not be reachable with the \f(CW\*(C`bl\*(C'\fR instruction |
| 13531 | (the compiler will generate the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR |
| 13532 | instruction sequence). |
| 13533 | .IP "\fB\-msdata=none\fR" 4 |
| 13534 | .IX Item "-msdata=none" |
| 13535 | Disable use of the small data area. Variables will be put into |
| 13536 | one of \fB.data\fR, \fBbss\fR, or \fB.rodata\fR (unless the |
| 13537 | \&\f(CW\*(C`section\*(C'\fR attribute has been specified). |
| 13538 | This is the default. |
| 13539 | .Sp |
| 13540 | The small data area consists of sections \fB.sdata\fR and \fB.sbss\fR. |
| 13541 | Objects may be explicitly put in the small data area with the |
| 13542 | \&\f(CW\*(C`section\*(C'\fR attribute using one of these sections. |
| 13543 | .IP "\fB\-msdata=sdata\fR" 4 |
| 13544 | .IX Item "-msdata=sdata" |
| 13545 | Put small global and static data in the small data area, but do not |
| 13546 | generate special code to reference them. |
| 13547 | .IP "\fB\-msdata=use\fR" 4 |
| 13548 | .IX Item "-msdata=use" |
| 13549 | Put small global and static data in the small data area, and generate |
| 13550 | special instructions to reference them. |
| 13551 | .IP "\fB\-G\fR \fInum\fR" 4 |
| 13552 | .IX Item "-G num" |
| 13553 | Put global and static objects less than or equal to \fInum\fR bytes |
| 13554 | into the small data or bss sections instead of the normal data or bss |
| 13555 | sections. The default value of \fInum\fR is 8. |
| 13556 | The \fB\-msdata\fR option must be set to one of \fBsdata\fR or \fBuse\fR |
| 13557 | for this option to have any effect. |
| 13558 | .Sp |
| 13559 | All modules should be compiled with the same \fB\-G\fR \fInum\fR value. |
| 13560 | Compiling with different values of \fInum\fR may or may not work; if it |
| 13561 | doesn't the linker will give an error message\-\-\-incorrect code will not be |
| 13562 | generated. |
| 13563 | .IP "\fB\-mdebug\fR" 4 |
| 13564 | .IX Item "-mdebug" |
| 13565 | Makes the M32R specific code in the compiler display some statistics |
| 13566 | that might help in debugging programs. |
| 13567 | .IP "\fB\-malign\-loops\fR" 4 |
| 13568 | .IX Item "-malign-loops" |
| 13569 | Align all loops to a 32\-byte boundary. |
| 13570 | .IP "\fB\-mno\-align\-loops\fR" 4 |
| 13571 | .IX Item "-mno-align-loops" |
| 13572 | Do not enforce a 32\-byte alignment for loops. This is the default. |
| 13573 | .IP "\fB\-missue\-rate=\fR\fInumber\fR" 4 |
| 13574 | .IX Item "-missue-rate=number" |
| 13575 | Issue \fInumber\fR instructions per cycle. \fInumber\fR can only be 1 |
| 13576 | or 2. |
| 13577 | .IP "\fB\-mbranch\-cost=\fR\fInumber\fR" 4 |
| 13578 | .IX Item "-mbranch-cost=number" |
| 13579 | \&\fInumber\fR can only be 1 or 2. If it is 1 then branches will be |
| 13580 | preferred over conditional code, if it is 2, then the opposite will |
| 13581 | apply. |
| 13582 | .IP "\fB\-mflush\-trap=\fR\fInumber\fR" 4 |
| 13583 | .IX Item "-mflush-trap=number" |
| 13584 | Specifies the trap number to use to flush the cache. The default is |
| 13585 | 12. Valid numbers are between 0 and 15 inclusive. |
| 13586 | .IP "\fB\-mno\-flush\-trap\fR" 4 |
| 13587 | .IX Item "-mno-flush-trap" |
| 13588 | Specifies that the cache cannot be flushed by using a trap. |
| 13589 | .IP "\fB\-mflush\-func=\fR\fIname\fR" 4 |
| 13590 | .IX Item "-mflush-func=name" |
| 13591 | Specifies the name of the operating system function to call to flush |
| 13592 | the cache. The default is \fI_flush_cache\fR, but a function call |
| 13593 | will only be used if a trap is not available. |
| 13594 | .IP "\fB\-mno\-flush\-func\fR" 4 |
| 13595 | .IX Item "-mno-flush-func" |
| 13596 | Indicates that there is no \s-1OS\s0 function for flushing the cache. |
| 13597 | .PP |
| 13598 | \fIM680x0 Options\fR |
| 13599 | .IX Subsection "M680x0 Options" |
| 13600 | .PP |
| 13601 | These are the \fB\-m\fR options defined for M680x0 and ColdFire processors. |
| 13602 | The default settings depend on which architecture was selected when |
| 13603 | the compiler was configured; the defaults for the most common choices |
| 13604 | are given below. |
| 13605 | .IP "\fB\-march=\fR\fIarch\fR" 4 |
| 13606 | .IX Item "-march=arch" |
| 13607 | Generate code for a specific M680x0 or ColdFire instruction set |
| 13608 | architecture. Permissible values of \fIarch\fR for M680x0 |
| 13609 | architectures are: \fB68000\fR, \fB68010\fR, \fB68020\fR, |
| 13610 | \&\fB68030\fR, \fB68040\fR, \fB68060\fR and \fBcpu32\fR. ColdFire |
| 13611 | architectures are selected according to Freescale's \s-1ISA\s0 classification |
| 13612 | and the permissible values are: \fBisaa\fR, \fBisaaplus\fR, |
| 13613 | \&\fBisab\fR and \fBisac\fR. |
| 13614 | .Sp |
| 13615 | gcc defines a macro \fB_\|_mcf\fR\fIarch\fR\fB_\|_\fR whenever it is generating |
| 13616 | code for a ColdFire target. The \fIarch\fR in this macro is one of the |
| 13617 | \&\fB\-march\fR arguments given above. |
| 13618 | .Sp |
| 13619 | When used together, \fB\-march\fR and \fB\-mtune\fR select code |
| 13620 | that runs on a family of similar processors but that is optimized |
| 13621 | for a particular microarchitecture. |
| 13622 | .IP "\fB\-mcpu=\fR\fIcpu\fR" 4 |
| 13623 | .IX Item "-mcpu=cpu" |
| 13624 | Generate code for a specific M680x0 or ColdFire processor. |
| 13625 | The M680x0 \fIcpu\fRs are: \fB68000\fR, \fB68010\fR, \fB68020\fR, |
| 13626 | \&\fB68030\fR, \fB68040\fR, \fB68060\fR, \fB68302\fR, \fB68332\fR |
| 13627 | and \fBcpu32\fR. The ColdFire \fIcpu\fRs are given by the table |
| 13628 | below, which also classifies the CPUs into families: |
| 13629 | .RS 4 |
| 13630 | .IP "Family : \fB\-mcpu\fR arguments" 4 |
| 13631 | .IX Item "Family : -mcpu arguments" |
| 13632 | .PD 0 |
| 13633 | .IP "\fB51\fR : \fB51\fR \fB51ac\fR \fB51cn\fR \fB51em\fR \fB51qe\fR" 4 |
| 13634 | .IX Item "51 : 51 51ac 51cn 51em 51qe" |
| 13635 | .IP "\fB5206\fR : \fB5202\fR \fB5204\fR \fB5206\fR" 4 |
| 13636 | .IX Item "5206 : 5202 5204 5206" |
| 13637 | .IP "\fB5206e\fR : \fB5206e\fR" 4 |
| 13638 | .IX Item "5206e : 5206e" |
| 13639 | .IP "\fB5208\fR : \fB5207\fR \fB5208\fR" 4 |
| 13640 | .IX Item "5208 : 5207 5208" |
| 13641 | .IP "\fB5211a\fR : \fB5210a\fR \fB5211a\fR" 4 |
| 13642 | .IX Item "5211a : 5210a 5211a" |
| 13643 | .IP "\fB5213\fR : \fB5211\fR \fB5212\fR \fB5213\fR" 4 |
| 13644 | .IX Item "5213 : 5211 5212 5213" |
| 13645 | .IP "\fB5216\fR : \fB5214\fR \fB5216\fR" 4 |
| 13646 | .IX Item "5216 : 5214 5216" |
| 13647 | .IP "\fB52235\fR : \fB52230\fR \fB52231\fR \fB52232\fR \fB52233\fR \fB52234\fR \fB52235\fR" 4 |
| 13648 | .IX Item "52235 : 52230 52231 52232 52233 52234 52235" |
| 13649 | .IP "\fB5225\fR : \fB5224\fR \fB5225\fR" 4 |
| 13650 | .IX Item "5225 : 5224 5225" |
| 13651 | .IP "\fB52259\fR : \fB52252\fR \fB52254\fR \fB52255\fR \fB52256\fR \fB52258\fR \fB52259\fR" 4 |
| 13652 | .IX Item "52259 : 52252 52254 52255 52256 52258 52259" |
| 13653 | .IP "\fB5235\fR : \fB5232\fR \fB5233\fR \fB5234\fR \fB5235\fR \fB523x\fR" 4 |
| 13654 | .IX Item "5235 : 5232 5233 5234 5235 523x" |
| 13655 | .IP "\fB5249\fR : \fB5249\fR" 4 |
| 13656 | .IX Item "5249 : 5249" |
| 13657 | .IP "\fB5250\fR : \fB5250\fR" 4 |
| 13658 | .IX Item "5250 : 5250" |
| 13659 | .IP "\fB5271\fR : \fB5270\fR \fB5271\fR" 4 |
| 13660 | .IX Item "5271 : 5270 5271" |
| 13661 | .IP "\fB5272\fR : \fB5272\fR" 4 |
| 13662 | .IX Item "5272 : 5272" |
| 13663 | .IP "\fB5275\fR : \fB5274\fR \fB5275\fR" 4 |
| 13664 | .IX Item "5275 : 5274 5275" |
| 13665 | .IP "\fB5282\fR : \fB5280\fR \fB5281\fR \fB5282\fR \fB528x\fR" 4 |
| 13666 | .IX Item "5282 : 5280 5281 5282 528x" |
| 13667 | .IP "\fB53017\fR : \fB53011\fR \fB53012\fR \fB53013\fR \fB53014\fR \fB53015\fR \fB53016\fR \fB53017\fR" 4 |
| 13668 | .IX Item "53017 : 53011 53012 53013 53014 53015 53016 53017" |
| 13669 | .IP "\fB5307\fR : \fB5307\fR" 4 |
| 13670 | .IX Item "5307 : 5307" |
| 13671 | .IP "\fB5329\fR : \fB5327\fR \fB5328\fR \fB5329\fR \fB532x\fR" 4 |
| 13672 | .IX Item "5329 : 5327 5328 5329 532x" |
| 13673 | .IP "\fB5373\fR : \fB5372\fR \fB5373\fR \fB537x\fR" 4 |
| 13674 | .IX Item "5373 : 5372 5373 537x" |
| 13675 | .IP "\fB5407\fR : \fB5407\fR" 4 |
| 13676 | .IX Item "5407 : 5407" |
| 13677 | .IP "\fB5475\fR : \fB5470\fR \fB5471\fR \fB5472\fR \fB5473\fR \fB5474\fR \fB5475\fR \fB547x\fR \fB5480\fR \fB5481\fR \fB5482\fR \fB5483\fR \fB5484\fR \fB5485\fR" 4 |
| 13678 | .IX Item "5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485" |
| 13679 | .RE |
| 13680 | .RS 4 |
| 13681 | .PD |
| 13682 | .Sp |
| 13683 | \&\fB\-mcpu=\fR\fIcpu\fR overrides \fB\-march=\fR\fIarch\fR if |
| 13684 | \&\fIarch\fR is compatible with \fIcpu\fR. Other combinations of |
| 13685 | \&\fB\-mcpu\fR and \fB\-march\fR are rejected. |
| 13686 | .Sp |
| 13687 | gcc defines the macro \fB_\|_mcf_cpu_\fR\fIcpu\fR when ColdFire target |
| 13688 | \&\fIcpu\fR is selected. It also defines \fB_\|_mcf_family_\fR\fIfamily\fR, |
| 13689 | where the value of \fIfamily\fR is given by the table above. |
| 13690 | .RE |
| 13691 | .IP "\fB\-mtune=\fR\fItune\fR" 4 |
| 13692 | .IX Item "-mtune=tune" |
| 13693 | Tune the code for a particular microarchitecture, within the |
| 13694 | constraints set by \fB\-march\fR and \fB\-mcpu\fR. |
| 13695 | The M680x0 microarchitectures are: \fB68000\fR, \fB68010\fR, |
| 13696 | \&\fB68020\fR, \fB68030\fR, \fB68040\fR, \fB68060\fR |
| 13697 | and \fBcpu32\fR. The ColdFire microarchitectures |
| 13698 | are: \fBcfv1\fR, \fBcfv2\fR, \fBcfv3\fR, \fBcfv4\fR and \fBcfv4e\fR. |
| 13699 | .Sp |
| 13700 | You can also use \fB\-mtune=68020\-40\fR for code that needs |
| 13701 | to run relatively well on 68020, 68030 and 68040 targets. |
| 13702 | \&\fB\-mtune=68020\-60\fR is similar but includes 68060 targets |
| 13703 | as well. These two options select the same tuning decisions as |
| 13704 | \&\fB\-m68020\-40\fR and \fB\-m68020\-60\fR respectively. |
| 13705 | .Sp |
| 13706 | gcc defines the macros \fB_\|_mc\fR\fIarch\fR and \fB_\|_mc\fR\fIarch\fR\fB_\|_\fR |
| 13707 | when tuning for 680x0 architecture \fIarch\fR. It also defines |
| 13708 | \&\fBmc\fR\fIarch\fR unless either \fB\-ansi\fR or a non-GNU \fB\-std\fR |
| 13709 | option is used. If gcc is tuning for a range of architectures, |
| 13710 | as selected by \fB\-mtune=68020\-40\fR or \fB\-mtune=68020\-60\fR, |
| 13711 | it defines the macros for every architecture in the range. |
| 13712 | .Sp |
| 13713 | gcc also defines the macro \fB_\|_m\fR\fIuarch\fR\fB_\|_\fR when tuning for |
| 13714 | ColdFire microarchitecture \fIuarch\fR, where \fIuarch\fR is one |
| 13715 | of the arguments given above. |
| 13716 | .IP "\fB\-m68000\fR" 4 |
| 13717 | .IX Item "-m68000" |
| 13718 | .PD 0 |
| 13719 | .IP "\fB\-mc68000\fR" 4 |
| 13720 | .IX Item "-mc68000" |
| 13721 | .PD |
| 13722 | Generate output for a 68000. This is the default |
| 13723 | when the compiler is configured for 68000\-based systems. |
| 13724 | It is equivalent to \fB\-march=68000\fR. |
| 13725 | .Sp |
| 13726 | Use this option for microcontrollers with a 68000 or \s-1EC000\s0 core, |
| 13727 | including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. |
| 13728 | .IP "\fB\-m68010\fR" 4 |
| 13729 | .IX Item "-m68010" |
| 13730 | Generate output for a 68010. This is the default |
| 13731 | when the compiler is configured for 68010\-based systems. |
| 13732 | It is equivalent to \fB\-march=68010\fR. |
| 13733 | .IP "\fB\-m68020\fR" 4 |
| 13734 | .IX Item "-m68020" |
| 13735 | .PD 0 |
| 13736 | .IP "\fB\-mc68020\fR" 4 |
| 13737 | .IX Item "-mc68020" |
| 13738 | .PD |
| 13739 | Generate output for a 68020. This is the default |
| 13740 | when the compiler is configured for 68020\-based systems. |
| 13741 | It is equivalent to \fB\-march=68020\fR. |
| 13742 | .IP "\fB\-m68030\fR" 4 |
| 13743 | .IX Item "-m68030" |
| 13744 | Generate output for a 68030. This is the default when the compiler is |
| 13745 | configured for 68030\-based systems. It is equivalent to |
| 13746 | \&\fB\-march=68030\fR. |
| 13747 | .IP "\fB\-m68040\fR" 4 |
| 13748 | .IX Item "-m68040" |
| 13749 | Generate output for a 68040. This is the default when the compiler is |
| 13750 | configured for 68040\-based systems. It is equivalent to |
| 13751 | \&\fB\-march=68040\fR. |
| 13752 | .Sp |
| 13753 | This option inhibits the use of 68881/68882 instructions that have to be |
| 13754 | emulated by software on the 68040. Use this option if your 68040 does not |
| 13755 | have code to emulate those instructions. |
| 13756 | .IP "\fB\-m68060\fR" 4 |
| 13757 | .IX Item "-m68060" |
| 13758 | Generate output for a 68060. This is the default when the compiler is |
| 13759 | configured for 68060\-based systems. It is equivalent to |
| 13760 | \&\fB\-march=68060\fR. |
| 13761 | .Sp |
| 13762 | This option inhibits the use of 68020 and 68881/68882 instructions that |
| 13763 | have to be emulated by software on the 68060. Use this option if your 68060 |
| 13764 | does not have code to emulate those instructions. |
| 13765 | .IP "\fB\-mcpu32\fR" 4 |
| 13766 | .IX Item "-mcpu32" |
| 13767 | Generate output for a \s-1CPU32\s0. This is the default |
| 13768 | when the compiler is configured for CPU32\-based systems. |
| 13769 | It is equivalent to \fB\-march=cpu32\fR. |
| 13770 | .Sp |
| 13771 | Use this option for microcontrollers with a |
| 13772 | \&\s-1CPU32\s0 or \s-1CPU32+\s0 core, including the 68330, 68331, 68332, 68333, 68334, |
| 13773 | 68336, 68340, 68341, 68349 and 68360. |
| 13774 | .IP "\fB\-m5200\fR" 4 |
| 13775 | .IX Item "-m5200" |
| 13776 | Generate output for a 520X ColdFire \s-1CPU\s0. This is the default |
| 13777 | when the compiler is configured for 520X\-based systems. |
| 13778 | It is equivalent to \fB\-mcpu=5206\fR, and is now deprecated |
| 13779 | in favor of that option. |
| 13780 | .Sp |
| 13781 | Use this option for microcontroller with a 5200 core, including |
| 13782 | the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5206\s0. |
| 13783 | .IP "\fB\-m5206e\fR" 4 |
| 13784 | .IX Item "-m5206e" |
| 13785 | Generate output for a 5206e ColdFire \s-1CPU\s0. The option is now |
| 13786 | deprecated in favor of the equivalent \fB\-mcpu=5206e\fR. |
| 13787 | .IP "\fB\-m528x\fR" 4 |
| 13788 | .IX Item "-m528x" |
| 13789 | Generate output for a member of the ColdFire 528X family. |
| 13790 | The option is now deprecated in favor of the equivalent |
| 13791 | \&\fB\-mcpu=528x\fR. |
| 13792 | .IP "\fB\-m5307\fR" 4 |
| 13793 | .IX Item "-m5307" |
| 13794 | Generate output for a ColdFire 5307 \s-1CPU\s0. The option is now deprecated |
| 13795 | in favor of the equivalent \fB\-mcpu=5307\fR. |
| 13796 | .IP "\fB\-m5407\fR" 4 |
| 13797 | .IX Item "-m5407" |
| 13798 | Generate output for a ColdFire 5407 \s-1CPU\s0. The option is now deprecated |
| 13799 | in favor of the equivalent \fB\-mcpu=5407\fR. |
| 13800 | .IP "\fB\-mcfv4e\fR" 4 |
| 13801 | .IX Item "-mcfv4e" |
| 13802 | Generate output for a ColdFire V4e family \s-1CPU\s0 (e.g. 547x/548x). |
| 13803 | This includes use of hardware floating-point instructions. |
| 13804 | The option is equivalent to \fB\-mcpu=547x\fR, and is now |
| 13805 | deprecated in favor of that option. |
| 13806 | .IP "\fB\-m68020\-40\fR" 4 |
| 13807 | .IX Item "-m68020-40" |
| 13808 | Generate output for a 68040, without using any of the new instructions. |
| 13809 | This results in code that can run relatively efficiently on either a |
| 13810 | 68020/68881 or a 68030 or a 68040. The generated code does use the |
| 13811 | 68881 instructions that are emulated on the 68040. |
| 13812 | .Sp |
| 13813 | The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-40\fR. |
| 13814 | .IP "\fB\-m68020\-60\fR" 4 |
| 13815 | .IX Item "-m68020-60" |
| 13816 | Generate output for a 68060, without using any of the new instructions. |
| 13817 | This results in code that can run relatively efficiently on either a |
| 13818 | 68020/68881 or a 68030 or a 68040. The generated code does use the |
| 13819 | 68881 instructions that are emulated on the 68060. |
| 13820 | .Sp |
| 13821 | The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-60\fR. |
| 13822 | .IP "\fB\-mhard\-float\fR" 4 |
| 13823 | .IX Item "-mhard-float" |
| 13824 | .PD 0 |
| 13825 | .IP "\fB\-m68881\fR" 4 |
| 13826 | .IX Item "-m68881" |
| 13827 | .PD |
| 13828 | Generate floating-point instructions. This is the default for 68020 |
| 13829 | and above, and for ColdFire devices that have an \s-1FPU\s0. It defines the |
| 13830 | macro \fB_\|_HAVE_68881_\|_\fR on M680x0 targets and \fB_\|_mcffpu_\|_\fR |
| 13831 | on ColdFire targets. |
| 13832 | .IP "\fB\-msoft\-float\fR" 4 |
| 13833 | .IX Item "-msoft-float" |
| 13834 | Do not generate floating-point instructions; use library calls instead. |
| 13835 | This is the default for 68000, 68010, and 68832 targets. It is also |
| 13836 | the default for ColdFire devices that have no \s-1FPU\s0. |
| 13837 | .IP "\fB\-mdiv\fR" 4 |
| 13838 | .IX Item "-mdiv" |
| 13839 | .PD 0 |
| 13840 | .IP "\fB\-mno\-div\fR" 4 |
| 13841 | .IX Item "-mno-div" |
| 13842 | .PD |
| 13843 | Generate (do not generate) ColdFire hardware divide and remainder |
| 13844 | instructions. If \fB\-march\fR is used without \fB\-mcpu\fR, |
| 13845 | the default is \*(L"on\*(R" for ColdFire architectures and \*(L"off\*(R" for M680x0 |
| 13846 | architectures. Otherwise, the default is taken from the target \s-1CPU\s0 |
| 13847 | (either the default \s-1CPU\s0, or the one specified by \fB\-mcpu\fR). For |
| 13848 | example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for |
| 13849 | \&\fB\-mcpu=5206e\fR. |
| 13850 | .Sp |
| 13851 | gcc defines the macro \fB_\|_mcfhwdiv_\|_\fR when this option is enabled. |
| 13852 | .IP "\fB\-mshort\fR" 4 |
| 13853 | .IX Item "-mshort" |
| 13854 | Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR. |
| 13855 | Additionally, parameters passed on the stack are also aligned to a |
| 13856 | 16\-bit boundary even on targets whose \s-1API\s0 mandates promotion to 32\-bit. |
| 13857 | .IP "\fB\-mno\-short\fR" 4 |
| 13858 | .IX Item "-mno-short" |
| 13859 | Do not consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide. This is the default. |
| 13860 | .IP "\fB\-mnobitfield\fR" 4 |
| 13861 | .IX Item "-mnobitfield" |
| 13862 | .PD 0 |
| 13863 | .IP "\fB\-mno\-bitfield\fR" 4 |
| 13864 | .IX Item "-mno-bitfield" |
| 13865 | .PD |
| 13866 | Do not use the bit-field instructions. The \fB\-m68000\fR, \fB\-mcpu32\fR |
| 13867 | and \fB\-m5200\fR options imply \fB\-mnobitfield\fR. |
| 13868 | .IP "\fB\-mbitfield\fR" 4 |
| 13869 | .IX Item "-mbitfield" |
| 13870 | Do use the bit-field instructions. The \fB\-m68020\fR option implies |
| 13871 | \&\fB\-mbitfield\fR. This is the default if you use a configuration |
| 13872 | designed for a 68020. |
| 13873 | .IP "\fB\-mrtd\fR" 4 |
| 13874 | .IX Item "-mrtd" |
| 13875 | Use a different function-calling convention, in which functions |
| 13876 | that take a fixed number of arguments return with the \f(CW\*(C`rtd\*(C'\fR |
| 13877 | instruction, which pops their arguments while returning. This |
| 13878 | saves one instruction in the caller since there is no need to pop |
| 13879 | the arguments there. |
| 13880 | .Sp |
| 13881 | This calling convention is incompatible with the one normally |
| 13882 | used on Unix, so you cannot use it if you need to call libraries |
| 13883 | compiled with the Unix compiler. |
| 13884 | .Sp |
| 13885 | Also, you must provide function prototypes for all functions that |
| 13886 | take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR); |
| 13887 | otherwise incorrect code will be generated for calls to those |
| 13888 | functions. |
| 13889 | .Sp |
| 13890 | In addition, seriously incorrect code will result if you call a |
| 13891 | function with too many arguments. (Normally, extra arguments are |
| 13892 | harmlessly ignored.) |
| 13893 | .Sp |
| 13894 | The \f(CW\*(C`rtd\*(C'\fR instruction is supported by the 68010, 68020, 68030, |
| 13895 | 68040, 68060 and \s-1CPU32\s0 processors, but not by the 68000 or 5200. |
| 13896 | .IP "\fB\-mno\-rtd\fR" 4 |
| 13897 | .IX Item "-mno-rtd" |
| 13898 | Do not use the calling conventions selected by \fB\-mrtd\fR. |
| 13899 | This is the default. |
| 13900 | .IP "\fB\-malign\-int\fR" 4 |
| 13901 | .IX Item "-malign-int" |
| 13902 | .PD 0 |
| 13903 | .IP "\fB\-mno\-align\-int\fR" 4 |
| 13904 | .IX Item "-mno-align-int" |
| 13905 | .PD |
| 13906 | Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR, |
| 13907 | \&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit |
| 13908 | boundary (\fB\-malign\-int\fR) or a 16\-bit boundary (\fB\-mno\-align\-int\fR). |
| 13909 | Aligning variables on 32\-bit boundaries produces code that runs somewhat |
| 13910 | faster on processors with 32\-bit busses at the expense of more memory. |
| 13911 | .Sp |
| 13912 | \&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 will |
| 13913 | align structures containing the above types differently than |
| 13914 | most published application binary interface specifications for the m68k. |
| 13915 | .IP "\fB\-mpcrel\fR" 4 |
| 13916 | .IX Item "-mpcrel" |
| 13917 | Use the pc-relative addressing mode of the 68000 directly, instead of |
| 13918 | using a global offset table. At present, this option implies \fB\-fpic\fR, |
| 13919 | allowing at most a 16\-bit offset for pc-relative addressing. \fB\-fPIC\fR is |
| 13920 | not presently supported with \fB\-mpcrel\fR, though this could be supported for |
| 13921 | 68020 and higher processors. |
| 13922 | .IP "\fB\-mno\-strict\-align\fR" 4 |
| 13923 | .IX Item "-mno-strict-align" |
| 13924 | .PD 0 |
| 13925 | .IP "\fB\-mstrict\-align\fR" 4 |
| 13926 | .IX Item "-mstrict-align" |
| 13927 | .PD |
| 13928 | Do not (do) assume that unaligned memory references will be handled by |
| 13929 | the system. |
| 13930 | .IP "\fB\-msep\-data\fR" 4 |
| 13931 | .IX Item "-msep-data" |
| 13932 | Generate code that allows the data segment to be located in a different |
| 13933 | area of memory from the text segment. This allows for execute in place in |
| 13934 | an environment without virtual memory management. This option implies |
| 13935 | \&\fB\-fPIC\fR. |
| 13936 | .IP "\fB\-mno\-sep\-data\fR" 4 |
| 13937 | .IX Item "-mno-sep-data" |
| 13938 | Generate code that assumes that the data segment follows the text segment. |
| 13939 | This is the default. |
| 13940 | .IP "\fB\-mid\-shared\-library\fR" 4 |
| 13941 | .IX Item "-mid-shared-library" |
| 13942 | Generate code that supports shared libraries via the library \s-1ID\s0 method. |
| 13943 | This allows for execute in place and shared libraries in an environment |
| 13944 | without virtual memory management. This option implies \fB\-fPIC\fR. |
| 13945 | .IP "\fB\-mno\-id\-shared\-library\fR" 4 |
| 13946 | .IX Item "-mno-id-shared-library" |
| 13947 | Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used. |
| 13948 | This is the default. |
| 13949 | .IP "\fB\-mshared\-library\-id=n\fR" 4 |
| 13950 | .IX Item "-mshared-library-id=n" |
| 13951 | Specified the identification number of the \s-1ID\s0 based shared library being |
| 13952 | compiled. Specifying a value of 0 will generate more compact code, specifying |
| 13953 | other values will force the allocation of that number to the current |
| 13954 | library but is no more space or time efficient than omitting this option. |
| 13955 | .IP "\fB\-mxgot\fR" 4 |
| 13956 | .IX Item "-mxgot" |
| 13957 | .PD 0 |
| 13958 | .IP "\fB\-mno\-xgot\fR" 4 |
| 13959 | .IX Item "-mno-xgot" |
| 13960 | .PD |
| 13961 | When generating position-independent code for ColdFire, generate code |
| 13962 | that works if the \s-1GOT\s0 has more than 8192 entries. This code is |
| 13963 | larger and slower than code generated without this option. On M680x0 |
| 13964 | processors, this option is not needed; \fB\-fPIC\fR suffices. |
| 13965 | .Sp |
| 13966 | \&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. |
| 13967 | While this is relatively efficient, it only works if the \s-1GOT\s0 |
| 13968 | is smaller than about 64k. Anything larger causes the linker |
| 13969 | to report an error such as: |
| 13970 | .Sp |
| 13971 | .Vb 1 |
| 13972 | \& relocation truncated to fit: R_68K_GOT16O foobar |
| 13973 | .Ve |
| 13974 | .Sp |
| 13975 | If this happens, you should recompile your code with \fB\-mxgot\fR. |
| 13976 | It should then work with very large GOTs. However, code generated with |
| 13977 | \&\fB\-mxgot\fR is less efficient, since it takes 4 instructions to fetch |
| 13978 | the value of a global symbol. |
| 13979 | .Sp |
| 13980 | Note that some linkers, including newer versions of the \s-1GNU\s0 linker, |
| 13981 | can create multiple GOTs and sort \s-1GOT\s0 entries. If you have such a linker, |
| 13982 | you should only need to use \fB\-mxgot\fR when compiling a single |
| 13983 | object file that accesses more than 8192 \s-1GOT\s0 entries. Very few do. |
| 13984 | .Sp |
| 13985 | These options have no effect unless \s-1GCC\s0 is generating |
| 13986 | position-independent code. |
| 13987 | .PP |
| 13988 | \fIMCore Options\fR |
| 13989 | .IX Subsection "MCore Options" |
| 13990 | .PP |
| 13991 | These are the \fB\-m\fR options defined for the Motorola M*Core |
| 13992 | processors. |
| 13993 | .IP "\fB\-mhardlit\fR" 4 |
| 13994 | .IX Item "-mhardlit" |
| 13995 | .PD 0 |
| 13996 | .IP "\fB\-mno\-hardlit\fR" 4 |
| 13997 | .IX Item "-mno-hardlit" |
| 13998 | .PD |
| 13999 | Inline constants into the code stream if it can be done in two |
| 14000 | instructions or less. |
| 14001 | .IP "\fB\-mdiv\fR" 4 |
| 14002 | .IX Item "-mdiv" |
| 14003 | .PD 0 |
| 14004 | .IP "\fB\-mno\-div\fR" 4 |
| 14005 | .IX Item "-mno-div" |
| 14006 | .PD |
| 14007 | Use the divide instruction. (Enabled by default). |
| 14008 | .IP "\fB\-mrelax\-immediate\fR" 4 |
| 14009 | .IX Item "-mrelax-immediate" |
| 14010 | .PD 0 |
| 14011 | .IP "\fB\-mno\-relax\-immediate\fR" 4 |
| 14012 | .IX Item "-mno-relax-immediate" |
| 14013 | .PD |
| 14014 | Allow arbitrary sized immediates in bit operations. |
| 14015 | .IP "\fB\-mwide\-bitfields\fR" 4 |
| 14016 | .IX Item "-mwide-bitfields" |
| 14017 | .PD 0 |
| 14018 | .IP "\fB\-mno\-wide\-bitfields\fR" 4 |
| 14019 | .IX Item "-mno-wide-bitfields" |
| 14020 | .PD |
| 14021 | Always treat bit-fields as int-sized. |
| 14022 | .IP "\fB\-m4byte\-functions\fR" 4 |
| 14023 | .IX Item "-m4byte-functions" |
| 14024 | .PD 0 |
| 14025 | .IP "\fB\-mno\-4byte\-functions\fR" 4 |
| 14026 | .IX Item "-mno-4byte-functions" |
| 14027 | .PD |
| 14028 | Force all functions to be aligned to a 4\-byte boundary. |
| 14029 | .IP "\fB\-mcallgraph\-data\fR" 4 |
| 14030 | .IX Item "-mcallgraph-data" |
| 14031 | .PD 0 |
| 14032 | .IP "\fB\-mno\-callgraph\-data\fR" 4 |
| 14033 | .IX Item "-mno-callgraph-data" |
| 14034 | .PD |
| 14035 | Emit callgraph information. |
| 14036 | .IP "\fB\-mslow\-bytes\fR" 4 |
| 14037 | .IX Item "-mslow-bytes" |
| 14038 | .PD 0 |
| 14039 | .IP "\fB\-mno\-slow\-bytes\fR" 4 |
| 14040 | .IX Item "-mno-slow-bytes" |
| 14041 | .PD |
| 14042 | Prefer word access when reading byte quantities. |
| 14043 | .IP "\fB\-mlittle\-endian\fR" 4 |
| 14044 | .IX Item "-mlittle-endian" |
| 14045 | .PD 0 |
| 14046 | .IP "\fB\-mbig\-endian\fR" 4 |
| 14047 | .IX Item "-mbig-endian" |
| 14048 | .PD |
| 14049 | Generate code for a little-endian target. |
| 14050 | .IP "\fB\-m210\fR" 4 |
| 14051 | .IX Item "-m210" |
| 14052 | .PD 0 |
| 14053 | .IP "\fB\-m340\fR" 4 |
| 14054 | .IX Item "-m340" |
| 14055 | .PD |
| 14056 | Generate code for the 210 processor. |
| 14057 | .IP "\fB\-mno\-lsim\fR" 4 |
| 14058 | .IX Item "-mno-lsim" |
| 14059 | Assume that runtime support has been provided and so omit the |
| 14060 | simulator library (\fIlibsim.a)\fR from the linker command line. |
| 14061 | .IP "\fB\-mstack\-increment=\fR\fIsize\fR" 4 |
| 14062 | .IX Item "-mstack-increment=size" |
| 14063 | Set the maximum amount for a single stack increment operation. Large |
| 14064 | values can increase the speed of programs that contain functions |
| 14065 | that need a large amount of stack space, but they can also trigger a |
| 14066 | segmentation fault if the stack is extended too much. The default |
| 14067 | value is 0x1000. |
| 14068 | .PP |
| 14069 | \fIMeP Options\fR |
| 14070 | .IX Subsection "MeP Options" |
| 14071 | .IP "\fB\-mabsdiff\fR" 4 |
| 14072 | .IX Item "-mabsdiff" |
| 14073 | Enables the \f(CW\*(C`abs\*(C'\fR instruction, which is the absolute difference |
| 14074 | between two registers. |
| 14075 | .IP "\fB\-mall\-opts\fR" 4 |
| 14076 | .IX Item "-mall-opts" |
| 14077 | Enables all the optional instructions \- average, multiply, divide, bit |
| 14078 | operations, leading zero, absolute difference, min/max, clip, and |
| 14079 | saturation. |
| 14080 | .IP "\fB\-maverage\fR" 4 |
| 14081 | .IX Item "-maverage" |
| 14082 | Enables the \f(CW\*(C`ave\*(C'\fR instruction, which computes the average of two |
| 14083 | registers. |
| 14084 | .IP "\fB\-mbased=\fR\fIn\fR" 4 |
| 14085 | .IX Item "-mbased=n" |
| 14086 | Variables of size \fIn\fR bytes or smaller will be placed in the |
| 14087 | \&\f(CW\*(C`.based\*(C'\fR section by default. Based variables use the \f(CW$tp\fR |
| 14088 | register as a base register, and there is a 128\-byte limit to the |
| 14089 | \&\f(CW\*(C`.based\*(C'\fR section. |
| 14090 | .IP "\fB\-mbitops\fR" 4 |
| 14091 | .IX Item "-mbitops" |
| 14092 | Enables the bit operation instructions \- bit test (\f(CW\*(C`btstm\*(C'\fR), set |
| 14093 | (\f(CW\*(C`bsetm\*(C'\fR), clear (\f(CW\*(C`bclrm\*(C'\fR), invert (\f(CW\*(C`bnotm\*(C'\fR), and |
| 14094 | test-and-set (\f(CW\*(C`tas\*(C'\fR). |
| 14095 | .IP "\fB\-mc=\fR\fIname\fR" 4 |
| 14096 | .IX Item "-mc=name" |
| 14097 | Selects which section constant data will be placed in. \fIname\fR may |
| 14098 | be \f(CW\*(C`tiny\*(C'\fR, \f(CW\*(C`near\*(C'\fR, or \f(CW\*(C`far\*(C'\fR. |
| 14099 | .IP "\fB\-mclip\fR" 4 |
| 14100 | .IX Item "-mclip" |
| 14101 | Enables the \f(CW\*(C`clip\*(C'\fR instruction. Note that \f(CW\*(C`\-mclip\*(C'\fR is not |
| 14102 | useful unless you also provide \f(CW\*(C`\-mminmax\*(C'\fR. |
| 14103 | .IP "\fB\-mconfig=\fR\fIname\fR" 4 |
| 14104 | .IX Item "-mconfig=name" |
| 14105 | Selects one of the build-in core configurations. Each MeP chip has |
| 14106 | one or more modules in it; each module has a core \s-1CPU\s0 and a variety of |
| 14107 | coprocessors, optional instructions, and peripherals. The |
| 14108 | \&\f(CW\*(C`MeP\-Integrator\*(C'\fR tool, not part of \s-1GCC\s0, provides these |
| 14109 | configurations through this option; using this option is the same as |
| 14110 | using all the corresponding command-line options. The default |
| 14111 | configuration is \f(CW\*(C`default\*(C'\fR. |
| 14112 | .IP "\fB\-mcop\fR" 4 |
| 14113 | .IX Item "-mcop" |
| 14114 | Enables the coprocessor instructions. By default, this is a 32\-bit |
| 14115 | coprocessor. Note that the coprocessor is normally enabled via the |
| 14116 | \&\f(CW\*(C`\-mconfig=\*(C'\fR option. |
| 14117 | .IP "\fB\-mcop32\fR" 4 |
| 14118 | .IX Item "-mcop32" |
| 14119 | Enables the 32\-bit coprocessor's instructions. |
| 14120 | .IP "\fB\-mcop64\fR" 4 |
| 14121 | .IX Item "-mcop64" |
| 14122 | Enables the 64\-bit coprocessor's instructions. |
| 14123 | .IP "\fB\-mivc2\fR" 4 |
| 14124 | .IX Item "-mivc2" |
| 14125 | Enables \s-1IVC2\s0 scheduling. \s-1IVC2\s0 is a 64\-bit \s-1VLIW\s0 coprocessor. |
| 14126 | .IP "\fB\-mdc\fR" 4 |
| 14127 | .IX Item "-mdc" |
| 14128 | Causes constant variables to be placed in the \f(CW\*(C`.near\*(C'\fR section. |
| 14129 | .IP "\fB\-mdiv\fR" 4 |
| 14130 | .IX Item "-mdiv" |
| 14131 | Enables the \f(CW\*(C`div\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions. |
| 14132 | .IP "\fB\-meb\fR" 4 |
| 14133 | .IX Item "-meb" |
| 14134 | Generate big-endian code. |
| 14135 | .IP "\fB\-mel\fR" 4 |
| 14136 | .IX Item "-mel" |
| 14137 | Generate little-endian code. |
| 14138 | .IP "\fB\-mio\-volatile\fR" 4 |
| 14139 | .IX Item "-mio-volatile" |
| 14140 | Tells the compiler that any variable marked with the \f(CW\*(C`io\*(C'\fR |
| 14141 | attribute is to be considered volatile. |
| 14142 | .IP "\fB\-ml\fR" 4 |
| 14143 | .IX Item "-ml" |
| 14144 | Causes variables to be assigned to the \f(CW\*(C`.far\*(C'\fR section by default. |
| 14145 | .IP "\fB\-mleadz\fR" 4 |
| 14146 | .IX Item "-mleadz" |
| 14147 | Enables the \f(CW\*(C`leadz\*(C'\fR (leading zero) instruction. |
| 14148 | .IP "\fB\-mm\fR" 4 |
| 14149 | .IX Item "-mm" |
| 14150 | Causes variables to be assigned to the \f(CW\*(C`.near\*(C'\fR section by default. |
| 14151 | .IP "\fB\-mminmax\fR" 4 |
| 14152 | .IX Item "-mminmax" |
| 14153 | Enables the \f(CW\*(C`min\*(C'\fR and \f(CW\*(C`max\*(C'\fR instructions. |
| 14154 | .IP "\fB\-mmult\fR" 4 |
| 14155 | .IX Item "-mmult" |
| 14156 | Enables the multiplication and multiply-accumulate instructions. |
| 14157 | .IP "\fB\-mno\-opts\fR" 4 |
| 14158 | .IX Item "-mno-opts" |
| 14159 | Disables all the optional instructions enabled by \f(CW\*(C`\-mall\-opts\*(C'\fR. |
| 14160 | .IP "\fB\-mrepeat\fR" 4 |
| 14161 | .IX Item "-mrepeat" |
| 14162 | Enables the \f(CW\*(C`repeat\*(C'\fR and \f(CW\*(C`erepeat\*(C'\fR instructions, used for |
| 14163 | low-overhead looping. |
| 14164 | .IP "\fB\-ms\fR" 4 |
| 14165 | .IX Item "-ms" |
| 14166 | Causes all variables to default to the \f(CW\*(C`.tiny\*(C'\fR section. Note |
| 14167 | that there is a 65536\-byte limit to this section. Accesses to these |
| 14168 | variables use the \f(CW%gp\fR base register. |
| 14169 | .IP "\fB\-msatur\fR" 4 |
| 14170 | .IX Item "-msatur" |
| 14171 | Enables the saturation instructions. Note that the compiler does not |
| 14172 | currently generate these itself, but this option is included for |
| 14173 | compatibility with other tools, like \f(CW\*(C`as\*(C'\fR. |
| 14174 | .IP "\fB\-msdram\fR" 4 |
| 14175 | .IX Item "-msdram" |
| 14176 | Link the SDRAM-based runtime instead of the default ROM-based runtime. |
| 14177 | .IP "\fB\-msim\fR" 4 |
| 14178 | .IX Item "-msim" |
| 14179 | Link the simulator runtime libraries. |
| 14180 | .IP "\fB\-msimnovec\fR" 4 |
| 14181 | .IX Item "-msimnovec" |
| 14182 | Link the simulator runtime libraries, excluding built-in support |
| 14183 | for reset and exception vectors and tables. |
| 14184 | .IP "\fB\-mtf\fR" 4 |
| 14185 | .IX Item "-mtf" |
| 14186 | Causes all functions to default to the \f(CW\*(C`.far\*(C'\fR section. Without |
| 14187 | this option, functions default to the \f(CW\*(C`.near\*(C'\fR section. |
| 14188 | .IP "\fB\-mtiny=\fR\fIn\fR" 4 |
| 14189 | .IX Item "-mtiny=n" |
| 14190 | Variables that are \fIn\fR bytes or smaller will be allocated to the |
| 14191 | \&\f(CW\*(C`.tiny\*(C'\fR section. These variables use the \f(CW$gp\fR base |
| 14192 | register. The default for this option is 4, but note that there's a |
| 14193 | 65536\-byte limit to the \f(CW\*(C`.tiny\*(C'\fR section. |
| 14194 | .PP |
| 14195 | \fIMicroBlaze Options\fR |
| 14196 | .IX Subsection "MicroBlaze Options" |
| 14197 | .IP "\fB\-msoft\-float\fR" 4 |
| 14198 | .IX Item "-msoft-float" |
| 14199 | Use software emulation for floating point (default). |
| 14200 | .IP "\fB\-mhard\-float\fR" 4 |
| 14201 | .IX Item "-mhard-float" |
| 14202 | Use hardware floating-point instructions. |
| 14203 | .IP "\fB\-mmemcpy\fR" 4 |
| 14204 | .IX Item "-mmemcpy" |
| 14205 | Do not optimize block moves, use \f(CW\*(C`memcpy\*(C'\fR. |
| 14206 | .IP "\fB\-mno\-clearbss\fR" 4 |
| 14207 | .IX Item "-mno-clearbss" |
| 14208 | This option is deprecated. Use \fB\-fno\-zero\-initialized\-in\-bss\fR instead. |
| 14209 | .IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4 |
| 14210 | .IX Item "-mcpu=cpu-type" |
| 14211 | Use features of and schedule code for given \s-1CPU\s0. |
| 14212 | Supported values are in the format \fBv\fR\fIX\fR\fB.\fR\fI\s-1YY\s0\fR\fB.\fR\fIZ\fR, |
| 14213 | where \fIX\fR is a major version, \fI\s-1YY\s0\fR is the minor version, and |
| 14214 | \&\fIZ\fR is compatibility code. Example values are \fBv3.00.a\fR, |
| 14215 | \&\fBv4.00.b\fR, \fBv5.00.a\fR, \fBv5.00.b\fR, \fBv5.00.b\fR, \fBv6.00.a\fR. |
| 14216 | .IP "\fB\-mxl\-soft\-mul\fR" 4 |
| 14217 | .IX Item "-mxl-soft-mul" |
| 14218 | Use software multiply emulation (default). |
| 14219 | .IP "\fB\-mxl\-soft\-div\fR" 4 |
| 14220 | .IX Item "-mxl-soft-div" |
| 14221 | Use software emulation for divides (default). |
| 14222 | .IP "\fB\-mxl\-barrel\-shift\fR" 4 |
| 14223 | .IX Item "-mxl-barrel-shift" |
| 14224 | Use the hardware barrel shifter. |
| 14225 | .IP "\fB\-mxl\-pattern\-compare\fR" 4 |
| 14226 | .IX Item "-mxl-pattern-compare" |
| 14227 | Use pattern compare instructions. |
| 14228 | .IP "\fB\-msmall\-divides\fR" 4 |
| 14229 | .IX Item "-msmall-divides" |
| 14230 | Use table lookup optimization for small signed integer divisions. |
| 14231 | .IP "\fB\-mxl\-stack\-check\fR" 4 |
| 14232 | .IX Item "-mxl-stack-check" |
| 14233 | This option is deprecated. Use \-fstack\-check instead. |
| 14234 | .IP "\fB\-mxl\-gp\-opt\fR" 4 |
| 14235 | .IX Item "-mxl-gp-opt" |
| 14236 | Use \s-1GP\s0 relative sdata/sbss sections. |
| 14237 | .IP "\fB\-mxl\-multiply\-high\fR" 4 |
| 14238 | .IX Item "-mxl-multiply-high" |
| 14239 | Use multiply high instructions for high part of 32x32 multiply. |
| 14240 | .IP "\fB\-mxl\-float\-convert\fR" 4 |
| 14241 | .IX Item "-mxl-float-convert" |
| 14242 | Use hardware floating-point conversion instructions. |
| 14243 | .IP "\fB\-mxl\-float\-sqrt\fR" 4 |
| 14244 | .IX Item "-mxl-float-sqrt" |
| 14245 | Use hardware floating-point square root instruction. |
| 14246 | .IP "\fB\-mxl\-mode\-\fR\fIapp-model\fR" 4 |
| 14247 | .IX Item "-mxl-mode-app-model" |
| 14248 | Select application model \fIapp-model\fR. Valid models are |
| 14249 | .RS 4 |
| 14250 | .IP "\fBexecutable\fR" 4 |
| 14251 | .IX Item "executable" |
| 14252 | normal executable (default), uses startup code \fIcrt0.o\fR. |
| 14253 | .IP "\fBxmdstub\fR" 4 |
| 14254 | .IX Item "xmdstub" |
| 14255 | for use with Xilinx Microprocessor Debugger (\s-1XMD\s0) based |
| 14256 | software intrusive debug agent called xmdstub. This uses startup file |
| 14257 | \&\fIcrt1.o\fR and sets the start address of the program to be 0x800. |
| 14258 | .IP "\fBbootstrap\fR" 4 |
| 14259 | .IX Item "bootstrap" |
| 14260 | for applications that are loaded using a bootloader. |
| 14261 | This model uses startup file \fIcrt2.o\fR which does not contain a processor |
| 14262 | reset vector handler. This is suitable for transferring control on a |
| 14263 | processor reset to the bootloader rather than the application. |
| 14264 | .IP "\fBnovectors\fR" 4 |
| 14265 | .IX Item "novectors" |
| 14266 | for applications that do not require any of the |
| 14267 | MicroBlaze vectors. This option may be useful for applications running |
| 14268 | within a monitoring application. This model uses \fIcrt3.o\fR as a startup file. |
| 14269 | .RE |
| 14270 | .RS 4 |
| 14271 | .Sp |
| 14272 | Option \fB\-xl\-mode\-\fR\fIapp-model\fR is a deprecated alias for |
| 14273 | \&\fB\-mxl\-mode\-\fR\fIapp-model\fR. |
| 14274 | .RE |
| 14275 | .PP |
| 14276 | \fI\s-1MIPS\s0 Options\fR |
| 14277 | .IX Subsection "MIPS Options" |
| 14278 | .IP "\fB\-EB\fR" 4 |
| 14279 | .IX Item "-EB" |
| 14280 | Generate big-endian code. |
| 14281 | .IP "\fB\-EL\fR" 4 |
| 14282 | .IX Item "-EL" |
| 14283 | Generate little-endian code. This is the default for \fBmips*el\-*\-*\fR |
| 14284 | configurations. |
| 14285 | .IP "\fB\-march=\fR\fIarch\fR" 4 |
| 14286 | .IX Item "-march=arch" |
| 14287 | Generate code that will run on \fIarch\fR, which can be the name of a |
| 14288 | generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor. |
| 14289 | The \s-1ISA\s0 names are: |
| 14290 | \&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR, |
| 14291 | \&\fBmips32\fR, \fBmips32r2\fR, \fBmips64\fR and \fBmips64r2\fR. |
| 14292 | The processor names are: |
| 14293 | \&\fB4kc\fR, \fB4km\fR, \fB4kp\fR, \fB4ksc\fR, |
| 14294 | \&\fB4kec\fR, \fB4kem\fR, \fB4kep\fR, \fB4ksd\fR, |
| 14295 | \&\fB5kc\fR, \fB5kf\fR, |
| 14296 | \&\fB20kc\fR, |
| 14297 | \&\fB24kc\fR, \fB24kf2_1\fR, \fB24kf1_1\fR, |
| 14298 | \&\fB24kec\fR, \fB24kef2_1\fR, \fB24kef1_1\fR, |
| 14299 | \&\fB34kc\fR, \fB34kf2_1\fR, \fB34kf1_1\fR, |
| 14300 | \&\fB74kc\fR, \fB74kf2_1\fR, \fB74kf1_1\fR, \fB74kf3_2\fR, |
| 14301 | \&\fB1004kc\fR, \fB1004kf2_1\fR, \fB1004kf1_1\fR, |
| 14302 | \&\fBloongson2e\fR, \fBloongson2f\fR, \fBloongson3a\fR, |
| 14303 | \&\fBm4k\fR, |
| 14304 | \&\fBocteon\fR, \fBocteon+\fR, \fBocteon2\fR, |
| 14305 | \&\fBorion\fR, |
| 14306 | \&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR, |
| 14307 | \&\fBr4600\fR, \fBr4650\fR, \fBr6000\fR, \fBr8000\fR, |
| 14308 | \&\fBrm7000\fR, \fBrm9000\fR, |
| 14309 | \&\fBr10000\fR, \fBr12000\fR, \fBr14000\fR, \fBr16000\fR, |
| 14310 | \&\fBsb1\fR, |
| 14311 | \&\fBsr71000\fR, |
| 14312 | \&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4130\fR, \fBvr4300\fR, |
| 14313 | \&\fBvr5000\fR, \fBvr5400\fR, \fBvr5500\fR |
| 14314 | and \fBxlr\fR. |
| 14315 | The special value \fBfrom-abi\fR selects the |
| 14316 | most compatible architecture for the selected \s-1ABI\s0 (that is, |
| 14317 | \&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs). |
| 14318 | .Sp |
| 14319 | Native Linux/GNU and \s-1IRIX\s0 toolchains also support the value \fBnative\fR, |
| 14320 | which selects the best architecture option for the host processor. |
| 14321 | \&\fB\-march=native\fR has no effect if \s-1GCC\s0 does not recognize |
| 14322 | the processor. |
| 14323 | .Sp |
| 14324 | In processor names, a final \fB000\fR can be abbreviated as \fBk\fR |
| 14325 | (for example, \fB\-march=r2k\fR). Prefixes are optional, and |
| 14326 | \&\fBvr\fR may be written \fBr\fR. |
| 14327 | .Sp |
| 14328 | Names of the form \fIn\fR\fBf2_1\fR refer to processors with |
| 14329 | FPUs clocked at half the rate of the core, names of the form |
| 14330 | \&\fIn\fR\fBf1_1\fR refer to processors with FPUs clocked at the same |
| 14331 | rate as the core, and names of the form \fIn\fR\fBf3_2\fR refer to |
| 14332 | processors with FPUs clocked a ratio of 3:2 with respect to the core. |
| 14333 | For compatibility reasons, \fIn\fR\fBf\fR is accepted as a synonym |
| 14334 | for \fIn\fR\fBf2_1\fR while \fIn\fR\fBx\fR and \fIb\fR\fBfx\fR are |
| 14335 | accepted as synonyms for \fIn\fR\fBf1_1\fR. |
| 14336 | .Sp |
| 14337 | \&\s-1GCC\s0 defines two macros based on the value of this option. The first |
| 14338 | is \fB_MIPS_ARCH\fR, which gives the name of target architecture, as |
| 14339 | a string. The second has the form \fB_MIPS_ARCH_\fR\fIfoo\fR, |
| 14340 | where \fIfoo\fR is the capitalized value of \fB_MIPS_ARCH\fR. |
| 14341 | For example, \fB\-march=r2000\fR will set \fB_MIPS_ARCH\fR |
| 14342 | to \fB\*(L"r2000\*(R"\fR and define the macro \fB_MIPS_ARCH_R2000\fR. |
| 14343 | .Sp |
| 14344 | Note that the \fB_MIPS_ARCH\fR macro uses the processor names given |
| 14345 | above. In other words, it will have the full prefix and will not |
| 14346 | abbreviate \fB000\fR as \fBk\fR. In the case of \fBfrom-abi\fR, |
| 14347 | the macro names the resolved architecture (either \fB\*(L"mips1\*(R"\fR or |
| 14348 | \&\fB\*(L"mips3\*(R"\fR). It names the default architecture when no |
| 14349 | \&\fB\-march\fR option is given. |
| 14350 | .IP "\fB\-mtune=\fR\fIarch\fR" 4 |
| 14351 | .IX Item "-mtune=arch" |
| 14352 | Optimize for \fIarch\fR. Among other things, this option controls |
| 14353 | the way instructions are scheduled, and the perceived cost of arithmetic |
| 14354 | operations. The list of \fIarch\fR values is the same as for |
| 14355 | \&\fB\-march\fR. |
| 14356 | .Sp |
| 14357 | When this option is not used, \s-1GCC\s0 will optimize for the processor |
| 14358 | specified by \fB\-march\fR. By using \fB\-march\fR and |
| 14359 | \&\fB\-mtune\fR together, it is possible to generate code that will |
| 14360 | run on a family of processors, but optimize the code for one |
| 14361 | particular member of that family. |
| 14362 | .Sp |
| 14363 | \&\fB\-mtune\fR defines the macros \fB_MIPS_TUNE\fR and |
| 14364 | \&\fB_MIPS_TUNE_\fR\fIfoo\fR, which work in the same way as the |
| 14365 | \&\fB\-march\fR ones described above. |
| 14366 | .IP "\fB\-mips1\fR" 4 |
| 14367 | .IX Item "-mips1" |
| 14368 | Equivalent to \fB\-march=mips1\fR. |
| 14369 | .IP "\fB\-mips2\fR" 4 |
| 14370 | .IX Item "-mips2" |
| 14371 | Equivalent to \fB\-march=mips2\fR. |
| 14372 | .IP "\fB\-mips3\fR" 4 |
| 14373 | .IX Item "-mips3" |
| 14374 | Equivalent to \fB\-march=mips3\fR. |
| 14375 | .IP "\fB\-mips4\fR" 4 |
| 14376 | .IX Item "-mips4" |
| 14377 | Equivalent to \fB\-march=mips4\fR. |
| 14378 | .IP "\fB\-mips32\fR" 4 |
| 14379 | .IX Item "-mips32" |
| 14380 | Equivalent to \fB\-march=mips32\fR. |
| 14381 | .IP "\fB\-mips32r2\fR" 4 |
| 14382 | .IX Item "-mips32r2" |
| 14383 | Equivalent to \fB\-march=mips32r2\fR. |
| 14384 | .IP "\fB\-mips64\fR" 4 |
| 14385 | .IX Item "-mips64" |
| 14386 | Equivalent to \fB\-march=mips64\fR. |
| 14387 | .IP "\fB\-mips64r2\fR" 4 |
| 14388 | .IX Item "-mips64r2" |
| 14389 | Equivalent to \fB\-march=mips64r2\fR. |
| 14390 | .IP "\fB\-mips16\fR" 4 |
| 14391 | .IX Item "-mips16" |
| 14392 | .PD 0 |
| 14393 | .IP "\fB\-mno\-mips16\fR" 4 |
| 14394 | .IX Item "-mno-mips16" |
| 14395 | .PD |
| 14396 | Generate (do not generate) \s-1MIPS16\s0 code. If \s-1GCC\s0 is targetting a |
| 14397 | \&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it will make use of the MIPS16e \s-1ASE\s0. |
| 14398 | .Sp |
| 14399 | \&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis |
| 14400 | by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes. |
| 14401 | .IP "\fB\-mflip\-mips16\fR" 4 |
| 14402 | .IX Item "-mflip-mips16" |
| 14403 | Generate \s-1MIPS16\s0 code on alternating functions. This option is provided |
| 14404 | for regression testing of mixed MIPS16/non\-MIPS16 code generation, and is |
| 14405 | not intended for ordinary use in compiling user code. |
| 14406 | .IP "\fB\-minterlink\-mips16\fR" 4 |
| 14407 | .IX Item "-minterlink-mips16" |
| 14408 | .PD 0 |
| 14409 | .IP "\fB\-mno\-interlink\-mips16\fR" 4 |
| 14410 | .IX Item "-mno-interlink-mips16" |
| 14411 | .PD |
| 14412 | Require (do not require) that non\-MIPS16 code be link-compatible with |
| 14413 | \&\s-1MIPS16\s0 code. |
| 14414 | .Sp |
| 14415 | For example, non\-MIPS16 code cannot jump directly to \s-1MIPS16\s0 code; |
| 14416 | it must either use a call or an indirect jump. \fB\-minterlink\-mips16\fR |
| 14417 | therefore disables direct jumps unless \s-1GCC\s0 knows that the target of the |
| 14418 | jump is not \s-1MIPS16\s0. |
| 14419 | .IP "\fB\-mabi=32\fR" 4 |
| 14420 | .IX Item "-mabi=32" |
| 14421 | .PD 0 |
| 14422 | .IP "\fB\-mabi=o64\fR" 4 |
| 14423 | .IX Item "-mabi=o64" |
| 14424 | .IP "\fB\-mabi=n32\fR" 4 |
| 14425 | .IX Item "-mabi=n32" |
| 14426 | .IP "\fB\-mabi=64\fR" 4 |
| 14427 | .IX Item "-mabi=64" |
| 14428 | .IP "\fB\-mabi=eabi\fR" 4 |
| 14429 | .IX Item "-mabi=eabi" |
| 14430 | .PD |
| 14431 | Generate code for the given \s-1ABI\s0. |
| 14432 | .Sp |
| 14433 | Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant. \s-1GCC\s0 normally |
| 14434 | generates 64\-bit code when you select a 64\-bit architecture, but you |
| 14435 | can use \fB\-mgp32\fR to get 32\-bit code instead. |
| 14436 | .Sp |
| 14437 | For information about the O64 \s-1ABI\s0, see |
| 14438 | <\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>. |
| 14439 | .Sp |
| 14440 | \&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers |
| 14441 | are 64 rather than 32 bits wide. You can select this combination with |
| 14442 | \&\fB\-mabi=32\fR \fB\-mfp64\fR. This \s-1ABI\s0 relies on the \fBmthc1\fR |
| 14443 | and \fBmfhc1\fR instructions and is therefore only supported for |
| 14444 | \&\s-1MIPS32R2\s0 processors. |
| 14445 | .Sp |
| 14446 | The register assignments for arguments and return values remain the |
| 14447 | same, but each scalar value is passed in a single 64\-bit register |
| 14448 | rather than a pair of 32\-bit registers. For example, scalar |
| 14449 | floating-point values are returned in \fB\f(CB$f0\fB\fR only, not a |
| 14450 | \&\fB\f(CB$f0\fB\fR/\fB\f(CB$f1\fB\fR pair. The set of call-saved registers also |
| 14451 | remains the same, but all 64 bits are saved. |
| 14452 | .IP "\fB\-mabicalls\fR" 4 |
| 14453 | .IX Item "-mabicalls" |
| 14454 | .PD 0 |
| 14455 | .IP "\fB\-mno\-abicalls\fR" 4 |
| 14456 | .IX Item "-mno-abicalls" |
| 14457 | .PD |
| 14458 | Generate (do not generate) code that is suitable for SVR4\-style |
| 14459 | dynamic objects. \fB\-mabicalls\fR is the default for SVR4\-based |
| 14460 | systems. |
| 14461 | .IP "\fB\-mshared\fR" 4 |
| 14462 | .IX Item "-mshared" |
| 14463 | .PD 0 |
| 14464 | .IP "\fB\-mno\-shared\fR" 4 |
| 14465 | .IX Item "-mno-shared" |
| 14466 | .PD |
| 14467 | Generate (do not generate) code that is fully position-independent, |
| 14468 | and that can therefore be linked into shared libraries. This option |
| 14469 | only affects \fB\-mabicalls\fR. |
| 14470 | .Sp |
| 14471 | All \fB\-mabicalls\fR code has traditionally been position-independent, |
| 14472 | regardless of options like \fB\-fPIC\fR and \fB\-fpic\fR. However, |
| 14473 | as an extension, the \s-1GNU\s0 toolchain allows executables to use absolute |
| 14474 | accesses for locally-binding symbols. It can also use shorter \s-1GP\s0 |
| 14475 | initialization sequences and generate direct calls to locally-defined |
| 14476 | functions. This mode is selected by \fB\-mno\-shared\fR. |
| 14477 | .Sp |
| 14478 | \&\fB\-mno\-shared\fR depends on binutils 2.16 or higher and generates |
| 14479 | objects that can only be linked by the \s-1GNU\s0 linker. However, the option |
| 14480 | does not affect the \s-1ABI\s0 of the final executable; it only affects the \s-1ABI\s0 |
| 14481 | of relocatable objects. Using \fB\-mno\-shared\fR will generally make |
| 14482 | executables both smaller and quicker. |
| 14483 | .Sp |
| 14484 | \&\fB\-mshared\fR is the default. |
| 14485 | .IP "\fB\-mplt\fR" 4 |
| 14486 | .IX Item "-mplt" |
| 14487 | .PD 0 |
| 14488 | .IP "\fB\-mno\-plt\fR" 4 |
| 14489 | .IX Item "-mno-plt" |
| 14490 | .PD |
| 14491 | Assume (do not assume) that the static and dynamic linkers |
| 14492 | support PLTs and copy relocations. This option only affects |
| 14493 | \&\fB\-mno\-shared \-mabicalls\fR. For the n64 \s-1ABI\s0, this option |
| 14494 | has no effect without \fB\-msym32\fR. |
| 14495 | .Sp |
| 14496 | You can make \fB\-mplt\fR the default by configuring |
| 14497 | \&\s-1GCC\s0 with \fB\-\-with\-mips\-plt\fR. The default is |
| 14498 | \&\fB\-mno\-plt\fR otherwise. |
| 14499 | .IP "\fB\-mxgot\fR" 4 |
| 14500 | .IX Item "-mxgot" |
| 14501 | .PD 0 |
| 14502 | .IP "\fB\-mno\-xgot\fR" 4 |
| 14503 | .IX Item "-mno-xgot" |
| 14504 | .PD |
| 14505 | Lift (do not lift) the usual restrictions on the size of the global |
| 14506 | offset table. |
| 14507 | .Sp |
| 14508 | \&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0. |
| 14509 | While this is relatively efficient, it will only work if the \s-1GOT\s0 |
| 14510 | is smaller than about 64k. Anything larger will cause the linker |
| 14511 | to report an error such as: |
| 14512 | .Sp |
| 14513 | .Vb 1 |
| 14514 | \& relocation truncated to fit: R_MIPS_GOT16 foobar |
| 14515 | .Ve |
| 14516 | .Sp |
| 14517 | If this happens, you should recompile your code with \fB\-mxgot\fR. |
| 14518 | It should then work with very large GOTs, although it will also be |
| 14519 | less efficient, since it will take three instructions to fetch the |
| 14520 | value of a global symbol. |
| 14521 | .Sp |
| 14522 | Note that some linkers can create multiple GOTs. If you have such a |
| 14523 | linker, you should only need to use \fB\-mxgot\fR when a single object |
| 14524 | file accesses more than 64k's worth of \s-1GOT\s0 entries. Very few do. |
| 14525 | .Sp |
| 14526 | These options have no effect unless \s-1GCC\s0 is generating position |
| 14527 | independent code. |
| 14528 | .IP "\fB\-mgp32\fR" 4 |
| 14529 | .IX Item "-mgp32" |
| 14530 | Assume that general-purpose registers are 32 bits wide. |
| 14531 | .IP "\fB\-mgp64\fR" 4 |
| 14532 | .IX Item "-mgp64" |
| 14533 | Assume that general-purpose registers are 64 bits wide. |
| 14534 | .IP "\fB\-mfp32\fR" 4 |
| 14535 | .IX Item "-mfp32" |
| 14536 | Assume that floating-point registers are 32 bits wide. |
| 14537 | .IP "\fB\-mfp64\fR" 4 |
| 14538 | .IX Item "-mfp64" |
| 14539 | Assume that floating-point registers are 64 bits wide. |
| 14540 | .IP "\fB\-mhard\-float\fR" 4 |
| 14541 | .IX Item "-mhard-float" |
| 14542 | Use floating-point coprocessor instructions. |
| 14543 | .IP "\fB\-msoft\-float\fR" 4 |
| 14544 | .IX Item "-msoft-float" |
| 14545 | Do not use floating-point coprocessor instructions. Implement |
| 14546 | floating-point calculations using library calls instead. |
| 14547 | .IP "\fB\-msingle\-float\fR" 4 |
| 14548 | .IX Item "-msingle-float" |
| 14549 | Assume that the floating-point coprocessor only supports single-precision |
| 14550 | operations. |
| 14551 | .IP "\fB\-mdouble\-float\fR" 4 |
| 14552 | .IX Item "-mdouble-float" |
| 14553 | Assume that the floating-point coprocessor supports double-precision |
| 14554 | operations. This is the default. |
| 14555 | .IP "\fB\-mllsc\fR" 4 |
| 14556 | .IX Item "-mllsc" |
| 14557 | .PD 0 |
| 14558 | .IP "\fB\-mno\-llsc\fR" 4 |
| 14559 | .IX Item "-mno-llsc" |
| 14560 | .PD |
| 14561 | Use (do not use) \fBll\fR, \fBsc\fR, and \fBsync\fR instructions to |
| 14562 | implement atomic memory built-in functions. When neither option is |
| 14563 | specified, \s-1GCC\s0 will use the instructions if the target architecture |
| 14564 | supports them. |
| 14565 | .Sp |
| 14566 | \&\fB\-mllsc\fR is useful if the runtime environment can emulate the |
| 14567 | instructions and \fB\-mno\-llsc\fR can be useful when compiling for |
| 14568 | nonstandard ISAs. You can make either option the default by |
| 14569 | configuring \s-1GCC\s0 with \fB\-\-with\-llsc\fR and \fB\-\-without\-llsc\fR |
| 14570 | respectively. \fB\-\-with\-llsc\fR is the default for some |
| 14571 | configurations; see the installation documentation for details. |
| 14572 | .IP "\fB\-mdsp\fR" 4 |
| 14573 | .IX Item "-mdsp" |
| 14574 | .PD 0 |
| 14575 | .IP "\fB\-mno\-dsp\fR" 4 |
| 14576 | .IX Item "-mno-dsp" |
| 14577 | .PD |
| 14578 | Use (do not use) revision 1 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. |
| 14579 | This option defines the |
| 14580 | preprocessor macro \fB_\|_mips_dsp\fR. It also defines |
| 14581 | \&\fB_\|_mips_dsp_rev\fR to 1. |
| 14582 | .IP "\fB\-mdspr2\fR" 4 |
| 14583 | .IX Item "-mdspr2" |
| 14584 | .PD 0 |
| 14585 | .IP "\fB\-mno\-dspr2\fR" 4 |
| 14586 | .IX Item "-mno-dspr2" |
| 14587 | .PD |
| 14588 | Use (do not use) revision 2 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0. |
| 14589 | This option defines the |
| 14590 | preprocessor macros \fB_\|_mips_dsp\fR and \fB_\|_mips_dspr2\fR. |
| 14591 | It also defines \fB_\|_mips_dsp_rev\fR to 2. |
| 14592 | .IP "\fB\-msmartmips\fR" 4 |
| 14593 | .IX Item "-msmartmips" |
| 14594 | .PD 0 |
| 14595 | .IP "\fB\-mno\-smartmips\fR" 4 |
| 14596 | .IX Item "-mno-smartmips" |
| 14597 | .PD |
| 14598 | Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE\s0. |
| 14599 | .IP "\fB\-mpaired\-single\fR" 4 |
| 14600 | .IX Item "-mpaired-single" |
| 14601 | .PD 0 |
| 14602 | .IP "\fB\-mno\-paired\-single\fR" 4 |
| 14603 | .IX Item "-mno-paired-single" |
| 14604 | .PD |
| 14605 | Use (do not use) paired-single floating-point instructions. |
| 14606 | This option requires |
| 14607 | hardware floating-point support to be enabled. |
| 14608 | .IP "\fB\-mdmx\fR" 4 |
| 14609 | .IX Item "-mdmx" |
| 14610 | .PD 0 |
| 14611 | .IP "\fB\-mno\-mdmx\fR" 4 |
| 14612 | .IX Item "-mno-mdmx" |
| 14613 | .PD |
| 14614 | Use (do not use) \s-1MIPS\s0 Digital Media Extension instructions. |
| 14615 | This option can only be used when generating 64\-bit code and requires |
| 14616 | hardware floating-point support to be enabled. |
| 14617 | .IP "\fB\-mips3d\fR" 4 |
| 14618 | .IX Item "-mips3d" |
| 14619 | .PD 0 |
| 14620 | .IP "\fB\-mno\-mips3d\fR" 4 |
| 14621 | .IX Item "-mno-mips3d" |
| 14622 | .PD |
| 14623 | Use (do not use) the \s-1MIPS\-3D\s0 \s-1ASE\s0. |
| 14624 | The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR. |
| 14625 | .IP "\fB\-mmt\fR" 4 |
| 14626 | .IX Item "-mmt" |
| 14627 | .PD 0 |
| 14628 | .IP "\fB\-mno\-mt\fR" 4 |
| 14629 | .IX Item "-mno-mt" |
| 14630 | .PD |
| 14631 | Use (do not use) \s-1MT\s0 Multithreading instructions. |
| 14632 | .IP "\fB\-mlong64\fR" 4 |
| 14633 | .IX Item "-mlong64" |
| 14634 | Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide. See \fB\-mlong32\fR for |
| 14635 | an explanation of the default and the way that the pointer size is |
| 14636 | determined. |
| 14637 | .IP "\fB\-mlong32\fR" 4 |
| 14638 | .IX Item "-mlong32" |
| 14639 | Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide. |
| 14640 | .Sp |
| 14641 | The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on |
| 14642 | the \s-1ABI\s0. All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs. The n64 \s-1ABI\s0 |
| 14643 | uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use |
| 14644 | 32\-bit \f(CW\*(C`long\*(C'\fRs. Pointers are the same size as \f(CW\*(C`long\*(C'\fRs, |
| 14645 | or the same size as integer registers, whichever is smaller. |
| 14646 | .IP "\fB\-msym32\fR" 4 |
| 14647 | .IX Item "-msym32" |
| 14648 | .PD 0 |
| 14649 | .IP "\fB\-mno\-sym32\fR" 4 |
| 14650 | .IX Item "-mno-sym32" |
| 14651 | .PD |
| 14652 | Assume (do not assume) that all symbols have 32\-bit values, regardless |
| 14653 | of the selected \s-1ABI\s0. This option is useful in combination with |
| 14654 | \&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0 |
| 14655 | to generate shorter and faster references to symbolic addresses. |
| 14656 | .IP "\fB\-G\fR \fInum\fR" 4 |
| 14657 | .IX Item "-G num" |
| 14658 | Put definitions of externally-visible data in a small data section |
| 14659 | if that data is no bigger than \fInum\fR bytes. \s-1GCC\s0 can then access |
| 14660 | the data more efficiently; see \fB\-mgpopt\fR for details. |
| 14661 | .Sp |
| 14662 | The default \fB\-G\fR option depends on the configuration. |
| 14663 | .IP "\fB\-mlocal\-sdata\fR" 4 |
| 14664 | .IX Item "-mlocal-sdata" |
| 14665 | .PD 0 |
| 14666 | .IP "\fB\-mno\-local\-sdata\fR" 4 |
| 14667 | .IX Item "-mno-local-sdata" |
| 14668 | .PD |
| 14669 | Extend (do not extend) the \fB\-G\fR behavior to local data too, |
| 14670 | such as to static variables in C. \fB\-mlocal\-sdata\fR is the |
| 14671 | default for all configurations. |
| 14672 | .Sp |
| 14673 | If the linker complains that an application is using too much small data, |
| 14674 | you might want to try rebuilding the less performance-critical parts with |
| 14675 | \&\fB\-mno\-local\-sdata\fR. You might also want to build large |
| 14676 | libraries with \fB\-mno\-local\-sdata\fR, so that the libraries leave |
| 14677 | more room for the main program. |
| 14678 | .IP "\fB\-mextern\-sdata\fR" 4 |
| 14679 | .IX Item "-mextern-sdata" |
| 14680 | .PD 0 |
| 14681 | .IP "\fB\-mno\-extern\-sdata\fR" 4 |
| 14682 | .IX Item "-mno-extern-sdata" |
| 14683 | .PD |
| 14684 | Assume (do not assume) that externally-defined data will be in |
| 14685 | a small data section if that data is within the \fB\-G\fR limit. |
| 14686 | \&\fB\-mextern\-sdata\fR is the default for all configurations. |
| 14687 | .Sp |
| 14688 | If you compile a module \fIMod\fR with \fB\-mextern\-sdata\fR \fB\-G\fR |
| 14689 | \&\fInum\fR \fB\-mgpopt\fR, and \fIMod\fR references a variable \fIVar\fR |
| 14690 | that is no bigger than \fInum\fR bytes, you must make sure that \fIVar\fR |
| 14691 | is placed in a small data section. If \fIVar\fR is defined by another |
| 14692 | module, you must either compile that module with a high-enough |
| 14693 | \&\fB\-G\fR setting or attach a \f(CW\*(C`section\*(C'\fR attribute to \fIVar\fR's |
| 14694 | definition. If \fIVar\fR is common, you must link the application |
| 14695 | with a high-enough \fB\-G\fR setting. |
| 14696 | .Sp |
| 14697 | The easiest way of satisfying these restrictions is to compile |
| 14698 | and link every module with the same \fB\-G\fR option. However, |
| 14699 | you may wish to build a library that supports several different |
| 14700 | small data limits. You can do this by compiling the library with |
| 14701 | the highest supported \fB\-G\fR setting and additionally using |
| 14702 | \&\fB\-mno\-extern\-sdata\fR to stop the library from making assumptions |
| 14703 | about externally-defined data. |
| 14704 | .IP "\fB\-mgpopt\fR" 4 |
| 14705 | .IX Item "-mgpopt" |
| 14706 | .PD 0 |
| 14707 | .IP "\fB\-mno\-gpopt\fR" 4 |
| 14708 | .IX Item "-mno-gpopt" |
| 14709 | .PD |
| 14710 | Use (do not use) GP-relative accesses for symbols that are known to be |
| 14711 | in a small data section; see \fB\-G\fR, \fB\-mlocal\-sdata\fR and |
| 14712 | \&\fB\-mextern\-sdata\fR. \fB\-mgpopt\fR is the default for all |
| 14713 | configurations. |
| 14714 | .Sp |
| 14715 | \&\fB\-mno\-gpopt\fR is useful for cases where the \f(CW$gp\fR register |
| 14716 | might not hold the value of \f(CW\*(C`_gp\*(C'\fR. For example, if the code is |
| 14717 | part of a library that might be used in a boot monitor, programs that |
| 14718 | call boot monitor routines will pass an unknown value in \f(CW$gp\fR. |
| 14719 | (In such situations, the boot monitor itself would usually be compiled |
| 14720 | with \fB\-G0\fR.) |
| 14721 | .Sp |
| 14722 | \&\fB\-mno\-gpopt\fR implies \fB\-mno\-local\-sdata\fR and |
| 14723 | \&\fB\-mno\-extern\-sdata\fR. |
| 14724 | .IP "\fB\-membedded\-data\fR" 4 |
| 14725 | .IX Item "-membedded-data" |
| 14726 | .PD 0 |
| 14727 | .IP "\fB\-mno\-embedded\-data\fR" 4 |
| 14728 | .IX Item "-mno-embedded-data" |
| 14729 | .PD |
| 14730 | Allocate variables to the read-only data section first if possible, then |
| 14731 | next in the small data section if possible, otherwise in data. This gives |
| 14732 | slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required |
| 14733 | when executing, and thus may be preferred for some embedded systems. |
| 14734 | .IP "\fB\-muninit\-const\-in\-rodata\fR" 4 |
| 14735 | .IX Item "-muninit-const-in-rodata" |
| 14736 | .PD 0 |
| 14737 | .IP "\fB\-mno\-uninit\-const\-in\-rodata\fR" 4 |
| 14738 | .IX Item "-mno-uninit-const-in-rodata" |
| 14739 | .PD |
| 14740 | Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section. |
| 14741 | This option is only meaningful in conjunction with \fB\-membedded\-data\fR. |
| 14742 | .IP "\fB\-mcode\-readable=\fR\fIsetting\fR" 4 |
| 14743 | .IX Item "-mcode-readable=setting" |
| 14744 | Specify whether \s-1GCC\s0 may generate code that reads from executable sections. |
| 14745 | There are three possible settings: |
| 14746 | .RS 4 |
| 14747 | .IP "\fB\-mcode\-readable=yes\fR" 4 |
| 14748 | .IX Item "-mcode-readable=yes" |
| 14749 | Instructions may freely access executable sections. This is the |
| 14750 | default setting. |
| 14751 | .IP "\fB\-mcode\-readable=pcrel\fR" 4 |
| 14752 | .IX Item "-mcode-readable=pcrel" |
| 14753 | \&\s-1MIPS16\s0 PC-relative load instructions can access executable sections, |
| 14754 | but other instructions must not do so. This option is useful on 4KSc |
| 14755 | and 4KSd processors when the code TLBs have the Read Inhibit bit set. |
| 14756 | It is also useful on processors that can be configured to have a dual |
| 14757 | instruction/data \s-1SRAM\s0 interface and that, like the M4K, automatically |
| 14758 | redirect PC-relative loads to the instruction \s-1RAM\s0. |
| 14759 | .IP "\fB\-mcode\-readable=no\fR" 4 |
| 14760 | .IX Item "-mcode-readable=no" |
| 14761 | Instructions must not access executable sections. This option can be |
| 14762 | useful on targets that are configured to have a dual instruction/data |
| 14763 | \&\s-1SRAM\s0 interface but that (unlike the M4K) do not automatically redirect |
| 14764 | PC-relative loads to the instruction \s-1RAM\s0. |
| 14765 | .RE |
| 14766 | .RS 4 |
| 14767 | .RE |
| 14768 | .IP "\fB\-msplit\-addresses\fR" 4 |
| 14769 | .IX Item "-msplit-addresses" |
| 14770 | .PD 0 |
| 14771 | .IP "\fB\-mno\-split\-addresses\fR" 4 |
| 14772 | .IX Item "-mno-split-addresses" |
| 14773 | .PD |
| 14774 | Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler |
| 14775 | relocation operators. This option has been superseded by |
| 14776 | \&\fB\-mexplicit\-relocs\fR but is retained for backwards compatibility. |
| 14777 | .IP "\fB\-mexplicit\-relocs\fR" 4 |
| 14778 | .IX Item "-mexplicit-relocs" |
| 14779 | .PD 0 |
| 14780 | .IP "\fB\-mno\-explicit\-relocs\fR" 4 |
| 14781 | .IX Item "-mno-explicit-relocs" |
| 14782 | .PD |
| 14783 | Use (do not use) assembler relocation operators when dealing with symbolic |
| 14784 | addresses. The alternative, selected by \fB\-mno\-explicit\-relocs\fR, |
| 14785 | is to use assembler macros instead. |
| 14786 | .Sp |
| 14787 | \&\fB\-mexplicit\-relocs\fR is the default if \s-1GCC\s0 was configured |
| 14788 | to use an assembler that supports relocation operators. |
| 14789 | .IP "\fB\-mcheck\-zero\-division\fR" 4 |
| 14790 | .IX Item "-mcheck-zero-division" |
| 14791 | .PD 0 |
| 14792 | .IP "\fB\-mno\-check\-zero\-division\fR" 4 |
| 14793 | .IX Item "-mno-check-zero-division" |
| 14794 | .PD |
| 14795 | Trap (do not trap) on integer division by zero. |
| 14796 | .Sp |
| 14797 | The default is \fB\-mcheck\-zero\-division\fR. |
| 14798 | .IP "\fB\-mdivide\-traps\fR" 4 |
| 14799 | .IX Item "-mdivide-traps" |
| 14800 | .PD 0 |
| 14801 | .IP "\fB\-mdivide\-breaks\fR" 4 |
| 14802 | .IX Item "-mdivide-breaks" |
| 14803 | .PD |
| 14804 | \&\s-1MIPS\s0 systems check for division by zero by generating either a |
| 14805 | conditional trap or a break instruction. Using traps results in |
| 14806 | smaller code, but is only supported on \s-1MIPS\s0 \s-1II\s0 and later. Also, some |
| 14807 | versions of the Linux kernel have a bug that prevents trap from |
| 14808 | generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR). Use \fB\-mdivide\-traps\fR to |
| 14809 | allow conditional traps on architectures that support them and |
| 14810 | \&\fB\-mdivide\-breaks\fR to force the use of breaks. |
| 14811 | .Sp |
| 14812 | The default is usually \fB\-mdivide\-traps\fR, but this can be |
| 14813 | overridden at configure time using \fB\-\-with\-divide=breaks\fR. |
| 14814 | Divide-by-zero checks can be completely disabled using |
| 14815 | \&\fB\-mno\-check\-zero\-division\fR. |
| 14816 | .IP "\fB\-mmemcpy\fR" 4 |
| 14817 | .IX Item "-mmemcpy" |
| 14818 | .PD 0 |
| 14819 | .IP "\fB\-mno\-memcpy\fR" 4 |
| 14820 | .IX Item "-mno-memcpy" |
| 14821 | .PD |
| 14822 | Force (do not force) the use of \f(CW\*(C`memcpy()\*(C'\fR for non-trivial block |
| 14823 | moves. The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline |
| 14824 | most constant-sized copies. |
| 14825 | .IP "\fB\-mlong\-calls\fR" 4 |
| 14826 | .IX Item "-mlong-calls" |
| 14827 | .PD 0 |
| 14828 | .IP "\fB\-mno\-long\-calls\fR" 4 |
| 14829 | .IX Item "-mno-long-calls" |
| 14830 | .PD |
| 14831 | Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction. Calling |
| 14832 | functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller |
| 14833 | and callee to be in the same 256 megabyte segment. |
| 14834 | .Sp |
| 14835 | This option has no effect on abicalls code. The default is |
| 14836 | \&\fB\-mno\-long\-calls\fR. |
| 14837 | .IP "\fB\-mmad\fR" 4 |
| 14838 | .IX Item "-mmad" |
| 14839 | .PD 0 |
| 14840 | .IP "\fB\-mno\-mad\fR" 4 |
| 14841 | .IX Item "-mno-mad" |
| 14842 | .PD |
| 14843 | Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR |
| 14844 | instructions, as provided by the R4650 \s-1ISA\s0. |
| 14845 | .IP "\fB\-mfused\-madd\fR" 4 |
| 14846 | .IX Item "-mfused-madd" |
| 14847 | .PD 0 |
| 14848 | .IP "\fB\-mno\-fused\-madd\fR" 4 |
| 14849 | .IX Item "-mno-fused-madd" |
| 14850 | .PD |
| 14851 | Enable (disable) use of the floating-point multiply-accumulate |
| 14852 | instructions, when they are available. The default is |
| 14853 | \&\fB\-mfused\-madd\fR. |
| 14854 | .Sp |
| 14855 | When multiply-accumulate instructions are used, the intermediate |
| 14856 | product is calculated to infinite precision and is not subject to |
| 14857 | the \s-1FCSR\s0 Flush to Zero bit. This may be undesirable in some |
| 14858 | circumstances. |
| 14859 | .IP "\fB\-nocpp\fR" 4 |
| 14860 | .IX Item "-nocpp" |
| 14861 | Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user |
| 14862 | assembler files (with a \fB.s\fR suffix) when assembling them. |
| 14863 | .IP "\fB\-mfix\-24k\fR" 4 |
| 14864 | .IX Item "-mfix-24k" |
| 14865 | .PD 0 |
| 14866 | .IP "\fB\-mno\-fix\-24k\fR" 4 |
| 14867 | .IX Item "-mno-fix-24k" |
| 14868 | .PD |
| 14869 | Work around the 24K E48 (lost data on stores during refill) errata. |
| 14870 | The workarounds are implemented by the assembler rather than by \s-1GCC\s0. |
| 14871 | .IP "\fB\-mfix\-r4000\fR" 4 |
| 14872 | .IX Item "-mfix-r4000" |
| 14873 | .PD 0 |
| 14874 | .IP "\fB\-mno\-fix\-r4000\fR" 4 |
| 14875 | .IX Item "-mno-fix-r4000" |
| 14876 | .PD |
| 14877 | Work around certain R4000 \s-1CPU\s0 errata: |
| 14878 | .RS 4 |
| 14879 | .IP "\-" 4 |
| 14880 | A double-word or a variable shift may give an incorrect result if executed |
| 14881 | immediately after starting an integer division. |
| 14882 | .IP "\-" 4 |
| 14883 | A double-word or a variable shift may give an incorrect result if executed |
| 14884 | while an integer multiplication is in progress. |
| 14885 | .IP "\-" 4 |
| 14886 | An integer division may give an incorrect result if started in a delay slot |
| 14887 | of a taken branch or a jump. |
| 14888 | .RE |
| 14889 | .RS 4 |
| 14890 | .RE |
| 14891 | .IP "\fB\-mfix\-r4400\fR" 4 |
| 14892 | .IX Item "-mfix-r4400" |
| 14893 | .PD 0 |
| 14894 | .IP "\fB\-mno\-fix\-r4400\fR" 4 |
| 14895 | .IX Item "-mno-fix-r4400" |
| 14896 | .PD |
| 14897 | Work around certain R4400 \s-1CPU\s0 errata: |
| 14898 | .RS 4 |
| 14899 | .IP "\-" 4 |
| 14900 | A double-word or a variable shift may give an incorrect result if executed |
| 14901 | immediately after starting an integer division. |
| 14902 | .RE |
| 14903 | .RS 4 |
| 14904 | .RE |
| 14905 | .IP "\fB\-mfix\-r10000\fR" 4 |
| 14906 | .IX Item "-mfix-r10000" |
| 14907 | .PD 0 |
| 14908 | .IP "\fB\-mno\-fix\-r10000\fR" 4 |
| 14909 | .IX Item "-mno-fix-r10000" |
| 14910 | .PD |
| 14911 | Work around certain R10000 errata: |
| 14912 | .RS 4 |
| 14913 | .IP "\-" 4 |
| 14914 | \&\f(CW\*(C`ll\*(C'\fR/\f(CW\*(C`sc\*(C'\fR sequences may not behave atomically on revisions |
| 14915 | prior to 3.0. They may deadlock on revisions 2.6 and earlier. |
| 14916 | .RE |
| 14917 | .RS 4 |
| 14918 | .Sp |
| 14919 | This option can only be used if the target architecture supports |
| 14920 | branch-likely instructions. \fB\-mfix\-r10000\fR is the default when |
| 14921 | \&\fB\-march=r10000\fR is used; \fB\-mno\-fix\-r10000\fR is the default |
| 14922 | otherwise. |
| 14923 | .RE |
| 14924 | .IP "\fB\-mfix\-vr4120\fR" 4 |
| 14925 | .IX Item "-mfix-vr4120" |
| 14926 | .PD 0 |
| 14927 | .IP "\fB\-mno\-fix\-vr4120\fR" 4 |
| 14928 | .IX Item "-mno-fix-vr4120" |
| 14929 | .PD |
| 14930 | Work around certain \s-1VR4120\s0 errata: |
| 14931 | .RS 4 |
| 14932 | .IP "\-" 4 |
| 14933 | \&\f(CW\*(C`dmultu\*(C'\fR does not always produce the correct result. |
| 14934 | .IP "\-" 4 |
| 14935 | \&\f(CW\*(C`div\*(C'\fR and \f(CW\*(C`ddiv\*(C'\fR do not always produce the correct result if one |
| 14936 | of the operands is negative. |
| 14937 | .RE |
| 14938 | .RS 4 |
| 14939 | .Sp |
| 14940 | The workarounds for the division errata rely on special functions in |
| 14941 | \&\fIlibgcc.a\fR. At present, these functions are only provided by |
| 14942 | the \f(CW\*(C`mips64vr*\-elf\*(C'\fR configurations. |
| 14943 | .Sp |
| 14944 | Other \s-1VR4120\s0 errata require a nop to be inserted between certain pairs of |
| 14945 | instructions. These errata are handled by the assembler, not by \s-1GCC\s0 itself. |
| 14946 | .RE |
| 14947 | .IP "\fB\-mfix\-vr4130\fR" 4 |
| 14948 | .IX Item "-mfix-vr4130" |
| 14949 | Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata. The |
| 14950 | workarounds are implemented by the assembler rather than by \s-1GCC\s0, |
| 14951 | although \s-1GCC\s0 will avoid using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the |
| 14952 | \&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR |
| 14953 | instructions are available instead. |
| 14954 | .IP "\fB\-mfix\-sb1\fR" 4 |
| 14955 | .IX Item "-mfix-sb1" |
| 14956 | .PD 0 |
| 14957 | .IP "\fB\-mno\-fix\-sb1\fR" 4 |
| 14958 | .IX Item "-mno-fix-sb1" |
| 14959 | .PD |
| 14960 | Work around certain \s-1SB\-1\s0 \s-1CPU\s0 core errata. |
| 14961 | (This flag currently works around the \s-1SB\-1\s0 revision 2 |
| 14962 | \&\*(L"F1\*(R" and \*(L"F2\*(R" floating-point errata.) |
| 14963 | .IP "\fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR" 4 |
| 14964 | .IX Item "-mr10k-cache-barrier=setting" |
| 14965 | Specify whether \s-1GCC\s0 should insert cache barriers to avoid the |
| 14966 | side-effects of speculation on R10K processors. |
| 14967 | .Sp |
| 14968 | In common with many processors, the R10K tries to predict the outcome |
| 14969 | of a conditional branch and speculatively executes instructions from |
| 14970 | the \*(L"taken\*(R" branch. It later aborts these instructions if the |
| 14971 | predicted outcome was wrong. However, on the R10K, even aborted |
| 14972 | instructions can have side effects. |
| 14973 | .Sp |
| 14974 | This problem only affects kernel stores and, depending on the system, |
| 14975 | kernel loads. As an example, a speculatively-executed store may load |
| 14976 | the target memory into cache and mark the cache line as dirty, even if |
| 14977 | the store itself is later aborted. If a \s-1DMA\s0 operation writes to the |
| 14978 | same area of memory before the \*(L"dirty\*(R" line is flushed, the cached |
| 14979 | data will overwrite the DMA-ed data. See the R10K processor manual |
| 14980 | for a full description, including other potential problems. |
| 14981 | .Sp |
| 14982 | One workaround is to insert cache barrier instructions before every memory |
| 14983 | access that might be speculatively executed and that might have side |
| 14984 | effects even if aborted. \fB\-mr10k\-cache\-barrier=\fR\fIsetting\fR |
| 14985 | controls \s-1GCC\s0's implementation of this workaround. It assumes that |
| 14986 | aborted accesses to any byte in the following regions will not have |
| 14987 | side effects: |
| 14988 | .RS 4 |
| 14989 | .IP "1." 4 |
| 14990 | the memory occupied by the current function's stack frame; |
| 14991 | .IP "2." 4 |
| 14992 | the memory occupied by an incoming stack argument; |
| 14993 | .IP "3." 4 |
| 14994 | the memory occupied by an object with a link-time-constant address. |
| 14995 | .RE |
| 14996 | .RS 4 |
| 14997 | .Sp |
| 14998 | It is the kernel's responsibility to ensure that speculative |
| 14999 | accesses to these regions are indeed safe. |
| 15000 | .Sp |
| 15001 | If the input program contains a function declaration such as: |
| 15002 | .Sp |
| 15003 | .Vb 1 |
| 15004 | \& void foo (void); |
| 15005 | .Ve |
| 15006 | .Sp |
| 15007 | then the implementation of \f(CW\*(C`foo\*(C'\fR must allow \f(CW\*(C`j foo\*(C'\fR and |
| 15008 | \&\f(CW\*(C`jal foo\*(C'\fR to be executed speculatively. \s-1GCC\s0 honors this |
| 15009 | restriction for functions it compiles itself. It expects non-GCC |
| 15010 | functions (such as hand-written assembly code) to do the same. |
| 15011 | .Sp |
| 15012 | The option has three forms: |
| 15013 | .IP "\fB\-mr10k\-cache\-barrier=load\-store\fR" 4 |
| 15014 | .IX Item "-mr10k-cache-barrier=load-store" |
| 15015 | Insert a cache barrier before a load or store that might be |
| 15016 | speculatively executed and that might have side effects even |
| 15017 | if aborted. |
| 15018 | .IP "\fB\-mr10k\-cache\-barrier=store\fR" 4 |
| 15019 | .IX Item "-mr10k-cache-barrier=store" |
| 15020 | Insert a cache barrier before a store that might be speculatively |
| 15021 | executed and that might have side effects even if aborted. |
| 15022 | .IP "\fB\-mr10k\-cache\-barrier=none\fR" 4 |
| 15023 | .IX Item "-mr10k-cache-barrier=none" |
| 15024 | Disable the insertion of cache barriers. This is the default setting. |
| 15025 | .RE |
| 15026 | .RS 4 |
| 15027 | .RE |
| 15028 | .IP "\fB\-mflush\-func=\fR\fIfunc\fR" 4 |
| 15029 | .IX Item "-mflush-func=func" |
| 15030 | .PD 0 |
| 15031 | .IP "\fB\-mno\-flush\-func\fR" 4 |
| 15032 | .IX Item "-mno-flush-func" |
| 15033 | .PD |
| 15034 | Specifies the function to call to flush the I and D caches, or to not |
| 15035 | call any such function. If called, the function must take the same |
| 15036 | arguments as the common \f(CW\*(C`_flush_func()\*(C'\fR, that is, the address of the |
| 15037 | memory range for which the cache is being flushed, the size of the |
| 15038 | memory range, and the number 3 (to flush both caches). The default |
| 15039 | depends on the target \s-1GCC\s0 was configured for, but commonly is either |
| 15040 | \&\fB_flush_func\fR or \fB_\|_cpu_flush\fR. |
| 15041 | .IP "\fBmbranch\-cost=\fR\fInum\fR" 4 |
| 15042 | .IX Item "mbranch-cost=num" |
| 15043 | Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions. |
| 15044 | This cost is only a heuristic and is not guaranteed to produce |
| 15045 | consistent results across releases. A zero cost redundantly selects |
| 15046 | the default, which is based on the \fB\-mtune\fR setting. |
| 15047 | .IP "\fB\-mbranch\-likely\fR" 4 |
| 15048 | .IX Item "-mbranch-likely" |
| 15049 | .PD 0 |
| 15050 | .IP "\fB\-mno\-branch\-likely\fR" 4 |
| 15051 | .IX Item "-mno-branch-likely" |
| 15052 | .PD |
| 15053 | Enable or disable use of Branch Likely instructions, regardless of the |
| 15054 | default for the selected architecture. By default, Branch Likely |
| 15055 | instructions may be generated if they are supported by the selected |
| 15056 | architecture. An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures |
| 15057 | and processors that implement those architectures; for those, Branch |
| 15058 | Likely instructions will not be generated by default because the \s-1MIPS32\s0 |
| 15059 | and \s-1MIPS64\s0 architectures specifically deprecate their use. |
| 15060 | .IP "\fB\-mfp\-exceptions\fR" 4 |
| 15061 | .IX Item "-mfp-exceptions" |
| 15062 | .PD 0 |
| 15063 | .IP "\fB\-mno\-fp\-exceptions\fR" 4 |
| 15064 | .IX Item "-mno-fp-exceptions" |
| 15065 | .PD |
| 15066 | Specifies whether \s-1FP\s0 exceptions are enabled. This affects how we schedule |
| 15067 | \&\s-1FP\s0 instructions for some processors. The default is that \s-1FP\s0 exceptions are |
| 15068 | enabled. |
| 15069 | .Sp |
| 15070 | For instance, on the \s-1SB\-1\s0, if \s-1FP\s0 exceptions are disabled, and we are emitting |
| 15071 | 64\-bit code, then we can use both \s-1FP\s0 pipes. Otherwise, we can only use one |
| 15072 | \&\s-1FP\s0 pipe. |
| 15073 | .IP "\fB\-mvr4130\-align\fR" 4 |
| 15074 | .IX Item "-mvr4130-align" |
| 15075 | .PD 0 |
| 15076 | .IP "\fB\-mno\-vr4130\-align\fR" 4 |
| 15077 | .IX Item "-mno-vr4130-align" |
| 15078 | .PD |
| 15079 | The \s-1VR4130\s0 pipeline is two-way superscalar, but can only issue two |
| 15080 | instructions together if the first one is 8\-byte aligned. When this |
| 15081 | option is enabled, \s-1GCC\s0 will align pairs of instructions that it |
| 15082 | thinks should execute in parallel. |
| 15083 | .Sp |
| 15084 | This option only has an effect when optimizing for the \s-1VR4130\s0. |
| 15085 | It normally makes code faster, but at the expense of making it bigger. |
| 15086 | It is enabled by default at optimization level \fB\-O3\fR. |
| 15087 | .IP "\fB\-msynci\fR" 4 |
| 15088 | .IX Item "-msynci" |
| 15089 | .PD 0 |
| 15090 | .IP "\fB\-mno\-synci\fR" 4 |
| 15091 | .IX Item "-mno-synci" |
| 15092 | .PD |
| 15093 | Enable (disable) generation of \f(CW\*(C`synci\*(C'\fR instructions on |
| 15094 | architectures that support it. The \f(CW\*(C`synci\*(C'\fR instructions (if |
| 15095 | enabled) will be generated when \f(CW\*(C`_\|_builtin_\|_\|_clear_cache()\*(C'\fR is |
| 15096 | compiled. |
| 15097 | .Sp |
| 15098 | This option defaults to \f(CW\*(C`\-mno\-synci\*(C'\fR, but the default can be |
| 15099 | overridden by configuring with \f(CW\*(C`\-\-with\-synci\*(C'\fR. |
| 15100 | .Sp |
| 15101 | When compiling code for single processor systems, it is generally safe |
| 15102 | to use \f(CW\*(C`synci\*(C'\fR. However, on many multi-core (\s-1SMP\s0) systems, it |
| 15103 | will not invalidate the instruction caches on all cores and may lead |
| 15104 | to undefined behavior. |
| 15105 | .IP "\fB\-mrelax\-pic\-calls\fR" 4 |
| 15106 | .IX Item "-mrelax-pic-calls" |
| 15107 | .PD 0 |
| 15108 | .IP "\fB\-mno\-relax\-pic\-calls\fR" 4 |
| 15109 | .IX Item "-mno-relax-pic-calls" |
| 15110 | .PD |
| 15111 | Try to turn \s-1PIC\s0 calls that are normally dispatched via register |
| 15112 | \&\f(CW$25\fR into direct calls. This is only possible if the linker can |
| 15113 | resolve the destination at link-time and if the destination is within |
| 15114 | range for a direct call. |
| 15115 | .Sp |
| 15116 | \&\fB\-mrelax\-pic\-calls\fR is the default if \s-1GCC\s0 was configured to use |
| 15117 | an assembler and a linker that supports the \f(CW\*(C`.reloc\*(C'\fR assembly |
| 15118 | directive and \f(CW\*(C`\-mexplicit\-relocs\*(C'\fR is in effect. With |
| 15119 | \&\f(CW\*(C`\-mno\-explicit\-relocs\*(C'\fR, this optimization can be performed by the |
| 15120 | assembler and the linker alone without help from the compiler. |
| 15121 | .IP "\fB\-mmcount\-ra\-address\fR" 4 |
| 15122 | .IX Item "-mmcount-ra-address" |
| 15123 | .PD 0 |
| 15124 | .IP "\fB\-mno\-mcount\-ra\-address\fR" 4 |
| 15125 | .IX Item "-mno-mcount-ra-address" |
| 15126 | .PD |
| 15127 | Emit (do not emit) code that allows \f(CW\*(C`_mcount\*(C'\fR to modify the |
| 15128 | calling function's return address. When enabled, this option extends |
| 15129 | the usual \f(CW\*(C`_mcount\*(C'\fR interface with a new \fIra-address\fR |
| 15130 | parameter, which has type \f(CW\*(C`intptr_t *\*(C'\fR and is passed in register |
| 15131 | \&\f(CW$12\fR. \f(CW\*(C`_mcount\*(C'\fR can then modify the return address by |
| 15132 | doing both of the following: |
| 15133 | .RS 4 |
| 15134 | .IP "\(bu" 4 |
| 15135 | Returning the new address in register \f(CW$31\fR. |
| 15136 | .IP "\(bu" 4 |
| 15137 | Storing the new address in \f(CW\*(C`*\f(CIra\-address\f(CW\*(C'\fR, |
| 15138 | if \fIra-address\fR is nonnull. |
| 15139 | .RE |
| 15140 | .RS 4 |
| 15141 | .Sp |
| 15142 | The default is \fB\-mno\-mcount\-ra\-address\fR. |
| 15143 | .RE |
| 15144 | .PP |
| 15145 | \fI\s-1MMIX\s0 Options\fR |
| 15146 | .IX Subsection "MMIX Options" |
| 15147 | .PP |
| 15148 | These options are defined for the \s-1MMIX:\s0 |
| 15149 | .IP "\fB\-mlibfuncs\fR" 4 |
| 15150 | .IX Item "-mlibfuncs" |
| 15151 | .PD 0 |
| 15152 | .IP "\fB\-mno\-libfuncs\fR" 4 |
| 15153 | .IX Item "-mno-libfuncs" |
| 15154 | .PD |
| 15155 | Specify that intrinsic library functions are being compiled, passing all |
| 15156 | values in registers, no matter the size. |
| 15157 | .IP "\fB\-mepsilon\fR" 4 |
| 15158 | .IX Item "-mepsilon" |
| 15159 | .PD 0 |
| 15160 | .IP "\fB\-mno\-epsilon\fR" 4 |
| 15161 | .IX Item "-mno-epsilon" |
| 15162 | .PD |
| 15163 | Generate floating-point comparison instructions that compare with respect |
| 15164 | to the \f(CW\*(C`rE\*(C'\fR epsilon register. |
| 15165 | .IP "\fB\-mabi=mmixware\fR" 4 |
| 15166 | .IX Item "-mabi=mmixware" |
| 15167 | .PD 0 |
| 15168 | .IP "\fB\-mabi=gnu\fR" 4 |
| 15169 | .IX Item "-mabi=gnu" |
| 15170 | .PD |
| 15171 | Generate code that passes function parameters and return values that (in |
| 15172 | the called function) are seen as registers \f(CW$0\fR and up, as opposed to |
| 15173 | the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW$231\fR and up. |
| 15174 | .IP "\fB\-mzero\-extend\fR" 4 |
| 15175 | .IX Item "-mzero-extend" |
| 15176 | .PD 0 |
| 15177 | .IP "\fB\-mno\-zero\-extend\fR" 4 |
| 15178 | .IX Item "-mno-zero-extend" |
| 15179 | .PD |
| 15180 | When reading data from memory in sizes shorter than 64 bits, use (do not |
| 15181 | use) zero-extending load instructions by default, rather than |
| 15182 | sign-extending ones. |
| 15183 | .IP "\fB\-mknuthdiv\fR" 4 |
| 15184 | .IX Item "-mknuthdiv" |
| 15185 | .PD 0 |
| 15186 | .IP "\fB\-mno\-knuthdiv\fR" 4 |
| 15187 | .IX Item "-mno-knuthdiv" |
| 15188 | .PD |
| 15189 | Make the result of a division yielding a remainder have the same sign as |
| 15190 | the divisor. With the default, \fB\-mno\-knuthdiv\fR, the sign of the |
| 15191 | remainder follows the sign of the dividend. Both methods are |
| 15192 | arithmetically valid, the latter being almost exclusively used. |
| 15193 | .IP "\fB\-mtoplevel\-symbols\fR" 4 |
| 15194 | .IX Item "-mtoplevel-symbols" |
| 15195 | .PD 0 |
| 15196 | .IP "\fB\-mno\-toplevel\-symbols\fR" 4 |
| 15197 | .IX Item "-mno-toplevel-symbols" |
| 15198 | .PD |
| 15199 | Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly |
| 15200 | code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive. |
| 15201 | .IP "\fB\-melf\fR" 4 |
| 15202 | .IX Item "-melf" |
| 15203 | Generate an executable in the \s-1ELF\s0 format, rather than the default |
| 15204 | \&\fBmmo\fR format used by the \fBmmix\fR simulator. |
| 15205 | .IP "\fB\-mbranch\-predict\fR" 4 |
| 15206 | .IX Item "-mbranch-predict" |
| 15207 | .PD 0 |
| 15208 | .IP "\fB\-mno\-branch\-predict\fR" 4 |
| 15209 | .IX Item "-mno-branch-predict" |
| 15210 | .PD |
| 15211 | Use (do not use) the probable-branch instructions, when static branch |
| 15212 | prediction indicates a probable branch. |
| 15213 | .IP "\fB\-mbase\-addresses\fR" 4 |
| 15214 | .IX Item "-mbase-addresses" |
| 15215 | .PD 0 |
| 15216 | .IP "\fB\-mno\-base\-addresses\fR" 4 |
| 15217 | .IX Item "-mno-base-addresses" |
| 15218 | .PD |
| 15219 | Generate (do not generate) code that uses \fIbase addresses\fR. Using a |
| 15220 | base address automatically generates a request (handled by the assembler |
| 15221 | and the linker) for a constant to be set up in a global register. The |
| 15222 | register is used for one or more base address requests within the range 0 |
| 15223 | to 255 from the value held in the register. The generally leads to short |
| 15224 | and fast code, but the number of different data items that can be |
| 15225 | addressed is limited. This means that a program that uses lots of static |
| 15226 | data may require \fB\-mno\-base\-addresses\fR. |
| 15227 | .IP "\fB\-msingle\-exit\fR" 4 |
| 15228 | .IX Item "-msingle-exit" |
| 15229 | .PD 0 |
| 15230 | .IP "\fB\-mno\-single\-exit\fR" 4 |
| 15231 | .IX Item "-mno-single-exit" |
| 15232 | .PD |
| 15233 | Force (do not force) generated code to have a single exit point in each |
| 15234 | function. |
| 15235 | .PP |
| 15236 | \fI\s-1MN10300\s0 Options\fR |
| 15237 | .IX Subsection "MN10300 Options" |
| 15238 | .PP |
| 15239 | These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures: |
| 15240 | .IP "\fB\-mmult\-bug\fR" 4 |
| 15241 | .IX Item "-mmult-bug" |
| 15242 | Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0 |
| 15243 | processors. This is the default. |
| 15244 | .IP "\fB\-mno\-mult\-bug\fR" 4 |
| 15245 | .IX Item "-mno-mult-bug" |
| 15246 | Do not generate code to avoid bugs in the multiply instructions for the |
| 15247 | \&\s-1MN10300\s0 processors. |
| 15248 | .IP "\fB\-mam33\fR" 4 |
| 15249 | .IX Item "-mam33" |
| 15250 | Generate code using features specific to the \s-1AM33\s0 processor. |
| 15251 | .IP "\fB\-mno\-am33\fR" 4 |
| 15252 | .IX Item "-mno-am33" |
| 15253 | Do not generate code using features specific to the \s-1AM33\s0 processor. This |
| 15254 | is the default. |
| 15255 | .IP "\fB\-mam33\-2\fR" 4 |
| 15256 | .IX Item "-mam33-2" |
| 15257 | Generate code using features specific to the \s-1AM33/2\s0.0 processor. |
| 15258 | .IP "\fB\-mam34\fR" 4 |
| 15259 | .IX Item "-mam34" |
| 15260 | Generate code using features specific to the \s-1AM34\s0 processor. |
| 15261 | .IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 |
| 15262 | .IX Item "-mtune=cpu-type" |
| 15263 | Use the timing characteristics of the indicated \s-1CPU\s0 type when |
| 15264 | scheduling instructions. This does not change the targeted processor |
| 15265 | type. The \s-1CPU\s0 type must be one of \fBmn10300\fR, \fBam33\fR, |
| 15266 | \&\fBam33\-2\fR or \fBam34\fR. |
| 15267 | .IP "\fB\-mreturn\-pointer\-on\-d0\fR" 4 |
| 15268 | .IX Item "-mreturn-pointer-on-d0" |
| 15269 | When generating a function that returns a pointer, return the pointer |
| 15270 | in both \f(CW\*(C`a0\*(C'\fR and \f(CW\*(C`d0\*(C'\fR. Otherwise, the pointer is returned |
| 15271 | only in a0, and attempts to call such functions without a prototype |
| 15272 | would result in errors. Note that this option is on by default; use |
| 15273 | \&\fB\-mno\-return\-pointer\-on\-d0\fR to disable it. |
| 15274 | .IP "\fB\-mno\-crt0\fR" 4 |
| 15275 | .IX Item "-mno-crt0" |
| 15276 | Do not link in the C run-time initialization object file. |
| 15277 | .IP "\fB\-mrelax\fR" 4 |
| 15278 | .IX Item "-mrelax" |
| 15279 | Indicate to the linker that it should perform a relaxation optimization pass |
| 15280 | to shorten branches, calls and absolute memory addresses. This option only |
| 15281 | has an effect when used on the command line for the final link step. |
| 15282 | .Sp |
| 15283 | This option makes symbolic debugging impossible. |
| 15284 | .IP "\fB\-mliw\fR" 4 |
| 15285 | .IX Item "-mliw" |
| 15286 | Allow the compiler to generate \fILong Instruction Word\fR |
| 15287 | instructions if the target is the \fB\s-1AM33\s0\fR or later. This is the |
| 15288 | default. This option defines the preprocessor macro \fB_\|_LIW_\|_\fR. |
| 15289 | .IP "\fB\-mnoliw\fR" 4 |
| 15290 | .IX Item "-mnoliw" |
| 15291 | Do not allow the compiler to generate \fILong Instruction Word\fR |
| 15292 | instructions. This option defines the preprocessor macro |
| 15293 | \&\fB_\|_NO_LIW_\|_\fR. |
| 15294 | .IP "\fB\-msetlb\fR" 4 |
| 15295 | .IX Item "-msetlb" |
| 15296 | Allow the compiler to generate the \fI\s-1SETLB\s0\fR and \fILcc\fR |
| 15297 | instructions if the target is the \fB\s-1AM33\s0\fR or later. This is the |
| 15298 | default. This option defines the preprocessor macro \fB_\|_SETLB_\|_\fR. |
| 15299 | .IP "\fB\-mnosetlb\fR" 4 |
| 15300 | .IX Item "-mnosetlb" |
| 15301 | Do not allow the compiler to generate \fI\s-1SETLB\s0\fR or \fILcc\fR |
| 15302 | instructions. This option defines the preprocessor macro |
| 15303 | \&\fB_\|_NO_SETLB_\|_\fR. |
| 15304 | .PP |
| 15305 | \fI\s-1PDP\-11\s0 Options\fR |
| 15306 | .IX Subsection "PDP-11 Options" |
| 15307 | .PP |
| 15308 | These options are defined for the \s-1PDP\-11:\s0 |
| 15309 | .IP "\fB\-mfpu\fR" 4 |
| 15310 | .IX Item "-mfpu" |
| 15311 | Use hardware \s-1FPP\s0 floating point. This is the default. (\s-1FIS\s0 floating |
| 15312 | point on the \s-1PDP\-11/40\s0 is not supported.) |
| 15313 | .IP "\fB\-msoft\-float\fR" 4 |
| 15314 | .IX Item "-msoft-float" |
| 15315 | Do not use hardware floating point. |
| 15316 | .IP "\fB\-mac0\fR" 4 |
| 15317 | .IX Item "-mac0" |
| 15318 | Return floating-point results in ac0 (fr0 in Unix assembler syntax). |
| 15319 | .IP "\fB\-mno\-ac0\fR" 4 |
| 15320 | .IX Item "-mno-ac0" |
| 15321 | Return floating-point results in memory. This is the default. |
| 15322 | .IP "\fB\-m40\fR" 4 |
| 15323 | .IX Item "-m40" |
| 15324 | Generate code for a \s-1PDP\-11/40\s0. |
| 15325 | .IP "\fB\-m45\fR" 4 |
| 15326 | .IX Item "-m45" |
| 15327 | Generate code for a \s-1PDP\-11/45\s0. This is the default. |
| 15328 | .IP "\fB\-m10\fR" 4 |
| 15329 | .IX Item "-m10" |
| 15330 | Generate code for a \s-1PDP\-11/10\s0. |
| 15331 | .IP "\fB\-mbcopy\-builtin\fR" 4 |
| 15332 | .IX Item "-mbcopy-builtin" |
| 15333 | Use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory. This is the |
| 15334 | default. |
| 15335 | .IP "\fB\-mbcopy\fR" 4 |
| 15336 | .IX Item "-mbcopy" |
| 15337 | Do not use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory. |
| 15338 | .IP "\fB\-mint16\fR" 4 |
| 15339 | .IX Item "-mint16" |
| 15340 | .PD 0 |
| 15341 | .IP "\fB\-mno\-int32\fR" 4 |
| 15342 | .IX Item "-mno-int32" |
| 15343 | .PD |
| 15344 | Use 16\-bit \f(CW\*(C`int\*(C'\fR. This is the default. |
| 15345 | .IP "\fB\-mint32\fR" 4 |
| 15346 | .IX Item "-mint32" |
| 15347 | .PD 0 |
| 15348 | .IP "\fB\-mno\-int16\fR" 4 |
| 15349 | .IX Item "-mno-int16" |
| 15350 | .PD |
| 15351 | Use 32\-bit \f(CW\*(C`int\*(C'\fR. |
| 15352 | .IP "\fB\-mfloat64\fR" 4 |
| 15353 | .IX Item "-mfloat64" |
| 15354 | .PD 0 |
| 15355 | .IP "\fB\-mno\-float32\fR" 4 |
| 15356 | .IX Item "-mno-float32" |
| 15357 | .PD |
| 15358 | Use 64\-bit \f(CW\*(C`float\*(C'\fR. This is the default. |
| 15359 | .IP "\fB\-mfloat32\fR" 4 |
| 15360 | .IX Item "-mfloat32" |
| 15361 | .PD 0 |
| 15362 | .IP "\fB\-mno\-float64\fR" 4 |
| 15363 | .IX Item "-mno-float64" |
| 15364 | .PD |
| 15365 | Use 32\-bit \f(CW\*(C`float\*(C'\fR. |
| 15366 | .IP "\fB\-mabshi\fR" 4 |
| 15367 | .IX Item "-mabshi" |
| 15368 | Use \f(CW\*(C`abshi2\*(C'\fR pattern. This is the default. |
| 15369 | .IP "\fB\-mno\-abshi\fR" 4 |
| 15370 | .IX Item "-mno-abshi" |
| 15371 | Do not use \f(CW\*(C`abshi2\*(C'\fR pattern. |
| 15372 | .IP "\fB\-mbranch\-expensive\fR" 4 |
| 15373 | .IX Item "-mbranch-expensive" |
| 15374 | Pretend that branches are expensive. This is for experimenting with |
| 15375 | code generation only. |
| 15376 | .IP "\fB\-mbranch\-cheap\fR" 4 |
| 15377 | .IX Item "-mbranch-cheap" |
| 15378 | Do not pretend that branches are expensive. This is the default. |
| 15379 | .IP "\fB\-munix\-asm\fR" 4 |
| 15380 | .IX Item "-munix-asm" |
| 15381 | Use Unix assembler syntax. This is the default when configured for |
| 15382 | \&\fBpdp11\-*\-bsd\fR. |
| 15383 | .IP "\fB\-mdec\-asm\fR" 4 |
| 15384 | .IX Item "-mdec-asm" |
| 15385 | Use \s-1DEC\s0 assembler syntax. This is the default when configured for any |
| 15386 | \&\s-1PDP\-11\s0 target other than \fBpdp11\-*\-bsd\fR. |
| 15387 | .PP |
| 15388 | \fIpicoChip Options\fR |
| 15389 | .IX Subsection "picoChip Options" |
| 15390 | .PP |
| 15391 | These \fB\-m\fR options are defined for picoChip implementations: |
| 15392 | .IP "\fB\-mae=\fR\fIae_type\fR" 4 |
| 15393 | .IX Item "-mae=ae_type" |
| 15394 | Set the instruction set, register set, and instruction scheduling |
| 15395 | parameters for array element type \fIae_type\fR. Supported values |
| 15396 | for \fIae_type\fR are \fB\s-1ANY\s0\fR, \fB\s-1MUL\s0\fR, and \fB\s-1MAC\s0\fR. |
| 15397 | .Sp |
| 15398 | \&\fB\-mae=ANY\fR selects a completely generic \s-1AE\s0 type. Code |
| 15399 | generated with this option will run on any of the other \s-1AE\s0 types. The |
| 15400 | code will not be as efficient as it would be if compiled for a specific |
| 15401 | \&\s-1AE\s0 type, and some types of operation (e.g., multiplication) will not |
| 15402 | work properly on all types of \s-1AE\s0. |
| 15403 | .Sp |
| 15404 | \&\fB\-mae=MUL\fR selects a \s-1MUL\s0 \s-1AE\s0 type. This is the most useful \s-1AE\s0 type |
| 15405 | for compiled code, and is the default. |
| 15406 | .Sp |
| 15407 | \&\fB\-mae=MAC\fR selects a DSP-style \s-1MAC\s0 \s-1AE\s0. Code compiled with this |
| 15408 | option may suffer from poor performance of byte (char) manipulation, |
| 15409 | since the \s-1DSP\s0 \s-1AE\s0 does not provide hardware support for byte load/stores. |
| 15410 | .IP "\fB\-msymbol\-as\-address\fR" 4 |
| 15411 | .IX Item "-msymbol-as-address" |
| 15412 | Enable the compiler to directly use a symbol name as an address in a |
| 15413 | load/store instruction, without first loading it into a |
| 15414 | register. Typically, the use of this option will generate larger |
| 15415 | programs, which run faster than when the option isn't used. However, the |
| 15416 | results vary from program to program, so it is left as a user option, |
| 15417 | rather than being permanently enabled. |
| 15418 | .IP "\fB\-mno\-inefficient\-warnings\fR" 4 |
| 15419 | .IX Item "-mno-inefficient-warnings" |
| 15420 | Disables warnings about the generation of inefficient code. These |
| 15421 | warnings can be generated, for example, when compiling code that |
| 15422 | performs byte-level memory operations on the \s-1MAC\s0 \s-1AE\s0 type. The \s-1MAC\s0 \s-1AE\s0 has |
| 15423 | no hardware support for byte-level memory operations, so all byte |
| 15424 | load/stores must be synthesized from word load/store operations. This is |
| 15425 | inefficient and a warning will be generated indicating to the programmer |
| 15426 | that they should rewrite the code to avoid byte operations, or to target |
| 15427 | an \s-1AE\s0 type that has the necessary hardware support. This option enables |
| 15428 | the warning to be turned off. |
| 15429 | .PP |
| 15430 | \fIPowerPC Options\fR |
| 15431 | .IX Subsection "PowerPC Options" |
| 15432 | .PP |
| 15433 | These are listed under |
| 15434 | .PP |
| 15435 | \fI\s-1RL78\s0 Options\fR |
| 15436 | .IX Subsection "RL78 Options" |
| 15437 | .IP "\fB\-msim\fR" 4 |
| 15438 | .IX Item "-msim" |
| 15439 | Links in additional target libraries to support operation within a |
| 15440 | simulator. |
| 15441 | .IP "\fB\-mmul=none\fR" 4 |
| 15442 | .IX Item "-mmul=none" |
| 15443 | .PD 0 |
| 15444 | .IP "\fB\-mmul=g13\fR" 4 |
| 15445 | .IX Item "-mmul=g13" |
| 15446 | .IP "\fB\-mmul=rl78\fR" 4 |
| 15447 | .IX Item "-mmul=rl78" |
| 15448 | .PD |
| 15449 | Specifies the type of hardware multiplication support to be used. The |
| 15450 | default is \f(CW\*(C`none\*(C'\fR, which uses software multiplication functions. |
| 15451 | The \f(CW\*(C`g13\*(C'\fR option is for the hardware multiply/divide peripheral |
| 15452 | only on the \s-1RL78/G13\s0 targets. The \f(CW\*(C`rl78\*(C'\fR option is for the |
| 15453 | standard hardware multiplication defined in the \s-1RL78\s0 software manual. |
| 15454 | .PP |
| 15455 | \fI\s-1IBM\s0 \s-1RS/6000\s0 and PowerPC Options\fR |
| 15456 | .IX Subsection "IBM RS/6000 and PowerPC Options" |
| 15457 | .PP |
| 15458 | These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerPC: |
| 15459 | .IP "\fB\-mpower\fR" 4 |
| 15460 | .IX Item "-mpower" |
| 15461 | .PD 0 |
| 15462 | .IP "\fB\-mno\-power\fR" 4 |
| 15463 | .IX Item "-mno-power" |
| 15464 | .IP "\fB\-mpower2\fR" 4 |
| 15465 | .IX Item "-mpower2" |
| 15466 | .IP "\fB\-mno\-power2\fR" 4 |
| 15467 | .IX Item "-mno-power2" |
| 15468 | .IP "\fB\-mpowerpc\fR" 4 |
| 15469 | .IX Item "-mpowerpc" |
| 15470 | .IP "\fB\-mno\-powerpc\fR" 4 |
| 15471 | .IX Item "-mno-powerpc" |
| 15472 | .IP "\fB\-mpowerpc\-gpopt\fR" 4 |
| 15473 | .IX Item "-mpowerpc-gpopt" |
| 15474 | .IP "\fB\-mno\-powerpc\-gpopt\fR" 4 |
| 15475 | .IX Item "-mno-powerpc-gpopt" |
| 15476 | .IP "\fB\-mpowerpc\-gfxopt\fR" 4 |
| 15477 | .IX Item "-mpowerpc-gfxopt" |
| 15478 | .IP "\fB\-mno\-powerpc\-gfxopt\fR" 4 |
| 15479 | .IX Item "-mno-powerpc-gfxopt" |
| 15480 | .IP "\fB\-mpowerpc64\fR" 4 |
| 15481 | .IX Item "-mpowerpc64" |
| 15482 | .IP "\fB\-mno\-powerpc64\fR" 4 |
| 15483 | .IX Item "-mno-powerpc64" |
| 15484 | .IP "\fB\-mmfcrf\fR" 4 |
| 15485 | .IX Item "-mmfcrf" |
| 15486 | .IP "\fB\-mno\-mfcrf\fR" 4 |
| 15487 | .IX Item "-mno-mfcrf" |
| 15488 | .IP "\fB\-mpopcntb\fR" 4 |
| 15489 | .IX Item "-mpopcntb" |
| 15490 | .IP "\fB\-mno\-popcntb\fR" 4 |
| 15491 | .IX Item "-mno-popcntb" |
| 15492 | .IP "\fB\-mpopcntd\fR" 4 |
| 15493 | .IX Item "-mpopcntd" |
| 15494 | .IP "\fB\-mno\-popcntd\fR" 4 |
| 15495 | .IX Item "-mno-popcntd" |
| 15496 | .IP "\fB\-mfprnd\fR" 4 |
| 15497 | .IX Item "-mfprnd" |
| 15498 | .IP "\fB\-mno\-fprnd\fR" 4 |
| 15499 | .IX Item "-mno-fprnd" |
| 15500 | .IP "\fB\-mcmpb\fR" 4 |
| 15501 | .IX Item "-mcmpb" |
| 15502 | .IP "\fB\-mno\-cmpb\fR" 4 |
| 15503 | .IX Item "-mno-cmpb" |
| 15504 | .IP "\fB\-mmfpgpr\fR" 4 |
| 15505 | .IX Item "-mmfpgpr" |
| 15506 | .IP "\fB\-mno\-mfpgpr\fR" 4 |
| 15507 | .IX Item "-mno-mfpgpr" |
| 15508 | .IP "\fB\-mhard\-dfp\fR" 4 |
| 15509 | .IX Item "-mhard-dfp" |
| 15510 | .IP "\fB\-mno\-hard\-dfp\fR" 4 |
| 15511 | .IX Item "-mno-hard-dfp" |
| 15512 | .PD |
| 15513 | \&\s-1GCC\s0 supports two related instruction set architectures for the |
| 15514 | \&\s-1RS/6000\s0 and PowerPC. The \fI\s-1POWER\s0\fR instruction set are those |
| 15515 | instructions supported by the \fBrios\fR chip set used in the original |
| 15516 | \&\s-1RS/6000\s0 systems and the \fIPowerPC\fR instruction set is the |
| 15517 | architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and |
| 15518 | the \s-1IBM\s0 4xx, 6xx, and follow-on microprocessors. |
| 15519 | .Sp |
| 15520 | Neither architecture is a subset of the other. However there is a |
| 15521 | large common subset of instructions supported by both. An \s-1MQ\s0 |
| 15522 | register is included in processors supporting the \s-1POWER\s0 architecture. |
| 15523 | .Sp |
| 15524 | You use these options to specify which instructions are available on the |
| 15525 | processor you are using. The default value of these options is |
| 15526 | determined when configuring \s-1GCC\s0. Specifying the |
| 15527 | \&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these |
| 15528 | options. We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option |
| 15529 | rather than the options listed above. |
| 15530 | .Sp |
| 15531 | The \fB\-mpower\fR option allows \s-1GCC\s0 to generate instructions that |
| 15532 | are found only in the \s-1POWER\s0 architecture and to use the \s-1MQ\s0 register. |
| 15533 | Specifying \fB\-mpower2\fR implies \fB\-power\fR and also allows \s-1GCC\s0 |
| 15534 | to generate instructions that are present in the \s-1POWER2\s0 architecture but |
| 15535 | not the original \s-1POWER\s0 architecture. |
| 15536 | .Sp |
| 15537 | The \fB\-mpowerpc\fR option allows \s-1GCC\s0 to generate instructions that |
| 15538 | are found only in the 32\-bit subset of the PowerPC architecture. |
| 15539 | Specifying \fB\-mpowerpc\-gpopt\fR implies \fB\-mpowerpc\fR and also allows |
| 15540 | \&\s-1GCC\s0 to use the optional PowerPC architecture instructions in the |
| 15541 | General Purpose group, including floating-point square root. Specifying |
| 15542 | \&\fB\-mpowerpc\-gfxopt\fR implies \fB\-mpowerpc\fR and also allows \s-1GCC\s0 to |
| 15543 | use the optional PowerPC architecture instructions in the Graphics |
| 15544 | group, including floating-point select. |
| 15545 | .Sp |
| 15546 | The \fB\-mmfcrf\fR option allows \s-1GCC\s0 to generate the move from |
| 15547 | condition register field instruction implemented on the \s-1POWER4\s0 |
| 15548 | processor and other processors that support the PowerPC V2.01 |
| 15549 | architecture. |
| 15550 | The \fB\-mpopcntb\fR option allows \s-1GCC\s0 to generate the popcount and |
| 15551 | double-precision \s-1FP\s0 reciprocal estimate instruction implemented on the |
| 15552 | \&\s-1POWER5\s0 processor and other processors that support the PowerPC V2.02 |
| 15553 | architecture. |
| 15554 | The \fB\-mpopcntd\fR option allows \s-1GCC\s0 to generate the popcount |
| 15555 | instruction implemented on the \s-1POWER7\s0 processor and other processors |
| 15556 | that support the PowerPC V2.06 architecture. |
| 15557 | The \fB\-mfprnd\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 round to |
| 15558 | integer instructions implemented on the \s-1POWER5+\s0 processor and other |
| 15559 | processors that support the PowerPC V2.03 architecture. |
| 15560 | The \fB\-mcmpb\fR option allows \s-1GCC\s0 to generate the compare bytes |
| 15561 | instruction implemented on the \s-1POWER6\s0 processor and other processors |
| 15562 | that support the PowerPC V2.05 architecture. |
| 15563 | The \fB\-mmfpgpr\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 move to/from |
| 15564 | general-purpose register instructions implemented on the \s-1POWER6X\s0 |
| 15565 | processor and other processors that support the extended PowerPC V2.05 |
| 15566 | architecture. |
| 15567 | The \fB\-mhard\-dfp\fR option allows \s-1GCC\s0 to generate the decimal |
| 15568 | floating-point instructions implemented on some \s-1POWER\s0 processors. |
| 15569 | .Sp |
| 15570 | The \fB\-mpowerpc64\fR option allows \s-1GCC\s0 to generate the additional |
| 15571 | 64\-bit instructions that are found in the full PowerPC64 architecture |
| 15572 | and to treat GPRs as 64\-bit, doubleword quantities. \s-1GCC\s0 defaults to |
| 15573 | \&\fB\-mno\-powerpc64\fR. |
| 15574 | .Sp |
| 15575 | If you specify both \fB\-mno\-power\fR and \fB\-mno\-powerpc\fR, \s-1GCC\s0 |
| 15576 | will use only the instructions in the common subset of both |
| 15577 | architectures plus some special \s-1AIX\s0 common-mode calls, and will not use |
| 15578 | the \s-1MQ\s0 register. Specifying both \fB\-mpower\fR and \fB\-mpowerpc\fR |
| 15579 | permits \s-1GCC\s0 to use any instruction from either architecture and to |
| 15580 | allow use of the \s-1MQ\s0 register; specify this for the Motorola \s-1MPC601\s0. |
| 15581 | .IP "\fB\-mnew\-mnemonics\fR" 4 |
| 15582 | .IX Item "-mnew-mnemonics" |
| 15583 | .PD 0 |
| 15584 | .IP "\fB\-mold\-mnemonics\fR" 4 |
| 15585 | .IX Item "-mold-mnemonics" |
| 15586 | .PD |
| 15587 | Select which mnemonics to use in the generated assembler code. With |
| 15588 | \&\fB\-mnew\-mnemonics\fR, \s-1GCC\s0 uses the assembler mnemonics defined for |
| 15589 | the PowerPC architecture. With \fB\-mold\-mnemonics\fR it uses the |
| 15590 | assembler mnemonics defined for the \s-1POWER\s0 architecture. Instructions |
| 15591 | defined in only one architecture have only one mnemonic; \s-1GCC\s0 uses that |
| 15592 | mnemonic irrespective of which of these options is specified. |
| 15593 | .Sp |
| 15594 | \&\s-1GCC\s0 defaults to the mnemonics appropriate for the architecture in |
| 15595 | use. Specifying \fB\-mcpu=\fR\fIcpu_type\fR sometimes overrides the |
| 15596 | value of these option. Unless you are building a cross-compiler, you |
| 15597 | should normally not specify either \fB\-mnew\-mnemonics\fR or |
| 15598 | \&\fB\-mold\-mnemonics\fR, but should instead accept the default. |
| 15599 | .IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 |
| 15600 | .IX Item "-mcpu=cpu_type" |
| 15601 | Set architecture type, register usage, choice of mnemonics, and |
| 15602 | instruction scheduling parameters for machine type \fIcpu_type\fR. |
| 15603 | Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR, |
| 15604 | \&\fB405\fR, \fB405fp\fR, \fB440\fR, \fB440fp\fR, \fB464\fR, \fB464fp\fR, |
| 15605 | \&\fB476\fR, \fB476fp\fR, \fB505\fR, \fB601\fR, \fB602\fR, \fB603\fR, |
| 15606 | \&\fB603e\fR, \fB604\fR, \fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR, |
| 15607 | \&\fB7400\fR, \fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR, |
| 15608 | \&\fB860\fR, \fB970\fR, \fB8540\fR, \fBa2\fR, \fBe300c2\fR, |
| 15609 | \&\fBe300c3\fR, \fBe500mc\fR, \fBe500mc64\fR, \fBec603e\fR, \fBG3\fR, |
| 15610 | \&\fBG4\fR, \fBG5\fR, \fBtitan\fR, \fBpower\fR, \fBpower2\fR, \fBpower3\fR, |
| 15611 | \&\fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, \fBpower6\fR, \fBpower6x\fR, |
| 15612 | \&\fBpower7\fR, \fBcommon\fR, \fBpowerpc\fR, \fBpowerpc64\fR, \fBrios\fR, |
| 15613 | \&\fBrios1\fR, \fBrios2\fR, \fBrsc\fR, and \fBrs64\fR. |
| 15614 | .Sp |
| 15615 | \&\fB\-mcpu=common\fR selects a completely generic processor. Code |
| 15616 | generated under this option will run on any \s-1POWER\s0 or PowerPC processor. |
| 15617 | \&\s-1GCC\s0 will use only the instructions in the common subset of both |
| 15618 | architectures, and will not use the \s-1MQ\s0 register. \s-1GCC\s0 assumes a generic |
| 15619 | processor model for scheduling purposes. |
| 15620 | .Sp |
| 15621 | \&\fB\-mcpu=power\fR, \fB\-mcpu=power2\fR, \fB\-mcpu=powerpc\fR, and |
| 15622 | \&\fB\-mcpu=powerpc64\fR specify generic \s-1POWER\s0, \s-1POWER2\s0, pure 32\-bit |
| 15623 | PowerPC (i.e., not \s-1MPC601\s0), and 64\-bit PowerPC architecture machine |
| 15624 | types, with an appropriate, generic processor model assumed for |
| 15625 | scheduling purposes. |
| 15626 | .Sp |
| 15627 | The other options specify a specific processor. Code generated under |
| 15628 | those options will run best on that processor, and may not run at all on |
| 15629 | others. |
| 15630 | .Sp |
| 15631 | The \fB\-mcpu\fR options automatically enable or disable the |
| 15632 | following options: |
| 15633 | .Sp |
| 15634 | \&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple |
| 15635 | \&\-mnew\-mnemonics \-mpopcntb \-mpopcntd \-mpower \-mpower2 \-mpowerpc64 |
| 15636 | \&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float |
| 15637 | \&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx\fR |
| 15638 | .Sp |
| 15639 | The particular options set for any particular \s-1CPU\s0 will vary between |
| 15640 | compiler versions, depending on what setting seems to produce optimal |
| 15641 | code for that \s-1CPU\s0; it doesn't necessarily reflect the actual hardware's |
| 15642 | capabilities. If you wish to set an individual option to a particular |
| 15643 | value, you may specify it after the \fB\-mcpu\fR option, like |
| 15644 | \&\fB\-mcpu=970 \-mno\-altivec\fR. |
| 15645 | .Sp |
| 15646 | On \s-1AIX\s0, the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are |
| 15647 | not enabled or disabled by the \fB\-mcpu\fR option at present because |
| 15648 | \&\s-1AIX\s0 does not have full support for these options. You may still |
| 15649 | enable or disable them individually if you're sure it'll work in your |
| 15650 | environment. |
| 15651 | .IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 |
| 15652 | .IX Item "-mtune=cpu_type" |
| 15653 | Set the instruction scheduling parameters for machine type |
| 15654 | \&\fIcpu_type\fR, but do not set the architecture type, register usage, or |
| 15655 | choice of mnemonics, as \fB\-mcpu=\fR\fIcpu_type\fR would. The same |
| 15656 | values for \fIcpu_type\fR are used for \fB\-mtune\fR as for |
| 15657 | \&\fB\-mcpu\fR. If both are specified, the code generated will use the |
| 15658 | architecture, registers, and mnemonics set by \fB\-mcpu\fR, but the |
| 15659 | scheduling parameters set by \fB\-mtune\fR. |
| 15660 | .IP "\fB\-mcmodel=small\fR" 4 |
| 15661 | .IX Item "-mcmodel=small" |
| 15662 | Generate PowerPC64 code for the small model: The \s-1TOC\s0 is limited to |
| 15663 | 64k. |
| 15664 | .IP "\fB\-mcmodel=medium\fR" 4 |
| 15665 | .IX Item "-mcmodel=medium" |
| 15666 | Generate PowerPC64 code for the medium model: The \s-1TOC\s0 and other static |
| 15667 | data may be up to a total of 4G in size. |
| 15668 | .IP "\fB\-mcmodel=large\fR" 4 |
| 15669 | .IX Item "-mcmodel=large" |
| 15670 | Generate PowerPC64 code for the large model: The \s-1TOC\s0 may be up to 4G |
| 15671 | in size. Other data and code is only limited by the 64\-bit address |
| 15672 | space. |
| 15673 | .IP "\fB\-maltivec\fR" 4 |
| 15674 | .IX Item "-maltivec" |
| 15675 | .PD 0 |
| 15676 | .IP "\fB\-mno\-altivec\fR" 4 |
| 15677 | .IX Item "-mno-altivec" |
| 15678 | .PD |
| 15679 | Generate code that uses (does not use) AltiVec instructions, and also |
| 15680 | enable the use of built-in functions that allow more direct access to |
| 15681 | the AltiVec instruction set. You may also need to set |
| 15682 | \&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 |
| 15683 | enhancements. |
| 15684 | .IP "\fB\-mvrsave\fR" 4 |
| 15685 | .IX Item "-mvrsave" |
| 15686 | .PD 0 |
| 15687 | .IP "\fB\-mno\-vrsave\fR" 4 |
| 15688 | .IX Item "-mno-vrsave" |
| 15689 | .PD |
| 15690 | Generate \s-1VRSAVE\s0 instructions when generating AltiVec code. |
| 15691 | .IP "\fB\-mgen\-cell\-microcode\fR" 4 |
| 15692 | .IX Item "-mgen-cell-microcode" |
| 15693 | Generate Cell microcode instructions |
| 15694 | .IP "\fB\-mwarn\-cell\-microcode\fR" 4 |
| 15695 | .IX Item "-mwarn-cell-microcode" |
| 15696 | Warning when a Cell microcode instruction is going to emitted. An example |
| 15697 | of a Cell microcode instruction is a variable shift. |
| 15698 | .IP "\fB\-msecure\-plt\fR" 4 |
| 15699 | .IX Item "-msecure-plt" |
| 15700 | Generate code that allows ld and ld.so to build executables and shared |
| 15701 | libraries with non-exec .plt and .got sections. This is a PowerPC |
| 15702 | 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. |
| 15703 | .IP "\fB\-mbss\-plt\fR" 4 |
| 15704 | .IX Item "-mbss-plt" |
| 15705 | Generate code that uses a \s-1BSS\s0 .plt section that ld.so fills in, and |
| 15706 | requires .plt and .got sections that are both writable and executable. |
| 15707 | This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. |
| 15708 | .IP "\fB\-misel\fR" 4 |
| 15709 | .IX Item "-misel" |
| 15710 | .PD 0 |
| 15711 | .IP "\fB\-mno\-isel\fR" 4 |
| 15712 | .IX Item "-mno-isel" |
| 15713 | .PD |
| 15714 | This switch enables or disables the generation of \s-1ISEL\s0 instructions. |
| 15715 | .IP "\fB\-misel=\fR\fIyes/no\fR" 4 |
| 15716 | .IX Item "-misel=yes/no" |
| 15717 | This switch has been deprecated. Use \fB\-misel\fR and |
| 15718 | \&\fB\-mno\-isel\fR instead. |
| 15719 | .IP "\fB\-mspe\fR" 4 |
| 15720 | .IX Item "-mspe" |
| 15721 | .PD 0 |
| 15722 | .IP "\fB\-mno\-spe\fR" 4 |
| 15723 | .IX Item "-mno-spe" |
| 15724 | .PD |
| 15725 | This switch enables or disables the generation of \s-1SPE\s0 simd |
| 15726 | instructions. |
| 15727 | .IP "\fB\-mpaired\fR" 4 |
| 15728 | .IX Item "-mpaired" |
| 15729 | .PD 0 |
| 15730 | .IP "\fB\-mno\-paired\fR" 4 |
| 15731 | .IX Item "-mno-paired" |
| 15732 | .PD |
| 15733 | This switch enables or disables the generation of \s-1PAIRED\s0 simd |
| 15734 | instructions. |
| 15735 | .IP "\fB\-mspe=\fR\fIyes/no\fR" 4 |
| 15736 | .IX Item "-mspe=yes/no" |
| 15737 | This option has been deprecated. Use \fB\-mspe\fR and |
| 15738 | \&\fB\-mno\-spe\fR instead. |
| 15739 | .IP "\fB\-mvsx\fR" 4 |
| 15740 | .IX Item "-mvsx" |
| 15741 | .PD 0 |
| 15742 | .IP "\fB\-mno\-vsx\fR" 4 |
| 15743 | .IX Item "-mno-vsx" |
| 15744 | .PD |
| 15745 | Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) |
| 15746 | instructions, and also enable the use of built-in functions that allow |
| 15747 | more direct access to the \s-1VSX\s0 instruction set. |
| 15748 | .IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4 |
| 15749 | .IX Item "-mfloat-gprs=yes/single/double/no" |
| 15750 | .PD 0 |
| 15751 | .IP "\fB\-mfloat\-gprs\fR" 4 |
| 15752 | .IX Item "-mfloat-gprs" |
| 15753 | .PD |
| 15754 | This switch enables or disables the generation of floating-point |
| 15755 | operations on the general-purpose registers for architectures that |
| 15756 | support it. |
| 15757 | .Sp |
| 15758 | The argument \fIyes\fR or \fIsingle\fR enables the use of |
| 15759 | single-precision floating-point operations. |
| 15760 | .Sp |
| 15761 | The argument \fIdouble\fR enables the use of single and |
| 15762 | double-precision floating-point operations. |
| 15763 | .Sp |
| 15764 | The argument \fIno\fR disables floating-point operations on the |
| 15765 | general-purpose registers. |
| 15766 | .Sp |
| 15767 | This option is currently only available on the MPC854x. |
| 15768 | .IP "\fB\-m32\fR" 4 |
| 15769 | .IX Item "-m32" |
| 15770 | .PD 0 |
| 15771 | .IP "\fB\-m64\fR" 4 |
| 15772 | .IX Item "-m64" |
| 15773 | .PD |
| 15774 | Generate code for 32\-bit or 64\-bit environments of Darwin and \s-1SVR4\s0 |
| 15775 | targets (including GNU/Linux). The 32\-bit environment sets int, long |
| 15776 | and pointer to 32 bits and generates code that runs on any PowerPC |
| 15777 | variant. The 64\-bit environment sets int to 32 bits and long and |
| 15778 | pointer to 64 bits, and generates code for PowerPC64, as for |
| 15779 | \&\fB\-mpowerpc64\fR. |
| 15780 | .IP "\fB\-mfull\-toc\fR" 4 |
| 15781 | .IX Item "-mfull-toc" |
| 15782 | .PD 0 |
| 15783 | .IP "\fB\-mno\-fp\-in\-toc\fR" 4 |
| 15784 | .IX Item "-mno-fp-in-toc" |
| 15785 | .IP "\fB\-mno\-sum\-in\-toc\fR" 4 |
| 15786 | .IX Item "-mno-sum-in-toc" |
| 15787 | .IP "\fB\-mminimal\-toc\fR" 4 |
| 15788 | .IX Item "-mminimal-toc" |
| 15789 | .PD |
| 15790 | Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for |
| 15791 | every executable file. The \fB\-mfull\-toc\fR option is selected by |
| 15792 | default. In that case, \s-1GCC\s0 will allocate at least one \s-1TOC\s0 entry for |
| 15793 | each unique non-automatic variable reference in your program. \s-1GCC\s0 |
| 15794 | will also place floating-point constants in the \s-1TOC\s0. However, only |
| 15795 | 16,384 entries are available in the \s-1TOC\s0. |
| 15796 | .Sp |
| 15797 | If you receive a linker error message that saying you have overflowed |
| 15798 | the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used |
| 15799 | with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options. |
| 15800 | \&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point |
| 15801 | constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to |
| 15802 | generate code to calculate the sum of an address and a constant at |
| 15803 | run time instead of putting that sum into the \s-1TOC\s0. You may specify one |
| 15804 | or both of these options. Each causes \s-1GCC\s0 to produce very slightly |
| 15805 | slower and larger code at the expense of conserving \s-1TOC\s0 space. |
| 15806 | .Sp |
| 15807 | If you still run out of space in the \s-1TOC\s0 even when you specify both of |
| 15808 | these options, specify \fB\-mminimal\-toc\fR instead. This option causes |
| 15809 | \&\s-1GCC\s0 to make only one \s-1TOC\s0 entry for every file. When you specify this |
| 15810 | option, \s-1GCC\s0 will produce code that is slower and larger but which |
| 15811 | uses extremely little \s-1TOC\s0 space. You may wish to use this option |
| 15812 | only on files that contain less frequently executed code. |
| 15813 | .IP "\fB\-maix64\fR" 4 |
| 15814 | .IX Item "-maix64" |
| 15815 | .PD 0 |
| 15816 | .IP "\fB\-maix32\fR" 4 |
| 15817 | .IX Item "-maix32" |
| 15818 | .PD |
| 15819 | Enable 64\-bit \s-1AIX\s0 \s-1ABI\s0 and calling convention: 64\-bit pointers, 64\-bit |
| 15820 | \&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them. |
| 15821 | Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR and |
| 15822 | \&\fB\-mpowerpc\fR, while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and |
| 15823 | implies \fB\-mno\-powerpc64\fR. \s-1GCC\s0 defaults to \fB\-maix32\fR. |
| 15824 | .IP "\fB\-mxl\-compat\fR" 4 |
| 15825 | .IX Item "-mxl-compat" |
| 15826 | .PD 0 |
| 15827 | .IP "\fB\-mno\-xl\-compat\fR" 4 |
| 15828 | .IX Item "-mno-xl-compat" |
| 15829 | .PD |
| 15830 | Produce code that conforms more closely to \s-1IBM\s0 \s-1XL\s0 compiler semantics |
| 15831 | when using AIX-compatible \s-1ABI\s0. Pass floating-point arguments to |
| 15832 | prototyped functions beyond the register save area (\s-1RSA\s0) on the stack |
| 15833 | in addition to argument FPRs. Do not assume that most significant |
| 15834 | double in 128\-bit long double value is properly rounded when comparing |
| 15835 | values and converting to double. Use \s-1XL\s0 symbol names for long double |
| 15836 | support routines. |
| 15837 | .Sp |
| 15838 | The \s-1AIX\s0 calling convention was extended but not initially documented to |
| 15839 | handle an obscure K&R C case of calling a function that takes the |
| 15840 | address of its arguments with fewer arguments than declared. \s-1IBM\s0 \s-1XL\s0 |
| 15841 | compilers access floating-point arguments that do not fit in the |
| 15842 | \&\s-1RSA\s0 from the stack when a subroutine is compiled without |
| 15843 | optimization. Because always storing floating-point arguments on the |
| 15844 | stack is inefficient and rarely needed, this option is not enabled by |
| 15845 | default and only is necessary when calling subroutines compiled by \s-1IBM\s0 |
| 15846 | \&\s-1XL\s0 compilers without optimization. |
| 15847 | .IP "\fB\-mpe\fR" 4 |
| 15848 | .IX Item "-mpe" |
| 15849 | Support \fI\s-1IBM\s0 \s-1RS/6000\s0 \s-1SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0). Link an |
| 15850 | application written to use message passing with special startup code to |
| 15851 | enable the application to run. The system must have \s-1PE\s0 installed in the |
| 15852 | standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file |
| 15853 | must be overridden with the \fB\-specs=\fR option to specify the |
| 15854 | appropriate directory location. The Parallel Environment does not |
| 15855 | support threads, so the \fB\-mpe\fR option and the \fB\-pthread\fR |
| 15856 | option are incompatible. |
| 15857 | .IP "\fB\-malign\-natural\fR" 4 |
| 15858 | .IX Item "-malign-natural" |
| 15859 | .PD 0 |
| 15860 | .IP "\fB\-malign\-power\fR" 4 |
| 15861 | .IX Item "-malign-power" |
| 15862 | .PD |
| 15863 | On \s-1AIX\s0, 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option |
| 15864 | \&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger |
| 15865 | types, such as floating-point doubles, on their natural size-based boundary. |
| 15866 | The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified |
| 15867 | alignment rules. \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI\s0. |
| 15868 | .Sp |
| 15869 | On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR |
| 15870 | is not supported. |
| 15871 | .IP "\fB\-msoft\-float\fR" 4 |
| 15872 | .IX Item "-msoft-float" |
| 15873 | .PD 0 |
| 15874 | .IP "\fB\-mhard\-float\fR" 4 |
| 15875 | .IX Item "-mhard-float" |
| 15876 | .PD |
| 15877 | Generate code that does not use (uses) the floating-point register set. |
| 15878 | Software floating-point emulation is provided if you use the |
| 15879 | \&\fB\-msoft\-float\fR option, and pass the option to \s-1GCC\s0 when linking. |
| 15880 | .IP "\fB\-msingle\-float\fR" 4 |
| 15881 | .IX Item "-msingle-float" |
| 15882 | .PD 0 |
| 15883 | .IP "\fB\-mdouble\-float\fR" 4 |
| 15884 | .IX Item "-mdouble-float" |
| 15885 | .PD |
| 15886 | Generate code for single\- or double-precision floating-point operations. |
| 15887 | \&\fB\-mdouble\-float\fR implies \fB\-msingle\-float\fR. |
| 15888 | .IP "\fB\-msimple\-fpu\fR" 4 |
| 15889 | .IX Item "-msimple-fpu" |
| 15890 | Do not generate sqrt and div instructions for hardware floating-point unit. |
| 15891 | .IP "\fB\-mfpu\fR" 4 |
| 15892 | .IX Item "-mfpu" |
| 15893 | Specify type of floating-point unit. Valid values are \fIsp_lite\fR |
| 15894 | (equivalent to \-msingle\-float \-msimple\-fpu), \fIdp_lite\fR (equivalent |
| 15895 | to \-mdouble\-float \-msimple\-fpu), \fIsp_full\fR (equivalent to \-msingle\-float), |
| 15896 | and \fIdp_full\fR (equivalent to \-mdouble\-float). |
| 15897 | .IP "\fB\-mxilinx\-fpu\fR" 4 |
| 15898 | .IX Item "-mxilinx-fpu" |
| 15899 | Perform optimizations for the floating-point unit on Xilinx \s-1PPC\s0 405/440. |
| 15900 | .IP "\fB\-mmultiple\fR" 4 |
| 15901 | .IX Item "-mmultiple" |
| 15902 | .PD 0 |
| 15903 | .IP "\fB\-mno\-multiple\fR" 4 |
| 15904 | .IX Item "-mno-multiple" |
| 15905 | .PD |
| 15906 | Generate code that uses (does not use) the load multiple word |
| 15907 | instructions and the store multiple word instructions. These |
| 15908 | instructions are generated by default on \s-1POWER\s0 systems, and not |
| 15909 | generated on PowerPC systems. Do not use \fB\-mmultiple\fR on little-endian |
| 15910 | PowerPC systems, since those instructions do not work when the |
| 15911 | processor is in little-endian mode. The exceptions are \s-1PPC740\s0 and |
| 15912 | \&\s-1PPC750\s0 which permit these instructions in little-endian mode. |
| 15913 | .IP "\fB\-mstring\fR" 4 |
| 15914 | .IX Item "-mstring" |
| 15915 | .PD 0 |
| 15916 | .IP "\fB\-mno\-string\fR" 4 |
| 15917 | .IX Item "-mno-string" |
| 15918 | .PD |
| 15919 | Generate code that uses (does not use) the load string instructions |
| 15920 | and the store string word instructions to save multiple registers and |
| 15921 | do small block moves. These instructions are generated by default on |
| 15922 | \&\s-1POWER\s0 systems, and not generated on PowerPC systems. Do not use |
| 15923 | \&\fB\-mstring\fR on little-endian PowerPC systems, since those |
| 15924 | instructions do not work when the processor is in little-endian mode. |
| 15925 | The exceptions are \s-1PPC740\s0 and \s-1PPC750\s0 which permit these instructions |
| 15926 | in little-endian mode. |
| 15927 | .IP "\fB\-mupdate\fR" 4 |
| 15928 | .IX Item "-mupdate" |
| 15929 | .PD 0 |
| 15930 | .IP "\fB\-mno\-update\fR" 4 |
| 15931 | .IX Item "-mno-update" |
| 15932 | .PD |
| 15933 | Generate code that uses (does not use) the load or store instructions |
| 15934 | that update the base register to the address of the calculated memory |
| 15935 | location. These instructions are generated by default. If you use |
| 15936 | \&\fB\-mno\-update\fR, there is a small window between the time that the |
| 15937 | stack pointer is updated and the address of the previous frame is |
| 15938 | stored, which means code that walks the stack frame across interrupts or |
| 15939 | signals may get corrupted data. |
| 15940 | .IP "\fB\-mavoid\-indexed\-addresses\fR" 4 |
| 15941 | .IX Item "-mavoid-indexed-addresses" |
| 15942 | .PD 0 |
| 15943 | .IP "\fB\-mno\-avoid\-indexed\-addresses\fR" 4 |
| 15944 | .IX Item "-mno-avoid-indexed-addresses" |
| 15945 | .PD |
| 15946 | Generate code that tries to avoid (not avoid) the use of indexed load |
| 15947 | or store instructions. These instructions can incur a performance |
| 15948 | penalty on Power6 processors in certain situations, such as when |
| 15949 | stepping through large arrays that cross a 16M boundary. This option |
| 15950 | is enabled by default when targetting Power6 and disabled otherwise. |
| 15951 | .IP "\fB\-mfused\-madd\fR" 4 |
| 15952 | .IX Item "-mfused-madd" |
| 15953 | .PD 0 |
| 15954 | .IP "\fB\-mno\-fused\-madd\fR" 4 |
| 15955 | .IX Item "-mno-fused-madd" |
| 15956 | .PD |
| 15957 | Generate code that uses (does not use) the floating-point multiply and |
| 15958 | accumulate instructions. These instructions are generated by default |
| 15959 | if hardware floating point is used. The machine-dependent |
| 15960 | \&\fB\-mfused\-madd\fR option is now mapped to the machine-independent |
| 15961 | \&\fB\-ffp\-contract=fast\fR option, and \fB\-mno\-fused\-madd\fR is |
| 15962 | mapped to \fB\-ffp\-contract=off\fR. |
| 15963 | .IP "\fB\-mmulhw\fR" 4 |
| 15964 | .IX Item "-mmulhw" |
| 15965 | .PD 0 |
| 15966 | .IP "\fB\-mno\-mulhw\fR" 4 |
| 15967 | .IX Item "-mno-mulhw" |
| 15968 | .PD |
| 15969 | Generate code that uses (does not use) the half-word multiply and |
| 15970 | multiply-accumulate instructions on the \s-1IBM\s0 405, 440, 464 and 476 processors. |
| 15971 | These instructions are generated by default when targetting those |
| 15972 | processors. |
| 15973 | .IP "\fB\-mdlmzb\fR" 4 |
| 15974 | .IX Item "-mdlmzb" |
| 15975 | .PD 0 |
| 15976 | .IP "\fB\-mno\-dlmzb\fR" 4 |
| 15977 | .IX Item "-mno-dlmzb" |
| 15978 | .PD |
| 15979 | Generate code that uses (does not use) the string-search \fBdlmzb\fR |
| 15980 | instruction on the \s-1IBM\s0 405, 440, 464 and 476 processors. This instruction is |
| 15981 | generated by default when targetting those processors. |
| 15982 | .IP "\fB\-mno\-bit\-align\fR" 4 |
| 15983 | .IX Item "-mno-bit-align" |
| 15984 | .PD 0 |
| 15985 | .IP "\fB\-mbit\-align\fR" 4 |
| 15986 | .IX Item "-mbit-align" |
| 15987 | .PD |
| 15988 | On System V.4 and embedded PowerPC systems do not (do) force structures |
| 15989 | and unions that contain bit-fields to be aligned to the base type of the |
| 15990 | bit-field. |
| 15991 | .Sp |
| 15992 | For example, by default a structure containing nothing but 8 |
| 15993 | \&\f(CW\*(C`unsigned\*(C'\fR bit-fields of length 1 is aligned to a 4\-byte |
| 15994 | boundary and has a size of 4 bytes. By using \fB\-mno\-bit\-align\fR, |
| 15995 | the structure is aligned to a 1\-byte boundary and is 1 byte in |
| 15996 | size. |
| 15997 | .IP "\fB\-mno\-strict\-align\fR" 4 |
| 15998 | .IX Item "-mno-strict-align" |
| 15999 | .PD 0 |
| 16000 | .IP "\fB\-mstrict\-align\fR" 4 |
| 16001 | .IX Item "-mstrict-align" |
| 16002 | .PD |
| 16003 | On System V.4 and embedded PowerPC systems do not (do) assume that |
| 16004 | unaligned memory references will be handled by the system. |
| 16005 | .IP "\fB\-mrelocatable\fR" 4 |
| 16006 | .IX Item "-mrelocatable" |
| 16007 | .PD 0 |
| 16008 | .IP "\fB\-mno\-relocatable\fR" 4 |
| 16009 | .IX Item "-mno-relocatable" |
| 16010 | .PD |
| 16011 | Generate code that allows (does not allow) a static executable to be |
| 16012 | relocated to a different address at run time. A simple embedded |
| 16013 | PowerPC system loader should relocate the entire contents of |
| 16014 | \&\f(CW\*(C`.got2\*(C'\fR and 4\-byte locations listed in the \f(CW\*(C`.fixup\*(C'\fR section, |
| 16015 | a table of 32\-bit addresses generated by this option. For this to |
| 16016 | work, all objects linked together must be compiled with |
| 16017 | \&\fB\-mrelocatable\fR or \fB\-mrelocatable\-lib\fR. |
| 16018 | \&\fB\-mrelocatable\fR code aligns the stack to an 8\-byte boundary. |
| 16019 | .IP "\fB\-mrelocatable\-lib\fR" 4 |
| 16020 | .IX Item "-mrelocatable-lib" |
| 16021 | .PD 0 |
| 16022 | .IP "\fB\-mno\-relocatable\-lib\fR" 4 |
| 16023 | .IX Item "-mno-relocatable-lib" |
| 16024 | .PD |
| 16025 | Like \fB\-mrelocatable\fR, \fB\-mrelocatable\-lib\fR generates a |
| 16026 | \&\f(CW\*(C`.fixup\*(C'\fR section to allow static executables to be relocated at |
| 16027 | run time, but \fB\-mrelocatable\-lib\fR does not use the smaller stack |
| 16028 | alignment of \fB\-mrelocatable\fR. Objects compiled with |
| 16029 | \&\fB\-mrelocatable\-lib\fR may be linked with objects compiled with |
| 16030 | any combination of the \fB\-mrelocatable\fR options. |
| 16031 | .IP "\fB\-mno\-toc\fR" 4 |
| 16032 | .IX Item "-mno-toc" |
| 16033 | .PD 0 |
| 16034 | .IP "\fB\-mtoc\fR" 4 |
| 16035 | .IX Item "-mtoc" |
| 16036 | .PD |
| 16037 | On System V.4 and embedded PowerPC systems do not (do) assume that |
| 16038 | register 2 contains a pointer to a global area pointing to the addresses |
| 16039 | used in the program. |
| 16040 | .IP "\fB\-mlittle\fR" 4 |
| 16041 | .IX Item "-mlittle" |
| 16042 | .PD 0 |
| 16043 | .IP "\fB\-mlittle\-endian\fR" 4 |
| 16044 | .IX Item "-mlittle-endian" |
| 16045 | .PD |
| 16046 | On System V.4 and embedded PowerPC systems compile code for the |
| 16047 | processor in little-endian mode. The \fB\-mlittle\-endian\fR option is |
| 16048 | the same as \fB\-mlittle\fR. |
| 16049 | .IP "\fB\-mbig\fR" 4 |
| 16050 | .IX Item "-mbig" |
| 16051 | .PD 0 |
| 16052 | .IP "\fB\-mbig\-endian\fR" 4 |
| 16053 | .IX Item "-mbig-endian" |
| 16054 | .PD |
| 16055 | On System V.4 and embedded PowerPC systems compile code for the |
| 16056 | processor in big-endian mode. The \fB\-mbig\-endian\fR option is |
| 16057 | the same as \fB\-mbig\fR. |
| 16058 | .IP "\fB\-mdynamic\-no\-pic\fR" 4 |
| 16059 | .IX Item "-mdynamic-no-pic" |
| 16060 | On Darwin and Mac \s-1OS\s0 X systems, compile code so that it is not |
| 16061 | relocatable, but that its external references are relocatable. The |
| 16062 | resulting code is suitable for applications, but not shared |
| 16063 | libraries. |
| 16064 | .IP "\fB\-msingle\-pic\-base\fR" 4 |
| 16065 | .IX Item "-msingle-pic-base" |
| 16066 | Treat the register used for \s-1PIC\s0 addressing as read-only, rather than |
| 16067 | loading it in the prologue for each function. The runtime system is |
| 16068 | responsible for initializing this register with an appropriate value |
| 16069 | before execution begins. |
| 16070 | .IP "\fB\-mprioritize\-restricted\-insns=\fR\fIpriority\fR" 4 |
| 16071 | .IX Item "-mprioritize-restricted-insns=priority" |
| 16072 | This option controls the priority that is assigned to |
| 16073 | dispatch-slot restricted instructions during the second scheduling |
| 16074 | pass. The argument \fIpriority\fR takes the value \fI0/1/2\fR to assign |
| 16075 | \&\fIno/highest/second\-highest\fR priority to dispatch slot restricted |
| 16076 | instructions. |
| 16077 | .IP "\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR" 4 |
| 16078 | .IX Item "-msched-costly-dep=dependence_type" |
| 16079 | This option controls which dependences are considered costly |
| 16080 | by the target during instruction scheduling. The argument |
| 16081 | \&\fIdependence_type\fR takes one of the following values: |
| 16082 | \&\fIno\fR: no dependence is costly, |
| 16083 | \&\fIall\fR: all dependences are costly, |
| 16084 | \&\fItrue_store_to_load\fR: a true dependence from store to load is costly, |
| 16085 | \&\fIstore_to_load\fR: any dependence from store to load is costly, |
| 16086 | \&\fInumber\fR: any dependence for which latency >= \fInumber\fR is costly. |
| 16087 | .IP "\fB\-minsert\-sched\-nops=\fR\fIscheme\fR" 4 |
| 16088 | .IX Item "-minsert-sched-nops=scheme" |
| 16089 | This option controls which nop insertion scheme will be used during |
| 16090 | the second scheduling pass. The argument \fIscheme\fR takes one of the |
| 16091 | following values: |
| 16092 | \&\fIno\fR: Don't insert nops. |
| 16093 | \&\fIpad\fR: Pad with nops any dispatch group that has vacant issue slots, |
| 16094 | according to the scheduler's grouping. |
| 16095 | \&\fIregroup_exact\fR: Insert nops to force costly dependent insns into |
| 16096 | separate groups. Insert exactly as many nops as needed to force an insn |
| 16097 | to a new group, according to the estimated processor grouping. |
| 16098 | \&\fInumber\fR: Insert nops to force costly dependent insns into |
| 16099 | separate groups. Insert \fInumber\fR nops to force an insn to a new group. |
| 16100 | .IP "\fB\-mcall\-sysv\fR" 4 |
| 16101 | .IX Item "-mcall-sysv" |
| 16102 | On System V.4 and embedded PowerPC systems compile code using calling |
| 16103 | conventions that adheres to the March 1995 draft of the System V |
| 16104 | Application Binary Interface, PowerPC processor supplement. This is the |
| 16105 | default unless you configured \s-1GCC\s0 using \fBpowerpc\-*\-eabiaix\fR. |
| 16106 | .IP "\fB\-mcall\-sysv\-eabi\fR" 4 |
| 16107 | .IX Item "-mcall-sysv-eabi" |
| 16108 | .PD 0 |
| 16109 | .IP "\fB\-mcall\-eabi\fR" 4 |
| 16110 | .IX Item "-mcall-eabi" |
| 16111 | .PD |
| 16112 | Specify both \fB\-mcall\-sysv\fR and \fB\-meabi\fR options. |
| 16113 | .IP "\fB\-mcall\-sysv\-noeabi\fR" 4 |
| 16114 | .IX Item "-mcall-sysv-noeabi" |
| 16115 | Specify both \fB\-mcall\-sysv\fR and \fB\-mno\-eabi\fR options. |
| 16116 | .IP "\fB\-mcall\-aixdesc\fR" 4 |
| 16117 | .IX Item "-mcall-aixdesc" |
| 16118 | On System V.4 and embedded PowerPC systems compile code for the \s-1AIX\s0 |
| 16119 | operating system. |
| 16120 | .IP "\fB\-mcall\-linux\fR" 4 |
| 16121 | .IX Item "-mcall-linux" |
| 16122 | On System V.4 and embedded PowerPC systems compile code for the |
| 16123 | Linux-based \s-1GNU\s0 system. |
| 16124 | .IP "\fB\-mcall\-freebsd\fR" 4 |
| 16125 | .IX Item "-mcall-freebsd" |
| 16126 | On System V.4 and embedded PowerPC systems compile code for the |
| 16127 | FreeBSD operating system. |
| 16128 | .IP "\fB\-mcall\-netbsd\fR" 4 |
| 16129 | .IX Item "-mcall-netbsd" |
| 16130 | On System V.4 and embedded PowerPC systems compile code for the |
| 16131 | NetBSD operating system. |
| 16132 | .IP "\fB\-mcall\-openbsd\fR" 4 |
| 16133 | .IX Item "-mcall-openbsd" |
| 16134 | On System V.4 and embedded PowerPC systems compile code for the |
| 16135 | OpenBSD operating system. |
| 16136 | .IP "\fB\-maix\-struct\-return\fR" 4 |
| 16137 | .IX Item "-maix-struct-return" |
| 16138 | Return all structures in memory (as specified by the \s-1AIX\s0 \s-1ABI\s0). |
| 16139 | .IP "\fB\-msvr4\-struct\-return\fR" 4 |
| 16140 | .IX Item "-msvr4-struct-return" |
| 16141 | Return structures smaller than 8 bytes in registers (as specified by the |
| 16142 | \&\s-1SVR4\s0 \s-1ABI\s0). |
| 16143 | .IP "\fB\-mabi=\fR\fIabi-type\fR" 4 |
| 16144 | .IX Item "-mabi=abi-type" |
| 16145 | Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. |
| 16146 | Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR, |
| 16147 | \&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR. |
| 16148 | .IP "\fB\-mabi=spe\fR" 4 |
| 16149 | .IX Item "-mabi=spe" |
| 16150 | Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change |
| 16151 | the default \s-1ABI\s0, instead it adds the \s-1SPE\s0 \s-1ABI\s0 extensions to the current |
| 16152 | \&\s-1ABI\s0. |
| 16153 | .IP "\fB\-mabi=no\-spe\fR" 4 |
| 16154 | .IX Item "-mabi=no-spe" |
| 16155 | Disable Booke \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0. |
| 16156 | .IP "\fB\-mabi=ibmlongdouble\fR" 4 |
| 16157 | .IX Item "-mabi=ibmlongdouble" |
| 16158 | Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended-precision long double. |
| 16159 | This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. |
| 16160 | .IP "\fB\-mabi=ieeelongdouble\fR" 4 |
| 16161 | .IX Item "-mabi=ieeelongdouble" |
| 16162 | Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. |
| 16163 | This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. |
| 16164 | .IP "\fB\-mprototype\fR" 4 |
| 16165 | .IX Item "-mprototype" |
| 16166 | .PD 0 |
| 16167 | .IP "\fB\-mno\-prototype\fR" 4 |
| 16168 | .IX Item "-mno-prototype" |
| 16169 | .PD |
| 16170 | On System V.4 and embedded PowerPC systems assume that all calls to |
| 16171 | variable argument functions are properly prototyped. Otherwise, the |
| 16172 | compiler must insert an instruction before every non prototyped call to |
| 16173 | set or clear bit 6 of the condition code register (\fI\s-1CR\s0\fR) to |
| 16174 | indicate whether floating-point values were passed in the floating-point |
| 16175 | registers in case the function takes variable arguments. With |
| 16176 | \&\fB\-mprototype\fR, only calls to prototyped variable argument functions |
| 16177 | will set or clear the bit. |
| 16178 | .IP "\fB\-msim\fR" 4 |
| 16179 | .IX Item "-msim" |
| 16180 | On embedded PowerPC systems, assume that the startup module is called |
| 16181 | \&\fIsim\-crt0.o\fR and that the standard C libraries are \fIlibsim.a\fR and |
| 16182 | \&\fIlibc.a\fR. This is the default for \fBpowerpc\-*\-eabisim\fR |
| 16183 | configurations. |
| 16184 | .IP "\fB\-mmvme\fR" 4 |
| 16185 | .IX Item "-mmvme" |
| 16186 | On embedded PowerPC systems, assume that the startup module is called |
| 16187 | \&\fIcrt0.o\fR and the standard C libraries are \fIlibmvme.a\fR and |
| 16188 | \&\fIlibc.a\fR. |
| 16189 | .IP "\fB\-mads\fR" 4 |
| 16190 | .IX Item "-mads" |
| 16191 | On embedded PowerPC systems, assume that the startup module is called |
| 16192 | \&\fIcrt0.o\fR and the standard C libraries are \fIlibads.a\fR and |
| 16193 | \&\fIlibc.a\fR. |
| 16194 | .IP "\fB\-myellowknife\fR" 4 |
| 16195 | .IX Item "-myellowknife" |
| 16196 | On embedded PowerPC systems, assume that the startup module is called |
| 16197 | \&\fIcrt0.o\fR and the standard C libraries are \fIlibyk.a\fR and |
| 16198 | \&\fIlibc.a\fR. |
| 16199 | .IP "\fB\-mvxworks\fR" 4 |
| 16200 | .IX Item "-mvxworks" |
| 16201 | On System V.4 and embedded PowerPC systems, specify that you are |
| 16202 | compiling for a VxWorks system. |
| 16203 | .IP "\fB\-memb\fR" 4 |
| 16204 | .IX Item "-memb" |
| 16205 | On embedded PowerPC systems, set the \fI\s-1PPC_EMB\s0\fR bit in the \s-1ELF\s0 flags |
| 16206 | header to indicate that \fBeabi\fR extended relocations are used. |
| 16207 | .IP "\fB\-meabi\fR" 4 |
| 16208 | .IX Item "-meabi" |
| 16209 | .PD 0 |
| 16210 | .IP "\fB\-mno\-eabi\fR" 4 |
| 16211 | .IX Item "-mno-eabi" |
| 16212 | .PD |
| 16213 | On System V.4 and embedded PowerPC systems do (do not) adhere to the |
| 16214 | Embedded Applications Binary Interface (eabi) which is a set of |
| 16215 | modifications to the System V.4 specifications. Selecting \fB\-meabi\fR |
| 16216 | means that the stack is aligned to an 8\-byte boundary, a function |
| 16217 | \&\f(CW\*(C`_\|_eabi\*(C'\fR is called to from \f(CW\*(C`main\*(C'\fR to set up the eabi |
| 16218 | environment, and the \fB\-msdata\fR option can use both \f(CW\*(C`r2\*(C'\fR and |
| 16219 | \&\f(CW\*(C`r13\*(C'\fR to point to two separate small data areas. Selecting |
| 16220 | \&\fB\-mno\-eabi\fR means that the stack is aligned to a 16\-byte boundary, |
| 16221 | do not call an initialization function from \f(CW\*(C`main\*(C'\fR, and the |
| 16222 | \&\fB\-msdata\fR option will only use \f(CW\*(C`r13\*(C'\fR to point to a single |
| 16223 | small data area. The \fB\-meabi\fR option is on by default if you |
| 16224 | configured \s-1GCC\s0 using one of the \fBpowerpc*\-*\-eabi*\fR options. |
| 16225 | .IP "\fB\-msdata=eabi\fR" 4 |
| 16226 | .IX Item "-msdata=eabi" |
| 16227 | On System V.4 and embedded PowerPC systems, put small initialized |
| 16228 | \&\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata2\fR section, which |
| 16229 | is pointed to by register \f(CW\*(C`r2\*(C'\fR. Put small initialized |
| 16230 | non\-\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata\fR section, |
| 16231 | which is pointed to by register \f(CW\*(C`r13\*(C'\fR. Put small uninitialized |
| 16232 | global and static data in the \fB.sbss\fR section, which is adjacent to |
| 16233 | the \fB.sdata\fR section. The \fB\-msdata=eabi\fR option is |
| 16234 | incompatible with the \fB\-mrelocatable\fR option. The |
| 16235 | \&\fB\-msdata=eabi\fR option also sets the \fB\-memb\fR option. |
| 16236 | .IP "\fB\-msdata=sysv\fR" 4 |
| 16237 | .IX Item "-msdata=sysv" |
| 16238 | On System V.4 and embedded PowerPC systems, put small global and static |
| 16239 | data in the \fB.sdata\fR section, which is pointed to by register |
| 16240 | \&\f(CW\*(C`r13\*(C'\fR. Put small uninitialized global and static data in the |
| 16241 | \&\fB.sbss\fR section, which is adjacent to the \fB.sdata\fR section. |
| 16242 | The \fB\-msdata=sysv\fR option is incompatible with the |
| 16243 | \&\fB\-mrelocatable\fR option. |
| 16244 | .IP "\fB\-msdata=default\fR" 4 |
| 16245 | .IX Item "-msdata=default" |
| 16246 | .PD 0 |
| 16247 | .IP "\fB\-msdata\fR" 4 |
| 16248 | .IX Item "-msdata" |
| 16249 | .PD |
| 16250 | On System V.4 and embedded PowerPC systems, if \fB\-meabi\fR is used, |
| 16251 | compile code the same as \fB\-msdata=eabi\fR, otherwise compile code the |
| 16252 | same as \fB\-msdata=sysv\fR. |
| 16253 | .IP "\fB\-msdata=data\fR" 4 |
| 16254 | .IX Item "-msdata=data" |
| 16255 | On System V.4 and embedded PowerPC systems, put small global |
| 16256 | data in the \fB.sdata\fR section. Put small uninitialized global |
| 16257 | data in the \fB.sbss\fR section. Do not use register \f(CW\*(C`r13\*(C'\fR |
| 16258 | to address small data however. This is the default behavior unless |
| 16259 | other \fB\-msdata\fR options are used. |
| 16260 | .IP "\fB\-msdata=none\fR" 4 |
| 16261 | .IX Item "-msdata=none" |
| 16262 | .PD 0 |
| 16263 | .IP "\fB\-mno\-sdata\fR" 4 |
| 16264 | .IX Item "-mno-sdata" |
| 16265 | .PD |
| 16266 | On embedded PowerPC systems, put all initialized global and static data |
| 16267 | in the \fB.data\fR section, and all uninitialized data in the |
| 16268 | \&\fB.bss\fR section. |
| 16269 | .IP "\fB\-mblock\-move\-inline\-limit=\fR\fInum\fR" 4 |
| 16270 | .IX Item "-mblock-move-inline-limit=num" |
| 16271 | Inline all block moves (such as calls to \f(CW\*(C`memcpy\*(C'\fR or structure |
| 16272 | copies) less than or equal to \fInum\fR bytes. The minimum value for |
| 16273 | \&\fInum\fR is 32 bytes on 32\-bit targets and 64 bytes on 64\-bit |
| 16274 | targets. The default value is target-specific. |
| 16275 | .IP "\fB\-G\fR \fInum\fR" 4 |
| 16276 | .IX Item "-G num" |
| 16277 | On embedded PowerPC systems, put global and static items less than or |
| 16278 | equal to \fInum\fR bytes into the small data or bss sections instead of |
| 16279 | the normal data or bss section. By default, \fInum\fR is 8. The |
| 16280 | \&\fB\-G\fR \fInum\fR switch is also passed to the linker. |
| 16281 | All modules should be compiled with the same \fB\-G\fR \fInum\fR value. |
| 16282 | .IP "\fB\-mregnames\fR" 4 |
| 16283 | .IX Item "-mregnames" |
| 16284 | .PD 0 |
| 16285 | .IP "\fB\-mno\-regnames\fR" 4 |
| 16286 | .IX Item "-mno-regnames" |
| 16287 | .PD |
| 16288 | On System V.4 and embedded PowerPC systems do (do not) emit register |
| 16289 | names in the assembly language output using symbolic forms. |
| 16290 | .IP "\fB\-mlongcall\fR" 4 |
| 16291 | .IX Item "-mlongcall" |
| 16292 | .PD 0 |
| 16293 | .IP "\fB\-mno\-longcall\fR" 4 |
| 16294 | .IX Item "-mno-longcall" |
| 16295 | .PD |
| 16296 | By default assume that all calls are far away so that a longer more |
| 16297 | expensive calling sequence is required. This is required for calls |
| 16298 | further than 32 megabytes (33,554,432 bytes) from the current location. |
| 16299 | A short call will be generated if the compiler knows |
| 16300 | the call cannot be that far away. This setting can be overridden by |
| 16301 | the \f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma |
| 16302 | longcall(0)\*(C'\fR. |
| 16303 | .Sp |
| 16304 | Some linkers are capable of detecting out-of-range calls and generating |
| 16305 | glue code on the fly. On these systems, long calls are unnecessary and |
| 16306 | generate slower code. As of this writing, the \s-1AIX\s0 linker can do this, |
| 16307 | as can the \s-1GNU\s0 linker for PowerPC/64. It is planned to add this feature |
| 16308 | to the \s-1GNU\s0 linker for 32\-bit PowerPC systems as well. |
| 16309 | .Sp |
| 16310 | On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR will generate \*(L"jbsr |
| 16311 | callee, L42\*(R", plus a \*(L"branch island\*(R" (glue code). The two target |
| 16312 | addresses represent the callee and the \*(L"branch island\*(R". The |
| 16313 | Darwin/PPC linker will prefer the first address and generate a \*(L"bl |
| 16314 | callee\*(R" if the \s-1PPC\s0 \*(L"bl\*(R" instruction will reach the callee directly; |
| 16315 | otherwise, the linker will generate \*(L"bl L42\*(R" to call the \*(L"branch |
| 16316 | island\*(R". The \*(L"branch island\*(R" is appended to the body of the |
| 16317 | calling function; it computes the full 32\-bit address of the callee |
| 16318 | and jumps to it. |
| 16319 | .Sp |
| 16320 | On Mach-O (Darwin) systems, this option directs the compiler emit to |
| 16321 | the glue for every direct call, and the Darwin linker decides whether |
| 16322 | to use or discard it. |
| 16323 | .Sp |
| 16324 | In the future, we may cause \s-1GCC\s0 to ignore all longcall specifications |
| 16325 | when the linker is known to generate glue. |
| 16326 | .IP "\fB\-mtls\-markers\fR" 4 |
| 16327 | .IX Item "-mtls-markers" |
| 16328 | .PD 0 |
| 16329 | .IP "\fB\-mno\-tls\-markers\fR" 4 |
| 16330 | .IX Item "-mno-tls-markers" |
| 16331 | .PD |
| 16332 | Mark (do not mark) calls to \f(CW\*(C`_\|_tls_get_addr\*(C'\fR with a relocation |
| 16333 | specifying the function argument. The relocation allows ld to |
| 16334 | reliably associate function call with argument setup instructions for |
| 16335 | \&\s-1TLS\s0 optimization, which in turn allows gcc to better schedule the |
| 16336 | sequence. |
| 16337 | .IP "\fB\-pthread\fR" 4 |
| 16338 | .IX Item "-pthread" |
| 16339 | Adds support for multithreading with the \fIpthreads\fR library. |
| 16340 | This option sets flags for both the preprocessor and linker. |
| 16341 | .IP "\fB\-mrecip\fR" 4 |
| 16342 | .IX Item "-mrecip" |
| 16343 | .PD 0 |
| 16344 | .IP "\fB\-mno\-recip\fR" 4 |
| 16345 | .IX Item "-mno-recip" |
| 16346 | .PD |
| 16347 | This option will enable \s-1GCC\s0 to use the reciprocal estimate and |
| 16348 | reciprocal square root estimate instructions with additional |
| 16349 | Newton-Raphson steps to increase precision instead of doing a divide or |
| 16350 | square root and divide for floating-point arguments. You should use |
| 16351 | the \fB\-ffast\-math\fR option when using \fB\-mrecip\fR (or at |
| 16352 | least \fB\-funsafe\-math\-optimizations\fR, |
| 16353 | \&\fB\-finite\-math\-only\fR, \fB\-freciprocal\-math\fR and |
| 16354 | \&\fB\-fno\-trapping\-math\fR). Note that while the throughput of the |
| 16355 | sequence is generally higher than the throughput of the non-reciprocal |
| 16356 | instruction, the precision of the sequence can be decreased by up to 2 |
| 16357 | ulp (i.e. the inverse of 1.0 equals 0.99999994) for reciprocal square |
| 16358 | roots. |
| 16359 | .IP "\fB\-mrecip=\fR\fIopt\fR" 4 |
| 16360 | .IX Item "-mrecip=opt" |
| 16361 | This option allows to control which reciprocal estimate instructions |
| 16362 | may be used. \fIopt\fR is a comma separated list of options, which may |
| 16363 | be preceded by a \f(CW\*(C`!\*(C'\fR to invert the option: |
| 16364 | \&\f(CW\*(C`all\*(C'\fR: enable all estimate instructions, |
| 16365 | \&\f(CW\*(C`default\*(C'\fR: enable the default instructions, equivalent to \fB\-mrecip\fR, |
| 16366 | \&\f(CW\*(C`none\*(C'\fR: disable all estimate instructions, equivalent to \fB\-mno\-recip\fR; |
| 16367 | \&\f(CW\*(C`div\*(C'\fR: enable the reciprocal approximation instructions for both single and double precision; |
| 16368 | \&\f(CW\*(C`divf\*(C'\fR: enable the single-precision reciprocal approximation instructions; |
| 16369 | \&\f(CW\*(C`divd\*(C'\fR: enable the double-precision reciprocal approximation instructions; |
| 16370 | \&\f(CW\*(C`rsqrt\*(C'\fR: enable the reciprocal square root approximation instructions for both single and double precision; |
| 16371 | \&\f(CW\*(C`rsqrtf\*(C'\fR: enable the single-precision reciprocal square root approximation instructions; |
| 16372 | \&\f(CW\*(C`rsqrtd\*(C'\fR: enable the double-precision reciprocal square root approximation instructions; |
| 16373 | .Sp |
| 16374 | So for example, \fB\-mrecip=all,!rsqrtd\fR would enable the |
| 16375 | all of the reciprocal estimate instructions, except for the |
| 16376 | \&\f(CW\*(C`FRSQRTE\*(C'\fR, \f(CW\*(C`XSRSQRTEDP\*(C'\fR, and \f(CW\*(C`XVRSQRTEDP\*(C'\fR instructions |
| 16377 | which handle the double-precision reciprocal square root calculations. |
| 16378 | .IP "\fB\-mrecip\-precision\fR" 4 |
| 16379 | .IX Item "-mrecip-precision" |
| 16380 | .PD 0 |
| 16381 | .IP "\fB\-mno\-recip\-precision\fR" 4 |
| 16382 | .IX Item "-mno-recip-precision" |
| 16383 | .PD |
| 16384 | Assume (do not assume) that the reciprocal estimate instructions |
| 16385 | provide higher-precision estimates than is mandated by the PowerPC |
| 16386 | \&\s-1ABI\s0. Selecting \fB\-mcpu=power6\fR or \fB\-mcpu=power7\fR |
| 16387 | automatically selects \fB\-mrecip\-precision\fR. The double-precision |
| 16388 | square root estimate instructions are not generated by |
| 16389 | default on low-precision machines, since they do not provide an |
| 16390 | estimate that converges after three steps. |
| 16391 | .IP "\fB\-mveclibabi=\fR\fItype\fR" 4 |
| 16392 | .IX Item "-mveclibabi=type" |
| 16393 | Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an |
| 16394 | external library. The only type supported at present is \f(CW\*(C`mass\*(C'\fR, |
| 16395 | which specifies to use \s-1IBM\s0's Mathematical Acceleration Subsystem |
| 16396 | (\s-1MASS\s0) libraries for vectorizing intrinsics using external libraries. |
| 16397 | \&\s-1GCC\s0 will currently emit calls to \f(CW\*(C`acosd2\*(C'\fR, \f(CW\*(C`acosf4\*(C'\fR, |
| 16398 | \&\f(CW\*(C`acoshd2\*(C'\fR, \f(CW\*(C`acoshf4\*(C'\fR, \f(CW\*(C`asind2\*(C'\fR, \f(CW\*(C`asinf4\*(C'\fR, |
| 16399 | \&\f(CW\*(C`asinhd2\*(C'\fR, \f(CW\*(C`asinhf4\*(C'\fR, \f(CW\*(C`atan2d2\*(C'\fR, \f(CW\*(C`atan2f4\*(C'\fR, |
| 16400 | \&\f(CW\*(C`atand2\*(C'\fR, \f(CW\*(C`atanf4\*(C'\fR, \f(CW\*(C`atanhd2\*(C'\fR, \f(CW\*(C`atanhf4\*(C'\fR, |
| 16401 | \&\f(CW\*(C`cbrtd2\*(C'\fR, \f(CW\*(C`cbrtf4\*(C'\fR, \f(CW\*(C`cosd2\*(C'\fR, \f(CW\*(C`cosf4\*(C'\fR, |
| 16402 | \&\f(CW\*(C`coshd2\*(C'\fR, \f(CW\*(C`coshf4\*(C'\fR, \f(CW\*(C`erfcd2\*(C'\fR, \f(CW\*(C`erfcf4\*(C'\fR, |
| 16403 | \&\f(CW\*(C`erfd2\*(C'\fR, \f(CW\*(C`erff4\*(C'\fR, \f(CW\*(C`exp2d2\*(C'\fR, \f(CW\*(C`exp2f4\*(C'\fR, |
| 16404 | \&\f(CW\*(C`expd2\*(C'\fR, \f(CW\*(C`expf4\*(C'\fR, \f(CW\*(C`expm1d2\*(C'\fR, \f(CW\*(C`expm1f4\*(C'\fR, |
| 16405 | \&\f(CW\*(C`hypotd2\*(C'\fR, \f(CW\*(C`hypotf4\*(C'\fR, \f(CW\*(C`lgammad2\*(C'\fR, \f(CW\*(C`lgammaf4\*(C'\fR, |
| 16406 | \&\f(CW\*(C`log10d2\*(C'\fR, \f(CW\*(C`log10f4\*(C'\fR, \f(CW\*(C`log1pd2\*(C'\fR, \f(CW\*(C`log1pf4\*(C'\fR, |
| 16407 | \&\f(CW\*(C`log2d2\*(C'\fR, \f(CW\*(C`log2f4\*(C'\fR, \f(CW\*(C`logd2\*(C'\fR, \f(CW\*(C`logf4\*(C'\fR, |
| 16408 | \&\f(CW\*(C`powd2\*(C'\fR, \f(CW\*(C`powf4\*(C'\fR, \f(CW\*(C`sind2\*(C'\fR, \f(CW\*(C`sinf4\*(C'\fR, \f(CW\*(C`sinhd2\*(C'\fR, |
| 16409 | \&\f(CW\*(C`sinhf4\*(C'\fR, \f(CW\*(C`sqrtd2\*(C'\fR, \f(CW\*(C`sqrtf4\*(C'\fR, \f(CW\*(C`tand2\*(C'\fR, |
| 16410 | \&\f(CW\*(C`tanf4\*(C'\fR, \f(CW\*(C`tanhd2\*(C'\fR, and \f(CW\*(C`tanhf4\*(C'\fR when generating code |
| 16411 | for power7. Both \fB\-ftree\-vectorize\fR and |
| 16412 | \&\fB\-funsafe\-math\-optimizations\fR have to be enabled. The \s-1MASS\s0 |
| 16413 | libraries will have to be specified at link time. |
| 16414 | .IP "\fB\-mfriz\fR" 4 |
| 16415 | .IX Item "-mfriz" |
| 16416 | .PD 0 |
| 16417 | .IP "\fB\-mno\-friz\fR" 4 |
| 16418 | .IX Item "-mno-friz" |
| 16419 | .PD |
| 16420 | Generate (do not generate) the \f(CW\*(C`friz\*(C'\fR instruction when the |
| 16421 | \&\fB\-funsafe\-math\-optimizations\fR option is used to optimize |
| 16422 | rounding of floating-point values to 64\-bit integer and back to floating |
| 16423 | point. The \f(CW\*(C`friz\*(C'\fR instruction does not return the same value if |
| 16424 | the floating-point number is too large to fit in an integer. |
| 16425 | .IP "\fB\-mpointers\-to\-nested\-functions\fR" 4 |
| 16426 | .IX Item "-mpointers-to-nested-functions" |
| 16427 | .PD 0 |
| 16428 | .IP "\fB\-mno\-pointers\-to\-nested\-functions\fR" 4 |
| 16429 | .IX Item "-mno-pointers-to-nested-functions" |
| 16430 | .PD |
| 16431 | Generate (do not generate) code to load up the static chain register |
| 16432 | (\fIr11\fR) when calling through a pointer on \s-1AIX\s0 and 64\-bit Linux |
| 16433 | systems where a function pointer points to a 3\-word descriptor giving |
| 16434 | the function address, \s-1TOC\s0 value to be loaded in register \fIr2\fR, and |
| 16435 | static chain value to be loaded in register \fIr11\fR. The |
| 16436 | \&\fB\-mpointers\-to\-nested\-functions\fR is on by default. You will |
| 16437 | not be able to call through pointers to nested functions or pointers |
| 16438 | to functions compiled in other languages that use the static chain if |
| 16439 | you use the \fB\-mno\-pointers\-to\-nested\-functions\fR. |
| 16440 | .IP "\fB\-msave\-toc\-indirect\fR" 4 |
| 16441 | .IX Item "-msave-toc-indirect" |
| 16442 | .PD 0 |
| 16443 | .IP "\fB\-mno\-save\-toc\-indirect\fR" 4 |
| 16444 | .IX Item "-mno-save-toc-indirect" |
| 16445 | .PD |
| 16446 | Generate (do not generate) code to save the \s-1TOC\s0 value in the reserved |
| 16447 | stack location in the function prologue if the function calls through |
| 16448 | a pointer on \s-1AIX\s0 and 64\-bit Linux systems. If the \s-1TOC\s0 value is not |
| 16449 | saved in the prologue, it is saved just before the call through the |
| 16450 | pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. |
| 16451 | .PP |
| 16452 | \fI\s-1RX\s0 Options\fR |
| 16453 | .IX Subsection "RX Options" |
| 16454 | .PP |
| 16455 | These command-line options are defined for \s-1RX\s0 targets: |
| 16456 | .IP "\fB\-m64bit\-doubles\fR" 4 |
| 16457 | .IX Item "-m64bit-doubles" |
| 16458 | .PD 0 |
| 16459 | .IP "\fB\-m32bit\-doubles\fR" 4 |
| 16460 | .IX Item "-m32bit-doubles" |
| 16461 | .PD |
| 16462 | Make the \f(CW\*(C`double\*(C'\fR data type be 64 bits (\fB\-m64bit\-doubles\fR) |
| 16463 | or 32 bits (\fB\-m32bit\-doubles\fR) in size. The default is |
| 16464 | \&\fB\-m32bit\-doubles\fR. \fINote\fR \s-1RX\s0 floating-point hardware only |
| 16465 | works on 32\-bit values, which is why the default is |
| 16466 | \&\fB\-m32bit\-doubles\fR. |
| 16467 | .IP "\fB\-fpu\fR" 4 |
| 16468 | .IX Item "-fpu" |
| 16469 | .PD 0 |
| 16470 | .IP "\fB\-nofpu\fR" 4 |
| 16471 | .IX Item "-nofpu" |
| 16472 | .PD |
| 16473 | Enables (\fB\-fpu\fR) or disables (\fB\-nofpu\fR) the use of \s-1RX\s0 |
| 16474 | floating-point hardware. The default is enabled for the \fI\s-1RX600\s0\fR |
| 16475 | series and disabled for the \fI\s-1RX200\s0\fR series. |
| 16476 | .Sp |
| 16477 | Floating-point instructions will only be generated for 32\-bit floating-point |
| 16478 | values however, so if the \fB\-m64bit\-doubles\fR option is in |
| 16479 | use then the \s-1FPU\s0 hardware will not be used for doubles. |
| 16480 | .Sp |
| 16481 | \&\fINote\fR If the \fB\-fpu\fR option is enabled then |
| 16482 | \&\fB\-funsafe\-math\-optimizations\fR is also enabled automatically. |
| 16483 | This is because the \s-1RX\s0 \s-1FPU\s0 instructions are themselves unsafe. |
| 16484 | .IP "\fB\-mcpu=\fR\fIname\fR" 4 |
| 16485 | .IX Item "-mcpu=name" |
| 16486 | Selects the type of \s-1RX\s0 \s-1CPU\s0 to be targeted. Currently three types are |
| 16487 | supported, the generic \fI\s-1RX600\s0\fR and \fI\s-1RX200\s0\fR series hardware and |
| 16488 | the specific \fI\s-1RX610\s0\fR \s-1CPU\s0. The default is \fI\s-1RX600\s0\fR. |
| 16489 | .Sp |
| 16490 | The only difference between \fI\s-1RX600\s0\fR and \fI\s-1RX610\s0\fR is that the |
| 16491 | \&\fI\s-1RX610\s0\fR does not support the \f(CW\*(C`MVTIPL\*(C'\fR instruction. |
| 16492 | .Sp |
| 16493 | The \fI\s-1RX200\s0\fR series does not have a hardware floating-point unit |
| 16494 | and so \fB\-nofpu\fR is enabled by default when this type is |
| 16495 | selected. |
| 16496 | .IP "\fB\-mbig\-endian\-data\fR" 4 |
| 16497 | .IX Item "-mbig-endian-data" |
| 16498 | .PD 0 |
| 16499 | .IP "\fB\-mlittle\-endian\-data\fR" 4 |
| 16500 | .IX Item "-mlittle-endian-data" |
| 16501 | .PD |
| 16502 | Store data (but not code) in the big-endian format. The default is |
| 16503 | \&\fB\-mlittle\-endian\-data\fR, i.e. to store data in the little-endian |
| 16504 | format. |
| 16505 | .IP "\fB\-msmall\-data\-limit=\fR\fIN\fR" 4 |
| 16506 | .IX Item "-msmall-data-limit=N" |
| 16507 | Specifies the maximum size in bytes of global and static variables |
| 16508 | which can be placed into the small data area. Using the small data |
| 16509 | area can lead to smaller and faster code, but the size of area is |
| 16510 | limited and it is up to the programmer to ensure that the area does |
| 16511 | not overflow. Also when the small data area is used one of the \s-1RX\s0's |
| 16512 | registers (usually \f(CW\*(C`r13\*(C'\fR) is reserved for use pointing to this |
| 16513 | area, so it is no longer available for use by the compiler. This |
| 16514 | could result in slower and/or larger code if variables which once |
| 16515 | could have been held in the reserved register are now pushed onto the |
| 16516 | stack. |
| 16517 | .Sp |
| 16518 | Note, common variables (variables that have not been initialized) and |
| 16519 | constants are not placed into the small data area as they are assigned |
| 16520 | to other sections in the output executable. |
| 16521 | .Sp |
| 16522 | The default value is zero, which disables this feature. Note, this |
| 16523 | feature is not enabled by default with higher optimization levels |
| 16524 | (\fB\-O2\fR etc) because of the potentially detrimental effects of |
| 16525 | reserving a register. It is up to the programmer to experiment and |
| 16526 | discover whether this feature is of benefit to their program. See the |
| 16527 | description of the \fB\-mpid\fR option for a description of how the |
| 16528 | actual register to hold the small data area pointer is chosen. |
| 16529 | .IP "\fB\-msim\fR" 4 |
| 16530 | .IX Item "-msim" |
| 16531 | .PD 0 |
| 16532 | .IP "\fB\-mno\-sim\fR" 4 |
| 16533 | .IX Item "-mno-sim" |
| 16534 | .PD |
| 16535 | Use the simulator runtime. The default is to use the libgloss board |
| 16536 | specific runtime. |
| 16537 | .IP "\fB\-mas100\-syntax\fR" 4 |
| 16538 | .IX Item "-mas100-syntax" |
| 16539 | .PD 0 |
| 16540 | .IP "\fB\-mno\-as100\-syntax\fR" 4 |
| 16541 | .IX Item "-mno-as100-syntax" |
| 16542 | .PD |
| 16543 | When generating assembler output use a syntax that is compatible with |
| 16544 | Renesas's \s-1AS100\s0 assembler. This syntax can also be handled by the \s-1GAS\s0 |
| 16545 | assembler but it has some restrictions so generating it is not the |
| 16546 | default option. |
| 16547 | .IP "\fB\-mmax\-constant\-size=\fR\fIN\fR" 4 |
| 16548 | .IX Item "-mmax-constant-size=N" |
| 16549 | Specifies the maximum size, in bytes, of a constant that can be used as |
| 16550 | an operand in a \s-1RX\s0 instruction. Although the \s-1RX\s0 instruction set does |
| 16551 | allow constants of up to 4 bytes in length to be used in instructions, |
| 16552 | a longer value equates to a longer instruction. Thus in some |
| 16553 | circumstances it can be beneficial to restrict the size of constants |
| 16554 | that are used in instructions. Constants that are too big are instead |
| 16555 | placed into a constant pool and referenced via register indirection. |
| 16556 | .Sp |
| 16557 | The value \fIN\fR can be between 0 and 4. A value of 0 (the default) |
| 16558 | or 4 means that constants of any size are allowed. |
| 16559 | .IP "\fB\-mrelax\fR" 4 |
| 16560 | .IX Item "-mrelax" |
| 16561 | Enable linker relaxation. Linker relaxation is a process whereby the |
| 16562 | linker will attempt to reduce the size of a program by finding shorter |
| 16563 | versions of various instructions. Disabled by default. |
| 16564 | .IP "\fB\-mint\-register=\fR\fIN\fR" 4 |
| 16565 | .IX Item "-mint-register=N" |
| 16566 | Specify the number of registers to reserve for fast interrupt handler |
| 16567 | functions. The value \fIN\fR can be between 0 and 4. A value of 1 |
| 16568 | means that register \f(CW\*(C`r13\*(C'\fR will be reserved for the exclusive use |
| 16569 | of fast interrupt handlers. A value of 2 reserves \f(CW\*(C`r13\*(C'\fR and |
| 16570 | \&\f(CW\*(C`r12\*(C'\fR. A value of 3 reserves \f(CW\*(C`r13\*(C'\fR, \f(CW\*(C`r12\*(C'\fR and |
| 16571 | \&\f(CW\*(C`r11\*(C'\fR, and a value of 4 reserves \f(CW\*(C`r13\*(C'\fR through \f(CW\*(C`r10\*(C'\fR. |
| 16572 | A value of 0, the default, does not reserve any registers. |
| 16573 | .IP "\fB\-msave\-acc\-in\-interrupts\fR" 4 |
| 16574 | .IX Item "-msave-acc-in-interrupts" |
| 16575 | Specifies that interrupt handler functions should preserve the |
| 16576 | accumulator register. This is only necessary if normal code might use |
| 16577 | the accumulator register, for example because it performs 64\-bit |
| 16578 | multiplications. The default is to ignore the accumulator as this |
| 16579 | makes the interrupt handlers faster. |
| 16580 | .IP "\fB\-mpid\fR" 4 |
| 16581 | .IX Item "-mpid" |
| 16582 | .PD 0 |
| 16583 | .IP "\fB\-mno\-pid\fR" 4 |
| 16584 | .IX Item "-mno-pid" |
| 16585 | .PD |
| 16586 | Enables the generation of position independent data. When enabled any |
| 16587 | access to constant data will done via an offset from a base address |
| 16588 | held in a register. This allows the location of constant data to be |
| 16589 | determined at run time without requiring the executable to be |
| 16590 | relocated, which is a benefit to embedded applications with tight |
| 16591 | memory constraints. Data that can be modified is not affected by this |
| 16592 | option. |
| 16593 | .Sp |
| 16594 | Note, using this feature reserves a register, usually \f(CW\*(C`r13\*(C'\fR, for |
| 16595 | the constant data base address. This can result in slower and/or |
| 16596 | larger code, especially in complicated functions. |
| 16597 | .Sp |
| 16598 | The actual register chosen to hold the constant data base address |
| 16599 | depends upon whether the \fB\-msmall\-data\-limit\fR and/or the |
| 16600 | \&\fB\-mint\-register\fR command-line options are enabled. Starting |
| 16601 | with register \f(CW\*(C`r13\*(C'\fR and proceeding downwards, registers are |
| 16602 | allocated first to satisfy the requirements of \fB\-mint\-register\fR, |
| 16603 | then \fB\-mpid\fR and finally \fB\-msmall\-data\-limit\fR. Thus it |
| 16604 | is possible for the small data area register to be \f(CW\*(C`r8\*(C'\fR if both |
| 16605 | \&\fB\-mint\-register=4\fR and \fB\-mpid\fR are specified on the |
| 16606 | command line. |
| 16607 | .Sp |
| 16608 | By default this feature is not enabled. The default can be restored |
| 16609 | via the \fB\-mno\-pid\fR command-line option. |
| 16610 | .PP |
| 16611 | \&\fINote:\fR The generic \s-1GCC\s0 command-line option \fB\-ffixed\-\fR\fIreg\fR |
| 16612 | has special significance to the \s-1RX\s0 port when used with the |
| 16613 | \&\f(CW\*(C`interrupt\*(C'\fR function attribute. This attribute indicates a |
| 16614 | function intended to process fast interrupts. \s-1GCC\s0 will will ensure |
| 16615 | that it only uses the registers \f(CW\*(C`r10\*(C'\fR, \f(CW\*(C`r11\*(C'\fR, \f(CW\*(C`r12\*(C'\fR |
| 16616 | and/or \f(CW\*(C`r13\*(C'\fR and only provided that the normal use of the |
| 16617 | corresponding registers have been restricted via the |
| 16618 | \&\fB\-ffixed\-\fR\fIreg\fR or \fB\-mint\-register\fR command-line |
| 16619 | options. |
| 16620 | .PP |
| 16621 | \fIS/390 and zSeries Options\fR |
| 16622 | .IX Subsection "S/390 and zSeries Options" |
| 16623 | .PP |
| 16624 | These are the \fB\-m\fR options defined for the S/390 and zSeries architecture. |
| 16625 | .IP "\fB\-mhard\-float\fR" 4 |
| 16626 | .IX Item "-mhard-float" |
| 16627 | .PD 0 |
| 16628 | .IP "\fB\-msoft\-float\fR" 4 |
| 16629 | .IX Item "-msoft-float" |
| 16630 | .PD |
| 16631 | Use (do not use) the hardware floating-point instructions and registers |
| 16632 | for floating-point operations. When \fB\-msoft\-float\fR is specified, |
| 16633 | functions in \fIlibgcc.a\fR will be used to perform floating-point |
| 16634 | operations. When \fB\-mhard\-float\fR is specified, the compiler |
| 16635 | generates \s-1IEEE\s0 floating-point instructions. This is the default. |
| 16636 | .IP "\fB\-mhard\-dfp\fR" 4 |
| 16637 | .IX Item "-mhard-dfp" |
| 16638 | .PD 0 |
| 16639 | .IP "\fB\-mno\-hard\-dfp\fR" 4 |
| 16640 | .IX Item "-mno-hard-dfp" |
| 16641 | .PD |
| 16642 | Use (do not use) the hardware decimal-floating-point instructions for |
| 16643 | decimal-floating-point operations. When \fB\-mno\-hard\-dfp\fR is |
| 16644 | specified, functions in \fIlibgcc.a\fR will be used to perform |
| 16645 | decimal-floating-point operations. When \fB\-mhard\-dfp\fR is |
| 16646 | specified, the compiler generates decimal-floating-point hardware |
| 16647 | instructions. This is the default for \fB\-march=z9\-ec\fR or higher. |
| 16648 | .IP "\fB\-mlong\-double\-64\fR" 4 |
| 16649 | .IX Item "-mlong-double-64" |
| 16650 | .PD 0 |
| 16651 | .IP "\fB\-mlong\-double\-128\fR" 4 |
| 16652 | .IX Item "-mlong-double-128" |
| 16653 | .PD |
| 16654 | These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size |
| 16655 | of 64 bits makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR |
| 16656 | type. This is the default. |
| 16657 | .IP "\fB\-mbackchain\fR" 4 |
| 16658 | .IX Item "-mbackchain" |
| 16659 | .PD 0 |
| 16660 | .IP "\fB\-mno\-backchain\fR" 4 |
| 16661 | .IX Item "-mno-backchain" |
| 16662 | .PD |
| 16663 | Store (do not store) the address of the caller's frame as backchain pointer |
| 16664 | into the callee's stack frame. |
| 16665 | A backchain may be needed to allow debugging using tools that do not understand |
| 16666 | \&\s-1DWARF\-2\s0 call frame information. |
| 16667 | When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored |
| 16668 | at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect, |
| 16669 | the backchain is placed into the topmost word of the 96/160 byte register |
| 16670 | save area. |
| 16671 | .Sp |
| 16672 | In general, code compiled with \fB\-mbackchain\fR is call-compatible with |
| 16673 | code compiled with \fB\-mmo\-backchain\fR; however, use of the backchain |
| 16674 | for debugging purposes usually requires that the whole binary is built with |
| 16675 | \&\fB\-mbackchain\fR. Note that the combination of \fB\-mbackchain\fR, |
| 16676 | \&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order |
| 16677 | to build a linux kernel use \fB\-msoft\-float\fR. |
| 16678 | .Sp |
| 16679 | The default is to not maintain the backchain. |
| 16680 | .IP "\fB\-mpacked\-stack\fR" 4 |
| 16681 | .IX Item "-mpacked-stack" |
| 16682 | .PD 0 |
| 16683 | .IP "\fB\-mno\-packed\-stack\fR" 4 |
| 16684 | .IX Item "-mno-packed-stack" |
| 16685 | .PD |
| 16686 | Use (do not use) the packed stack layout. When \fB\-mno\-packed\-stack\fR is |
| 16687 | specified, the compiler uses the all fields of the 96/160 byte register save |
| 16688 | area only for their default purpose; unused fields still take up stack space. |
| 16689 | When \fB\-mpacked\-stack\fR is specified, register save slots are densely |
| 16690 | packed at the top of the register save area; unused space is reused for other |
| 16691 | purposes, allowing for more efficient use of the available stack space. |
| 16692 | However, when \fB\-mbackchain\fR is also in effect, the topmost word of |
| 16693 | the save area is always used to store the backchain, and the return address |
| 16694 | register is always saved two words below the backchain. |
| 16695 | .Sp |
| 16696 | As long as the stack frame backchain is not used, code generated with |
| 16697 | \&\fB\-mpacked\-stack\fR is call-compatible with code generated with |
| 16698 | \&\fB\-mno\-packed\-stack\fR. Note that some non-FSF releases of \s-1GCC\s0 2.95 for |
| 16699 | S/390 or zSeries generated code that uses the stack frame backchain at run |
| 16700 | time, not just for debugging purposes. Such code is not call-compatible |
| 16701 | with code compiled with \fB\-mpacked\-stack\fR. Also, note that the |
| 16702 | combination of \fB\-mbackchain\fR, |
| 16703 | \&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported. In order |
| 16704 | to build a linux kernel use \fB\-msoft\-float\fR. |
| 16705 | .Sp |
| 16706 | The default is to not use the packed stack layout. |
| 16707 | .IP "\fB\-msmall\-exec\fR" 4 |
| 16708 | .IX Item "-msmall-exec" |
| 16709 | .PD 0 |
| 16710 | .IP "\fB\-mno\-small\-exec\fR" 4 |
| 16711 | .IX Item "-mno-small-exec" |
| 16712 | .PD |
| 16713 | Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction |
| 16714 | to do subroutine calls. |
| 16715 | This only works reliably if the total executable size does not |
| 16716 | exceed 64k. The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead, |
| 16717 | which does not have this limitation. |
| 16718 | .IP "\fB\-m64\fR" 4 |
| 16719 | .IX Item "-m64" |
| 16720 | .PD 0 |
| 16721 | .IP "\fB\-m31\fR" 4 |
| 16722 | .IX Item "-m31" |
| 16723 | .PD |
| 16724 | When \fB\-m31\fR is specified, generate code compliant to the |
| 16725 | GNU/Linux for S/390 \s-1ABI\s0. When \fB\-m64\fR is specified, generate |
| 16726 | code compliant to the GNU/Linux for zSeries \s-1ABI\s0. This allows \s-1GCC\s0 in |
| 16727 | particular to generate 64\-bit instructions. For the \fBs390\fR |
| 16728 | targets, the default is \fB\-m31\fR, while the \fBs390x\fR |
| 16729 | targets default to \fB\-m64\fR. |
| 16730 | .IP "\fB\-mzarch\fR" 4 |
| 16731 | .IX Item "-mzarch" |
| 16732 | .PD 0 |
| 16733 | .IP "\fB\-mesa\fR" 4 |
| 16734 | .IX Item "-mesa" |
| 16735 | .PD |
| 16736 | When \fB\-mzarch\fR is specified, generate code using the |
| 16737 | instructions available on z/Architecture. |
| 16738 | When \fB\-mesa\fR is specified, generate code using the |
| 16739 | instructions available on \s-1ESA/390\s0. Note that \fB\-mesa\fR is |
| 16740 | not possible with \fB\-m64\fR. |
| 16741 | When generating code compliant to the GNU/Linux for S/390 \s-1ABI\s0, |
| 16742 | the default is \fB\-mesa\fR. When generating code compliant |
| 16743 | to the GNU/Linux for zSeries \s-1ABI\s0, the default is \fB\-mzarch\fR. |
| 16744 | .IP "\fB\-mmvcle\fR" 4 |
| 16745 | .IX Item "-mmvcle" |
| 16746 | .PD 0 |
| 16747 | .IP "\fB\-mno\-mvcle\fR" 4 |
| 16748 | .IX Item "-mno-mvcle" |
| 16749 | .PD |
| 16750 | Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction |
| 16751 | to perform block moves. When \fB\-mno\-mvcle\fR is specified, |
| 16752 | use a \f(CW\*(C`mvc\*(C'\fR loop instead. This is the default unless optimizing for |
| 16753 | size. |
| 16754 | .IP "\fB\-mdebug\fR" 4 |
| 16755 | .IX Item "-mdebug" |
| 16756 | .PD 0 |
| 16757 | .IP "\fB\-mno\-debug\fR" 4 |
| 16758 | .IX Item "-mno-debug" |
| 16759 | .PD |
| 16760 | Print (or do not print) additional debug information when compiling. |
| 16761 | The default is to not print debug information. |
| 16762 | .IP "\fB\-march=\fR\fIcpu-type\fR" 4 |
| 16763 | .IX Item "-march=cpu-type" |
| 16764 | Generate code that will run on \fIcpu-type\fR, which is the name of a system |
| 16765 | representing a certain processor type. Possible values for |
| 16766 | \&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, \fBz990\fR, |
| 16767 | \&\fBz9\-109\fR, \fBz9\-ec\fR and \fBz10\fR. |
| 16768 | When generating code using the instructions available on z/Architecture, |
| 16769 | the default is \fB\-march=z900\fR. Otherwise, the default is |
| 16770 | \&\fB\-march=g5\fR. |
| 16771 | .IP "\fB\-mtune=\fR\fIcpu-type\fR" 4 |
| 16772 | .IX Item "-mtune=cpu-type" |
| 16773 | Tune to \fIcpu-type\fR everything applicable about the generated code, |
| 16774 | except for the \s-1ABI\s0 and the set of available instructions. |
| 16775 | The list of \fIcpu-type\fR values is the same as for \fB\-march\fR. |
| 16776 | The default is the value used for \fB\-march\fR. |
| 16777 | .IP "\fB\-mtpf\-trace\fR" 4 |
| 16778 | .IX Item "-mtpf-trace" |
| 16779 | .PD 0 |
| 16780 | .IP "\fB\-mno\-tpf\-trace\fR" 4 |
| 16781 | .IX Item "-mno-tpf-trace" |
| 16782 | .PD |
| 16783 | Generate code that adds (does not add) in \s-1TPF\s0 \s-1OS\s0 specific branches to trace |
| 16784 | routines in the operating system. This option is off by default, even |
| 16785 | when compiling for the \s-1TPF\s0 \s-1OS\s0. |
| 16786 | .IP "\fB\-mfused\-madd\fR" 4 |
| 16787 | .IX Item "-mfused-madd" |
| 16788 | .PD 0 |
| 16789 | .IP "\fB\-mno\-fused\-madd\fR" 4 |
| 16790 | .IX Item "-mno-fused-madd" |
| 16791 | .PD |
| 16792 | Generate code that uses (does not use) the floating-point multiply and |
| 16793 | accumulate instructions. These instructions are generated by default if |
| 16794 | hardware floating point is used. |
| 16795 | .IP "\fB\-mwarn\-framesize=\fR\fIframesize\fR" 4 |
| 16796 | .IX Item "-mwarn-framesize=framesize" |
| 16797 | Emit a warning if the current function exceeds the given frame size. Because |
| 16798 | this is a compile-time check it doesn't need to be a real problem when the program |
| 16799 | runs. It is intended to identify functions that most probably cause |
| 16800 | a stack overflow. It is useful to be used in an environment with limited stack |
| 16801 | size e.g. the linux kernel. |
| 16802 | .IP "\fB\-mwarn\-dynamicstack\fR" 4 |
| 16803 | .IX Item "-mwarn-dynamicstack" |
| 16804 | Emit a warning if the function calls alloca or uses dynamically |
| 16805 | sized arrays. This is generally a bad idea with a limited stack size. |
| 16806 | .IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4 |
| 16807 | .IX Item "-mstack-guard=stack-guard" |
| 16808 | .PD 0 |
| 16809 | .IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4 |
| 16810 | .IX Item "-mstack-size=stack-size" |
| 16811 | .PD |
| 16812 | If these options are provided the s390 back end emits additional instructions in |
| 16813 | the function prologue which trigger a trap if the stack size is \fIstack-guard\fR |
| 16814 | bytes above the \fIstack-size\fR (remember that the stack on s390 grows downward). |
| 16815 | If the \fIstack-guard\fR option is omitted the smallest power of 2 larger than |
| 16816 | the frame size of the compiled function is chosen. |
| 16817 | These options are intended to be used to help debugging stack overflow problems. |
| 16818 | The additionally emitted code causes only little overhead and hence can also be |
| 16819 | used in production like systems without greater performance degradation. The given |
| 16820 | values have to be exact powers of 2 and \fIstack-size\fR has to be greater than |
| 16821 | \&\fIstack-guard\fR without exceeding 64k. |
| 16822 | In order to be efficient the extra code makes the assumption that the stack starts |
| 16823 | at an address aligned to the value given by \fIstack-size\fR. |
| 16824 | The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. |
| 16825 | .PP |
| 16826 | \fIScore Options\fR |
| 16827 | .IX Subsection "Score Options" |
| 16828 | .PP |
| 16829 | These options are defined for Score implementations: |
| 16830 | .IP "\fB\-meb\fR" 4 |
| 16831 | .IX Item "-meb" |
| 16832 | Compile code for big-endian mode. This is the default. |
| 16833 | .IP "\fB\-mel\fR" 4 |
| 16834 | .IX Item "-mel" |
| 16835 | Compile code for little-endian mode. |
| 16836 | .IP "\fB\-mnhwloop\fR" 4 |
| 16837 | .IX Item "-mnhwloop" |
| 16838 | Disable generate bcnz instruction. |
| 16839 | .IP "\fB\-muls\fR" 4 |
| 16840 | .IX Item "-muls" |
| 16841 | Enable generate unaligned load and store instruction. |
| 16842 | .IP "\fB\-mmac\fR" 4 |
| 16843 | .IX Item "-mmac" |
| 16844 | Enable the use of multiply-accumulate instructions. Disabled by default. |
| 16845 | .IP "\fB\-mscore5\fR" 4 |
| 16846 | .IX Item "-mscore5" |
| 16847 | Specify the \s-1SCORE5\s0 as the target architecture. |
| 16848 | .IP "\fB\-mscore5u\fR" 4 |
| 16849 | .IX Item "-mscore5u" |
| 16850 | Specify the \s-1SCORE5U\s0 of the target architecture. |
| 16851 | .IP "\fB\-mscore7\fR" 4 |
| 16852 | .IX Item "-mscore7" |
| 16853 | Specify the \s-1SCORE7\s0 as the target architecture. This is the default. |
| 16854 | .IP "\fB\-mscore7d\fR" 4 |
| 16855 | .IX Item "-mscore7d" |
| 16856 | Specify the \s-1SCORE7D\s0 as the target architecture. |
| 16857 | .PP |
| 16858 | \fI\s-1SH\s0 Options\fR |
| 16859 | .IX Subsection "SH Options" |
| 16860 | .PP |
| 16861 | These \fB\-m\fR options are defined for the \s-1SH\s0 implementations: |
| 16862 | .IP "\fB\-m1\fR" 4 |
| 16863 | .IX Item "-m1" |
| 16864 | Generate code for the \s-1SH1\s0. |
| 16865 | .IP "\fB\-m2\fR" 4 |
| 16866 | .IX Item "-m2" |
| 16867 | Generate code for the \s-1SH2\s0. |
| 16868 | .IP "\fB\-m2e\fR" 4 |
| 16869 | .IX Item "-m2e" |
| 16870 | Generate code for the SH2e. |
| 16871 | .IP "\fB\-m2a\-nofpu\fR" 4 |
| 16872 | .IX Item "-m2a-nofpu" |
| 16873 | Generate code for the SH2a without \s-1FPU\s0, or for a SH2a\-FPU in such a way |
| 16874 | that the floating-point unit is not used. |
| 16875 | .IP "\fB\-m2a\-single\-only\fR" 4 |
| 16876 | .IX Item "-m2a-single-only" |
| 16877 | Generate code for the SH2a\-FPU, in such a way that no double-precision |
| 16878 | floating-point operations are used. |
| 16879 | .IP "\fB\-m2a\-single\fR" 4 |
| 16880 | .IX Item "-m2a-single" |
| 16881 | Generate code for the SH2a\-FPU assuming the floating-point unit is in |
| 16882 | single-precision mode by default. |
| 16883 | .IP "\fB\-m2a\fR" 4 |
| 16884 | .IX Item "-m2a" |
| 16885 | Generate code for the SH2a\-FPU assuming the floating-point unit is in |
| 16886 | double-precision mode by default. |
| 16887 | .IP "\fB\-m3\fR" 4 |
| 16888 | .IX Item "-m3" |
| 16889 | Generate code for the \s-1SH3\s0. |
| 16890 | .IP "\fB\-m3e\fR" 4 |
| 16891 | .IX Item "-m3e" |
| 16892 | Generate code for the SH3e. |
| 16893 | .IP "\fB\-m4\-nofpu\fR" 4 |
| 16894 | .IX Item "-m4-nofpu" |
| 16895 | Generate code for the \s-1SH4\s0 without a floating-point unit. |
| 16896 | .IP "\fB\-m4\-single\-only\fR" 4 |
| 16897 | .IX Item "-m4-single-only" |
| 16898 | Generate code for the \s-1SH4\s0 with a floating-point unit that only |
| 16899 | supports single-precision arithmetic. |
| 16900 | .IP "\fB\-m4\-single\fR" 4 |
| 16901 | .IX Item "-m4-single" |
| 16902 | Generate code for the \s-1SH4\s0 assuming the floating-point unit is in |
| 16903 | single-precision mode by default. |
| 16904 | .IP "\fB\-m4\fR" 4 |
| 16905 | .IX Item "-m4" |
| 16906 | Generate code for the \s-1SH4\s0. |
| 16907 | .IP "\fB\-m4a\-nofpu\fR" 4 |
| 16908 | .IX Item "-m4a-nofpu" |
| 16909 | Generate code for the SH4al\-dsp, or for a SH4a in such a way that the |
| 16910 | floating-point unit is not used. |
| 16911 | .IP "\fB\-m4a\-single\-only\fR" 4 |
| 16912 | .IX Item "-m4a-single-only" |
| 16913 | Generate code for the SH4a, in such a way that no double-precision |
| 16914 | floating-point operations are used. |
| 16915 | .IP "\fB\-m4a\-single\fR" 4 |
| 16916 | .IX Item "-m4a-single" |
| 16917 | Generate code for the SH4a assuming the floating-point unit is in |
| 16918 | single-precision mode by default. |
| 16919 | .IP "\fB\-m4a\fR" 4 |
| 16920 | .IX Item "-m4a" |
| 16921 | Generate code for the SH4a. |
| 16922 | .IP "\fB\-m4al\fR" 4 |
| 16923 | .IX Item "-m4al" |
| 16924 | Same as \fB\-m4a\-nofpu\fR, except that it implicitly passes |
| 16925 | \&\fB\-dsp\fR to the assembler. \s-1GCC\s0 doesn't generate any \s-1DSP\s0 |
| 16926 | instructions at the moment. |
| 16927 | .IP "\fB\-mb\fR" 4 |
| 16928 | .IX Item "-mb" |
| 16929 | Compile code for the processor in big-endian mode. |
| 16930 | .IP "\fB\-ml\fR" 4 |
| 16931 | .IX Item "-ml" |
| 16932 | Compile code for the processor in little-endian mode. |
| 16933 | .IP "\fB\-mdalign\fR" 4 |
| 16934 | .IX Item "-mdalign" |
| 16935 | Align doubles at 64\-bit boundaries. Note that this changes the calling |
| 16936 | conventions, and thus some functions from the standard C library will |
| 16937 | not work unless you recompile it first with \fB\-mdalign\fR. |
| 16938 | .IP "\fB\-mrelax\fR" 4 |
| 16939 | .IX Item "-mrelax" |
| 16940 | Shorten some address references at link time, when possible; uses the |
| 16941 | linker option \fB\-relax\fR. |
| 16942 | .IP "\fB\-mbigtable\fR" 4 |
| 16943 | .IX Item "-mbigtable" |
| 16944 | Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables. The default is to use |
| 16945 | 16\-bit offsets. |
| 16946 | .IP "\fB\-mbitops\fR" 4 |
| 16947 | .IX Item "-mbitops" |
| 16948 | Enable the use of bit manipulation instructions on \s-1SH2A\s0. |
| 16949 | .IP "\fB\-mfmovd\fR" 4 |
| 16950 | .IX Item "-mfmovd" |
| 16951 | Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR. Check \fB\-mdalign\fR for |
| 16952 | alignment constraints. |
| 16953 | .IP "\fB\-mhitachi\fR" 4 |
| 16954 | .IX Item "-mhitachi" |
| 16955 | Comply with the calling conventions defined by Renesas. |
| 16956 | .IP "\fB\-mrenesas\fR" 4 |
| 16957 | .IX Item "-mrenesas" |
| 16958 | Comply with the calling conventions defined by Renesas. |
| 16959 | .IP "\fB\-mno\-renesas\fR" 4 |
| 16960 | .IX Item "-mno-renesas" |
| 16961 | Comply with the calling conventions defined for \s-1GCC\s0 before the Renesas |
| 16962 | conventions were available. This option is the default for all |
| 16963 | targets of the \s-1SH\s0 toolchain. |
| 16964 | .IP "\fB\-mnomacsave\fR" 4 |
| 16965 | .IX Item "-mnomacsave" |
| 16966 | Mark the \f(CW\*(C`MAC\*(C'\fR register as call-clobbered, even if |
| 16967 | \&\fB\-mhitachi\fR is given. |
| 16968 | .IP "\fB\-mieee\fR" 4 |
| 16969 | .IX Item "-mieee" |
| 16970 | .PD 0 |
| 16971 | .IP "\fB\-mno\-ieee\fR" 4 |
| 16972 | .IX Item "-mno-ieee" |
| 16973 | .PD |
| 16974 | Control the \s-1IEEE\s0 compliance of floating-point comparisons, which affects the |
| 16975 | handling of cases where the result of a comparison is unordered. By default |
| 16976 | \&\fB\-mieee\fR is implicitly enabled. If \fB\-ffinite\-math\-only\fR is |
| 16977 | enabled \fB\-mno\-ieee\fR is implicitly set, which results in faster |
| 16978 | floating-point greater-equal and less-equal comparisons. The implcit settings |
| 16979 | can be overridden by specifying either \fB\-mieee\fR or \fB\-mno\-ieee\fR. |
| 16980 | .IP "\fB\-minline\-ic_invalidate\fR" 4 |
| 16981 | .IX Item "-minline-ic_invalidate" |
| 16982 | Inline code to invalidate instruction cache entries after setting up |
| 16983 | nested function trampolines. |
| 16984 | This option has no effect if \-musermode is in effect and the selected |
| 16985 | code generation option (e.g. \-m4) does not allow the use of the icbi |
| 16986 | instruction. |
| 16987 | If the selected code generation option does not allow the use of the icbi |
| 16988 | instruction, and \-musermode is not in effect, the inlined code will |
| 16989 | manipulate the instruction cache address array directly with an associative |
| 16990 | write. This not only requires privileged mode, but it will also |
| 16991 | fail if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped. |
| 16992 | .IP "\fB\-misize\fR" 4 |
| 16993 | .IX Item "-misize" |
| 16994 | Dump instruction size and location in the assembly code. |
| 16995 | .IP "\fB\-mpadstruct\fR" 4 |
| 16996 | .IX Item "-mpadstruct" |
| 16997 | This option is deprecated. It pads structures to multiple of 4 bytes, |
| 16998 | which is incompatible with the \s-1SH\s0 \s-1ABI\s0. |
| 16999 | .IP "\fB\-msoft\-atomic\fR" 4 |
| 17000 | .IX Item "-msoft-atomic" |
| 17001 | Generate GNU/Linux compatible gUSA software atomic sequences for the atomic |
| 17002 | built-in functions. The generated atomic sequences require support from the |
| 17003 | interrupt / exception handling code of the system and are only suitable for |
| 17004 | single-core systems. They will not perform correctly on multi-core systems. |
| 17005 | This option is enabled by default when the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR. |
| 17006 | For details on the atomic built-in functions see \fB_\|_atomic Builtins\fR. |
| 17007 | .IP "\fB\-mspace\fR" 4 |
| 17008 | .IX Item "-mspace" |
| 17009 | Optimize for space instead of speed. Implied by \fB\-Os\fR. |
| 17010 | .IP "\fB\-mprefergot\fR" 4 |
| 17011 | .IX Item "-mprefergot" |
| 17012 | When generating position-independent code, emit function calls using |
| 17013 | the Global Offset Table instead of the Procedure Linkage Table. |
| 17014 | .IP "\fB\-musermode\fR" 4 |
| 17015 | .IX Item "-musermode" |
| 17016 | Don't generate privileged mode only code; implies \-mno\-inline\-ic_invalidate |
| 17017 | if the inlined code would not work in user mode. |
| 17018 | This is the default when the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR. |
| 17019 | .IP "\fB\-multcost=\fR\fInumber\fR" 4 |
| 17020 | .IX Item "-multcost=number" |
| 17021 | Set the cost to assume for a multiply insn. |
| 17022 | .IP "\fB\-mdiv=\fR\fIstrategy\fR" 4 |
| 17023 | .IX Item "-mdiv=strategy" |
| 17024 | Set the division strategy to be used for integer division operations. |
| 17025 | For SHmedia \fIstrategy\fR can be one of: |
| 17026 | .RS 4 |
| 17027 | .IP "\fBfp\fR" 4 |
| 17028 | .IX Item "fp" |
| 17029 | Performs the operation in floating point. This has a very high latency, |
| 17030 | but needs only a few instructions, so it might be a good choice if |
| 17031 | your code has enough easily-exploitable \s-1ILP\s0 to allow the compiler to |
| 17032 | schedule the floating-point instructions together with other instructions. |
| 17033 | Division by zero causes a floating-point exception. |
| 17034 | .IP "\fBinv\fR" 4 |
| 17035 | .IX Item "inv" |
| 17036 | Uses integer operations to calculate the inverse of the divisor, |
| 17037 | and then multiplies the dividend with the inverse. This strategy allows |
| 17038 | \&\s-1CSE\s0 and hoisting of the inverse calculation. Division by zero calculates |
| 17039 | an unspecified result, but does not trap. |
| 17040 | .IP "\fBinv:minlat\fR" 4 |
| 17041 | .IX Item "inv:minlat" |
| 17042 | A variant of \fBinv\fR where, if no \s-1CSE\s0 or hoisting opportunities |
| 17043 | have been found, or if the entire operation has been hoisted to the same |
| 17044 | place, the last stages of the inverse calculation are intertwined with the |
| 17045 | final multiply to reduce the overall latency, at the expense of using a few |
| 17046 | more instructions, and thus offering fewer scheduling opportunities with |
| 17047 | other code. |
| 17048 | .IP "\fBcall\fR" 4 |
| 17049 | .IX Item "call" |
| 17050 | Calls a library function that usually implements the \fBinv:minlat\fR |
| 17051 | strategy. |
| 17052 | This gives high code density for \f(CW\*(C`m5\-*media\-nofpu\*(C'\fR compilations. |
| 17053 | .IP "\fBcall2\fR" 4 |
| 17054 | .IX Item "call2" |
| 17055 | Uses a different entry point of the same library function, where it |
| 17056 | assumes that a pointer to a lookup table has already been set up, which |
| 17057 | exposes the pointer load to \s-1CSE\s0 and code hoisting optimizations. |
| 17058 | .IP "\fBinv:call\fR" 4 |
| 17059 | .IX Item "inv:call" |
| 17060 | .PD 0 |
| 17061 | .IP "\fBinv:call2\fR" 4 |
| 17062 | .IX Item "inv:call2" |
| 17063 | .IP "\fBinv:fp\fR" 4 |
| 17064 | .IX Item "inv:fp" |
| 17065 | .PD |
| 17066 | Use the \fBinv\fR algorithm for initial |
| 17067 | code generation, but if the code stays unoptimized, revert to the \fBcall\fR, |
| 17068 | \&\fBcall2\fR, or \fBfp\fR strategies, respectively. Note that the |
| 17069 | potentially-trapping side effect of division by zero is carried by a |
| 17070 | separate instruction, so it is possible that all the integer instructions |
| 17071 | are hoisted out, but the marker for the side effect stays where it is. |
| 17072 | A recombination to floating-point operations or a call is not possible |
| 17073 | in that case. |
| 17074 | .IP "\fBinv20u\fR" 4 |
| 17075 | .IX Item "inv20u" |
| 17076 | .PD 0 |
| 17077 | .IP "\fBinv20l\fR" 4 |
| 17078 | .IX Item "inv20l" |
| 17079 | .PD |
| 17080 | Variants of the \fBinv:minlat\fR strategy. In the case |
| 17081 | that the inverse calculation is not separated from the multiply, they speed |
| 17082 | up division where the dividend fits into 20 bits (plus sign where applicable) |
| 17083 | by inserting a test to skip a number of operations in this case; this test |
| 17084 | slows down the case of larger dividends. \fBinv20u\fR assumes the case of a such |
| 17085 | a small dividend to be unlikely, and \fBinv20l\fR assumes it to be likely. |
| 17086 | .RE |
| 17087 | .RS 4 |
| 17088 | .Sp |
| 17089 | For targets other than SHmedia \fIstrategy\fR can be one of: |
| 17090 | .IP "\fBcall\-div1\fR" 4 |
| 17091 | .IX Item "call-div1" |
| 17092 | Calls a library function that uses the single-step division instruction |
| 17093 | \&\f(CW\*(C`div1\*(C'\fR to perform the operation. Division by zero calculates an |
| 17094 | unspecified result and does not trap. This is the default except for \s-1SH4\s0, |
| 17095 | \&\s-1SH2A\s0 and SHcompact. |
| 17096 | .IP "\fBcall-fp\fR" 4 |
| 17097 | .IX Item "call-fp" |
| 17098 | Calls a library function that performs the operation in double precision |
| 17099 | floating point. Division by zero causes a floating-point exception. This is |
| 17100 | the default for SHcompact with \s-1FPU\s0. Specifying this for targets that do not |
| 17101 | have a double precision \s-1FPU\s0 will default to \f(CW\*(C`call\-div1\*(C'\fR. |
| 17102 | .IP "\fBcall-table\fR" 4 |
| 17103 | .IX Item "call-table" |
| 17104 | Calls a library function that uses a lookup table for small divisors and |
| 17105 | the \f(CW\*(C`div1\*(C'\fR instruction with case distinction for larger divisors. Division |
| 17106 | by zero calculates an unspecified result and does not trap. This is the default |
| 17107 | for \s-1SH4\s0. Specifying this for targets that do not have dynamic shift |
| 17108 | instructions will default to \f(CW\*(C`call\-div1\*(C'\fR. |
| 17109 | .RE |
| 17110 | .RS 4 |
| 17111 | .Sp |
| 17112 | When a division strategy has not been specified the default strategy will be |
| 17113 | selected based on the current target. For \s-1SH2A\s0 the default strategy is to |
| 17114 | use the \f(CW\*(C`divs\*(C'\fR and \f(CW\*(C`divu\*(C'\fR instructions instead of library function |
| 17115 | calls. |
| 17116 | .RE |
| 17117 | .IP "\fB\-maccumulate\-outgoing\-args\fR" 4 |
| 17118 | .IX Item "-maccumulate-outgoing-args" |
| 17119 | Reserve space once for outgoing arguments in the function prologue rather |
| 17120 | than around each call. Generally beneficial for performance and size. Also |
| 17121 | needed for unwinding to avoid changing the stack frame around conditional code. |
| 17122 | .IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4 |
| 17123 | .IX Item "-mdivsi3_libfunc=name" |
| 17124 | Set the name of the library function used for 32\-bit signed division to |
| 17125 | \&\fIname\fR. This only affect the name used in the call and inv:call |
| 17126 | division strategies, and the compiler will still expect the same |
| 17127 | sets of input/output/clobbered registers as if this option was not present. |
| 17128 | .IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 |
| 17129 | .IX Item "-mfixed-range=register-range" |
| 17130 | Generate code treating the given register range as fixed registers. |
| 17131 | A fixed register is one that the register allocator can not use. This is |
| 17132 | useful when compiling kernel code. A register range is specified as |
| 17133 | two registers separated by a dash. Multiple register ranges can be |
| 17134 | specified separated by a comma. |
| 17135 | .IP "\fB\-madjust\-unroll\fR" 4 |
| 17136 | .IX Item "-madjust-unroll" |
| 17137 | Throttle unrolling to avoid thrashing target registers. |
| 17138 | This option only has an effect if the gcc code base supports the |
| 17139 | \&\s-1TARGET_ADJUST_UNROLL_MAX\s0 target hook. |
| 17140 | .IP "\fB\-mindexed\-addressing\fR" 4 |
| 17141 | .IX Item "-mindexed-addressing" |
| 17142 | Enable the use of the indexed addressing mode for SHmedia32/SHcompact. |
| 17143 | This is only safe if the hardware and/or \s-1OS\s0 implement 32\-bit wrap-around |
| 17144 | semantics for the indexed addressing mode. The architecture allows the |
| 17145 | implementation of processors with 64\-bit \s-1MMU\s0, which the \s-1OS\s0 could use to |
| 17146 | get 32\-bit addressing, but since no current hardware implementation supports |
| 17147 | this or any other way to make the indexed addressing mode safe to use in |
| 17148 | the 32\-bit \s-1ABI\s0, the default is \fB\-mno\-indexed\-addressing\fR. |
| 17149 | .IP "\fB\-mgettrcost=\fR\fInumber\fR" 4 |
| 17150 | .IX Item "-mgettrcost=number" |
| 17151 | Set the cost assumed for the gettr instruction to \fInumber\fR. |
| 17152 | The default is 2 if \fB\-mpt\-fixed\fR is in effect, 100 otherwise. |
| 17153 | .IP "\fB\-mpt\-fixed\fR" 4 |
| 17154 | .IX Item "-mpt-fixed" |
| 17155 | Assume pt* instructions won't trap. This will generally generate better |
| 17156 | scheduled code, but is unsafe on current hardware. The current architecture |
| 17157 | definition says that ptabs and ptrel trap when the target anded with 3 is 3. |
| 17158 | This has the unintentional effect of making it unsafe to schedule ptabs / |
| 17159 | ptrel before a branch, or hoist it out of a loop. For example, |
| 17160 | _\|_do_global_ctors, a part of libgcc that runs constructors at program |
| 17161 | startup, calls functions in a list which is delimited by \-1. With the |
| 17162 | \&\-mpt\-fixed option, the ptabs will be done before testing against \-1. |
| 17163 | That means that all the constructors will be run a bit quicker, but when |
| 17164 | the loop comes to the end of the list, the program crashes because ptabs |
| 17165 | loads \-1 into a target register. Since this option is unsafe for any |
| 17166 | hardware implementing the current architecture specification, the default |
| 17167 | is \-mno\-pt\-fixed. Unless the user specifies a specific cost with |
| 17168 | \&\fB\-mgettrcost\fR, \-mno\-pt\-fixed also implies \fB\-mgettrcost=100\fR; |
| 17169 | this deters register allocation using target registers for storing |
| 17170 | ordinary integers. |
| 17171 | .IP "\fB\-minvalid\-symbols\fR" 4 |
| 17172 | .IX Item "-minvalid-symbols" |
| 17173 | Assume symbols might be invalid. Ordinary function symbols generated by |
| 17174 | the compiler will always be valid to load with movi/shori/ptabs or |
| 17175 | movi/shori/ptrel, but with assembler and/or linker tricks it is possible |
| 17176 | to generate symbols that will cause ptabs / ptrel to trap. |
| 17177 | This option is only meaningful when \fB\-mno\-pt\-fixed\fR is in effect. |
| 17178 | It will then prevent cross-basic-block cse, hoisting and most scheduling |
| 17179 | of symbol loads. The default is \fB\-mno\-invalid\-symbols\fR. |
| 17180 | .IP "\fB\-mbranch\-cost=\fR\fInum\fR" 4 |
| 17181 | .IX Item "-mbranch-cost=num" |
| 17182 | Assume \fInum\fR to be the cost for a branch instruction. Higher numbers |
| 17183 | will make the compiler try to generate more branch-free code if possible. |
| 17184 | If not specified the value is selected depending on the processor type that |
| 17185 | is being compiled for. |
| 17186 | .IP "\fB\-mcbranchdi\fR" 4 |
| 17187 | .IX Item "-mcbranchdi" |
| 17188 | Enable the \f(CW\*(C`cbranchdi4\*(C'\fR instruction pattern. |
| 17189 | .IP "\fB\-mcmpeqdi\fR" 4 |
| 17190 | .IX Item "-mcmpeqdi" |
| 17191 | Emit the \f(CW\*(C`cmpeqdi_t\*(C'\fR instruction pattern even when \fB\-mcbranchdi\fR |
| 17192 | is in effect. |
| 17193 | .IP "\fB\-mfused\-madd\fR" 4 |
| 17194 | .IX Item "-mfused-madd" |
| 17195 | Allow the usage of the \f(CW\*(C`fmac\*(C'\fR instruction (floating-point |
| 17196 | multiply-accumulate) if the processor type supports it. Enabling this |
| 17197 | option might generate code that produces different numeric floating-point |
| 17198 | results compared to strict \s-1IEEE\s0 754 arithmetic. |
| 17199 | .IP "\fB\-mpretend\-cmove\fR" 4 |
| 17200 | .IX Item "-mpretend-cmove" |
| 17201 | Prefer zero-displacement conditional branches for conditional move instruction |
| 17202 | patterns. This can result in faster code on the \s-1SH4\s0 processor. |
| 17203 | .PP |
| 17204 | \fISolaris 2 Options\fR |
| 17205 | .IX Subsection "Solaris 2 Options" |
| 17206 | .PP |
| 17207 | These \fB\-m\fR options are supported on Solaris 2: |
| 17208 | .IP "\fB\-mimpure\-text\fR" 4 |
| 17209 | .IX Item "-mimpure-text" |
| 17210 | \&\fB\-mimpure\-text\fR, used in addition to \fB\-shared\fR, tells |
| 17211 | the compiler to not pass \fB\-z text\fR to the linker when linking a |
| 17212 | shared object. Using this option, you can link position-dependent |
| 17213 | code into a shared object. |
| 17214 | .Sp |
| 17215 | \&\fB\-mimpure\-text\fR suppresses the \*(L"relocations remain against |
| 17216 | allocatable but non-writable sections\*(R" linker error message. |
| 17217 | However, the necessary relocations will trigger copy-on-write, and the |
| 17218 | shared object is not actually shared across processes. Instead of |
| 17219 | using \fB\-mimpure\-text\fR, you should compile all source code with |
| 17220 | \&\fB\-fpic\fR or \fB\-fPIC\fR. |
| 17221 | .PP |
| 17222 | These switches are supported in addition to the above on Solaris 2: |
| 17223 | .IP "\fB\-pthreads\fR" 4 |
| 17224 | .IX Item "-pthreads" |
| 17225 | Add support for multithreading using the \s-1POSIX\s0 threads library. This |
| 17226 | option sets flags for both the preprocessor and linker. This option does |
| 17227 | not affect the thread safety of object code produced by the compiler or |
| 17228 | that of libraries supplied with it. |
| 17229 | .IP "\fB\-pthread\fR" 4 |
| 17230 | .IX Item "-pthread" |
| 17231 | This is a synonym for \fB\-pthreads\fR. |
| 17232 | .PP |
| 17233 | \fI\s-1SPARC\s0 Options\fR |
| 17234 | .IX Subsection "SPARC Options" |
| 17235 | .PP |
| 17236 | These \fB\-m\fR options are supported on the \s-1SPARC:\s0 |
| 17237 | .IP "\fB\-mno\-app\-regs\fR" 4 |
| 17238 | .IX Item "-mno-app-regs" |
| 17239 | .PD 0 |
| 17240 | .IP "\fB\-mapp\-regs\fR" 4 |
| 17241 | .IX Item "-mapp-regs" |
| 17242 | .PD |
| 17243 | Specify \fB\-mapp\-regs\fR to generate output using the global registers |
| 17244 | 2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. Like the |
| 17245 | global register 1, each global register 2 through 4 is then treated as an |
| 17246 | allocable register that is clobbered by function calls. This is the default. |
| 17247 | .Sp |
| 17248 | To be fully \s-1SVR4\s0 \s-1ABI\s0 compliant at the cost of some performance loss, |
| 17249 | specify \fB\-mno\-app\-regs\fR. You should compile libraries and system |
| 17250 | software with this option. |
| 17251 | .IP "\fB\-mflat\fR" 4 |
| 17252 | .IX Item "-mflat" |
| 17253 | .PD 0 |
| 17254 | .IP "\fB\-mno\-flat\fR" 4 |
| 17255 | .IX Item "-mno-flat" |
| 17256 | .PD |
| 17257 | With \fB\-mflat\fR, the compiler does not generate save/restore instructions |
| 17258 | and uses a \*(L"flat\*(R" or single register window model. This model is compatible |
| 17259 | with the regular register window model. The local registers and the input |
| 17260 | registers (0\-\-5) are still treated as \*(L"call-saved\*(R" registers and will be |
| 17261 | saved on the stack as needed. |
| 17262 | .Sp |
| 17263 | With \fB\-mno\-flat\fR (the default), the compiler generates save/restore |
| 17264 | instructions (except for leaf functions). This is the normal operating mode. |
| 17265 | .IP "\fB\-mfpu\fR" 4 |
| 17266 | .IX Item "-mfpu" |
| 17267 | .PD 0 |
| 17268 | .IP "\fB\-mhard\-float\fR" 4 |
| 17269 | .IX Item "-mhard-float" |
| 17270 | .PD |
| 17271 | Generate output containing floating-point instructions. This is the |
| 17272 | default. |
| 17273 | .IP "\fB\-mno\-fpu\fR" 4 |
| 17274 | .IX Item "-mno-fpu" |
| 17275 | .PD 0 |
| 17276 | .IP "\fB\-msoft\-float\fR" 4 |
| 17277 | .IX Item "-msoft-float" |
| 17278 | .PD |
| 17279 | Generate output containing library calls for floating point. |
| 17280 | \&\fBWarning:\fR the requisite libraries are not available for all \s-1SPARC\s0 |
| 17281 | targets. Normally the facilities of the machine's usual C compiler are |
| 17282 | used, but this cannot be done directly in cross-compilation. You must make |
| 17283 | your own arrangements to provide suitable library functions for |
| 17284 | cross-compilation. The embedded targets \fBsparc\-*\-aout\fR and |
| 17285 | \&\fBsparclite\-*\-*\fR do provide software floating-point support. |
| 17286 | .Sp |
| 17287 | \&\fB\-msoft\-float\fR changes the calling convention in the output file; |
| 17288 | therefore, it is only useful if you compile \fIall\fR of a program with |
| 17289 | this option. In particular, you need to compile \fIlibgcc.a\fR, the |
| 17290 | library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for |
| 17291 | this to work. |
| 17292 | .IP "\fB\-mhard\-quad\-float\fR" 4 |
| 17293 | .IX Item "-mhard-quad-float" |
| 17294 | Generate output containing quad-word (long double) floating-point |
| 17295 | instructions. |
| 17296 | .IP "\fB\-msoft\-quad\-float\fR" 4 |
| 17297 | .IX Item "-msoft-quad-float" |
| 17298 | Generate output containing library calls for quad-word (long double) |
| 17299 | floating-point instructions. The functions called are those specified |
| 17300 | in the \s-1SPARC\s0 \s-1ABI\s0. This is the default. |
| 17301 | .Sp |
| 17302 | As of this writing, there are no \s-1SPARC\s0 implementations that have hardware |
| 17303 | support for the quad-word floating-point instructions. They all invoke |
| 17304 | a trap handler for one of these instructions, and then the trap handler |
| 17305 | emulates the effect of the instruction. Because of the trap handler overhead, |
| 17306 | this is much slower than calling the \s-1ABI\s0 library routines. Thus the |
| 17307 | \&\fB\-msoft\-quad\-float\fR option is the default. |
| 17308 | .IP "\fB\-mno\-unaligned\-doubles\fR" 4 |
| 17309 | .IX Item "-mno-unaligned-doubles" |
| 17310 | .PD 0 |
| 17311 | .IP "\fB\-munaligned\-doubles\fR" 4 |
| 17312 | .IX Item "-munaligned-doubles" |
| 17313 | .PD |
| 17314 | Assume that doubles have 8\-byte alignment. This is the default. |
| 17315 | .Sp |
| 17316 | With \fB\-munaligned\-doubles\fR, \s-1GCC\s0 assumes that doubles have 8\-byte |
| 17317 | alignment only if they are contained in another type, or if they have an |
| 17318 | absolute address. Otherwise, it assumes they have 4\-byte alignment. |
| 17319 | Specifying this option avoids some rare compatibility problems with code |
| 17320 | generated by other compilers. It is not the default because it results |
| 17321 | in a performance loss, especially for floating-point code. |
| 17322 | .IP "\fB\-mno\-faster\-structs\fR" 4 |
| 17323 | .IX Item "-mno-faster-structs" |
| 17324 | .PD 0 |
| 17325 | .IP "\fB\-mfaster\-structs\fR" 4 |
| 17326 | .IX Item "-mfaster-structs" |
| 17327 | .PD |
| 17328 | With \fB\-mfaster\-structs\fR, the compiler assumes that structures |
| 17329 | should have 8\-byte alignment. This enables the use of pairs of |
| 17330 | \&\f(CW\*(C`ldd\*(C'\fR and \f(CW\*(C`std\*(C'\fR instructions for copies in structure |
| 17331 | assignment, in place of twice as many \f(CW\*(C`ld\*(C'\fR and \f(CW\*(C`st\*(C'\fR pairs. |
| 17332 | However, the use of this changed alignment directly violates the \s-1SPARC\s0 |
| 17333 | \&\s-1ABI\s0. Thus, it's intended only for use on targets where the developer |
| 17334 | acknowledges that their resulting code will not be directly in line with |
| 17335 | the rules of the \s-1ABI\s0. |
| 17336 | .IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4 |
| 17337 | .IX Item "-mcpu=cpu_type" |
| 17338 | Set the instruction set, register set, and instruction scheduling parameters |
| 17339 | for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are |
| 17340 | \&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, |
| 17341 | \&\fBleon\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, |
| 17342 | \&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, |
| 17343 | \&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR, |
| 17344 | and \fBniagara4\fR. |
| 17345 | .Sp |
| 17346 | Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, |
| 17347 | which selects the best architecture option for the host processor. |
| 17348 | \&\fB\-mcpu=native\fR has no effect if \s-1GCC\s0 does not recognize |
| 17349 | the processor. |
| 17350 | .Sp |
| 17351 | Default instruction scheduling parameters are used for values that select |
| 17352 | an architecture and not an implementation. These are \fBv7\fR, \fBv8\fR, |
| 17353 | \&\fBsparclite\fR, \fBsparclet\fR, \fBv9\fR. |
| 17354 | .Sp |
| 17355 | Here is a list of each supported architecture and their supported |
| 17356 | implementations. |
| 17357 | .RS 4 |
| 17358 | .IP "v7" 4 |
| 17359 | .IX Item "v7" |
| 17360 | cypress |
| 17361 | .IP "v8" 4 |
| 17362 | .IX Item "v8" |
| 17363 | supersparc, hypersparc, leon |
| 17364 | .IP "sparclite" 4 |
| 17365 | .IX Item "sparclite" |
| 17366 | f930, f934, sparclite86x |
| 17367 | .IP "sparclet" 4 |
| 17368 | .IX Item "sparclet" |
| 17369 | tsc701 |
| 17370 | .IP "v9" 4 |
| 17371 | .IX Item "v9" |
| 17372 | ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4 |
| 17373 | .RE |
| 17374 | .RS 4 |
| 17375 | .Sp |
| 17376 | By default (unless configured otherwise), \s-1GCC\s0 generates code for the V7 |
| 17377 | variant of the \s-1SPARC\s0 architecture. With \fB\-mcpu=cypress\fR, the compiler |
| 17378 | additionally optimizes it for the Cypress \s-1CY7C602\s0 chip, as used in the |
| 17379 | SPARCStation/SPARCServer 3xx series. This is also appropriate for the older |
| 17380 | SPARCStation 1, 2, \s-1IPX\s0 etc. |
| 17381 | .Sp |
| 17382 | With \fB\-mcpu=v8\fR, \s-1GCC\s0 generates code for the V8 variant of the \s-1SPARC\s0 |
| 17383 | architecture. The only difference from V7 code is that the compiler emits |
| 17384 | the integer multiply and integer divide instructions which exist in \s-1SPARC\-V8\s0 |
| 17385 | but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=supersparc\fR, the compiler additionally |
| 17386 | optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and |
| 17387 | 2000 series. |
| 17388 | .Sp |
| 17389 | With \fB\-mcpu=sparclite\fR, \s-1GCC\s0 generates code for the SPARClite variant of |
| 17390 | the \s-1SPARC\s0 architecture. This adds the integer multiply, integer divide step |
| 17391 | and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClite but not in \s-1SPARC\-V7\s0. |
| 17392 | With \fB\-mcpu=f930\fR, the compiler additionally optimizes it for the |
| 17393 | Fujitsu \s-1MB86930\s0 chip, which is the original SPARClite, with no \s-1FPU\s0. With |
| 17394 | \&\fB\-mcpu=f934\fR, the compiler additionally optimizes it for the Fujitsu |
| 17395 | \&\s-1MB86934\s0 chip, which is the more recent SPARClite with \s-1FPU\s0. |
| 17396 | .Sp |
| 17397 | With \fB\-mcpu=sparclet\fR, \s-1GCC\s0 generates code for the SPARClet variant of |
| 17398 | the \s-1SPARC\s0 architecture. This adds the integer multiply, multiply/accumulate, |
| 17399 | integer divide step and scan (\f(CW\*(C`ffs\*(C'\fR) instructions which exist in SPARClet |
| 17400 | but not in \s-1SPARC\-V7\s0. With \fB\-mcpu=tsc701\fR, the compiler additionally |
| 17401 | optimizes it for the \s-1TEMIC\s0 SPARClet chip. |
| 17402 | .Sp |
| 17403 | With \fB\-mcpu=v9\fR, \s-1GCC\s0 generates code for the V9 variant of the \s-1SPARC\s0 |
| 17404 | architecture. This adds 64\-bit integer and floating-point move instructions, |
| 17405 | 3 additional floating-point condition code registers and conditional move |
| 17406 | instructions. With \fB\-mcpu=ultrasparc\fR, the compiler additionally |
| 17407 | optimizes it for the Sun UltraSPARC I/II/IIi chips. With |
| 17408 | \&\fB\-mcpu=ultrasparc3\fR, the compiler additionally optimizes it for the |
| 17409 | Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With |
| 17410 | \&\fB\-mcpu=niagara\fR, the compiler additionally optimizes it for |
| 17411 | Sun UltraSPARC T1 chips. With \fB\-mcpu=niagara2\fR, the compiler |
| 17412 | additionally optimizes it for Sun UltraSPARC T2 chips. With |
| 17413 | \&\fB\-mcpu=niagara3\fR, the compiler additionally optimizes it for Sun |
| 17414 | UltraSPARC T3 chips. With \fB\-mcpu=niagara4\fR, the compiler |
| 17415 | additionally optimizes it for Sun UltraSPARC T4 chips. |
| 17416 | .RE |
| 17417 | .IP "\fB\-mtune=\fR\fIcpu_type\fR" 4 |
| 17418 | .IX Item "-mtune=cpu_type" |
| 17419 | Set the instruction scheduling parameters for machine type |
| 17420 | \&\fIcpu_type\fR, but do not set the instruction set or register set that the |
| 17421 | option \fB\-mcpu=\fR\fIcpu_type\fR would. |
| 17422 | .Sp |
| 17423 | The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for |
| 17424 | \&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those |
| 17425 | that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, |
| 17426 | \&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBf930\fR, \fBf934\fR, |
| 17427 | \&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, \fBultrasparc3\fR, |
| 17428 | \&\fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and \fBniagara4\fR. With |
| 17429 | native Solaris and GNU/Linux toolchains, \fBnative\fR can also be used. |
| 17430 | .IP "\fB\-mv8plus\fR" 4 |
| 17431 | .IX Item "-mv8plus" |
| 17432 | .PD 0 |
| 17433 | .IP "\fB\-mno\-v8plus\fR" 4 |
| 17434 | .IX Item "-mno-v8plus" |
| 17435 | .PD |
| 17436 | With \fB\-mv8plus\fR, \s-1GCC\s0 generates code for the \s-1SPARC\-V8+\s0 \s-1ABI\s0. The |
| 17437 | difference from the V8 \s-1ABI\s0 is that the global and out registers are |
| 17438 | considered 64 bits wide. This is enabled by default on Solaris in 32\-bit |
| 17439 | mode for all \s-1SPARC\-V9\s0 processors. |
| 17440 | .IP "\fB\-mvis\fR" 4 |
| 17441 | .IX Item "-mvis" |
| 17442 | .PD 0 |
| 17443 | .IP "\fB\-mno\-vis\fR" 4 |
| 17444 | .IX Item "-mno-vis" |
| 17445 | .PD |
| 17446 | With \fB\-mvis\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC |
| 17447 | Visual Instruction Set extensions. The default is \fB\-mno\-vis\fR. |
| 17448 | .IP "\fB\-mvis2\fR" 4 |
| 17449 | .IX Item "-mvis2" |
| 17450 | .PD 0 |
| 17451 | .IP "\fB\-mno\-vis2\fR" 4 |
| 17452 | .IX Item "-mno-vis2" |
| 17453 | .PD |
| 17454 | With \fB\-mvis2\fR, \s-1GCC\s0 generates code that takes advantage of |
| 17455 | version 2.0 of the UltraSPARC Visual Instruction Set extensions. The |
| 17456 | default is \fB\-mvis2\fR when targetting a cpu that supports such |
| 17457 | instructions, such as UltraSPARC-III and later. Setting \fB\-mvis2\fR |
| 17458 | also sets \fB\-mvis\fR. |
| 17459 | .IP "\fB\-mvis3\fR" 4 |
| 17460 | .IX Item "-mvis3" |
| 17461 | .PD 0 |
| 17462 | .IP "\fB\-mno\-vis3\fR" 4 |
| 17463 | .IX Item "-mno-vis3" |
| 17464 | .PD |
| 17465 | With \fB\-mvis3\fR, \s-1GCC\s0 generates code that takes advantage of |
| 17466 | version 3.0 of the UltraSPARC Visual Instruction Set extensions. The |
| 17467 | default is \fB\-mvis3\fR when targetting a cpu that supports such |
| 17468 | instructions, such as niagara\-3 and later. Setting \fB\-mvis3\fR |
| 17469 | also sets \fB\-mvis2\fR and \fB\-mvis\fR. |
| 17470 | .IP "\fB\-mpopc\fR" 4 |
| 17471 | .IX Item "-mpopc" |
| 17472 | .PD 0 |
| 17473 | .IP "\fB\-mno\-popc\fR" 4 |
| 17474 | .IX Item "-mno-popc" |
| 17475 | .PD |
| 17476 | With \fB\-mpopc\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC |
| 17477 | population count instruction. The default is \fB\-mpopc\fR |
| 17478 | when targetting a cpu that supports such instructions, such as Niagara\-2 and |
| 17479 | later. |
| 17480 | .IP "\fB\-mfmaf\fR" 4 |
| 17481 | .IX Item "-mfmaf" |
| 17482 | .PD 0 |
| 17483 | .IP "\fB\-mno\-fmaf\fR" 4 |
| 17484 | .IX Item "-mno-fmaf" |
| 17485 | .PD |
| 17486 | With \fB\-mfmaf\fR, \s-1GCC\s0 generates code that takes advantage of the UltraSPARC |
| 17487 | Fused Multiply-Add Floating-point extensions. The default is \fB\-mfmaf\fR |
| 17488 | when targetting a cpu that supports such instructions, such as Niagara\-3 and |
| 17489 | later. |
| 17490 | .IP "\fB\-mfix\-at697f\fR" 4 |
| 17491 | .IX Item "-mfix-at697f" |
| 17492 | Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 |
| 17493 | processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). |
| 17494 | .PP |
| 17495 | These \fB\-m\fR options are supported in addition to the above |
| 17496 | on \s-1SPARC\-V9\s0 processors in 64\-bit environments: |
| 17497 | .IP "\fB\-m32\fR" 4 |
| 17498 | .IX Item "-m32" |
| 17499 | .PD 0 |
| 17500 | .IP "\fB\-m64\fR" 4 |
| 17501 | .IX Item "-m64" |
| 17502 | .PD |
| 17503 | Generate code for a 32\-bit or 64\-bit environment. |
| 17504 | The 32\-bit environment sets int, long and pointer to 32 bits. |
| 17505 | The 64\-bit environment sets int to 32 bits and long and pointer |
| 17506 | to 64 bits. |
| 17507 | .IP "\fB\-mcmodel=\fR\fIwhich\fR" 4 |
| 17508 | .IX Item "-mcmodel=which" |
| 17509 | Set the code model to one of |
| 17510 | .RS 4 |
| 17511 | .IP "\fBmedlow\fR" 4 |
| 17512 | .IX Item "medlow" |
| 17513 | The Medium/Low code model: 64\-bit addresses, programs |
| 17514 | must be linked in the low 32 bits of memory. Programs can be statically |
| 17515 | or dynamically linked. |
| 17516 | .IP "\fBmedmid\fR" 4 |
| 17517 | .IX Item "medmid" |
| 17518 | The Medium/Middle code model: 64\-bit addresses, programs |
| 17519 | must be linked in the low 44 bits of memory, the text and data segments must |
| 17520 | be less than 2GB in size and the data segment must be located within 2GB of |
| 17521 | the text segment. |
| 17522 | .IP "\fBmedany\fR" 4 |
| 17523 | .IX Item "medany" |
| 17524 | The Medium/Anywhere code model: 64\-bit addresses, programs |
| 17525 | may be linked anywhere in memory, the text and data segments must be less |
| 17526 | than 2GB in size and the data segment must be located within 2GB of the |
| 17527 | text segment. |
| 17528 | .IP "\fBembmedany\fR" 4 |
| 17529 | .IX Item "embmedany" |
| 17530 | The Medium/Anywhere code model for embedded systems: |
| 17531 | 64\-bit addresses, the text and data segments must be less than 2GB in |
| 17532 | size, both starting anywhere in memory (determined at link time). The |
| 17533 | global register \f(CW%g4\fR points to the base of the data segment. Programs |
| 17534 | are statically linked and \s-1PIC\s0 is not supported. |
| 17535 | .RE |
| 17536 | .RS 4 |
| 17537 | .RE |
| 17538 | .IP "\fB\-mmemory\-model=\fR\fImem-model\fR" 4 |
| 17539 | .IX Item "-mmemory-model=mem-model" |
| 17540 | Set the memory model in force on the processor to one of |
| 17541 | .RS 4 |
| 17542 | .IP "\fBdefault\fR" 4 |
| 17543 | .IX Item "default" |
| 17544 | The default memory model for the processor and operating system. |
| 17545 | .IP "\fBrmo\fR" 4 |
| 17546 | .IX Item "rmo" |
| 17547 | Relaxed Memory Order |
| 17548 | .IP "\fBpso\fR" 4 |
| 17549 | .IX Item "pso" |
| 17550 | Partial Store Order |
| 17551 | .IP "\fBtso\fR" 4 |
| 17552 | .IX Item "tso" |
| 17553 | Total Store Order |
| 17554 | .IP "\fBsc\fR" 4 |
| 17555 | .IX Item "sc" |
| 17556 | Sequential Consistency |
| 17557 | .RE |
| 17558 | .RS 4 |
| 17559 | .Sp |
| 17560 | These memory models are formally defined in Appendix D of the Sparc V9 |
| 17561 | architecture manual, as set in the processor's \f(CW\*(C`PSTATE.MM\*(C'\fR field. |
| 17562 | .RE |
| 17563 | .IP "\fB\-mstack\-bias\fR" 4 |
| 17564 | .IX Item "-mstack-bias" |
| 17565 | .PD 0 |
| 17566 | .IP "\fB\-mno\-stack\-bias\fR" 4 |
| 17567 | .IX Item "-mno-stack-bias" |
| 17568 | .PD |
| 17569 | With \fB\-mstack\-bias\fR, \s-1GCC\s0 assumes that the stack pointer, and |
| 17570 | frame pointer if present, are offset by \-2047 which must be added back |
| 17571 | when making stack frame references. This is the default in 64\-bit mode. |
| 17572 | Otherwise, assume no such offset is present. |
| 17573 | .PP |
| 17574 | \fI\s-1SPU\s0 Options\fR |
| 17575 | .IX Subsection "SPU Options" |
| 17576 | .PP |
| 17577 | These \fB\-m\fR options are supported on the \s-1SPU:\s0 |
| 17578 | .IP "\fB\-mwarn\-reloc\fR" 4 |
| 17579 | .IX Item "-mwarn-reloc" |
| 17580 | .PD 0 |
| 17581 | .IP "\fB\-merror\-reloc\fR" 4 |
| 17582 | .IX Item "-merror-reloc" |
| 17583 | .PD |
| 17584 | The loader for \s-1SPU\s0 does not handle dynamic relocations. By default, \s-1GCC\s0 |
| 17585 | will give an error when it generates code that requires a dynamic |
| 17586 | relocation. \fB\-mno\-error\-reloc\fR disables the error, |
| 17587 | \&\fB\-mwarn\-reloc\fR will generate a warning instead. |
| 17588 | .IP "\fB\-msafe\-dma\fR" 4 |
| 17589 | .IX Item "-msafe-dma" |
| 17590 | .PD 0 |
| 17591 | .IP "\fB\-munsafe\-dma\fR" 4 |
| 17592 | .IX Item "-munsafe-dma" |
| 17593 | .PD |
| 17594 | Instructions that initiate or test completion of \s-1DMA\s0 must not be |
| 17595 | reordered with respect to loads and stores of the memory that is being |
| 17596 | accessed. Users typically address this problem using the volatile |
| 17597 | keyword, but that can lead to inefficient code in places where the |
| 17598 | memory is known to not change. Rather than mark the memory as volatile |
| 17599 | we treat the \s-1DMA\s0 instructions as potentially effecting all memory. With |
| 17600 | \&\fB\-munsafe\-dma\fR users must use the volatile keyword to protect |
| 17601 | memory accesses. |
| 17602 | .IP "\fB\-mbranch\-hints\fR" 4 |
| 17603 | .IX Item "-mbranch-hints" |
| 17604 | By default, \s-1GCC\s0 will generate a branch hint instruction to avoid |
| 17605 | pipeline stalls for always taken or probably taken branches. A hint |
| 17606 | will not be generated closer than 8 instructions away from its branch. |
| 17607 | There is little reason to disable them, except for debugging purposes, |
| 17608 | or to make an object a little bit smaller. |
| 17609 | .IP "\fB\-msmall\-mem\fR" 4 |
| 17610 | .IX Item "-msmall-mem" |
| 17611 | .PD 0 |
| 17612 | .IP "\fB\-mlarge\-mem\fR" 4 |
| 17613 | .IX Item "-mlarge-mem" |
| 17614 | .PD |
| 17615 | By default, \s-1GCC\s0 generates code assuming that addresses are never larger |
| 17616 | than 18 bits. With \fB\-mlarge\-mem\fR code is generated that assumes |
| 17617 | a full 32\-bit address. |
| 17618 | .IP "\fB\-mstdmain\fR" 4 |
| 17619 | .IX Item "-mstdmain" |
| 17620 | By default, \s-1GCC\s0 links against startup code that assumes the SPU-style |
| 17621 | main function interface (which has an unconventional parameter list). |
| 17622 | With \fB\-mstdmain\fR, \s-1GCC\s0 will link your program against startup |
| 17623 | code that assumes a C99\-style interface to \f(CW\*(C`main\*(C'\fR, including a |
| 17624 | local copy of \f(CW\*(C`argv\*(C'\fR strings. |
| 17625 | .IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4 |
| 17626 | .IX Item "-mfixed-range=register-range" |
| 17627 | Generate code treating the given register range as fixed registers. |
| 17628 | A fixed register is one that the register allocator can not use. This is |
| 17629 | useful when compiling kernel code. A register range is specified as |
| 17630 | two registers separated by a dash. Multiple register ranges can be |
| 17631 | specified separated by a comma. |
| 17632 | .IP "\fB\-mea32\fR" 4 |
| 17633 | .IX Item "-mea32" |
| 17634 | .PD 0 |
| 17635 | .IP "\fB\-mea64\fR" 4 |
| 17636 | .IX Item "-mea64" |
| 17637 | .PD |
| 17638 | Compile code assuming that pointers to the \s-1PPU\s0 address space accessed |
| 17639 | via the \f(CW\*(C`_\|_ea\*(C'\fR named address space qualifier are either 32 or 64 |
| 17640 | bits wide. The default is 32 bits. As this is an \s-1ABI\s0 changing option, |
| 17641 | all object code in an executable must be compiled with the same setting. |
| 17642 | .IP "\fB\-maddress\-space\-conversion\fR" 4 |
| 17643 | .IX Item "-maddress-space-conversion" |
| 17644 | .PD 0 |
| 17645 | .IP "\fB\-mno\-address\-space\-conversion\fR" 4 |
| 17646 | .IX Item "-mno-address-space-conversion" |
| 17647 | .PD |
| 17648 | Allow/disallow treating the \f(CW\*(C`_\|_ea\*(C'\fR address space as superset |
| 17649 | of the generic address space. This enables explicit type casts |
| 17650 | between \f(CW\*(C`_\|_ea\*(C'\fR and generic pointer as well as implicit |
| 17651 | conversions of generic pointers to \f(CW\*(C`_\|_ea\*(C'\fR pointers. The |
| 17652 | default is to allow address space pointer conversions. |
| 17653 | .IP "\fB\-mcache\-size=\fR\fIcache-size\fR" 4 |
| 17654 | .IX Item "-mcache-size=cache-size" |
| 17655 | This option controls the version of libgcc that the compiler links to an |
| 17656 | executable and selects a software-managed cache for accessing variables |
| 17657 | in the \f(CW\*(C`_\|_ea\*(C'\fR address space with a particular cache size. Possible |
| 17658 | options for \fIcache-size\fR are \fB8\fR, \fB16\fR, \fB32\fR, \fB64\fR |
| 17659 | and \fB128\fR. The default cache size is 64KB. |
| 17660 | .IP "\fB\-matomic\-updates\fR" 4 |
| 17661 | .IX Item "-matomic-updates" |
| 17662 | .PD 0 |
| 17663 | .IP "\fB\-mno\-atomic\-updates\fR" 4 |
| 17664 | .IX Item "-mno-atomic-updates" |
| 17665 | .PD |
| 17666 | This option controls the version of libgcc that the compiler links to an |
| 17667 | executable and selects whether atomic updates to the software-managed |
| 17668 | cache of PPU-side variables are used. If you use atomic updates, changes |
| 17669 | to a \s-1PPU\s0 variable from \s-1SPU\s0 code using the \f(CW\*(C`_\|_ea\*(C'\fR named address space |
| 17670 | qualifier will not interfere with changes to other \s-1PPU\s0 variables residing |
| 17671 | in the same cache line from \s-1PPU\s0 code. If you do not use atomic updates, |
| 17672 | such interference may occur; however, writing back cache lines will be |
| 17673 | more efficient. The default behavior is to use atomic updates. |
| 17674 | .IP "\fB\-mdual\-nops\fR" 4 |
| 17675 | .IX Item "-mdual-nops" |
| 17676 | .PD 0 |
| 17677 | .IP "\fB\-mdual\-nops=\fR\fIn\fR" 4 |
| 17678 | .IX Item "-mdual-nops=n" |
| 17679 | .PD |
| 17680 | By default, \s-1GCC\s0 will insert nops to increase dual issue when it expects |
| 17681 | it to increase performance. \fIn\fR can be a value from 0 to 10. A |
| 17682 | smaller \fIn\fR will insert fewer nops. 10 is the default, 0 is the |
| 17683 | same as \fB\-mno\-dual\-nops\fR. Disabled with \fB\-Os\fR. |
| 17684 | .IP "\fB\-mhint\-max\-nops=\fR\fIn\fR" 4 |
| 17685 | .IX Item "-mhint-max-nops=n" |
| 17686 | Maximum number of nops to insert for a branch hint. A branch hint must |
| 17687 | be at least 8 instructions away from the branch it is effecting. \s-1GCC\s0 |
| 17688 | will insert up to \fIn\fR nops to enforce this, otherwise it will not |
| 17689 | generate the branch hint. |
| 17690 | .IP "\fB\-mhint\-max\-distance=\fR\fIn\fR" 4 |
| 17691 | .IX Item "-mhint-max-distance=n" |
| 17692 | The encoding of the branch hint instruction limits the hint to be within |
| 17693 | 256 instructions of the branch it is effecting. By default, \s-1GCC\s0 makes |
| 17694 | sure it is within 125. |
| 17695 | .IP "\fB\-msafe\-hints\fR" 4 |
| 17696 | .IX Item "-msafe-hints" |
| 17697 | Work around a hardware bug that causes the \s-1SPU\s0 to stall indefinitely. |
| 17698 | By default, \s-1GCC\s0 will insert the \f(CW\*(C`hbrp\*(C'\fR instruction to make sure |
| 17699 | this stall won't happen. |
| 17700 | .PP |
| 17701 | \fIOptions for System V\fR |
| 17702 | .IX Subsection "Options for System V" |
| 17703 | .PP |
| 17704 | These additional options are available on System V Release 4 for |
| 17705 | compatibility with other compilers on those systems: |
| 17706 | .IP "\fB\-G\fR" 4 |
| 17707 | .IX Item "-G" |
| 17708 | Create a shared object. |
| 17709 | It is recommended that \fB\-symbolic\fR or \fB\-shared\fR be used instead. |
| 17710 | .IP "\fB\-Qy\fR" 4 |
| 17711 | .IX Item "-Qy" |
| 17712 | Identify the versions of each tool used by the compiler, in a |
| 17713 | \&\f(CW\*(C`.ident\*(C'\fR assembler directive in the output. |
| 17714 | .IP "\fB\-Qn\fR" 4 |
| 17715 | .IX Item "-Qn" |
| 17716 | Refrain from adding \f(CW\*(C`.ident\*(C'\fR directives to the output file (this is |
| 17717 | the default). |
| 17718 | .IP "\fB\-YP,\fR\fIdirs\fR" 4 |
| 17719 | .IX Item "-YP,dirs" |
| 17720 | Search the directories \fIdirs\fR, and no others, for libraries |
| 17721 | specified with \fB\-l\fR. |
| 17722 | .IP "\fB\-Ym,\fR\fIdir\fR" 4 |
| 17723 | .IX Item "-Ym,dir" |
| 17724 | Look in the directory \fIdir\fR to find the M4 preprocessor. |
| 17725 | The assembler uses this option. |
| 17726 | .PP |
| 17727 | \fITILE-Gx Options\fR |
| 17728 | .IX Subsection "TILE-Gx Options" |
| 17729 | .PP |
| 17730 | These \fB\-m\fR options are supported on the TILE-Gx: |
| 17731 | .IP "\fB\-mcpu=\fR\fIname\fR" 4 |
| 17732 | .IX Item "-mcpu=name" |
| 17733 | Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported |
| 17734 | type is \fBtilegx\fR. |
| 17735 | .IP "\fB\-m32\fR" 4 |
| 17736 | .IX Item "-m32" |
| 17737 | .PD 0 |
| 17738 | .IP "\fB\-m64\fR" 4 |
| 17739 | .IX Item "-m64" |
| 17740 | .PD |
| 17741 | Generate code for a 32\-bit or 64\-bit environment. The 32\-bit |
| 17742 | environment sets int, long, and pointer to 32 bits. The 64\-bit |
| 17743 | environment sets int to 32 bits and long and pointer to 64 bits. |
| 17744 | .PP |
| 17745 | \fITILEPro Options\fR |
| 17746 | .IX Subsection "TILEPro Options" |
| 17747 | .PP |
| 17748 | These \fB\-m\fR options are supported on the TILEPro: |
| 17749 | .IP "\fB\-mcpu=\fR\fIname\fR" 4 |
| 17750 | .IX Item "-mcpu=name" |
| 17751 | Selects the type of \s-1CPU\s0 to be targeted. Currently the only supported |
| 17752 | type is \fBtilepro\fR. |
| 17753 | .IP "\fB\-m32\fR" 4 |
| 17754 | .IX Item "-m32" |
| 17755 | Generate code for a 32\-bit environment, which sets int, long, and |
| 17756 | pointer to 32 bits. This is the only supported behavior so the flag |
| 17757 | is essentially ignored. |
| 17758 | .PP |
| 17759 | \fIV850 Options\fR |
| 17760 | .IX Subsection "V850 Options" |
| 17761 | .PP |
| 17762 | These \fB\-m\fR options are defined for V850 implementations: |
| 17763 | .IP "\fB\-mlong\-calls\fR" 4 |
| 17764 | .IX Item "-mlong-calls" |
| 17765 | .PD 0 |
| 17766 | .IP "\fB\-mno\-long\-calls\fR" 4 |
| 17767 | .IX Item "-mno-long-calls" |
| 17768 | .PD |
| 17769 | Treat all calls as being far away (near). If calls are assumed to be |
| 17770 | far away, the compiler will always load the functions address up into a |
| 17771 | register, and call indirect through the pointer. |
| 17772 | .IP "\fB\-mno\-ep\fR" 4 |
| 17773 | .IX Item "-mno-ep" |
| 17774 | .PD 0 |
| 17775 | .IP "\fB\-mep\fR" 4 |
| 17776 | .IX Item "-mep" |
| 17777 | .PD |
| 17778 | Do not optimize (do optimize) basic blocks that use the same index |
| 17779 | pointer 4 or more times to copy pointer into the \f(CW\*(C`ep\*(C'\fR register, and |
| 17780 | use the shorter \f(CW\*(C`sld\*(C'\fR and \f(CW\*(C`sst\*(C'\fR instructions. The \fB\-mep\fR |
| 17781 | option is on by default if you optimize. |
| 17782 | .IP "\fB\-mno\-prolog\-function\fR" 4 |
| 17783 | .IX Item "-mno-prolog-function" |
| 17784 | .PD 0 |
| 17785 | .IP "\fB\-mprolog\-function\fR" 4 |
| 17786 | .IX Item "-mprolog-function" |
| 17787 | .PD |
| 17788 | Do not use (do use) external functions to save and restore registers |
| 17789 | at the prologue and epilogue of a function. The external functions |
| 17790 | are slower, but use less code space if more than one function saves |
| 17791 | the same number of registers. The \fB\-mprolog\-function\fR option |
| 17792 | is on by default if you optimize. |
| 17793 | .IP "\fB\-mspace\fR" 4 |
| 17794 | .IX Item "-mspace" |
| 17795 | Try to make the code as small as possible. At present, this just turns |
| 17796 | on the \fB\-mep\fR and \fB\-mprolog\-function\fR options. |
| 17797 | .IP "\fB\-mtda=\fR\fIn\fR" 4 |
| 17798 | .IX Item "-mtda=n" |
| 17799 | Put static or global variables whose size is \fIn\fR bytes or less into |
| 17800 | the tiny data area that register \f(CW\*(C`ep\*(C'\fR points to. The tiny data |
| 17801 | area can hold up to 256 bytes in total (128 bytes for byte references). |
| 17802 | .IP "\fB\-msda=\fR\fIn\fR" 4 |
| 17803 | .IX Item "-msda=n" |
| 17804 | Put static or global variables whose size is \fIn\fR bytes or less into |
| 17805 | the small data area that register \f(CW\*(C`gp\*(C'\fR points to. The small data |
| 17806 | area can hold up to 64 kilobytes. |
| 17807 | .IP "\fB\-mzda=\fR\fIn\fR" 4 |
| 17808 | .IX Item "-mzda=n" |
| 17809 | Put static or global variables whose size is \fIn\fR bytes or less into |
| 17810 | the first 32 kilobytes of memory. |
| 17811 | .IP "\fB\-mv850\fR" 4 |
| 17812 | .IX Item "-mv850" |
| 17813 | Specify that the target processor is the V850. |
| 17814 | .IP "\fB\-mbig\-switch\fR" 4 |
| 17815 | .IX Item "-mbig-switch" |
| 17816 | Generate code suitable for big switch tables. Use this option only if |
| 17817 | the assembler/linker complain about out of range branches within a switch |
| 17818 | table. |
| 17819 | .IP "\fB\-mapp\-regs\fR" 4 |
| 17820 | .IX Item "-mapp-regs" |
| 17821 | This option will cause r2 and r5 to be used in the code generated by |
| 17822 | the compiler. This setting is the default. |
| 17823 | .IP "\fB\-mno\-app\-regs\fR" 4 |
| 17824 | .IX Item "-mno-app-regs" |
| 17825 | This option will cause r2 and r5 to be treated as fixed registers. |
| 17826 | .IP "\fB\-mv850e2v3\fR" 4 |
| 17827 | .IX Item "-mv850e2v3" |
| 17828 | Specify that the target processor is the V850E2V3. The preprocessor |
| 17829 | constants \fB_\|_v850e2v3_\|_\fR will be defined if |
| 17830 | this option is used. |
| 17831 | .IP "\fB\-mv850e2\fR" 4 |
| 17832 | .IX Item "-mv850e2" |
| 17833 | Specify that the target processor is the V850E2. The preprocessor |
| 17834 | constants \fB_\|_v850e2_\|_\fR will be defined if this option is used. |
| 17835 | .IP "\fB\-mv850e1\fR" 4 |
| 17836 | .IX Item "-mv850e1" |
| 17837 | Specify that the target processor is the V850E1. The preprocessor |
| 17838 | constants \fB_\|_v850e1_\|_\fR and \fB_\|_v850e_\|_\fR will be defined if |
| 17839 | this option is used. |
| 17840 | .IP "\fB\-mv850es\fR" 4 |
| 17841 | .IX Item "-mv850es" |
| 17842 | Specify that the target processor is the V850ES. This is an alias for |
| 17843 | the \fB\-mv850e1\fR option. |
| 17844 | .IP "\fB\-mv850e\fR" 4 |
| 17845 | .IX Item "-mv850e" |
| 17846 | Specify that the target processor is the V850E. The preprocessor |
| 17847 | constant \fB_\|_v850e_\|_\fR will be defined if this option is used. |
| 17848 | .Sp |
| 17849 | If neither \fB\-mv850\fR nor \fB\-mv850e\fR nor \fB\-mv850e1\fR |
| 17850 | nor \fB\-mv850e2\fR nor \fB\-mv850e2v3\fR |
| 17851 | are defined then a default target processor will be chosen and the |
| 17852 | relevant \fB_\|_v850*_\|_\fR preprocessor constant will be defined. |
| 17853 | .Sp |
| 17854 | The preprocessor constants \fB_\|_v850\fR and \fB_\|_v851_\|_\fR are always |
| 17855 | defined, regardless of which processor variant is the target. |
| 17856 | .IP "\fB\-mdisable\-callt\fR" 4 |
| 17857 | .IX Item "-mdisable-callt" |
| 17858 | This option will suppress generation of the \s-1CALLT\s0 instruction for the |
| 17859 | v850e, v850e1, v850e2 and v850e2v3 flavors of the v850 architecture. The default is |
| 17860 | \&\fB\-mno\-disable\-callt\fR which allows the \s-1CALLT\s0 instruction to be used. |
| 17861 | .PP |
| 17862 | \fI\s-1VAX\s0 Options\fR |
| 17863 | .IX Subsection "VAX Options" |
| 17864 | .PP |
| 17865 | These \fB\-m\fR options are defined for the \s-1VAX:\s0 |
| 17866 | .IP "\fB\-munix\fR" 4 |
| 17867 | .IX Item "-munix" |
| 17868 | Do not output certain jump instructions (\f(CW\*(C`aobleq\*(C'\fR and so on) |
| 17869 | that the Unix assembler for the \s-1VAX\s0 cannot handle across long |
| 17870 | ranges. |
| 17871 | .IP "\fB\-mgnu\fR" 4 |
| 17872 | .IX Item "-mgnu" |
| 17873 | Do output those jump instructions, on the assumption that you |
| 17874 | will assemble with the \s-1GNU\s0 assembler. |
| 17875 | .IP "\fB\-mg\fR" 4 |
| 17876 | .IX Item "-mg" |
| 17877 | Output code for G\-format floating-point numbers instead of D\-format. |
| 17878 | .PP |
| 17879 | \fIVxWorks Options\fR |
| 17880 | .IX Subsection "VxWorks Options" |
| 17881 | .PP |
| 17882 | The options in this section are defined for all VxWorks targets. |
| 17883 | Options specific to the target hardware are listed with the other |
| 17884 | options for that target. |
| 17885 | .IP "\fB\-mrtp\fR" 4 |
| 17886 | .IX Item "-mrtp" |
| 17887 | \&\s-1GCC\s0 can generate code for both VxWorks kernels and real time processes |
| 17888 | (RTPs). This option switches from the former to the latter. It also |
| 17889 | defines the preprocessor macro \f(CW\*(C`_\|_RTP_\|_\*(C'\fR. |
| 17890 | .IP "\fB\-non\-static\fR" 4 |
| 17891 | .IX Item "-non-static" |
| 17892 | Link an \s-1RTP\s0 executable against shared libraries rather than static |
| 17893 | libraries. The options \fB\-static\fR and \fB\-shared\fR can |
| 17894 | also be used for RTPs; \fB\-static\fR |
| 17895 | is the default. |
| 17896 | .IP "\fB\-Bstatic\fR" 4 |
| 17897 | .IX Item "-Bstatic" |
| 17898 | .PD 0 |
| 17899 | .IP "\fB\-Bdynamic\fR" 4 |
| 17900 | .IX Item "-Bdynamic" |
| 17901 | .PD |
| 17902 | These options are passed down to the linker. They are defined for |
| 17903 | compatibility with Diab. |
| 17904 | .IP "\fB\-Xbind\-lazy\fR" 4 |
| 17905 | .IX Item "-Xbind-lazy" |
| 17906 | Enable lazy binding of function calls. This option is equivalent to |
| 17907 | \&\fB\-Wl,\-z,now\fR and is defined for compatibility with Diab. |
| 17908 | .IP "\fB\-Xbind\-now\fR" 4 |
| 17909 | .IX Item "-Xbind-now" |
| 17910 | Disable lazy binding of function calls. This option is the default and |
| 17911 | is defined for compatibility with Diab. |
| 17912 | .PP |
| 17913 | \fIx86\-64 Options\fR |
| 17914 | .IX Subsection "x86-64 Options" |
| 17915 | .PP |
| 17916 | These are listed under |
| 17917 | .PP |
| 17918 | \fIXstormy16 Options\fR |
| 17919 | .IX Subsection "Xstormy16 Options" |
| 17920 | .PP |
| 17921 | These options are defined for Xstormy16: |
| 17922 | .IP "\fB\-msim\fR" 4 |
| 17923 | .IX Item "-msim" |
| 17924 | Choose startup files and linker script suitable for the simulator. |
| 17925 | .PP |
| 17926 | \fIXtensa Options\fR |
| 17927 | .IX Subsection "Xtensa Options" |
| 17928 | .PP |
| 17929 | These options are supported for Xtensa targets: |
| 17930 | .IP "\fB\-mconst16\fR" 4 |
| 17931 | .IX Item "-mconst16" |
| 17932 | .PD 0 |
| 17933 | .IP "\fB\-mno\-const16\fR" 4 |
| 17934 | .IX Item "-mno-const16" |
| 17935 | .PD |
| 17936 | Enable or disable use of \f(CW\*(C`CONST16\*(C'\fR instructions for loading |
| 17937 | constant values. The \f(CW\*(C`CONST16\*(C'\fR instruction is currently not a |
| 17938 | standard option from Tensilica. When enabled, \f(CW\*(C`CONST16\*(C'\fR |
| 17939 | instructions are always used in place of the standard \f(CW\*(C`L32R\*(C'\fR |
| 17940 | instructions. The use of \f(CW\*(C`CONST16\*(C'\fR is enabled by default only if |
| 17941 | the \f(CW\*(C`L32R\*(C'\fR instruction is not available. |
| 17942 | .IP "\fB\-mfused\-madd\fR" 4 |
| 17943 | .IX Item "-mfused-madd" |
| 17944 | .PD 0 |
| 17945 | .IP "\fB\-mno\-fused\-madd\fR" 4 |
| 17946 | .IX Item "-mno-fused-madd" |
| 17947 | .PD |
| 17948 | Enable or disable use of fused multiply/add and multiply/subtract |
| 17949 | instructions in the floating-point option. This has no effect if the |
| 17950 | floating-point option is not also enabled. Disabling fused multiply/add |
| 17951 | and multiply/subtract instructions forces the compiler to use separate |
| 17952 | instructions for the multiply and add/subtract operations. This may be |
| 17953 | desirable in some cases where strict \s-1IEEE\s0 754\-compliant results are |
| 17954 | required: the fused multiply add/subtract instructions do not round the |
| 17955 | intermediate result, thereby producing results with \fImore\fR bits of |
| 17956 | precision than specified by the \s-1IEEE\s0 standard. Disabling fused multiply |
| 17957 | add/subtract instructions also ensures that the program output is not |
| 17958 | sensitive to the compiler's ability to combine multiply and add/subtract |
| 17959 | operations. |
| 17960 | .IP "\fB\-mserialize\-volatile\fR" 4 |
| 17961 | .IX Item "-mserialize-volatile" |
| 17962 | .PD 0 |
| 17963 | .IP "\fB\-mno\-serialize\-volatile\fR" 4 |
| 17964 | .IX Item "-mno-serialize-volatile" |
| 17965 | .PD |
| 17966 | When this option is enabled, \s-1GCC\s0 inserts \f(CW\*(C`MEMW\*(C'\fR instructions before |
| 17967 | \&\f(CW\*(C`volatile\*(C'\fR memory references to guarantee sequential consistency. |
| 17968 | The default is \fB\-mserialize\-volatile\fR. Use |
| 17969 | \&\fB\-mno\-serialize\-volatile\fR to omit the \f(CW\*(C`MEMW\*(C'\fR instructions. |
| 17970 | .IP "\fB\-mforce\-no\-pic\fR" 4 |
| 17971 | .IX Item "-mforce-no-pic" |
| 17972 | For targets, like GNU/Linux, where all user-mode Xtensa code must be |
| 17973 | position-independent code (\s-1PIC\s0), this option disables \s-1PIC\s0 for compiling |
| 17974 | kernel code. |
| 17975 | .IP "\fB\-mtext\-section\-literals\fR" 4 |
| 17976 | .IX Item "-mtext-section-literals" |
| 17977 | .PD 0 |
| 17978 | .IP "\fB\-mno\-text\-section\-literals\fR" 4 |
| 17979 | .IX Item "-mno-text-section-literals" |
| 17980 | .PD |
| 17981 | Control the treatment of literal pools. The default is |
| 17982 | \&\fB\-mno\-text\-section\-literals\fR, which places literals in a separate |
| 17983 | section in the output file. This allows the literal pool to be placed |
| 17984 | in a data \s-1RAM/ROM\s0, and it also allows the linker to combine literal |
| 17985 | pools from separate object files to remove redundant literals and |
| 17986 | improve code size. With \fB\-mtext\-section\-literals\fR, the literals |
| 17987 | are interspersed in the text section in order to keep them as close as |
| 17988 | possible to their references. This may be necessary for large assembly |
| 17989 | files. |
| 17990 | .IP "\fB\-mtarget\-align\fR" 4 |
| 17991 | .IX Item "-mtarget-align" |
| 17992 | .PD 0 |
| 17993 | .IP "\fB\-mno\-target\-align\fR" 4 |
| 17994 | .IX Item "-mno-target-align" |
| 17995 | .PD |
| 17996 | When this option is enabled, \s-1GCC\s0 instructs the assembler to |
| 17997 | automatically align instructions to reduce branch penalties at the |
| 17998 | expense of some code density. The assembler attempts to widen density |
| 17999 | instructions to align branch targets and the instructions following call |
| 18000 | instructions. If there are not enough preceding safe density |
| 18001 | instructions to align a target, no widening will be performed. The |
| 18002 | default is \fB\-mtarget\-align\fR. These options do not affect the |
| 18003 | treatment of auto-aligned instructions like \f(CW\*(C`LOOP\*(C'\fR, which the |
| 18004 | assembler will always align, either by widening density instructions or |
| 18005 | by inserting no-op instructions. |
| 18006 | .IP "\fB\-mlongcalls\fR" 4 |
| 18007 | .IX Item "-mlongcalls" |
| 18008 | .PD 0 |
| 18009 | .IP "\fB\-mno\-longcalls\fR" 4 |
| 18010 | .IX Item "-mno-longcalls" |
| 18011 | .PD |
| 18012 | When this option is enabled, \s-1GCC\s0 instructs the assembler to translate |
| 18013 | direct calls to indirect calls unless it can determine that the target |
| 18014 | of a direct call is in the range allowed by the call instruction. This |
| 18015 | translation typically occurs for calls to functions in other source |
| 18016 | files. Specifically, the assembler translates a direct \f(CW\*(C`CALL\*(C'\fR |
| 18017 | instruction into an \f(CW\*(C`L32R\*(C'\fR followed by a \f(CW\*(C`CALLX\*(C'\fR instruction. |
| 18018 | The default is \fB\-mno\-longcalls\fR. This option should be used in |
| 18019 | programs where the call target can potentially be out of range. This |
| 18020 | option is implemented in the assembler, not the compiler, so the |
| 18021 | assembly code generated by \s-1GCC\s0 will still show direct call |
| 18022 | instructions\-\-\-look at the disassembled object code to see the actual |
| 18023 | instructions. Note that the assembler will use an indirect call for |
| 18024 | every cross-file call, not just those that really will be out of range. |
| 18025 | .PP |
| 18026 | \fIzSeries Options\fR |
| 18027 | .IX Subsection "zSeries Options" |
| 18028 | .PP |
| 18029 | These are listed under |
| 18030 | .Sh "Options for Code Generation Conventions" |
| 18031 | .IX Subsection "Options for Code Generation Conventions" |
| 18032 | These machine-independent options control the interface conventions |
| 18033 | used in code generation. |
| 18034 | .PP |
| 18035 | Most of them have both positive and negative forms; the negative form |
| 18036 | of \fB\-ffoo\fR would be \fB\-fno\-foo\fR. In the table below, only |
| 18037 | one of the forms is listed\-\-\-the one that is not the default. You |
| 18038 | can figure out the other form by either removing \fBno\-\fR or adding |
| 18039 | it. |
| 18040 | .IP "\fB\-fbounds\-check\fR" 4 |
| 18041 | .IX Item "-fbounds-check" |
| 18042 | For front ends that support it, generate additional code to check that |
| 18043 | indices used to access arrays are within the declared range. This is |
| 18044 | currently only supported by the Java and Fortran front ends, where |
| 18045 | this option defaults to true and false respectively. |
| 18046 | .IP "\fB\-ftrapv\fR" 4 |
| 18047 | .IX Item "-ftrapv" |
| 18048 | This option generates traps for signed overflow on addition, subtraction, |
| 18049 | multiplication operations. |
| 18050 | .IP "\fB\-fwrapv\fR" 4 |
| 18051 | .IX Item "-fwrapv" |
| 18052 | This option instructs the compiler to assume that signed arithmetic |
| 18053 | overflow of addition, subtraction and multiplication wraps around |
| 18054 | using twos-complement representation. This flag enables some optimizations |
| 18055 | and disables others. This option is enabled by default for the Java |
| 18056 | front end, as required by the Java language specification. |
| 18057 | .IP "\fB\-fexceptions\fR" 4 |
| 18058 | .IX Item "-fexceptions" |
| 18059 | Enable exception handling. Generates extra code needed to propagate |
| 18060 | exceptions. For some targets, this implies \s-1GCC\s0 will generate frame |
| 18061 | unwind information for all functions, which can produce significant data |
| 18062 | size overhead, although it does not affect execution. If you do not |
| 18063 | specify this option, \s-1GCC\s0 will enable it by default for languages like |
| 18064 | \&\*(C+ that normally require exception handling, and disable it for |
| 18065 | languages like C that do not normally require it. However, you may need |
| 18066 | to enable this option when compiling C code that needs to interoperate |
| 18067 | properly with exception handlers written in \*(C+. You may also wish to |
| 18068 | disable this option if you are compiling older \*(C+ programs that don't |
| 18069 | use exception handling. |
| 18070 | .IP "\fB\-fnon\-call\-exceptions\fR" 4 |
| 18071 | .IX Item "-fnon-call-exceptions" |
| 18072 | Generate code that allows trapping instructions to throw exceptions. |
| 18073 | Note that this requires platform-specific runtime support that does |
| 18074 | not exist everywhere. Moreover, it only allows \fItrapping\fR |
| 18075 | instructions to throw exceptions, i.e. memory references or floating-point |
| 18076 | instructions. It does not allow exceptions to be thrown from |
| 18077 | arbitrary signal handlers such as \f(CW\*(C`SIGALRM\*(C'\fR. |
| 18078 | .IP "\fB\-funwind\-tables\fR" 4 |
| 18079 | .IX Item "-funwind-tables" |
| 18080 | Similar to \fB\-fexceptions\fR, except that it will just generate any needed |
| 18081 | static data, but will not affect the generated code in any other way. |
| 18082 | You will normally not enable this option; instead, a language processor |
| 18083 | that needs this handling would enable it on your behalf. |
| 18084 | .IP "\fB\-fasynchronous\-unwind\-tables\fR" 4 |
| 18085 | .IX Item "-fasynchronous-unwind-tables" |
| 18086 | Generate unwind table in dwarf2 format, if supported by target machine. The |
| 18087 | table is exact at each instruction boundary, so it can be used for stack |
| 18088 | unwinding from asynchronous events (such as debugger or garbage collector). |
| 18089 | .IP "\fB\-fpcc\-struct\-return\fR" 4 |
| 18090 | .IX Item "-fpcc-struct-return" |
| 18091 | Return \*(L"short\*(R" \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in memory like |
| 18092 | longer ones, rather than in registers. This convention is less |
| 18093 | efficient, but it has the advantage of allowing intercallability between |
| 18094 | GCC-compiled files and files compiled with other compilers, particularly |
| 18095 | the Portable C Compiler (pcc). |
| 18096 | .Sp |
| 18097 | The precise convention for returning structures in memory depends |
| 18098 | on the target configuration macros. |
| 18099 | .Sp |
| 18100 | Short structures and unions are those whose size and alignment match |
| 18101 | that of some integer type. |
| 18102 | .Sp |
| 18103 | \&\fBWarning:\fR code compiled with the \fB\-fpcc\-struct\-return\fR |
| 18104 | switch is not binary compatible with code compiled with the |
| 18105 | \&\fB\-freg\-struct\-return\fR switch. |
| 18106 | Use it to conform to a non-default application binary interface. |
| 18107 | .IP "\fB\-freg\-struct\-return\fR" 4 |
| 18108 | .IX Item "-freg-struct-return" |
| 18109 | Return \f(CW\*(C`struct\*(C'\fR and \f(CW\*(C`union\*(C'\fR values in registers when possible. |
| 18110 | This is more efficient for small structures than |
| 18111 | \&\fB\-fpcc\-struct\-return\fR. |
| 18112 | .Sp |
| 18113 | If you specify neither \fB\-fpcc\-struct\-return\fR nor |
| 18114 | \&\fB\-freg\-struct\-return\fR, \s-1GCC\s0 defaults to whichever convention is |
| 18115 | standard for the target. If there is no standard convention, \s-1GCC\s0 |
| 18116 | defaults to \fB\-fpcc\-struct\-return\fR, except on targets where \s-1GCC\s0 is |
| 18117 | the principal compiler. In those cases, we can choose the standard, and |
| 18118 | we chose the more efficient register return alternative. |
| 18119 | .Sp |
| 18120 | \&\fBWarning:\fR code compiled with the \fB\-freg\-struct\-return\fR |
| 18121 | switch is not binary compatible with code compiled with the |
| 18122 | \&\fB\-fpcc\-struct\-return\fR switch. |
| 18123 | Use it to conform to a non-default application binary interface. |
| 18124 | .IP "\fB\-fshort\-enums\fR" 4 |
| 18125 | .IX Item "-fshort-enums" |
| 18126 | Allocate to an \f(CW\*(C`enum\*(C'\fR type only as many bytes as it needs for the |
| 18127 | declared range of possible values. Specifically, the \f(CW\*(C`enum\*(C'\fR type |
| 18128 | will be equivalent to the smallest integer type that has enough room. |
| 18129 | .Sp |
| 18130 | \&\fBWarning:\fR the \fB\-fshort\-enums\fR switch causes \s-1GCC\s0 to generate |
| 18131 | code that is not binary compatible with code generated without that switch. |
| 18132 | Use it to conform to a non-default application binary interface. |
| 18133 | .IP "\fB\-fshort\-double\fR" 4 |
| 18134 | .IX Item "-fshort-double" |
| 18135 | Use the same size for \f(CW\*(C`double\*(C'\fR as for \f(CW\*(C`float\*(C'\fR. |
| 18136 | .Sp |
| 18137 | \&\fBWarning:\fR the \fB\-fshort\-double\fR switch causes \s-1GCC\s0 to generate |
| 18138 | code that is not binary compatible with code generated without that switch. |
| 18139 | Use it to conform to a non-default application binary interface. |
| 18140 | .IP "\fB\-fshort\-wchar\fR" 4 |
| 18141 | .IX Item "-fshort-wchar" |
| 18142 | Override the underlying type for \fBwchar_t\fR to be \fBshort |
| 18143 | unsigned int\fR instead of the default for the target. This option is |
| 18144 | useful for building programs to run under \s-1WINE\s0. |
| 18145 | .Sp |
| 18146 | \&\fBWarning:\fR the \fB\-fshort\-wchar\fR switch causes \s-1GCC\s0 to generate |
| 18147 | code that is not binary compatible with code generated without that switch. |
| 18148 | Use it to conform to a non-default application binary interface. |
| 18149 | .IP "\fB\-fno\-common\fR" 4 |
| 18150 | .IX Item "-fno-common" |
| 18151 | In C code, controls the placement of uninitialized global variables. |
| 18152 | Unix C compilers have traditionally permitted multiple definitions of |
| 18153 | such variables in different compilation units by placing the variables |
| 18154 | in a common block. |
| 18155 | This is the behavior specified by \fB\-fcommon\fR, and is the default |
| 18156 | for \s-1GCC\s0 on most targets. |
| 18157 | On the other hand, this behavior is not required by \s-1ISO\s0 C, and on some |
| 18158 | targets may carry a speed or code size penalty on variable references. |
| 18159 | The \fB\-fno\-common\fR option specifies that the compiler should place |
| 18160 | uninitialized global variables in the data section of the object file, |
| 18161 | rather than generating them as common blocks. |
| 18162 | This has the effect that if the same variable is declared |
| 18163 | (without \f(CW\*(C`extern\*(C'\fR) in two different compilations, |
| 18164 | you will get a multiple-definition error when you link them. |
| 18165 | In this case, you must compile with \fB\-fcommon\fR instead. |
| 18166 | Compiling with \fB\-fno\-common\fR is useful on targets for which |
| 18167 | it provides better performance, or if you wish to verify that the |
| 18168 | program will work on other systems that always treat uninitialized |
| 18169 | variable declarations this way. |
| 18170 | .IP "\fB\-fno\-ident\fR" 4 |
| 18171 | .IX Item "-fno-ident" |
| 18172 | Ignore the \fB#ident\fR directive. |
| 18173 | .IP "\fB\-finhibit\-size\-directive\fR" 4 |
| 18174 | .IX Item "-finhibit-size-directive" |
| 18175 | Don't output a \f(CW\*(C`.size\*(C'\fR assembler directive, or anything else that |
| 18176 | would cause trouble if the function is split in the middle, and the |
| 18177 | two halves are placed at locations far apart in memory. This option is |
| 18178 | used when compiling \fIcrtstuff.c\fR; you should not need to use it |
| 18179 | for anything else. |
| 18180 | .IP "\fB\-fverbose\-asm\fR" 4 |
| 18181 | .IX Item "-fverbose-asm" |
| 18182 | Put extra commentary information in the generated assembly code to |
| 18183 | make it more readable. This option is generally only of use to those |
| 18184 | who actually need to read the generated assembly code (perhaps while |
| 18185 | debugging the compiler itself). |
| 18186 | .Sp |
| 18187 | \&\fB\-fno\-verbose\-asm\fR, the default, causes the |
| 18188 | extra information to be omitted and is useful when comparing two assembler |
| 18189 | files. |
| 18190 | .IP "\fB\-frecord\-gcc\-switches\fR" 4 |
| 18191 | .IX Item "-frecord-gcc-switches" |
| 18192 | This switch causes the command line that was used to invoke the |
| 18193 | compiler to be recorded into the object file that is being created. |
| 18194 | This switch is only implemented on some targets and the exact format |
| 18195 | of the recording is target and binary file format dependent, but it |
| 18196 | usually takes the form of a section containing \s-1ASCII\s0 text. This |
| 18197 | switch is related to the \fB\-fverbose\-asm\fR switch, but that |
| 18198 | switch only records information in the assembler output file as |
| 18199 | comments, so it never reaches the object file. |
| 18200 | See also \fB\-grecord\-gcc\-switches\fR for another |
| 18201 | way of storing compiler options into the object file. |
| 18202 | .IP "\fB\-fpic\fR" 4 |
| 18203 | .IX Item "-fpic" |
| 18204 | Generate position-independent code (\s-1PIC\s0) suitable for use in a shared |
| 18205 | library, if supported for the target machine. Such code accesses all |
| 18206 | constant addresses through a global offset table (\s-1GOT\s0). The dynamic |
| 18207 | loader resolves the \s-1GOT\s0 entries when the program starts (the dynamic |
| 18208 | loader is not part of \s-1GCC\s0; it is part of the operating system). If |
| 18209 | the \s-1GOT\s0 size for the linked executable exceeds a machine-specific |
| 18210 | maximum size, you get an error message from the linker indicating that |
| 18211 | \&\fB\-fpic\fR does not work; in that case, recompile with \fB\-fPIC\fR |
| 18212 | instead. (These maximums are 8k on the \s-1SPARC\s0 and 32k |
| 18213 | on the m68k and \s-1RS/6000\s0. The 386 has no such limit.) |
| 18214 | .Sp |
| 18215 | Position-independent code requires special support, and therefore works |
| 18216 | only on certain machines. For the 386, \s-1GCC\s0 supports \s-1PIC\s0 for System V |
| 18217 | but not for the Sun 386i. Code generated for the \s-1IBM\s0 \s-1RS/6000\s0 is always |
| 18218 | position-independent. |
| 18219 | .Sp |
| 18220 | When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR |
| 18221 | are defined to 1. |
| 18222 | .IP "\fB\-fPIC\fR" 4 |
| 18223 | .IX Item "-fPIC" |
| 18224 | If supported for the target machine, emit position-independent code, |
| 18225 | suitable for dynamic linking and avoiding any limit on the size of the |
| 18226 | global offset table. This option makes a difference on the m68k, |
| 18227 | PowerPC and \s-1SPARC\s0. |
| 18228 | .Sp |
| 18229 | Position-independent code requires special support, and therefore works |
| 18230 | only on certain machines. |
| 18231 | .Sp |
| 18232 | When this flag is set, the macros \f(CW\*(C`_\|_pic_\|_\*(C'\fR and \f(CW\*(C`_\|_PIC_\|_\*(C'\fR |
| 18233 | are defined to 2. |
| 18234 | .IP "\fB\-fpie\fR" 4 |
| 18235 | .IX Item "-fpie" |
| 18236 | .PD 0 |
| 18237 | .IP "\fB\-fPIE\fR" 4 |
| 18238 | .IX Item "-fPIE" |
| 18239 | .PD |
| 18240 | These options are similar to \fB\-fpic\fR and \fB\-fPIC\fR, but |
| 18241 | generated position independent code can be only linked into executables. |
| 18242 | Usually these options are used when \fB\-pie\fR \s-1GCC\s0 option will be |
| 18243 | used during linking. |
| 18244 | .Sp |
| 18245 | \&\fB\-fpie\fR and \fB\-fPIE\fR both define the macros |
| 18246 | \&\f(CW\*(C`_\|_pie_\|_\*(C'\fR and \f(CW\*(C`_\|_PIE_\|_\*(C'\fR. The macros have the value 1 |
| 18247 | for \fB\-fpie\fR and 2 for \fB\-fPIE\fR. |
| 18248 | .IP "\fB\-fno\-jump\-tables\fR" 4 |
| 18249 | .IX Item "-fno-jump-tables" |
| 18250 | Do not use jump tables for switch statements even where it would be |
| 18251 | more efficient than other code generation strategies. This option is |
| 18252 | of use in conjunction with \fB\-fpic\fR or \fB\-fPIC\fR for |
| 18253 | building code that forms part of a dynamic linker and cannot |
| 18254 | reference the address of a jump table. On some targets, jump tables |
| 18255 | do not require a \s-1GOT\s0 and this option is not needed. |
| 18256 | .IP "\fB\-ffixed\-\fR\fIreg\fR" 4 |
| 18257 | .IX Item "-ffixed-reg" |
| 18258 | Treat the register named \fIreg\fR as a fixed register; generated code |
| 18259 | should never refer to it (except perhaps as a stack pointer, frame |
| 18260 | pointer or in some other fixed role). |
| 18261 | .Sp |
| 18262 | \&\fIreg\fR must be the name of a register. The register names accepted |
| 18263 | are machine-specific and are defined in the \f(CW\*(C`REGISTER_NAMES\*(C'\fR |
| 18264 | macro in the machine description macro file. |
| 18265 | .Sp |
| 18266 | This flag does not have a negative form, because it specifies a |
| 18267 | three-way choice. |
| 18268 | .IP "\fB\-fcall\-used\-\fR\fIreg\fR" 4 |
| 18269 | .IX Item "-fcall-used-reg" |
| 18270 | Treat the register named \fIreg\fR as an allocable register that is |
| 18271 | clobbered by function calls. It may be allocated for temporaries or |
| 18272 | variables that do not live across a call. Functions compiled this way |
| 18273 | will not save and restore the register \fIreg\fR. |
| 18274 | .Sp |
| 18275 | It is an error to used this flag with the frame pointer or stack pointer. |
| 18276 | Use of this flag for other registers that have fixed pervasive roles in |
| 18277 | the machine's execution model will produce disastrous results. |
| 18278 | .Sp |
| 18279 | This flag does not have a negative form, because it specifies a |
| 18280 | three-way choice. |
| 18281 | .IP "\fB\-fcall\-saved\-\fR\fIreg\fR" 4 |
| 18282 | .IX Item "-fcall-saved-reg" |
| 18283 | Treat the register named \fIreg\fR as an allocable register saved by |
| 18284 | functions. It may be allocated even for temporaries or variables that |
| 18285 | live across a call. Functions compiled this way will save and restore |
| 18286 | the register \fIreg\fR if they use it. |
| 18287 | .Sp |
| 18288 | It is an error to used this flag with the frame pointer or stack pointer. |
| 18289 | Use of this flag for other registers that have fixed pervasive roles in |
| 18290 | the machine's execution model will produce disastrous results. |
| 18291 | .Sp |
| 18292 | A different sort of disaster will result from the use of this flag for |
| 18293 | a register in which function values may be returned. |
| 18294 | .Sp |
| 18295 | This flag does not have a negative form, because it specifies a |
| 18296 | three-way choice. |
| 18297 | .IP "\fB\-fpack\-struct[=\fR\fIn\fR\fB]\fR" 4 |
| 18298 | .IX Item "-fpack-struct[=n]" |
| 18299 | Without a value specified, pack all structure members together without |
| 18300 | holes. When a value is specified (which must be a small power of two), pack |
| 18301 | structure members according to this value, representing the maximum |
| 18302 | alignment (that is, objects with default alignment requirements larger than |
| 18303 | this will be output potentially unaligned at the next fitting location. |
| 18304 | .Sp |
| 18305 | \&\fBWarning:\fR the \fB\-fpack\-struct\fR switch causes \s-1GCC\s0 to generate |
| 18306 | code that is not binary compatible with code generated without that switch. |
| 18307 | Additionally, it makes the code suboptimal. |
| 18308 | Use it to conform to a non-default application binary interface. |
| 18309 | .IP "\fB\-finstrument\-functions\fR" 4 |
| 18310 | .IX Item "-finstrument-functions" |
| 18311 | Generate instrumentation calls for entry and exit to functions. Just |
| 18312 | after function entry and just before function exit, the following |
| 18313 | profiling functions will be called with the address of the current |
| 18314 | function and its call site. (On some platforms, |
| 18315 | \&\f(CW\*(C`_\|_builtin_return_address\*(C'\fR does not work beyond the current |
| 18316 | function, so the call site information may not be available to the |
| 18317 | profiling functions otherwise.) |
| 18318 | .Sp |
| 18319 | .Vb 4 |
| 18320 | \& void _\|_cyg_profile_func_enter (void *this_fn, |
| 18321 | \& void *call_site); |
| 18322 | \& void _\|_cyg_profile_func_exit (void *this_fn, |
| 18323 | \& void *call_site); |
| 18324 | .Ve |
| 18325 | .Sp |
| 18326 | The first argument is the address of the start of the current function, |
| 18327 | which may be looked up exactly in the symbol table. |
| 18328 | .Sp |
| 18329 | This instrumentation is also done for functions expanded inline in other |
| 18330 | functions. The profiling calls will indicate where, conceptually, the |
| 18331 | inline function is entered and exited. This means that addressable |
| 18332 | versions of such functions must be available. If all your uses of a |
| 18333 | function are expanded inline, this may mean an additional expansion of |
| 18334 | code size. If you use \fBextern inline\fR in your C code, an |
| 18335 | addressable version of such functions must be provided. (This is |
| 18336 | normally the case anyways, but if you get lucky and the optimizer always |
| 18337 | expands the functions inline, you might have gotten away without |
| 18338 | providing static copies.) |
| 18339 | .Sp |
| 18340 | A function may be given the attribute \f(CW\*(C`no_instrument_function\*(C'\fR, in |
| 18341 | which case this instrumentation will not be done. This can be used, for |
| 18342 | example, for the profiling functions listed above, high-priority |
| 18343 | interrupt routines, and any functions from which the profiling functions |
| 18344 | cannot safely be called (perhaps signal handlers, if the profiling |
| 18345 | routines generate output or allocate memory). |
| 18346 | .IP "\fB\-finstrument\-functions\-exclude\-file\-list=\fR\fIfile\fR\fB,\fR\fIfile\fR\fB,...\fR" 4 |
| 18347 | .IX Item "-finstrument-functions-exclude-file-list=file,file,..." |
| 18348 | Set the list of functions that are excluded from instrumentation (see |
| 18349 | the description of \f(CW\*(C`\-finstrument\-functions\*(C'\fR). If the file that |
| 18350 | contains a function definition matches with one of \fIfile\fR, then |
| 18351 | that function is not instrumented. The match is done on substrings: |
| 18352 | if the \fIfile\fR parameter is a substring of the file name, it is |
| 18353 | considered to be a match. |
| 18354 | .Sp |
| 18355 | For example: |
| 18356 | .Sp |
| 18357 | .Vb 1 |
| 18358 | \& \-finstrument\-functions\-exclude\-file\-list=/bits/stl,include/sys |
| 18359 | .Ve |
| 18360 | .Sp |
| 18361 | will exclude any inline function defined in files whose pathnames |
| 18362 | contain \f(CW\*(C`/bits/stl\*(C'\fR or \f(CW\*(C`include/sys\*(C'\fR. |
| 18363 | .Sp |
| 18364 | If, for some reason, you want to include letter \f(CW\*(Aq,\*(Aq\fR in one of |
| 18365 | \&\fIsym\fR, write \f(CW\*(Aq,\*(Aq\fR. For example, |
| 18366 | \&\f(CW\*(C`\-finstrument\-functions\-exclude\-file\-list=\*(Aq,,tmp\*(Aq\*(C'\fR |
| 18367 | (note the single quote surrounding the option). |
| 18368 | .IP "\fB\-finstrument\-functions\-exclude\-function\-list=\fR\fIsym\fR\fB,\fR\fIsym\fR\fB,...\fR" 4 |
| 18369 | .IX Item "-finstrument-functions-exclude-function-list=sym,sym,..." |
| 18370 | This is similar to \f(CW\*(C`\-finstrument\-functions\-exclude\-file\-list\*(C'\fR, |
| 18371 | but this option sets the list of function names to be excluded from |
| 18372 | instrumentation. The function name to be matched is its user-visible |
| 18373 | name, such as \f(CW\*(C`vector<int> blah(const vector<int> &)\*(C'\fR, not the |
| 18374 | internal mangled name (e.g., \f(CW\*(C`_Z4blahRSt6vectorIiSaIiEE\*(C'\fR). The |
| 18375 | match is done on substrings: if the \fIsym\fR parameter is a substring |
| 18376 | of the function name, it is considered to be a match. For C99 and \*(C+ |
| 18377 | extended identifiers, the function name must be given in \s-1UTF\-8\s0, not |
| 18378 | using universal character names. |
| 18379 | .IP "\fB\-fstack\-check\fR" 4 |
| 18380 | .IX Item "-fstack-check" |
| 18381 | Generate code to verify that you do not go beyond the boundary of the |
| 18382 | stack. You should specify this flag if you are running in an |
| 18383 | environment with multiple threads, but only rarely need to specify it in |
| 18384 | a single-threaded environment since stack overflow is automatically |
| 18385 | detected on nearly all systems if there is only one stack. |
| 18386 | .Sp |
| 18387 | Note that this switch does not actually cause checking to be done; the |
| 18388 | operating system or the language runtime must do that. The switch causes |
| 18389 | generation of code to ensure that they see the stack being extended. |
| 18390 | .Sp |
| 18391 | You can additionally specify a string parameter: \f(CW\*(C`no\*(C'\fR means no |
| 18392 | checking, \f(CW\*(C`generic\*(C'\fR means force the use of old-style checking, |
| 18393 | \&\f(CW\*(C`specific\*(C'\fR means use the best checking method and is equivalent |
| 18394 | to bare \fB\-fstack\-check\fR. |
| 18395 | .Sp |
| 18396 | Old-style checking is a generic mechanism that requires no specific |
| 18397 | target support in the compiler but comes with the following drawbacks: |
| 18398 | .RS 4 |
| 18399 | .IP "1." 4 |
| 18400 | Modified allocation strategy for large objects: they will always be |
| 18401 | allocated dynamically if their size exceeds a fixed threshold. |
| 18402 | .IP "2." 4 |
| 18403 | Fixed limit on the size of the static frame of functions: when it is |
| 18404 | topped by a particular function, stack checking is not reliable and |
| 18405 | a warning is issued by the compiler. |
| 18406 | .IP "3." 4 |
| 18407 | Inefficiency: because of both the modified allocation strategy and the |
| 18408 | generic implementation, the performances of the code are hampered. |
| 18409 | .RE |
| 18410 | .RS 4 |
| 18411 | .Sp |
| 18412 | Note that old-style stack checking is also the fallback method for |
| 18413 | \&\f(CW\*(C`specific\*(C'\fR if no target support has been added in the compiler. |
| 18414 | .RE |
| 18415 | .IP "\fB\-fstack\-limit\-register=\fR\fIreg\fR" 4 |
| 18416 | .IX Item "-fstack-limit-register=reg" |
| 18417 | .PD 0 |
| 18418 | .IP "\fB\-fstack\-limit\-symbol=\fR\fIsym\fR" 4 |
| 18419 | .IX Item "-fstack-limit-symbol=sym" |
| 18420 | .IP "\fB\-fno\-stack\-limit\fR" 4 |
| 18421 | .IX Item "-fno-stack-limit" |
| 18422 | .PD |
| 18423 | Generate code to ensure that the stack does not grow beyond a certain value, |
| 18424 | either the value of a register or the address of a symbol. If the stack |
| 18425 | would grow beyond the value, a signal is raised. For most targets, |
| 18426 | the signal is raised before the stack overruns the boundary, so |
| 18427 | it is possible to catch the signal without taking special precautions. |
| 18428 | .Sp |
| 18429 | For instance, if the stack starts at absolute address \fB0x80000000\fR |
| 18430 | and grows downwards, you can use the flags |
| 18431 | \&\fB\-fstack\-limit\-symbol=_\|_stack_limit\fR and |
| 18432 | \&\fB\-Wl,\-\-defsym,_\|_stack_limit=0x7ffe0000\fR to enforce a stack limit |
| 18433 | of 128KB. Note that this may only work with the \s-1GNU\s0 linker. |
| 18434 | .IP "\fB\-fsplit\-stack\fR" 4 |
| 18435 | .IX Item "-fsplit-stack" |
| 18436 | Generate code to automatically split the stack before it overflows. |
| 18437 | The resulting program has a discontiguous stack which can only |
| 18438 | overflow if the program is unable to allocate any more memory. This |
| 18439 | is most useful when running threaded programs, as it is no longer |
| 18440 | necessary to calculate a good stack size to use for each thread. This |
| 18441 | is currently only implemented for the i386 and x86_64 back ends running |
| 18442 | GNU/Linux. |
| 18443 | .Sp |
| 18444 | When code compiled with \fB\-fsplit\-stack\fR calls code compiled |
| 18445 | without \fB\-fsplit\-stack\fR, there may not be much stack space |
| 18446 | available for the latter code to run. If compiling all code, |
| 18447 | including library code, with \fB\-fsplit\-stack\fR is not an option, |
| 18448 | then the linker can fix up these calls so that the code compiled |
| 18449 | without \fB\-fsplit\-stack\fR always has a large stack. Support for |
| 18450 | this is implemented in the gold linker in \s-1GNU\s0 binutils release 2.21 |
| 18451 | and later. |
| 18452 | .IP "\fB\-fleading\-underscore\fR" 4 |
| 18453 | .IX Item "-fleading-underscore" |
| 18454 | This option and its counterpart, \fB\-fno\-leading\-underscore\fR, forcibly |
| 18455 | change the way C symbols are represented in the object file. One use |
| 18456 | is to help link with legacy assembly code. |
| 18457 | .Sp |
| 18458 | \&\fBWarning:\fR the \fB\-fleading\-underscore\fR switch causes \s-1GCC\s0 to |
| 18459 | generate code that is not binary compatible with code generated without that |
| 18460 | switch. Use it to conform to a non-default application binary interface. |
| 18461 | Not all targets provide complete support for this switch. |
| 18462 | .IP "\fB\-ftls\-model=\fR\fImodel\fR" 4 |
| 18463 | .IX Item "-ftls-model=model" |
| 18464 | Alter the thread-local storage model to be used. |
| 18465 | The \fImodel\fR argument should be one of \f(CW\*(C`global\-dynamic\*(C'\fR, |
| 18466 | \&\f(CW\*(C`local\-dynamic\*(C'\fR, \f(CW\*(C`initial\-exec\*(C'\fR or \f(CW\*(C`local\-exec\*(C'\fR. |
| 18467 | .Sp |
| 18468 | The default without \fB\-fpic\fR is \f(CW\*(C`initial\-exec\*(C'\fR; with |
| 18469 | \&\fB\-fpic\fR the default is \f(CW\*(C`global\-dynamic\*(C'\fR. |
| 18470 | .IP "\fB\-fvisibility=\fR\fIdefault|internal|hidden|protected\fR" 4 |
| 18471 | .IX Item "-fvisibility=default|internal|hidden|protected" |
| 18472 | Set the default \s-1ELF\s0 image symbol visibility to the specified option\-\-\-all |
| 18473 | symbols will be marked with this unless overridden within the code. |
| 18474 | Using this feature can very substantially improve linking and |
| 18475 | load times of shared object libraries, produce more optimized |
| 18476 | code, provide near-perfect \s-1API\s0 export and prevent symbol clashes. |
| 18477 | It is \fBstrongly\fR recommended that you use this in any shared objects |
| 18478 | you distribute. |
| 18479 | .Sp |
| 18480 | Despite the nomenclature, \f(CW\*(C`default\*(C'\fR always means public; i.e., |
| 18481 | available to be linked against from outside the shared object. |
| 18482 | \&\f(CW\*(C`protected\*(C'\fR and \f(CW\*(C`internal\*(C'\fR are pretty useless in real-world |
| 18483 | usage so the only other commonly used option will be \f(CW\*(C`hidden\*(C'\fR. |
| 18484 | The default if \fB\-fvisibility\fR isn't specified is |
| 18485 | \&\f(CW\*(C`default\*(C'\fR, i.e., make every |
| 18486 | symbol public\-\-\-this causes the same behavior as previous versions of |
| 18487 | \&\s-1GCC\s0. |
| 18488 | .Sp |
| 18489 | A good explanation of the benefits offered by ensuring \s-1ELF\s0 |
| 18490 | symbols have the correct visibility is given by \*(L"How To Write |
| 18491 | Shared Libraries\*(R" by Ulrich Drepper (which can be found at |
| 18492 | <\fBhttp://people.redhat.com/~drepper/\fR>)\-\-\-however a superior |
| 18493 | solution made possible by this option to marking things hidden when |
| 18494 | the default is public is to make the default hidden and mark things |
| 18495 | public. This is the norm with \s-1DLL\s0's on Windows and with \fB\-fvisibility=hidden\fR |
| 18496 | and \f(CW\*(C`_\|_attribute_\|_ ((visibility("default")))\*(C'\fR instead of |
| 18497 | \&\f(CW\*(C`_\|_declspec(dllexport)\*(C'\fR you get almost identical semantics with |
| 18498 | identical syntax. This is a great boon to those working with |
| 18499 | cross-platform projects. |
| 18500 | .Sp |
| 18501 | For those adding visibility support to existing code, you may find |
| 18502 | \&\fB#pragma \s-1GCC\s0 visibility\fR of use. This works by you enclosing |
| 18503 | the declarations you wish to set visibility for with (for example) |
| 18504 | \&\fB#pragma \s-1GCC\s0 visibility push(hidden)\fR and |
| 18505 | \&\fB#pragma \s-1GCC\s0 visibility pop\fR. |
| 18506 | Bear in mind that symbol visibility should be viewed \fBas |
| 18507 | part of the \s-1API\s0 interface contract\fR and thus all new code should |
| 18508 | always specify visibility when it is not the default; i.e., declarations |
| 18509 | only for use within the local \s-1DSO\s0 should \fBalways\fR be marked explicitly |
| 18510 | as hidden as so to avoid \s-1PLT\s0 indirection overheads\-\-\-making this |
| 18511 | abundantly clear also aids readability and self-documentation of the code. |
| 18512 | Note that due to \s-1ISO\s0 \*(C+ specification requirements, operator new and |
| 18513 | operator delete must always be of default visibility. |
| 18514 | .Sp |
| 18515 | Be aware that headers from outside your project, in particular system |
| 18516 | headers and headers from any other library you use, may not be |
| 18517 | expecting to be compiled with visibility other than the default. You |
| 18518 | may need to explicitly say \fB#pragma \s-1GCC\s0 visibility push(default)\fR |
| 18519 | before including any such headers. |
| 18520 | .Sp |
| 18521 | \&\fBextern\fR declarations are not affected by \fB\-fvisibility\fR, so |
| 18522 | a lot of code can be recompiled with \fB\-fvisibility=hidden\fR with |
| 18523 | no modifications. However, this means that calls to \fBextern\fR |
| 18524 | functions with no explicit visibility will use the \s-1PLT\s0, so it is more |
| 18525 | effective to use \fB_\|_attribute ((visibility))\fR and/or |
| 18526 | \&\fB#pragma \s-1GCC\s0 visibility\fR to tell the compiler which \fBextern\fR |
| 18527 | declarations should be treated as hidden. |
| 18528 | .Sp |
| 18529 | Note that \fB\-fvisibility\fR does affect \*(C+ vague linkage |
| 18530 | entities. This means that, for instance, an exception class that will |
| 18531 | be thrown between DSOs must be explicitly marked with default |
| 18532 | visibility so that the \fBtype_info\fR nodes will be unified between |
| 18533 | the DSOs. |
| 18534 | .Sp |
| 18535 | An overview of these techniques, their benefits and how to use them |
| 18536 | is at <\fBhttp://gcc.gnu.org/wiki/Visibility\fR>. |
| 18537 | .IP "\fB\-fstrict\-volatile\-bitfields\fR" 4 |
| 18538 | .IX Item "-fstrict-volatile-bitfields" |
| 18539 | This option should be used if accesses to volatile bit-fields (or other |
| 18540 | structure fields, although the compiler usually honors those types |
| 18541 | anyway) should use a single access of the width of the |
| 18542 | field's type, aligned to a natural alignment if possible. For |
| 18543 | example, targets with memory-mapped peripheral registers might require |
| 18544 | all such accesses to be 16 bits wide; with this flag the user could |
| 18545 | declare all peripheral bit-fields as \*(L"unsigned short\*(R" (assuming short |
| 18546 | is 16 bits on these targets) to force \s-1GCC\s0 to use 16\-bit accesses |
| 18547 | instead of, perhaps, a more efficient 32\-bit access. |
| 18548 | .Sp |
| 18549 | If this option is disabled, the compiler will use the most efficient |
| 18550 | instruction. In the previous example, that might be a 32\-bit load |
| 18551 | instruction, even though that will access bytes that do not contain |
| 18552 | any portion of the bit-field, or memory-mapped registers unrelated to |
| 18553 | the one being updated. |
| 18554 | .Sp |
| 18555 | If the target requires strict alignment, and honoring the field |
| 18556 | type would require violating this alignment, a warning is issued. |
| 18557 | If the field has \f(CW\*(C`packed\*(C'\fR attribute, the access is done without |
| 18558 | honoring the field type. If the field doesn't have \f(CW\*(C`packed\*(C'\fR |
| 18559 | attribute, the access is done honoring the field type. In both cases, |
| 18560 | \&\s-1GCC\s0 assumes that the user knows something about the target hardware |
| 18561 | that it is unaware of. |
| 18562 | .Sp |
| 18563 | The default value of this option is determined by the application binary |
| 18564 | interface for the target processor. |
| 18565 | .SH "ENVIRONMENT" |
| 18566 | .IX Header "ENVIRONMENT" |
| 18567 | This section describes several environment variables that affect how \s-1GCC\s0 |
| 18568 | operates. Some of them work by specifying directories or prefixes to use |
| 18569 | when searching for various kinds of files. Some are used to specify other |
| 18570 | aspects of the compilation environment. |
| 18571 | .PP |
| 18572 | Note that you can also specify places to search using options such as |
| 18573 | \&\fB\-B\fR, \fB\-I\fR and \fB\-L\fR. These |
| 18574 | take precedence over places specified using environment variables, which |
| 18575 | in turn take precedence over those specified by the configuration of \s-1GCC\s0. |
| 18576 | .IP "\fB\s-1LANG\s0\fR" 4 |
| 18577 | .IX Item "LANG" |
| 18578 | .PD 0 |
| 18579 | .IP "\fB\s-1LC_CTYPE\s0\fR" 4 |
| 18580 | .IX Item "LC_CTYPE" |
| 18581 | .IP "\fB\s-1LC_MESSAGES\s0\fR" 4 |
| 18582 | .IX Item "LC_MESSAGES" |
| 18583 | .IP "\fB\s-1LC_ALL\s0\fR" 4 |
| 18584 | .IX Item "LC_ALL" |
| 18585 | .PD |
| 18586 | These environment variables control the way that \s-1GCC\s0 uses |
| 18587 | localization information which allows \s-1GCC\s0 to work with different |
| 18588 | national conventions. \s-1GCC\s0 inspects the locale categories |
| 18589 | \&\fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR if it has been configured to do |
| 18590 | so. These locale categories can be set to any value supported by your |
| 18591 | installation. A typical value is \fBen_GB.UTF\-8\fR for English in the United |
| 18592 | Kingdom encoded in \s-1UTF\-8\s0. |
| 18593 | .Sp |
| 18594 | The \fB\s-1LC_CTYPE\s0\fR environment variable specifies character |
| 18595 | classification. \s-1GCC\s0 uses it to determine the character boundaries in |
| 18596 | a string; this is needed for some multibyte encodings that contain quote |
| 18597 | and escape characters that would otherwise be interpreted as a string |
| 18598 | end or escape. |
| 18599 | .Sp |
| 18600 | The \fB\s-1LC_MESSAGES\s0\fR environment variable specifies the language to |
| 18601 | use in diagnostic messages. |
| 18602 | .Sp |
| 18603 | If the \fB\s-1LC_ALL\s0\fR environment variable is set, it overrides the value |
| 18604 | of \fB\s-1LC_CTYPE\s0\fR and \fB\s-1LC_MESSAGES\s0\fR; otherwise, \fB\s-1LC_CTYPE\s0\fR |
| 18605 | and \fB\s-1LC_MESSAGES\s0\fR default to the value of the \fB\s-1LANG\s0\fR |
| 18606 | environment variable. If none of these variables are set, \s-1GCC\s0 |
| 18607 | defaults to traditional C English behavior. |
| 18608 | .IP "\fB\s-1TMPDIR\s0\fR" 4 |
| 18609 | .IX Item "TMPDIR" |
| 18610 | If \fB\s-1TMPDIR\s0\fR is set, it specifies the directory to use for temporary |
| 18611 | files. \s-1GCC\s0 uses temporary files to hold the output of one stage of |
| 18612 | compilation which is to be used as input to the next stage: for example, |
| 18613 | the output of the preprocessor, which is the input to the compiler |
| 18614 | proper. |
| 18615 | .IP "\fB\s-1GCC_COMPARE_DEBUG\s0\fR" 4 |
| 18616 | .IX Item "GCC_COMPARE_DEBUG" |
| 18617 | Setting \fB\s-1GCC_COMPARE_DEBUG\s0\fR is nearly equivalent to passing |
| 18618 | \&\fB\-fcompare\-debug\fR to the compiler driver. See the documentation |
| 18619 | of this option for more details. |
| 18620 | .IP "\fB\s-1GCC_EXEC_PREFIX\s0\fR" 4 |
| 18621 | .IX Item "GCC_EXEC_PREFIX" |
| 18622 | If \fB\s-1GCC_EXEC_PREFIX\s0\fR is set, it specifies a prefix to use in the |
| 18623 | names of the subprograms executed by the compiler. No slash is added |
| 18624 | when this prefix is combined with the name of a subprogram, but you can |
| 18625 | specify a prefix that ends with a slash if you wish. |
| 18626 | .Sp |
| 18627 | If \fB\s-1GCC_EXEC_PREFIX\s0\fR is not set, \s-1GCC\s0 will attempt to figure out |
| 18628 | an appropriate prefix to use based on the pathname it was invoked with. |
| 18629 | .Sp |
| 18630 | If \s-1GCC\s0 cannot find the subprogram using the specified prefix, it |
| 18631 | tries looking in the usual places for the subprogram. |
| 18632 | .Sp |
| 18633 | The default value of \fB\s-1GCC_EXEC_PREFIX\s0\fR is |
| 18634 | \&\fI\fIprefix\fI/lib/gcc/\fR where \fIprefix\fR is the prefix to |
| 18635 | the installed compiler. In many cases \fIprefix\fR is the value |
| 18636 | of \f(CW\*(C`prefix\*(C'\fR when you ran the \fIconfigure\fR script. |
| 18637 | .Sp |
| 18638 | Other prefixes specified with \fB\-B\fR take precedence over this prefix. |
| 18639 | .Sp |
| 18640 | This prefix is also used for finding files such as \fIcrt0.o\fR that are |
| 18641 | used for linking. |
| 18642 | .Sp |
| 18643 | In addition, the prefix is used in an unusual way in finding the |
| 18644 | directories to search for header files. For each of the standard |
| 18645 | directories whose name normally begins with \fB/usr/local/lib/gcc\fR |
| 18646 | (more precisely, with the value of \fB\s-1GCC_INCLUDE_DIR\s0\fR), \s-1GCC\s0 tries |
| 18647 | replacing that beginning with the specified prefix to produce an |
| 18648 | alternate directory name. Thus, with \fB\-Bfoo/\fR, \s-1GCC\s0 will search |
| 18649 | \&\fIfoo/bar\fR where it would normally search \fI/usr/local/lib/bar\fR. |
| 18650 | These alternate directories are searched first; the standard directories |
| 18651 | come next. If a standard directory begins with the configured |
| 18652 | \&\fIprefix\fR then the value of \fIprefix\fR is replaced by |
| 18653 | \&\fB\s-1GCC_EXEC_PREFIX\s0\fR when looking for header files. |
| 18654 | .IP "\fB\s-1COMPILER_PATH\s0\fR" 4 |
| 18655 | .IX Item "COMPILER_PATH" |
| 18656 | The value of \fB\s-1COMPILER_PATH\s0\fR is a colon-separated list of |
| 18657 | directories, much like \fB\s-1PATH\s0\fR. \s-1GCC\s0 tries the directories thus |
| 18658 | specified when searching for subprograms, if it can't find the |
| 18659 | subprograms using \fB\s-1GCC_EXEC_PREFIX\s0\fR. |
| 18660 | .IP "\fB\s-1LIBRARY_PATH\s0\fR" 4 |
| 18661 | .IX Item "LIBRARY_PATH" |
| 18662 | The value of \fB\s-1LIBRARY_PATH\s0\fR is a colon-separated list of |
| 18663 | directories, much like \fB\s-1PATH\s0\fR. When configured as a native compiler, |
| 18664 | \&\s-1GCC\s0 tries the directories thus specified when searching for special |
| 18665 | linker files, if it can't find them using \fB\s-1GCC_EXEC_PREFIX\s0\fR. Linking |
| 18666 | using \s-1GCC\s0 also uses these directories when searching for ordinary |
| 18667 | libraries for the \fB\-l\fR option (but directories specified with |
| 18668 | \&\fB\-L\fR come first). |
| 18669 | .IP "\fB\s-1LANG\s0\fR" 4 |
| 18670 | .IX Item "LANG" |
| 18671 | This variable is used to pass locale information to the compiler. One way in |
| 18672 | which this information is used is to determine the character set to be used |
| 18673 | when character literals, string literals and comments are parsed in C and \*(C+. |
| 18674 | When the compiler is configured to allow multibyte characters, |
| 18675 | the following values for \fB\s-1LANG\s0\fR are recognized: |
| 18676 | .RS 4 |
| 18677 | .IP "\fBC\-JIS\fR" 4 |
| 18678 | .IX Item "C-JIS" |
| 18679 | Recognize \s-1JIS\s0 characters. |
| 18680 | .IP "\fBC\-SJIS\fR" 4 |
| 18681 | .IX Item "C-SJIS" |
| 18682 | Recognize \s-1SJIS\s0 characters. |
| 18683 | .IP "\fBC\-EUCJP\fR" 4 |
| 18684 | .IX Item "C-EUCJP" |
| 18685 | Recognize \s-1EUCJP\s0 characters. |
| 18686 | .RE |
| 18687 | .RS 4 |
| 18688 | .Sp |
| 18689 | If \fB\s-1LANG\s0\fR is not defined, or if it has some other value, then the |
| 18690 | compiler will use mblen and mbtowc as defined by the default locale to |
| 18691 | recognize and translate multibyte characters. |
| 18692 | .RE |
| 18693 | .PP |
| 18694 | Some additional environments variables affect the behavior of the |
| 18695 | preprocessor. |
| 18696 | .IP "\fB\s-1CPATH\s0\fR" 4 |
| 18697 | .IX Item "CPATH" |
| 18698 | .PD 0 |
| 18699 | .IP "\fBC_INCLUDE_PATH\fR" 4 |
| 18700 | .IX Item "C_INCLUDE_PATH" |
| 18701 | .IP "\fB\s-1CPLUS_INCLUDE_PATH\s0\fR" 4 |
| 18702 | .IX Item "CPLUS_INCLUDE_PATH" |
| 18703 | .IP "\fB\s-1OBJC_INCLUDE_PATH\s0\fR" 4 |
| 18704 | .IX Item "OBJC_INCLUDE_PATH" |
| 18705 | .PD |
| 18706 | Each variable's value is a list of directories separated by a special |
| 18707 | character, much like \fB\s-1PATH\s0\fR, in which to look for header files. |
| 18708 | The special character, \f(CW\*(C`PATH_SEPARATOR\*(C'\fR, is target-dependent and |
| 18709 | determined at \s-1GCC\s0 build time. For Microsoft Windows-based targets it is a |
| 18710 | semicolon, and for almost all other targets it is a colon. |
| 18711 | .Sp |
| 18712 | \&\fB\s-1CPATH\s0\fR specifies a list of directories to be searched as if |
| 18713 | specified with \fB\-I\fR, but after any paths given with \fB\-I\fR |
| 18714 | options on the command line. This environment variable is used |
| 18715 | regardless of which language is being preprocessed. |
| 18716 | .Sp |
| 18717 | The remaining environment variables apply only when preprocessing the |
| 18718 | particular language indicated. Each specifies a list of directories |
| 18719 | to be searched as if specified with \fB\-isystem\fR, but after any |
| 18720 | paths given with \fB\-isystem\fR options on the command line. |
| 18721 | .Sp |
| 18722 | In all these variables, an empty element instructs the compiler to |
| 18723 | search its current working directory. Empty elements can appear at the |
| 18724 | beginning or end of a path. For instance, if the value of |
| 18725 | \&\fB\s-1CPATH\s0\fR is \f(CW\*(C`:/special/include\*(C'\fR, that has the same |
| 18726 | effect as \fB\-I.\ \-I/special/include\fR. |
| 18727 | .IP "\fB\s-1DEPENDENCIES_OUTPUT\s0\fR" 4 |
| 18728 | .IX Item "DEPENDENCIES_OUTPUT" |
| 18729 | If this variable is set, its value specifies how to output |
| 18730 | dependencies for Make based on the non-system header files processed |
| 18731 | by the compiler. System header files are ignored in the dependency |
| 18732 | output. |
| 18733 | .Sp |
| 18734 | The value of \fB\s-1DEPENDENCIES_OUTPUT\s0\fR can be just a file name, in |
| 18735 | which case the Make rules are written to that file, guessing the target |
| 18736 | name from the source file name. Or the value can have the form |
| 18737 | \&\fIfile\fR\fB \fR\fItarget\fR, in which case the rules are written to |
| 18738 | file \fIfile\fR using \fItarget\fR as the target name. |
| 18739 | .Sp |
| 18740 | In other words, this environment variable is equivalent to combining |
| 18741 | the options \fB\-MM\fR and \fB\-MF\fR, |
| 18742 | with an optional \fB\-MT\fR switch too. |
| 18743 | .IP "\fB\s-1SUNPRO_DEPENDENCIES\s0\fR" 4 |
| 18744 | .IX Item "SUNPRO_DEPENDENCIES" |
| 18745 | This variable is the same as \fB\s-1DEPENDENCIES_OUTPUT\s0\fR (see above), |
| 18746 | except that system header files are not ignored, so it implies |
| 18747 | \&\fB\-M\fR rather than \fB\-MM\fR. However, the dependence on the |
| 18748 | main input file is omitted. |
| 18749 | .SH "BUGS" |
| 18750 | .IX Header "BUGS" |
| 18751 | For instructions on reporting bugs, see |
| 18752 | <\fBhttp://gcc.gnu.org/bugs.html\fR>. |
| 18753 | .SH "FOOTNOTES" |
| 18754 | .IX Header "FOOTNOTES" |
| 18755 | .IP "1." 4 |
| 18756 | On some systems, \fBgcc \-shared\fR |
| 18757 | needs to build supplementary stub code for constructors to work. On |
| 18758 | multi-libbed systems, \fBgcc \-shared\fR must select the correct support |
| 18759 | libraries to link against. Failing to supply the correct flags may lead |
| 18760 | to subtle defects. Supplying them in cases where they are not necessary |
| 18761 | is innocuous. |
| 18762 | .SH "SEE ALSO" |
| 18763 | .IX Header "SEE ALSO" |
| 18764 | \&\fIgpl\fR\|(7), \fIgfdl\fR\|(7), \fIfsf\-funding\fR\|(7), |
| 18765 | \&\fIcpp\fR\|(1), \fIgcov\fR\|(1), \fIas\fR\|(1), \fIld\fR\|(1), \fIgdb\fR\|(1), \fIadb\fR\|(1), \fIdbx\fR\|(1), \fIsdb\fR\|(1) |
| 18766 | and the Info entries for \fIgcc\fR, \fIcpp\fR, \fIas\fR, |
| 18767 | \&\fIld\fR, \fIbinutils\fR and \fIgdb\fR. |
| 18768 | .SH "AUTHOR" |
| 18769 | .IX Header "AUTHOR" |
| 18770 | See the Info entry for \fBgcc\fR, or |
| 18771 | <\fBhttp://gcc.gnu.org/onlinedocs/gcc/Contributors.html\fR>, |
| 18772 | for contributors to \s-1GCC\s0. |
| 18773 | .SH "COPYRIGHT" |
| 18774 | .IX Header "COPYRIGHT" |
| 18775 | Copyright (c) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
| 18776 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, |
| 18777 | 2012 |
| 18778 | Free Software Foundation, Inc. |
| 18779 | .PP |
| 18780 | Permission is granted to copy, distribute and/or modify this document |
| 18781 | under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3 or |
| 18782 | any later version published by the Free Software Foundation; with the |
| 18783 | Invariant Sections being \*(L"\s-1GNU\s0 General Public License\*(R" and \*(L"Funding |
| 18784 | Free Software\*(R", the Front-Cover texts being (a) (see below), and with |
| 18785 | the Back-Cover Texts being (b) (see below). A copy of the license is |
| 18786 | included in the \fIgfdl\fR\|(7) man page. |
| 18787 | .PP |
| 18788 | (a) The \s-1FSF\s0's Front-Cover Text is: |
| 18789 | .PP |
| 18790 | .Vb 1 |
| 18791 | \& A GNU Manual |
| 18792 | .Ve |
| 18793 | .PP |
| 18794 | (b) The \s-1FSF\s0's Back-Cover Text is: |
| 18795 | .PP |
| 18796 | .Vb 3 |
| 18797 | \& You have freedom to copy and modify this GNU Manual, like GNU |
| 18798 | \& software. Copies published by the Free Software Foundation raise |
| 18799 | \& funds for GNU development. |
| 18800 | .Ve |