2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.16 2005/02/20 03:55:14 joerg Exp $
35 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
39 * Winbond fast ethernet PCI NIC driver
41 * Supports various cheap network adapters based on the Winbond W89C840F
42 * fast ethernet controller chip. This includes adapters manufactured by
43 * Winbond itself and some made by Linksys.
45 * Written by Bill Paul <wpaul@ctr.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The Winbond W89C840F chip is a bus master; in some ways it resembles
52 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
53 * one major difference which is that while the registers do many of
54 * the same things as a tulip adapter, the offsets are different: where
55 * tulip registers are typically spaced 8 bytes apart, the Winbond
56 * registers are spaced 4 bytes apart. The receiver filter is also
57 * programmed differently.
59 * Like the tulip, the Winbond chip uses small descriptors containing
60 * a status word, a control word and 32-bit areas that can either be used
61 * to point to two external data blocks, or to point to a single block
62 * and another descriptor in a linked list. Descriptors can be grouped
63 * together in blocks to form fixed length rings or can be chained
64 * together in linked lists. A single packet may be spread out over
65 * several descriptors if necessary.
67 * For the receive ring, this driver uses a linked list of descriptors,
68 * each pointing to a single mbuf cluster buffer, which us large enough
69 * to hold an entire packet. The link list is looped back to created a
72 * For transmission, the driver creates a linked list of 'super descriptors'
73 * which each contain several individual descriptors linked toghether.
74 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
75 * abuse as fragment pointers. This allows us to use a buffer managment
76 * scheme very similar to that used in the ThunderLAN and Etherlink XL
79 * Autonegotiation is performed using the external PHY via the MII bus.
80 * The sample boards I have all use a Davicom PHY.
82 * Note: the author of the Linux driver for the Winbond chip alludes
83 * to some sort of flaw in the chip's design that seems to mandate some
84 * drastic workaround which signigicantly impairs transmit performance.
85 * I have no idea what he's on about: transmit performance with all
86 * three of my test boards seems fine.
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
98 #include <sys/queue.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
109 #include <vm/vm.h> /* for vtophys */
110 #include <vm/pmap.h> /* for vtophys */
111 #include <machine/clock.h> /* for DELAY */
112 #include <machine/bus_memio.h>
113 #include <machine/bus_pio.h>
114 #include <machine/bus.h>
115 #include <machine/resource.h>
117 #include <sys/rman.h>
119 #include <bus/pci/pcireg.h>
120 #include <bus/pci/pcivar.h>
122 #include "../mii_layer/mii.h"
123 #include "../mii_layer/miivar.h"
125 /* "controller miibus0" required. See GENERIC if you get errors here. */
126 #include "miibus_if.h"
128 #define WB_USEIOSPACE
130 #include "if_wbreg.h"
133 * Various supported device vendors/types and their names.
135 static struct wb_type wb_devs[] = {
136 { WB_VENDORID, WB_DEVICEID_840F,
137 "Winbond W89C840F 10/100BaseTX" },
138 { CP_VENDORID, CP_DEVICEID_RL100,
139 "Compex RL100-ATX 10/100baseTX" },
143 static int wb_probe (device_t);
144 static int wb_attach (device_t);
145 static int wb_detach (device_t);
147 static void wb_bfree (caddr_t, u_int);
148 static int wb_newbuf (struct wb_softc *,
149 struct wb_chain_onefrag *,
151 static int wb_encap (struct wb_softc *, struct wb_chain *,
154 static void wb_rxeof (struct wb_softc *);
155 static void wb_rxeoc (struct wb_softc *);
156 static void wb_txeof (struct wb_softc *);
157 static void wb_txeoc (struct wb_softc *);
158 static void wb_intr (void *);
159 static void wb_tick (void *);
160 static void wb_start (struct ifnet *);
161 static int wb_ioctl (struct ifnet *, u_long, caddr_t,
163 static void wb_init (void *);
164 static void wb_stop (struct wb_softc *);
165 static void wb_watchdog (struct ifnet *);
166 static void wb_shutdown (device_t);
167 static int wb_ifmedia_upd (struct ifnet *);
168 static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *);
170 static void wb_eeprom_putbyte (struct wb_softc *, int);
171 static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *);
172 static void wb_read_eeprom (struct wb_softc *, caddr_t, int,
174 static void wb_mii_sync (struct wb_softc *);
175 static void wb_mii_send (struct wb_softc *, u_int32_t, int);
176 static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *);
177 static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *);
179 static void wb_setcfg (struct wb_softc *, u_int32_t);
180 static u_int8_t wb_calchash (caddr_t);
181 static void wb_setmulti (struct wb_softc *);
182 static void wb_reset (struct wb_softc *);
183 static void wb_fixmedia (struct wb_softc *);
184 static int wb_list_rx_init (struct wb_softc *);
185 static int wb_list_tx_init (struct wb_softc *);
187 static int wb_miibus_readreg (device_t, int, int);
188 static int wb_miibus_writereg (device_t, int, int, int);
189 static void wb_miibus_statchg (device_t);
192 #define WB_RES SYS_RES_IOPORT
193 #define WB_RID WB_PCI_LOIO
195 #define WB_RES SYS_RES_MEMORY
196 #define WB_RID WB_PCI_LOMEM
199 static device_method_t wb_methods[] = {
200 /* Device interface */
201 DEVMETHOD(device_probe, wb_probe),
202 DEVMETHOD(device_attach, wb_attach),
203 DEVMETHOD(device_detach, wb_detach),
204 DEVMETHOD(device_shutdown, wb_shutdown),
206 /* bus interface, for miibus */
207 DEVMETHOD(bus_print_child, bus_generic_print_child),
208 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
211 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
212 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
213 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
217 static driver_t wb_driver = {
220 sizeof(struct wb_softc)
223 static devclass_t wb_devclass;
225 DECLARE_DUMMY_MODULE(if_wb);
226 DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
227 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
229 #define WB_SETBIT(sc, reg, x) \
230 CSR_WRITE_4(sc, reg, \
231 CSR_READ_4(sc, reg) | x)
233 #define WB_CLRBIT(sc, reg, x) \
234 CSR_WRITE_4(sc, reg, \
235 CSR_READ_4(sc, reg) & ~x)
238 CSR_WRITE_4(sc, WB_SIO, \
239 CSR_READ_4(sc, WB_SIO) | x)
242 CSR_WRITE_4(sc, WB_SIO, \
243 CSR_READ_4(sc, WB_SIO) & ~x)
246 * Send a read command and address to the EEPROM, check for ACK.
248 static void wb_eeprom_putbyte(sc, addr)
254 d = addr | WB_EECMD_READ;
257 * Feed in each bit and stobe the clock.
259 for (i = 0x400; i; i >>= 1) {
261 SIO_SET(WB_SIO_EE_DATAIN);
263 SIO_CLR(WB_SIO_EE_DATAIN);
266 SIO_SET(WB_SIO_EE_CLK);
268 SIO_CLR(WB_SIO_EE_CLK);
276 * Read a word of data stored in the EEPROM at address 'addr.'
278 static void wb_eeprom_getword(sc, addr, dest)
286 /* Enter EEPROM access mode. */
287 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
290 * Send address of word we want to read.
292 wb_eeprom_putbyte(sc, addr);
294 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
297 * Start reading bits from EEPROM.
299 for (i = 0x8000; i; i >>= 1) {
300 SIO_SET(WB_SIO_EE_CLK);
302 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
304 SIO_CLR(WB_SIO_EE_CLK);
308 /* Turn off EEPROM access mode. */
309 CSR_WRITE_4(sc, WB_SIO, 0);
317 * Read a sequence of words from the EEPROM.
319 static void wb_read_eeprom(sc, dest, off, cnt, swap)
327 u_int16_t word = 0, *ptr;
329 for (i = 0; i < cnt; i++) {
330 wb_eeprom_getword(sc, off + i, &word);
331 ptr = (u_int16_t *)(dest + (i * 2));
342 * Sync the PHYs by setting data bit and strobing the clock 32 times.
344 static void wb_mii_sync(sc)
349 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
351 for (i = 0; i < 32; i++) {
352 SIO_SET(WB_SIO_MII_CLK);
354 SIO_CLR(WB_SIO_MII_CLK);
362 * Clock a series of bits through the MII.
364 static void wb_mii_send(sc, bits, cnt)
371 SIO_CLR(WB_SIO_MII_CLK);
373 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
375 SIO_SET(WB_SIO_MII_DATAIN);
377 SIO_CLR(WB_SIO_MII_DATAIN);
380 SIO_CLR(WB_SIO_MII_CLK);
382 SIO_SET(WB_SIO_MII_CLK);
387 * Read an PHY register through the MII.
389 static int wb_mii_readreg(sc, frame)
391 struct wb_mii_frame *frame;
399 * Set up frame for RX.
401 frame->mii_stdelim = WB_MII_STARTDELIM;
402 frame->mii_opcode = WB_MII_READOP;
403 frame->mii_turnaround = 0;
406 CSR_WRITE_4(sc, WB_SIO, 0);
411 SIO_SET(WB_SIO_MII_DIR);
416 * Send command/address info.
418 wb_mii_send(sc, frame->mii_stdelim, 2);
419 wb_mii_send(sc, frame->mii_opcode, 2);
420 wb_mii_send(sc, frame->mii_phyaddr, 5);
421 wb_mii_send(sc, frame->mii_regaddr, 5);
424 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
426 SIO_SET(WB_SIO_MII_CLK);
430 SIO_CLR(WB_SIO_MII_DIR);
432 SIO_CLR(WB_SIO_MII_CLK);
434 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
435 SIO_SET(WB_SIO_MII_CLK);
437 SIO_CLR(WB_SIO_MII_CLK);
439 SIO_SET(WB_SIO_MII_CLK);
443 * Now try reading data bits. If the ack failed, we still
444 * need to clock through 16 cycles to keep the PHY(s) in sync.
447 for(i = 0; i < 16; i++) {
448 SIO_CLR(WB_SIO_MII_CLK);
450 SIO_SET(WB_SIO_MII_CLK);
456 for (i = 0x8000; i; i >>= 1) {
457 SIO_CLR(WB_SIO_MII_CLK);
460 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
461 frame->mii_data |= i;
464 SIO_SET(WB_SIO_MII_CLK);
470 SIO_CLR(WB_SIO_MII_CLK);
472 SIO_SET(WB_SIO_MII_CLK);
483 * Write to a PHY register through the MII.
485 static int wb_mii_writereg(sc, frame)
487 struct wb_mii_frame *frame;
494 * Set up frame for TX.
497 frame->mii_stdelim = WB_MII_STARTDELIM;
498 frame->mii_opcode = WB_MII_WRITEOP;
499 frame->mii_turnaround = WB_MII_TURNAROUND;
502 * Turn on data output.
504 SIO_SET(WB_SIO_MII_DIR);
508 wb_mii_send(sc, frame->mii_stdelim, 2);
509 wb_mii_send(sc, frame->mii_opcode, 2);
510 wb_mii_send(sc, frame->mii_phyaddr, 5);
511 wb_mii_send(sc, frame->mii_regaddr, 5);
512 wb_mii_send(sc, frame->mii_turnaround, 2);
513 wb_mii_send(sc, frame->mii_data, 16);
516 SIO_SET(WB_SIO_MII_CLK);
518 SIO_CLR(WB_SIO_MII_CLK);
524 SIO_CLR(WB_SIO_MII_DIR);
531 static int wb_miibus_readreg(dev, phy, reg)
536 struct wb_mii_frame frame;
538 sc = device_get_softc(dev);
540 bzero((char *)&frame, sizeof(frame));
542 frame.mii_phyaddr = phy;
543 frame.mii_regaddr = reg;
544 wb_mii_readreg(sc, &frame);
546 return(frame.mii_data);
549 static int wb_miibus_writereg(dev, phy, reg, data)
554 struct wb_mii_frame frame;
556 sc = device_get_softc(dev);
558 bzero((char *)&frame, sizeof(frame));
560 frame.mii_phyaddr = phy;
561 frame.mii_regaddr = reg;
562 frame.mii_data = data;
564 wb_mii_writereg(sc, &frame);
569 static void wb_miibus_statchg(dev)
573 struct mii_data *mii;
575 sc = device_get_softc(dev);
576 mii = device_get_softc(sc->wb_miibus);
577 wb_setcfg(sc, mii->mii_media_active);
582 static u_int8_t wb_calchash(addr)
585 u_int32_t crc, carry;
589 /* Compute CRC for the address value. */
590 crc = 0xFFFFFFFF; /* initial value */
592 for (i = 0; i < 6; i++) {
594 for (j = 0; j < 8; j++) {
595 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
599 crc = (crc ^ 0x04c11db6) | carry;
604 * return the filter bit position
605 * Note: I arrived at the following nonsense
606 * through experimentation. It's not the usual way to
607 * generate the bit position but it's the only thing
608 * I could come up with that works.
610 return(~(crc >> 26) & 0x0000003F);
614 * Program the 64-bit multicast hash filter.
616 static void wb_setmulti(sc)
621 u_int32_t hashes[2] = { 0, 0 };
622 struct ifmultiaddr *ifma;
626 ifp = &sc->arpcom.ac_if;
628 rxfilt = CSR_READ_4(sc, WB_NETCFG);
630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
631 rxfilt |= WB_NETCFG_RX_MULTI;
632 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
633 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
634 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
638 /* first, zot all the existing hash bits */
639 CSR_WRITE_4(sc, WB_MAR0, 0);
640 CSR_WRITE_4(sc, WB_MAR1, 0);
642 /* now program new ones */
643 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
644 ifma = ifma->ifma_link.le_next) {
645 if (ifma->ifma_addr->sa_family != AF_LINK)
647 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
649 hashes[0] |= (1 << h);
651 hashes[1] |= (1 << (h - 32));
656 rxfilt |= WB_NETCFG_RX_MULTI;
658 rxfilt &= ~WB_NETCFG_RX_MULTI;
660 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
661 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
662 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
668 * The Winbond manual states that in order to fiddle with the
669 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
670 * first have to put the transmit and/or receive logic in the idle state.
672 static void wb_setcfg(sc, media)
678 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
680 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
682 for (i = 0; i < WB_TIMEOUT; i++) {
684 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
685 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
690 printf("wb%d: failed to force tx and "
691 "rx to idle state\n", sc->wb_unit);
694 if (IFM_SUBTYPE(media) == IFM_10_T)
695 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
697 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
699 if ((media & IFM_GMASK) == IFM_FDX)
700 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
702 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
705 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
710 static void wb_reset(sc)
714 struct mii_data *mii;
716 CSR_WRITE_4(sc, WB_NETCFG, 0);
717 CSR_WRITE_4(sc, WB_BUSCTL, 0);
718 CSR_WRITE_4(sc, WB_TXADDR, 0);
719 CSR_WRITE_4(sc, WB_RXADDR, 0);
721 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
722 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
724 for (i = 0; i < WB_TIMEOUT; i++) {
726 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
730 printf("wb%d: reset never completed!\n", sc->wb_unit);
732 /* Wait a little while for the chip to get its brains in order. */
735 if (sc->wb_miibus == NULL)
738 mii = device_get_softc(sc->wb_miibus);
742 if (mii->mii_instance) {
743 struct mii_softc *miisc;
744 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
745 miisc = LIST_NEXT(miisc, mii_list))
746 mii_phy_reset(miisc);
752 static void wb_fixmedia(sc)
755 struct mii_data *mii = NULL;
759 if (sc->wb_miibus == NULL)
762 mii = device_get_softc(sc->wb_miibus);
763 ifp = &sc->arpcom.ac_if;
766 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
767 media = mii->mii_media_active & ~IFM_10_T;
769 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
770 media = mii->mii_media_active & ~IFM_100_TX;
775 ifmedia_set(&mii->mii_media, media);
781 * Probe for a Winbond chip. Check the PCI vendor and device
782 * IDs against our list and return a device name if we find a match.
784 static int wb_probe(dev)
791 while(t->wb_name != NULL) {
792 if ((pci_get_vendor(dev) == t->wb_vid) &&
793 (pci_get_device(dev) == t->wb_did)) {
794 device_set_desc(dev, t->wb_name);
804 * Attach the interface. Allocate softc structures, do ifmedia
805 * setup and ethernet/BPF attach.
807 static int wb_attach(dev)
811 u_char eaddr[ETHER_ADDR_LEN];
815 int unit, error = 0, rid;
819 sc = device_get_softc(dev);
820 unit = device_get_unit(dev);
821 callout_init(&sc->wb_stat_timer);
824 * Handle power management nonsense.
827 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF;
828 if (command == 0x01) {
830 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4);
831 if (command & WB_PSTATE_MASK) {
832 u_int32_t iobase, membase, irq;
834 /* Save important PCI config data. */
835 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
836 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
837 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
839 /* Reset the power state. */
840 printf("wb%d: chip is in D%d power mode "
841 "-- setting to D0\n", unit, command & WB_PSTATE_MASK);
842 command &= 0xFFFFFFFC;
843 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4);
845 /* Restore PCI config data. */
846 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
847 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
848 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
853 * Map control/status registers.
855 command = pci_read_config(dev, PCIR_COMMAND, 4);
856 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
857 pci_write_config(dev, PCIR_COMMAND, command, 4);
858 command = pci_read_config(dev, PCIR_COMMAND, 4);
861 if (!(command & PCIM_CMD_PORTEN)) {
862 printf("wb%d: failed to enable I/O ports!\n", unit);
867 if (!(command & PCIM_CMD_MEMEN)) {
868 printf("wb%d: failed to enable memory mapping!\n", unit);
875 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid,
876 0, ~0, 1, RF_ACTIVE);
878 if (sc->wb_res == NULL) {
879 printf("wb%d: couldn't map ports/memory\n", unit);
884 sc->wb_btag = rman_get_bustag(sc->wb_res);
885 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
887 /* Allocate interrupt */
889 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
890 RF_SHAREABLE | RF_ACTIVE);
892 if (sc->wb_irq == NULL) {
893 printf("wb%d: couldn't map interrupt\n", unit);
894 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
899 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET,
900 wb_intr, sc, &sc->wb_intrhand);
903 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
904 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
905 printf("wb%d: couldn't set up irq\n", unit);
909 /* Save the cache line size. */
910 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
912 /* Reset the adapter. */
916 * Get station address from the EEPROM.
918 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
922 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
923 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
925 if (sc->wb_ldata == NULL) {
926 printf("wb%d: no memory for list buffers!\n", unit);
927 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
928 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
929 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
934 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
936 ifp = &sc->arpcom.ac_if;
938 if_initname(ifp, "wb", unit);
939 ifp->if_mtu = ETHERMTU;
940 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
941 ifp->if_ioctl = wb_ioctl;
942 ifp->if_start = wb_start;
943 ifp->if_watchdog = wb_watchdog;
944 ifp->if_init = wb_init;
945 ifp->if_baudrate = 10000000;
946 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1);
947 ifq_set_ready(&ifp->if_snd);
952 if (mii_phy_probe(dev, &sc->wb_miibus,
953 wb_ifmedia_upd, wb_ifmedia_sts)) {
954 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
956 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
957 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
958 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
964 * Call MI attach routine.
966 ether_ifattach(ifp, eaddr);
970 device_delete_child(dev, sc->wb_miibus);
976 static int wb_detach(dev)
985 sc = device_get_softc(dev);
986 ifp = &sc->arpcom.ac_if;
991 /* Delete any miibus and phy devices attached to this interface */
992 bus_generic_detach(dev);
993 device_delete_child(dev, sc->wb_miibus);
995 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
996 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
997 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
999 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
1008 * Initialize the transmit descriptors.
1010 static int wb_list_tx_init(sc)
1011 struct wb_softc *sc;
1013 struct wb_chain_data *cd;
1014 struct wb_list_data *ld;
1020 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1021 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
1022 if (i == (WB_TX_LIST_CNT - 1)) {
1023 cd->wb_tx_chain[i].wb_nextdesc =
1024 &cd->wb_tx_chain[0];
1026 cd->wb_tx_chain[i].wb_nextdesc =
1027 &cd->wb_tx_chain[i + 1];
1031 cd->wb_tx_free = &cd->wb_tx_chain[0];
1032 cd->wb_tx_tail = cd->wb_tx_head = NULL;
1039 * Initialize the RX descriptors and allocate mbufs for them. Note that
1040 * we arrange the descriptors in a closed ring, so that the last descriptor
1041 * points back to the first.
1043 static int wb_list_rx_init(sc)
1044 struct wb_softc *sc;
1046 struct wb_chain_data *cd;
1047 struct wb_list_data *ld;
1053 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1054 cd->wb_rx_chain[i].wb_ptr =
1055 (struct wb_desc *)&ld->wb_rx_list[i];
1056 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
1057 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
1059 if (i == (WB_RX_LIST_CNT - 1)) {
1060 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
1061 ld->wb_rx_list[i].wb_next =
1062 vtophys(&ld->wb_rx_list[0]);
1064 cd->wb_rx_chain[i].wb_nextdesc =
1065 &cd->wb_rx_chain[i + 1];
1066 ld->wb_rx_list[i].wb_next =
1067 vtophys(&ld->wb_rx_list[i + 1]);
1071 cd->wb_rx_head = &cd->wb_rx_chain[0];
1076 static void wb_bfree(buf, size)
1084 * Initialize an RX descriptor and attach an MBUF cluster.
1086 static int wb_newbuf(sc, c, m)
1087 struct wb_softc *sc;
1088 struct wb_chain_onefrag *c;
1091 struct mbuf *m_new = NULL;
1094 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1098 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
1099 m_new->m_flags |= M_EXT | M_EXT_OLD;
1100 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1101 m_new->m_len = WB_BUFBYTES;
1102 m_new->m_ext.ext_nfree.old = wb_bfree;
1103 m_new->m_ext.ext_nref.old = wb_bfree;
1106 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1107 m_new->m_data = m_new->m_ext.ext_buf;
1110 m_adj(m_new, sizeof(u_int64_t));
1113 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1114 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1115 c->wb_ptr->wb_status = WB_RXSTAT;
1121 * A frame has been uploaded: pass the resulting mbuf chain up to
1122 * the higher level protocols.
1124 static void wb_rxeof(sc)
1125 struct wb_softc *sc;
1127 struct mbuf *m = NULL;
1129 struct wb_chain_onefrag *cur_rx;
1133 ifp = &sc->arpcom.ac_if;
1135 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1137 struct mbuf *m0 = NULL;
1139 cur_rx = sc->wb_cdata.wb_rx_head;
1140 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1142 m = cur_rx->wb_mbuf;
1144 if ((rxstat & WB_RXSTAT_MIIERR) ||
1145 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1146 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1147 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1148 !(rxstat & WB_RXSTAT_RXCMP)) {
1150 wb_newbuf(sc, cur_rx, m);
1151 printf("wb%x: receiver babbling: possible chip "
1152 "bug, forcing reset\n", sc->wb_unit);
1159 if (rxstat & WB_RXSTAT_RXERR) {
1161 wb_newbuf(sc, cur_rx, m);
1165 /* No errors; receive the packet. */
1166 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1169 * XXX The Winbond chip includes the CRC with every
1170 * received frame, and there's no way to turn this
1171 * behavior off (at least, I can't find anything in
1172 * the manual that explains how to do it) so we have
1173 * to trim off the CRC manually.
1175 total_len -= ETHER_CRC_LEN;
1177 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1178 total_len + ETHER_ALIGN, 0, ifp, NULL);
1179 wb_newbuf(sc, cur_rx, m);
1184 m_adj(m0, ETHER_ALIGN);
1188 (*ifp->if_input)(ifp, m);
1193 struct wb_softc *sc;
1197 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1198 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1199 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1200 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1201 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1207 * A frame was downloaded to the chip. It's safe for us to clean up
1210 static void wb_txeof(sc)
1211 struct wb_softc *sc;
1213 struct wb_chain *cur_tx;
1216 ifp = &sc->arpcom.ac_if;
1218 /* Clear the timeout timer. */
1221 if (sc->wb_cdata.wb_tx_head == NULL)
1225 * Go through our tx list and free mbufs for those
1226 * frames that have been transmitted.
1228 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1231 cur_tx = sc->wb_cdata.wb_tx_head;
1232 txstat = WB_TXSTATUS(cur_tx);
1234 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1237 if (txstat & WB_TXSTAT_TXERR) {
1239 if (txstat & WB_TXSTAT_ABORT)
1240 ifp->if_collisions++;
1241 if (txstat & WB_TXSTAT_LATECOLL)
1242 ifp->if_collisions++;
1245 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1248 m_freem(cur_tx->wb_mbuf);
1249 cur_tx->wb_mbuf = NULL;
1251 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1252 sc->wb_cdata.wb_tx_head = NULL;
1253 sc->wb_cdata.wb_tx_tail = NULL;
1257 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1264 * TX 'end of channel' interrupt handler.
1266 static void wb_txeoc(sc)
1267 struct wb_softc *sc;
1271 ifp = &sc->arpcom.ac_if;
1275 if (sc->wb_cdata.wb_tx_head == NULL) {
1276 ifp->if_flags &= ~IFF_OACTIVE;
1277 sc->wb_cdata.wb_tx_tail = NULL;
1279 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1280 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1282 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1289 static void wb_intr(arg)
1292 struct wb_softc *sc;
1297 ifp = &sc->arpcom.ac_if;
1299 if (!(ifp->if_flags & IFF_UP))
1302 /* Disable interrupts. */
1303 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1307 status = CSR_READ_4(sc, WB_ISR);
1309 CSR_WRITE_4(sc, WB_ISR, status);
1311 if ((status & WB_INTRS) == 0)
1314 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1317 if (status & WB_ISR_RX_ERR)
1323 if (status & WB_ISR_RX_OK)
1326 if (status & WB_ISR_RX_IDLE)
1329 if (status & WB_ISR_TX_OK)
1332 if (status & WB_ISR_TX_NOBUF)
1335 if (status & WB_ISR_TX_IDLE) {
1337 if (sc->wb_cdata.wb_tx_head != NULL) {
1338 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1339 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1343 if (status & WB_ISR_TX_UNDERRUN) {
1346 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1347 /* Jack up TX threshold */
1348 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1349 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1350 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1351 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1354 if (status & WB_ISR_BUS_ERR) {
1361 /* Re-enable interrupts. */
1362 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1364 if (!ifq_is_empty(&ifp->if_snd)) {
1371 static void wb_tick(xsc)
1374 struct wb_softc *sc;
1375 struct mii_data *mii;
1381 mii = device_get_softc(sc->wb_miibus);
1385 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1393 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1394 * pointers to the fragment pointers.
1396 static int wb_encap(sc, c, m_head)
1397 struct wb_softc *sc;
1399 struct mbuf *m_head;
1402 struct wb_desc *f = NULL;
1407 * Start packing the mbufs in this chain into
1408 * the fragment pointers. Stop when we run out
1409 * of fragments or hit the end of the mbuf chain.
1414 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1415 if (m->m_len != 0) {
1416 if (frag == WB_MAXFRAGS)
1418 total_len += m->m_len;
1419 f = &c->wb_ptr->wb_frag[frag];
1420 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1422 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1425 f->wb_status = WB_TXSTAT_OWN;
1426 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1427 f->wb_data = vtophys(mtod(m, vm_offset_t));
1433 * Handle special case: we used up all 16 fragments,
1434 * but we have more mbufs left in the chain. Copy the
1435 * data into an mbuf cluster. Note that we don't
1436 * bother clearing the values in the other fragment
1437 * pointers/counters; it wouldn't gain us anything,
1438 * and would waste cycles.
1441 struct mbuf *m_new = NULL;
1443 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1446 if (m_head->m_pkthdr.len > MHLEN) {
1447 MCLGET(m_new, MB_DONTWAIT);
1448 if (!(m_new->m_flags & M_EXT)) {
1453 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1454 mtod(m_new, caddr_t));
1455 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1458 f = &c->wb_ptr->wb_frag[0];
1460 f->wb_data = vtophys(mtod(m_new, caddr_t));
1461 f->wb_ctl = total_len = m_new->m_len;
1462 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1466 if (total_len < WB_MIN_FRAMELEN) {
1467 f = &c->wb_ptr->wb_frag[frag];
1468 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1469 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1470 f->wb_ctl |= WB_TXCTL_TLINK;
1471 f->wb_status = WB_TXSTAT_OWN;
1475 c->wb_mbuf = m_head;
1476 c->wb_lastdesc = frag - 1;
1477 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1478 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1484 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1485 * to the mbuf data regions directly in the transmit lists. We also save a
1486 * copy of the pointers since the transmit list fragment pointers are
1487 * physical addresses.
1490 static void wb_start(ifp)
1493 struct wb_softc *sc;
1494 struct mbuf *m_head = NULL;
1495 struct wb_chain *cur_tx = NULL, *start_tx;
1500 * Check for an available queue slot. If there are none,
1503 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1504 ifp->if_flags |= IFF_OACTIVE;
1508 start_tx = sc->wb_cdata.wb_tx_free;
1510 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1511 m_head = ifq_dequeue(&ifp->if_snd);
1515 /* Pick a descriptor off the free list. */
1516 cur_tx = sc->wb_cdata.wb_tx_free;
1517 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1519 /* Pack the data into the descriptor. */
1520 wb_encap(sc, cur_tx, m_head);
1522 if (cur_tx != start_tx)
1523 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1525 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1529 * If there are no packets queued, bail.
1535 * Place the request for the upload interrupt
1536 * in the last descriptor in the chain. This way, if
1537 * we're chaining several packets at once, we'll only
1538 * get an interupt once for the whole chain rather than
1539 * once for each packet.
1541 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1542 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1543 sc->wb_cdata.wb_tx_tail = cur_tx;
1545 if (sc->wb_cdata.wb_tx_head == NULL) {
1546 sc->wb_cdata.wb_tx_head = start_tx;
1547 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1548 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1551 * We need to distinguish between the case where
1552 * the own bit is clear because the chip cleared it
1553 * and where the own bit is clear because we haven't
1554 * set it yet. The magic value WB_UNSET is just some
1555 * ramdomly chosen number which doesn't have the own
1556 * bit set. When we actually transmit the frame, the
1557 * status word will have _only_ the own bit set, so
1558 * the txeoc handler will be able to tell if it needs
1559 * to initiate another transmission to flush out pending
1562 WB_TXOWN(start_tx) = WB_UNSENT;
1566 * Set a timeout in case the chip goes out to lunch.
1573 static void wb_init(xsc)
1576 struct wb_softc *sc = xsc;
1577 struct ifnet *ifp = &sc->arpcom.ac_if;
1579 struct mii_data *mii;
1583 mii = device_get_softc(sc->wb_miibus);
1586 * Cancel pending I/O and free all RX/TX buffers.
1591 sc->wb_txthresh = WB_TXTHRESH_INIT;
1594 * Set cache alignment and burst length.
1597 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1598 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1599 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1602 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1603 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1604 switch(sc->wb_cachesize) {
1606 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1609 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1612 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1616 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1620 /* This doesn't tend to work too well at 100Mbps. */
1621 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1623 /* Init our MAC address */
1624 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1625 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1628 /* Init circular RX list. */
1629 if (wb_list_rx_init(sc) == ENOBUFS) {
1630 printf("wb%d: initialization failed: no "
1631 "memory for rx buffers\n", sc->wb_unit);
1637 /* Init TX descriptors. */
1638 wb_list_tx_init(sc);
1640 /* If we want promiscuous mode, set the allframes bit. */
1641 if (ifp->if_flags & IFF_PROMISC) {
1642 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1644 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1648 * Set capture broadcast bit to capture broadcast frames.
1650 if (ifp->if_flags & IFF_BROADCAST) {
1651 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1653 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1657 * Program the multicast filter, if necessary.
1662 * Load the address of the RX list.
1664 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1665 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1668 * Enable interrupts.
1670 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1671 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1673 /* Enable receiver and transmitter. */
1674 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1675 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1677 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1678 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1679 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1683 ifp->if_flags |= IFF_RUNNING;
1684 ifp->if_flags &= ~IFF_OACTIVE;
1688 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
1692 * Set media options.
1694 static int wb_ifmedia_upd(ifp)
1697 struct wb_softc *sc;
1701 if (ifp->if_flags & IFF_UP)
1708 * Report current media status.
1710 static void wb_ifmedia_sts(ifp, ifmr)
1712 struct ifmediareq *ifmr;
1714 struct wb_softc *sc;
1715 struct mii_data *mii;
1719 mii = device_get_softc(sc->wb_miibus);
1722 ifmr->ifm_active = mii->mii_media_active;
1723 ifmr->ifm_status = mii->mii_media_status;
1728 static int wb_ioctl(ifp, command, data, cr)
1734 struct wb_softc *sc = ifp->if_softc;
1735 struct mii_data *mii;
1736 struct ifreq *ifr = (struct ifreq *) data;
1745 error = ether_ioctl(ifp, command, data);
1748 if (ifp->if_flags & IFF_UP) {
1751 if (ifp->if_flags & IFF_RUNNING)
1763 mii = device_get_softc(sc->wb_miibus);
1764 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1776 static void wb_watchdog(ifp)
1779 struct wb_softc *sc;
1784 printf("wb%d: watchdog timeout\n", sc->wb_unit);
1786 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1787 printf("wb%d: no carrier - transceiver cable problem?\n",
1794 if (!ifq_is_empty(&ifp->if_snd))
1801 * Stop the adapter and free any mbufs allocated to the
1804 static void wb_stop(sc)
1805 struct wb_softc *sc;
1810 ifp = &sc->arpcom.ac_if;
1813 callout_stop(&sc->wb_stat_timer);
1815 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1816 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1817 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1818 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1821 * Free data in the RX lists.
1823 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1824 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1825 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1826 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1829 bzero((char *)&sc->wb_ldata->wb_rx_list,
1830 sizeof(sc->wb_ldata->wb_rx_list));
1833 * Free the TX list buffers.
1835 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1836 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1837 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1838 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1842 bzero((char *)&sc->wb_ldata->wb_tx_list,
1843 sizeof(sc->wb_ldata->wb_tx_list));
1845 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1851 * Stop all chip I/O so that the kernel's probe routines don't
1852 * get confused by errant DMAs when rebooting.
1854 static void wb_shutdown(dev)
1857 struct wb_softc *sc;
1859 sc = device_get_softc(dev);