2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/bitops.h>
37 #include <sys/endian.h>
38 #include <sys/kernel.h>
40 #include <sys/interrupt.h>
41 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/ifq_var.h>
56 #include <net/vlan/if_vlan_var.h>
58 #include <dev/netif/mii_layer/miivar.h>
60 #include <bus/pci/pcireg.h>
61 #include <bus/pci/pcivar.h>
64 #include <dev/netif/et/if_etreg.h>
65 #include <dev/netif/et/if_etvar.h>
67 #include "miibus_if.h"
69 static int et_probe(device_t);
70 static int et_attach(device_t);
71 static int et_detach(device_t);
72 static int et_shutdown(device_t);
74 static int et_miibus_readreg(device_t, int, int);
75 static int et_miibus_writereg(device_t, int, int, int);
76 static void et_miibus_statchg(device_t);
78 static void et_init(void *);
79 static int et_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
80 static void et_start(struct ifnet *, struct ifaltq_subque *);
81 static void et_watchdog(struct ifnet *);
82 static int et_ifmedia_upd(struct ifnet *);
83 static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *);
85 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS);
86 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS);
88 static void et_intr(void *);
89 static void et_enable_intrs(struct et_softc *, uint32_t);
90 static void et_disable_intrs(struct et_softc *);
91 static void et_rxeof(struct et_softc *);
92 static void et_txeof(struct et_softc *, int);
94 static int et_dma_alloc(device_t);
95 static void et_dma_free(device_t);
96 static void et_dma_mem_destroy(bus_dma_tag_t, void *, bus_dmamap_t);
97 static int et_dma_mbuf_create(device_t);
98 static void et_dma_mbuf_destroy(device_t, int, const int[]);
99 static int et_jumbo_mem_alloc(device_t);
100 static void et_jumbo_mem_free(device_t);
101 static int et_init_tx_ring(struct et_softc *);
102 static int et_init_rx_ring(struct et_softc *);
103 static void et_free_tx_ring(struct et_softc *);
104 static void et_free_rx_ring(struct et_softc *);
105 static int et_encap(struct et_softc *, struct mbuf **);
106 static struct et_jslot *
107 et_jalloc(struct et_jumbo_data *);
108 static void et_jfree(void *);
109 static void et_jref(void *);
110 static int et_newbuf(struct et_rxbuf_data *, int, int, int);
111 static int et_newbuf_cluster(struct et_rxbuf_data *, int, int);
112 static int et_newbuf_hdr(struct et_rxbuf_data *, int, int);
113 static int et_newbuf_jumbo(struct et_rxbuf_data *, int, int);
115 static void et_stop(struct et_softc *);
116 static int et_chip_init(struct et_softc *);
117 static void et_chip_attach(struct et_softc *);
118 static void et_init_mac(struct et_softc *);
119 static void et_init_rxmac(struct et_softc *);
120 static void et_init_txmac(struct et_softc *);
121 static int et_init_rxdma(struct et_softc *);
122 static int et_init_txdma(struct et_softc *);
123 static int et_start_rxdma(struct et_softc *);
124 static int et_start_txdma(struct et_softc *);
125 static int et_stop_rxdma(struct et_softc *);
126 static int et_stop_txdma(struct et_softc *);
127 static int et_enable_txrx(struct et_softc *, int);
128 static void et_reset(struct et_softc *);
129 static int et_bus_config(device_t);
130 static void et_get_eaddr(device_t, uint8_t[]);
131 static void et_setmulti(struct et_softc *);
132 static void et_tick(void *);
133 static void et_setmedia(struct et_softc *);
134 static void et_setup_rxdesc(struct et_rxbuf_data *, int, bus_addr_t);
136 static const struct et_dev {
141 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310,
142 "Agere ET1310 Gigabit Ethernet" },
143 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST,
144 "Agere ET1310 Fast Ethernet" },
148 static device_method_t et_methods[] = {
149 DEVMETHOD(device_probe, et_probe),
150 DEVMETHOD(device_attach, et_attach),
151 DEVMETHOD(device_detach, et_detach),
152 DEVMETHOD(device_shutdown, et_shutdown),
154 DEVMETHOD(device_suspend, et_suspend),
155 DEVMETHOD(device_resume, et_resume),
158 DEVMETHOD(bus_print_child, bus_generic_print_child),
159 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
161 DEVMETHOD(miibus_readreg, et_miibus_readreg),
162 DEVMETHOD(miibus_writereg, et_miibus_writereg),
163 DEVMETHOD(miibus_statchg, et_miibus_statchg),
168 static driver_t et_driver = {
171 sizeof(struct et_softc)
174 static devclass_t et_devclass;
176 DECLARE_DUMMY_MODULE(if_et);
177 MODULE_DEPEND(if_et, miibus, 1, 1, 1);
178 DRIVER_MODULE(if_et, pci, et_driver, et_devclass, NULL, NULL);
179 DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, NULL, NULL);
181 static int et_rx_intr_npkts = 129;
182 static int et_rx_intr_delay = 25; /* x4 usec */
183 static int et_tx_intr_nsegs = 256;
184 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */
186 static int et_msi_enable = 1;
188 TUNABLE_INT("hw.et.timer", &et_timer);
189 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts);
190 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay);
191 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs);
192 TUNABLE_INT("hw.et.msi.enable", &et_msi_enable);
200 static const struct et_bsize et_bufsize_std[ET_RX_NRING] = {
201 { .bufsize = ET_RXDMA_CTRL_RING0_128, .jumbo = 0,
202 .newbuf = et_newbuf_hdr },
203 { .bufsize = ET_RXDMA_CTRL_RING1_2048, .jumbo = 0,
204 .newbuf = et_newbuf_cluster },
207 static const struct et_bsize et_bufsize_jumbo[ET_RX_NRING] = {
208 { .bufsize = ET_RXDMA_CTRL_RING0_128, .jumbo = 0,
209 .newbuf = et_newbuf_hdr },
210 { .bufsize = ET_RXDMA_CTRL_RING1_16384, .jumbo = 1,
211 .newbuf = et_newbuf_jumbo },
215 et_probe(device_t dev)
217 const struct et_dev *d;
220 vid = pci_get_vendor(dev);
221 did = pci_get_device(dev);
223 for (d = et_devices; d->desc != NULL; ++d) {
224 if (vid == d->vid && did == d->did) {
225 device_set_desc(dev, d->desc);
233 et_attach(device_t dev)
235 struct et_softc *sc = device_get_softc(dev);
236 struct ifnet *ifp = &sc->arpcom.ac_if;
237 uint8_t eaddr[ETHER_ADDR_LEN];
241 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
242 callout_init(&sc->sc_tick);
245 * Initialize tunables
247 sc->sc_rx_intr_npkts = et_rx_intr_npkts;
248 sc->sc_rx_intr_delay = et_rx_intr_delay;
249 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs;
250 sc->sc_timer = et_timer;
253 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
256 irq = pci_read_config(dev, PCIR_INTLINE, 4);
257 mem = pci_read_config(dev, ET_PCIR_BAR, 4);
259 device_printf(dev, "chip is in D%d power mode "
260 "-- setting to D0\n", pci_get_powerstate(dev));
262 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
264 pci_write_config(dev, PCIR_INTLINE, irq, 4);
265 pci_write_config(dev, ET_PCIR_BAR, mem, 4);
267 #endif /* !BURN_BRIDGE */
269 /* Enable bus mastering */
270 pci_enable_busmaster(dev);
275 sc->sc_mem_rid = ET_PCIR_BAR;
276 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
277 &sc->sc_mem_rid, RF_ACTIVE);
278 if (sc->sc_mem_res == NULL) {
279 device_printf(dev, "can't allocate IO memory\n");
282 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
283 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
288 sc->sc_irq_type = pci_alloc_1intr(dev, et_msi_enable,
289 &sc->sc_irq_rid, &irq_flags);
290 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
291 &sc->sc_irq_rid, irq_flags);
292 if (sc->sc_irq_res == NULL) {
293 device_printf(dev, "can't allocate irq\n");
301 sysctl_ctx_init(&sc->sc_sysctl_ctx);
302 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
303 SYSCTL_STATIC_CHILDREN(_hw),
305 device_get_nameunit(dev),
307 if (sc->sc_sysctl_tree == NULL) {
308 device_printf(dev, "can't add sysctl node\n");
313 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
314 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
315 OID_AUTO, "rx_intr_npkts", CTLTYPE_INT | CTLFLAG_RW,
316 sc, 0, et_sysctl_rx_intr_npkts, "I",
317 "RX IM, # packets per RX interrupt");
318 SYSCTL_ADD_PROC(&sc->sc_sysctl_ctx,
319 SYSCTL_CHILDREN(sc->sc_sysctl_tree),
320 OID_AUTO, "rx_intr_delay", CTLTYPE_INT | CTLFLAG_RW,
321 sc, 0, et_sysctl_rx_intr_delay, "I",
322 "RX IM, RX interrupt delay (x10 usec)");
323 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
324 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
325 "tx_intr_nsegs", CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0,
326 "TX IM, # segments per TX interrupt");
327 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
328 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
329 "timer", CTLFLAG_RW, &sc->sc_timer, 0,
332 error = et_bus_config(dev);
336 et_get_eaddr(dev, eaddr);
338 CSR_WRITE_4(sc, ET_PM,
339 ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE);
343 et_disable_intrs(sc);
345 error = et_dma_alloc(dev);
350 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
351 ifp->if_init = et_init;
352 ifp->if_ioctl = et_ioctl;
353 ifp->if_start = et_start;
354 ifp->if_watchdog = et_watchdog;
355 ifp->if_mtu = ETHERMTU;
356 ifp->if_capabilities = IFCAP_VLAN_MTU;
357 ifp->if_capenable = ifp->if_capabilities;
358 ifq_set_maxlen(&ifp->if_snd, ET_TX_NDESC);
359 ifq_set_ready(&ifp->if_snd);
363 error = mii_phy_probe(dev, &sc->sc_miibus,
364 et_ifmedia_upd, et_ifmedia_sts);
366 device_printf(dev, "can't probe any PHY\n");
370 ether_ifattach(ifp, eaddr, NULL);
372 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq_res));
374 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, et_intr, sc,
375 &sc->sc_irq_handle, ifp->if_serializer);
378 device_printf(dev, "can't setup intr\n");
389 et_detach(device_t dev)
391 struct et_softc *sc = device_get_softc(dev);
393 if (device_is_attached(dev)) {
394 struct ifnet *ifp = &sc->arpcom.ac_if;
396 lwkt_serialize_enter(ifp->if_serializer);
398 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
399 lwkt_serialize_exit(ifp->if_serializer);
404 if (sc->sc_sysctl_tree != NULL)
405 sysctl_ctx_free(&sc->sc_sysctl_ctx);
407 if (sc->sc_miibus != NULL)
408 device_delete_child(dev, sc->sc_miibus);
409 bus_generic_detach(dev);
411 if (sc->sc_irq_res != NULL) {
412 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
415 if (sc->sc_irq_type == PCI_INTR_TYPE_MSI)
416 pci_release_msi(dev);
418 if (sc->sc_mem_res != NULL) {
419 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
429 et_shutdown(device_t dev)
431 struct et_softc *sc = device_get_softc(dev);
432 struct ifnet *ifp = &sc->arpcom.ac_if;
434 lwkt_serialize_enter(ifp->if_serializer);
436 lwkt_serialize_exit(ifp->if_serializer);
441 et_miibus_readreg(device_t dev, int phy, int reg)
443 struct et_softc *sc = device_get_softc(dev);
447 /* Stop any pending operations */
448 CSR_WRITE_4(sc, ET_MII_CMD, 0);
450 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
451 __SHIFTIN(reg, ET_MII_ADDR_REG);
452 CSR_WRITE_4(sc, ET_MII_ADDR, val);
455 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ);
459 for (i = 0; i < NRETRY; ++i) {
460 val = CSR_READ_4(sc, ET_MII_IND);
461 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0)
466 if_printf(&sc->arpcom.ac_if,
467 "read phy %d, reg %d timed out\n", phy, reg);
474 val = CSR_READ_4(sc, ET_MII_STAT);
475 ret = __SHIFTOUT(val, ET_MII_STAT_VALUE);
478 /* Make sure that the current operation is stopped */
479 CSR_WRITE_4(sc, ET_MII_CMD, 0);
484 et_miibus_writereg(device_t dev, int phy, int reg, int val0)
486 struct et_softc *sc = device_get_softc(dev);
490 /* Stop any pending operations */
491 CSR_WRITE_4(sc, ET_MII_CMD, 0);
493 val = __SHIFTIN(phy, ET_MII_ADDR_PHY) |
494 __SHIFTIN(reg, ET_MII_ADDR_REG);
495 CSR_WRITE_4(sc, ET_MII_ADDR, val);
498 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE));
502 for (i = 0; i < NRETRY; ++i) {
503 val = CSR_READ_4(sc, ET_MII_IND);
504 if ((val & ET_MII_IND_BUSY) == 0)
509 if_printf(&sc->arpcom.ac_if,
510 "write phy %d, reg %d timed out\n", phy, reg);
511 et_miibus_readreg(dev, phy, reg);
516 /* Make sure that the current operation is stopped */
517 CSR_WRITE_4(sc, ET_MII_CMD, 0);
522 et_miibus_statchg(device_t dev)
524 et_setmedia(device_get_softc(dev));
528 et_ifmedia_upd(struct ifnet *ifp)
530 struct et_softc *sc = ifp->if_softc;
531 struct mii_data *mii = device_get_softc(sc->sc_miibus);
533 if (mii->mii_instance != 0) {
534 struct mii_softc *miisc;
536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
537 mii_phy_reset(miisc);
545 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
547 struct et_softc *sc = ifp->if_softc;
548 struct mii_data *mii = device_get_softc(sc->sc_miibus);
551 ifmr->ifm_active = mii->mii_media_active;
552 ifmr->ifm_status = mii->mii_media_status;
556 et_stop(struct et_softc *sc)
558 struct ifnet *ifp = &sc->arpcom.ac_if;
560 ASSERT_SERIALIZED(ifp->if_serializer);
562 callout_stop(&sc->sc_tick);
567 et_disable_intrs(sc);
576 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED;
579 ifp->if_flags &= ~IFF_RUNNING;
580 ifq_clr_oactive(&ifp->if_snd);
584 et_bus_config(device_t dev)
586 uint32_t val, max_plsz;
587 uint16_t ack_latency, replay_timer;
590 * Test whether EEPROM is valid
591 * NOTE: Read twice to get the correct value
593 pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1);
594 val = pci_read_config(dev, ET_PCIR_EEPROM_STATUS, 1);
595 if (val & ET_PCIM_EEPROM_STATUS_ERROR) {
596 device_printf(dev, "EEPROM status error 0x%02x\n", val);
603 * Configure ACK latency and replay timer according to
606 val = pci_read_config(dev, ET_PCIR_DEVICE_CAPS, 4);
607 max_plsz = val & ET_PCIM_DEVICE_CAPS_MAX_PLSZ;
610 case ET_PCIV_DEVICE_CAPS_PLSZ_128:
611 ack_latency = ET_PCIV_ACK_LATENCY_128;
612 replay_timer = ET_PCIV_REPLAY_TIMER_128;
615 case ET_PCIV_DEVICE_CAPS_PLSZ_256:
616 ack_latency = ET_PCIV_ACK_LATENCY_256;
617 replay_timer = ET_PCIV_REPLAY_TIMER_256;
621 ack_latency = pci_read_config(dev, ET_PCIR_ACK_LATENCY, 2);
622 replay_timer = pci_read_config(dev, ET_PCIR_REPLAY_TIMER, 2);
623 device_printf(dev, "ack latency %u, replay timer %u\n",
624 ack_latency, replay_timer);
627 if (ack_latency != 0) {
628 pci_write_config(dev, ET_PCIR_ACK_LATENCY, ack_latency, 2);
629 pci_write_config(dev, ET_PCIR_REPLAY_TIMER, replay_timer, 2);
633 * Set L0s and L1 latency timer to 2us
635 val = ET_PCIV_L0S_LATENCY(2) | ET_PCIV_L1_LATENCY(2);
636 pci_write_config(dev, ET_PCIR_L0S_L1_LATENCY, val, 1);
639 * Set max read request size to 2048 bytes
641 val = pci_read_config(dev, ET_PCIR_DEVICE_CTRL, 2);
642 val &= ~ET_PCIM_DEVICE_CTRL_MAX_RRSZ;
643 val |= ET_PCIV_DEVICE_CTRL_RRSZ_2K;
644 pci_write_config(dev, ET_PCIR_DEVICE_CTRL, val, 2);
650 et_get_eaddr(device_t dev, uint8_t eaddr[])
655 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4);
656 for (i = 0; i < 4; ++i)
657 eaddr[i] = (val >> (8 * i)) & 0xff;
659 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2);
660 for (; i < ETHER_ADDR_LEN; ++i)
661 eaddr[i] = (val >> (8 * (i - 4))) & 0xff;
665 et_reset(struct et_softc *sc)
667 CSR_WRITE_4(sc, ET_MAC_CFG1,
668 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
669 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
670 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
672 CSR_WRITE_4(sc, ET_SWRST,
673 ET_SWRST_TXDMA | ET_SWRST_RXDMA |
674 ET_SWRST_TXMAC | ET_SWRST_RXMAC |
675 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC);
677 CSR_WRITE_4(sc, ET_MAC_CFG1,
678 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
679 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC);
680 CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
684 et_disable_intrs(struct et_softc *sc)
686 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
690 et_enable_intrs(struct et_softc *sc, uint32_t intrs)
692 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs);
696 et_dma_alloc(device_t dev)
698 struct et_softc *sc = device_get_softc(dev);
699 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
700 struct et_txstatus_data *txsd = &sc->sc_tx_status;
701 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
702 struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
706 * Create top level DMA tag
708 error = bus_dma_tag_create(NULL, 1, 0,
712 BUS_SPACE_MAXSIZE_32BIT,
714 BUS_SPACE_MAXSIZE_32BIT,
717 device_printf(dev, "can't create DMA tag\n");
722 * Create TX ring DMA stuffs
724 tx_ring->tr_desc = bus_dmamem_coherent_any(sc->sc_dtag,
725 ET_ALIGN, ET_TX_RING_SIZE,
726 BUS_DMA_WAITOK | BUS_DMA_ZERO,
727 &tx_ring->tr_dtag, &tx_ring->tr_dmap,
729 if (tx_ring->tr_desc == NULL) {
730 device_printf(dev, "can't create TX ring DMA stuffs\n");
735 * Create TX status DMA stuffs
737 txsd->txsd_status = bus_dmamem_coherent_any(sc->sc_dtag,
738 ET_ALIGN, sizeof(uint32_t),
739 BUS_DMA_WAITOK | BUS_DMA_ZERO,
740 &txsd->txsd_dtag, &txsd->txsd_dmap,
742 if (txsd->txsd_status == NULL) {
743 device_printf(dev, "can't create TX status DMA stuffs\n");
748 * Create DMA stuffs for RX rings
750 for (i = 0; i < ET_RX_NRING; ++i) {
751 static const uint32_t rx_ring_posreg[ET_RX_NRING] =
752 { ET_RX_RING0_POS, ET_RX_RING1_POS };
754 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
756 rx_ring->rr_desc = bus_dmamem_coherent_any(sc->sc_dtag,
757 ET_ALIGN, ET_RX_RING_SIZE,
758 BUS_DMA_WAITOK | BUS_DMA_ZERO,
759 &rx_ring->rr_dtag, &rx_ring->rr_dmap,
761 if (rx_ring->rr_desc == NULL) {
762 device_printf(dev, "can't create DMA stuffs for "
763 "the %d RX ring\n", i);
766 rx_ring->rr_posreg = rx_ring_posreg[i];
770 * Create RX stat ring DMA stuffs
772 rxst_ring->rsr_stat = bus_dmamem_coherent_any(sc->sc_dtag,
773 ET_ALIGN, ET_RXSTAT_RING_SIZE,
774 BUS_DMA_WAITOK | BUS_DMA_ZERO,
775 &rxst_ring->rsr_dtag, &rxst_ring->rsr_dmap,
776 &rxst_ring->rsr_paddr);
777 if (rxst_ring->rsr_stat == NULL) {
778 device_printf(dev, "can't create RX stat ring DMA stuffs\n");
783 * Create RX status DMA stuffs
785 rxsd->rxsd_status = bus_dmamem_coherent_any(sc->sc_dtag,
786 ET_ALIGN, sizeof(struct et_rxstatus),
787 BUS_DMA_WAITOK | BUS_DMA_ZERO,
788 &rxsd->rxsd_dtag, &rxsd->rxsd_dmap,
790 if (rxsd->rxsd_status == NULL) {
791 device_printf(dev, "can't create RX status DMA stuffs\n");
796 * Create mbuf DMA stuffs
798 error = et_dma_mbuf_create(dev);
803 * Create jumbo buffer DMA stuffs
804 * NOTE: Allow it to fail
806 if (et_jumbo_mem_alloc(dev) == 0)
807 sc->sc_flags |= ET_FLAG_JUMBO;
813 et_dma_free(device_t dev)
815 struct et_softc *sc = device_get_softc(dev);
816 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
817 struct et_txstatus_data *txsd = &sc->sc_tx_status;
818 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
819 struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
820 int i, rx_done[ET_RX_NRING];
823 * Destroy TX ring DMA stuffs
825 et_dma_mem_destroy(tx_ring->tr_dtag, tx_ring->tr_desc,
829 * Destroy TX status DMA stuffs
831 et_dma_mem_destroy(txsd->txsd_dtag, txsd->txsd_status,
835 * Destroy DMA stuffs for RX rings
837 for (i = 0; i < ET_RX_NRING; ++i) {
838 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[i];
840 et_dma_mem_destroy(rx_ring->rr_dtag, rx_ring->rr_desc,
845 * Destroy RX stat ring DMA stuffs
847 et_dma_mem_destroy(rxst_ring->rsr_dtag, rxst_ring->rsr_stat,
848 rxst_ring->rsr_dmap);
851 * Destroy RX status DMA stuffs
853 et_dma_mem_destroy(rxsd->rxsd_dtag, rxsd->rxsd_status,
857 * Destroy mbuf DMA stuffs
859 for (i = 0; i < ET_RX_NRING; ++i)
860 rx_done[i] = ET_RX_NDESC;
861 et_dma_mbuf_destroy(dev, ET_TX_NDESC, rx_done);
864 * Destroy jumbo buffer DMA stuffs
866 if (sc->sc_flags & ET_FLAG_JUMBO)
867 et_jumbo_mem_free(dev);
870 * Destroy top level DMA tag
872 if (sc->sc_dtag != NULL)
873 bus_dma_tag_destroy(sc->sc_dtag);
877 et_dma_mbuf_create(device_t dev)
879 struct et_softc *sc = device_get_softc(dev);
880 struct et_txbuf_data *tbd = &sc->sc_tx_data;
881 int i, error, rx_done[ET_RX_NRING];
884 * Create RX mbuf DMA tag
886 error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
887 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
889 MCLBYTES, 1, MCLBYTES,
890 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
893 device_printf(dev, "can't create RX mbuf DMA tag\n");
898 * Create spare DMA map for RX mbufs
900 error = bus_dmamap_create(sc->sc_rxbuf_dtag, BUS_DMA_WAITOK,
901 &sc->sc_rxbuf_tmp_dmap);
903 device_printf(dev, "can't create spare mbuf DMA map\n");
904 bus_dma_tag_destroy(sc->sc_rxbuf_dtag);
905 sc->sc_rxbuf_dtag = NULL;
910 * Create DMA maps for RX mbufs
912 bzero(rx_done, sizeof(rx_done));
913 for (i = 0; i < ET_RX_NRING; ++i) {
914 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
917 for (j = 0; j < ET_RX_NDESC; ++j) {
918 error = bus_dmamap_create(sc->sc_rxbuf_dtag,
920 &rbd->rbd_buf[j].rb_dmap);
922 device_printf(dev, "can't create %d RX mbuf "
923 "for %d RX ring\n", j, i);
925 et_dma_mbuf_destroy(dev, 0, rx_done);
929 rx_done[i] = ET_RX_NDESC;
932 rbd->rbd_ring = &sc->sc_rx_ring[i];
936 * Create TX mbuf DMA tag
938 error = bus_dma_tag_create(sc->sc_dtag, 1, 0,
939 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
941 ET_JUMBO_FRAMELEN, ET_NSEG_MAX, MCLBYTES,
942 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
946 device_printf(dev, "can't create TX mbuf DMA tag\n");
951 * Create DMA maps for TX mbufs
953 for (i = 0; i < ET_TX_NDESC; ++i) {
954 error = bus_dmamap_create(sc->sc_txbuf_dtag,
955 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
956 &tbd->tbd_buf[i].tb_dmap);
958 device_printf(dev, "can't create %d TX mbuf "
960 et_dma_mbuf_destroy(dev, i, rx_done);
969 et_dma_mbuf_destroy(device_t dev, int tx_done, const int rx_done[])
971 struct et_softc *sc = device_get_softc(dev);
972 struct et_txbuf_data *tbd = &sc->sc_tx_data;
976 * Destroy DMA tag and maps for RX mbufs
978 if (sc->sc_rxbuf_dtag) {
979 for (i = 0; i < ET_RX_NRING; ++i) {
980 struct et_rxbuf_data *rbd = &sc->sc_rx_data[i];
983 for (j = 0; j < rx_done[i]; ++j) {
984 struct et_rxbuf *rb = &rbd->rbd_buf[j];
986 KASSERT(rb->rb_mbuf == NULL,
987 ("RX mbuf in %d RX ring is "
988 "not freed yet", i));
989 bus_dmamap_destroy(sc->sc_rxbuf_dtag,
993 bus_dmamap_destroy(sc->sc_rxbuf_dtag, sc->sc_rxbuf_tmp_dmap);
994 bus_dma_tag_destroy(sc->sc_rxbuf_dtag);
995 sc->sc_rxbuf_dtag = NULL;
999 * Destroy DMA tag and maps for TX mbufs
1001 if (sc->sc_txbuf_dtag) {
1002 for (i = 0; i < tx_done; ++i) {
1003 struct et_txbuf *tb = &tbd->tbd_buf[i];
1005 KASSERT(tb->tb_mbuf == NULL,
1006 ("TX mbuf is not freed yet"));
1007 bus_dmamap_destroy(sc->sc_txbuf_dtag, tb->tb_dmap);
1009 bus_dma_tag_destroy(sc->sc_txbuf_dtag);
1010 sc->sc_txbuf_dtag = NULL;
1015 et_dma_mem_destroy(bus_dma_tag_t dtag, void *addr, bus_dmamap_t dmap)
1018 bus_dmamap_unload(dtag, dmap);
1019 bus_dmamem_free(dtag, addr, dmap);
1020 bus_dma_tag_destroy(dtag);
1025 et_chip_attach(struct et_softc *sc)
1030 * Perform minimal initialization
1033 /* Disable loopback */
1034 CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1037 CSR_WRITE_4(sc, ET_MAC_CFG1,
1038 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1039 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1040 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1043 * Setup half duplex mode
1045 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
1046 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
1047 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) |
1048 ET_MAC_HDX_EXC_DEFER;
1049 CSR_WRITE_4(sc, ET_MAC_HDX, val);
1051 /* Clear MAC control */
1052 CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1055 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1057 /* Bring MAC out of reset state */
1058 CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1060 /* Enable memory controllers */
1061 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1067 struct et_softc *sc = xsc;
1068 struct ifnet *ifp = &sc->arpcom.ac_if;
1071 ASSERT_SERIALIZED(ifp->if_serializer);
1073 if ((ifp->if_flags & IFF_RUNNING) == 0)
1076 et_disable_intrs(sc);
1078 intrs = CSR_READ_4(sc, ET_INTR_STATUS);
1080 if (intrs == 0) /* Not interested */
1083 if (intrs & ET_INTR_RXEOF)
1085 if (intrs & (ET_INTR_TXEOF | ET_INTR_TIMER))
1087 if (intrs & ET_INTR_TIMER)
1088 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1090 et_enable_intrs(sc, ET_INTRS);
1096 struct et_softc *sc = xsc;
1097 struct ifnet *ifp = &sc->arpcom.ac_if;
1098 const struct et_bsize *arr;
1101 ASSERT_SERIALIZED(ifp->if_serializer);
1105 arr = ET_FRAMELEN(ifp->if_mtu) < MCLBYTES ?
1106 et_bufsize_std : et_bufsize_jumbo;
1107 for (i = 0; i < ET_RX_NRING; ++i) {
1108 sc->sc_rx_data[i].rbd_bufsize = arr[i].bufsize;
1109 sc->sc_rx_data[i].rbd_newbuf = arr[i].newbuf;
1110 sc->sc_rx_data[i].rbd_jumbo = arr[i].jumbo;
1113 error = et_init_tx_ring(sc);
1117 error = et_init_rx_ring(sc);
1121 error = et_chip_init(sc);
1125 error = et_enable_txrx(sc, 1);
1129 et_enable_intrs(sc, ET_INTRS);
1131 callout_reset(&sc->sc_tick, hz, et_tick, sc);
1133 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1135 ifp->if_flags |= IFF_RUNNING;
1136 ifq_clr_oactive(&ifp->if_snd);
1143 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1145 struct et_softc *sc = ifp->if_softc;
1146 struct mii_data *mii = device_get_softc(sc->sc_miibus);
1147 struct ifreq *ifr = (struct ifreq *)data;
1148 int error = 0, max_framelen;
1150 ASSERT_SERIALIZED(ifp->if_serializer);
1154 if (ifp->if_flags & IFF_UP) {
1155 if (ifp->if_flags & IFF_RUNNING) {
1156 if ((ifp->if_flags ^ sc->sc_if_flags) &
1157 (IFF_ALLMULTI | IFF_PROMISC))
1163 if (ifp->if_flags & IFF_RUNNING)
1166 sc->sc_if_flags = ifp->if_flags;
1171 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1176 if (ifp->if_flags & IFF_RUNNING)
1181 if (sc->sc_flags & ET_FLAG_JUMBO)
1182 max_framelen = ET_JUMBO_FRAMELEN;
1184 max_framelen = MCLBYTES - 1;
1186 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) {
1191 ifp->if_mtu = ifr->ifr_mtu;
1192 if (ifp->if_flags & IFF_RUNNING)
1197 error = ether_ioctl(ifp, cmd, data);
1204 et_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1206 struct et_softc *sc = ifp->if_softc;
1207 struct et_txbuf_data *tbd = &sc->sc_tx_data;
1210 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1211 ASSERT_SERIALIZED(ifp->if_serializer);
1213 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) {
1214 ifq_purge(&ifp->if_snd);
1218 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1227 if ((tbd->tbd_used + ET_NSEG_SPARE) > ET_TX_NDESC) {
1229 ifq_set_oactive(&ifp->if_snd);
1238 m = ifq_dequeue(&ifp->if_snd);
1242 error = et_encap(sc, &m);
1244 IFNET_STAT_INC(ifp, oerrors, 1);
1245 KKASSERT(m == NULL);
1247 if (error == EFBIG) {
1249 * Excessive fragmented packets
1252 ifq_set_oactive(&ifp->if_snd);
1272 et_watchdog(struct ifnet *ifp)
1274 ASSERT_SERIALIZED(ifp->if_serializer);
1276 if_printf(ifp, "watchdog timed out\n");
1278 ifp->if_init(ifp->if_softc);
1283 et_stop_rxdma(struct et_softc *sc)
1285 CSR_WRITE_4(sc, ET_RXDMA_CTRL,
1286 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE);
1289 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {
1290 if_printf(&sc->arpcom.ac_if, "can't stop RX DMA engine\n");
1297 et_stop_txdma(struct et_softc *sc)
1299 CSR_WRITE_4(sc, ET_TXDMA_CTRL,
1300 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT);
1305 et_free_tx_ring(struct et_softc *sc)
1307 struct et_txbuf_data *tbd = &sc->sc_tx_data;
1308 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1311 for (i = 0; i < ET_TX_NDESC; ++i) {
1312 struct et_txbuf *tb = &tbd->tbd_buf[i];
1314 if (tb->tb_mbuf != NULL) {
1315 bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap);
1316 m_freem(tb->tb_mbuf);
1320 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1324 et_free_rx_ring(struct et_softc *sc)
1328 for (n = 0; n < ET_RX_NRING; ++n) {
1329 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1330 struct et_rxdesc_ring *rx_ring = &sc->sc_rx_ring[n];
1333 for (i = 0; i < ET_RX_NDESC; ++i) {
1334 struct et_rxbuf *rb = &rbd->rbd_buf[i];
1336 if (rb->rb_mbuf != NULL) {
1337 if (!rbd->rbd_jumbo) {
1338 bus_dmamap_unload(sc->sc_rxbuf_dtag,
1341 m_freem(rb->rb_mbuf);
1345 bzero(rx_ring->rr_desc, ET_RX_RING_SIZE);
1350 et_setmulti(struct et_softc *sc)
1352 struct ifnet *ifp = &sc->arpcom.ac_if;
1353 uint32_t hash[4] = { 0, 0, 0, 0 };
1354 uint32_t rxmac_ctrl, pktfilt;
1355 struct ifmultiaddr *ifma;
1358 pktfilt = CSR_READ_4(sc, ET_PKTFILT);
1359 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL);
1361 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST);
1362 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1363 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT;
1368 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1371 if (ifma->ifma_addr->sa_family != AF_LINK)
1374 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
1375 ifma->ifma_addr), ETHER_ADDR_LEN);
1376 h = (h & 0x3f800000) >> 23;
1379 if (h >= 32 && h < 64) {
1382 } else if (h >= 64 && h < 96) {
1385 } else if (h >= 96) {
1394 for (i = 0; i < 4; ++i)
1395 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]);
1398 pktfilt |= ET_PKTFILT_MCAST;
1399 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT;
1401 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt);
1402 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl);
1406 et_chip_init(struct et_softc *sc)
1408 struct ifnet *ifp = &sc->arpcom.ac_if;
1410 int error, frame_len, rxmem_size;
1413 * Split 16Kbytes internal memory between TX and RX
1414 * according to frame length.
1416 frame_len = ET_FRAMELEN(ifp->if_mtu);
1417 if (frame_len < 2048) {
1418 rxmem_size = ET_MEM_RXSIZE_DEFAULT;
1419 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) {
1420 rxmem_size = ET_MEM_SIZE / 2;
1422 rxmem_size = ET_MEM_SIZE -
1423 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT);
1425 rxq_end = ET_QUEUE_ADDR(rxmem_size);
1427 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START);
1428 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end);
1429 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1);
1430 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END);
1433 CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1435 /* Clear MSI configure */
1436 CSR_WRITE_4(sc, ET_MSI_CFG, 0);
1439 CSR_WRITE_4(sc, ET_TIMER, 0);
1441 /* Initialize MAC */
1444 /* Enable memory controllers */
1445 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1447 /* Initialize RX MAC */
1450 /* Initialize TX MAC */
1453 /* Initialize RX DMA engine */
1454 error = et_init_rxdma(sc);
1458 /* Initialize TX DMA engine */
1459 error = et_init_txdma(sc);
1467 et_init_tx_ring(struct et_softc *sc)
1469 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1470 struct et_txstatus_data *txsd = &sc->sc_tx_status;
1471 struct et_txbuf_data *tbd = &sc->sc_tx_data;
1473 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE);
1475 tbd->tbd_start_index = 0;
1476 tbd->tbd_start_wrap = 0;
1479 bzero(txsd->txsd_status, sizeof(uint32_t));
1485 et_init_rx_ring(struct et_softc *sc)
1487 struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1488 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1491 for (n = 0; n < ET_RX_NRING; ++n) {
1492 struct et_rxbuf_data *rbd = &sc->sc_rx_data[n];
1495 for (i = 0; i < ET_RX_NDESC; ++i) {
1496 error = rbd->rbd_newbuf(rbd, i, 1);
1498 if_printf(&sc->arpcom.ac_if, "%d ring %d buf, "
1499 "newbuf failed: %d\n", n, i, error);
1505 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus));
1506 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE);
1512 et_init_rxdma(struct et_softc *sc)
1514 struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1515 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1516 struct et_rxdesc_ring *rx_ring;
1519 error = et_stop_rxdma(sc);
1521 if_printf(&sc->arpcom.ac_if, "can't init RX DMA engine\n");
1528 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr));
1529 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr));
1532 * Install RX stat ring
1534 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr));
1535 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr));
1536 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1);
1537 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0);
1538 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1);
1540 /* Match ET_RXSTAT_POS */
1541 rxst_ring->rsr_index = 0;
1542 rxst_ring->rsr_wrap = 0;
1545 * Install the 2nd RX descriptor ring
1547 rx_ring = &sc->sc_rx_ring[1];
1548 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1549 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1550 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1);
1551 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP);
1552 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1554 /* Match ET_RX_RING1_POS */
1555 rx_ring->rr_index = 0;
1556 rx_ring->rr_wrap = 1;
1559 * Install the 1st RX descriptor ring
1561 rx_ring = &sc->sc_rx_ring[0];
1562 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1563 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1564 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1);
1565 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP);
1566 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1568 /* Match ET_RX_RING0_POS */
1569 rx_ring->rr_index = 0;
1570 rx_ring->rr_wrap = 1;
1573 * RX intr moderation
1575 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts);
1576 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay);
1582 et_init_txdma(struct et_softc *sc)
1584 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1585 struct et_txstatus_data *txsd = &sc->sc_tx_status;
1588 error = et_stop_txdma(sc);
1590 if_printf(&sc->arpcom.ac_if, "can't init TX DMA engine\n");
1595 * Install TX descriptor ring
1597 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr));
1598 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr));
1599 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1);
1604 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr));
1605 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr));
1607 CSR_WRITE_4(sc, ET_TX_READY_POS, 0);
1609 /* Match ET_TX_READY_POS */
1610 tx_ring->tr_ready_index = 0;
1611 tx_ring->tr_ready_wrap = 0;
1617 et_init_mac(struct et_softc *sc)
1619 struct ifnet *ifp = &sc->arpcom.ac_if;
1620 const uint8_t *eaddr = IF_LLADDR(ifp);
1624 CSR_WRITE_4(sc, ET_MAC_CFG1,
1625 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC |
1626 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC |
1627 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST);
1630 * Setup inter packet gap
1632 val = __SHIFTIN(56, ET_IPG_NONB2B_1) |
1633 __SHIFTIN(88, ET_IPG_NONB2B_2) |
1634 __SHIFTIN(80, ET_IPG_MINIFG) |
1635 __SHIFTIN(96, ET_IPG_B2B);
1636 CSR_WRITE_4(sc, ET_IPG, val);
1639 * Setup half duplex mode
1641 val = __SHIFTIN(10, ET_MAC_HDX_ALT_BEB_TRUNC) |
1642 __SHIFTIN(15, ET_MAC_HDX_REXMIT_MAX) |
1643 __SHIFTIN(55, ET_MAC_HDX_COLLWIN) |
1644 ET_MAC_HDX_EXC_DEFER;
1645 CSR_WRITE_4(sc, ET_MAC_HDX, val);
1647 /* Clear MAC control */
1648 CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1651 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1656 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24);
1657 CSR_WRITE_4(sc, ET_MAC_ADDR1, val);
1658 val = (eaddr[0] << 16) | (eaddr[1] << 24);
1659 CSR_WRITE_4(sc, ET_MAC_ADDR2, val);
1661 /* Set max frame length */
1662 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu));
1664 /* Bring MAC out of reset state */
1665 CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1669 et_init_rxmac(struct et_softc *sc)
1671 struct ifnet *ifp = &sc->arpcom.ac_if;
1672 const uint8_t *eaddr = IF_LLADDR(ifp);
1676 /* Disable RX MAC and WOL */
1677 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE);
1680 * Clear all WOL related registers
1682 for (i = 0; i < 3; ++i)
1683 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0);
1684 for (i = 0; i < 20; ++i)
1685 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0);
1688 * Set WOL source address. XXX is this necessary?
1690 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5];
1691 CSR_WRITE_4(sc, ET_WOL_SA_LO, val);
1692 val = (eaddr[0] << 8) | eaddr[1];
1693 CSR_WRITE_4(sc, ET_WOL_SA_HI, val);
1695 /* Clear packet filters */
1696 CSR_WRITE_4(sc, ET_PKTFILT, 0);
1698 /* No ucast filtering */
1699 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0);
1700 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0);
1701 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0);
1703 if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) {
1705 * In order to transmit jumbo packets greater than
1706 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between
1707 * RX MAC and RX DMA needs to be reduced in size to
1708 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In
1709 * order to implement this, we must use "cut through"
1710 * mode in the RX MAC, which chops packets down into
1711 * segments. In this case we selected 256 bytes,
1712 * since this is the size of the PCI-Express TLP's
1713 * that the ET1310 uses.
1715 val = __SHIFTIN(ET_RXMAC_SEGSZ(256), ET_RXMAC_MC_SEGSZ_MAX) |
1716 ET_RXMAC_MC_SEGSZ_ENABLE;
1720 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val);
1722 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0);
1724 /* Initialize RX MAC management register */
1725 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0);
1727 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0);
1729 CSR_WRITE_4(sc, ET_RXMAC_MGT,
1730 ET_RXMAC_MGT_PASS_ECRC |
1731 ET_RXMAC_MGT_PASS_ELEN |
1732 ET_RXMAC_MGT_PASS_ETRUNC |
1733 ET_RXMAC_MGT_CHECK_PKT);
1736 * Configure runt filtering (may not work on certain chip generation)
1738 val = __SHIFTIN(ETHER_MIN_LEN, ET_PKTFILT_MINLEN) | ET_PKTFILT_FRAG;
1739 CSR_WRITE_4(sc, ET_PKTFILT, val);
1741 /* Enable RX MAC but leave WOL disabled */
1742 CSR_WRITE_4(sc, ET_RXMAC_CTRL,
1743 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE);
1746 * Setup multicast hash and allmulti/promisc mode
1752 et_init_txmac(struct et_softc *sc)
1754 /* Disable TX MAC and FC(?) */
1755 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE);
1757 /* No flow control yet */
1758 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0);
1760 /* Enable TX MAC but leave FC(?) diabled */
1761 CSR_WRITE_4(sc, ET_TXMAC_CTRL,
1762 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE);
1766 et_start_rxdma(struct et_softc *sc)
1770 val |= __SHIFTIN(sc->sc_rx_data[0].rbd_bufsize,
1771 ET_RXDMA_CTRL_RING0_SIZE) |
1772 ET_RXDMA_CTRL_RING0_ENABLE;
1773 val |= __SHIFTIN(sc->sc_rx_data[1].rbd_bufsize,
1774 ET_RXDMA_CTRL_RING1_SIZE) |
1775 ET_RXDMA_CTRL_RING1_ENABLE;
1777 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val);
1781 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) {
1782 if_printf(&sc->arpcom.ac_if, "can't start RX DMA engine\n");
1789 et_start_txdma(struct et_softc *sc)
1791 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT);
1796 et_enable_txrx(struct et_softc *sc, int media_upd)
1798 struct ifnet *ifp = &sc->arpcom.ac_if;
1802 val = CSR_READ_4(sc, ET_MAC_CFG1);
1803 val |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN;
1804 val &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW |
1805 ET_MAC_CFG1_LOOPBACK);
1806 CSR_WRITE_4(sc, ET_MAC_CFG1, val);
1809 et_ifmedia_upd(ifp);
1815 for (i = 0; i < NRETRY; ++i) {
1816 val = CSR_READ_4(sc, ET_MAC_CFG1);
1817 if ((val & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) ==
1818 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN))
1824 if_printf(ifp, "can't enable RX/TX\n");
1827 sc->sc_flags |= ET_FLAG_TXRX_ENABLED;
1832 * Start TX/RX DMA engine
1834 error = et_start_rxdma(sc);
1838 error = et_start_txdma(sc);
1846 et_rxeof(struct et_softc *sc)
1848 struct ifnet *ifp = &sc->arpcom.ac_if;
1849 struct et_rxstatus_data *rxsd = &sc->sc_rx_status;
1850 struct et_rxstat_ring *rxst_ring = &sc->sc_rxstat_ring;
1851 uint32_t rxs_stat_ring;
1852 int rxst_wrap, rxst_index;
1854 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
1857 rxs_stat_ring = rxsd->rxsd_status->rxs_stat_ring;
1858 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0;
1859 rxst_index = __SHIFTOUT(rxs_stat_ring, ET_RXS_STATRING_INDEX);
1861 while (rxst_index != rxst_ring->rsr_index ||
1862 rxst_wrap != rxst_ring->rsr_wrap) {
1863 struct et_rxbuf_data *rbd;
1864 struct et_rxdesc_ring *rx_ring;
1865 struct et_rxstat *st;
1867 int buflen, buf_idx, ring_idx;
1868 uint32_t rxstat_pos, rxring_pos;
1870 KKASSERT(rxst_ring->rsr_index < ET_RX_NSTAT);
1871 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index];
1873 buflen = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_LEN);
1874 buf_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_BUFIDX);
1875 ring_idx = __SHIFTOUT(st->rxst_info2, ET_RXST_INFO2_RINGIDX);
1877 if (++rxst_ring->rsr_index == ET_RX_NSTAT) {
1878 rxst_ring->rsr_index = 0;
1879 rxst_ring->rsr_wrap ^= 1;
1881 rxstat_pos = __SHIFTIN(rxst_ring->rsr_index,
1882 ET_RXSTAT_POS_INDEX);
1883 if (rxst_ring->rsr_wrap)
1884 rxstat_pos |= ET_RXSTAT_POS_WRAP;
1885 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos);
1887 if (ring_idx >= ET_RX_NRING) {
1888 IFNET_STAT_INC(ifp, ierrors, 1);
1889 if_printf(ifp, "invalid ring index %d\n", ring_idx);
1892 if (buf_idx >= ET_RX_NDESC) {
1893 IFNET_STAT_INC(ifp, ierrors, 1);
1894 if_printf(ifp, "invalid buf index %d\n", buf_idx);
1898 rbd = &sc->sc_rx_data[ring_idx];
1899 m = rbd->rbd_buf[buf_idx].rb_mbuf;
1901 if (rbd->rbd_newbuf(rbd, buf_idx, 0) == 0) {
1902 if (buflen < ETHER_CRC_LEN) {
1904 IFNET_STAT_INC(ifp, ierrors, 1);
1906 m->m_pkthdr.len = m->m_len = buflen;
1907 m->m_pkthdr.rcvif = ifp;
1909 m_adj(m, -ETHER_CRC_LEN);
1911 IFNET_STAT_INC(ifp, ipackets, 1);
1912 ifp->if_input(ifp, m, NULL, -1);
1915 IFNET_STAT_INC(ifp, ierrors, 1);
1917 m = NULL; /* Catch invalid reference */
1919 rx_ring = &sc->sc_rx_ring[ring_idx];
1921 if (buf_idx != rx_ring->rr_index) {
1922 if_printf(ifp, "WARNING!! ring %d, "
1923 "buf_idx %d, rr_idx %d\n",
1924 ring_idx, buf_idx, rx_ring->rr_index);
1927 KKASSERT(rx_ring->rr_index < ET_RX_NDESC);
1928 if (++rx_ring->rr_index == ET_RX_NDESC) {
1929 rx_ring->rr_index = 0;
1930 rx_ring->rr_wrap ^= 1;
1932 rxring_pos = __SHIFTIN(rx_ring->rr_index, ET_RX_RING_POS_INDEX);
1933 if (rx_ring->rr_wrap)
1934 rxring_pos |= ET_RX_RING_POS_WRAP;
1935 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos);
1940 et_encap(struct et_softc *sc, struct mbuf **m0)
1942 bus_dma_segment_t segs[ET_NSEG_MAX];
1943 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
1944 struct et_txbuf_data *tbd = &sc->sc_tx_data;
1945 struct et_txdesc *td;
1947 int error, maxsegs, nsegs, first_idx, last_idx, i;
1948 uint32_t tx_ready_pos, last_td_ctrl2;
1950 maxsegs = ET_TX_NDESC - tbd->tbd_used;
1951 if (maxsegs > ET_NSEG_MAX)
1952 maxsegs = ET_NSEG_MAX;
1953 KASSERT(maxsegs >= ET_NSEG_SPARE,
1954 ("not enough spare TX desc (%d)", maxsegs));
1956 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC);
1957 first_idx = tx_ring->tr_ready_index;
1958 map = tbd->tbd_buf[first_idx].tb_dmap;
1960 error = bus_dmamap_load_mbuf_defrag(sc->sc_txbuf_dtag, map, m0,
1961 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1964 bus_dmamap_sync(sc->sc_txbuf_dtag, map, BUS_DMASYNC_PREWRITE);
1966 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG;
1968 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) {
1969 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs;
1970 last_td_ctrl2 |= ET_TDCTRL2_INTR;
1974 for (i = 0; i < nsegs; ++i) {
1977 idx = (first_idx + i) % ET_TX_NDESC;
1978 td = &tx_ring->tr_desc[idx];
1979 td->td_addr_hi = ET_ADDR_HI(segs[i].ds_addr);
1980 td->td_addr_lo = ET_ADDR_LO(segs[i].ds_addr);
1981 td->td_ctrl1 = __SHIFTIN(segs[i].ds_len, ET_TDCTRL1_LEN);
1983 if (i == nsegs - 1) { /* Last frag */
1984 td->td_ctrl2 = last_td_ctrl2;
1988 KKASSERT(tx_ring->tr_ready_index < ET_TX_NDESC);
1989 if (++tx_ring->tr_ready_index == ET_TX_NDESC) {
1990 tx_ring->tr_ready_index = 0;
1991 tx_ring->tr_ready_wrap ^= 1;
1994 td = &tx_ring->tr_desc[first_idx];
1995 td->td_ctrl2 |= ET_TDCTRL2_FIRST_FRAG; /* First frag */
1997 KKASSERT(last_idx >= 0);
1998 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap;
1999 tbd->tbd_buf[last_idx].tb_dmap = map;
2000 tbd->tbd_buf[last_idx].tb_mbuf = *m0;
2002 tbd->tbd_used += nsegs;
2003 KKASSERT(tbd->tbd_used <= ET_TX_NDESC);
2005 tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index,
2006 ET_TX_READY_POS_INDEX);
2007 if (tx_ring->tr_ready_wrap)
2008 tx_ready_pos |= ET_TX_READY_POS_WRAP;
2009 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos);
2021 et_txeof(struct et_softc *sc, int start)
2023 struct ifnet *ifp = &sc->arpcom.ac_if;
2024 struct et_txdesc_ring *tx_ring = &sc->sc_tx_ring;
2025 struct et_txbuf_data *tbd = &sc->sc_tx_data;
2029 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0)
2032 if (tbd->tbd_used == 0)
2035 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);
2036 end = __SHIFTOUT(tx_done, ET_TX_DONE_POS_INDEX);
2037 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0;
2039 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) {
2040 struct et_txbuf *tb;
2042 KKASSERT(tbd->tbd_start_index < ET_TX_NDESC);
2043 tb = &tbd->tbd_buf[tbd->tbd_start_index];
2045 bzero(&tx_ring->tr_desc[tbd->tbd_start_index],
2046 sizeof(struct et_txdesc));
2048 if (tb->tb_mbuf != NULL) {
2049 bus_dmamap_unload(sc->sc_txbuf_dtag, tb->tb_dmap);
2050 m_freem(tb->tb_mbuf);
2052 IFNET_STAT_INC(ifp, opackets, 1);
2055 if (++tbd->tbd_start_index == ET_TX_NDESC) {
2056 tbd->tbd_start_index = 0;
2057 tbd->tbd_start_wrap ^= 1;
2060 KKASSERT(tbd->tbd_used > 0);
2064 if (tbd->tbd_used == 0)
2066 if (tbd->tbd_used + ET_NSEG_SPARE <= ET_TX_NDESC)
2067 ifq_clr_oactive(&ifp->if_snd);
2076 struct et_softc *sc = xsc;
2077 struct ifnet *ifp = &sc->arpcom.ac_if;
2078 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2080 lwkt_serialize_enter(ifp->if_serializer);
2083 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0 &&
2084 (mii->mii_media_status & IFM_ACTIVE) &&
2085 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2086 if_printf(ifp, "Link up, enable TX/RX\n");
2087 if (et_enable_txrx(sc, 0) == 0)
2090 callout_reset(&sc->sc_tick, hz, et_tick, sc);
2092 lwkt_serialize_exit(ifp->if_serializer);
2096 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx, int init)
2098 return et_newbuf(rbd, buf_idx, init, MCLBYTES);
2102 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx, int init)
2104 return et_newbuf(rbd, buf_idx, init, MHLEN);
2108 et_newbuf(struct et_rxbuf_data *rbd, int buf_idx, int init, int len0)
2110 struct et_softc *sc = rbd->rbd_softc;
2111 struct et_rxbuf *rb;
2113 bus_dma_segment_t seg;
2115 int error, len, nseg;
2117 KASSERT(!rbd->rbd_jumbo, ("calling %s with jumbo ring", __func__));
2119 KKASSERT(buf_idx < ET_RX_NDESC);
2120 rb = &rbd->rbd_buf[buf_idx];
2122 m = m_getl(len0, init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR, &len);
2127 if_printf(&sc->arpcom.ac_if,
2128 "m_getl failed, size %d\n", len0);
2134 m->m_len = m->m_pkthdr.len = len;
2137 * Try load RX mbuf into temporary DMA tag
2139 error = bus_dmamap_load_mbuf_segment(sc->sc_rxbuf_dtag,
2140 sc->sc_rxbuf_tmp_dmap, m, &seg, 1, &nseg,
2145 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2153 bus_dmamap_sync(sc->sc_rxbuf_dtag, rb->rb_dmap,
2154 BUS_DMASYNC_POSTREAD);
2155 bus_dmamap_unload(sc->sc_rxbuf_dtag, rb->rb_dmap);
2158 rb->rb_paddr = seg.ds_addr;
2161 * Swap RX buf's DMA map with the loaded temporary one
2164 rb->rb_dmap = sc->sc_rxbuf_tmp_dmap;
2165 sc->sc_rxbuf_tmp_dmap = dmap;
2169 et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr);
2174 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS)
2176 struct et_softc *sc = arg1;
2177 struct ifnet *ifp = &sc->arpcom.ac_if;
2180 lwkt_serialize_enter(ifp->if_serializer);
2182 v = sc->sc_rx_intr_npkts;
2183 error = sysctl_handle_int(oidp, &v, 0, req);
2184 if (error || req->newptr == NULL)
2191 if (sc->sc_rx_intr_npkts != v) {
2192 if (ifp->if_flags & IFF_RUNNING)
2193 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v);
2194 sc->sc_rx_intr_npkts = v;
2197 lwkt_serialize_exit(ifp->if_serializer);
2202 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS)
2204 struct et_softc *sc = arg1;
2205 struct ifnet *ifp = &sc->arpcom.ac_if;
2208 lwkt_serialize_enter(ifp->if_serializer);
2210 v = sc->sc_rx_intr_delay;
2211 error = sysctl_handle_int(oidp, &v, 0, req);
2212 if (error || req->newptr == NULL)
2219 if (sc->sc_rx_intr_delay != v) {
2220 if (ifp->if_flags & IFF_RUNNING)
2221 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v);
2222 sc->sc_rx_intr_delay = v;
2225 lwkt_serialize_exit(ifp->if_serializer);
2230 et_setmedia(struct et_softc *sc)
2232 struct mii_data *mii = device_get_softc(sc->sc_miibus);
2233 uint32_t cfg2, ctrl;
2235 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
2236 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII |
2237 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM);
2238 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC |
2239 __SHIFTIN(7, ET_MAC_CFG2_PREAMBLE_LEN);
2241 ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
2242 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII);
2244 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
2245 cfg2 |= ET_MAC_CFG2_MODE_GMII;
2247 cfg2 |= ET_MAC_CFG2_MODE_MII;
2248 ctrl |= ET_MAC_CTRL_MODE_MII;
2251 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
2252 cfg2 |= ET_MAC_CFG2_FDX;
2254 ctrl |= ET_MAC_CTRL_GHDX;
2256 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
2257 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
2261 et_jumbo_mem_alloc(device_t dev)
2263 struct et_softc *sc = device_get_softc(dev);
2264 struct et_jumbo_data *jd = &sc->sc_jumbo_data;
2269 jd->jd_buf = bus_dmamem_coherent_any(sc->sc_dtag,
2270 ET_JUMBO_ALIGN, ET_JUMBO_MEM_SIZE, BUS_DMA_WAITOK,
2271 &jd->jd_dtag, &jd->jd_dmap, &paddr);
2272 if (jd->jd_buf == NULL) {
2273 device_printf(dev, "can't create jumbo DMA stuffs\n");
2277 jd->jd_slots = kmalloc(sizeof(*jd->jd_slots) * ET_JSLOTS, M_DEVBUF,
2279 lwkt_serialize_init(&jd->jd_serializer);
2280 SLIST_INIT(&jd->jd_free_slots);
2283 for (i = 0; i < ET_JSLOTS; ++i) {
2284 struct et_jslot *jslot = &jd->jd_slots[i];
2286 jslot->jslot_data = jd;
2287 jslot->jslot_buf = buf;
2288 jslot->jslot_paddr = paddr;
2289 jslot->jslot_inuse = 0;
2290 jslot->jslot_index = i;
2291 SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot, jslot_link);
2300 et_jumbo_mem_free(device_t dev)
2302 struct et_softc *sc = device_get_softc(dev);
2303 struct et_jumbo_data *jd = &sc->sc_jumbo_data;
2305 KKASSERT(sc->sc_flags & ET_FLAG_JUMBO);
2307 kfree(jd->jd_slots, M_DEVBUF);
2308 et_dma_mem_destroy(jd->jd_dtag, jd->jd_buf, jd->jd_dmap);
2311 static struct et_jslot *
2312 et_jalloc(struct et_jumbo_data *jd)
2314 struct et_jslot *jslot;
2316 lwkt_serialize_enter(&jd->jd_serializer);
2318 jslot = SLIST_FIRST(&jd->jd_free_slots);
2320 SLIST_REMOVE_HEAD(&jd->jd_free_slots, jslot_link);
2321 jslot->jslot_inuse = 1;
2324 lwkt_serialize_exit(&jd->jd_serializer);
2329 et_jfree(void *xjslot)
2331 struct et_jslot *jslot = xjslot;
2332 struct et_jumbo_data *jd = jslot->jslot_data;
2334 if (&jd->jd_slots[jslot->jslot_index] != jslot) {
2335 panic("%s wrong jslot!?", __func__);
2336 } else if (jslot->jslot_inuse == 0) {
2337 panic("%s jslot already freed", __func__);
2339 lwkt_serialize_enter(&jd->jd_serializer);
2341 atomic_subtract_int(&jslot->jslot_inuse, 1);
2342 if (jslot->jslot_inuse == 0) {
2343 SLIST_INSERT_HEAD(&jd->jd_free_slots, jslot,
2347 lwkt_serialize_exit(&jd->jd_serializer);
2352 et_jref(void *xjslot)
2354 struct et_jslot *jslot = xjslot;
2355 struct et_jumbo_data *jd = jslot->jslot_data;
2357 if (&jd->jd_slots[jslot->jslot_index] != jslot)
2358 panic("%s wrong jslot!?", __func__);
2359 else if (jslot->jslot_inuse == 0)
2360 panic("%s jslot already freed", __func__);
2362 atomic_add_int(&jslot->jslot_inuse, 1);
2366 et_newbuf_jumbo(struct et_rxbuf_data *rbd, int buf_idx, int init)
2368 struct et_softc *sc = rbd->rbd_softc;
2369 struct et_rxbuf *rb;
2371 struct et_jslot *jslot;
2374 KASSERT(rbd->rbd_jumbo, ("calling %s with non-jumbo ring", __func__));
2376 KKASSERT(buf_idx < ET_RX_NDESC);
2377 rb = &rbd->rbd_buf[buf_idx];
2381 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
2384 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
2391 jslot = et_jalloc(&sc->sc_jumbo_data);
2392 if (jslot == NULL) {
2396 if_printf(&sc->arpcom.ac_if,
2397 "jslot allocation failed\n");
2404 m->m_ext.ext_arg = jslot;
2405 m->m_ext.ext_buf = jslot->jslot_buf;
2406 m->m_ext.ext_free = et_jfree;
2407 m->m_ext.ext_ref = et_jref;
2408 m->m_ext.ext_size = ET_JUMBO_FRAMELEN;
2409 m->m_flags |= M_EXT;
2410 m->m_data = m->m_ext.ext_buf;
2411 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
2414 rb->rb_paddr = jslot->jslot_paddr;
2418 et_setup_rxdesc(rbd, buf_idx, rb->rb_paddr);
2423 et_setup_rxdesc(struct et_rxbuf_data *rbd, int buf_idx, bus_addr_t paddr)
2425 struct et_rxdesc_ring *rx_ring = rbd->rbd_ring;
2426 struct et_rxdesc *desc;
2428 KKASSERT(buf_idx < ET_RX_NDESC);
2429 desc = &rx_ring->rr_desc[buf_idx];
2431 desc->rd_addr_hi = ET_ADDR_HI(paddr);
2432 desc->rd_addr_lo = ET_ADDR_LO(paddr);
2433 desc->rd_ctrl = __SHIFTIN(buf_idx, ET_RDCTRL_BUFIDX);